SPC56EL60xx/SPC56xL70xx device exception handling
Contents
1. vera wanga TR E RE RE ERE 9 3 SPC56EL60xx SPC56xL70xx exception cases 10 3 1 Flash 2b ECO Sfor sus eua sux uer KR REOR e EE 10 3 1 1 Cause of the exception llli 10 3 1 2 Machine check exception status 11 3 1 3 User exception handler 11 3 1 4 Error SOWING susce ME ERR du ua rubus eel ae Oates 11 Revision history esca a osa c dio rab in PR de Qoa oa ec daa andi a RU 12 2 13 DoclD025333 Rev 1 Ly 4367 List of tables List of tables Table 1 Machine check interrupt causes lille 5 Table 2 Machine check register 5 Table 3 Machine check CaUSES 1 2 0 ee tees 6 Table 4 SPC56EL60xx SPC56xL70xx exception causes 10 Table 5 Flash 2b ECC machine check exception 11 Table 6 Document revision history 0 0 12 Ly DoclD025333 Rev 1 3 13 List of figures AN4367 List of figures Figure 1 Machine check exception flow lilseeleeee RII 7 Figure 2 Modification of MCSRRO register content liliis 8 Figure 3 Machine check exception user handler flow 9 Figure4 Flash 2b ECCerror 2 0 tt eet eee ae 10 4 13 DoclD025333 Rev 12. v AN4367 JJ VNDE Application note SPC56EL60xx SPC56xL70xx device exception handling Introduction This document provides overview of SPC56EL60xx SPC56xL70xx exception handling with main focus on different kind of exception that the application code can face during the runtime like Flash 2b ECC error RAM 2b ECC error MPU protection violation AIPS access protection violation and others It starts simple overview of Machine check interrupt highlighting important things from application perspective To get detailed view and to implement low level machine check interrupt handler it is necessary to use Z4 Core User Manual which describes all the details about the Core exception and interrupts The following part lists the SPC56EL60xx SPC56xL70xx exceptions describes the reason of the exception how to find it and what possibilities exists to remove the fault October 2013 DoclD025333 Rev 1 1 13 www st com Contents AN4367 Contents 1 24 Core exception overview 5 1 1 Machine check interrupt IVOR1 00 00 cee eee 5 1 1 1 Machine check registers 0c ees 5 2 Machine check handler 7 2 1 bow level handler isses sea eb RR RE SERO EX ARE 7 2 1 1 Siri n 7 2 1 2 Final phase a O A piene Spe uu waded Yates 8 2 1 3 Modification of the MCSRRO register 8 2 2 User handler iius
3. Start phase First steps when machine check exception occurs are done by the hardware Core which stores content of the MSR register and address of the current instruction pointer if it is possible precise exception DoclD025333 Rev 1 7 13 Machine check handler AN4367 8 13 Low level driver immediately starts processing after It executes several steps like machine check status register saving context of the interrupted process saving and other This part should store some additional information too as they will be used by higher layer user handler to analyze the root cause of the exception later Detailed description of the machine check resources their meaning and proper handling in case of interrupt is described in the Z4 Core User Manual documentation Low level handler shall follow rules and recommendation described there Final phase Here the handler should restore the saved context of the interrupted process and return with the merfi instruction Before rfmci instruction is executed which fills instruction pointer with MCSRRO content and MSR register with MCSRR1 content MCSRRO modification might be needed There are two cases which determine if the manipulation is needed or not such information should be decided in the user handler and passed down to the low level driver 1 User handler was able to find the cause of the machine check exception and to fix it in a way that program can re execute the same instruc
4. and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONA
5. Ly 4367 Z4 Core exception overview 1 1 Interrupt type Exception conditions Machine check Z4 Core exception overview 24 Core used on SPC56EL60xx SPC56xL70xx devices contains many exception sources and sixteen interrupts to service them Multiple exception sources can be mapped to one interrupt handler where few supportive status registers provide flags to find the cause of the exception in the handler Detail list of exception causes and their mapping to interrupt handlers can be found in the Z4 Core Reference Manual This reference manual is available online at http www st com This chapter gives overview simple overview of machine check interrupt that is utilized for several important fault states of SPC56EL60xx SPC56xL70xx device Machine check interrupt IVOR1 Machine check interrupt is a handler that services multiple fault events that can occur during runtime code execution Table 1 Machine check interrupt causes NMI ISI ITLB Error on first instruction fetch for an exception handler Parity Error signaled on cache access External bus error MCSR syndrome register This interrupt is used to handle various faults generated by peripherals in the SPC56EL60xx SPC56xL70xx device like MPU protection fault 2DECC error in the Flash or RAM memory etc The reason is that most of the faults are signaled back as external bus error situation during the CPU Submodule bus tran
6. type back to the low level driver indication if MCSRRO content should be modified or not before merfi instruction Figure 3 Machine check exception user handler flow Machine check exception bus error termination Low level driver Access type check Instruction fetch IF DR DW Data read write Memory range check MAV 1 Flash Code Clear MCSR MAV bit after reading MCAR value 3 Low level driver provides information to the user handler User Handler Submodule check Fault processing and fix if possible User handler passes information about the requested return Program will continue on next instruction following the failing one fo avoid fault retrigger in case the fault remains Program will continue from fhe same No instruction that caused the exception because fault was solved Update MCSRRO merfi Return from machine check exception 4 DoclD025333 Rev 1 9 13 SPC56EL60xx SPC56xL70xx exception cases AN4367 3 SPC56EL60xx SPC56xL70xx exception cases This chapter lists most common exception cases that application software can experience while running code on SPC56EL60xx SPC56xL70xx device Table 4 SPC56EL60xx SPC56xL70xx exception causes Exception cause Error Exception Description signaling External bus Two or multiple bit error in the Flash memory leads to the Flash 2b ECC error buon Machine check machine check exception when faulty area is read instructi
7. with the current instruction execution Error Report Machine check stream They are not masked with MSRye bit It means the exception is always IF _LD ST G taken whenever the condition occurs They enable to differentiate between Instruction fetch Data store and load Non maskable interrupt Not MSRyg gated exception that occurs when NMI signaling is enabled and NMI NMI pin is driven low Asynchronous Machine check the Core They have to be enabled by MSRye bit They are cumulative This BUS_IREER BUS_DRERR machine check exception group triggers capture of the corresponding address to BUS_WRERR the MCAR register if MCSRyay bit is cleared If MCSRyay was previously set 6 13 Exceptions reported by the subsystem usually as bus error termination back to then the MCAR register is not affected Machine check address register MCAR MCAR register contains target address reporting the fault condition It is updated only for Asynchronous Machine check group when MCSR MAV bit is cleared and it is valid only if MCSR MAV status flag is set Otherwise the MCAR register cannot be used in the fault analysis It is important to clear MCSR MAV bit after reading MCAR register value to enable capture of the address in case of new asynchronous machine check fault Machine check MCSRRO register This register is updated by the HW in the beginning of the machine check interrupt It stores the address of the instruction that cau
8. L SAFETY REQUIREMENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FORMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippin
9. ata write Only instruction fetch or data read access are expected in case of 2 Flash error e Memory range e Memory access must be within area belonging to the Flash memory User has to know which part belongs to the code flash and which part to the data flash memory 3 1 4 Error solving Flash 2b ECC error can be solved only with erase of the flash sector containing the cell with 2b ECC error It is usually not the thing to be done in the exception handler itself because it takes significant amount of time It is application specific the decision what to do in case of 2b ECC error if to go to degraded mode or to continue the case of EEPROM emulation and to solve the issue later in the application If the decision is to continue user handler has to request modification of the MCSRRO register to continue the program flow with next instruction Otherwise program would be stuck in the read of the fault flash address invoking machine checks DoclD025333 Rev 1 11 13 Revision history 4367 Revision history 12 13 Table 6 Document revision history Date 02 Oct 2013 Revision 1 Initial release Changes DoclD025333 Rev 1 4367 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document
10. es Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ly DoclD025333 Rev 1 13 13
11. on fetch or data read In general all protection access exceptions and 2b ECC exception leads to the same machine check exception because of external bus error termination In such case further analysis relies on memory area check 3 1 Flash 2b ECC error 3 1 1 Cause of the exception Platform flash memory controller PFLASHC terminates bus transaction between CPU and PFLASHC controller in case the Flash memory array signals 2b ECC problem during read access This leads to machine check exception because of bus error termination Figure 4 Flash 2b ECC error Read access Instruction fetch or Data PFLASHC Y 2b ECC error found FLASH Array Extemal bus error termination read Read data from Flash array 10 13 DoclD025333 Rev 1 Ly 4367 SPC56EL60xx SPC56xL70xx exception cases 3 1 2 Machine check exception status Table 5 Flash 2b ECC machine check exception status Register Description Address of the instruction that caused the exception In case of ECC error in the data flash MCSRRO Pap area register modification will be most probably needed MCSR Type of operation is highlighted here instruction fetch data load or data write Target address that was accessed but finished with 2b ECC error This address can be MCAR used for further analysis 3 1 3 User exception handler Handler has to analyze e of access instruction fetch data read d
12. saction Machine check registers 24 core implements few machine check status registers that are updated upon the exception event with some constraints stated in the Z4 Core Reference Manual These registers are used to find the source of the exception and based on it to decide how to solve it Table 2 Machine check register Register Content Register indicates the source of machine check condition that gives possibility to differentiate between them MCAR address capture exception was raised Register contains for some sort of machine check conditions the address for which the asynchronous type of the machine check Address valid only when MCSR MAV bit was 0 before the exception otherwise MCAR register is not updated DoclD025333 Rev 1 5 13 Z4 Core exception overview AN4367 Table 2 Machine check register continued MCSRRO Save Restore register exception is finished mcrfi instruction program starts execution with Register Content Address of the instruction that caused the exception Once the the same instruction that was the cause of the exception Machine check syndrome register MCSR This register is the first register to check as it collects additional information about the cause of the exception There are three groups of machine check causes Table 3 Machine check causes Machine check cause Brief description These exceptions are directly associated
13. sed the error condition It is used in the end of the machine check when instruction is executed to fill the instruction pointer The result is that code restarts the same instruction that was cause of the error if additional modification of the MCSRRO register is not explicitly done DoclD025333 Rev 1 Ly AN4367 Machine check handler 2 2 1 Machine check handler Machine check handler usually splits into two parts e level handler e User handler Low level handler Low level handler is responsible for first and last part of the exception execution It is usually written in assembly as it needs to execute proper instruction sequence before it can pass the code execution to higher level routine and accesses special purpose Core registers The middle of the interrupt service routine belongs to the user handler where analysis of the root cause of the exception and fault removal is done Once the user handler is finished code execution is given back to the low level driver to finish the interrupt and return back to the interrupted process Figure 1 Machine check exception flow Machine check exception t HW updates MCSSRO MCSRR1 Standard exception processing Low level handler prepare info for user handler User handler prepare for finishing the interrupt Low level handler MCSRROupdateif needed j i AM Interrupted process continues
14. tion that caused the machine check exception 2 User was able to find the cause of the exception but the problem remains and re executing the same instruction would lead again the machine check exception gt Modification of the MCSRRO is needed Modification of the MCSRRO register In case that the cause of the exception cannot be removed MCSRRO register value has to be modified in a way that it takes the address of the following instruction This prevents re execution of the faulty instruction and retriggering the machine check exception Modification has to consider VLE instruction coding in case the interrupted process is implemented in VLE coding and increment the value accordingly of the length of the faulty instruction pointed by the current MCSRRO register content see Figure 2 Figure 2 Modification of MCSRRO register content instruction Read content of address given by MCSRRO reg Y 0 Instruction k Bit 3 1 instruction Bit 0 16 bit 0 32 bit instruction instruction Y MCSRRO MCSRRO MCSRRO 2 MCSRRO 4 DoclD025333 Rev 1 Ly 4367 Machine check handler 2 2 User handler Here the root cause analysis is done Such analyses requires supportive information from e Low level driver MCAR MCSR etc e Peripherals status registers for further elaboration Based on the results of analysis and corrective actions done user handler should pass the information about the return
Download Pdf Manuals
Related Search