Raggedstone3 User Manual Issue – 1.0
Contents
1. Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Push Button Switches 19 Raggedstone3 has two tactile push button switches To use these switches it is necessary to set the IO pins connected to the switches to have a pull up resistor setting in the constraints file Any switch pressed or made will then give a LOW signal at the FPGA otherwise a HIGH is seen The two push button switches are connected to the following IO pins SWITCH 1 SWITCH 2 L14 H8 RAGGEDSTONE3 s il LA LIIIIIIIJ 00000000 T 22141 100 3 L SRRELIFFTEIT LI 0000000066 0000000900 Di e e o o bd Rees 0009900 ATELE i 220000000 1000000000000 TT nea TII NE 292 4009999900000 00000209000900000900 gt www enterpoint co uk C 2011 Enterpoint Ltd Figure 10 Raggedstone3 Switches Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 20 gU RAGGEDSTONE3 uu ME ISSUE 1 ad AA T x LA si 25 sop se e oo se ss ss se ee re oe oo ee eo ce LA a eo ce eoe i A mo i 22 t eo Lo MET TY 35 Le HE Sii ti ms z LT 1 443 338 U15 soe tf 0 26 i i m 35 ee ee U16 55 s 33 S ss H LA Figure 10 Raggedstone3 DDR2 Raggedstone3 has two Micron MT47H32M16BN or Winbond W9751G6JB 25 DDR2 device2. FPGA Raggedstone3 supports Cyclone IV devices in the 484 pin package Raggedstone3 is normally available with the EPACGX110 FPGA fitted which has 109 424 logic elements or the larger EP4CGX150 149 760 Logic elements Should you have an application that needs industrial or faster speed grades please contact sales for a quote at boardsales enterpoint co uk Oscillator The oscillator socket U12 on Raggedstone3 supports 3 3V 8 pin DIL outline oscillator crystals This clock signal is routed directly through to the FPGA on pin K10 Bank 8 which is a Clock input to the FPGA A fixed 25MHz ASEM oscillator is also fitted to Raggedstone3 The signal from this oscillator is connected to the FPGA on pins L21 and L22 Bank 6 which are Clock inputs to the FPGA The Cyclone IV has Digital Clock Multipliers DCMs to produce multiples divisions and phases of clock signals Please consult the Cyclone IV datasheet available from the Altera website at http www altera com if multiple clock signals are required LEDs On Raggedstone3 there are 5 LEDS LEDI is situated on the top left corner of the board and indicates the presence of the 3 3v power rail It is not available for other uses LEDs 2 to 5 which are situated the top of the board to the right of the 7 segment display are user LEDs and are connected to the FPGA as indicated below LED2 LED3 LED4 LEDS R22 115 T18 T17 LED1 LEDS 2 TO 5 LEDS LED2 RAG
3. Trademarks Cyclone Altera Byteblaster Quartus are trademarks of Altera Corporation San Jose California USA Raggedstone3 is a trademark of Enterpoint Ltd Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 ETC ISSUE 1 66 00006 000000000000000000 EE TII 00000000 9990909 99990 2685826 die HEADER TOP i 586558 e o e e e e e z e e e 0909990909090 25585 0000000000 900000000 VLLLLILIII 0000000000 0090090090 www enterpoint co uk C 2011 Enterpoint Ltd Figure 1 Raggedstone3 Board Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Introduction Welcome to your Raggedstone3 board Raggedstone3 is Enterpoint s Cyclone IV PCIE version of the very popular Raggedstonel FPGA development board The aim of this manual is to assist in using the main features of Raggedstone3 There are features that are beyond the scope of the manual Should you need to use these features then please email support enterpoint co uk for detailed instructions Raggedstone3 comes in two main variants either based on an EP4CGX110 or EP4CGX150 Cyclone IV FPGA Should you need a non standard size speed grade or temperature grade of Cyclone IV FPGA fitted to your Raggedstone3 please contact Enterpoint sales for a quote In addition Raggedstone3 is supported by a wide range of add on modules So
4. point Raggedstone3 User Manual Issue 1 0 Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Kit Contents You should receive the following items with your Raggedstone3 development kit Raggedstone3 Board 2 4 Digit 7 Segment LED display fitted 3 PCI mounting bracket fitted 3 Prog2 parallel port or Prog3 USB programming cable Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Contents Kit Contents Foreword Trademarks INTRODUCTION RAGGEDSTONE3 BOARD GETTING STARTED AIN SELECTING THE FPGA BANK VOLTAGES PROGRAMMING RAGGEDSTONE3 RAGGEDSTONE3 FEATURES 12 POWER INPUTS AND PICKUPS 12 POWER REGULATORS 13 DIL HEADERS 14 SIL HEADERS 16 CLOCK MODULE HEADER 16 7 SEGMENT DISPLAY HEADER 17 FPGA 18 OSCILLATOR 18 LEDS 18 USB 19 SWITCHES 20 DDR2 MEMORY 21 PCIE 23 SERIAL EEPROM 24 TEMPERATURE SENSOR 24 CONFIGURATION CPLD 25 SPI FLASH 25 MECHANICAL 26 Medical and Safety Critical Use 27 Warranty Zi Support 27 Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR RAGGEDSTONE3 BOARD PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL
5. 3 H PIN30 ss SEE Figure 7 Raggedstone3 DIL Headers Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 15 SIL Headers There are 4 SIP headers on Raggedstone3 They are arranged as 2 pairs J10 and J12 form the Clock Module header and have 5 pins each The two 8 pin SIL headers are usually used to support the LTC C4627JR 4 digit 7 segment display U14 however the 7 segment display to make these pins available to the user Voltages outside the range OV to 3 3V must not be applied to the SIL headers The Cyclone IV has a maximum IO input voltage of 3 9V U14 PINS PIN1 PIN16 PINS SACL EDS TONGS v PIN1 23 PIN1 J10 Jis J12 PINS 255 ER ces 44444444 ce eo oo e oo oo oo oo e 2 0000 20000000 TOEL Figure 8 Raggedstone3 SIL Headers 1 CLOCK MODULE HEADER These header pins are designed to allow the Enterpoint Clock module to be fitted This module is fitted with an ICS8442 700MHZ Crystal Oscillator To Differential LVDS Frequency Synthesizer device If this module is not fitted the header pins are available to the user J12 has a permanent positive power pin 3V3 at the top position J10 has a GND connection at the top position The connections to the FPGA are shown below with the Bank number in parentheses J10 J12 SIGNAL J10 PIN FPGA SIGNAL J12 PIN FPGA NAME NUMBE
6. the DDR2 memory devices 3 3V REGULATOR IIIIIII 0000000000000 1 2V REGULATOR 551104 2 5V REGULATOR E 1 5V REGULATOR 0 75V REGULATOR Figure 6 Raggedstone3 POWER REGULATORS Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 DIL Headers The four 2x30 DIL Headers provide a simple mechanical and electrical interface for add on modules The connectors on this header are on a 0 linch 2 54mm pitch and allow either custom modules or strip board to be fitted The headers have a row of permanent positive power sockets 3 3V to the left of JL2 and JR2 and a row of permanent GND 0V sockets to the right of the JL1 and JR1 Voltages outside the range OV to 3 3V must not be applied to the DIL headers The Cyclone IV has an absolute maximum IO input voltage of 3 9 V The connections between the DIL the headers and the FPGA are shown below LEFT DIL HEADER RIGHT DIL HEADER JL1 JL2 JR1 JR2 1 J13 OV 3 3V C16 B19 OV 3 3V G22 2 H13 OV 3 3V B16 A20 OV 3 3V F22 3 D9 OV 3 3V D15 B20 OV 3 3V J21 4 C9 OV 3 3V C15 B21 OV 3 3V H22 5 F8 OV 3 3V B15 C19 OV 3 3V K19 6 E8 OV 3 3V A15 C20 OV 3 3V K20 7 B7 OV 3 3V D14 E21 OV 3 3V N21 8 A8 OV 3 3V C14
7. 000900009009000 dimensions are shown in millimetres AND are subject to manufacturing tolerances The maximum height of the components on the board is approximately 13mm measured from the lower surface of the PCB to the upper surface of the 7 segment display If the display is not fitted the maximum height is approximately 12 5mm measured from the lower surface of the PCB to the upper surface of the 2 1mm jack socket If you need any further mechanical information please contact us Contact information is shown on page 27 of this manual Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 26 Medical and Safety Critical Use Raggedstone3 boards are not authorised for the use in or use in the design of medical or other safety critical systems without the express written person of the Board of Enterpoint If such use is allowed the said use will be entirely the responsibility of the user Enterpoint Ltd will accepts no liability for any failure or defect of the Raggedstone3 board or its design when it is used in any medical or safety critical application Warranty Raggedstone3 comes with a 90 day return to base warranty Do not attempt to solder connections to the Raggedstone3 Enterpoint reserves the right not honour a warranty if the failure is due to soldering or other maltreatment of the Raggedstone3 board Outside warranty Enterpoint offers a fixed price repair or replacement service We reserve the right not to o
8. 5V supply The choice of which of these 3 3V supplies is used is determined by the settings of J7 When using the on board 5V to 3 3V regulator the 5V input power that powers the board is supplied either through the DC Jack J8 or the disk drive connector J13 5V pin Only a single input 5V supply should be used as these inputs are hard connected together on Raggedstone3 and differential inputs will cause large currents to flow between the input 5V options Care should also be taken not to exceed 5 5V on either of these inputs as an overvoltage will damage the regulator circuit The 1 2V 1 8V and 2 5V power rails are derived from the internal 3 3V rails using 3 further MIC22600 regulator circuits Fig 3 below shows the locations of test points where you can check voltages on the Raggedstone3 For powering add on modules Raggedstone3 has 30 header pins with 3 3V and OV available on each side of the board allowing users to access power for their own add on circuitry These pins are arranged on a 0 linch grid to enable users to plug in their own stripboard designs 2 1MM JACK SOCKET DISK DRIVE COLUMN OF COLUMN OF 30 COLUMN OF 30 CONNECTOR 30 OV SOCKETS 3 3V SOCKETS OV SOCKETS Me 0000000 LT 1 2V TEST POINT 2 MITTIT D L LIIITIT Ra 920292900955 0000000000008 TII e ce e 020909000000000000 Li T 000 rb dies 1 Ein LI 9090000090009 099999000 090000002000
9. COLUMN OF 30 2 5V TESTPOINT 3 3V SOCKETS 1 8v TESTPOINT Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 12 Figure 5 Raggedstone3 Power Supply Features Power Regulators WARNING THE REGULATORS MAY BECOME HOT IN NORMAL OPERATION ALONG WITH THE BOARDS THERMAL RELIEF PLEASE DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE RAGGEDSTONE3 BOARD IS IN OPERATION Raggedstone3 has four Micrel MIC22600 switching regulator circuits These regulators are each capable of delivering 6 amps but may be limited by input supply and fusing restrictions As standard a 2 6A fuse is fitted limiting the power usage of Raggedstone to about 8 6W but for special OEM build this fuse can be replaced with a higher capacity link allowing a higher board power envelope In such special configurations the board power envelope can rise to 10W when powered from the PCIe connector or 20W when using one of the 5V input options For OEM customers of this board we can also offer a MIC22700 in any on the MIC22600 regulator positions offering a slightly higher 7A capability if needed If more current is drawn the resettable fuse will cut the supply to the board if this happens the power supply must be switched off and time given for the fuse to reset which occurs when the fuse has cooled and reconnected its internal contacts This typically takes 1 2 seconds A fifth linear regulator LP2996 provides a 0 9V reference for
10. E22 OV 3 3V N22 9 D7 OV 3 3V B13 F20 OV 3 3V R19 10 C7 OV 3 3V B12 E20 OV 3 3V T20 11 H12 OV 3 3V G15 J19 OV 3 3V T19 12 G12 OV 3 3V G14 J20 OV 3 3V U20 13 C11 OV 3 3V J14 M13 OV 3 3V V20 14 C10 OV 3 3V H14 L13 OV 3 3V V21 15 B9 OV 3 3V A14 T21 OV 3 3V A21 16 AQ OV 3 3V A13 T22 OV 3 3V A22 17 D8 OV 3 3V C13 K22 OV 3 3V C22 18 C8 OV 3 3V C12 J22 OV 3 3V B22 19 E6 OV 3 3V A12 M18 OV 3 3V D19 20 D6 OV 3 3V A11 M19 OV 3 3V D20 21 H7 OV 3 3V B10 N19 OV 3 3V D21 22 G7 OV 3 3V A10 N20 OV 3 3V D22 23 C4 OV 3 3V A7 N17 OV 3 3V F18 24 C3 OV 3 3V A6 M17 OV 3 3V G19 25 C2 OV 3 3V C6 R20 OV 3 3V G20 26 Ci OV 3 3V B6 R21 OV 3 3V Gel 27 D4 OV 3 3V A5 V22 OV 3 3V H20 28 C5 OV 3 3V A4 U22 OV 3 3V H21 29 E5 OV 3 3V B4 W20 OV 3 3V Y22 30 D5 OV 3 3V B3 W21 OV 3 3V W22 The signals on the DIL headers are arranged in LVDS pairs and routed such that the trace lengths approximately match and skew is minimised within pair Adjacent LVDS P and LVDS N form the matched pair at the DIL Header and the Cyclone IV FPGA For example H12 and G12 form one pair Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 14 LVDS pairs can be used as general inputs outputs from the Cyclone IV JL1 JL2 JR1 JR2 RAGGEDSTONES PIN1 ME i cet i RA PINI ss
11. GEDSTONE3 N A CENSURE 20092225 OSCILLATOR 22 SOCKET ecce 1a Es ers mm 3 ms Li med aut 00000000000000008 L ilo 14 ed e PIN1 0000000000 22002000000 Figure 8 Raggedstone3 FPGA Oscillator socket and LEDs Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 18 USB USB SOCKET MINI B FTDI DEVICE LA IIIIIIIJ 2 02992009 LLLILITITIILIIITTT PITTTTT LLC A ded IIIIIIIITIIIIIIIAII AAA Figure 10 Raggedstone3USB interface The USB interface on the Raggedstone3 is achieved using an FT232R USB to serial UART interface The datasheet and drivers for this device are available from http www ftdichip com When appropriate drivers are installed the Raggedstone3 USB port should be detected as a serial port Alternative data optimised drivers are also available from FTDI The FT232R is connected to the Cyclone IV and provided a simple UART or other converter is implemented then the data sent over the USB serial port can be used either as control and or data information This allows a host computer to act in a number of ways including system control and data storage functions The connections between the USB device and the FPGA are shown below FT232R FPGA PIN CTS D17 DCD C17 DSR 17 RH E17 RTS J10 DTR A16 TXD F16 RXD F17
12. PBACK TEST sof EP4CGX110CF23 Choose the options shown above right clicking in the white window to activate the add file button and navigating to your sof file Click Generate The pof file will appear at the location chosen b Programming the flash memory Return to the Quartus programmer Programmer IChainl cdfj i File Edit View Processing Tools Window Help amp Hardware Setup ckground programming for MAX II and MAX V devices File Device a Usercode Program Configure none EP4CGX110 00000000 lt none gt lt none gt EPM2210 00000000 00000000 7 4 E PROJECT_ARCHIV QSPI iGb gi Auto Detect 0 X Delete a Add Fite 5066606068 Right click on the none to the left of QSPI 1Gb and navigate to your pof file Check the boxes in the Program Configure column it is only necessary to check the top of the 3 checked boxes the others check automatically Click on the Start button The SPI flash devices will program This will take 5 10 minutes Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 11 Raggedstone3 Features Power Inputs and Pick ups Raggedstone3 is powered from 3 3V input direct from the PCIe edge connector or the 3 3V output from an on board Micrel MIC22600 6A regulator circuit This regulator circuit produces 3 3V from an input
13. R PIN NAME NUMBER PIN DGND PINI OV VD3V3 PINI 3 3V GCLKI PIN2 M7 3 CLKHDRI PIN2 P20 5 GCLKO PIN3 N7 3 CLKHDR2 PIN3 P22 5 CLKHDR5 PIN4 L19 6 CLKHDR3 PIN4 R16 5 CLKHDR6 PINS L20 6 CLKHDR4 PINS R17 5 Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 16 The connections to J10 are LVDS pairs connecting to Differential Clock inputs on the FPGA The connections to R16 R17 and L19 L20 are on LVDS pairs The Connections to P20 and P22 are to general purpose IO pins The horizontal distance between J12 and J10 is 0 6inch 15 25mm 2 7 SEGMENT DISPLAY HEADER The two 8 pin headers which form the 7 segment display holder U14 have 14 connections to the FPGA Of these 14 connections 8 shown BOLD have series 470ohm resistors which are normally used as current limiting resistors for the 7 segment display This should be taken into account if this header is used for other purposes The connections between U14 and the FPGA are shown below Bank number in parentheses PIN16 PIN15 PIN 14 PIN13 PIN12 PIN11 PIN10 PIN9 D11 8 F12 7 D12 8 H17 6 J15 6 A18 7 NC NC PIN1 PIN2 PIN3 PIN4 PINS PING PIN7 PINS G10 8 D10 8 D13 7 H9 8 G16 6 G17 6 A19 7 D16 7 Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 The vertical distance between the upper and lower pins of U6 is 0 4inch 10 2mm 17
14. TA0 K4 M15 CFG DATAI D1 L12 CFG DATA2 G8 M16 CFG_DATA3 G6 M13 CFG_DATA4 F6 L14 DATAS5 WA N14 DATA6 Y4 M14 CFG _DATA7 R9 P15 CONF_DONE U5 N15 NSTATUS R8 N16 DCLK D3 L13 NCONFIG H4 111 SPI Flash Memory The four MX25L25635ENZI Quad flash memory devices hold the configuration code for the FPGA when it is powered providing a suitable pof file is programmed into the devices The combined capacity of the four 256Mbit flash memory devices is 1GBit with a single configuration bitstream for Raggedstone3 taking 3 5MBits Advanced users may wish to use the remaining space in the four flash memory devices for alternative configuration data files or user code and data storage This will entail modifying the configuration file in the CPLD After configuration the SPI Flash devices can be accessed via the following pins of the CPLD The pin number on the flash memory device appears in parentheses following the signal name P13 MI2 MII R7 CS 1 Q MISO1 2 R16 R13 N9 T6 WP MISO2 3 P12 Pll R8 M7 HOLD MISO3 7 T15 T13 8 R6 CCLK 6 N12 Nill 7 7 D MISOO 5 R14 R12 P8 T5 Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 25 Mechanical information 006000000 o 9 o Le o o Le o o Le 9 o o o 000000000000000000000000000000 000000000000000000000000000008 d000000000000000090
15. Then check the Program Configure box on the same line as the Cyclone IV device and click on the Start button on the left The progress bar at the top left of the screen should turn green as programming proceeds This process is very quick typically 10 15 seconds Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 10 2 Programming the SPI flash memory This is a 2 stage process converting the sof file into a pof file then programming the flash memory a Converting the file On the Quartus screen file menu choose convert programming files This screen will appear Qu Convert Programming File File Tools Window Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Programmer Object File pof X Options Configuration device CFI 16b Mode Fast Passive Parallel M File name E PROJECT_ARCHIVES RAGGEDSTONE3 fpga_builds altera_builds RS3_LOOPBACK_TEST output_file pof Advanced Remote Local update difference file NONE V Memory Map File Input files to convert File Data area Properties Start Address 0 00000000 auto Options 4 SOF Data Page 0 RS3 LOO
16. as 3 address lines which are permanently connected to OV It can run at speeds up to 400 kHz This serial memory has 2048 words of 8 bits and employs a byte or page programming system The connections between the EEPROM and the FPGA are shown below EEPROM SIGNAL FPGAPIN SDA B18 SCL C18 WP G18 Temperature Sensor There is a temperature sensor type LM75C on Raggedstone3 which has a 2 wire serial interface and an output which behaves as an over temperature warning The connections to the FPGA are shown below SIGNAL FPGAPIN SDA BI SCL A2 OVER TEMPERATURE Al RAGGEDSTONES s a m Ko gt ISSUE 1500000000 zi Les n ra TEMPERATURE peg tea 2 i SENSOR 2 ze 43 11 jee so PCIE CONNECTOR i www enterpot co uir C 2011 Enterpoint Lid EEPROM Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 24 Configuration CPLD Raggedstone3 uses an EPM2210F256C5 CPLD to configure the Cyclone IV FPGA from four 128Mbit SPI flash memory devices This device is preloaded with a core which takes the configuration data from the 4 flash memory devices and sends it in an 8 bit parallel format to the FPGA A 50 MHz oscillator drives the configuration rate The connections between the CPLD and the FPGA are CFG_DA
17. connector or plug in a 5V power supply using the 2 1mm Jack socket 3 Fit an oscillator into the oscillator socket may already be fitted 4 Switch on your power source Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Selecting the FPGA Bank voltages The User I O pins of the Cyclone IV on Raggedstone3 are divided into 2 banks The left hand side header pins are routed to Banks 7 and 8 of the FPGA the Right hand side headers are routed to Banks 5 and 6 The IO voltages are set to either 3 3V or 2 5V using jumpers on the 6 pin headers J11 for Banks 5 and 6 and J9 for Banks 7 and 8 Alternatively a user generated Bank IO voltage could be introduced on pin 2 of J9 or J11 There is a OV reference on pin 5 of J9 and J11 for this purpose If you choose to use this option please refer to the Cyclone IV user manual from www altera com to check the allowed IO voltage range for the FPGA J9 J11 OO 30 11980090060 1 1 S 0000080 eo se ee ee so ee ee e 00000000000 Lj TIZI Figure 4 Raggedstone3 VCCO Supply Selection Figure 4a Pin allocation of J11 J9 is identical Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Programming Raggedstone3 The programming of the FPGA and SPI Flash on Raggedstone3 is achieved using the JTAG connection There is a single JTAG c
18. edstone3 Manual Issue 1 14 04 2012 22 PCIe Edge Connector The Raggedstone3 has a x4 PCIe Interface The pin out of the Cyclone IV FPGA has been chosen such that the PCI interface follows the pinout for the Altera Cyclone IV hard core for PCIe which can be generated automatically by the Quartus software The configuration arrangement of Raggedstone3 allows the FPGA to configure within the time requirements for the PCIe specification The connections between the PCIe connector and the FPGA are shown below SIGNAL PCIE CONNECTOR FPGA PIN NAME PIN PCIE CLK P A13 MII PCIE_CLK_N A14 Nil PCIE P 16 2 PCIE 17 PCIE 14 Y2 PCIE_RX0_N B15 PCIE PWRGD 11 20 PCIE_PRESENT 1 A TO B32 PCIE_PRESENT 2 B17 PCIE_PRESENT 3 B32 TO AI PCIE_TX1_P A2 P2 PCIE TX1 N A22 PI PCIE RXI P B19 T2 PCIE N B20 TI PCIE TX2 P A25 K2 PCIE TX2 N A26 KI PCIE RX2 P B23 M2 PCIE RX2 N B24 MI PCIE TX3 P 29 F2 PCIE TX3 N A30 Fi PCIE RX3 P B27 H2 PCIE RX3 N B28 HI Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 23 Serial EEPROM Raggedstone3 has a 16K Two Wire Atmel AT24C16BY6 EEPROM device which uses a simple Parallel address and single serial data line and clock There is also a write protect line which can be used to electronically safeguard the information contained in the device The EEPROM h
19. ffer this service where a Raggedstone3 has been maltreated or otherwise deliberately damaged Please contact support if need to use this service Other specialised warranty programs can be offered to users of multiple Enterpoint products Please contact sales on boardsales enterpoint co uk if you are interested in these types of warranty Support Enterpoint offers support during normal United Kingdom working hours 9 00am to 5 00pm Please examine our Raggedstone3 FAQ web page and the contents of this manual before raising a support query We can be contacted as follows Telephone 44 0 121 288 3945 Email support enterpoint co uk Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012
20. hain on Raggedstone3 The JTAG chain allows the programming of the Cyclone IV the configuration CPLD and the SPI Flash devices There are 2 JTAG connector sites on Raggedstone3 The first J2 is a 2x7x2mm right angled connector which is used with the Enterpoint PROG4 programming cable This connector has a layout as follows Top edge of board GND GND GND GND GND GND GND The second JTAG connector site J1 is designed to accept the 2x5x0 linch header used by the Altera USB blaster programming cable The pinout is shown below TDI NC GND NC NC Using the Quartus Programmer and Auto Detect the JTAG chain appears like this Fie View Processing Tools Window Hep 2 setup Us saster 358 0 Enable real time ISP to allow background programming for MAX II and MAX V devices Device EPM2210 QSPI 256Mb 4 1 Programming the FPGA directly Direct programming of the Cyclone IV FPGA is volatile and the FPGA will lose its configuration every time the board power is cycled For sustained use of an FPGA design programming the design into the Flash memory is recommended see 2 below Direct JTAG programming of the FPGA using a sof file is useful for fast temporary programming during development of FPGA programs Right click the word lt none gt to the left of EP4CGX110 above Choose Add File Navigate to your sof file
21. me examples of these include ADC 7927 MODULE LED DOT MATRIX MODULE BUTTONS SWITCHES SATA MEMORY MODULE RS232 AND RS485 HEADER MODULES DP83816 ETHERNET MODULE SD CARD MODULE DDR2 MODULE IDE SV TOLERANT CPLD MODULE USB2 MODULE D A CONVERTER MODULE ADV7202 MODULE OLED DISPLAY MODULE FT4232 4 CHANNEL USB MODULE SPI ETHERNET MODULE ACCELEROMETER MODULE XC383400A ACCELERATOR MODULE X1 XC6SLX150 ACCELERATOR MODULE X2 XC6SLX150 ACCELERATOR MODULE New modules are regularly added to our range We can also offer custom DIL Header modules should you require a function not covered by our current range of modules Typical turn around for this service is 6 8 weeks depending upon quantity ordered and availability of components Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 Raggedstone3 Board USB JTAG INTERFACE CONNECTOR 7 SEGMENT DISPLAY 4 USER LEDS USER DEFINED OSCILLATOR RAGGEDSTONES mc i uit d 4 x 128Mbit FLASH 122229229 21 00000006 290000000000 o Q ve o e e 7 CONFIGURATION CPLD AXI 00000 200000000000 2 PUSH BUTTON SWITCHES PCIE CONNECTOR FPGA DDR2 Figure 2 Raggedstone3 MAIN FEATURES Getting Started Your Raggedstone3 will be supplied with a default setting of jumpers fitted 1 Fit the LED 7 segment display into its connector may already be fitted 2 Either connect the Raggedstone3 board to a powered PCIe
22. s as standard These devices are organised as 8 Meg x 16 x 4 banks These devices are supported by the hard core memory controller that is in the Cyclone IV FPGA To add this core to your design use the Megafunction wizard tool part of the Quartus suite which will generate implementation templates in VHDL or Verilog for the configuration that you want to use More details on the memory controller can be found in the user guide http www altera com The DDR2 devices use 16 address lines and 32 data lines to address all the available memory which can be accessed at speeds of 2 5ns The Address lines A 0 15 are common to the two DDR2 devices as are the ODT BA 0 2 CS RAS CAS WE and all the Clock signals The remaining signals from each DDR2 device are routed separately to the FPGA U16 connects via data lines DQ 0 15 DM 0 1 and DQS 0 1 while U15 connects via DQ 16 31 DM 2 3 and DQS 2 3 More details of the DDR2 can be found from www micron com the signals are terminated with appropriate resistors There is a timing loop implemented between pins AA12 and AB12 The connections between the FPGA and the DDR2 devices are shown below Enterpoint Ltd Raggedstone3 Manual Issue 1 14 04 2012 21 The DDRZ2 sites have the following connections to the FPGA DDR2 SIGNAL peu DDR2PIN DDR2SIGNAL pon DDR2 PIN DDR A8 AAI3 P8 DDR AIS YIT RS Eo ee E Enterpoint Ltd Ragg
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