MIDAS-20/20R MIDAS
Contents
1. 4 Qm e 6 mum 9m a PMC MODULE 5 DS F aa Ct ET r oss sd I 41 342 Mat M22 LJ PMC MODULE 4 PMC MODULE 2 H4 i Lh n Lal e p EN 331 J32 MT 2 PMC MODULE 3 n PMC MODULE 1 J34 1a AOL o D Figure 5 Steps 2 amp 3 Mount PMC modules on the MEZZ x50 and the MIDAS 50 mother board Q STEP 4 Note Before proceeding make sure that the switch and jumper settings on the MIDAS 50 50R mother board is according to the needs of your application Mount MEZZ x50 with PMC modules on the MIDAS 50 50R mother board If the SPACER x50 board and the five metal spacers are not already mounted on the bottom side of the MEZZ x50 board do it now Place the MIDAS 50 50R mother board on a smooth static protected work surface Carefully position the MEZZ x50 board over the MIDAS 50 50R mother board so that the three connector on the bottom side of the spacer are aligned with the connectors J50 J51 and J52 on the MIDAS 50 50R mother board Make sure that neither of the five metal spacers mounted on the MEZZ x50 board touches components or component leads on the MIDAS 50 50R mother board in the process Push the MEZZ x50 board down so that all connectors m2. Power Up Options Registers The VME PCI bridge on MIDAS is highly programmable through a large number of internal registers In addition to this MIDAS has one status register and a configuration ROM implemented in a PLD All register amp ROM locations on MIDAS can be accessed from VMEbus as well as from the PMC modules Note that parity is not generated when reading the MIDAS status register and 0 configuration ROM Parity errors should therefor be disregarded when reading these locations In the power up state of the Universe VME PCI bridge parity errors are disregarded Register Access from VMEbus The MIDAS CR CSR PLD is accessed using PCI bus I O Space commands From VMEbus this is done by accessing the CR CSR address space of the board or by using one of the four VMEbus Slave Images in the VME PCI bridge This image must be set up to generate I O Space accesses on PCI bus 18 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Please refer to UNIVERSE USER MANUAL for details and for information on how to access registers internal to the VME PCI bridge Register Access from PCI Bus The MIDAS CR CSR PLD can be accessed directly from the PMC modules or the RACEway through the PXB chip by the use of the PCI bus I O Space commands Register Descriptions Universe Registers Please refer to UNIVERSE USER MANUAL for this information PXB Registers Please refer to PXB BRIDGE SPECIFICATION and Appendix IV for this
3. assumed 1 Alignment 1MB Table 28 Memory Mapped I O Limit Address Register Prefetchable Memory Base Address Register Register Name PMBAR Size 16 bits Offset 0x24 PMBA 31 24 PMBA 23 16 0000 PMBAR Description Name Type Reset Function State PMBA R W Base Address inclusive for Prefetchable Memory space 20 Isb assumed 0 Alignment 1MB Table 29 Prefetchable Memory Base Address Register MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Prefetchable Memory Limit Address Register Register Name PMLAR Size 16 bits Offset 0x26 PMLA 31 24 PMLA 23 16 0000 PMLAR Description Name Type Reset Function State PMLA R W Base Limit inclusive for PrefetchableMemory space 20 lsb assumed 1 Alignment 1 MB Table 30 Prefetchable Memory Limit Address Register Bridge Control Register Register Name BCR Size 16 bits Offset 0x3E 15 8 8 RESERVED 0000 0000 BCR Description Name Type Reset Function State FBTB E CEN NEN a Fast Back to Fast Back to Back Enable Enable SBRES Secondary Bus Reset 0 Do not assert RST 1 Assert RST on secondary bus MAM R W Master Abort Mode 0 Do not report master abort all 1 1 Report master abort with target abort LR MR EE for system errors detected on secondary bus and reported to primary bus PERREN ad ME EE eie Enable for parity errors response on secondary bus Table 31 Bridge Control Register MIDAS 20 20R
4. address space etc for initialization the initialization is done Note When the Auto Slot ID feature is enabled the MIDAS board asserts IRQ2 on VMEbus reset Auto Slot ID Plug amp Play The MIDAS has full support for the Auto Slot ID mechanism as defined by the VME64 specification By use of the daisy chained IACK signal CR CSR space accesses are enabled for one VME slot at a time Thus the Monarch host for initialization is able to recognize installed modules and initialize them to achieve Plug amp Play VMEbus systems The board is shipped with a jumper setting in which Auto Slot ID is enabled This means that MIDAS can be plugged directly into PnP VMEbus systems without moving jumpers VMEbus Switch amp Jumper Descriptions MIDAS has one DIP switch and five jumpers used for VMEbus configuration T gereg AUTO ID Figure 7 MIDAS Configuration Switch and Jumpers Auto Slot ID settings shown Switch amp Jumpers for manual configuration The DIP Switch and three of the jumpers are of this category Unless the Auto Slot ID protocol is used by the host system see section above and descriptions below these switch jumpers should be used to define a window in the VMEbus address space for configuration of the VME PCI bridge on MIDAS VME Register Access Image ENABLE DISABLE The VME Register Access Image VRAI permits accesses from VMEbus to the VME PCI bridge i
5. amp MIDAS 50 50R USER s GUIDE 39 40 PXB Bridge Control Register Register Name PBCR Size 8 bits Offset 0x40 PBCR Description Name Type Reset Function State EBAR EIXN SENE 00 5 Enable memory internal BAR 1 enable 0 disable memory internal BAR 1 enable 0 disable MODE Operating Mode 0 Bridge Mode 1 Endpoint Mode This bit should always be cleared use Bridge Mode Dwswar ww 1 vers Sn ee aan oswa ww o ovesi comis ocaso Prim Sec Mode 0 Secondary Mode 1 Primary Mode E ee ee Table 32 PXB Bridge Control Register MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Memory Window Register Register Name MWR Size 8 bits Offset 0x41 Function PPAGE MWSHIFT MWR Description Name Type Reset Function State PPAGE W Primary Page Used by secondary PXB as index into page ram when out of bounds accesses occurs should be set to unused page register Returns zeros when read MWSHIFT R W Memory window shift Selects which address bitsare used to index page ram during memory accesses Bits Big Window Small Window 0000 31 28 4GB 256 MB 0001 30 27 2 GB 128 MB 0010 29 26 1 GB 64 MB 0011 28 25 512 MB 32 MB 0100 27 24 256 MB 16 MB 0101 26 23 128 MB 8 MB 0110 25 22 64 MB 4 MB 0111 24 21 32 MB 2 MB Ixxx 23 20 16 MB 1 MB Table 33 Memory Window Register MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 41 TO MIO Window Register Register Name IOM
6. 64 Auto Slot ID ENABLE DISABLE By the use of a new address space for CR CSR accesses the VME64 specification defines a method for implementing Plug amp Play on VMEbus called Auto Slot ID The AUTO ID jumper controls the enabling of the VME64 Auto Slot ID mechanism Note that to fully support Auto Slot ID the Monarch needs access to Configuration ROM data located on the PCI bus Note When the Auto Slot ID feature is enabled the MIDAS board asserts IRQ2 on VMEbus reset zb come n UP VME64 AUTO SLOT ID ENABLED 7U z zi WT D IE F T DOWN VME64 AUTO SLOT ID DISABLED MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 13 SYSFAIL Assertion This jumper can be used to make the Universe assert SYSFAIL upon reset power up Normally this option should be disabled Jumper in its upper position adl E Sem lr UP SYSFAIL ASSERTION DISABLED aq lt EE 4j g zd di ll mig E 12 TE DOWN SYSFAIL ASSERTION ENABLED RACEway Interface Jumper Descriptions The MIDAS 20R 50R models incorporate the PXB chip a PCI RACEway bridge developed by Mercury Computer Systems MIDAS has two jumpers for configuration of the RACEway interface They are located close to the bottom edge of the board indicated with silk screen text RACEWAY As explained in the description b
7. AS Doc Kit MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Product Overview VMEbus Configuration Jumpers NC JTAG Connector Reset Button N N N N X X vn EES EE Te THEE 3 MIDAS 20 PCB C Cs Oo 9999 pss Soe PCI CONNECTORS for MIDAS 50 50R Expansion PCI CONNECTORS PMC 2 _ P2 VO CONNECTOR PMC 2 Not mounted for R option Universe Pci CONNECTORS PMC 1 P2 VO CONNECTOR PMC 1 Not mounted for R option Bridae modi RACEway PC ea m ic SS pe d og p o m F o RACEway Jumpers Figure 1 MIDAS 20R board layout Expantion connectors and the PCI to PCI bridge are mounted only on the MIDAS 50 50R mother board MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 3 t 01m p mmm h SPACER x50 5 0 MEZZO PEA e fpc NEN MS 52 BI o en ur eel e ys a1 42 24 E
8. DE 43 X Side Register Descriptions m 44 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Table 36 PXB X side CSR Registers Miscellaneous PXB Information Configuration Serial EEPROM e Intypical P2P applications the configuration PROM is normally used only by the primary PXB Secondary PXBs are set up from the host using config cycles type 1 through the primary PXB e Inan embedded application using a fixed predetermined address map where no off the shelf POST initialization code is running all PXBs may be initialized almost completely from the configuration PROM The only bit field which must be set is the Routes to Primary bit in the Miscon register 0x410 e All configuration registers inside the PXB may be initialized from either side of the chip e In order for a primary PXB to do Typel to Type0 configuration operations or virtual Typel to Type0 operations accessing CSRs in secondary PXBs the lookup tables for config ops in the PROM must be initialized The contents of these tables are used to index the route table for configuration type 1 accesses The tables are located in PROM address ranges 0x80 0xBF and 0x220 gt PCI to RACEway Addressing e Three bits of PCI address are used to index the Route Table This table holds the routes used to set up a connection through the crossbars MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 45 46 e With Big Mem enabled the least significant p
9. E RAI described in the VMEbus Slave Image section is also utilized to set up PCI slave images in the examples below PCI Target Enable Memory amp I O Space In addition to the configuration registers for the PCI slave images two control register bits are essential for mapping PCI bus cycles to VMEbus cycles through the Universe The PCI Target Memory Enable MS and Target IO Enable IOS bits located in the PCI CSR register offset 0x004 must be set to allow the Universe to respond to PCI memory and I O commands MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 27 VMEbus PCI bus UNIVERSE 0x000000 VMEbus A24 all AM A VME Register codes Access Image 0x000FFF 0x001000 0x00000000 VMEbus A24 D16 PCI Slave Image supervisor data 0 PCI bus I O Space 0x001FFF 0x0000FFF 0x20000000 0x10000000 VMEbus A32 D32 non privileged data allow PCI E Image PCI bus Memory Space BLT Ox3FFFFFFF Ox2FFFFFFF 0x0000 0000 0x4000 0000 VMEbus A32 D64 non privileged data allow ME ques RelbusMem Space BLT Ox1FFF FFFF Ox5FFF FFFF PCI Slave Image 3 not used Figure 10 Configuration Example for PCI Slave Images PCI Slave Image 0 In this configuration example the PCI Slave Image 0 is set up to map PCI VO Space transactions in the address range 0x0 OxFFF to A24 D16 VMEbus cycles in the address range 0x1000 0x1FFF 28 MIDAS 20 20R amp MIDAS 50 50R USE
10. Enabe SERR SERR Enable REEN ww o eee coen 0000 Table 24 PCI Command Register PCI Status Register Register Name PSR Size 16 bits Offset 0x06 Bits Function RESERVED 000000 PSR Description Name Type Reset Function State Ces xw aree sme x 9 sese ee eae om xw s merespemd Table 25 PCI Status Register MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Secondary Status Register Register Name SSR Size 16 bits Offset 0x1E Bits Function RESERVED 000000 SSR Description State De RW Detected parity error Detected parity error 0 parity error Lm oe essi wes xw p eewMeenen ome ww EEN EE ome RO Seme es Woes wm ww v lbs pes Table 26 Secondary Status Register Memory Mapped I O Base Address Register Register Name MIOBAR Size 16 bits Offset 0x20 MIOBA 31 24 MIOBA 23 16 0000 MIOBAR Description Name Type Reset Function State MIOBA R W Base Address inclusive for Memory Mapped I O 20 Isb assumed 0 Alignment IMB Table 27 Memory Mapped VO Base Address Register MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 37 38 Memory Mapped I O Limit Address Register Register Name MIOLAR Size 16 bits Offset 0x22 158 8 MIOLA 31 o MBA fk MIOLA 23 16 0000 MIOLAR Description Name Type Reset Function State MIOLA R W Base Limit inclusive for Memory Mapped I O 20 Isb
11. G e m e un una JSt 82 14 a 4 0 SERIAL NO o H 0 e g P MEZZ x50 MIDAS 50 mother board Figure 2 MIDAS 50 MEZZ x50 SPACER x50 MIDAS 50 mother board MIDAS 20 20R VMEbus Universe Figure 3 MIDAS 20R Block Diagram The MIDAS 20 is a PMC carrier for VMEbus The MIDAS 20R option contains the PCI to RACEway interface chip the PXB The MIDAS 20 20R with the PCI to PCI bridge and the expantion connectors mounted on it provides the mother board for the MIDAS 50 50R 4 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE MIDAS 50 50R MIDAS 50R mother board MEZZ x50 i PMC 1 PMC 2 PMC 3 PMC 4 PMC 5 VMEbus i Universe Il PCI bus PCI bus i Ter PCI secondary A RACEWAY es Figure 4 MIDAS 50R Block Diagram The MIDAS 50 is a PMC carrier VMEbus board which supports up to five PMC slots The MIDAS 50R option contains the PCI to RACEway interface chip the PXB The MIDAS 50 occupies two VMEbus slots MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Installation Board Precautions The circuit boards are sensitive to static electricity and can be damaged by a static discharge Always wear a grounded anti static wrist strap and use grounded static protected work surfaces when touching the circuit boards and their components When the board is not installed always keep it in its static protective envelope Unpacking MIDAS 20 20R MIDAS 50 50R All precautions desc
12. IOWR Size 8 bits Offset 0x42 IOSHIFT MIOSHIFT MWR Description Name Type Reset Function State 42 IOSHIFT R W I O window shift Selects which address bits are used to index page ram during I O accesses Bits Big Window Small Window 0000 23 20 16 MB 1 MB 0001 22 19 8MB 512 KB 0010 21 18 4MB 256 KB 0011 20 17 2MB 128 KB 0100 19 16 1 MB 64 KB 0101 18 15 512 KB 32 KB 0110 17 14 256 KB 16 KB 0111 16 13 128 KB 8KB Ixxx 15 12 64 KB 4KB MIOSHIFT R W Memory Mapped I O window shift Selects which address bits are used to index page ram during memory mapped I O accesses 0000 0001 0010 0011 0100 0101 0110 0111 lxxx 21 18 4 MB 256 KB Table 34 IO MIO Window Register Bits 29 26 28 25 27 24 26 23 25 22 24 21 23 20 22 19 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Big Window 1 GB 512 MB 256 MB 128 MB 64 MB 32 MB 16 MB 8MB Small Window 64 MB 32 MB 16 MB 8 MB 4 MB 2MB 1 MB 512 KB PXB Misc Register Register Name PMR Size 8 bits Offset 0x43 PMR Description Name Type Reset Function State UNAL R W Unaligned 1 unaligned 0 aligned For most normal operations aligned operation is used NAL R W No auto load Used to control if the PCI mask registers are auto loaded for each RACEway to PCI transaction Should always be 0 for secondary PXBs PPAGE DOR Primary Page Read only Table 35 PXB Misc Register MIDAS 20 20R amp MIDAS 50 50R USER s GUI
13. PCI bus 0 0x000000 DEC21052 VMEbus A24 all AM gt VME Register codes Access Image Config Space IDSEL AD 20 mise EN gt PCI Configuration OXOOOFFF wv Registers 0x0000 0000 N VMEbus A32 supervisor gt VME Slave Image gt PCI bus Config Space 0x0001 0000 AM codes 0 Cfg Cycle type 1 PCI bus Config Cycle type 1 gt to Cfg Cycle type 0 PCI bus Config Cycle typ OxOFFF FFFF Conversion 0x0001 FFFF VME Slave Image 0x7000 0000 ma EE 1 i Upstream T Memory Space i i Inverse decoding Ox7FFF FFFF ME 0x0000 0000 Ox6FFF FFFF 0x4000 0000 0x6000 0000 oe 0x7000 0000 TN 0x7000 0000 4 gt PCI bus Mem Space N Downstream PCI bus Mem Space VMEbus A32 all AM Memory Space codes Write posting and VME Slave Image PCI bus Memory Space Image read prefetching enabled 2 EA Ox7FFF FFFF aa Ox7FFF FFFF bu m 0x8000 0000 ME sr EE HA 0x8000 0000 Ox9FFF FFFF r JMTEFEEERE _ Upstream Memory Space i VME Slave Image OxFFFF FFFF el MEE k OxFFFF FFFF 3 not used M E Figure 11 Configuration Examples for the PCI to PCI Bridge Universe Initialization Sequence By performing the list of cycles shown in the table below the Universe is set up according to the address mapping for this configuration example MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 31 Write from VME PCI D
14. R s GUIDE Write from VME PCI Data Base Address set to 0x0000 0000 Bound Address set to 0x0000 1000 D 0x0010 0000 to A 0x00010C 0x0000 1000 Translation Offset set to 0x0000 1000 D 0x0110 4180 to A 0x000100 0x8041 1001 Enable Image VAS A24 VDW D16 LAS I O Space PGM data SUPER supervisor other options disabled D This column shows write data for configuration from PCI Table 15 PCI Slave Image 0 Setup PCI Slave Image 1 In this configuration example the PCI Slave Image is set up to map PCI Memory Space transactions in the address range 0x1000 0000 0x2FFF FFFF to A32 D32 VMEbus cycles in the address range 0x2000 0000 0x3FFF FFFF D 0x0001 82C0 to A 0x000114 0xC082 0100 Enable Image VAS A32 VDW D32 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed This column shows write data for configuration from PCI Table 16 PCI Slave Image 1 Setup PCI Slave Image 2 PCI Slave Image 2 is set up to map PCI Memory Space transactions in the address range 0x4000 0000 0x5FFF FFFF to A32 D64 VMEbus cycles in the address range 0x0000 0000 0x 1 FFF FFFF Write from VME PCI Data Base Address set to 0x4000 0000 D 0x0000 00C0 to A 0x000134 0xC000 0000 Translation Offset set to 0xC000 0000 D 0x0001 C2C0 to A 0x000128 0xC0C2 0100 Enable Image VAS A32 VDW D64 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed D This column shows writ
15. User s Manual MIDAS 20 20R MIDAS 50 50R PMC Carriers for VMEbus and RACEway Valid for MIDAS 20 PCB C Rev 1 7 P2 VO VMEbus P2 VO MIDAS 20 MIDAS 50 A The information in this document is subject to change without notice and should not be construed as a commitment by VMETRO While reasonable precautions have been taken VMETRO assumes no responsibility for any errors that may appear in this document Copyright VMETRO 2000 This document may not be furnished or disclosed to any third party and may not be copied or reproduced in any form electronic mechanical or otherwise in whole or in part without prior written consent of VMETRO Inc Houston TX USA or VMETRO ASA Oslo Norway UMETRO ii MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Warranty VMETRO products are warranted against defective materials and workmanship within the warranty period of 1 one year from date of invoice Within the warranty period VMETRO will free of charge repair or replace any defective unit covered by this warranty shipping prepaid A Return Authorization Code should be obtained from VMETRO prior to return of any defective product With any returned product a written description of the nature of malfunction should be enclosed The product must be shipped in its original shipping container or similar packaging with sufficient mechanical and electrical protection in order t
16. VO Routing E a EEN INEEN TEE L o o EE EE 10 25 m p T a as s o pw EN I fo p 2 EN m m m af a is a ETE IE ala is TEE ETE IE 53 a m P EN 57 a o e m a a x _ 1 1 1 WS Polla WIL WININITNITNININI NININMOITN RP JTRIrPIrRPIrRi_rRPIrPIRPfRefie J ula lwlnle Nin ljoj w oj o o s5l wc Nv mnm i joljuljo o u 5 co N n jo Ww N Ww N pa A He WS N H H UI NN NEN MEME Eu Ee ee w w N NN N H H e N ND eo N 22 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Appendix III Universe Configuration Examples General Information o Note that the Universe PCI VME Bridge performs byte swapping of the data lanes on all transactions between VMEbus and PCI bus This is also the case for accesses to the internal registers The internal register bank is located on the PCT side of the byte swapping This means that when registers are read or written from the VMEbus all bytes are shuffled compared to the bit numbering used in the Universe User Manual VMEbus Slave Images PCI Master Enable In addition to the configuration registers for the VMEbus slave images one control register bit is essential for mapping VMEbus cycles to PCI bus cycles through the Universe the PCI master enable BM bit located in the PCI CSR register space offset 0x004 This bit is set as a default after power up Some VMEbus Slave Image examples are shown
17. XB chip is only present on the MIDAS 20R 50R model 16 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE For details on setting up interrupt channels please refer to the UNIVERSE II USER MANUAL UNIVERSE INT PMC 1 PMC 2 PMC 3 PMC Z4 PMC Z5 UNIVERSE INT PMC 1 PMC 2 PMC 3 PMC 4 PMC 5 Table 7 MIDAS 20R 50R Interrupt Routing Subtractive Decoding Agent The CR CSR PLD utilizes subtractive decoding in the PCI bus O Space No other PCI devices are therefor allowed to do the same Subtractive decoding in Memory Space may be used Universe Power Up Options A number of power up options are loaded by the Universe after power up or system reset A detailed description of these options is found in the UNIVERSE USER MANUAL The table below shows how they are controlled on the MIDAS MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 17 by VME Register Access Slave Image PPWR SYS VRAI CTL VRAI jumper address size VRAI BS j VME CR CSR Slave Image WR SYS VCSR CTL VCSR TO PCI CSR MAST EN Enabled EN VAS BS LAS TO PCI Slave Image PWR SYS LSIO CTL EN Disabled LAS Mem space VAS A16 LSIO BS BS 0x0 BD 0 Ox IPCI Register Access PWR SYS PCL BS SPACE VO Space IPCI Bus Size RST MISC STAT LCLSIZE Auto ID PWR SYS MISC_STAT DY4AUTO Disabled VME64AUTO AUTO ID jumper BI Mode PWR SYS MISC CTL BI Disabled SYSFAIL Assertion PWR SYS VCSR SET SYSFAIL S FAIL jumper VCSR CLR SYSFAIL Table 8 Universe
18. able 20 Intel 21152 Initialization Sequence After the initialization sequence described in the sections above one 256Mbyte window into the memory space of the secondary PCI bus is set up VME Address Primary PCI Address Secondary PCI Address MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE A32 0x5000 0000 0x5FFF FFFF Mem 0x7000 0000 OX7FFF FFFF Mem 0x7000 0000 Ox7FFF FFFF Table 21 Address map resulting from this configuration example Scan PCI Config Space on MIDAS 50 50R Using VMEbus Slave Image set up and the Intel 21152 set up in this configuration example a VMEbus host can scan the configuration space on the MIDAS 50 50R board by performing the set of read cycles listed below Read from VME host Primary PCI AM 0x0D A 0x0000 2800 0x0001 0000 Read Device ID Vendor ID from PMC module installed in PMC slot 1 AM 0x0D A 0x0000 3000 0x0002 0000 Read Device ID Vendor ID from PMC module installed in PMC slot 2 AM 0x0D A 0x0000 4800 0x0010 0000 Read Byte swapped Device ID Vendor ID from PCI to PCI bridge AM 0x0D A 0x0001 0000 type 1 Read Device ID Vendor ID from PMC module installed in PMC slot 3 AM 0x0D A 0x0001 0800 type 1 Read Device ID Vendor ID from PMC module installed in PMC slot 4 AM 0x0D A 0x0001 1000 type 1 Read Device ID Vendor ID from PMC module installed in PMC slot 5 Table 22 Scanning PCI Config Space on MIDAS 50 50R MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 33 Append
19. ata D 0x0700 8002 to A 0x000004 0x0280 0007 PCI Master Enable bit set this write cycle also sets the PCI target enable bit D 0x0200 E280 to A 0x000F00 0x80E2 0002 VSI 0 Enable Image VAS A32 LAS Config Space PGM both SUPER Supervisor other options disabled VSI 2 Translation Offset set to 0x2000 0000 D 0x0000 F2E0 to A 0x000F28 OxEOF2 0000 VSI 2 Enable Image VAS A32 LAS Mem Space PGM both SUPER both PWEN amp PREN enabled other options disabled This column shows write data for configuration from PCI Table 19 Initialization Sequence for Universe Intel 21152 Configuration Sequence Some basic configuration registers of the PCI to PCI bridge chip must be set up prior to operation of the bridge In this configuration example the primary PCI bus is defined as bus 0 and the secondary bus as bus 1 Write from VME PCI Cycle Result D 0x0700 8002 to A 0x0000 4804 D 0x0280 0007 to Cfg Space A 0x0000 4804 Intel 21152 Enable PCI Target VO and AM 0D Memory space and Master enable D 0x0001 0100 to A 0x0000 4818 D 0x0001 0100 to Cfg Space A 0x0000 4818 Secondary bus number 1 AM 0D Highest downstream bus number 1 D 0x0070 F07F to A 0x0000 4820 D O0x7FF0 7000 to Cfg Space A 0x0000 4818 Downstream address window AM 0D 0x7000 0000 Ox7FFF FFFF 1 This column shows the PCI bus command resulting from the VMEbus access Configuration can also be done directly from PCI 32 bus T
20. ate completely MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE gue inj 9 Figure 6 Step 4 Mount the MEZZ x50 with PMC modules on the MIDAS 50 50R mother board STEP 5 Mount and fasten screws to all metal spacers from the back of the MIDAS 50 50R mother board Take the 5 screws removed in step 1 of this procedure and mount them from the back side of the MIDAS 50 50R mother board through the holes which mate the 5 metal spacers on the MEZZ x50 Fasten all five screws with a suitable screw driver Verify that the screws attaching the metal spacers to the MEZZ x50 are also fastened All screws holding the five metal spacers from both boards must be firmly fastened in order to make the MIDAS 50 50R mechanically stable MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 9 Installation in VMEbus System Slot selection The MIDAS can be installed in any slot in a GU VMEbus chassis as long as the daisy chains for the bus grant and interrupt acknowledge signals are continuous from slot 1 to the slot in which the board is installed If the MIDAS is installed in slot 1 of a VMEbus system it will automatically detect this as specified in the VME64 specification and enable its system controller functions WARNING Do not install the board in a powered system MIDAS 50 Daisy Chain The P1 connector of the MEZZ x50 prov
21. bellow MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 23 VMEbus PCI bus UNIVERSE 0x000000 VMEbus A24 all AM A VME Register codes Access Image 0x000FFF 0x0000 VMEbus A16 supervisor b VME Slave Image AM codes P 0 9 gt PCI bus Config Space Ox4FFF 0x100000 0x02100000 VMEbus A24 all AM codes No write posting or read prefetching PCI gt VME Slave Image PCI bus VO Space Lock of VMEbus RMW 1 enabled 0x023FFFFF Ox3FFFFF 0x4000 0000 0x6000 0000 VMEbus A32 all AM codes Write posting and VME Slave Image PCI bus Memory Space read prefetching enabled 2 Ox7FFF FFFF Ox9FFF FFFF VME Slave Image 3 not used Figure 9 Configuration Example for VMEbus Slave Images VMEbus Register Access Image In this configuration example the VMEbus Register Access Image is set up by use of the DIP switch and jumpers 24 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Locate VRAI in its upper position VME RAI is enabled Locate both of the address size jumpers VME RAI is mapped in A24 address in their upper positions space Set the DIP switch with all switches VME RAI base address is set to pointing down 0x000000 Locate the Auto ID jumper in its lower Disable Auto slot ID protocol position Table 10 VME RAI Setup With the jumper settings described above the Universe will power up in a state where VMEbus accesses with A24 AM codes in the address
22. d on a smooth static protected work surface with the bottom side of the board facing up From the bottom side of the MIDAS 50 50R PCB unscrew the 5 screws holding the metal spacers between the MEZZ x50 and the mother board these screws are located close to the edge of the board in each corner and between the VMEbus connectors Note Don t throw away the screws They are needed later in this procedure Pull the boards carefully apart Use hand force only applied to the two the upper VMEbus connector of both boards If the small SPACER x50 PCB is attached to the MIDAS 50 50R mother board PCB after the separation remove it and mount it on the bottom side of the MEZZ x50 board instead Mount PMC modules 1 and 2 on the MIDAS 50 50R mother board Place the MIDAS 50 50R mother board on a smooth static protected work surface Install PMC module 1 in the lower PMC position Install PMC module Z2 in the upper PMC position Secure PMC modules with screws from the bottom side of the mother board Mount PMC modules 3 4 and 5 on the MEZZ x50 board Place the MEZZ x50 board on a smooth static protected work surface Install PMC module 3 in the lower PMC position Install PMC module 4 in the middle PMC position Install PMC module 5 in the upper PMC position Secure PMC modules with screws from the bottom side of the MEZZ x50 board MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE EEN 0 are
23. dix V PXB Information 34 PXB PCI RACEway Bridge esse sesse see se ee se ee eene nnne ennt nennen enne ge AA Ge ee Ge ee 34 PXB Register Descriptions rerit dre Se eee Rr EE Be BEG Ge eR e red eR Ge a de SeSe Ge de ek nen 35 P Side Register Descriptions eene enne 35 X Side Register Descriptions rient tte neret 44 Miscellaneous PXB Information eese rennen ennemi Ge ek Ge 45 Configuration Serial EEPROM ssssssssesseeeeeeeneneren enne enne nennen 45 PCI to RACEway Addressing essen nee 45 RACEway to PCI Addressing nene 47 PCI to PCI Bridge Operation esse see se ee Ge Re ek ee GR Ge AR Ge Re GR ee GRA Ge AR Ge Re eke ie 47 PXB Initialization Example see ee ae RA GRA Re ee Ee ee ee enne ener nennen 48 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE V General Information This document This document has been prepared to help the customer in the integration of the products MIDAS 20 20R and MIDAS 50 50R in their system The following models are covered by this document MIDAS 20 Dual PMC Carrier for VMEbus MIDAS 20Z Dual PMC Carrier for VMEbus with 5 row DIN connectors MIDAS 20R Dual PMC Carrier for VMEbus with an interface to the RACEway crossbar interconnect MIDAS 50 PMC Carrier for VMEbus capable of carrying up to 5 PMC modules MIDAS 50R PMC Carrier for VMEbus capable of carrying up to 5 PMC modules with an interface to the RACEway crossbar interco
24. e data for configuration from PCI Table 17 PCI Slave Image 2 Setup MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 29 Initialization Sequence By performing the list of cycles shown in the table below the mapping for this configuration example is achieved Write from VME PCI Data D 0x0700 8002 to A 0x000004 0x0200 0007 PCI Target Enable bits set this write cycle also sets the PCI master enable bit if it is disabled ref VMEbus Slave Image section D 0x0110 4180 to A 0x000100 0x8041 1001 L S 0 Enable Image VAS A24 VDW D16 LAS I O Space PGM data SUPER supervisor other options disabled LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed LSI 2 Bound Address set to 0x6000 0000 LSI 2 Translation Offset set to 0xC000 0000 D 0x0001 C2CO to A 0x000128 0xCOC2 0100 LS 2 Enable Image VAS A32 VDW D64 LAS Mem Space PGM data SUPER non priv Posted Write enabled BLT allowed D This column shows write data for configuration from PCI Table 18 Initialization Sequence for PCI Slave Image Config Example 30 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Appendix IV INTEL 21152 Configuration Example The PCI to PCI bridge on the MIDAS 50 50R board is set up by use of PCI configuration cycles A slightly different setup of the VMEbus Slave Images in the Universe is used compared to previous configuration examples EG Primary PCI bus Pe ira u us UNIVERSE
25. elow both RACEway jumpers are removed during normal operation No EEPROM When the No EEPROM jumper leftmost RACEway jumper is removed the PCI RACEway bridge chip loads its internal registers from a serial EEPROM This setting should always be used except for cases where the PROM is blank or corrupted If the PROM is corrupted and this jumper is removed the PCI RACEway bridge may reset to a state which causes the MIDAS board in worst case the entire system to hang If the No EEPROM jumper is inserted the PCI RACEway bridge reset state is independent of the PROM contents This setting is normally used for the initial programming of the PROM or if the board is plugged into a non RACEway slot Note that before programming the PROM the PXB must be set in bridge mode RACEway Inserted PXB registers not loaded from EEPROM RACEway Removed PXB registers loaded from EEPROM For more information about this chip and some configuration examples please refer to Appendix IV 14 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Reset from X When the Reset from X jumper rightmost RACEway jumper is removed the PCI RACEway bridge receives reset from PCI bus i e MIDAS reset circuitry and drives reset to the RACEway interlink This setting should always be used Inserting this jumper may be destructive for the MIDAS board and is likely to Gron cause system malfunction H g Removed This se
26. em Table 37 PXB Route Format PXB Return Route Format MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Big Address PXB Return Route Description Return Routes Concatenated three bit route codes used in the response of split RACEway transactions one three bit field per hop Return Route codes 111 Port A 110 Port B 101 Port C 100 Port D 011 Port E 010 Port F 001 Adaptive Route E first 000 Adaptive Route F first If Split Disable in the route is set the return route is not used BigAddress In BigMem Mode a number of bits number is depending on prefetchable memory window size from this field replaces the most significant address bits when going from PCI into RACEway Bit 0 of this field replaces the least significant bit used to index the page table The most significant bit replaced is always bit 27 of the PCI address With 256MByte windows no bits are replaced If BigMem Mode is not used always the case for P2P applications this field is not used Table 38 PXB Return Route Format RACEway to PCI Addressing PCI Mask registers one for each address window are always used by secondary PXB to generate the high order PCI address bits All bits from the least significant 1 and up to 3 are used as PCI bus addresses These registers are normally loaded automatically from the BARs for each transaction i e as long as the no autoload bit in register 0x40 is cleared The regist
27. ener GE Re Ge Re GR nennen 20 Appendix I MIDAS 20 50 PMC VO Routing 21 Appendix II MIDAS 20Z PMC VO Routing 22 Appendix Ill Universe Configuration Examples 23 General Information ie ee ee ee AR GR RR RR GRA eerie enne nennen nnne nene nr ee nennen nnns 23 VMEbus Slave Images sess Ee nnns 23 PCI Master Enable ESE Es es Ee EE E cease ee Ee ee Gee EN es 23 VMEbus Register Access Image ies tenete RS GES ke GN Ge ie BE erred 24 VMEbus Slave Image O ese ee ae see Gee Gee ee ee ee Re Re Re RR enirn nnn Gee Gee ee 25 VMEbus Slave Image 1 ees esse ese ee ae ee ae Gee nennen nennen enne nnne 25 VMEbus Slave Image 2 edicere ede Re etr be ene gee bee dere e ERA See RE ee 26 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Initialization Sequerce eerie cos SEER ASE KEER GR e re eke EER rna a 27 PEL Slave lima es EE IS EE De IE iiu Se ee die Re Oe teret o Fus RIP De Pene erede si eg bu 27 PCI Target Enable Memory amp VO Space seen 27 PCI Slave Ima AE EE N re tere eee ees teils deser 28 PCI Slave limage D ae 29 PCI Slave Image RE OE EE TR ERR REDDERE ERR 29 Initialization SequeliCe cotto veo roit erts Pa erat evi Er eg ies ke 30 Appendix IV INTEL 21152 Configuration Example 31 Universe Initialization Seguence iese see ses Ge ee AR Ge Re nennen 31 Intel 21152 Configuration Sequence 32 Scan PCI Config Space on MIDAS 50 50R sse 33 Appen
28. er is not used by primary PXB PCI to PCI Bridge Operation Both a memory mapped I O window and a prefetchable memory window must be defined in order to make the bridge operation from secondary to primary side work correctly BAR and limit registers of the secondary PXB are set to values corresponding to the address space on their PCI side PXB will calculate the size of the big window BAR limit on primary PXB based on the BAR and window size Widow sizes set in 0x40 must be the same for primary and secondary PXBs MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 47 PXB Initialization Example Below is an example on how to setup registers of two PXB chips so that they provide a PCI to PCI bridge across a RACEway interlink ILK4 The PXB in the RACEway slot A is reffered to as the primary PXB and the PXB in the slot B as the secondary PXB The following example creates an 8 Mbytes window at PCI Memory space addresses 0x80000000 0x807fffff from the primary to the secondary side i e the primary PXB will respond to address cycles between 0x80000000 0x807fffff and forward them to the secondary side The secondary PXB will forward transactions in address ranges 0x0 Ox7FFFFFFF and 0x81000000 OXFFFFFFFF to the primary side The initialization values may easily be programmed into the PXB using PCI Configuration Type 0 cycles The offsets for each register is given PCI to PCI Bridge Configuration Space Header Registers of the P
29. ides a daisy chain bypass for the signals BG 3 0 and IACKIO No action is therefor required to keep the daisy chain continuous through the MIDAS 50 50R board Power consumption Model Typical current Test condition consumption 5V M20 0 5A Board idle 1 0A Board active PM20R 1A Board idle 1 8A Board active Table 1 Power consumption PMC current supply capabilities 10 The MIDAS M20x has the ability to power both 5 and 3 3 Volt PMC modules with the following limitations Voltage Maximum current Additional information 23 3 DAA Max total current 5 Supplied from VME Refer to PMC standard backplane Table 2 Current supply Capabilities D Note as 3 3V is supplied by a linear regulator mounted on the MIDAS additional current drawn from 3 3V has a direct effect on the 5 Volt power consumed P 3 3 Volt capabilities available on MIDAS 20 with ECO level C 3 or higher MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Configuration Switch amp Jumpers Q Q The VME PCI bridge on the MIDAS 20 20R and MIDAS 50 50R boards has a number of configuration registers which need to be initialized before the bridge is fully operational This initialization is done by a host processor residing either on VMEbus or on the local PCI bus This host is normally on VMEbus The switch and jumpers cannot alone be used to initialize the MIDAS board They are used to define how base address
30. information MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 19 Configuration ROM 20 MIDAS Configuration ROM CROM Offset 03 VME CR CSR Space Offset Description itin Checksum Eight bit 2s complement binary checksum CR bytes 03 7F Length of ROM to be checksummed MSB Length of ROM to be checksummed NMSB Length of ROM to be checksummed LSB CR Data access width 0x81 D08 EO every forth byte CSR Data access width 0x81 D08 EO every forth byte CR CSR Space Specification ID 0x01 VME64 1994 version O ME ER NND ETE ELEM E or 49 C UsdwoidenifyvatiacR o R Usedt Meng vag CR 0 24 bit IEEE Assigned Manufacturers ID 6 0x006046 VMETRO ME oo ME NE CN Oo m Board ID VMETRO Assigned 0x00100020 MIDAS 20 Revision ID VMETRO Assigned Example 0x0000C001 PCB Rev C ECO level 1 ECO level Pointer to null terminated ASCII string Revision ID VMETRO Assigned 0x000000 No string Reserved for future use Program ID Code 0x01 No program ID ROM only Table 9 MIDAS 20 20R and MIDAS 50 50R Configuration ROM 5F 7B MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Appendix I MIDAS 20 50 PMC I O Routing The I O connectors for PMC slots on the MIDAS 20R and the mother board of the MIDAS 50R are not mounted and P2 rows A and C are used for the RACEway AE Me aac MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 21 Appendix Il MIDAS 20Z PMC
31. ix V PXB Information PXB PCI RACEway Bridge 34 The PXB is a high performance RACEway to PCI bridge developed by Mercury Computer Systems It features Bridges a 32 bit 33MHz PCI bus with a 32 bit 40MHz RACEway switching fabric Compliant to Rev 2 1 PCI local bus specification including delayed operations Compliant to Rev 1 0 PCI to PCI Bridge specification Bridges up to sixteen 32 bit 33MHz PCI busses Able to sustain up to 125MB sec with large memory write transfers and 100MB sec with large memory read transfers Integral FIFOs for write posting to maximize bandwidth utilization MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE PXB Register Descriptions P Side Register Descriptions If no valid PROM is present the PXB powers up in endpoint mode but should always be used in bridge mode This is done by clearing bit 6 in register 0x40 oseaan voaa w hss code an o 9 Low p ome oes cm ps Prefetchable Memory BAR ie a Mode _ EIC see ed EG seg sme seme RE s Pet Memory tin eemo Er N P 28 N Ii oni owo o E a E PXB Misc TO MIO Shift Memory Window PXB Bridge Control Memory Internal Base Misc BAR Size Mailbox Vector ER Table 23 PXB P side CSR Registers MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 35 36 PCI Command Register Register Name PCMDR Size 16 bits Offset 0x04 PERR EN PCMDR Description State SERR EN EN SRREN RW 0 SERR
32. lation of PMC Modules se ee ee RA GRA GR Re ee ee Re Re GR Re RR RA nnne nnne nnns 6 Assembly Procedure for MIDAS SO SOR ee ee ee ee ee Re RR RR RA RA GRA Gee ee ee ee nennen 6 Installation in VMEbus System see ee ee se ee Ge ek GR Ge Re GR ee enne GR Re GR ge AA Ge Re Ge ee 10 Slot selection uoce OE OE EN 10 MIDAS 50 Daisy Chain esse esse see se Ge AR Ge AR GR ee GRA Ge AR Ge Re GR ee Re Re GRA Ge eene 10 Power consumption RR 10 PMC current supply capabilities essent 10 Configuration Switch amp Jumpers sa ee Re Re ee ee ee ee enne enne enne 11 AMO Slot ID oe iterari M E EO rre rer 11 VMEbus Switch amp Jumper Description sesse se ee ee ee Re GR Re GR Re GR Re RA GRA ee ee 11 RACEway Interface Jumper Description esse sesse se se se ek Ge ek GR ee GR Ge AR Ge Re ek ee 14 Functional Description 16 PCI Bus IDSEL Generation esse ese se ese see se ee Se ee Be ee enitn AA Se GO Be note seni daens se ee Se nete bee se 16 Interrapt ec lE 16 Subtractive Decoding Agent eei t ie he een dnd 17 Universe Power Up Options ccccecccssessseeseeesceeeceeeeseceaeceaeenaecaaecaeecaeeeaeseeeseesseseaeeeseenaeenaees 17 HEU AC MEO DD DT LT ILI 18 Register Access from VMEDUS sssssssesseeeeeeeeenen enne 18 Register Access from PCI Bus cese ette titre tere eee edenda 19 Repister Desceriplionis c eoe tie etta NEE EE N 19 Configuration ROM ee ee ee Re RR RA GRA
33. mage 2 is set up to map A32 accesses in the address range 0x4000 0000 0x 7FFF FFFF from VMEbus to Memory Cycles on the PCI bus with PCI addresses starting from 0x6000 0000 Write posting and read prefetching is enabled Write from VME PCI Data Base Address set to 04000 0000 Bound Address set to 0x8000 0000 D 0x0000 0020 to A 0x000F34 0x2000 0000 Translation Offset set to 0x2000 0000 D 0x0000 F2E0 to A 0x000F28 OxEOF2 0000 Enable Image VAS A32 LAS Mem Space PGM both SUPER both PWEN amp PREN enabled other options disabled D This column shows write data for configuration from PCI Table 13 VME Slave Image 2 Setup 26 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Initialization Sequence By performing the list of cycles shown in the table below the mapping for this configuration example is achieved D 0x0200 E080 to A 0x000F00 Ox80EO 0002 VSI 0 Enable Image VAS A16 LAS Config Space PGM both SUPER Supervisor other options disabled D 0x4100 F180 to A 0x000F14 Ox80F1 0041 VSI I Enable Image VAS A24 LAS I O Space PGM both SUPER both LLRMW enabled other options disabled D 0x0000 F2E0 to A 0x000F28 OxEOF2 0000 VSI 2 Enable Image VAS A32 LAS Mem Space PGM both SUPER both PWEN amp PREN enabled other options disabled This column shows write data for configuration from PCI Table 14 Initialization Sequence for VMEbus Slave Image Config Example PCI Slave Images The VM
34. nnect During this document the generic name MIDAS refers to all models whenever their common features are described Conventions used in this document Symbols e The following section describes conventions used in this document Meaning The STOP symbol indicates a section of critical importance Overlooking this information may cause damage to the MIDAS and or other equipment Indicates important but not crucial information Still you should take notice if you want to use all capabilities built into your MIDAS MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Related Documents 9 This document does not include detailed information about the Universe IT VME to PCI bridge chip the 21152 PCI to PCI bridge and the PCI to RACEway interface chip the PXB A majority of the control registers and a large part of the complexity of the products is implemented in these chips The documents related to these chips contain essential information for understanding the products The following documents can be provided directly from the chip vendor also available on the internet Tundra Semiconductor Corp UNIVERSE II USER MANUAL http www tundra com INTEL 21152 PCI TO PCI BRIDGE http www intel com design bridge datasheets Information should also include updated information on device errata A copy of the documents listed above along with the PXB BRIDGE SPECIFICATION can be obtained directly from VMETRO MID
35. nternal registers at power up Unless the Auto Slot ID protocol which uses its MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 11 own slave image is used this slave image must be enabled to allow initialization from VMEbus se 4 ODE DOWN VME Register Access Image DISABLED n N 123 ug zd UP VME Register Access Image ENABLED TAE Bg Ug VME Register Access Image address size The VME Register Access Image can accept A16 A24 or A32 AM codes depending on the positioning of these two jumpers At power up this slave image accepts AM codes for Supervisor User Data and Code L v UU d thet UP UP VME Register Access Image A24 n d 1 23 z ais VE ng Sc DOWN DOWN VME Register Access Image A32 Us E EE aT 1 AE UP DOWN VME Register Access Image A16 Us 12 VME Register Access Base Address The DIP switch is used to define the base address for the VME Register Access Image The size of this image is fixed to 4KB MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE BASE ADDRESS VRAI Addr Size BS 31 24 BS 23 16 BS 15 12 From switch 4 MSB From switch Table 3 VRAI Base Address Definition From switch not used for A16 Most Significant Bit MSB J j EL id Figure 8 DIP Switch Details VME
36. o maintain warranty This warranty assumes normal use Products subjected to unreasonably rough handling negligence abnormal voltages abrasion unauthorized parts replacement and repairs or theft are not covered by this warranty and will if possible be repaired for time and material charges in effect at the time of repair Any customer modification to VMETRO products including conformal coating voids the warranty unless agreed to in writing by VMETRO If boards that have been modified are returned for repair this modification should be removed prior to the board being shipped back to VMETRO for the best possibility of repair Boards received without the modification removed will be reviewed for repairability If it is determined that the board is not repairable the board will returned to the customer All review and repair time will be billed to the customer at the current time and materials rates for repair actions VMETRO s warranty is limited to the repair or replacement policy described above and neither VMETRO nor its agent shall be responsible for consequential or special damages related to the use of their products Limited Liability VMETRO does not assume any liability arising out of the application or use of any product described herein neither does it convey any license under its patent rights nor the rights of others VMETRO products are not designed intended or authorized for use as components in systems intended to support or su
37. ortion of the Return Route holds the most significant bits of the RACEway address Bit 0 of the Return Route will replace the least significant PCI bus address bit used to index the Route Table The most significant bit replaced is always bit 27 of the PCI address Big Mem is only used for prefetchable memory space Big Mem is not used for P2P applications Configuration Cycles e Lookup table in EEPROM is used to index the route table for each PCI bus device PXB Route Format 31 24 24 BP RM ERE 15 8 8 Routes EM 0 BigMem Priority B cast Splitable PXB Route Description Routes Concatenated three bit route codes one per crossbar hop Route codes 111 2 Port A 110 Port B 101 Port C 100 Port D 011 Port E 010 Port F 001 Adaptive Route E first 000 Adaptive Route F first Example Route entry 0xFACx xxxA is used to route a transfer through 4 crossbars ports A B C and D with splitable bit set and priority 01 BigMem Enables addition of high order address bits when addressing RACEway from PCI Not to be used for P2P operation Split Disable A 1 disables split transactions on RACEway Split should always be enabled Priority Two bit priority code Ref RACEway specification Note Never use 11b as priority for I O space Broadcast Set for broadcast operations on RACEway In broadcast mode the meaning of rout codes change Ref RACEway specification Requires split disabled and no BigM
38. range 0x0 OxFFF will map into Universe registers The VME RAI will be utilized to set up the VMEbus slave images described below VMEbus Slave Image 0 In this configuration example the VMEbus Slave Image 0 is set up to map A16 supervisory accesses in the address range 0x0 Ox4FFF from VMEbus to Configuration Cycles on the PCI bus Write from ME PCI Data Base Address set to 000000 Bound Address set to 0s00s000 D 0x0000 0000 to A 0x000F0C 0x0000 0000 Translation Offset set to 0x000000 D 0x0200 E080 to A 0x000F00 0x80E0 0002 Enable Image VAS A1G LAS Config Space PGM both SUPER Supervisor other options disabled This column shows write data for configuration from PCI Table 11 VME Slave Image 0 Setup VMEbus Slave Image 1 The VMEbus Slave Image 1 is set up to map A24 accesses in the address range 0x100000 0x3FFFFF from VMEbus to I O Cycles on the PCI bus with PCI addresses starting from 0x02100000 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 25 Write from VME PCI Data Base Address set to 0100000 Bound Address set to 400000 D 0x0000 0002 to A 0x000F20 0x0200 0000 Translation Offset set to 0x2000000 D 0x4100 F180 to A 0x000F14 OXSOF10041 Enable Image VAS A24 LAS I O Space PGM both SUPER both LLRMW enabled other options disabled Table 12 VME Slave Image I Setup D This column shows write data for configuration from PCI VMEbus Slave Image 2 VMEbus Slave I
39. ribed above must be taken when unpacking the product from its shipping container s Verify that no damage has occurred in the shipment Verify that all Items are present e One MIDAS 20 20R board e This manual e One dual slot VMEbus plug in unit consisting of One MIDAS 50 50R mother board One MEZZ x50 board One SPACER x50 board Five metal spacers e This manual Installation of PMC Modules The MIDAS 20 20R and MIDAS 50 50R are shipped with PMC filler panels mounted in the front panel They act as EMC shielding in unused PMC positions Before installing a PMC module the filler panel s must be removed This is done by pushing them out from the back side of the front panel Please refer to assembly procedures below for further instructions on the installation of PMC modules Assembly Procedure for MIDAS 50 50R The MIDAS 50 50R is a dual slot VMEbus board which mates the backplane connectors in two neighbor slots The MIDAS 50 50R module can handle the insertion and extraction forces applied when installing or removing it from the backplane However this requires that the assembly procedure described in this section is followed WARNING The MIDAS 50 50R boards may be destroyed during insertion or extraction from a VMEbus system if this procedure is not followed MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE STEP 1 STEP 2 STEP 3 Dismount MEZZ x50 board from MIDAS 50 50R board Place the MIDAS 50 50R boar
40. rimary PXB 0x0 0x0 0x00030100 0x04800111 0x00000010 0x80f08000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000100 0x10880826 0x00000000 0x0000f773 SOc 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 48 MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE Route Table for the Primary PXB Ox 0000083 Ox c0000000 Ox 0000084 Ox c0000000 Ox 0000085 Ox c0000000 Ox 0000086 Ox c0000000 Ox e0000087 Ox a0000000 Ox 0000088 Ox 20000000 Ox e0000089 Ox a0000000 Ox e000008a Ox 20000000 Ox e0000000 Ox 80000000 Ox 0000000 Ox 80000000 PCI to PCI Bridge Configuration Space Header Registers of the Secondary PXB MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 49 50 E fOe 0x00000000 Route Table for the Secondary PXB MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 51
41. stain life or for any application in which failure of the VMETRO product could create a situation where personal injury or death may occur Should Buyer purchase or use VMETRO products for any such unintended or unauthorized application Buyer shall indemnify and hold VMETRO and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that VMETRO was negligent regarding the design or manufacture of the part USA VMETRO Inc 1880 Dairy Ashford Suite 535 Houston TX 77077 USA Tel 281 584 0728 Fax 281 584 9034 Email info vmetro com Europe Asia VMETRO asa Brynsveien 5 N 0667 OSLO Norway Tel 47 2210 6090 Fax 47 2210 6202 Email info vmetro no http www vmetro com MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE iii Contents General Information 1 MISSA ele ies oo N DE EE EE EE EE EE EE ER EE 1 Conventions used in this document IRL IEEE e ED HN Ge GE ERE EE Eee NEE ER ER Ee 1 Related Documents AR EO OR shee i Eene 2 Product Overview 3 MIDAS OOR EE N EER OE EE N EE EE EE OR 4 MIDAS 50 50R RE EE EE EE HERE 5 Installation 6 Board Precautions 5 N EO IS E ota o RETURN URELHU VEL REEEURE 6 Unpacking c E 6 Instal
42. tting should always be used MIDAS 20 20R amp MIDAS 50 50R USER s GUIDE 15 Functional Description PCI Bus IDSEL Generation PCI bus uses a separate address space for initialization called Configuration Space This address space uses a geographic addressing signal IDSEL to select target for all transactions The standard way of assigning IDSEL to PCI devices amp boards is to connect the IDSEL pin of each device board to a unique AD bit This is also how IDSEL is generated on MIDAS The table below shows IDSEL assignments CONFIG CYCLE FOR PCI CONFIG CYCLE oxYYZz280o oxYYzzaooo _ve rcierince appr oxox O ZZ PCI Bus Number as defined in Universe MAST CTL register YY VME base address for slave image Table 4 IDSEL Assignments for Primary PCI Bus PCI DEVICE BOARD IDSEL PCI ADDRESS FOR VME BASE ADDRESS CONFIG CYCLE FOR PCI CONFIG CYCLE PMC 3 sAD 16 0x00010XXX OxYYWW 0000 PMC 4 sAD 17 0x00020XXX OxYYWW 0800 PMC 5 sAD 18 0x00040XXX OxYYWW 1000 WW PCI Bus Number for secondary bus as defined in the PCI to PCI bridge YY VME base address for slave image Table 5 IDSEL Assignments for Secondary PCI Bus on MIDAS 50 50R Interrupt Routing The VME PCI bridge provides eight bi directional interrupt pins to the local bus interface Their routing to PMC interrupt pins is shown in the tables below The P2P bridge is only present on the MIDAS 50 50R mother board The P
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