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ADSP-21065L DSP Microcomputer Data Sheet

1. t 2ND BIT DT LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK tuorsen q TFS lt lt gt 2ND BIT DT Figure 22 External Late Frame Sync Frame Sync Setup gt 2 34 REV C ADSP 21065L Test Access Port and Emulation Parameter Min Max Unit Timing Requirements trck TCK Period tck ns TDI TMS Setup Before TCK High 3 0 ns TDI TMS Hold After TCK High 3 0 ns tssys System Inputs Setup Before TCK Low 7 0 ns tusys System Inputs Hold After TCK Low 12 0 ns trrstw TRST Pulsewidth 4 ns Switching Characteristics tpTDo TDO Delay from TCK Low 11 0 ns tpsys System Outputs Delay After TCK Low 15 0 ns NOTES ISystem Inputs DATA 9 ADDR2 oo RD WR 5815 SW HBR HBG CS DMAR DMAR ID DROx DR1x RCLK0 RCLKI 50 51 RFSO RFS1 BSEL BMS CLKIN RESET SDCLK RAS CAS SDWE SDCKE EVENTx System Outputs ADDRz3 0 MS3 0 RD WR ACK SW HBG REDY DMAGI DMAG2 CPA FLAG PWM_EVENTx DTOx DT1x TCLK1 RCLK1 0 TFS1 RFS0 RFS1 BMS SDCLK0 SDCLK1 DOM SDA10 RAS CAS SDWE SDCKE BM XTAL TCK tstap
2. 13 00 00000000000000 F BSC K L GE TOP VIEW DETARA 155 13 00 BSC BOTTOM VIEW 0 75 0 70 0 65 EI d 3 1O 1 10 NA O 0 60 1 00 070 020 030 0 90 0 60 MAX BALL 0 35 0 50 COPLANARITY BALL SEATING PLANE DIAMETER DETAIL DETAIL B NOTES 1 THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0 30 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 2 THE ACTUAL POSITION OF EACH BALL IS WITHIN 0 10 OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID 3 DIMENSIONS COMPLY WITH JEDEC STANDARD MS 034AAE 1 4 CENTER DIMENSIONS ARE NOMINAL Revision History Location Page 6 03 Data Sheet changed from REV B to REV C Edit to GENERAL DESGRIPTION kwa Aid din aL Rae E 3 Removal of overbar from DOM 252259 e Universal Edit to POWER DISSIPATION ADSP 21065L equations above Table 13 Addition to ORDERING GUIDE 5 2c and gad dalle wanted E RU a dune CR GR RR a 44 Update to OUTLINE DIMENSIONS sa d da ERR HERRERA GU paw od 41 44 44 REV C 00172 0 6 03 PRINTED IN U S A
3. Xk 00 095 lt tssys tusys gt INPUTS AWA X tpsvs dit oo aon Figure 23 JTAG Test Access Port and Emulation REV 35 ADSP 21065L OUTPUT DRIVE CURRENT 80 60 3 6V 40 C _ _3 1v 85 C__ 40 3 3V 25 C lt 20 3 1V 100 0 20 3 1V 100 C 40 3 3V 425 C7 5 40 C 8 60 o 80 1 85 C 1 VoL 100 120 0 50 100 150 20 250 3 00 3 50 SOURCE VOLTAGE V Figure 24 Typical Drive Currents TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they stop driv ing go into a high impedance state and start to decay from their output high or low voltage The time for the voltage on the bus to decay by AV is dependent on the capacitive load Cr and the load current This decay time can be approximated by the following equation CL x AV Ir The output disable time tprs is the difference between tMEASURED and tpgcay as shown Figure 26 The time tygasurep 15 the interval from when the reference signal switches to when the output voltage decays AV from the measured output high or output low voltage tpgcay is calculated with test loads Cr and Ij and with AV equal to 0 5 V Output Enable Time Output pins are considered to be enabled when they have made a transition from a high imp
4. 2 2 5 tscrx 2 2 5 ns Enable and Three State Switching Characteristics tpTENE Data Enable from External TCLK 5 0 ns tpDTTE Data Disable from External RCLK 10 0 ns tpTENI Data Enable from Internal TCLK 0 0 ns tppTTI Data Disable from Internal TCLK 3 0 ns TCLK RCLK Delay from CLKIN 18 0 6 DT ns tpPTR SPORT Disable After CLKIN 14 0 ns External Late Frame Sync tppTLESE Data Delay from Late External TFS or External RFS with MCE 1 MFD 054 10 5 ns tp TENLFSE Data Enable from late FS or MCE 1 MFD 0 4 3 5 ns tppTLSCK Data Delay from TCLK RCLK for Late External TFS or External RFS with MCE 1 MFD 0 12 0 ns tpTENLSCK Data Enable from RCLK TCLK for Late External FS or MCE 1 MFD 0 45 ns NOTES To determine whether communication is possible between two devices at clock speed n the following specifications must be confirmed 1 frame sync delay and frame sync setup and hold 2 data delay and data setup and hold and 3 SCLK width Referenced to sample edge Referenced to drive edge 3MCE 1 TFS enable TFS valid follow tDDTENFS and tpDTLFSE If external RFS TFS setup to RCLK TCLK gt tscrx 2 then tpprrsck and tpTENLSCK apply otherwise tpprirsg and tpTENLFS apply Word selected timing for 125 mode is the same as TFS RFS timing normal framing only 32 REV C ADSP 21065L DATA RECEIVE INTERNAL CLOCK DATA RECEIVE EXTERNAL CLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE
5. 20 REV C ADSP 21065L CLKIN f f tsADRI gt thApRI J i AXXO 4 toack 4 lackTR ACK READ ACCESS s III tupaTwH tspaTwH gt DATA IN Figure 14 Synchronous Read Write Bus Slave REV 21 ADSP 21065L Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP 21065Ls BRx a host processor HBR HBG Parameter Min Max Unit Timing Requirements tHBGRCSV HBG Low to RD WR CS Valid 20 0 36 DT ns tsHBRI HBR Setup Before CLKIN 12 0 12 DT ns tHHBRI HBR Hold Before CLKIN 6 0 12 DT ns tsHBGI HBG Setup Before CLKIN 6 0 ns tinggi HBG Hold Before CLKIN High 1 0 ns tsBRI BRx CPA Setup Before CLKIN 7 0 8DT ns tHERI BRx CPA Hold Before CLKIN High 1 0 ns Switching Characteristics tpHBGO HBG Delay After CLKIN 8 0 2DT ns HBG Hold After CLKIN 1 0 2DT ns DBRO BRx Delay After CLKIN 7 0 2DT ns Hold After CLKIN 1 0 2DT ns CPAO CPA Low Delay After CLKIN 11 5 2DT ns CPA Disable After CLKIN 1 0 2DT 5 5 2DT ns tprpycs REDY 0 0 A D Low from CS and HBR Low 13 0 ns tTRDYHG 0 0 Disable or A D High from 44 0 43 DT ns taRDYTR A D Disable from CS or HBR High 10 0 ns NOTES 1For first asynchronous acce
6. ns tDSAK ACK Delay from RD Low 19 5 24DT W ns Switching Characteristics tpRHA Address Selects Hold After RD High 104 ns tDARL Address Selects to RD Low2 3 0 6 DT ns trw RD Pulsewidth 25 0 26 W ns tRWR RD High to WR RD Low 4 5 6 DT HI ns tRDGL RD High to DMAGx Low 11 0 12 DT HI ns W number of wait states specified in WAIT register X tcx tcx if an address hold cycle or bus idle cycle occurs as specified in WAIT register otherwise 0 H tcx if an address hold cycle occurs as specified in WAIT register otherwise H 0 NOTES Data Delay Setup User must meet tpap or to tprrp or synchronous specification tsspATI The falling edge of MSx SW BMS are referenced 3ACK is not sampled on external memory accesses that use the Internal wait state mode For the first CLKIN cycle of a new external memory access ACK must be valid by tpsax or synchronous specification for wait state modes External Either or Both Both if the internal wait state is zero For the second and subsequent cycles of a wait stated external memory access synchronous specifications tsAckc and tgackc must be met for wait state modes External Either or Both Both after internal wait states have completed DATA XXX DMAG Figure 11 Memory Read Bus Master 16 REV C ADSP 21065L Memory Write Bus Master Use t
7. 4 tparpRH gt 4 tspATDGL DATA FROM EXTERNAL DEVICE TO ADSP 2106x TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY EXTERNAL HANDSHAKE MODE tpGwRL WR lt gt a tpowRH EXTERNAL DEVICE T TO EXTERNAL MEMORY tpGRDL RD EXTERNAL 0 EXTERNAL DEVICE lt gt DDGHA lt ADDRESS SW MSx READ BUS MASTER MEMORY WRITE BUS MASTER AND SYNCHRONOUS READ WRITE BUS MASTER TIMING SPECIFICATIONS FOR ADDR RD WR SW MS AND ACK ALSO APPLY HERE Figure 18 DMA Handshake Timing REV C 29 ADSP 21065L SDRAM Interface Bus Master Use these specifications for ADSP 21065L bus master accesses of SDRAM Parameter Min Max Unit Timing Requirements 5080 Data Setup Before SDCLK 2 0 ns tHDSDK Data Hold After SDCLK 1 25 ns Switching Characteristics tpspKi First SDCLK Rise Delay After CLKIN 9 0 6DT 12 75 6DT ns tpspk2 Second SDCLK Rise Delay After CLKIN 25 5 22DT 29 25 22 DT ns tspK SDCLK Period 16 67 1 2 ns tspKH SDCLK Width High 7 5 8DT ns SDCLK Width Low 6 5 ns tDCADSDK Command Address Data Delay After SDCLK 10 0 5 DT ns tHCADSDK Command Address Data Hold After SDCLK 4 5 5 DT ns tspTRSDK Data Three State After SDCLK 95 5 ns tsDENSDK Data Enable After SDCLK 6 0 5 DT ns tspcTR SD
8. SDRAM CONTROLLER ADDS ONE SDRAM CLK THREE STATED CYCLE DELAY tck 2 ON A READ FOLLOWED BY A WRITE Figure 19 SDRAM Interface REV 31 ADSP 21065L Serial Ports Parameter Min Max Unit External Clock Timing Requirements tSFSE TFS RFS Setup Before TCLK RCLK 4 0 ns tHFSE TFS RFS Hold After TCLK RCLK 4 0 ns tsprE Receive Data Setup Before RCLK 1 5 ns Receive Data Hold After RCLK 4 0 ns tscLKW TCLK RCLK Width 9 0 ns TCLK RCLK Period tex ns Internal Clock Timing Requirements tspsI TFS Setup Before TCLK RFS Setup Before 8 0 ns TFS RFS Hold After TCLK RCLK 1 0 ns tSDRI Receive Data Setup Before RCLK 3 0 ns tHDRI Receive Data Hold After RCLK 3 0 ns External or Internal Clock Switching Characteristics tpESE RFS Delay After RCLK Internally Generated RFS 2 13 0 ns tHOFSE RFS Hold After Internally Generated RFS 3 0 ns External Clock Switching Characteristics tpFSE TFS Delay After TCLK Internally Generated TFS 13 0 ns tHOFSE TFS Hold After TCLK Internally Generated TFS 3 0 ns tppTE Transmit Data Delay After TCLK 12 5 ns HDTE Transmit Data Hold After TCLK 4 0 ns Internal Clock Switching Characteristics tprpsI TFS Delay After TCLK Internally Generated TFS 4 5 ns tHOFSI TFS Hold After TCLK Internally Generated TFS 1 5 ns tppTI Transmit Data Delay After TCLK 7 5 ns tHDTI Transmit Data Hold After TCLK2 0 0 ns tscLKIW TCLK RCLK Width lt
9. 0 NOTES is not sampled on external memory accesses that use the Internal wait state mode For the first CLKIN cycle of a new external memory access ACK must be valid by tpaax tpsax or synchronous specification for wait state modes External Either or Both Both if the internal wait state is zero For the second and subsequent cycles of a wait stated external memory access synchronous specifications and tgackc must be met for wait state modes External Either or Both Both after internal wait states have completed The falling edge of MSx SW and BMS is referenced 5See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads ADDRESS MSx SW BMS DATA ACK DMAG Figure 12 Memory Write Bus Master REV C 17 ADSP 21065L Synchronous Read Write Bus Master Use these specifications for interfacing to external memory systems that require CLKIN relative timing or for accessing a slave ADSP 21065L in multiprocessor memory space These synchronous switching characteristics are also valid during asynchronous memory reads and writes see Memory Read Bus Master and Memory Write Bus Master When accessing a slave ADSP 21065L these switching characteristics must meet the slave s timing requirements for synchronous read writes see Synchronous Read Write Bus Slave The
10. BMSTR CAS RAS SDWE DQM SDCLK SDCKE VA 15 T S VA IO T IO T IO T O T I O S T IO T Boot Memory Select Output used as chip select for boot EPROM devices when BSEL 1 In a multiprocessor system BMS is output by the bus master Input When low indicates that no booting will occur and that the ADSP 21065L will begin executing instructions from exter nal memory See following table This input is a system configuration selection which should be hardwired Three statable only in EPROM boot mode when BMS is an output BSEL BMS 1 Output 0 1 Input 0 0 Input Booting Mode EPROM connect BMS to EPROM chip select Host processor HBW SYSCON bit selects host bus width No booting Processor executes from external memory Clock In Used in conjunction with XTAL configures the ADSP 21065L to use either its internal clock generator or an external clock source The external crystal should be rated at 1x frequency Connecting the necessary components to CLKIN and XTAL enables the internal clock genera tor The ADSP 21065L s internal clock generator multiplies the 1x clock to generate 2x clock for its core and SDRAM It drives 2x clock out on the SDCLKx pins for the SDRAM interface to use See also SDCLKx Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the ADSP 21065L to use the external clock source The instruction cycle rate is eq
11. NOTE See Environmental Conditions for information on thermal specifications ELECTRICAL CHARACTERISTICS C and K Grades Parameter Test Conditions Min Max Unit Vou High Level Output Voltage Vpp min 2 0 2 4 V Vor Low Level Output Voltage min Ip 4 0 0 4 V High Level Input Current max Vpp 10 Low Level Input Current max Vin 0 V 10 uA Low Level Input Current max Vin 0 V 150 uA Three State Leakage Current 10 max Vpp max 10 Three State Leakage Current max Vin 0 V 8 uA lozs Three State Leakage Current max Vin 0 V 150 uA IozrA Three State Leakage Current max 1 5 V 350 uA Ioziag Three State Leakage Current max Vn 0 V 4 mA Iozrc Three State Leakage Current max Vn 0 V 1 5 mA Cm Input Capacitance 12 1 MHz 25 C Vin 2 5 V 8 pF NOTES 1 Applies to input and bidirectional pins DATA5 9 BSEL RD WR SW ACK SBTS FLAG o HBG CS DMARI DMAR2 1 RPBA CPA 50 TFS1 RFS1 BMS TMS TDI HBR DROA DR1A DROB DRIB RCLK0 RCLK1 RESET TRST PWM_EVENT0 EVENTI RAS CAS SDWE SDCKE Applies to input pin CLKIN 3 Applies to output and b
12. 28 18 08 62 82 42 92 92 vL 62 24 02 69 89 19 99 99 v9 9 29 19 09 69 89 29 99 99 vs 64 iv1va ziviva oLlviva 1 aNd gvivq 9vivq sviva 1 gviva oviva 99V13 65v14 015v aaa ESN ZSIN LSIN oS aaa NS qu 5195 so uisa NO CONNECT NC REV C 40 ADSP 21065L OUTLINE DIMENSIONS 208 Lead Metric Quad Flat Package MQFP S 208 2 Dimensions shown in millimeters 30 85 0 75 ii 30 60 SQ 0 60 3 2 30 35 MAX 0 45 208 157 1 156 SEATING PLANE i PIN 1 INDICATOR 28 20 TOP VIEW 28 00 SQ PINS DOWN 27 80 3 60 VIEW A 3 40 1 52 105 0 09 zy i 0 50 0 50 BSC he 0 08 LEAD LEAD PITCH 0 17 COPLANARITY LEAD WIDTH VIEW ROTATED 90 CCW NOTES 1 THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0 08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION 2 CENTER DIMENSIONS ARE NOMINAL 3 DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS 029 FA 1 REV C 41 ADSP 21065L 196 BALL MINI BGA PIN CONFIGURATION Ball Name Ball Name Ball Name Ball Name Ball Name Al NCI Bl DROA Cl TCLKO DI RCLK1 El TFS1 A2 NC2
13. 021 243 ez 213 1213 SZ 921 141 8 1 641 081 181 881 est vet 881 981 281 881 681 061 161 261 861 t6L S6L 961 161 861 661 002 102 202 602 voc 502 902 TRST EMU 156 155 154 153 BMS 152 BSEL 151 TCK 150 GND 149 TMS 148 TDI 147 146 145 144 IDO 143 1D1 142 NC 141 VDD 140 VDD 139 GND 138 FLAG4 137 FLAG5 136 FLAG6 135 GND 134 FLAG7 133 DATA31 132 DATA30 131 VDD 130 VDD 129 GND 128 DATA29 127 DATA28 126 DATA27 125 GND 124 123 26 122 25 121 24 120 VDD 119 GND 118 DATA23 117 22 116 21 115 114 GND 113 20 112 19 111 18 110 VDD 109 17 108 16 107 15 106 GND 105 VDD IDENTIFIER 4 o o o 2 St n o a lt 59 gt rz 42 43 44 50 51 52 RCLKO 4 TCLK0 8 11 DT0B 12 16 TCLK1 19 VDD 20 VDD 21 DT1A 22 DT1B 23 PWM_EVENT1 24 GND 25 PWM EVENTO 26 BR1 27 2 28 VDD 29 CLKIN 30 XTAL 31 SDCLK1 34 SDCLKO 37 DMAR1 38 DMAR2 39 HBR 40 GND 41 5 5 SDWE VDD 145 DQM 46 SDCKE 47 SDA10 48 GND 49 DMAG1 DMAG2 HBG vot 601 ZOL LOL 001 66 86 16 96 96 76 t6 26 16 06 68 88 18 98 98 v8 8
14. 8703 2003 Analog Devices Inc All rights reserved ADSP 21065L 544 Kbits Configurable On Chip SRAM Dual Ported for Independent Access by Core Processor and DMA Configurable in Combinations of 16 32 48 Bit Data and Program Words in Block 0 and Block 1 DMA Controller Ten DMA Channels Two Dedicated to the External Port and Eight Dedicated to the Serial Ports Background DMA Transfers at up to 66 MHz in Parallel with Full Speed Processor Execution Performs Transfers Between Internal RAM and Host Internal RAM and Serial Ports Internal RAM and Master or Slave SHARC Internal RAM and External Memory or I O Devices External Memory and External Devices Host Processor Interface Efficient Interface to 8 16 and 32 Bit Microprocessors Host Can Directly Read Write ADSP 21065L IOP Registers Multiprocessing Distributed On Chip Bus Arbitration for Glueless Parallel Bus Connect Between Two ADSP 21065Ls Plus Host 132 Mbytes s Transfer Rate Over Parallel Bus Serial Ports Independent Transmit and Receive Functions Programmable 3 Bit to 32 Bit Serial Word Width S Support Allowing Eight Transmit and Eight Receive Channels Glueless Interface to Industry Standard Codecs TDM Multichannel Mode with p Law A Law Hardware Companding Multichannel Signaling Protocol REV ADSP 21065L GENERAL DESCRIPTION The ADSP 21065L is a powerful member of the SHARC family of 32 bit processors optimized for cost sensitive appli ca
15. B2 RFSO C2 RCLKO D2 50 E2 DTOB A3 FLAG2 B3 IRQO C3 IRQ2 D3 DROB E3 DTOA A4 ADDRO B4 FLAGO C4 FLAG3 D4 IRQI E4 RFS1 A5 ADDR3 B5 ADDR2 C5 ADDRI D5 FLAGI E5 VDD A6 ADDR6 B6 ADDR5 C6 ADDR4 D6 VDD E6 GND A7 ADDR7 B7 ADDR9 C7 ADDRIO D7 VDD E7 GND A8 ADDR8 B8 ADDR12 C8 ADDRI3 D8 VDD E8 GND 9 ADDRII B9 5 C9 ADDR16 D9 VDD E9 GND 10 ADDR14 B10 ADDR19 C10 ADDR20 D10 VDD E10 VDD All ADDRI7 B11 ADDR21 C11 ADDR22 D11 BMS Ell IDO A12 ADDR18 B12 ADDR23 C12 RESET D12 TMS E12 TDI A13 NC8 B13 GND C13 BSEL D13 TRST E13 ID1 Al4 NC7 B14 TCK C14 TDO D14 EMU E14 FLAG4 Fl TCLKI Gl PWM_ H1 PWM_ jl CLKIN K1 DMARI EVENT1 EVENTO F2 DRIB G2 H2 BRI 12 XTAL K2 SDCLK0 F3 DRIA G3 DTIA H3 BR2 13 SDCLK1 K3 HBR F4 VDD G4 VDD H4 VDD J4 VDD K4 SDWE F5 GND G5 GND H5 GND J5 GND K5 VDD F6 GND G6 GND H6 GND 16 GND K6 GND F7 GND G7 GND H7 GND 77 GND K7 GND F8 GND G8 GND H8 GND 18 GND K8 GND F9 GND G9 GND H9 GND J9 GND K9 GND 10 GND G10 GND H10 GND J10 GND K10 VDD VDD G11 VDD H11 VDD VDD K11 DATA19 F12 FLAG6 G12 DATA31 H12 DATA28 J12 DATA24 K12 DATA21 F13 FLAG5 G13 DATA30 H13 DATA27 J13 DATA25 K13 DATA20 F14 FLAG7 G14 DATA29 H14 DATA26 114 23 K14 DATA22 L1 DMAR2 M1 RAS N1 DQM P1 NC3 L2 CAS M2 SDCKE N2 HBG 2 NC4 L3 SDA10 M3 DMAGI N3 BMSTR P3 GND 14 DMAG2 M4 CS N4 SBTS P4 WR L5 VDD 5 RD N5 REDY P5 SW L6 VDD M6 CPA N6 GND P6 MSO L7 VDD M7 ACK N7 MSI P7 MS2 L8 VDD M8 FLAG10 N8 FLAGII P8 MS3 L9 VDD M9 DATA2 N9 DATAI P9 FLAG9 L10 DATA8 M
16. EDGE EDGE EDGE tscukiw 9 lt tscLkw gt RCLK RCLK RFS RFS gt tupni tspre J DR DR NOTE EITHER THE RISING EDGE OR FALLING EDGE OF RCLK TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE DATA TRANSMIT INTERNAL CLOCK DATA TRANSMIT EXTERNAL CLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE tscukiw lt tscLkw 4 tprsi 4 torse gt t t tgpge these TFS TFS lt gt NOTE EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE DRIVE DRIVE EDGE EDGE EXT TFS LATE EXT TCLK RCLK gt tpprrE DT DRIVE DRIVE EDGE EDGE TCLK INT TFS LATE INT TCLK RCLK tpprri DT CLKIN SPORT ENABLE AND TCLK RCLK SPORT DISABLE DELAY THREE STATE FROM INSTRUCTION LATENCY TES BES IS TWO CYCLES INT RCLK INT LOW TO HIGH ONLY Figure 20 Serial Ports REV C 33 ADSP 21065L EXTERNAL RFS with MCE 1 MFD 0 DRIVE SAMPLE DRIVE RCLK RFS DT 2ND BIT LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK TFS 2ND BIT DT tDDTLFSE Figure 21 External Late Frame Sync Frame Sync Setup lt 2 EXTERNAL RFS with MCE 1 MFD 0 DRIVE SAMPLE DRIVE RCLK lt RFS lt
17. EMU and GND signals be made accessible on the target system via a 14 pin connector a 2 row x 7 pin strip header such as that shown in Figure 6 The EZ ICE probe plugs directly onto this connector for chip on board emulation You must add this connector to your target board design if you intend to use the ADSP 2106x EZ ICE The total trace length between the EZ ICE connector and the furthest device sharing the EZ ICE JTAG pins should be lim ited to 15 inches maximum for guaranteed operation This restriction on length must include EZ ICE JTAG signals which are routed to one or more 2106x devices or to a combination of 2106xs and other JTAG devices on the chain The 14 pin 2 row pin strip header is keyed at the Pin 3 loca tion you must remove Pin 3 from the header The pins must be 0 025 inch square and at least 0 20 inch in length Pin spac ing should be 0 1 x 0 1 inches Pin strip headers are available from vendors such as 3M McKenzie and Samtec GND KEY NO PIN CLKIN OPTIONAL BTMS TMS BTCK BTRST BTDI TOP VIEW Figure 6 Target Board Connector for ADSP 2106x EZ ICE JTAG Header REV C ADSP 21065L The BTMS BTCK BTRST and BTDI signals are provided so that the test access port can also be used for board level testing When the connector is not being used for emulation place jumpers between the Bxxx pins and the xxx pins If you are not going to use the test access port for board tes
18. asserted when the ADSP 21065L reads from external memory devices or from the IOP register of another ADSP 21065L External devices including another ADSP 21065L must assert RD to read from the ADSP 21065L s IOP registers In a multipro cessor system RD is output by the bus master and is input by another ADSP 21065L WR I O T Memory Write Strobe This pin is asserted when the ADSP 21065L writes to external memory devices or to the IOP register of another ADSP 21065L External devices must assert WR to write to the ADSP 21065L s IOP registers In a multiprocessor system WR is output by the bus master and is input by the other ADSP 21065L SW I O T Synchronous Write Select This signal interfaces the ADSP 21065L to synchronous memory devices including another ADSP 21065L The ADSP 21065L asserts SW to provide an early indication of an impending write cycle which can be aborted if WR is not later asserted e g in a conditional write instruction In a multiprocessor system SW is output by the bus master and is input by the other ADSP 21065L to determine if the multiprocessor access is a read or write SW is asserted at the same time as the address output ACK I O S Memory Acknowledge External devices can deassert ACK to add wait states to an external memory access ACK is used by I O devices memory controllers or other peripherals to hold off completion of an external memory access The ADSP 21065L deasserts ACK as an output to add wait s
19. high impedance state It does however continue to drive the SDRAM control pins HBR has priority over all ADSP 21065L bus requests 1 in a multiprocessor system HBG Host Bus Grant Acknowledges bus request indicating that the host may take control of the external bus HBG is asserted by the ADSP 21065L until HBR is released In a multiprocessor system HBG is output by the ADSP 21065L bus master CS VA Chip Select Asserted by host processor to select the ADSP 21065L REDY O D Host Bus Acknowledge The ADSP 21065L deasserts REDY to add wait states to an asyn chronous access of its internal memory or IOP registers by a host Open drain output O D by default can be programmed in ADREDY bit of SYSCON register to be active drive A D REDY will only be output if the CS and HBR inputs are asserted DMAR VA DMA Request 1 DMA Channel 9 DMAR DMA Request 2 DMA Channel 8 DMAG O T Grant 1 DMA Channel 9 DMAG O T Grant 2 DMA Channel 8 I O S Multiprocessing Bus Requests Used by multiprocessing ADSP 21065Ls to arbitrate for bus mastership ADSP 21065L drives its own BRx line corresponding to the value of its inputs only and monitors all others In a uniprocessor system tie both BRx pins to VDD ID I Multiprocessing ID Determines which 1 multiprocessor bus request BR BR gt is used by ADSP 21065L ID 01 corresponds to BR ID 10 correspond
20. or a crystal See CLKIN pin description You can configure the ADSP 21065L to use its internal clock generator by connecting the necessary components to CLKIN and XTAL You can use either a crystal operating in the fundamental mode or a crystal operating at an overtone Figure 4 shows the component connections used for a crystal operating in fundamental mode and Figure 5 shows the component connections used for a crystal operating at an overtone CLKIN XTAL C1 I c2 I SUGGESTED COMPONENTS FOR 30 MHz OPERATION ECLIPTEK EC2SM 33 30 000M SURFACE MOUNT PACKAGE ECLIPTEK EC 33 30 000M THROUGH HOLE PACKAGE C1 33pF C2 27pF NOTE C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 CONTACT CRYSTAL MANUFACTURER FOR DETAILS Figure 4 30 MHz Operation Fundamental Mode Crystal CLKIN XTAL T 3 SUGGESTED COMPONENTS FOR 30MHz OPERATION ECLIPTEK EC2SM T 30 000M SURFACE MOUNT PACKAGE ECLIPTEK ECT 30 000M THROUGH HOLE PACKAGE C1 18pF C2 27pF 75pF L 3300nH Rg SEE NOTE NOTE C1 C2 C3 Rs AND L ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 CONTACT MANUFACTURER FOR DETAILS C1 Figure 5 30 MHz Operation 3rd Overtone Crystal 10 TARGET BOARD CONNECTOR FOR EZ ICE PROBE The ADSP 2106x EZ ICE emulator uses the IEEE 1149 1 JTAG test access port of the ADSP 2106x to monitor and con trol the target board processor during emulation The EZ ICE probe requires the ADSP 2106x s CLKIN TMS TCK TRST TDI TDO
21. register file combined with the ADSP 21000 Harvard architecture allows unconstrained data flow between computation units and internal memory Single Cycle Fetch of Instruction and Two Operands The ADSP 21065L features an enhanced Super Harvard Archi tecture in which the data memory DM bus transfers data and the program memory PM bus transfers both instructions and data see Figure 1 With its separate program and data memory buses and on chip instruction cache the processor can simulta neously fetch two operands and an instruction from the cache all in a single cycle Instruction Cache The ADSP 21065L includes an on chip instruction cache that enables three bus operation for fetching an instruction and two data values The cache is selective only the instructions that fetches conflict with PM bus data accesses are cached This allows full speed execution of core looped operations such as digital filter multiply accumulates and FFT butterfly processing Data Address Generators with Hardware Circular Buffers The ADSP 21065L s two data address generators DAGs implement circular data buffers in hardware Circular buffers allow efficient programming of delay lines and other data ADSP 21065L structures required in digital signal processing and are com monly used in digital filters and Fourier transforms The ADSP 21065L s two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers 16 prima
22. slave ADSP 21065L must also meet these bus master timing require ments for data and acknowledge setup and hold times Parameter Min Max Unit Timing Requirements tsspATI Data Setup Before CLKIN 0 25 2 DT ns tHSDATI Data Hold After CLKIN 4 0 2DT ns ACK Delay After Address MSx SW BMS 24 0 30DT W ns tsACKC ACK Setup Before CLKIN 2 75 4 DT ns ACK Hold After CLKIN 2 0 4 DT ns Switching Characteristics tpADRO Address MSx BMS SW Delay After CLKIN 7 0 2DT ns tHADRO Address MSx BMS SW Hold After CLKIN 0 5 2DT ns tpRDO RD High Delay After CLKIN 0 5 2 DT 6 0 2 DT ns tpwro WR High Delay After CLKIN 0 0 3 DT 6 0 3 DT ns tpRWL RD WR Low Delay After CLKIN 7 5 4DT 11 75 4 DT ns tppATO Data Delay After CLKIN 22 0 10 DT ns tpATTR Data Disable After CLKIN 1 0 2DT 7 0 2DT ns tpBM BMSTR Delay After CLKIN 3 0 ns BMSTR Hold After CLKIN 4 0 ns W number of wait states specified in WAIT register X tcx NOTES Hold User must meet tupa tgpgg or synchronous specification See system hold time calculation under test conditions for the calculation of hold times given capacitive and dc loads is not sampled on external memory accesses that use the Internal wait state mode For the first CLKIN cycle of a new external memory access ACK must be valid by tpAAK tpsax or synchronous specification for wait state modes External Either or Bot
23. 10 DATA5 N10 DATA4 P10 FLAG8 L11 DATA13 M11 DATA9 N11 DATA7 Pll DATAO L12 16 M12 DATA12 N12 DATA10 P12 DATA3 L13 DATA17 M13 DATA14 N13 DATA11 P13 DATA6 14 DATAI18 M14 DATA15 N14 NC6 P14 NC5 42 REV C REV C E E EI DE DATA10 DATA3 ADSP 21065L 196 BALL MINI BGA PIN CONFIGURATION ADDR18 ADDR17 ADDR14 ADDR11 ADDR8 ADDR7 ADDR6 ADDR23 ADDR21 ADDR19 ADDR15 ADDR12 ADDR9 ADDR5 RESET ADDR22 ADDR20 ADDR16 ADDR13 ADDR10 ADDR4 ADDR0 FLAG2 NC1 E DR0A PWM_ EVENT1 PWM_ EVENTO SDCLK1 CLKIN DATA2 FLAG10 DATA1 FLAG11 SDCKE SBTS BMSTR 43 ADSP 21065L ORDERING GUIDE Part Case Temperature Instruction On Chip Operating Package Number Range Rate SRAM Voltage Options ADSP 21065LKS 240 0 C to 85 C 60 MHz 544 Kbit 3 3 V MQFP ADSP 21065LCS 240 40 C to 100 C 60 MHz 544 Kbit 3 3V MQFP ADSP 21065LKCA 240 0 C to 85 C 60 MHz 544 Kbit 3 3 V Mini BGA ADSP 21065LKS 264 0 C to 85 C 66 MHz 544 Kbit 3 3 V MQFP ADSP 21065LKCA 264 0 C to 85 C 66 MHz 544 Kbit 3 3 V Mini BGA ADSP 21065LCCA 240 40 C to 100 60 MHz 544 Kbit 3 3 V Mini BGA OUTLINE DIMENSIONS 196 Lead Chip Scale Ball Grid Array CSPBGA Dimensions shown in millimeters 1500 n DETAIL B 1413121110 9 8 7 6 5 4 22222522221522 oooooooooooooo
24. 135 ns 9 4 x 4 x 4 x 1 240 ns 16 FIR Filter per Tap 15 ns 1 IIR Filter per Biquad 60 ns 4 Divide Y X 90 ns 6 Inverse Square Root Ax 135 ns 9 DMA Transfers 264 Mbytes sec ADSP 21000 FAMILY CORE ARCHITECTURE The ADSP 21065L is code and function compatible with the ADSP 21060 ADSP 21061 ADSP 21062 The ADSP 21065L includes the following architectural features of the SHARC family core REV C ADSP 21065L CLKIN BOOT ADDR EPROM DATA OPTIONAL CONTROL ADDR23 0 PROCESSOR OPTIONAL 2 5 ma 2585 als x OPTIONAL m 5 lt 5 m oi e e v 7 ES Figure 2 ADSP 21065L Single Processor System Independent Parallel Computation Units The arithmetic logic unit ALU multiplier and shifter all perform single cycle instructions The three units are arranged in parallel maximizing computational throughput Single multi function instructions execute parallel ALU and multiplier operations These computation units support IEEE 32 bit single precision floating point extended precision 40 bit floating point and 32 bit fixed point data formats Data Register File A general purpose data register file is used for transferring data between the computation units and the data buses and for storing intermediate results This 10 port 32 register 16 primary 16 secondary
25. 2 5 ns tspaTWH Data Setup Before WR High 4 5 ns Data Hold After WR High 0 0 ns Switching Characteristics tsDDATO Data Delay After CLKIN 31 75 21 DT ns tpaTTR Data Disable After CLKIN 1 0 2 DT 7 0 2 DT ns tpACK ACK Delay After CLKIN 29 5 20 DT ns tACKTR ACK Disable After CLKIN 1 0 2DT 60 2DT ns NOTES is specified when Multiprocessor Memory Space Wait State MMSWS bit in WAIT register is disabled when MMSWS is enabled tsawur min 17 5 18 DT See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads For two ADSP 21065Ls to communicate synchronously as master and slave certain master and slave specification combinations must be satisfied Do not compare specification values directly to calculate master slave clock skew margins for those specifications listed below The following table shows the appropriate clock skew margin Table IV Bus Master to Slave Skew Margins Master Specification Slave Specification Skew Margin tsspATI tcK 33 3 ns 2 25 ns tcx 30 0 ns 1 50 ns tpACK tck 33 3ns 3 00 ns 30 0 ns 2 25 ns tpADRO tSADRI tcx 33 3 ns 30 0 ns 2 75 ns tSRWII tcg 33 3 ns 1 50 ns 30 0ns 1 25 ns tHRWII Max tck 33 3 ns N A 30 0ns 3 00 ns tpwRo Max tHRWLI Max 33 3 ns N A 30 0ns 3 75 ns
26. 256 Kbits Bank 0 is configured with 9 columns of 2K x 16 bits and Bank 1 is configured with 8 columns of 2K x16 bits Each memory block is dual ported for single cycle independent accesses by the core processor and I O processor or DMA controller The dual ported memory and separate on chip buses allow two data transfers from the core and one from I O all in a single cycle see Figure 4 for the ADSP 21065L Memory Map On the ADSP 21065L the memory can be configured as a maximum of 16K words of 32 bit data 34K words for 16 bit data 10K words of 48 bit instructions and 40 bit data or combinations of different word sizes up to 544 Kbits All the memory can be accessed as 16 bit 32 bit or 48 bit While each memory block can store combinations of code and data accesses are most efficient when one block stores data using the DM bus for transfers and the other block stores instructions and data using the PM bus for transfers Using the DM and PM busses in this way with one dedicated to each memory block assures single cycle execution with two data transfers In this case the instruction must be available in the cache Single cycle execution is also maintained when one of the data operands is transferred to or from off chip via the ADSP 21065L s external port Off Chip Memory and Peripherals Interface The ADSP 21065L s external port provides the processor s interface to off chip memory and peripherals The 64M words off chip a
27. ANALOG DEVICES DSP Microcomputer ADSP 21065L SUMMARY High Performance Signal Computer for Communica tions Audio Automotive Instrumentation and Industrial Applications Super Harvard Architecture Computer SHARC Four Independent Buses for Dual Data Instruction and 1 0 Fetch a Single Cycle 32 Bit Fixed Point Arithmetic 32 Bit and 40 Bit Floating Point Arithmetic 544 Kbits On Chip SRAM Memory and Integrated I O Peripheral 125 Support for Eight Simultaneous Receive and Trans mit Channels KEY FEATURES 66 MIPS 198 MFLOPS Peak 132 MFLOPS Sustained Performance User Configurable 544 Kbits On Chip SRAM Memory Two External Port DMA Channels and Eight Serial Port DMA Channels CORE PROCESSOR INSTRUCTION CACHE 32 x 48BIT DAG1 8x4x32 PROCESSOR PORT ADDR SDRAMI Controller for Glueless Interface to Low Cost External Memory 66 MHz 64M Words External Address Range 12 Programmable I O Pins and Two Timers with Event Capture Options Code Compatible with ADSP 2106x Family 208 Lead MOFP or 196 Ball Mini BGA Package 3 3 Volt Operation Flexible Data Formats and 40 Bit Extended Precision 32 Bit Single Precision and 40 Bit Extended Precision IEEE Floating Point Data Formats 32 Bit Fixed Point Data Format Integer and Fractional with Dual 80 Bit Accumulators Parallel Computations Single Cycle Multiply and ALU Operations in Parallel with Dual Memory Read Wri
28. Before CLKIN High2 23 5 24 DT ns NOTES 1Applies after the power up sequence is complete At power up the processor s internal phase locked loop requires no more than 3000 CLKIN cycles while RESET is low assuming stable Vpp and CLKIN not including start up time of external clock oscillator Only required if multiple ADSP 2106xs must come out of reset synchronous to CLKIN with program counters PC equal i e for a SIMD system Not required for multiple ADSP 2106xs communicating over the shared bus through the external port because the bus arbitration logic synchronizes itself automatically after reset CLKIN t Q twnsr gt 357 RESET ANN Figure 8 Reset Parameter Min Max Unit Interrupts Timing Requirements tSIR IRQ2 0 Setup Before CLKIN High or Low 11 0 12 DT ns tum IRQ2 0 Hold Before CLKIN High or Low 0 0 12 DT ns trpw IRQ2 0 Pulsewidth2 2 0 1 2 ns NOTES 1Only required for IRQx recognition in the following cycle Applies only if and tpr requirements are not met _14 REV C ADSP 21065L CLKIN tsir tun 227 Figure 9 Interrupts Parameter Min Max Unit Timer Timing Requirements Timer Setup Before SDCLK High 0 0 ns turi Timer Hold After SDCLK High 6 0 ns Switching Characteristics tpTEX Timer Delay After SDCLK High 1 0 ns tHTEX Timer Hold After SDCLK High 5 0 ns Parameter Min Max Unit Flags Timing Requireme
29. CLK Command Three State After CLKIN 5 0 3 DT 9 75 3 DT ns tspcEN SDCLK Command Enable After CLKIN 5 0 2DT 10 0 2 DT ns tsDATR Address Three State After CLKIN 1 0 4DT 3 0 4DT ns tSDAEN Address Enable After CLKIN 1 0 2DT 7 0 2 DT ns NOTES 1Command SDCKE MSx RAS CAS SDWE DQM and SDA10 2SDRAM controller adds one SDRAM CLK three stated cycle delay tcx 2 on a Read followed by a Write SDRAM Interface Bus Slave These timing requirements allow a bus slave to sample the bus master s SDRAM command and detect when a refresh occurs Parameter Min Max Unit Timing Requirements tsspKC1 First SDCLK Rise After CLKIN 6 50 16 DT 17 5 16 DT ns tsspKc2 Second SDCLK Rise After CLKIN 23 25 34 25 ns tscspK Command Setup Before SDCLK 0 0 ns tHcsDK Command Hold After SDCLK 2 0 ns NOTE Command SDCKE RAS CAS and SDWE 30 REV C ADSP 21065L CLKIN tospk2 tspk SDCLK tspspk DATA IN tocapspk gt tspENsDK gt DATA OUT tocapspk CMND ADDR OUT t tspcen I CMND1 OUT ADDR OUT tspAEN lt 4 tspATR CLKIN lt tsspkc2 4 tsspkci gt SDCLK IN tscspk gt CMND IN lucspk NOTES 1COMMAND SDCKE MSy RAS CAS SDWE DQM AND SDA10
30. MS 191 VDD 24 PWM_EVENTI1 66 VDD 108 DATA16 150 GND 192 VDD 25 GND 67 VDD 109 DATAI7 151 TCK 193 ADDR2 26 EVENTO 68 GND 110 VDD 152 BSEL 194 ADDRI 27 BRI 69 ACK 111 18 153 BMS 195 ADDRO 28 BR2 70 MSO 112 19 154 GND 196 GND 29 VDD 71 113 DATA20 155 GND 197 FLAG0 30 CLKIN 72 GND 114 GND 156 VDD 198 FLAGI 31 XTAL 73 GND 115 NC 157 RESET 199 FLAG2 32 VDD 74 MS2 116 DATA21 158 VDD 200 VDD 33 GND 75 MS3 117 DATA22 159 GND 201 FLAG3 34 SDCLKI 76 FLAG11 118 DATA23 160 ADDR23 202 NC 35 GND 77 VDD 119 GND 161 ADDR22 203 NC 36 VDD 78 FLAG10 120 VDD 162 ADDR21 204 GND 37 SDCLKO 79 FLAG9 121 DATA24 163 VDD 205 IRQO 38 DMARI 80 FLAGS 122 DATA25 164 ADDR20 206 IROI 39 DMAR2 81 GND 123 DATA26 165 ADDR19 207 IRQ2 40 HBR 82 DATA0 124 VDD 166 ADDR18 208 NC 41 GND 83 DATAI 125 GND 167 GND 42 RAS 84 DATA2 126 DATA27 168 GND REV C 39 ADSP 21065L 208 LEAD MQFP PIN 19539 and 6 and 21 9 vrdHaav 6yqqv and 9 QNS ouaav and 09V14 LSV14 eovid SV14 ON ON and ON 181 891 691 091 191 291 691 vol 891 991 191 891 691
31. accesses of both ADSP 21065L s IOP registers Distributed bus arbitration logic is included on chip for simple glueless connection of systems containing a maximum of two ADSP 21065Ls and a host processor Master processor changeover incurs only one cycle of overhead Bus lock allows indivisible read modify write sequences for semaphores A vector interrupt is provided for interprocessor commands Maximum throughput for interprocessor data transfer is 132 Mbytes sec over the external port REV 5 DEVELOPMENT TOOLS The ADSP 21065L is supported with a complete set of software and hardware development tools including the EZ ICE In Circuit Emulator and development software The same EZ ICE hardware that you use for the ADSP 21060 ADSP 21062 also fully emulates the ADSP 21065L Both the SHARC Development Tools family and the VisualDSP integrated project management and debugging environment support the ADSP 21065L The VisualDSP project management environment enables you to develop and debug an application from within a single integrated program The SHARC Development Tools include an easy to use Assem bler that is based on an algebraic syntax an Assembly library librarian a linker a loader a cycle accurate instruction level simulator a C compiler and a C run time library that includes DSP and mathematical functions Debugging both C and Assembly programs with the Visual DSP debugger you can View Mixed C and Asse
32. ca 38 29 23 Address 11 50 10 7 x 30 MHz x 10 9 V 0 019 W MS 1 0 x 10 7 x 10 9 V 0 000 W SDWE 1 0 x 10 7 x 10 9 V 0 000 W Data 32 50 7 7 x 30 MHz x 10 9 V 0 042 W SDRAM 1 _ x 10 7 x30 MHz x 10 9 V 0 007 W 0 068 W 38 REV C ADSP 21065L 208 LEAD MQFP PIN CONFIGURATION Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name 1 VDD 43 CAS 85 VDD 127 DATA28 169 ADDRI7 2 RFSO 44 SDWE 86 DATA3 128 DATA29 170 ADDRI6 3 GND 45 VDD 87 DATA4 129 GND 171 ADDRI5 4 RCLK0 46 DQM 88 DATA5 130 VDD 172 VDD 5 DROA 47 SDCKE 89 GND 131 VDD 173 ADDR14 6 DROB 48 SDA10 90 DATA6 132 DATA30 174 ADDR13 7 TFS0 49 GND 91 DATA7 133 DATA31 175 ADDR12 8 50 DMAGI 92 DATAS 134 FLAG 176 VDD 9 VDD 5 DMAG2 93 VDD 135 GND 177 GND 10 GND 52 HBG 94 GND 136 FLAG6 178 ADDRII 11 DT0A 53 BMSTR 95 VDD 137 FLAGS 179 ADDRIO 12 DTOB 54 VDD 96 DATA9 138 FLAG4 180 ADDR9 13 RFSI 55 CS 97 DATAIO 139 GND 181 GND 14 GND 56 SBTS 98 11 140 VDD 182 VDD 15 RCLKI 51 GND 99 GND 141 VDD 183 ADDRS 16 DRIA 58 WR 100 DATA12 142 NC 184 ADDR7 17 DRIB 59 RD 101 13 143 185 ADDR6 18 TFS1 60 GND 102 NC 144 ID0 186 GND 19 TCLK1 61 VDD 103 NC 145 EMU 187 GND 20 VDD 62 GND 104 DATAI4 146 TDO 188 ADDR5 21 VDD 63 REDY 105 VDD 147 TRST 189 ADDR4 22 DTIA 64 SW 106 GND 148 TDI 190 ADDR3 23 65 107 DATAI5 149 T
33. ddress space is included in the ADSP 21065L s unified address space The separate on chip buses for program memory data memory and I O are multiplexed at the external port to create an external system bus with a single 24 bit address bus four memory selects and a single 32 bit data bus The on chip Super Harvard Architecture provides three bus performance while the off chip unified address space gives flexibility to the designer SDRAM Interface The SDRAM interface enables the ADSP 21065L to transfer data to and from synchronous DRAM SDRAM at 2x clock frequency The synchronous approach coupled with 2x clock frequency supports data transfer at a high throughput up to 220 Mbytes sec The SDRAM interface provides a glueless interface with stan dard SDRAMs 16 Mb 64 Mb and 128 Mb and includes options to support additional buffers between the ADSP 21065L and SDRAM The SDRAM interface is extremely flexible and provides capability for connecting SDRAMs to any one of the ADSP 21065L s four external memory banks Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements The ADSP 21065L supports pipelining of the address and control signals to enable such buffering between itself and multiple SDRAM devices Host Processor Interface The ADSP 21065L s host interface provides easy connection to standard microprocessor buses 8 16 and 32 bit requiring li
34. drive the RD and WR pins to access the ADSP 21065L s IOP registers HBR and HBG are assumed low for this timing Writes can occur at a minimum interval of 1 2 tex Parameter Min Max Unit Read Cycle Timing Requirements tsaDRDL Address Setup CS Low Before RD Low 0 0 ns tHADRDH Address Hold CS Hold Low After RD High 0 0 ns RD WR High Width 6 0 ns tpRDHRDY RD High Delay After REDY O D Disable 0 0 ns tpRDHRDY RD High Delay After REDY A D Disable 0 0 ns Switching Characteristics tspaTRDY Data Valid Before REDY Disable from Low 1 5 ns tpRDYRDL 0 0 A D Low Delay After RD Low 13 5 ns tRDYPRD REDY O D or A D Low Pulsewidth for Read 28 0 DT ns HDARWH Data Disable After RD High 2 0 10 0 ns Write Cycle Timing Requirements tscswRL CS Low Setup Before WR Low 0 0 ns THCSWRH CS Low Hold After WR High 0 0 ns tsADWRH Address Setup Before WR High 5 0 ns HADWRH Address Hold After WR High 2 0 ns twwRL WR Low Width 7 0 ns RD WR High Width 6 0 ns tpwRHRDY WR High Delay After REDY O D or A D Disable 0 0 ns tsDATWH Data Setup Before WR High 5 0 ns HDATWH Data Hold After WR High 1 0 ns Switching Characteristics tpRDYWRL REDY or A D Low Delay After WR CS Low 13 5 ns tRDYPWR REDY O D or A D Low Pulsewidth for Write 7 15 ns NOTE Not required if RD and address are valid after HBG goes low For first access after HBR asserted ADDR23 0 must be a no
35. e the values given in this data sheet reflect statistical varia tions and worst cases Consequently you cannot meaningfully add parameters to derive longer times See Figure 27 in Equivalent Device Loading for AC Measurements Includes All Fixtures for voltage reference levels REV 13 ADSP 21065L Switching Characteristics specify how the processor changes its signals You have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device con nected to the processor such as memory is satisfied Timing Requirements apply to signals that are controlled by circuitry external to the processor such as the data input for a read opera tion Timing requirements guarantee that the processor operates correctly with other devices O D Open Drain A D Active Drive 66 MHz 60 MHz Parameter Min Max Min Max Unit Clock Input Timing Requirements tex CLKIN Period 30 00 100 33 33 100 ns CLKIN Width Low 7 0 7 0 ns tckH CLKIN Width High 5 0 5 0 ns CLKIN Rise Fall 0 4 V 2 0 V 3 0 3 0 ns CLKIN Figure 7 Clock Input Parameter Min Max Unit Reset Timing Requirements twrst RESET Pulsewidth Low 2 tex ns tsRST RESET Setup
36. e Levels for AC Measure ments Except Output Enable Disable REV C ADSP 21065L Capacitive Loading Output delays and holds are based on standard capacitive loads 50 pF on all pins The delay and hold specifications given should be derated by a factor of 1 8 ns 50 pF for loads other than the nominal value of 50 pF Figure 28 and Figure 29 show how output rise time varies with capacitance Figure 30 shows graphically how output delays and hold vary with load capaci tance Note that this graph or derating does not apply to output disable delays see the previous section Output Disable time under Test Conditions The graphs of Figure 28 Figure 29 and Figure 30 may not be linear outside the ranges shown RISE AND FALL TIMES ns 0 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE pF Figure 28 Typical Rise and Fall Time 1090 9090 Vpp REV 37 8 0 7 0 6 0 5 0 RISE TIME 4 0 3 0 FALL TIME RISE AND FALL TIMES ns 2 0 1 0 00 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE pF Figure 29 Typical Rise and Fall Time 0 8 V 2 0 V OUTPUT DELAY OR HOLD ns 0 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE pF Figure 30 Typical Output Delay or Hold ADSP 21065L POWER DISSIPATION Total power dissipation has two compon
37. ed or when the ADSP 2106x is a bus slave Pin Type Function ADDR23 0 External Bus Address The ADSP 21065L outputs addresses for external memory and peripherals on these pins In a multiprocessor system the bus master outputs addresses for read writes of the IOP registers of the other ADSP 21065L The ADSP 21065L inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers I O T External Bus Data The ADSP 21065L inputs and outputs data and instructions on these pins The external data bus transfers 32 bit single precision floating point data and 32 bit fixed point data over bits 31 0 16 bit short word data is transferred over bits 15 0 of the bus Pull up resistors on unused DATA pins are not necessary 5 I O T Memory Select Lines These lines are asserted as chip selects for the corresponding banks of external memory Internal ADDR 5 24 are decoded into MS y The MS lines are decoded memory address lines that change at the same time as the other address lines When no external memory access is occurring the MS lines are inactive they are active however when a condi tional memory access instruction is executed whether or not the condition is true Additionally an MS o line which is mapped to SDRAM may be asserted even when SDRAM access is active In multiprocessor system the MS lines are output by the bus master RD Memory Read Strobe This pin is
38. edance state to when they start driving The output enable time is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the Output Enable Disable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving 36 Example System Hold Time Calculation To determine the data output hold time in a particular system first calculate tpgcAy using the equation given above Choose AV to be the difference between the ADSP 21065L s output voltage and the input threshold for the device requiring the hold time A typical AV will be 0 4 V Cy is the total bus capacitance per data line and I is the total leakage or three state current per data line The hold time will be tpgcay plus the minimum disable time 1 6 tpaTRwH for the write cycle REFERENCE SIGNAL tuEASURED MEASURED MEASURED MEASURED OUTPUT VoL MEASURED AV VoL MEASURED VoL MEASURED toecay OUTPUT STARTS DRIVING OUTPUT STOPS DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1 5V Figure 25 Output Enable lo OUTPUT 1 5V Figure 26 Equivalent Device Loading for Measure ments Includes All Fixtures INPUT OR 1 5V 1 5V OUTPUT Figure 27 Voltage Referenc
39. ents one due to inter nal circuitry and one due to the switching of external output drivers Internal power dissipation depends on the sequence in which instructions execute and the data operands involved See Ipp calculation in Electrical Characteristics section Internal power dissipation is calculated this way Ippin X Vop The external component of total power dissipation is caused by the switching of output pins Its magnitude depends on the number of output pins that switch during each cycle O the maximum frequency at which the pins can switch f the load capacitance of the pins C the voltage swing of the pins Vpp The external component is calculated using Ox Cx x f The load capacitance should include the processor s package capacitance The frequency f includes driving the load high and then back low Address and data pins can drive high and low at a maximum rate of l tcy while in SDRAM burst mode Example Estimate PExT with the following assumptions a system with one bank of external memory 32 bit two x 16 SDRAM chips each with a control signal load of 3 pF and a data signal load of 4 pF external data writes occur in burst mode two every cycles a potential frequency of l tcx cycles s Assume 50 pin switching the external SDRAM clock rate is 60 MHz 2 tcx The equation is calculated for each class of pins that can dr
40. er CLKIN 0 5 2DT ns tMIENHG HBG Enable After CLKIN 2 0 2DT ns tMITRA Address Select Disable After CLKIN 3 0 4DT ns tMITRS Strobes Disable After CLKIN 4 0 4DT ns MITRHG HBG Disable After CLKIN 5 5 4 DT ns tDATEN Data Enable After CLKIN2 10 0 5 DT ns tpATTR Data Disable After CLKIN 1 0 2 DT 7 0 2 DT ns tACKEN ACK Enable After CLKIN 75 4 ns tACKTR ACK Disable After CLKIN 1 0 2DT 6 0 2DT ns tMTRHBG Memory Interface Disable Before HBG Low 2 0 2DT ns tMENHBG Memory Interface Enable After HBG High 15 75 DT ns NOTES Strobes RD WR SW DMAG In addition to bus master transition cycles these specs also apply to bus master and bus slave synchronous read write 3Memory Interface Address RD WR MSx SW DMAGx BMS in EPROM boot mode 26 REV C ADSP 21065L CLKIN tstsck VAAAAAAAA NANAAAAAA V sers XA twmENA t MIENS MENHG turrra t MITRS t MITRHG 1222 2234 INTERFACE C t tpATTR toAreN i lt tAcKTR MTRHBG Fe tuENHBG MEMORY INTERFACE MEMORY INTERFACE ADDRESS RD WR MSx SW DMAGx BMS IN EPROM BOOT MODE Figure 17 Three State Timing REV C 27 ADSP 21065L DMA Handshake These specifications describe the three DMA handshake modes In all three modes DMAR is used to initiate transfers For hand shake mode DMAG controls the latching or enabling of data externally For external handsha
41. h Both if the internal wait state is zero For the second and subsequent cycles of a wait stated external memory access synchronous specifications and tyacxc must be met for wait state modes External Either or Both Both after internal wait states have completed 3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads 18 REV C ADSP 21065L CLKIN Z f gt 58 VAAAAAAAANAAAAAAA EI 4 gt TIX READ CYCLE lt lt tpnpo RD tuspati tsspati gt DATA IN WRITE CYCLE lt tpRwL lt WR tpatrR tpparo 001 COO Figure 13 Synchronous Read Write Bus Master REV 19 ADSP 21065L Synchronous Read Write Bus Slave Use these specifications for ADSP 21065L bus master accesses of a slave s IOP registers or internal memory in multiprocessor memory space The bus master must meet these bus slave timing requirements Parameter Min Max Unit Timing Requirements tSADRI Address SW Setup Before CLKIN 24 5 25 DT ns tHADRI Address SW Hold Before CLKIN 4 0 ns RD WR Low Setup Before 21 0 21 DT ns HRWLI RD WR Low Hold After CLKIN 2 50 5 DT 7 5 ns tRWHPI RD WR Pulse High
42. he serial ports and two via the processor s external port for either host processor other ADSP 21065L memory or REV ADSP 21065L I O transfers Programs can be downloaded to the ADSP 21065L using DMA transfers Asynchronous off chip peripherals can control two DMA channels using DMA Request Grant lines DMAR Other DMA features include interrupt generation on completion of DMA transfers and DMA chaining for automatically linked DMA transfers Serial Ports The ADSP 21065L features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed signal peripheral devices The serial ports can operate at 1x clock frequency providing each with a maximum data rate of 33 Mbit s Each serial port has a primary and a secondary set of transmit and receive channels Independent transmit and receive functions provide greater flexibility for serial communications Serial port data can be automatically transferred to and from on chip memory via DMA Each of the serial ports supports three operation modes DSP serial port mode PS mode an interface commonly used by audio codecs and TDM Time Division Multiplex multichannel mode The serial ports can operate with little endian or big endian transmission formats with selectable word lengths of 3 bits to 32 bits They offer selectable synchronization and transmit modes and optional A law companding Serial port cl
43. hese specifications for asynchronous interfacing to memories and memory mapped peripherals without reference to CLKIN These specifications apply when the ADSP 21065L is the bus master when accessing external memory space These switching characteristics also apply for bus master synchronous read write timing see Synchronous Read Write Bus Master below If these timing requirements are met the synchronous read write timing can be ignored and vice versa An exception to this is the ACK pin timing requirements as described in the note below Parameter Min Max Unit Timing Requirements tpAAK ACK Delay from Address 24 0 30DT W ns tpsAK ACK Delay from WR Low 19 5 24DT W ns Switching Characteristics tpAwH Address Selects to WR Deasserted 29 0 31 ns tDAWL Address Selects to WR Low2 3 5 6DT ns tww WR Pulsewidth 24 5 25 ns tppwH Data Setup Before WR High 15 5 19 DT ns tpwHA Address Hold After WR Deasserted 0 0 1DT H ns tpaTRWH Data Disable After WR Deasserted 10 1DT H 40 1DT H ns twwr WR High to WR RD Low 45 7DT H ns WR High to DMAGx Low 11 0 13DT H ns tpDWR Data Disable Before WR or RD Low 3 5 6 ns twpE WR Low to Data Enabled 45 6 DT ns W number of wait states specified in WAIT register X tcx H tcx if an address hold cycle occurs as specified in WAIT register otherwise H 0 I tcx if a bus idle cycle occurs as specified in WAIT register otherwise I
44. idirectional pins ADDR2 RD WR SW FLAG o HBG REDY DMAGI DMAG2 1 CPA TCLKO TCLK1 RCLK0 RCLK1 50 TFS1 RFSI DTOA DT1A DTOB DT1B XTAL BMS EMU BMSTR EVENTO EVENTI RAS CAS DQM SDWE SDCLKO0 SDCLK1 SDCKE SDA10 4 See Output Drive Currents for typical drive current capabilities 5 Applies to input pins ACK SBTS HBR CS DMARI DMAR2 BSEL CLKIN RESET TCK Note that ACK is pulled up internally with 2 during reset in a multiprocessor system when ID 01 and another ADSP 21065L is not requesting bus mastership to input pins with internal pull ups DROA DR1A DROB DRIB TRST TMS TDI 7Applies to three statable pins ADDR 3 9 MS j RD WR SW REDY DMAG DMAG BMS RAS CAS DQM SDWE SDCLKO0 SDCLKI SDCKE SDA10 and EMU Note that ACK is pulled up internally with 2 during reset in a multiprocessor system when ID 01 and another ADSP 21065L is not requesting bus mastership Applies to three statable pins with internal pull ups DTOA DT1A DTOB DT1B TCLK1 RCLKI Applies to CPA pin 10 to ACK pin when pulled up Applies to ACK pin when keeper latch enabled 12 Guaranteed but not tested 15 Applies to all signal pins Specificatio
45. ive Table V External Power Calculations A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation Ippin see calculation in Electrical Characteristics section Prorat X Vpp Note that the conditions causing worst case differ from those causing a worst case PINT Maximum cannot occur while 100 of the output pins are switching from all ones 1s to all zeros 0s Note also that it is not common for an appli cation to have 100 or even 50 of the outputs switching simultaneously ENVIRONMENTAL CONDITIONS Thermal Characteristics The ADSP 21065L is offered in a 208 lead MQFP and a 196 ball Mini BGA package The ADSP 21065L is specified for a case temperature Tease To ensure that Tcasg is not exceeded an air flow source may be used PD x 0c4 Tcasg Case temperature measured on top surface of package PD Power Dissipation in W this value depends upon the specific application a method for calculating PD is shown under Power Dissipation 7 1 C W for 208 lead 5 1 C W for 196 ball Mini BGA Airflow Table VI Thermal Characteristics 208 Lead MQFP Linear Ft Min 0 100 200 400 600 cA C W 24 20 19 17 13 Table VII 196 Ball Mini BGA us aeu Linear Ft Min 0 200 400 Type Pins Switching x C xf Vpp O
46. ke mode the data transfer is controlled by the ADDR 3 9 RD WR SW MS ACK and DMAG signals External mode cannot be used for transfers with SDRAM For Paced Master mode the data transfer is controlled by ADDR 3 9 RD WR MS o and ACK not DMAG For Paced Master mode the Memory Read Bus Master Memory Write Bus Master and Synchronous Read Write Bus Master timing specifications for ADDR RD WR 5 SW DATA and ACK also apply Parameter Min Max Unit Timing Requirements tSDRLC DMARx Low Setup Before CLKIN 5 0 ns tspRHC DMARx High Setup Before CLKIN 5 0 ns DMARx Width Low Nonsynchronous 6 0 ns tspATDGL Data Setup After DMAGx Low 15 0 20 DT ns tupATIDG Data Hold After DMAGx High 0 0 ns tpaTDRH Data Valid After DMARx High 25 0 14 DT ns tDMARIL DMARx Low Edge to Low Edge 18 0 14 DT ns tpMARH DMARx Width High 6 0 ns Switching Characteristics tppcL DMAG x Low Delay After CLKIN 14 0 10 DT 20 0 10 DT ns DMAG x High Width 10 0 12 DT HI ns twpGL DMAG x Low Width 16 0 20 DT ns DMAGx High Delay After CLKIN 0 0 2 DT 6 0 2 DT ns tpapGH Address Select Valid to DMAGx High 28 0 16 DT ns tppGHA Address Select Hold After DMAGx High 1 0 ns tvDATDGH Data Valid Before DMAGx High 16 0 20 DT ns tpaTRDGH Data Disable After DMAGx High 0 0 4 0 ns tpGWRL WR Low Before DMAGx Low 5 0 6 DT 8 0 6 DT ns tpGWRH DMAGx Low Before WR High 18 0 19DT W ns
47. max 300 mA Ippmrow Supply Current Internal 33 ns Vpp max 240 mA tcx 20 ns Vpp max 260 mA IppIDLE Supply Current IDLE 33 ns Vpp max 150 mA 30 ns Vpp max 155 mA IDDIDLE16 Supply Current IDLE16 Vpp max 50 mA NOTES 1The test program used to measure represents worst case processor operation and is not sustainable under normal application conditions Actual internal power measurements made using typical applications are less than specified 2IpbmHrcH is a composite average based on a range of high activity code 3Tppmtow is a composite average based on a range of low activity code IDLE denotes ADSP 21065L state during execution of IDLE instruction 5IDLE16 denotes ADSP 21065L state during execution IDLE16 instruction TIMING SPECIFICATIONS General Notes Two speed grades of the ADSP 21065L are offered 60 MHz and 66 MHz instruction rates The specifications shown are based on a CLKIN frequency of 30 MHz tcx 33 3 ns The DT derating allows specifications at other CLKIN frequencies within the min max range of the specification see Clock Input below DT is the difference between the actual CLKIN period and a CLKIN period of 33 3 ns DT 33 3 32 Use the exact timing information given Do not attempt to derive parameters from the addition or subtraction of others While addi tion or subtraction would yield meaningful results for an individual devic
48. mbly Code Insert Break Points Set Watch Points Trace Bus Activity Profile Program Execution Fill and Dump Memory Create Custom Debugger Windows The Visual IDE enables you to define and manage multiuser projects Its dialog boxes and property pages enable you to configure and manage all of the SHARC Development Tools This capability enables you to Control how the development tools process inputs and gen erate outputs Maintain a one to one correspondence with the tool s com mand line switches The EZ ICE Emulator uses the IEEE 1149 1 JTAG test access port of the ADSP 21065L processor to monitor and control the target board processor during emulation The EZ ICE provides full speed emulation allowing inspection and modification of memory registers and processor stacks Nonintrusive in circuit emulation is assured by the use of the processor s JTAG inter face the emulator does not affect target system loading or timing In addition to the software and hardware development tools available from Analog Devices third parties provide a wide range of tools supporting the SHARC processor family Hard ware tools include SHARC PC plug in cards multiprocessor SHARC VME boards and daughter and modules with multiple SHARCs and additional memory These modules are based on the SHARCPAC module specification Third Party software tools include an Ada compiler DSP libraries operating systems and block diagram design tool
49. nMMS value 1 2 tc x before RD or WR goes low or by tupogcsv after HBG goes low This is easily accomplished by driving an upper address signal high when HBG is asserted See Host Inter face in the ADSP 21065L SHARC User s Manual Second Edition 24 REV C ADSP 21065L READ CYCLE u WWW tsapRDL 4 thApRDH twnwh gt RD tupaRwH DATA OUT torDHRDY lt tspATRDY gt lt torpyRDL REDY O D REDY A D WRITE CYCLE AAA AAA ASA BABA tscswRL tsapwRH thcswRH cs XOXO IDDDOCOCODODVV twwRL twnwH m tupATwH lt tspaTwH gt DATA 0N 1 tpwnHRDY 6 tpapvwRL 9279 gt REDY O D REDY A D O D OPEN DRAIN A D ACTIVE DRIVE Figure 16 Asynchronous Read Write Host to ADSP 21065L REV 25 ADSP 21065L Three State Timing Bus Master Bus Slave HBR SBTS These specifications show how the memory interface is disabled stops driving or enabled resumes driving relative to CLKIN and the SBTS pin This timing is applicable to bus master transition cycles BTC and host transition cycles HTC as well as the SBTS pin Parameter Min Max Unit Timing Requirements tsTSCK SBTS Setup Before CLKIN 7 0 8DT ns tHTSCK SBTS Hold Before CLKIN 10 8DT ns Switching Characteristics tMIENA Address Select Enable After CLKIN 1 0 2DT ns tMIENS Strobes Enable Aft
50. ns subject to change without notice ABSOLUTE MAXIMUM RATINGS Storage Temperature Range 65 C to 150 C Supply Voltage 03 94 6 V Lead Temperature 5 seconds 280 C Input Voltage V duo MU RE 0 5 V to Vpp 0 5 V Stresses greater than those listed above may cause permanent damage to the device Output Voltage Swing 0 5 V to Vpp 0 5 V These are stress ratings only functional operation of the device at these or any other Load Capacitance coi fer iN EOS RS 200 pF conditions greater than those indicated in the operational sections of this specifica Junction Temperature Under Bias 130 C tion is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily I accumulate on the human body and test equipment and can discharge without detection Although WARNING we the ADSP 21065L features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality SENSITIVE DEVICE 12 REV C ADSP 21065L POWER DISSIPATION ADSP 21065L These specifications apply to the internal power portion of V
51. nts FLAG IN Setup Before SDCLK High 2 0 ns tHFI 1 013 Hold After SDCLK High 6 0 ns Switching Characteristics FLAG 4O0UT Delay After SDCLK High 1 0 ns FLAG OUT Hold After SDCLK High 4 0 ns tpFoE SDCLK High to FLAG OUT Enable 4 0 ns tpEoD SDCLK High to FLAG OUT Disable 1 75 ns NOTE 1Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle SDCLK FLAG gOUT SDCLK XX Figure 10 Flags REV C 15 ADSP 21065L Memory Read Bus Master Use these specifications for asynchronous interfacing to memories and memory mapped peripherals without reference to CLKIN These specifications apply when the ADSP 21065L is the bus master when accessing external memory space These switching characteristics also apply for bus master synchronous read write timing see Synchronous Read Write Bus Master below If these timing requirements are met the synchronous read write timing can be ignored and vice versa An exception to this is the ACK pin timing requirements as described in the note below Parameter Min Max Unit Timing Requirements tpAD Address Selects Delay to Data Valid 2 28 0 32 DT W ns tpRID RD Low to Data Valid 24 0 26DT W ns tupA Data Hold from Address Selects 0 0 ns Data Hold from RD High 0 0 ns tDAAK ACK Delay from Address Selects 3 24 0 30
52. ocks and frame syncs can be internally or externally generated The serial ports also include keyword and keymask features to enhance interprocessor communication Programmable Timers and General Purpose I O Ports The ADSP 21065L has two independent timer blocks each of which performs two functions Pulsewidth Generation and Pulse Count and Capture In Pulsewidth Generation mode the ADSP 21065L can gener ate a modulated waveform with an arbitrary pulsewidth within a maximum period of 71 5 secs In Pulse Counter mode the ADSP 21065L can measure either the high or low pulsewidth and the period of an input waveform The ADSP 21065L also contains twelve programmable general purpose I O pins that can function as either input or output As output these pins can signal peripheral devices as input these pins can provide the test for conditional branching Program Booting The internal memory of the ADSP 21065L can be booted at system power up from an 8 bit EPROM a host processor or external memory Selection of the boot source is controlled by the BMS Boot Memory Select and BSEL EPROM Boot pins Either 8 16 or 32 bit host processors can be used for booting For details see the descriptions of the BMS and BSEL pins in the Pin Descriptions section of this data sheet Multiprocessing The ADSP 21065L offers powerful features tailored to multi processing DSP systems The unified address space allows direct interprocessor
53. pp only See the Power Dissipation section of this data sheet for calcula tion of external supply current and total supply current For a complete discussion of the code used to measure power dissipation see the technical note SHARC Power Dissipation Measurements Specifications are based on the following operating scenarios Table II Internal Current Measurements Peak Activity High Activity Operation IppiwpEAx ppiuicn Low Activity IpprxLow Instruction Type Multifunction Multifunction Single Function Instruction Fetch Cache Internal Memory Internal Memory Core Memory Access 2 per Cycle DM and PM 1 per Cycle DM None Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles To estimate power consumption for a specific application use the following equation where is the amount of time your program spends in that state PEAK Ippmpgak HIGH X LOW IppiNtow IDLE POWER CONSUMPTION See note 4 below Table III OR PEAK x Ippmprax HIGH LOW x Ippintow IDLE16 x POWER CONSUMPTION See note 5 below Table III Table III Internal Current Measurement Scenarios Parameter Test Conditions Max Unit DDINPEAK Supply Current Internal tcx 33 ns Vpp max 470 mA 30 ns max 510 mA IDDINHIGH Supply Current Internal 33 ns max 275 mA 30 ns
54. ry register sets 16 secondary The DAGs automatically handle address pointer wraparound reducing overhead increasing perfor mance and simplifying implementation Circular buffers can start and end at any memory location Flexible Instruction Set The 48 bit instruction word accommodates a variety of parallel operations for concise programming For example the ADSP 21065L can conditionally execute a multiply an add a subtract and a branch all in a single instruction ADSP 21065L FEATURES The ADSP 21065L is designed to achieve the highest system throughput to enable maximum system performance It can be clocked by either a crystal or a TTL compatible clock signal The ADSP 21065L uses an input clock with a frequency equal to half the instruction rate a 33 MHz input clock yields a 15 ns processor cycle which is equivalent to 66 MHZ Inter faces on the ADSP 21065L operate as shown below Hereafter in this document 1x input clock frequency and 2x processor s instruction rate The following clock operation ratings are based on 1x 33 MHz instruction rate core 66 MHz SDRAM 66 MHz External SRAM 33 MHz Serial Ports 33 MHz Multiprocessing 33 MHz Host Asynchronous 33 MHz Augmenting the ADSP 21000 family core the ADSP 21065L adds the following architectural features Dual Ported On Chip Memory The ADSP 21065L contains 544 Kbits of on chip SRAM organized into two banks Bank 0 has 288 Kbits and Bank 1 has
55. s Additional Information For detailed information on the ADSP 21065L instruction set and architecture see the ADSP 21065L SHARC User s Manual Third Edition and the ADSP 21065L SHARC Technical Reference EZ ICE and VisualDSP are registered trademarks of Analog Devices Inc SHARCPAC is a trademark of Analog Devices Inc ADSP 21065L ADSP 21065L 2 DATA3 1 0 CONTROL SPORTO SPORT1 ADSP 21065L CLKIN cs BOOT EPROM RESET OPTIONAL ID1 0 PROCESSOR OPTIONAL 2 gt gt 2 2 7 SDRAM OPTIONAL Figure 3 Multiprocessing System REV C ADSP 21065L PIN DESCRIPTIONS ADSP 21065L pin definitions are listed below Inputs identified as synchronous S must meet timing requirements with respect to CLKIN or with respect to TCK for TMS TDT Inputs identified as asynchronous A can be asserted asynchronously to CLKIN or to TCK for TRST Unused inputs should be tied or pulled to VDD or GND except SW and inputs that have internal pull up or pull down resistors CPA ACK DTxX DRxX TCLKx RCLKx TMS and TDI these pins can be left float ing These pins have a logic level hold circuit that prevents the input from floating internally I Input S Synchronous P Power Supply O D Open Drain O Output A Asynchronous G Ground A D Active Drive T Three state when SBTS is assert
56. s to ID 00 in single processor systems These lines are a system configuration selection which should be hard wired or changed only at reset CPA O D IO Core Priority Access Asserting its CPA pin allows the core processor of an ADSP 21065L bus slave to interrupt background DMA transfers and gain access to the external bus CPA is an open drain output that is connected to both ADSP 21065Ls in the system The CPA pin has an internal 5 kQ pull up resistor If core access priority is not required in a system leave the CPA pin unconnected DTxX O Data Transmit Serial Ports 0 1 Channels A B Each DTxX pin has a 50 kQ internal pull up resistor DRxX I Data Receive Serial Ports 0 1 Channels A B Each DRxX pin has a 50 kQ internal pull up resistor TCLKx IO Transmit Clock Serial Ports 0 1 Each TCLK pin has a 50 kQ internal pull up resistor RCLKx IO Receive Clock Serial Ports 0 1 Each RCLK pin has a 50 kQ internal pull up resistor TFSx IO Transmit Frame Sync Serial Ports 0 1 RFSx IO Receive Frame Sync Serial Ports 0 1 BSEL I EPROM Boot Select When BSEL is high the ADSP 21065L is configured for booting from an 8 bit EPROM When BSEL is low the BSEL and BMS inputs determine booting mode See BMS for details This signal is a system configuration selection which should be hardwired 8 REV C ADSP 21065L Pin Type Function BMS CLKIN RESET TCK TMS TDI TDO TRST EMU O D
57. ss after HBR and CS asserted ADDR 3 must be a nonMMS value 1 2 tcx before RD or WR goes low or by after HBG goes low This is easily accomplished by driving an upper address signal high when HBG is asserted See the Host Processor Control of the ADSP 21065L section of the ADSP 21065L SHARC User s Manual Second Edition Only required for recognition in the current cycle 3CPA assertion must meet the setup to CLKIN deassertion does not need to meet the setup to CLKIN O D open drain A D active drive 22 REV C ADSP 21065L CLKIN suani gt lHHBRI 46 oun T tosno thero gt OUT QUA CPA OUT RE F E e m E 15 E 0 0 lt HBG IN tseRi gt tiern 4 BRx IN CPA IN O D BR cs tTRDYHG gt REDY 0 0 lt REDY A D theGRcsv HBG OUT O D OPEN DRAIN A D ACTIVE DRIVE 9598 Figure 15 Multiprocessor Bus Request and Host Bus Request REV C 23 ADSP 21065L Asynchronous Read Write Host to ADSP 21065L Use these specifications for asynchronous host processor accesses of an ADSP 21065L after the host has asserted CS and HBR low After the ADSP 21065L returns HBG the host can
58. tates to a synchronous access of its IOP registers In a multiprocessor system a slave ADSP 21065L deasserts the bus master s ACK input to add wait state s to an access of its IOP registers The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven SBTS 1 5 Suspend Bus Three State External devices can assert SBTS to place the external bus address data selects and strobes but not SDRAM control pins in a high impedance state for the following cycle If the ADSP 21065L attempts to access external memory while SBTS is as serted the processor will halt and the memory access will not finish until SBTS is deasserted SBTS should only be used to recover from host processor ADSP 21065L deadlock VA Interrupt Request Lines May be either edge triggered or level sensitive FLAG I O A Flag Pins Each is configured via control bits as either an input or an output As an input it can be tested as a condition As an output it can be used to signal external peripherals REV 7 ADSP 21065L Pin Type Function HBR VA Host Bus Request Must be asserted by a host processor to request control of the ADSP 21065L s external bus When HBR is asserted in a multiprocessing system the ADSP 21065L that is bus master will relinquish the bus and assert HBG To relinquish the bus the ADSP 21065L places the address data select and strobe lines in a
59. tes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT But terfly Computation 1024 Point Complex FFT Benchmark 0 274 ms 18 221 Cycles DUAL PORTED SRAM JTAG TWO INDEPENDENT d TEST amp DUAL PORTED BLOCKS EMULATION VO PORT DATA ADDR DATA EXTERNAL PORT SDRAM 1 INTERFACE 48 PM DATA BUS 16 x 40 BIT MULTIPLIER Sir us eae eae W aii ii a ii i IIIlI C lt I H gt aS I DATA BUS 20 40 DM DATA BUS s ESSI CI m mux ADDR BUS A IOP REGISTERS MEMORY MAPPED 2 Rx 2Tx PUS NN E EE 25 STATUS 2 Rx 2 DATA BUFFERS K 25 PORT SPORT 1 PROCESSOR Figure 1 Functional Block Diagram SHARC is a registered trademark of Analog Devices Inc REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326
60. ting tie BTRST to GND and tie or pull up BTCK to Vpp The TRST pin must be asserted after power up through BTRST on the connector or held low for proper operation of the ADSP 2106x None of the Bxxx pins Pins 5 7 9 11 are connected on the EZ ICE probe The JTAG signals are terminated on the EZ ICE probe as follows Signal Termination TMS Driven through 22 Q resistor 16 mA driver TCK Driven at 10 MHz through 22 Q resistor 16 mA driver TRST Driven through 22 Q resistor 16 mA driver pulled up by on chip 20 kQ resistor TDI Driven by 22 Q resistor 16 mA driver TDO One TTL load Split Termination 160 220 CLKIN One TTL load Split Termination 160 220 Caution Do not connect to CLKIN if internal XTAL oscillator is used EMU Active Low 4 7 kQ pull up resistor one TTL load open drain output from ADSP 2106xs TRST is driven low until the EZ ICE probe is turned on by the emulator at software start up After software start up TRST is driven high REV Connecting CLKIN to Pin 4 of the EZ ICE header is optional The emulator only uses CLKIN when directed to perform operations such as starting stopping and single stepping two ADSP 21065Ls in a synchronous manner If you do not need these operations to occur synchronously on the two processors simply tie Pin 4 of the EZ ICE header to ground For systems which use the internal clock generator and an external discrete crystal do not directl
61. tion with CAS MSx SDWE SDCLKx and sometimes SDA10 defines the operation for the SDRAM to perform SDRAM Write Enable In conjunction with CAS RAS MSx SDCLKx and sometimes SDA10 defines the operation for the SDRAM to perform SDRAM Data Mask In write mode DQM has a latency of zero and is used to block write operations SDRAM 2x Clock Output In systems with multiple SDRAM devices connected in parallel supports the corresponding increased clock load requirements eliminating need of off chip clock buffers Either SDCLK or both SDCLKx pins can be three stated SDRAM Clock Enable Enables and disables the CLK signal For details see the data sheet supplied with your SDRAM device REV C ADSP 21065L Pin Type Function SDA10 O T SDRAM A10 Pin Enables applications to refresh an SDRAM in parallel with a host access XTAL O Crystal Oscillator Terminal Used in conjunction with CLKIN to enable the ADSP 21065L s internal clock generator or to disable it to use an external clock source See CLKIN EVENT I O A PWM Output Event Capture In PWMOUT mode is an output pin and functions as a timer counter In WIDTH CNT mode is an input pin and functions as a pulse counter event capture VDD P Power Supply nominally 3 3 V dc 33 pins GND G Power Supply Return 37 pins NC Do Not Connect Reserved pins that must be left open and unconnected 7 pins CLOCK SIGNALS The ADSP 21065L can use an external clock
62. tions The SHARC Super Harvard Architecture offers the highest levels of performance and memory integration of any 32 bit DSP in the industry they are also the only DSP in the industry that offer both fixed and floating point capabilities without compromising precision or performance The ADSP 21065L is fabricated in a high speed low power CMOS process 0 35 um technology With its on chip instruc tion cache the processor can execute every instruction in a single cycle Table I lists the performance benchmarks for the ADSP 21065L The ADSP 21065L SHARC combines a floating point DSP core with integrated on chip system features including a 544 Kbit SRAM memory host processor interface DMA con troller SDRAM controller and enhanced serial ports Figure 1 shows a block diagram of the ADSP 21065L illustrat ing the following architectural features Computation Units ALU Multiplier and Shifter with a Shared Data Register File Data Address Generators DAG1 DAG2 Program Sequencer with Instruction Cache Timers with Event Capture Modes On Chip dual ported SRAM External Port for Interfacing to Off Chip Memory and Peripherals Host Port and SDRAM Interface DMA Controller Enhanced Serial Ports JTAG Test Access Port Table I Performance Benchmarks Benchmark Timing Cycles Cycle Time 15 00 ns 1 1024 Pt Complex FFT Radix 4 with Digit Reverse 0 274 ns 18221 Matrix Multiply Pipelined 3 x 3 x 3 x 1
63. tpGWRR WR High Before DMAGx High 0 75 1 DT 3 0 1 DT ns RD Low Before DMAGx Low 5 0 8 0 ns tikpat RD Low Before DMAGx High 24 0 26 DT W ns tpGRDR RD High Before DMAGx High 0 0 2 0 ns tpcwr DMAGx High to WR RD Low 5 0 6DT HI ns W number of wait states specified in WAIT register tcx tcx if an address hold cycle or bus idle cycle occurs as specified in WAIT register otherwise 0 NOTES 1Only required for recognition in the current cycle tepaTpar is the data setup requirement if DMARsx is not being used to hold off completion of a write Otherwise if DMARx low holds off completion of the write the data can be driven after DMARx is brought high is valid if DMARx is not being used to hold off completion of a read If DMARx is used to prolong the read then typarpcu 8 9 DT n x tex where equals the number of extra cycles that the access is prolonged 4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads 28 REV C ADSP 21065L CLKIN 1 tspric tpwARLL lt tspruc gt twr 1 tomarH DMARx tupac e I gt _ n I DMAGx TRANSFERS BETWEEN ADSP 2106x INTERNAL MEMORY AND EXTERNAL DEVICE gt tvpaTpGH gt DATA FROM ADSP 2106x TO EXTERNAL DEVICE
64. ttle additional hardware Supporting asynchronous transfers at speeds up to 1x clock frequency the host interface is accessed through the ADSP 21065L s external port Two channels of are available for the host interface code and data trans fers are accomplished with low software overhead The host processor requests the ADSP 21065L s external bus with the host bus request HBR host bus grant HBG and ready REDY signals The host can directly read and write the IOP registers of the ADSP 21065L and can access the DMA channel setup and mailbox registers Vector interrupt support enables efficient execution of host commands Controller The ADSP 21065L s on chip DMA controller allows zero overhead nonintrusive data transfers without processor inter vention The DMA controller operates independently and invisibly to the processor core allowing DMA operations to occur while the core is simultaneously executing its program instructions transfers can occur between ADSP 21065L s internal memory and either external memory external peripherals or a host processor DMA transfers can also occur between the ADSP 21065L s internal memory and its serial ports DMA transfers between external memory and external peripheral devices are another option External bus packing to 16 32 or 48 bit internal words is performed during DMA transfers Ten channels of DMA are available on the ADSP 21065L eight via t
65. ual to 2x CLKIN CLKIN may not be halted changed or operated below the specified frequency Processor Reset Resets the ADSP 21065L to a known state and begins execution at the program memory location specified by the hardware reset vector address This input must be asserted at power up Test Clock JTAG Provides an asynchronous clock for JTAG boundary scan Test Mode Select JTAG Used to control the test state machine TMS has 20 internal pull up resistor Test Data Input Provides serial data for the boundary scan logic TDI has a 20 internal pull up resistor Test Data Output JTAG Serial scan output of the boundary scan path Test Reset JTAG Resets the test state machine TRST must be asserted pulsed low after power up or held low for proper operation of the ADSP 21065L TRST has a 20 kQ internal pull up resistor Emulation Status Must be connected to the ADSP 21065L EZ ICE target board connector only Bus Master Output In a multiprocessor system indicates whether the ADSP 21065L is cur rent bus master of the shared external bus The ADSP 21065L drives BMSTR high only while it is the bus master In a single processor system ID 00 the processor drives this pin high SDRAM Column Access Strobe Provides the column address In conjunction with RAS MSx SDWE SDCLKx and sometimes SDA10 defines the operation for the SDRAM to perform SDRAM Row Access Strobe Provides the row address In conjunc
66. y connect the CLKIN pin to the JTAG probe This will load the oscillator circuit and possibly cause it to fail to oscillate Instead the JTAG probe s CLKIN can be driven by the XTAL pin through a high impedance buffer If synchronous multiprocessor operations are needed and CLKIN is connected clock skew between multiple ADSP 2106x processors and the CLKIN pin on the EZ ICE header must be minimal If the skew is too large synchronous operations may be off by one cycle between processors For synchronous multi processor operation TCK TMS CLKIN and EMU should be treated as critical signals in terms of skew and should be laid out as short as possible on your board If synchronous multiprocessor operations are not needed 1 CLKIN is not connected just use appropriate parallel termina tion on TCK and TMS TDI TDO EMU and TRST are not critical signals in terms of skew For complete information on the SHARC EZ ICE see the ADSP 21000 Family JTAG EZ ICE User s Guide and Reference 11 ADSP 21065L SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Test C Grade K Grade Parameter Conditions Min Max Min Max Unit Vpp Supply Voltage 3 13 3 60 3 13 3 60 V TcasE Case Operating Temperature 40 100 0 85 C Vin High Level Input Voltage Vpp max 2 0 Vpp 0 5 2 0 Vdp 0 5 V Vna Low Level Input Voltage Vpp min 0 5 0 8 0 5 0 8 V Low Level Input Voltage2 min 0 5 0 7 0 5 0 7 V

ADSP-21065L DSP Microcomputer Data Sheet

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