ADSP-2181 data sheet
Contents
1. 0 3 to Vpp 0 3 V Output Voltage Swing 0 3 V to Vpp 0 3 V Operating T emperature Range Ambient 40 to 85 C Storage T emperatureRange 65 to 150 Lead T emperature 5 sec 280 ead T emperature 5 sec 280 Stresses above those listed under Absolute M aximum Ratings may cause perma nent damage to the device T hese are stress ratings only functional operation of thedevice attheseor any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY TheADSP 2181 is an ESD electrostatic discharge sensitive device Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur to devices subjected to high energy electrostatic discharges The AD SP 2181 features proprietary ESD protection circuitry to dissipate high energy discharges Human Body M odel Per method 3015 of MIL ST D 883 the AD SP 2181 has been classified as a Class 1 device Proper ESD precautions are recommended to avoid performance degradation or loss of function WARNING ESD SENSITIVE DEVICE ality Unused devices must be stored in conductive foam or shunts and the foam should be discharge2. IAD 15 0 Data Setup before End of Write gt 5 ns pu IAD 15 0 Data Hold after End of Write 34 2 ns Switching Characteristic kuw Start of Write to IACK H igh 15 ns NOTES Start of Write IS Low and IWR Low 2 of Write IS High or IWR High Write Pulse ends before IACK Low use specifications tip su Write Pulse ends after IACK Low use specifications tixsy tu tkw ton tosu IAD15 0 Figure 15 IDMA Write Short Write Cycle REV D 21 ADSP 2181 Parameter Min Max Unit IDMA Write Long Write Cycle Timing R equirements kw IACK Low before Start of Write 0 ns tiksu IAD 15 0 Data Setup before IACK Low 3 0 5 10 ns IAD 15 0 Data Hold after IACK Low 3 2 ns Switching Characteristics tikLw Start of Write to IACK Low 1 5tcx ns kuw Start of Write to IACK H igh 15 ns NOTES IStart of Write IS Low and IWR Low f Write Pulse ends before IACK Low use specifications tipsy Write Pulse ends after IACK Low use specifications tix sy tiky T his is the earliest time for IACK L ow from Start of Write For IDM A Write cycle relationships please refer to the U ser s M anual TACK 5 WR miso Figure 16 IDMA Write Long Write Cycle 22 REV D ADSP 2181 Parameter Min Max Unit IDMA Read Long Read Cycle Timing R equirements tikr IACK Low before Start
3. xMS Setup before Write Start WR Low Address Setup 0 ty A0 A13 xMS Setup before Write End WR D easserted Address Hold Time A0 A13 xMS H old after WR D easserted D ata Setup before WR High D ata Hold after WR High RD Low to Data Valid A0 A13 xMS to Data Valid D ata Setup T ime tow Data Hold Time tox OE to Data Valid trop Address Access T ime ta xMS PMS DMS BMS CMS IOMS FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS is defined as 0 5tcx The ADSP 2181 uses an input clock with a frequency equal to half the instruction rate a 16 67 MHz input clock which is equivalent to 60 ns yields a 30 ns proces sor cycle equivalent to 33 M Hz values within the range of 0 5tc period should be substituted for all relevant timing pa rameters to obtain the specification value Example 0 5tck 7 ns 0 5 25 ns 7 ns 8 ns 13 ADSP 2181 Parameter Min Max Unit Clock Signals and Reset Timing Requirements tcki CLKIN Period 50 150 ns CLKIN Width Low 20 ns CLKIN Width High 20 ns Switching Characteristics CLKOUT Width Low Q 5tck 7 ns CLKOUT Width High Q 5tck 7 ns CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement tsp RESET Width L ow ns NOTE 1A pplies after power up sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN
4. 0028 Lowest Priority Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially Inter rupts can be masked or unmasked with the IM ASK register Individual interrupt requests are logically AN D ed with the bits in IM ASK the highest priority unmasked interrupt is then selected T he power down interrupt is nonmaskable TheADSP 2181 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register T his does not affect serial port autobuffering or DMA transfers he interrupt control register ICNTL controls interrupt nest ing and defines the IRQO and IRQ2 external interrupts to be either edge or level sensitive T he pin is an external edge sensitive interrupt and can be forced and cleared T he IRQLO and IRQLI pins are external level sensitive interrupts T heIFC register is a write only register used to force and clear interrupts On chip stacks preserve the processor status and are automati cally maintained during interrupt handling T he stacks are twelve levels deep to allow interrupt loop and subroutine nesting T hefollowing instructions allow global enable or disable servic ing of the interrupts including power down regardless of the state of IM ASK Disabling the interrupts does not affect serial port autobuffering or DM A ENA INTS DIS INTS W hen the processor is reset i
5. 2181 Basic System Configuration Clock Signals The ADSP 2181 can be clocked by either a crystal a TTL compatible clock signal TheCLKIN input cannot be halted changed during operation or operated below the specified frequency during normal opera tion T heonly exception is while the processor is in the power down state For additional information refer to Chapter 9 ADSP 2100 Family U se s M anual Third Edition for detailed information on this power down feature If an external clock is used it should be a T T L compatible signal running at half the instruction rate T he signal is con nected to the processor s CLKIN input When an external clock is used the XTAL input must be left unconnected The ADSP 2181 uses an input clock with a frequency equal to half the instruction rate a 20 00 M Hz input clock yields a 25 ns processor cycle which is equivalent to 40 M H z N ormally instructions are executed in a single processor cycle All device timing is relative to the internal instruction clock rate which is indicated by the CLK OUT signal when enabled Because the AD SP 2181 includes an on chip oscillator circuit an external crystal may be used T he crystal should be connected across the CLKIN and XT AL pins with two capacitors connected as shown in Figure 3 Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer A parallel resonant fundamental frequency microprocessor grad
6. High 0 ns trp TFS RF Soy Delay from SCLK High 15 ns tscpH DT Hold after SCLK High 0 ns trpE TFS Alt toDT Enable 0 ns TFS Alt to DT Valid 14 ns SCLK High to DT Disable 15 ns troy RFS Multichannel Frame D elay Zero to DT Valid 15 ns CLKOUT SCLK DR TFSin RFSin ma 180 try RFSout TFSour la lSCDV gt gt DT gt trov gt TFSour ALTERNATE FRAME MODE tov gt RFSour MULTICHANNEL MODE X FRAME DELAY 0 MFD 0 tre 4 gt trov gt TFSin ALTERNATE X FRAME MODE trov gt RFSin MULTICHANNEL MODE X FRAME DELAY 0 MFD 0 Figure 13 Serial Ports REV D 19 ADSP 2181 Parameter Min Max Unit IDMA Address Latch Timing equirenents trap Duration of Address L atch 10 ns tiasu IAD 15 0 Address Setup before Address L atch End 5 ns thay IAD 15 0 Address H old after Address L atch End 2 ns tika IACK Low before Start of Address Latch 0 ns tials Start of Write or Read after Address Latch End 3 3 ns NOTES 1Start of Address Latch IS Low and IAL High 2 of Address Latch 1 High or IAL Low 3Start of Write or Read IS Low and IWR Low or IRD Low TACK tka lt IAL 5 liasu 4 lian Figure 14 IDMA Address Latch 20 REV D ADSP 2181 Parameter Min Max Unit IDMA Write Short Write Cycle Timing Requirements tw TACK Low before Start of Write 0 ns D uration of Write 2 15 ns
7. Ox3FEO 0 2000 8K INTERNAL DMOVLAY 0 OR EXTERNAL 8K DMOVLAY 1 2 0 0000 Figure 6 Data Memory ADSP 2181 T here are 16 352 words of memory accessible internally when the DM OVLAY register is set to 0 When DM OVLAY is set to something other than 0 external accesses occur at addresses 0x0000 through Ox1FFF T he external address is generated as shown in T able lll Tablelll DMOVLAY Memory A13 120 0 Internal Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x0000 and Ox1F FF 2 External 1 13 LSBs of Address Overlay 2 Between 0x0000 Ox1F FF T his organization allows for two external 8K overlays using only the normal 14 address bits All internal accesses complete in one cycle Accesses to external memory are timed using the wait states specified by the D WAIT register Space The ADSP 2181 supports an additional external memory space called 1 0 space T his space is designed to support simple con nections to peripherals or to bus interface ASIC data registers 110 space supports 2048 locations T he lower eleven bits of the external address bus are used the upper three bits are unde fined T wo instructions were added to the core AD SP 2100 Family instruction set to read from and write to 1 0 memory space T 1 0 space also has four dedicated 3 bit wait state registers IOWAIT 0 3 which specify up to s
8. space consists of 256 pages each of which is 16K x 8 T he byte memory space on the AD SP 2181 supports read and write operations as well as four different data formats T he byte memory uses data bits 15 8 for data T he byte memory uses data bits 23 16 and address bits 13 0 to create a 22 bit address T his allows up to a 4 meg x 8 32 megabit ROM or RAM to be used without glue logic All byte memory accesses are timed by the BM WAIT register Byte Memory DMA BDMA T he Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one D SP cycle per 8 16 or 24 bit word transferred The BDMA circuit supports four different data formats which are selected by the BT Y PE register field T he appropriate num ber of 8 bit accesses are done from the byte memory space to build the word size selected T able V shows the data formats supported by the BDMA circuit Table V Internal BTYPE Memory Space Word Size Alignment 00 Program M emory 24 Full Word 01 D ata M emory 16 Full Word 10 D ata M emory 8 MSBs 11 D ata M emory 8 LSBs U nused bits in the 8 bit data memory formats are filled with Os The BIAD register field is used to specify the starting address for the on chip memory involved with the transfer T he 14 bit BEAD register specifies the st
9. 0 ARE TYPE 2 AND TYPE 6 AND 20 ARE IDLE INSTRUCTIONS Figure 21 Power vs Frequency 25 ADSP 2181 CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP 2181 25 N a RISE TIME 0 4V 2 4V ns 5 a 0 50 100 150 200 250 pF Figure 22 Range of Output Rise Time vs Load Capaci tance C at Maximum Ambient Operating Temperature 0 VALID OUTPUT DELAY OR HOLD ns 2 E 50 100 150 200 250 C pF Figure 23 Range of Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state T he out put disable time tps is the difference of tueasurep and tpgcav as shown in the Output Enable D isable diagram T he time is the interval from when a reference signal reaches a high or low volt age level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time tpecav is dependent on the capacitive load C and the current load on the output pin It can be approximated by the fol lowing equation C x0 5V toecay j L from which tbis ty EASURED toecay 26 is calculated If multiple pins such as the
10. 0x2000 and Ox3FFF 2 Externa 1 13 LSBs of Address Overlay 2 Between 0x2000 and Ox3FFF T his organization provides for two external 8K overlay segments using only the normal 14 address bits T his allows for simple program overlays using one of the two external segments in place of the on chip memory Care must be taken in using this overlay space in that the processor core i e the sequencer does not take into account the PM OVLAY register value example if a loop operation was occurring on one of the exter nal overlays and the program changes to another external over lay or internal memory an incorrect loop operation could occur In addition care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack For ADSP 2100 Family compatibility M M AP 1is allowed In this mode booting is disabled and overlay memory is dis abled PM OVLAY must be 0 Figure 5 shows the memory map in this configuration PROGRAM MEMORY ADDRESS Ox3FFF INTERNAL 8K PMOVLAY 0 MMAP 1 0x2000 0x1FFF 8K EXTERNAL 0x0000 Figure 5 Program Memory MMAP 1 Data Memory T he ADSP 2181 has 16 352 16 bit words of internal data memory In addition the ADSP 2181 allows the use of 8K external memory overlays Figure 6 shows the organization of the data memory DATA MEMORY 32 MEMORY MAPPED REGISTERS INTERNAL 8160 WORDS ADDRESS Ox3FFF
11. 4 D16 126 PF4 31 A10 63 EMS 95 D17 127 GND 32 A11 64 EE 96 D 18 128 IS REV D 29 ADSP 2181 128 1 PQFP Package Pinout PFO D22 WR D21 RD D20 IOMS D19 BMS D18 DMS D17 CMS D16 GND D15 VDD GND PMS VDD A0 GND 5 1281 014 p 28MM x 28MM Bi p TOP VIEW pn PINS DOWN oe A7 08 XTAL D7 CLKIN D6 GND D5 CLKOUT GNE GND 04 VDD D3 A8 D2 A9 A10 DO A11 VDD A12 BG A13 EBG IRQE BR MMAP EBR lQl wuxieraalele uweooocoeosolx n i x 55526 aoga DESEO R DO g9g9utu ma MARZ amp Fe 30 REV D ADSP 2181 PQFP Pin Configurations PQFP Pin PQFP Pin PQFP Pin PQFP Pin Number Name Number Name Number Name Number Name 1 PFO 33 PWD 65 EBR 97 D23 2 WR 34 IRQ2 66 BR 98 GND 3 RD 35 BMODE 67 EBG 99 IWR 4 IOMS 36 PWDACK 68 BG 100 IRD 5 BMS 37 IACK 69 VDD 101 IAD15 6 DMS 38 BGH 70 DO 102 IAD14 7 CMS 39 VDD 71 D1 103 IAD 13 8 GND 40 72 D2 104 14012 9 VDD 41 IRQLO 73 D3 105 IAD11 10 PMS 42 IRQLI 74 04 106 1AD10 11 43 FLO 75 GND 107 IAD9 12 A1 44 FL1 76 D5 108 IAD8 13 A2 45 FL2 71 D6 109 IAD7 14 A3 46 DTO 78 D7 110 IAD6 15 A4 47 TFSO 79 D8 111 VDD 16 A5 48 RFSO 80 09 112 GND 17 A6 49 DRO 81 D10 113 IAD5 18 7 50 SCLKO 82 D11 114 IADA 19 XTAL 51 DT 1 FO 83 D12 115 IAD3 20 CLKIN 52 TFSI IRQI 84 D13 116 1402 21 GND 53 RFSI IRQO 85 D14 117 IAD1 22 CLKOUT 54 GND 86 GND 118 IADO 23 GND 55 DRI F
12. ACH LEAD IS 0 05 0 002 0 58 0 023 0 27 0 011 WITHIN 20 008 FROM ITS IDEAL POSITION 1 50 0 059 0 42 0 017 0 17 0 007 WHEN MEASURED IN THE LATERAL DIRECTION 1 30 0 051 UNLESS OTHERWISE NOTED NOTE THE ACTUAL POSITION OF EACH LEAD IS WITHIN 08 0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION UNLESS OTHERWISE NOTED ORDERING GUIDE Part Number Ambient Temperature Range ADSP 2181K 51 115 ADSP 2181BST 115 5 2181 5 115 5 2181 5 115 ADSP 2181K ST 133 5 2181 5 133 5 2181 5 133 5 2181 5 133 5 2181 5 160 ADSP 2181K 5 160 0 to 70 40 to 85 0 to 70 40 to 85 0 to 70 C 40 to 85 0 to 70 40 to 85 0 to 70 0 to 70 C 5 Plastic Quad Flatpack PQFP ST Plastic Thin Quad Flatpack T QFP Instruction Rate Package Package MHz Description Options 28 8 128 Lead TQFP ST 128 28 8 128 Lead TQFP ST 128 28 8 128 L ead PQFP 5 128 28 8 128 L ead PQFP 5 128 33 3 128 Lead TQFP ST 128 33 3 128 Lead TQFP ST 128 33 3 128 L ead PQFP 5 128 33 3 128 L ead 5 128 40 128 Lead TQFP ST 128 40 128 L ead PQFP 5 128 32 REV D C2041c 3 3 98 PRINTED IN U S A
13. ANALOG DEVICES DSP Microcomputer ADSP 2181 FEATURES PERFORMANCE 25 ns Instruction Cycle Time from 20 MHz Crystal 9 5 0 Volts 40 MIPS Sustained Performance Single Cycle Instruction Execution Single Cycle Context Switch 3 Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP 2100 Family Code Compatible with Instruction Set Extensions 80K Bytes of On Chip RAM Configured as 16K Words On Chip Program Memory RAM 16K Words On Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16 Bit Interval Timer with Prescaler 128 Lead TQFP 128 Lead PQFP SYSTEM INTERFACE 16 Bit Internal DMA Port for High Speed Access to On Chip Memory 4 MByte Memory Interface for Storage of Data Tables and Program Overlays 8 Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe and Separate Memory Space Permits Glueless System Design Programmable W
14. I 2 L evel Sensitive Interrupt Requests 1 Edge Sensitive Interrupt Request BR 1 Bus Request Input BG 1 0 Bus Grant Output BGH 1 0 Bus Grant Hung Output PMS 1 0 Program M emory Select Output DMS 1 0 D ata emory Select Output BMS 1 0 Byte emory Select Output IOMS 1 0 110 Space emory Select Output CMS 1 0 Combined M emory Select O utput RD 1 0 M emory Read Enable Output WR 1 0 emory W rite Enable Output MMAP 1 emory M ap Select Input BMODE 1 Boot Option Control Input CLKIN XTAL 2 Clock or Quartz Crystal Input of Input Name s Output Function CLKOUT 1 0 Processor Clock Output SPORTO 5 1 0 Serial Port I O Pins SPORT1 5 1 0 Serial Port 1 or T wo External IRQs Flag and Flag Out IRD IWR 2 IDMA Port Read Write Inputs IS 1 IDMA Port Select IAL 1 IDMA Port Address L atch Enable IAD 16 1 0 IDMA Port Address D ata Bus JACK 1 0 IDMA Port Access Ready Acknowledge PWD 1 Power D own Control PWDACK 1 0 Power D own Control FLO FL1 FL2 3 0 Output Flags PF7 0 8 1 0 Programmable I O Pins EE 1 Emulator Only EBR 1 Emulator Only EBG 1 Emulator Only ERESET 1 Emulator Only EMS 1 Emulator Only EINT 1 Emulator Only ECLK 1 Emulator Only ELIN 1 Emulator Only ELOUT 1 Emulator Only GND 11 Ground Pins VDD 6 Power Supply Pins T hese ADSP 2181 pins must be connected only t
15. I 87 VDD 119 PF7 24 VDD 56 SCLK1 88 GND 120 PF6 25 A8 57 ERESET 89 D15 121 PF5 26 A9 58 RESET 90 D16 122 4 27 10 59 EMS 91 D17 123 GND 28 A11 60 EE 92 D18 124 IS 29 A12 61 ECLK 93 D19 125 IAL 30 A13 62 ELOUT 94 D20 126 PF3 31 IRQE 63 ELIN 95 D21 127 PF2 32 MMAP 64 EINT 96 D22 128 PF1 REV D 31 ADSP 2181 OUTLINE DIMENSIONS Dimensions shown in mm and inches 128 Lead Metric Plastic Quad Flatpack PQFP 128 Lead Metric Thin Plastic Quad Flatpack TQFP S 128 ST 128 31 45 1 238 16 25 0 640 30 95 1 219 15 75 0 620 4 07 28 10 1 106 1 60 0 063 14 10 0 555 0 160 27 90 1 098 13 90 0 547 MAX 24 87 0 979 lt gt 12 50 0 492 gt 0 75 0 030 1 1 03 0 041 24 73 0 974 045 01 Sr 128 0 65 0 031 D 1 102 Y SEATING SEATING PLANE PLANE 888849 A TOP VIEW 2 2 PINS DOWN g 2 5 TOP VIEW g 5 E PINS DOWN 5 9 gje NIN AN 2215 Bal als e 0 10 0 004 65 ___ Y MI Iji 000 0 25 0 010 gt 14 MIN 0 87 0 034 0 45 0 018 d 7 012 38 65 Y 3 67 0 144 0 73 0 029 0 30 0 012 0 004 5 l A ee 3 17 0 125 0 er 000 M gt lt 58 0 27 0 011 NOTE THE ACTUAL POSITION OF E
16. ITECTURE GENERAL DESCRIPTION TheADSP 2181 is a single chip microcomputer optimized for digital signal processing D SP and other high speed numeric processing applications TheADSP 2181 combines the AD SP 2100 family base archi tecture three computational units data address generators and a program sequencer with two serial ports a 16 bit internal DMA port a byte DM A port a programmable timer Flag 1 0 extensive interrupt capabilities and on chip program and data memory TheADSP 2181 integrates 80K bytes of on chip memory con figured as 16K words 24 bit of program RAM and 16K words 16 bit of data RAM Power down circuitry is also provided to meet the low power needs of battery operated portable equip ment The AD SP 2181 is available in 128 lead T QFP and 128 lead PQF P packages In addition the AD SP 2181 supports new instructions which include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding result free ALU operations 1 0 memory trans fers and global interrupt masking for increased flexibility Fabricated in a high speed double metal low power CM OS process the AD SP 2181 operates with a 25 ns instruction cycle time Every instruction can execute in a single processor cycle TheADSP 2181 s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera tions in parallel
17. Oca TQFP 50 C W 2 C W 48 C PQFP 41 C 10 C W 31 C W REV D 27 ADSP 2181 BGH BMODE PWDACK 1 OQajilj e waoooooo l ste Fe orc o 128 1 TQFP Package Pinout TOP VIEW PINS DOWN 28 rr Soin 4 10 0 5 ic ha a REV D ADSP 2181 TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 IAL 33 A12 65 ECLK 97 D19 2 PF3 34 A13 66 ELOUT 98 D 20 3 PF2 35 IRQE 67 ELIN 99 D21 4 1 36 68 100 022 5 PFO 37 PWD 69 EBR 101 D23 6 WR 38 IRQ2 70 BR 102 GND 7 RD 39 BMODE 71 EBG 103 IWR 8 IOMS 40 PWDACK 72 BG 104 IRD 9 BMS 41 IACK 73 VDD 105 IAD15 10 DMS 42 BGH 74 DO 106 IAD14 11 CMS 43 VDD 75 D1 107 IAD13 12 GND 44 GND 76 D2 108 IAD12 13 VDD 45 IRQLO 71 D3 109 IAD11 14 PMS 46 IRQLI 78 04 110 IAD10 15 47 FLO 79 GND 111 IAD9 16 A1 48 FL1 80 D5 112 IAD8 17 A2 49 FL2 81 D6 113 IAD7 18 A3 50 DTO 82 D7 114 IAD6 19 A4 51 TFSO 83 D8 115 VDD 20 A5 52 RFSO 84 D9 116 GND 21 A6 53 DRO 85 D10 117 IAD5 22 7 54 SCLKO 86 D11 118 4 23 XTAL 55 DT 1 FO 87 D12 119 IAD3 24 CLKIN 56 TFSI IRQI 88 D 13 120 1402 25 GND 57 RFSI IRQO 89 D14 121 IAD1 26 CLKOUT 58 GND 90 GND 122 IADO 27 GND 59 DRI FI 91 VDD 123 PF7 28 VDD 60 SCLK1 92 GND 124 PF6 29 A8 61 ERESET 93 D15 125 PF5 30 A9 62 RESET 9
18. R OUTPUT REGS Figure 1 ADSP 2181 Block Diagram INPUT REGS OUTPUT REGS REV D 3 TRANSMIT REG RECEIVE REG SERIAL PORTO TRANSMIT REG RECEIVE REG SERIAL PORTO ADSP 2181 SPORT s support serial data word lengths from 3 to 16 bits and provide optional A law and u law companding according to CCITT recommendation G 711 SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer SPORTS can receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer SPORT 0 has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed serial bitstream SPORT 1 can be configured to have two external interrupts IRQO and IRQI and the Flag In and Flag Out signals T he internally generated serial clock may still be used in this configuration Pin Descriptions The AD SP 2181 is available 128 lead T and 128 lead PQFP packages PIN FUNCTION DESCRIPTIONS Pin of Input Name s Pins Output Function Address 14 0 Address Output Pins for Program Data Byte and I O Spaces D ata 24 1 0 Data 1 0 Pins for Program and Data M emory Spaces 8 M SBs Are Also Used as Byte Space Addresses RESET 1 Processor Reset Input IRQ2 1 Edge evel Sensitive Interrupt Request IRQLO IRQL
19. TERFACE CHAPTER OF THE ADSP 2100 FAMILY USER S MANUAL THIRD EDITION FOR DETAILS 2 CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS Figure 20 Power Down Supply Current Typical REV D C x Vpp x is calculated for each output of Pins x C x Vpp xf Address DMS 8 x10pF x5 V x333MHz 66 6 mW Data Output WR 9 x10pF x5 V 16 67 MHz 37 5 mW RD 1 x10pF 5 x1667MHz 42mW CLKOUT 1 x10pF 5 x333MHz 83mW 116 6 mW T otal power dissipation for this example is 116 6 mW 2181 POWER 111 3 4 POWER mW 28 30 32 34 36 38 40 42 1 MHz POWER IDLE 2 3 E 1 u a a tc z 28 30 32 34 36 38 40 42 1 MHz 80 POWER IDLE n MODES3 IDLE E 1 a tc IDLE 16 IDLE 128 28 30 32 34 36 38 40 42 1 MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2IDLE REFERS TO ADSP 2181 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3TYPICAL POWER DISSIPATION AT 5 0V Vpp AND 25 C EXCEPT WHERE SPECIFIED MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY 50 OF THE INSTRUCTIONS ARE MULTIFUNCTION TYPES 1 4 5 12 13 14 3
20. acitance 12 13 Q 2 5 V fin 1 0 M Hz Tams 25 C 8 pF NOTES 1Bidirectional pins 00 0 23 RFSO 51 SCLK0 SCLK1 TFSO TFS1 A1 A13 PFO PF7 2Input only pins RESET BR DRO DR1 PWD 3Input only pins CLK IN RESET DRO DR1 PWD 40 utput pins BG PMS DMS BMS IOMS CMS RD WR PWDACK DT 1 CLKOUT FL2 0 5Although specified for TTL outputs all AD SP 2186 outputs are CM OS compatible and will drive to V pp and GND assuming no dc loads 66 uaranteed but not tested hree statable pins A0 A13 00 023 PMS DMS BMS IOMS CMS RD WR DT 1 SCLK0 SCLK 1 TFSO TFS1 RFSO RSF1 PFO PF7 80 V on BR CLKIN Inactive dle refers to AD SP 2181 state of operation during execution of IDLE instruction D easserted pins are driven to either V pp or GND 10 5p measurement taken with all instructions executing from internal memory 50 of the instructions multifunction types 1 4 5 12 13 14 30 are type 2 and type 6 and 20 are idle instructions Hy 0V 3 V For typical figures for supply currents refer to Power Dissipation section PApplies to T QF P and PQFP package types 130 utput pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice 12 REV D ADSP 2181 ABSOLUTE MAXIMUM RATINGS Supply 0 3 V to 7 V Input
21. ait State Generation Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On Chip Program Memory from Byte Wide Extemal Memory e g EPROM or Through Internal DMA Port Six Extemal Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling ICE Port Emulator Interface Supports Debugging in Final Systems ICE Port is a trademark of Analog D evices Inc REV D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM POWER DOWN PROGRAMMABLE CONTROL vo MEMORY FLAGS PROGRAM DATA BYTE DMA MEMORY MEMORY CONTROLLER Procram memory aporess T _ DL ll Ll MEMORY ADDRESS EXTERNAL DATA BUS oara ____ _ 1 barawEMoRvDarA DATA ADDRESS GENERATORS pac 1 2 PROGRAM SEQUENCER EXTERNAL ADDRESS BUS SERIAL PORTS ARITHMETIC UNITS INTERNAL DMA PORT ALU SHIFTER ADSP 2100 BASE ARCH
22. al address lines T his gives the BDM A Port an effective 22 bit address range On power up the D SP can automatically load bootstrap code from byte memory Space allows access to 2048 locations of 16 bit wide data It is intended to be used to communicate with parallel periph eral devices such as data converters and external registers or latches Program Memory TheADSP 2181 contains a 16K x 24 on chip program RAM T heon chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle In addition the AD SP 2181 allows the use of 8K external memory overlays T he program memory space organization is controlled by the MMAP pin and the PM OVLAY register Normally the ADSP 2181 is configured with M M AP 0 and program memory orga nized as shown in F igure 4 PROGRAM MEMORY ADDRESS Ox3FFF 8K INTERNAL PMOVLAY 0 MMAP 0 OR EXTERNAL 8K PMOVLAY 1 or 2 MMAP 0 0x2000 OxQFFF 8K INTERNAL 0x0000 Figure 4 Program Memory MMAP 0 T here are 16K words of memory accessible internally when the PM OVLAY register is set to 0 When PM OVLAY is set to something other than 0 external accesses occur at addresses 0x2000 through Ox3F FF T he external address is generated as shown in T able REV D Tablell PMOVLAY Memory A13 12 0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between
23. arting address for the external byte memory space T he 8 bit BM PAGE register specifies the start ing page for the external byte memory space T he BDIR register field selects the direction of the transfer Finally the 14 bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDM A circuit transfers BDMA accesses can cross page boundaries during sequential addressing A BDM A interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register TheBWCOUNT register is updated after each transfer so it can be used to check the status of the transfers When it reaches zero the transfers have finished and aBDM A interrupt is gener ated The BM PAGE and BEAD registers must not be accessed by the DSP during BDMA operations T he source or destination of a BDMA transfer will always be on chip program or data memory regardless of the values of M MAP OVLAY or DMOVLAY REV D ADSP 2181 When the BWCOUNT register is written with a nonzero value the BDM A circuit starts executing byte memory accesses with wait states set by BM WAIT T hese accesses continue until the count reaches zero When enough accesses have occurred to create a destination word it is transferred to or from on chip memory T he transfer takes one D SP cycle D SP accesses to external memory have priority over BDM A byte memory ac cesses TheBDMA Context Reset bit BCR controls whether the processor i
24. assembler mnemonics F or example a typical arithmetic add instruction such as AR AYO resembles a simple equation Every instruction assembles into a single 24 bit word that can execute in a single instruction cycle syntax is a superset AD SP 2100 F amily assembly lan guage and is completely source and object code compatible with other family members Programs may need to be relo cated to utilize on chip memory and conform to the AD SP 2181 s interrupt vector and reset vector map Sixteen condition codes are available For conditional jump call return or arithmetic instructions the condition can be checked and the operation executed in the same instruction cycle 10 Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle DESIGNING AN EZ ICE COMPATIBLE SYSTEM TheADSP 2181 hason chip emulation support and an ICE Port a special set of pins that interface to the EZ ICE T hese features allow in circuit emulation without replacing the target System processor by using only a 14 pin connection from the target system to the EZ ICE T arget systems must have 14 pin connector to accept the EZ ICE s in circuit probe a 14 pin plug T he ICE Port interface consists of the following AD SP 2181 pins EBR EMS ELIN EBG EINT ELOUT ERESET ECLK EE T hese ADSP 2181 pins must be connect
25. cle 24 REV D ADSP 2181 OUTPUT DRIVE CURRENTS Figure 19 shows typical I V characteristics for the output drivers of the AD SP 2181 T he curves represent the current drive capability of the output drivers as a function of output voltage 120 100 80 60 SOURCE CURRENT mA SOURCE VOLTAGE Volts Figure 19 Typical Drive Currents POWER DISSIPATION T o determine total power dissipation in a specific application the following equation should be applied for each output C xVpp xf load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin T he application operates at Vpp 5 0 V and tcx 30 ns Total Power Dissipation xVpp x f internal power dissipation from Power vs Frequency graph Figure 20 1000 4 Vpp 5 5V 1 5 0V T 100 Vpp 4 5V lt o o E 5 10 2 o 1 5 5 15 25 35 45 55 65 75 85 TEMPERATURE NOTES 1 REFLECTS ADSP 2181 OPERATION IN LOWEST POWER MODE SEE SYSTEM IN
26. d to the destination before devices are removed TIMING PARAMETERS GENERAL NOTES Use the exact timing information given D o not attempt to derive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching Characteristics specify how the processor changes its signals Y ou have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance Y ou can also use switch ing characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing Requirements apply to signals that are controlled by cir cuitry external to the processor such as the data input for a read operation T iming requirements guarantee that the processor operates correctly with other devices REV D MEMORY TIMING SPECIFICATIONS T he table below shows common memory device specifications and the corresponding AD SP 2181 timing parameters for your convenience Memory ADSP 2181 Timing Device Timing Parameter Specification Parameter Definition Address Setup A0 A13
27. data bus are dis abled the measurement value is that of the last pin to stop driving INPUT R OUTPUT Figure 24 Voltage Reference Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when they have made atransition from a high impedance state to when they start driving T he output enable time tena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the O utput Enable D isable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL VoH VoH MEASURED MEASURED OUTPUT Vor MEASURED 0 5V VoL MEASURED VoL t MEASURED DECAY OUTPUT STARTS OUTPUT STOPS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 25 Output Enable Disable lo 1 5V lon Figure 26 Equivalent Device Loading for AC Measure ments Including All Fixtures REV D ADSP 2181 ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tcase PD Oca Tcase Case Temperature in C PD Power Dissipation in W Thermal Resistance C ase to Ambient Thermal Resistance Junction to Ambient 6c Thermal Resistance Junction to C ase Package
28. e crystal should be used A clock output CLK OUT signal is generated by the processor at the processor s cycle rate T his can be enabled and disabled by the CLK ODIS bit in the SPORT 0 Autobuffer Control Register CLKIN XTAL CLKOUT DSP Figure 3 External Crystal Connections Reset T he RESET signal initiates a master reset of the AD SP 2181 T he RESET signal must be asserted during the power up se quence to assure proper initialization RESET during initial power up must be held long enough to allow the internal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabilization time T he power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is ap plied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time D uring this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the mini mum pulse width specification T he RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an external Schmidt trigger is recommended T he master reset sets all internal stack pointers to the empty stac
29. e of four possible modify registers A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers Efficient data transfer is achieved with the use of five internal buses Program M emory Address PM A Bus Program M emory Data PM D Bus D ata M emory Address DM A Bus Data M Data DM D Bus Result R Bus T hetwo address buses PM A and DM A share a single external address bus allowing memory to be expanded off chip and the two data buses PM D and DM D share a single external data bus Byte memory space and 1 0 memory space also share the external buses Program memory can store both instructions and data permit ting the ADSP 2181 to fetch two operands in a single cycle one from program memory and one from data memory T he REV D ADSP 2181 AD SP 2181 can fetch an operand from program memory and The ADSP 2181 provides up to 13 general purpose flag pins the next instruction in the same cycle T he data input and output pins on SPORT 1 can be alternatively In addition to the address and data bus for external memory configured as an input flag and an output flag In addition there connection the ADSP 2181 has a 16 bit Internal DMA port are eight flags that are programmable as inputs or outputs and IDM A port for connection to external systems The IDM A three flags that are always outputs port is made up of 16 data address pins and five control pins A prog
30. easserted 0 25tc 3 ns tRwR RD High to RD or WR Low 5 ns w wait states x xMS PMS DMS CMS IOMS BMS CLKOUT Figure 11 Memory Read REV D 17 ADSP 2181 Parameter Min Max Unit Memory Write Switching Characteristics tpw D ata Setup before WR H igh 7 w ns tou Data Hold after WR High 0 25tc 2 ns twp WR Pulsewidth 0 5tce 5 w ns WR LowtoDataEnabled 0 ns tasw A0 A13 xMS Setup before WR Low 0 25tc 4 ns tppn D ata Disable before WR or RD Low 0 25tc 4 ns CLKOUT Highto WRLow __ 0 25tc 5 0 25 tck 7 ns taw A0 A13 xMS Setup before WR D easserted 0 75tck 9 w ns twra A0 A13 xMS Hold after WR D easserted 0 25tc 3 ns twwer WR High to RD or WR Low 0 5 5 ns w wait states x xMS PMS DMS CMS IOMS BMS CLKOUT BMS CMS twra WR tasw twp twwr gt taw toy d 3 tpw twoe S Figure 12 Memory Write 18 REV D ADSP 2181 Parameter Min Max Unit Serial Ports Timing R equirements tsck SCLK Period 50 ns tscs D R TFS RFS Setup before SCLK Low 4 ns tscu D R TFS RFS Hold after SCLK Low 7 ns tscp SCLK n Width 20 ns Switching Characteristics tcc CLKOUT High to 5 0 25tc 0 25 10 ns tscot SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 15 ns tau TFS RF Soy Hold after SCLK
31. ed only to the EZ ICE connector in the target system T hese pins have no function except during emulation and do not require pull up or pull down resistors T he traces for these signals between the AD SP 2181 and the connector must be kept as short as possible no longer than three inches T he following pins are also used by the EZ ICE BR BG GND RESET T he EZ ICE uses the EE emulator enable signal to take con trol of the ADSP 2181 in the target system T his causes the processor to use its ERESET EBR and EBG pins instead of the RESET BR and BG pins T he BG output is three stated T hese signals do not need to be jumper isolated in your system T he EZ ICE connects to the target system via a ribbon cable and a 14 pin female plug T he ribbon cable is 10 inches in length with one end fixed to the EZ ICE T he female plug is plugged onto the 14 pin connector a pin strip header on the target board Target Board Connector for EZ ICE Probe T he EZ ICE connector a standard pin strip header is shown in Figure 7 Y ou must add this connector to your target board design if you intend to use the EZ ICE Be sure allow enough room in your system to fit the EZ ICE probe onto the 14 pin connector GND KEY NO PIN ELOUT EE TOP VIEW Figure 7 Target Board Connector for EZ ICE REV D ADSP 2181 T he 14 pin 2 row pin strip header is keyed at the Pin 7 loca tion you must remove Pin 7 from the heade
32. er accumulator M AC and the shifter T he computational units process 16 bit data directly and have provi sions to support multiprecision computations The ALU per forms a standard set of arithmetic and logic operations division primitives are also supported T he M AC performs single cycle multiply multiply add and multiply subtract operations with 40 bits of accumulation T he shifter performs logical and arith metic shifts normalization denormalization and derive expo nent operations T he shifter can be used to efficiently implement numeric format control including multiword and block floating point representations T heinternal result R bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa tional units T he sequencer supports conditional jumps subroutine calls and returns in a single cycle With internal loop counters and loop stacks the AD SP 2181 executes looped code with zero over head no explicit jump instructions are required to maintain loops T wo data address generators D s provide addresses for simultaneous dual operand fetches from data memory and program memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of on
33. even wait states to be automatically generated for each of four regions T he wait states act on address ranges as shown in T ablelV TablelV Address Range Wait State Register 0x000 0x1F F IOWAITO 0x200 0x3F F IOWAIT 1 0x400 0x5F F IOWAIT 2 0x600 0x7F F IOWAIT 3 Composite Memory Select CMS The ADSP 2181 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space T he CMS signal is generated to have the same timing as each of the individual memory select signals PMS DMS BMS IOMS but can combine their functionality When set each bit in the CM SSEL register causes the CMS signal to be asserted when the selected memory select is as serted For example to use a 32K word memory to act as both program and data memory set the PM S and DM S bits in the CM SSEL register and use the CMS pin to drive the chip select of the memory use either DMS or PMS as the additional address bit T he CMS pin functions like the other memory select signals with the same timing and bus request logic A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal All enable bits except the BMS bit default to 1 at reset Byte Memory T he byte memory space is a bidirectional 8 bit wide external memory space used to store programs and data Byte memory is accessed using the BDM A feature T he byte memory
34. hen the processor is booting and when RESET is active T he BGH pin is asserted when the AD SP 2181 is ready to execute an instruction but is stopped because the external bus is already granted to another device T he other device can re lease the bus by deasserting bus request Once the bus is re leased the AD SP 2181 deasserts BG and BGH and executes the external memory access Flagl O Pins The ADSP 2181 has eight general purpose programmable in put output flag pins T hey are controlled by two memory mapped registers T he PFTY PE register determines the direc tion 1 output and 0 input The PFDATA register is used to read and write the values on the pins D ata being read from a pin configured as an input is synchronized to ADSP 2181 s clock Bits that are programmed as outputs will read the value being output The PF pins default to input during reset In addition to the programmable flags the AD SP 2181 has five fixed mode flags FLAG IN FLAG OUT FLO FL1 and FL2 FLO FL2 are dedicated output flags FLAG IN and FLAG OUT are available as an alternate configuration of SPORT 1 INSTRUCTION SET DESCRIPTION The ADSP 2181 assembly language instruction set has an algebraic syntax that was designed for ease of coding and read ability T he assembly language which takes full advantage of the processor s unique architecture offers the following benefits The algebraic syntax eliminates the need to remember cryptic
35. ing down T he power down interrupt also can be used as a non maskable edge sensitive interrupt Context clear save control allows the processor to con tinue where it left off or start with a clean context when leaving the power down state T he RESET pin also can be used to terminate power down Power down acknowledge pin indicates when the proces sor has entered power down Idle When the ADSP 2181 is in theldle M ode the processor waits indefinitely in a low power state until an interrupt occurs When an unmasked interrupt occurs it is serviced execution then continues with the instruction following the IDLE instruction Slow Idle TheIDLE instruction is enhanced on the AD SP 2181 to let the processor s internal clock signal be slowed further reducing power consumption T he reduced clock fre quency a programmable fraction of the normal clock rate is specified by a selectable divisor given in the IDLE in struction T he format of the instruction is IDLE n where 16 32 64 or 128 T his instruction keeps the processor fully functional but operating at the slower clock rate While it is in this state the processor s other internal clock signals such as SCLK CLKOUT and timer clock are reduced by the same ratio T he default form of the instruction when no clock divisor is given is the standard IDLE instruction ADSP 2181 When the IDLE n instruction is used it effectively slows down the processo
36. k condition masks all interrupts and clears the M STAT register When RESET is released if there is no pending bus request and the chip is configured for booting M M AP 0 the boot loading sequence is performed T he first instruction is fetched from on chip program memory location 0x0000 once boot loading completes 6 REV D ADSP 2181 Memory Architecture The ADSP 2181 provides a variety of memory and peripheral interface options T he key functional groups are Program Memory Data M emory Byte M emory and I O Program Memory is a 24 bit wide space for storing both instruction opcodes and data T he ADSP 2181 has 16K words of Program M emory RAM on chip and the capability of access ing up to two 8K external memory overlay spaces using the external data bus Both an instruction opcode and a data value can be read from on chip program memory in a single cycle Data Memory is a 16 bit wide space used for the storage of data variables and for memory mapped control registers T he AD SP 2181 has 16K words on D ata M emory RAM on chip consisting of 16 352 user accessible locations and 32 memory mapped registers Support also exists for up to two 8K external memory overlay spaces through the external data bus Byte Memory provides access to an 8 bit wide memory space through the Byte DM A BDM A port T he Byte M emory inter face provides access to 4 M Bytes of memory by utilizing eight data lines as addition
37. ll up resistors are necessary because there are no internal pull ups to guarantee their state during prolonged three state conditions resulting from typical EZ ICE debugging sessions T hese resistors may be removed at your option when the EZ ICE is not being used REV D Target System Interface Signals W hen the EZ ICE board is installed the performance on some system signals changes D esign your system to be compatible with the following system interface signal changes introduced by the EZ ICE board EZ ICE emulation introduces an 8 ns propagation delay be tween your target circuitry and the D SP on the RESET signal EZ ICE emulation introduces an 8 ns propagation delay be tween your target circuitry and the DSP on the BR signal EZ ICE emulation ignores RESET and BR when single stepping EZ ICE emulation ignores RESET and BR when in Emulator Space D SP halted EZ ICE emulation ignores the state of target BR in certain modes As a result the target system may take control of the D SP s external memory bus only if bus grant BG is asserted by the EZ ICE board s DSP Target Architecture File T he EZ ICE software lets you load your program in its linked executable form T he EZ ICE PC program can not load sec tions of your executable located in boot pages by the linker With the exception of boot page 0 loaded into PM RAM all sections of your executable mapped into boot pages are not loaded Write your target a
38. n the C environment T he Runtime Library includes over 100 ANSI standard mathematical and D SP specific functions The EZ KIT Lite is a hardware software kit offering a complete development environment for the entire AD SP 21xx family an AD SP 2181 evaluation board with PC monitor software plus Assembler Linker Simulator and PROM Splitter software ADSP 218x EZ KIT Lite is a low cost easy to use hard ware platform on which you can quickly get started with your DSP software design T he EZ KIT Lite includes the following features 33 M Hz ADSP 2181 Full 16 bit Stereo Audio 1 0 with AD 1847 SoundPort Codec RS 232 Interface to PC with Windows 3 1 Control Software Stand Alone Operation with Socketed EPROM EZ ICE Connector for Emulator Control DSP Demo Programs T he AD SP 218x Emulator aids in the hardware debug ging of AD SP 218x systems T he emulator consists of hard ware host computer resident software and the target board connector T he AD SP 218x integrates on chip emulation sup port with a 14 pin ICE Port interface T his interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other AD SP 2100 Family EZ ICEs The ADSP 218x device need not be removed from the target system when using the EZ ICE nor are any adapters needed D ue to the small footprint of the EZ ICE connector emulation can be supported in final board designs T he EZ ICE
39. not including crystal oscillator start up time toxin CLKIN CLKOUT PF 2 0 tus 4 tun RESET PF2 IS MODE C PF1 IS MODE PFO IS MODE A Figure 8 Clock Signals 14 REV D ADSP 2181 Parameter Min Max Unit Interrupts and Flag Timing Requirements rs IRQx Fl or PFx Setup before CLKOUT Low 0 25tck 15 ns ten IRQx Fl or PFx Hold after CLK OUT High 2 4 0 25tc ns Switching Characteristics trou Flag Output H old after CLKOUT Low 0 5 7 ns trop Flag Output Delay from CLKOUT Low 0 5 5 ns NOTES Nf TRQx and FI inputs meet and setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the U ser s M anual for further information on interrupt servicing 2 dge sensitive interrupts require pulsewidths greater than 10 ns level sensitive interrupts must be held low until serviced 3IRQx IRQO IRQT IRQ2 RQLO IRQLT IRQE PFx PFO PF1 PF2 PF4 PF5 PF6 PF7 lag outputs PFx FLO FL1 FL2 Flag out4 CLKOUT FLAG OUTPUTS IRQx 4 irs 3 Figure 9 Interrupts and Flags REV D 15 ADSP 2181 Parameter Min Max Unit Bus Request Grant Timing Requirements BR H
40. nterrupt servicing is enabled LOW POWER OPERATION The ADSP 2181 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions T hese modes are Power Down Idle Slow Idle TheCLKOUT pin may also be disabled to reduce external power dissipation REV D Power D own The ADSP 2181 processor has low power feature that lets the processor enter a very low power dormant state through hardware or software control H ere is a brief list of power down features For detailed information about the power down feature refer to the ADSP 2100 Family U se sM anual Third Edition System Interface chapter Quick recovery from power down T he processor begins executing instructions in as few as 100 CLKIN cycles Support for an externally generated TTL or CMOS processor clock T he external clock can continue running during power down without affecting the lowest power rating and 100 CLKIN cycle recovery Support for crystal operation includes disabling the oscil lator to save power the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabi lize and letting the oscillator run to allow 100 CLKIN cycle start up Power down is initiated by either the power down pin PWD or the software power down force bit Interrupt support allows an unlimited number of instruc tions to be executed before optionally power
41. o the EZ ICE connector in the target system T hese pins have no function except during emulation and do not require pull up or pull down resistors Interrupts T heinterrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead AD SP 2181 provides four dedicated external interrupt input pins IRQ2 IRQLO IRQL1 In addition SPORT 1 may be reconfigured for IRQO IRQ1 FLAG IN and FLAG OUT for a total of six external interrupts T he AD SP 2181 also supports internal interrupts from the timer the byte DMA port the two serial ports software and the power down control circuit T he interrupt levels are internally prioritized and individually maskable except power down and reset T he IRQ2 IRQO and IRQI input pins can be programmed to be either level or edge sensitive IROLO and IRQLI level sensitive and IRQE is edge sensitive T he priorities and vector addresses of all interrupts are shown in T able REV D ADSP 2181 Tablel Interrupt Priority and Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address Hex Reset or Power U p with 1 0000 Highest Priority Power D own N onmaskable 002C IRQ2 0004 IRQLI 0008 IRQLO 000C SPORTO T ransmit 0010 SPORT 0 Receive 0014 IRQE 0018 BDMA Interrupt 001C SPORT1Transmit or IRQ1 0020 SPORT 1 Receive or IRQO 0024 Timer
42. of Read 0 ns tap D uration of Read 15 ns Switching Characteristics TACK High after Start of Read 15 ns ikps 15 0 Data Setup before Low 0 5 10 ns IAD 15 0 Data H old after End of Read 0 ns IAD 15 0 Data D isabled after End of Read 12 ns 15 0 Previous D ata Enabled after Start of Read 0 ns IAD 15 0 Previous D ata Valid after Start of Read 15 ns npu1 IAD 15 0 Previous D ata H old after Start of Read DM PM 1 2tck 5 ns tiRDH2 IAD 15 0 Previous D ata H old after Start of Read 2 tck 5 ns NOTES 1Start of Read IS Low IRD Low 2 of Read IS High or IRD High 3D M read or first half of PM read Second half of PM read al IAD15 0 Figure 17 IDMA Read Long Read Cycle REV D 23 ADSP 2181 Parameter Min Max Unit IDMA Read Short Read Cycle Timing Requirements tikr IACK Low before Start of Read 0 ns D uration of R ead 15 ns Switching Characteristics High after Start of Read 15 ns IAD 15 0 Data old after End of Read 0 ns 15 0 Data Disabled after End of Read 12 ns IAD 15 0 Previous D ata Enabled after Start of Read 0 ns IAD 15 0 Previous D ata Valid after Start of R ead 15 ns NOTES Start of Read IS Low and IRD Low End of Read IS High or IRD High tikr is mD 1AD15 0 Figure 18 IDMA Read Short Read Cy
43. old after CLKOUT High 0 25tc 2 ns tgs BR Setup before CLKOUT Low 0 25tc 17 ns Switching Characteristics tei CLKOUT High to xMS 0 25tc 10 ns RD WR Disable xMS RD WR Disable to BG Low 0 ns tse BG High to xMS RD WR Enable 0 ns xMS RD WR Enableto CLK OUT High 0 25tc 4 ns tspBH xMS RD WR Disable to BGH Low 0 ns High to xMS RD WR Enable 0 ns NOTES xMS PMS DMS CMS IOMS BMS TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family User s M anual Third Edition for BR BG cycle relationships is asserted when the bus is granted and the processor requires control of the bus to continue CLKOUT NL tes CLKOUT PMS DMS BMS RD R tsp gt tsec BG tse BGH tsoen tseH 4 Figure 10 Bus Request Bus Grant 16 REV D ADSP 2181 Parameter Min Max Unit Memory Read Timing Requirements _ trop RD Low to Data Valid 0 5 9 W ns taa A0 A13 xMS to Data Valid 0 75 10 5 w ns trou Data Hold from RD High 0 ns Switching Characteristics trp RD Pulsewidth 0 5tck 5 ns CLKOUT HightoRDLow _ 0 25tc 5 0 25tck 7 ns tasr A0 A13 xMS Setup before RD Low 0 25tc 4 ns troa A0 A13 xMS Hold after RD D
44. on 0 is written to The ADSP 2100 F amily D evelopment Software Revision 5 02 and later can generate ID M A compatible boot code Bus Request and Bus Grant TheADSP 2181 can relinquish control of the data and address buses to an external device When the external device requires access to memory it asserts the bus request BR signal If the ADSP 2181 is not performing an external memory access then it responds to the active BR input in the following processor cycle by three stating the data and address buses and the PMS DMS BMS CMS IOMS RD WR output drivers asserting the bus grant BG signal and halting program execution ADSP 2181 If Go M is enabled the AD SP 2181 will not halt program execution until it encounters an instruction that requires an external memory access If the AD SP 2181 is performing an external memory access when the external device asserts the BR signal then it will not three state the memory interfaces or assert the BG signal until the processor cycle after the access completes T he instruction does not need to be completed when the bus is granted If a single instruction requires two external memory accesses the bus will be granted between the two accesses When the BR signal is released the processor releases the BG signal reenables the output drivers and continues program execution from the point where it stopped T he bus request feature operates at all times including w
45. one processor cycle the AD SP 2181 can Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 ADSP 2181 T his takes place while the processor continues to Receive and transmit data through the two serial ports Receive and or transmit data through the internal DM A port Receive and or transmit data through the byte DM A port Decrement timer Development System The ADSP 2100 F amily Development Software a complete set of tools for software and hardware system development supports the AD SP 2181 T he System Builder provides a high level method for defining the architecture of systems under development T he Assembler has an algebraic syntax that is easy to program and debug T he Linker combines object files into an executable file T he Simulator provides an interactive instruction level simulation with a reconfigurable user interface to display different portions of the hardware environment A PROM Splitter generates PROM programmer compatible files The C Compiler based on the F ree Software oundation s GNU C Compiler generates AD SP 2181 assembly source code T he source code debugger allows programs to be cor rected i
46. performs a full range of functions including In target operation U p to 20 breakpoints Single step or full speed operation Registers and memory values can be examined and altered PC upload and download functions Instruction level emulation of program booting and execution Complete assembly and disassembly of instructions source level debugging See the Designing An EZ ICE Compatible T arget System sc tion of this data sheet for exact specifications of the EZ ICE target board connector EZ ICE and SoundPort are registered trademarks of Analog D evices Inc Additional Information T his data sheet provides a general overview of AD SP 2181 functionality F or additional information on the architecture and instruction set of the processor refer to the ADSP 2100 Family User s anual Third Edition For more information about the development tools refer to the ADSP 2100 Family Development Tools D ata Sheet ARCHITECTURE OVERVIEW TheADSP 2181 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single pro cessor cycle T he AD SP 2181 assembly language uses an alge braic syntax for ease of coding and readability A comprehensive set of development tools supports program development Figure 1 is an overall block diagram of the AD SP 2181 T he processor contains three independent computational units the ALU the multipli
47. r s internal clock and thus its response time to in coming interrupts T he one cycle response time of the standard idle state is increased by n the clock divisor When an enabled interrupt is received the ADSP 2181 will remain in the idle state for up to a maximum of n processor cycles n 16 32 64 or 128 before resuming normal operation When n instruction is used in systems that have an externally generated serial clock SCLK the serial clock rate may be faster than the processor s reduced internal clock rate U nder these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the idle state a maximum of n processor cycles SYSTEM INTERFACE Figure 2 shows a typical basic system configuration with the AD SP 2181 two serial devices a byte wide EPROM and op tional external program and data overlay memories mable wait state generation allows the processor to connect easily to slow peripheral devices The AD SP 2181 also provides four external interrupts and two serial ports or six external inter rupts and one serial port ADSP 2181 MEMORY DATA SPACE PERIPHERALS CS 2048 LOCATIONS TEN S i To i MEMORY SERIAL BESO TFSO TWO 8K DEVICE pro PM SEGMENTS TWO 8K DM SEGMENTS SYSTEM INTERFACE OR p CONTROLLER Figure 2 ADSP
48. r T he pins must be 0 025 inch square and at least 0 20 inch in length Pin spac ing should be 0 1 x 0 1 inches T he pin strip header must have at least 0 15 inch clearance on all sides to accept the EZ ICE probe plug Pin strip headers are available from vendors such as 3M McKenzie and Samtec Target Memory Interface For your target system to be compatible with the EZ I CE emu lator it must comply with the memory interface guidelines listed below PM DM BM IOM and CM D esign your Program M emory PM Data M emory DM Byte M emory BM 1 0 Memory and Composite M emory CM external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the D SP s data sheet T he performance of the EZ ICE may approach published worst case specification for some memory access timing requirements and switching characteristics Note f your target does not meet the worst case chip specifica tion for memory access parameters you may not be able to emulate your circuitry at the desired CLKIN frequency De pending on the severity of the specification violation you may have trouble manufacturing your system as D SP components statistically vary in switching characteristic and timing require ments within published limits Restriction All memory strobe signals on the AD SP 2181 target system must have 10 kQ pull up resistors connected when the EZ ICE is being used T he pu
49. rammable interval timer generates periodic interrupts A ThelDMA port provides transparent direct access to the DSPs 16 bit count register T COUNT is decremented every n pro on chip program and data RAM cessor cycles where n is a scaling value stored in an 8 bit regis An interface to low cost byte wide memory is provided by the ter TSCALE When the value of the count register reaches Byte DMA port BDMA port The BDMA port is bidirectional zero an interrupt is generated and the count register is reloaded and can directly address up to four megabytes of external RAM from a 16 bit period register T PERIOD or ROM for off chip storage of program overlays or data tables Serial Ports T he byte memory and 1 0 memory space interface supports slow The ADSP 2181 incorporates two complete synchronous serial memories and 1 0 memory mapped peripherals with program ports SPORT 0 and SPORT 1 for serial communications and mable wait state generation External devices can gain control of multiprocessor communication external buses with bus request grant signals BR and H ere is a brief list of the capabilities of the ADSP 2181 SPORT s One execution mode Go M ode allows the AD SP 2181 to con Refer to the ADSP 2100 Family User s M anual Third Edition for tinue running from on chip memory N ormal execution mode further details requires the processor to halt while buses are granted The ADSP 2181 can respond to 13 possible inter
50. rchitecture file to indicate that only PM RAM is available for program storage when using the EZ ICE software s loading feature D ata can be loaded to PM RAM or DM RAM 11 ADSP 2181 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit VDD Supply Voltage 4 5 5 5 4 5 5 5 V Tams Ambient Operating T emperature 0 70 40 85 C ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Typ Max Unit Vin Hi Level Input Voltage 2 9 max 2 0 V Vin Hi Level CLKIN Voltage 9 max 2 2 V Viu Lo L evel Input Voltage 3 9 Vpp 2 min 0 8 V Hi Level Output Voltage 9 Vpp min 0 5 mA 2 4 V Vop min lon 100 pA Voo 0 3 V VoL Lo L evel Output Voltage 9 Vpp min lo 2 mA 0 4 V liu Hi Level Input Current 9 max Vin 10 lu L o L evel Input Current 9 Vpp 2 max Vin 20V 10 T hree State L eakage C urrent 9 Vpp max Vin Vppmax 10 loz T hree State L eakage Current 9 Vpp 2 max Vin 20 V 10 Supply Current Idle Vpp 5 0 TAMB 25 C 34 7 ns 12 mA 30 ns 13 mA 25 ns 15 mA lop Supply Current D ynamic 9 Vpp 5 0 25 34 7 65 mA tck 30 nsH 73 mA tek 25 ns 85 mA Ci Input Pin Capacitance 12 2 5 V fin 1 0 M Hz TAMB 25 C 8 Output Pin Cap
51. rupts eleven of which are accessible at any given time T here can be up to six external interrupts one edge sensitive two level sensitive and SPORT s are bidirectional and have a separate double buffered transmit and receive section SPORT s can use an external serial clock or generate their three configurable and seven internal interrupts generated by own serial clock internally the timer the serial ports SPORT s the ByteDMA port and SPORT 5 have independent framing for the receive and trans the power down circuitry T hereis also a master RESET signal mit sections Sections run in a frameless mode or with frame T hetwo serial ports provide a complete synchronous serial inter synchronization signals internally or externally generated face with optional companding in hardware and a wide variety of Frame sync signals are active high or inverted with either of framed or frameless data transmit and receive modes of operation two pulsewidths and timings Each port can generate an internal programmable serial clock or accept an external serial clock 21xx CORE ADSP 2181 INTEGRATION E os contro LOGIC nerves KM PROGRAM REGISTER SRAM BYTE PROGRAMMABLE A DATA DATA CONTROLLER ADDRESS ADDRESS GENERATOR rcs 7 1 2 PMA BUS x EXTERNAL DATA BUS us ESI LL TES fif X ll 1 BUS INPU SHIFTE
52. s held off while the BD accesses are occurring Setting the BCR bit to 0 allows the processor to continue opera tions Setting the BCR bit to 1 causes the processor to stop execution while the BDM A accesses are occurring to clear the context of the processor and start execution at address 0 when the BDM A accesses have completed Internal Memory DMA Port IDMA Port ThelDMA Port provides an efficient means of communication between a host system and the AD SP 2181 T he port is used to access the on chip program memory and data memory of the DSP with only one D SP cycle per word overhead The IDM A port cannot however be used to write to the DSP s memory mapped control registers ThelDMA port has a 16 bit multiplexed address and data bus and supports 24 bit program memory TheIDMA port is completely asynchronous and can be written to while the AD SP 2181 is operating at full speed T he D SP memory address is latched and then automatically incremented after each IDM A transaction An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block T his in creases throughput as the address does not have to be sent for each memory access Port access occurs in two phases T he first is the IDM A Address L atch cycle When the acknowledge is asserted a 14 bit address and 1 bit destination type can be driven onto the bus by an external device T he address
53. specifies an on chip memory location the destination type specifies whether itis a DM or PM access T he falling edge of the address latch signal latches this value into the IDM AA register Once the address is stored data can either be read from or written to the AD SP 2181 s on chip memory Asserting the select line IS and the appropriate read or write line IRD and IWR respectively signals the AD SP 2181 that a particular transaction is required In either case there is a one processor cycle delay for synchronization T he memory access consumes one additional processor cycle an access has occurred the latched address is automati cally incremented and another access can occur T hrough the IDM AA register the D SP can also specify the starting address and data format for DM A operation Bootstrap Loading Booting The ADSP 2181 has two mechanisms to allow automatic load ing of the on chip program memory after reset T he method for booting after reset is controlled by the M M AP and BM ODE pins as shown in T able VI REV D Table VI Boot Summary Table MMAP BMODE BootingMethod 0 0 BDMA feature is used in default mode to load the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded IDMA feature is used to load any inter nal memory as desired Program execu tion is held off until internal program memory location 0 is wri
54. tten to Bootstrap features disabled Program execution immediately starts from location 0 BDMA Booting When the BM ODE and MM AP pins specify BDM A booting 0 BMODE 0 the ADSP 2181 initiates a BDM A boot sequence when reset is released The BDM A interface is set up during reset to the following defaults when BDM A boot ing is specified the BDIR BM PAGE BIAD and BEAD regis ters are set to 0 the BT Y PE register is set to 0 to specify program memory 24 bit words and the BWCOUNT register is Set to 32 T his causes 32 words of on chip program memory to be loaded from byte memory T hese 32 words are used to set up the BDMA to load in the remaining program code The BCR bit is also set to 1 which causes program execution to be held off until all 32 words are loaded into on chip program memory Execution then begins at address 0 TheADSP 2100 F amily D evelopment Software Revision 5 02 and later fully supports the BDM A booting feature and can generate byte memory space compatible boot code TheIDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BD M A interface IDMA Booting ADSP 2181 can also boot programs through its Internal port If BM 1and MM AP 0 the ADSP 2181 boots from the IDM A port IDM A feature can load as much on chip memory as desired Program execution is held off until on chip program memory locati
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