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ST10 family programming manual

1. Flags s s s E Restored from the PSW popped from stack Z Restored from the PSW popped from stack V Restored from the PSW popped from stack C Restored from the PSW popped from stack N Restored from the PSW popped from stack Addressing Modes Mnemonic Format Bytes RETI FB 88 2 106 172 yy ST10 FAMILY PROGRAMMING MANUAL RETP Return from Subroutine amp Pop Word Syntax RETP opl Operation IP SP SP lt SP 2 tmp S CSP 3 SP lt SP 2 op1 lt tmp Data Types WORD Description Returns from a subroutine The IP is first popped from the system stack and then the next word is popped from the system stack into the operand specified by op1 Execution resumes at the instruction following the CALL instruction in the calling routine Flags E Z V C N E Set if the value of the word popped into operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the word popped into operand op1 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the word popped into operand op1 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes RETP reg EB RR 2 ky 107 172 ST10 FAMILY PROGRAMMING MANUAL RETS Return from Inter Segment Subroutine Syntax RETS Operation IP SP SP SP 2 CSP
2. 169 172 ST10 FAMILY PROGRAMMING MANUAL 4 REVISION HISTORY Revision 5 version 4 Updated Disclaimer Revision 4 version 1 of January 2000 Chapter 2 1 4 See 1 GPRAddress CP 2 x ShortAddress See 3 LongAddress GPRAddress Constant See 4 PhysicalAddress DPPi LongAddress 3FFFh See5 GPRPAddress GPRDAddress A Chapter 2 2 3 Additional State Times Jumps into the internal ROM Space Label In 1 I 2 JMPR cc NC label Chapter 2 4 Table 9 10 11 12 13 14 15 16 17 18 19 All column 16 bit N MUX 16 bit MUX 8 bit N MUX 8 bit MUX This document number 70966264 is the transfer onto ADCS of document 42 1735 05 on the Bristol doc ument control system This revision includes extensive modifications to format The major modifications to content are summarized in this table r gt R In MAC instructions upper case R has replaced lower case r for Reverse operation data gt data In MAC instructions immediate shift value uses 5 bits to be coded not 4 Table 30 Instr COMACMus function code is 98 Instr COMACMus function code is A8 Instr COMACMus rnd function code is 99 Instr COMACMR function code is F9 Instr COMACM R su Addressing Mode CoMACRsu IDX amp Rw 93 Xm 70 rrrr rqqq CoMACRsu IDX Rw rnd 93 Xm 71 rrrr rqqq CoMACRsu Rw RW rnd 93 Xm 71 rrrr rqqq correction in Multiplication examples CoMULu and coMU
3. CoMULus Mixed Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULus opl op2 Operation ACC lt opl op2 Syntax CoMULus opl op2 Operation ACC opl1 op2 Syntax CoMULus opl op2 rnd Operation ACC opl op2 00 0000 8000 MAL lt 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two 16 bit unsigned and signed source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N Z C sv E SL 0 0 X Set if the most significant bit of the result is set Cleared otherwise Set if the result equals zero Cleared otherwise Always cleared V Not affected Always cleared L Not affected m O N Z Addressing Modes Mnemonic Rep Format Byt
4. IDXi DOUBLE WORD 40 bit signed value ST10 FAMILY PROGRAMMING MANUAL Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then and on condition the MP flag is set it is one bit left shifted and next it is option ally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and performs two parallel mem ory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as explained by the following table Addressing Mode Overwritten Address IDX no change IDX IDX 2 MAC Flags N Z C SV E SL N Set if the most significant bit of the result
5. Flags E Z V 0 0 0 0 E Always cleared Z Set if the source operand op2 equals zero Cleared otherwise V Always cleared C Always cleared N Always cleared Addressing Modes Mnemonic Format Bytes PRIOR Rwy RWg 2B nm 2 102 172 yy ST10 FAMILY PROGRAMMING MANUAL PUSH Push Word on System Stack Syntax PUSH opl Operation tmp opl SP SP 2 SP tmp Data Types WORD Description Moves the word specified by operand op1 to the location in the internal system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two Flags E Z V C N E Setif the value of the pushed word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed word is set Cleared otherwise Addressing Modes Mnemonic Format Bytes PUSH reg EC RR 2 ky 103 172 ST10 FAMILY PROGRAMMING MANUAL PWRDN Enter Power Down Mode Syntax PWRDN Operation Enter Power Down Mode Description This instruction causes the part to enter the power down mode In this mode all peripherals and the CPU are powered down until the part is externally reset To insure that this instruction is not accidentally exe cuted it is implemented as a protected instruction To further control the action o
6. 83 nm 40 0 0qqq 4 CoMULsu Rw Rw 83 nm 48 0 0qqq 4 CoMULsu Rw Rw rnd 83 nm 41 0 0qqq 4 160 172 yy ST10 FAMILY PROGRAMMING MANUAL Examples CoMULsu RO Rl rnd ACC RO R1 rnd CoMULsu R2 R6 ACC R2 R6 R6 R6 2 CoMULsu IDX0 R11 ACC IDX0 R11 R11 R11 2 CoMULsu IDX1 R15 ACC IDX1 R15 IDX1 IDX1 2 CoMULsu IDXO QX0 R9 QR1 rnd ACC IDX0 R9 rnd R9 R9 ORI IDXO IDXO QX0 Multiplication Examples posen Sa s maja s ss MeV POOP e NaN E RESI ERR RE SSES n si R ern A b CREARE IE On en o o o TESTES T Tan Tas Ta A s ses o fal es pm r Ls s Lo Pe I ky 161 172 ST10 FAMILY PROGRAMMING MANUAL CoNEG Negate Accumulator with Optional Rounding Group 32 bit Arithmetic Instructions Syntax CoNEG CoNEG nd Operation IF rnd THEN ACC 0 ACC 00 0000 8000 MAL O ELSE ACC 0 ACC END IF Data Types ACCUMULATOR Result 40 bit signed value Description The Accumulator content is subtracted from zero and the result is optionally rounded before being stored in the accumulator register With rnd option MAL is cleared When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 00004
7. ZvC N e V 1 N V an 0 Zv E O O Ke Jle il S ol II ky 35 172 ST10 FAMILY PROGRAMMING MANUAL 2 6 7 Flags This section shows the state of the N C V Z and E flags in the PSW register The resulting state of the flags is represented by the following symbols see Table 25 If the PSW register is specified as the destination operand of an instruction the flags can not be interpreted as described This is because the PSW register is modified according to the data format of the instruction For word operations the PSW register is over written with the word result Table 25 List of flags For byte operations the non addressed byte is cleared and the addressed byte is overwritten For bit or bit field operations on the PSW regis ter only the specified bits are modified If the flags are not selected as destination bits they stay unchanged i e they maintain the state existing after the previous instruction In all cases if the PSW is the destination operand of an instruction the PSW flags do NOT represent the flags of this instruction in the normal way The flag is set according to the following standard rules Most significant bit of the result is set Carry occurred during operation Most significant bit of the result is not set No Carry occurred during operation Arithmetic Overflow occurred during operation No Arith
8. o F fo wes gs Em a EI C FF T r9 9 155 172 ST10 FAMILY PROGRAMMING MANUAL CoMULu Unsigned Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULu opl op2 Operation ACC opl op2 Syntax CoMULu opl op2 Operation ACC opl1 op2 Syntax CoMULu opl op2 rnd Operation ACC opl op2 00 0000 8000 MAL 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two unsigned 16 bit source operands op1 and op2 The unsigned 32 bit product is first zero extended and then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag of the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N Z C SV E SL 0 x 0 L N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E
9. IDX0O QXO IDXO IDX0O IDXO QXO Repeat MRW times CoMACMRu CoMACMRu IDX1 QX1 R7 QRO ACC IDX1 R7 ACC 7 R7 lt R7 QRO 7 IDX1 QX1 lt IDX1 IDX1 IDX1 QX1 146 172 ky CoMACM R us ST10 FAMILY PROGRAMMING MANUAL Mixed Multiply Accumulate Parallel Data Move amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACMus opl op2 Operation tmp lt op1 op2 ACC lt ACC tmp IDX IDX Syntax CoMACMus opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 8000 MAL 0 IDX IDX Syntax CoMACMus opl op2 Operation tmp lt gt opl op2 ACC ACC tmp IDX IDX Syntax CoMACMRus opl op2 Operation tmp Ko opli op2 ACC tmp ACC IDX IDX Syntax CoMACMRus opl op2 rnd Operation tmp lt op1 op2 ACC tmp ACC 00 0000 80004 MAL lt 0 IDX IDX Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended it is then optionally negated prior being added subtracted to from the 40 bit ACC regis ter content finally the obtained result is optionally rounded before being stored
10. IDXO IDXO QX0 Repeat 3 times CoMACu IDX1 R9 ACC lt ACC IDX1 R9 R9 R9 2 IDX1 IDX1 2 Repeat MRW CoMACu R3 R7 QRO ACC ACC R3 R7 times 7 R7 R7 ORO CoMACRu IDX1 QX0 R4 rnd ACC IDX1 R4 ACC rnd IDX1 IDX1 QXO 137 172 ST10 FAMILY PROGRAMMING MANUAL CoMAC R us Mixed Multiply Accumulate amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACus opl op2 Operation tmp opl op2 ACC ACC tmp Syntax CoMACus opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 8000 MAL 0 Syntax CoMACus opl op2 Operation tmp opl op2 ACC ACC tmp Syntax CoMACRus opl op2 Operation tmp opl op2 ACC tmp ACC Syntax CoMACRus opl op2 rnd Operation tmp opl op2 ACC tmp ACC 00 0000 8000 MAL 0 Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two unsigned and signed 16 bit source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended and then it is optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never a
11. Operation tmp lt 2 op2 opl ACC lt 0 tmp Data Types DOUBLE WORD Result 40 bit signed value Description Loads the accumulator with a 40 bit source operand The 40 bit source operand results from the concate nation of the two source operands op1 LSW and op2 MSW which is then sign extended 2 and options indicate that the 40 bit operand is also multiplied by two or and negated respectively prior being stored in the accumulator The option indicates that the source operand is 2 s complemented When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is not repeatable and allows up to two parallel memory reads MAC Flags N Z C SV E SL Set if the most significant bit of the result is set Cleared otherwise Set if the result equals zero Cleared otherwise Set if a borrow is generated Cleared otherwise Not affected Set if the MAE is used Cleared otherwise L Set if the contents of the ACC is automatically saturated Not affected otherwise AMAONZ lt Addressing Modes Mnemonic Rep Format Bytes CoLOAD Rwy Rwy A3 nm 22 00 4 CoLOAD Rwy Rwy A3 nm 2A 00 4 CoLOAD2 Rwy Rwy A3 nm 62 00 4 CoLOAD2 Rwy Rwy A3 nm 6A 00 4 CoLOAD IDX Rw 93 Xm 22 0 0qqq 4 CoLOAD IDX Rw 93 Xm 2A 0 0q
12. Yes 93 Xm BO rrrr rqqq 4 CoMACRus IDX Rw rnd Yes 93 Xm Bl rrrr rqqgq 4 CoMACus Rwy Rw Yes 83 nm 90 rrrr rqqq 4 CoMACus Rw Rw Yes 83 nm AO rrrr rqqq 4 CoMACus Rw Rw rnd Yes 83 nm 91 rrrr rqqq 4 CoMACRus Rw Rw Yes 83 nm BO rrrr rqqq 4 CoMACRus Rw Rw rnd Yes 83 nm Bl rrrr rqqq 4 Examples CoMACus R5 R8 rnd ACC ACC R5 R8 rnd CoMACus R2 R7 ACC ACC R2 R7 CoMACus IDXO QX0 R11 ORO ACC ACC IDXO R11 R11 R11 QRO IDX0 IDXO QX0 Repeat 3 times CoMACus IDX1 R9 ACC ACC IDX1 R9 R9 R9 2 IDX1 IDX1 2 Repeat MRW times CoMACus R3 R7 ORO ACC ACC R3 R7 7 R7 R7 QRO CoMACRus IDX1 0X0 R4 rnd ACC IDX1 R4 ACC rnd IDX1 IDX1 QX0 139 172 ST10 FAMILY PROGRAMMING MANUAL CoMAC R su Mixed Multiply Accumulate amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACsu opl op2 Operation tmp opl op2 ACC lt ACC tmp Syntax CoMACsu opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 8000 MAL lt 0 Syntax CoMACsu opl op2 Operation tmp opl op2 ACC lt ACC tmp Syntax CoMACRsu opl op2 Operation tmp opl op2 ACC tmp ACC Syntax CoMACRsu op
13. maskg datag word memory with immediate data BMOV bitaddr bitaddr BMOVN bitaddr bitaddr BOR bitaddr bitaddr bitaddr Move direct bit to direct bit Move negated direct bit to direct bit OR direct bit with direct bit N m i Set direct bit XOR direct bit with direct bit ps E ES BXOR bitaddr bitaddr MP Rw Rw Compare direct word GPR to direct GPR UJ n m E Q CMP Rw Rw Compare indirect word memory to direct GPR CMP Rw Rw Compare indirect word memory to direct GPR and post increment source pointer by 2 Q MP Rw datas Compare immediate word data to direct GPR EUER sss a S T MP reg data Compare immediate word data to direct register EES MP reg mem CMPB Rb Rb Compare direct word memory to direct register Compare direct byte GPR to direct GPR Rb Rw Compare indirect byte memory to direct GPR ojlo lt uj U w w Rb Rw Compare indirect byte memory to direct GPR and post increment source pointer by 1 CMPB Rb datas Compare immediate byte data to direct GPR DERA 3 P E gad S Po N N N N N N N N N N N SER sn E SIS E o Se D S s s S byes Base E CMPB reg datay Compare immediate byte data to direct register m Dea MANN pum eee srao IE SE SD renea STN raK oP Corpre mesme vors aaae araras Ceres ren nena oaran Corese dramece E rares Z uc NN raak 5 ELI EN renne saepe i CMPB reg mem Compare direct byte mem
14. Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Note The E flag is set when the nine highest bits of the accumulator are not equal The SV flag is set when a 40 bit arithmetic overflow underflow occurs Addressing Modes Mnemonic Rep Format Bytes CoADD Rwy Rwy No A3 nm 02 00 4 CoADD2 Rwy Rwy No A3 nm 42 00 4 CoADD IDX Rw Yes 93 Xm 02 rrrr rqqq 4 CoADD2 IDX Rw Yes 93 Xm 42 rrrr rqqq 4 CoADD Rw Rw Yes 83 nm 02 rrrr rqqq 4 CoADD2 Rwy Rw Yes 83 nm 42 rrrr rqqq 4 ky 129 172 ST10 FAMILY PROGRAMMING MANUAL Examples CoADD RO R1 ACC ACC R1 N RO CoADD2 R2 R6 ACC ACC 2 R6 N R2 R6 R6 2 Repeat 3 times CoADD CoADD IDX1 QX1 R10 QRO ACC ACC R10 N IDX1 R10 R10 ORO IDX1 IDX1 QX1 Repeat MRW times CoADD2 CoADD2 RA R8 QR1 ACC ACC 2 R8 R4 R8 R8 QR1 Addition Examples er o nennen nmm T amp x murem wemomo worrmms o v nas x wm Tes wen mw v 5 Copo v mm on erer rrer vene of zuo v mw wm Tara mamowm v 5 sap
15. N Not affected Addressing Modes Mnemonic Format Bytes CALLS seg caddr DA ss MM MM 4 60 172 ky ST10 FAMILY PROGRAMMING MANUAL CMP Integer Compare Syntax CMP opl op2 Operation 0p1 lt gt op2 Data Types WORD Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set according to the rules of subtrac tion The operands remain unchanged Flags E Z V N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMP Rwy Rwy 40 nm 2 CMP Rwa Rw 48 n 10ii 2 CMP Rw Rw 48 n llii 2 CMP Rwy data 48 n 0 2 CMP reg fdataig 46 RR d 4 CMP reg mem 42 RR MM MM 4 ky 61 172 ST10 FAMILY PROGRAMMING MANUAL CMPB Integer Compare Syntax CMPB opl op2 Operation 0p1 lt gt op2 Data Types BYTE Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary
16. Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACu opl op2 Operation tmp opl op2 ACC ACC tmp Syntax CoMACu opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 80004 MAL 0 Syntax CoMACu opl op2 Operation tmp opl op2 ACC ACC tmp Syntax CoMACRu opl op2 Operation tmp opl op2 ACC tmp ACC Syntax CoMACRu opl op2 rnd Operation tmp opl op2 ACC tmp ACC 00 0000 8000 MAL 0 Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two unsigned 16 bit source operands op1 and op2 The obtained unsigned 32 bit prod uct is first zero extended and then optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and allows u
17. Refer to device datasheets for information about which ST10 devices include the MAC 3 1 Addressing modes MAC instructions use some standard ST10 addressing modes such as GPR direct or datas for immediate shift value To supply the MAC with up to 2 new operands per instruction cycle new MAC instruction addressing modes have been added These allow indirect addressing with address pointer post modification Double indirect addressing requires 2 pointers one of which can be supplied by any GPR the other is provided by one of two new specific SFRs IDXo and IDX Two pairs of offset registers QRO QR1 and QX0 QX1 are associated with each pointer GPR or IDX The GPR pointer gives access to the entire mem ory space whereas IDX are limited to the internal Dual Port RAM except for the CoMOV instruc tion The following table shows the various combi ST10 FAMILY PROGRAMMING MANUAL nations of pointer post modification for each of these 2 new addressing modes see Table 27 When using pointer post modification addressing modes the address pointed to i e the value in the IDX or Rw register must be a legal address even if its content is not modified An odd value e g in RO when using RO post modification adressing mode will trigger the class B hardware Trap 28h Illegal Word Operand Access Trap ILLOPA In this document the symbols Rw and IIDX amp are used to refer to these addressing modes A new in
18. Syntax CoMUL opl op2 Operation IF MP 1 THEN ACC opl op2 lt lt 1 ELSE ACC lt opl op2 END IF Syntax CoMUL opl op2 Operation IF MP 1 THEN ACC opl op2 lt lt 1 ELSE ACC opl op2 END IF Syntax CoMUL opl op2 rnd Operation IF MP 1 THEN ACC lt opl op2 lt lt 1 00 0000 8000 ELSE ACC opl op2 00 0000 80004 END IF MAL lt 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then and on condition MP is set it is one bit left shifted and finally it is optionally either negated or rounded before being stored in the 40 bit ACC register The option is used to negate the specified product while the rnd option is used to round the product using two s complement round ing The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Always cleared when MP is cl
19. Syntax DIVLU opl Operation MDL MD opl MDH MD mod opl Data Types WORD DOUBLEWORD Description Performs an extended unsigned 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags E Z C N S 0 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes DIVLU Rw 7B nn 2 72 172 ky ST10 FAMILY PROGRAMMING MANUAL DIVU 16 by 16 Unsigned Division Syntax DIVU opi Operation MDL MDL opl MDH lt MDL mod opl Data Types WORD Description Performs an unsigned 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags E Z C N S 0 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic
20. To insure that this instruction is not accidentally executed it is implemented as a protected instruction Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes IDLE 87 78 87 87 4 80 172 ky JB Syntax JB Operation IF opl IP ELSE END IF Data Types BIT Description ST10 FAMILY PROGRAMMING MANUAL Relative Jump if Bit Set opl op2 1 THEN lt IP sign_extend op2 Next Instruction If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calcu lation is the address of the instruction following the JB instruction If the specified bit is clear the instruc tion following the JB instruction is executed Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JB bitaddro q rel 8A QO rr q0 4 81 172 ST10 FAMILY PROGRAMMING MANUAL JBC Relative Jump if Bit Set amp Clear Bit Syntax JBC opl op2 Operation IF opl 1 THEN opl 0 IP IP sign extend op2 ELSE ext Instruction END IF Data Types BIT
21. opl op2 00 0000 8000 MAL lt 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two 16 bit signed and unsigned source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N Z C SV E SL k 0 0 N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Always cleared SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoMULsu Rwy Rwy A3 nm 40 00 4 CoMULsu Rwy Rwy A3 nm 48 00 4 CoMULsu Rwy Rwy rnd A3 nm 41 00 4 CoMULsu IDX Rw G 93 Xm 40 0 0qqq 4 CoMULsu IDX Rw4G 93 Xm 48 0 0qqq 4 CoMULsu IDX RWn rnd 93 Xm 41 0 0qqq 4 CoMULsu Rwy Rw
22. this extra time must always be considered The value of T add which must be considered for timing evaluations of internal program parts may fluctuate between 0 state times and 1 ALE Cycle Time This is because external writes are normally performed in parallel to other CPU operations Thus add could already have been considered in the standard processing time of another instruction Writing a word operand via an 8 bit wide data bus requires twice as much time 2 ALE Cycle Times as the writing of a byte operand ky 11 172 ST10 FAMILY PROGRAMMING MANUAL Jumps into the internal ROM space Tiada 0 or 2 States The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2 additional state times if the branch target instruction is a double word instruction at a non aligned double word location xxx2h xxx6h xxxAh xxxEh as shown in the following example label E Wes any non aligned double word instruction e g at location OFFEh Ini JMPA cc UC label if a standard branch is taken Tiada 2 x States Typ 6 States A cache jump which normally requires just 2 state times will be extended by 2 additional state times if both the cached jump target instruction and the following instruction are non aligned double word instruc tions as shown in the following example label EE A any non aligned double word instruction e g at location 12FAh ln SR eens any non alig
23. trap7 Immediate 7 bit trap or interrupt number Extension operations The EXT instructions override the standard DPP addressing scheme pag Immediate 10 bit page address seg Immediate 8 bit segment address 15 172 ST10 FAMILY PROGRAMMING MANUAL Branch condition codes cc Symbolically specifiable condition codes cc UC Unconditional cc NE Not Equal cc Z Zero cc_ULT Unsigned Less Than cc_NZ Not Zero cc_ULE Unsigned Less Than or Equal cc_V Overflow cc UGE Unsigned Greater Than or Equal cc_NV No Overflow cc_UGT Unsigned Greater Than cc_N Negative cc_SLE Signed Less Than or Equal cc_NN Not Negative cc_SLT Signed Less Than cc_C Carry cc SGE Signed Greater Than or Equal cc NC No Carry cc SGT Signed Greater Than cc EQ Equal cc NET Not Equal and Not End of Table Table 9 Arithmetic instructions _ Nu Rw Rw Add direct word GPR to direct GPR Rw Rw Add indirect word memory to direct GPR A A A A D D Add indirect word memory to direct GPR and post increment source pointer by 2 D D o 16 bit mux e bit n mux Iv ERE sire aL lede ua s Ie IE z I N NI N N NI N N N N D D D Add immediate word data to direct GPR Add immediate word data to direct register Add direct word memory to direct register D D D D D D Add direct word register to direct memory A Rb Rb Add direct byte GPR to direct GPR D B ADDB Rb Rw Add indirect byte memory to direct GPR
24. B B D ADD Rb Rw Add indirect byte memory to direct GPR and post increment source pointer by 1 D I N CEES ERE EZ EE ADD Rb amp data4 Add immediate byte data to direct GPR Add direct byte memory to direct register Add direct byte register to direct memory Add direct word GPR to direct GPR with Carry Add indirect word memory to direct GPR with Carry Add indirect word memory to direct GPR with Carry and post increment source pointer by 2 Add immediate word data to direct GPR with Carry ADDC reg data4 Add immediate word data to direct register with Carry EERE s Bass reg ADDB reg data Add immediate byte data to direct register ADDC reg mem Add direct word memory to direct register with Carry BB ADDC mem reg Add direct word register to direct memory with Carry A 2 16 172 ST10 FAMILY PROGRAMMING MANUAL Table 9 Arithmetic instructions continued ADDCB Rb Rb Add direct byte GPR to direct GPR with Carry 2 6 2 8 4 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry 2 e 2 8 4 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry and 2 3 post increment source pointer by 1 ADDCB Pb datas Add immediate byte data to direct GPR with Carry a2 e 2 8 4 6 ADDCB reg data Add immediate byte data to direct register with Carry a 8 4 e 8 12 4 ADDCB reg mem Add direct byte memory to direct register with Carry 2 8 4 6 8 12 4
25. Call indirect subroutine if condition is met 8 6 x s 5 JMPS seg caddr Jump absolute to a code segment JNB bitaddr rel Jump relative if direct bit is not set JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 PCALL reg caddr Push direct word register onto system stack and 4 call absolute subroutine TRAP trap7 Call interrupt service routine via immediate trap 4 number Table 17 System Stack Instructions _ a POP reg E Pop direct word register from system stack 2 JMPR cc rel Jump relative if condition is met 4 2 8 6 4 SCXT reg data g Push direct word register onto system stack and update 2 register with immediate data PUSH reg Push direct word register onto system stack 2 6 SCXT reg mem Push direct word register onto system stack and update 2 4 register with direct memory Table 18 Return Instructions om I eae Return from interrupt service subroutine 4 Return from intra segment subroutine and pop direct word 4 register from system stack Return from inter segment subroutine 24 172 ST10 FAMILY PROGRAMMING MANUAL Table 19 System Control Instructions continued ATOMIC data Begin ATOMIC sequence 2 DISWDT Disable Watchdog Timer EINIT Signify End of Initialization on RSTOUT pin 2 S SD S A Z G 0 EAS e laar 7 G HD EXTER Fw 90 EXTSR seg data Begin EXTended Segment and Register sequence a IDLE Ente
26. CoMACR rnd CoMACRu rnd CoMACRus rnd CoMACRsu rnd CoNOP CoNEG CoNEG rnd CoRND CoABS CoABS op1 op2 CoSTORE CoMOV wwww w000 ST10 FAMILY PROGRAMMING MANUAL co processor as its operation code Unused func tion codes are treated as CoNOP Function Code by the MAC nes aep 125 172 ST10 FAMILY PROGRAMMING MANUAL 3 4 MAC instruction conventions This section details the conventions used to describe the MAC instruction set 3 4 1 Operands opX Specifies the immediate constant value of opX opX Specifies the contents of opX opX Specifies the contents of bit n of opX opX Specifies the contents of opX i e opX is used as pointer to the actual operand rnd plus 00 0000 8000 3 4 2 Operations Diadic operations opX easy opY opXYopY opX is CONCATANATED to opY LSW Max opX opY MAXIMUM value between opX and opY Min opX opY MINIMUM value between opX and opY opX opX is Logically SHIFTED Left Monadic opX gt gt opX is Logically SHIFTED Right Operations opX 4 opX is Arithmetically SHIFTED Right Abs opX ABSOLUTE value of opX 3 4 3 Abbreviations 8 most significant bits of the accumulator lowest byte of the MSW register 3 4 4 Data addressing Modes Rwy or RW General Purpose Registers GPRs where n and m are any value between 0 and 15 Indirect word memory location CoReg MAC
27. CoRND Operation ACC ACC 00 0000 8000 MAL 0 Data Types ACCUMULATOR Result 40 bit signed value Description Rounds the ACC register contents by adding 0000 8000h to it and store the result in the ACC register and the lower part of the ACC register MAL is cleared When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFFy or FF 8000 00004 respectively This instruction is not repeatable MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoRND No A3 00 B2 00 4 Notes CoRND is equivalent to CoASHR 0 rnd Example CoRND ACC ACC rnd 164 172 yy ST10 FAMILY PROGRAMMING MANUAL CoSHL Accumulator Logical Shift Left Group Shift Instructions Syntax CoSHL opl Operation count opl C lt 0 DO WHILE count 0 C ACC39 ACC lt ACC _1 n 1 39 ACCg 0 count lt count 1 END WHILE Data types ACCUMULATOR Result 40 bit signed value Description Shifts the ACC regi
28. Description If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction If the specified bit was clear the instruction follow ing the JBC instruction is executed Flags E Z V C B 0 E Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes JBC bitaddro rel AA QQ rr q0 4 82 172 yr ST10 FAMILY PROGRAMMING MANUAL JMPA Absolute Conditional Jump Syntax JMPA opl op2 Operation IF opl 1 THEN IP op2 ELSE ext Instruction END IF Description If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed nor mally Condition Codes See Condition code Table 24 page 35 Flags E Z V C N E Not affected Z Not affected V Not affected C Not
29. PROGRAMMING MANUAL SHR Shift Right Syntax SHR opl op2 Operation count op2 C V lt 0 DO WHILE count 0 V C v V C oplg opl lt oplg n 0 14 oplys lt 0 count count 1 END WHILE Data Types WORD Description Shifts the destination word operand op1 right by as many times as specified by the source operand op2 The most significant bits of the result are filled with zeros accordingly Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an least significant bit Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Z V C N S E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared for a shift count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes SHR RwWy Rwy 6C nm 2 SHR Rwy datay 7C Tn 2 ky 113 172 ST10 FAMILY PROGRAMMING MANUAL SRST
30. Register Group Transfer Instructions Syntax CoSTORE opl op2 Operation op1 op2 Data Types WORD Description Moves the contents of a MAC Unit register specified by the source operand op2 to the location specified by the destination operand op1 This instruction is repeatable with destination indirect addressing mode for example to clear a table in memory MAC Flags N Z C SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoSTORE Rwy CoReg No C3 nn wwww w000 00 4 CoSTORE Rw CoReg Yes B3 nn wwww w000 rrrr rqqq 4 Note Due to pipeline side effects CoSTORE cannot be directly followed by a MOV instruction the source operand of which is also a MAC Unit register such as MSW MAH MAL MAS MRW or MCW In this case a NOP must be inserted between the CoSTORE and MOV instruction Examples CoSTORE R11 QR1 MAS R11 limited ACC R11 R11 QR1 Repeat 3 times CoSTORE CoSTORE R2 MAL R2 MAL G lt RZ o 2 ky 167 172 ST10 FAMILY PROGRAMMING MANUAL CoSUB 2 R Subtract Group Arithmetic Instructions Syntax CoSUB opl op2 Operation tmp lt op2 opl ACC lt ACC tmp Syntax CoSUB2 opl op2 Operation tmp lt 2 op2 opl ACC lt ACC tmp Syntax CoSUBR opl op2 Operation tmp op
31. Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ORB Rb ROn 71 nm 2 ORB Rb Rw 79 n 10ii 2 ORB Rb Rw 79 n 11ii 2 ORB Rb data3 79 n 0 2 ORB reg f dataig 77 RR 4 ORB reg mem 73 RR MM MM 4 ORB mem reg 75 RR MM MM 4 ky 99 172 ST10 FAMILY PROGRAMMING MANUAL PCALL Push Word amp Call Subroutine Absolute Syntax PCALL opl op2 Operation tmp opl SP lt SP 2 SP tmp SP SP 2 SP lt IP IP lt op2 Data Types WORD Description Pushes the word specified by operand op1 and the value of the instruction pointer IP onto the system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the system stack rep resents the return address of the calling routine Flags E Z V C N E Set if the value of the pushed operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand op1 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed operand op1 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes PCALL reg ca
32. Syntax BXOR opl op2 Operation 0p1 opl op2 Data Types BIT Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destina tion bit specified by operand op1 The XORed result is then stored in op1 Flags E Z V C N NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BXOR bitaddr bitaddro 7A QQ ZZ qz 4 56 172 ky CALLA Syntax Operation Description ST10 FAMILY PROGRAMMING MANUAL Call Subroutine Absolute CALLA opl op2 IF opl THEN SP So SP 2 SP IP IP lt op2 ELSE next instruction END IF If the condition specified by op1 is met a branch to the absolute memory location specified by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally Condition Codes See condition code Table 24 page 35 Flags E Z V C N E Not
33. The DPP override mechanism temporarily bypasses the DPP addressing scheme The EXTP R and EXTS R instructions override this addressing mechanism Instruction EXTP R replaces the content of the respective DPP register while instruction EXTS R concatenates the complete 16 bit long address with the specified segment base address The overriding page or segment may be specified directly as a constant pag seg or by a word GPR Rw see Figure 2 2 1 4 Indirect addressing modes Indirect addressing modes can be considered as a combination of short and long addressing modes In this mode long 16 bit addresses are specified indirectly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 Some indirect addressing modes add a constant value to the GPR contents before the long 16 bit address is calculated Other indirect addressing modes allow decrementing or incre menting of the indirect address pointers GPR con tent by 2 or 1 referring to words or bytes In each case one of the four DPP registers is used to specify the physical 18 bit or 24 bit addresses Any word or byte data within the entire memory space can be addressed indirectly Note that EXTP R and EXTS R instructions override the DPP mechanism Instructions using the lowest four word GPRs R3 RO as indirect address pointers are speci fied by short 2 bit addresses Figure 2 Overriding the DPP mechanism Word
34. Z and C flags contained in the MSW register leaving the accumulator unchanged The 40 bit operand results from the concatenation Y of the two source operands op1 LSW and op2 MSW which is then sign extended The MS bit of the MCW register does not affect the result This instruction is not repeatable and allows up to two parallel memory reads MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Not affected E Not affected SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoCMP Rwy Rwy No A3 nm C2 00 4 CoCMP IDX Rw No 93 Xm C2 0 0qqq 4 CoCMP Rw Rw No 83 nm C2 0 0qqq 4 Examples CoCMP IDX1 QX0 R11 QOR1 MSW N Z C ACC R11 IDX1 R11 R11 QR1 IDX1 IDX1 QX0 CoCMP R1 R2 MSW N Z C ACC R2 N R1 PO RZY Gen R2 2 CoCMP R2 R5 MSW N Z C ACC R5 R2 132 172 er ST10 FAMILY PROGRAMMING MANUAL CoLOAD 2 Load Accumulator Group 40 bit Arithmetic Instructions Syntax CoLOAD opl op2 Operation tmp op2 N op1 ACC 0 tmp Syntax CoLOAD opl op2 Operation tmp op2 opl ACC lt 0 tmp Syntax CoLOAD2 opl op2 Operation tmp lt 2 op2 opl ACC lt 0 tmp Syntax CoLOAD2 opl op2
35. affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes CALLA cc Cadar CA c0 MM MM 4 57 172 ST10 FAMILY PROGRAMMING MANUAL CALLI Call Subroutine Indirect Syntax CALLI opl op2 Operation IF opl THEN SP lt SP SP IP IP op2 ELSE next instruction END IF Description If the condition specified by op1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack rep resents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally Condition Codes See condition code Table 24 page 35 Flags E Z V N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format CALLI cc Rw AB cn Bytes 58 172 ST10 FAMILY PROGRAMMING MANUAL sign extend opl CALLR Call Subroutine Relative Syntax CALLR opl Operation SP SP SP lt gt LP IP lt IP Description A branch is taken to the location specified by the instruction pointer IP plus the relative displacement op1 The displacement is a two s complement number which is si
36. and logical the reference between the instruction format instructions where the addressing mode combina tion is not specified by the identical opcodes but ep Eo ens by particular bits within the operand field sponding internal organization of the instruction In the individual instruction description the format N nibble 4 bits Phisatollewing Sym addressing mode is described in terms of mne bols are used to describe the instruction for monic format and number of bytes mats representation of the assembler and the corre Table 26 Instruction format symbols f Eeeherte 4 charactors immediate folowing aclonepresensa sge ot U 0 2 bit short GPR address Rw ss 8 bit code segment number seg 2 bit immediate constant datas AHH 3 bit immediate constant datag 4 bit condition code specification cc 4 bit short GPR address Rw or Rb 4 bit short GPR address Rw or Rbm a_i othe source bt win tre word spected eyo 4 bit immediate constant data laa 8 bit word address of the source bit bitoff 8 bit relative target address word offset rel m Iaa _ j 8 bit word address of the destination bit bitoff 8 bit immediate constant datag 8 bit immediate constant maskg pp 0 00pp 10 bit page address pag10 MM MM 16 bit address mem or caddr low byte high byte THE HH 16 bit immediate constant data low byte high byte 2 37 172 ST10 FAMILY PROGRAMMING MANUAL Number
37. and rotate instructions continued R aE Rw Rw Arithmetic sign bit shift right direct word GPR number of R ee cycles specified by direct GPR ASHR Rw data4 Arithmetic sign bit shift right direct word GPR number of shift cycles specified by immediate data ROL Rw Rw Rotate left direct word GPR number of shift cycles 2 2 3 4 2 specified by direct GPR ROL Rw data Rotate left direct word GPR number of shift cycles 2 2 3 4 2 specified by immediate data ROR Rw Rw Rotate right direct word GPR number of shift cycles 2 2 3 4 2 specified by direct GPR ROR Rw data Rotate right direct word GPR number of shift cycles 2 212314 2 specified by immediate data Rw Rw Shift left direct word GPR number of shift cycles specified 2 by direct GPR Rw data4 Shift left direct word GPR number of shift cycles specified 21214 by immediate data Rw Rw Shift right direct word GPR number of shift cycles specified 4 by direct GPR Rw data4 Shift right direct word GPR number of shift cycles specified 2 21214 by immediate data Table 15 Data movement instructions Nor w TT TEKI arm area aor aj fa faye a 2 s 2 s e pum i IPLE DIDIES Rw MOV Rw Rw Move indirect word Move indirect word memory to direct GPR to direct Move indirect word memory to direct GPR gg K Rv Rw Move indirect word memory to direct GPR and 4 post increment source pointer by 2 MOV Rw Rw Rw Move direct word Move direct word GPR
38. ble word sized branch instruction Rw The 16 bit branch target instruction address is determined indirectly by the content of a word GPR In contrast to indirect data addresses indi rectly specified code addresses are NOT calcu lated by additional pointer registers e g DPP registers Branches MAY NOT be taken to odd code addresses Therefore to prevent a hardware trap the least significant bit of the address pointer GPR must always contain a 0 seg Specifies an absolute code segment number All devices support 256 different code segments so only the eight lower bits of the seg operand value are used for updating the CSP register trap7 Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine by a jump vector table Trap numbers from 00h to 7Fh can be specified which allows access to any double word code location within the address range 00 0000h 00 01FCh in code segment 0 i e the interrupt jump vector table 8 172 For further information on the relation between trap numbers and interrupt or trap sources refer to the device user manual section on Interrupt and Trap Functions 2 2 Instruction execution times The instruction execution time depends on where the instruction is fetched from and where the operands are read from or written to The fastest processing mode is to execute a pro gram fetched from the internal ROM In this
39. cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOVN bitaddrz z bitaddro q 3A QQ ZZ qz 4 ky 53 172 ST10 FAMILY PROGRAMMING MANUAL BOR Bit Logical OR Syntax BOR opl op2 Operation op1 opl v op2 Data Types BIT Description Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit speci fied by operand op1 The ORed result is then stored in op1 Flags NOR OR AND XOR Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits Contains the logical XOR of the two specified bits z O lt N m Addressing Modes Mnemonic Format Bytes BOR bitaddry bitaddrg SA QQ ZZ qz 4 54 172 ky ST10 FAMILY PROGRAMMING MANUAL BSET Bit Set Syntax BSET opl Operation 0p1 lt 1 Data Types BIT Description Sets the bit specified by op1 This instruction is primarily used for peripheral and system control Flags E Z C N 0 B 0 0 B E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes BSET bitaddro q qF QQ 2 ky 55 172 ST10 FAMILY PROGRAMMING MANUAL BXOR Bit Logical XOR
40. executed Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JNB bitaddro q rel 9A QQ rr q0 4 ky 87 172 ST10 FAMILY PROGRAMMING MANUAL JNBS Relative Jump if Bit Clear amp Set Bit Syntax JNBS opl op2 Operation IF opl 0 THEN opl 1 IP IP sign extend op2 ELSE ext Instruction END IF Data Types BIT Description If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is set allowing implementation of sema phore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNBS instruction If the specified bit was set the instruction following the JNBS instruction is executed Flags E Z V C B 0 E Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes JNBS bitaddro qr rel BA QQ rr q0 4 88 172 ky ST10 FAMILY PROGRAMMING MANUAL MOV Move Data Syntax MOV opl op2 Operation op1 op2 Data Types WOR
41. instruc tion can be used to perform multiple precision arithmetic Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ADDCB Rba Rb 11 nm 2 ADDCB Rba Rwi 9 n 10ii 2 ADDCB Rba Rwi 9 n llii 2 ADDCB Rb dataj 9 n 0 2 ADDCB reg dataj 17 RR 4 ADDCB reg mem 3 RR MM MM 4 ADDCB mem reg 5 RR MM MM 4 42 172 ky ST10 FAMILY PROGRAMMING MANUAL AND Logical AND Syntax AND opl op2 Operation op1 opl op2 Data Types WORD Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand spec ified by op1 The result is then stored in op1 Flags E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most sig
42. is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACM IDX Rw Yes 93 Xm D8 rrrr rqqq 4 CoMACM IDX Rw Yes 93 Xm E8 rrrr rqqq 4 CoMACM IDX Rw rnd Yes 93 Xm DY rrrr rqqq 4 CoMACMR IDX Rw Yes 93 Xm F8 rrrr rqqq 4 CoMACMR IDX Rw rnd Yes 93 Xm F9 rrrr rqqq 4 ky 143 172 ST10 FAMILY PROGRAMMING MANUAL Examples CoMACM IDX1 QX0 R10 QR1 rnd Repeat 3 times CoMACM CoMACM IDX0O QX0 R8 QRO0 Repeat MRW times CoMACM CoMACM IDX1 QX1 R7 QRO0 144 172 ACC lt ACC IDX1 R10 rnd R10 R10 QR1 IDX1 QX0 IDX1 IDX1 IDX1 QX0 ACC ACC IDXO R8 R8 R8 QRO IDXO QXO IDXO0 IDX0 IDXO QX0 ACC ACC IDX1 R7 R7 R7 QRO IDX1 QX1 IDX1 IDX1 IDX1 QX1 ST10 FAMILY PROGRAMMING MANUAL CoMACM R u Unsigned Multiply Accumulate Parallel Data Move amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACMu opl op2 Opera
43. lt SP SP lt SP 2 Description Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instruction following the CALLS instruction in the calling routine Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mode Mnemonic Format Bytes RETS DB 00 2 108 172 yy ST10 FAMILY PROGRAMMING MANUAL ROL Rotate Left Syntax ROL opl op2 Operation count op2 C lt 0 DO WHILE count z 0 C oplis opla opl n21 15 oplo lt gt C count lt count 1 END WHILE Data Types WORD Description Rotates the destination word operand op1 left by as many times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags E Z V N 0 S E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last most significant bit shifted out of op1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ROL Rwy Rwy OC nm 2 ROL Rw datay 1C Tn 2 ky 109 172 ST10 FAMILY PROGRAMMING MA
44. mne monic representation alternatives exist for some of the condition codes Notes on the BCLR and BSET instructions The position of the bit to be set or to be cleared is specified by the opcode The operand bitaddrg q where q 0 to 15 refers to a particular bit within a bit addressable word Notes on the undefined opcodes A hardware trap occurs when one of the unde fined opcodes signified by is decoded by the CPU ADDB Rb Rbm reg mem mem reg reg data4g ADDB reg datay Rw Rwi or Rw Rwi or Rwy datas ADDB Rb Rw or Rb Rw or Rb datas BFLDL bitoffg maskg datag ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued Rw Rwi or Rw Rw or Rwn datas Rb Rwi or Rb Rw or Rbr datas bitoffg maskg datag Rw Rw or Rwn Rw or Rwn datag Rb Rw or Rb Rw or Rbn datas m en reg mem N Hew ode 27 172 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued LTJEIIONEN NN ama x 9 x 2 C sme mem Rw Rwi or Rwn Rw or Rwn datas IIS E EM NN E em eee e or mmm j L9 4 w oS eoo C j C pe Rw Rwi or Rwr Rwi or Hwa datas Rb Rw or Rb Rw or Rb datas a IA 7 7 ee a 2 lt r er E 1 po e C2 o G TT I A N Kl Kl gt O m A I Aa
45. ne a wor and CS EN GNE EN NEN Lm ede 7 gt NNNM REN C JMR oc SGE rel J O UJ VU O O OO IO IO O ol 01 0 OO Ol O Ql KR o rm nimi olola ojl SINI la A GQ L ooa N N ii x 32 172 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued EE NM ms MN MOVB Rw datais Rb reg data4g MOVB reg data4g reg mem MOVB reg mem MOVB Rb Rw datais ww emm o o 3 es EN ie E s R8 we j bitaddro 15 MumberefByus 3 3 8 3 D H ee X9 783 E WE C Cs 78 Note 1 This instruction only applies to products including the MAC ky 33 172 ST10 FAMILY PROGRAMMING MANUAL 2 6 Instruction conventions This section details the conventions used in the individual instruction descriptions Each individual instruction description is described in a standard format in separate sections under the following headings 2 6 1 Instruction name Specifies the mnemonic opcode of the instruction 2 6 2 Syntax Specifies the mnemonic opcode and the required formal operands of the instruction Instructions can have either none one two or three operands which are separated from each other by commas MNEMONIC op1 0p2 0p3 The operand syntax depends on the addressing mode All of the available addressing modes are Table 22 Instruction operation
46. otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoABS No A3 00 1A 00 4 CoABS Rwy Rwy No A3 nm CA 00 4 CoABS IDX Rw No 93 Xm CA 0 0qqq 4 CoABS Rwy Rw No 83 nm CA 0 0qqq 4 128 172 ky ST10 FAMILY PROGRAMMING MANUAL CoADD 2 Add Group 40 bit Arithmetic Instructions Syntax CoADD opl op2 Operation tmp op2 N opl ACC ACC tmp Syntax CoADD2 opl op2 Operation tmp lt 2 op2 opl ACC ACC tmp Data Types DOUBLE WORD Result 40 bit signed value Description Adds a 40 bit operand to the 40 bit Accumulator contents and store the result in the accumulator The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended 2 option indicates that the 40 bit operand is also multiplied by two prior being added to ACC When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is repeatable with indirect addressing modes and allows up to two parallel memory reads MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set
47. reg Subtract direct byte register from direct memory Rw Rw Subtract direct word GPR from direct GPR with Carry gt mro Rw Rw Subtract indirect word memory from direct GPR with Carry Rw Rw Subtract indirect word memory from direct GPR with Carry and post increment source pointer by 2 Rw datas Subtract immediate word data from direct GPR with Carry reg data Subtract immediate word data from direct register with Carry reg mem Subtract direct word memory from direct register with Carry 4 mem reg Subtract direct word register from direct memory with Carry i2 8 4 e SUBCE memo SubvactarecibyieGPRomdrect GPAwinCary 2 2 9 4 S n Subvactindrect Bye memory om drea GPR wih Gary 2 5 2 5 SUBCB Rb Rw Subtract indirect byte memory from direct GPR with Carry 2 213 14 WE EHE usce Re sg Suman mmea oye cna ron aren oPR wir Cary 2 Z 3 SURO reg fag JSunrastimmedais bve sqa ton ren regsierwin Gan 2 fe 4 fe fo SUBOB reg mem Suorat arest ovie memory rom arei regsterwin Cary 2 5 4 6 5 SUBCE mem reg subraci ree ty register om rct memory win Cary 2 8 4 s 2 4 Table 10 Logical instructions DE AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 6 2 83 4 6 2 ND AND Rw Rw Bitwise AND direct word GPR with direct GPR BEBE A Rw Rw Bitwise AND indirect word memory with direct GPR and 2 21214 2 post increment source p
48. selected addressing mode in bytes Table 8 Mnemonic vs address mode amp number of esie Rw RWm 1 Rw Rw Rw Rwi Bw datas reg data reg mem mem reg Rwp RWm Rw data4 bitaddrz z bitaddro q Rw Rwm Hw data Rwn Rw Rwa RWmt Rwm Rw Rwm Rw Rwy Rwm Rw Rwg Rwy Rwm reg datais Rw Rwr datais Rw t data Rw Rw mem mem Rw reg mem mem reg 14 172 5 Modes Meren NEG B Rwy ffdata Rw datay Rw mem CMP B Rw Rwm 1 Rwn Rw Rw Rwi Rwp datas reg data reg mem c S lt s c cx z z lt U 70 I 05 Se q rel coc reg datay reg mem U o uU s O m c ol S z 9 3d gg r 2 4 4 2 2 2 4 4 E ky ST10 FAMILY PROGRAMMING MANUAL Table 8 Mnemonic vs address mode amp Tan 1 Demons continued Mnemonic Addressing Modes pe Addressing Modes d ATOMIC iu E ESE TRO data gt EXTPR pag data gt data gt EXTSR seg data gt SRST IDLE PWRDN SRVWDT DISWDT EINIT Note 1 Byte oriented instructions suffix B use Rb instead of Rw not with Rw 2 4 Instruction set ordered by functional group The minimum number of state times required for instruction execution are given for the following configurations internal ROM internal RAM exter nal memory with a 16 bit demultiplexed a
49. subtraction of op2 from op1 The flags are set according to the rules of subtrac tion The operands remain unchanged Flag E Z V C N x x x S x E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMPB Rb RIY 41 nm 2 CMPB Rb Rwi 49 n 10ii 2 CMPB Rb Rw 49 n llii 2 CMPB Rb data3 49 n 0 2 CMPB reg fdataig 47 RR 4 4 CMPB reg mem 43 RR MM MM 4 62 172 ky ST10 FAMILY PROGRAMMING MANUAL CMPD1 Integer Compare amp Decrement by 1 Syntax CMPD1 opl op2 Operation op1 lt gt op2 op1 lt opl 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary sub traction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has com pleted the operand op1 is decremented by one Using the set flags a branch instruction can then be used in conjunction with this instruct
50. to indirect memory to indirect memory eee S ea ee my w Rw Rw Pre decrement destination pointer by 2 and move direct word GPR to indirect memory MOV Rw Rw Rw Move indirect word memory to indirect memory indirect word memory to indirect memory E E LM Rw Move indirect word memory to indirect memory amp post increment destination pointer by 2 Rw Rw Move indirect word memory to indirect memory amp post increment source pointer by 2 31 22 172 ST10 FAMILY PROGRAMMING MANUAL Table 15 Data movement instructions continued E AR S x eo eo E Rw Rw data g Move indirect word memory by base plus constant to direct GPR Rw data g Rw Move direct word GPR to indirect memory by base plus constant MOV MOV MOV Rw mem Move direct word memory to indirect memory MOV MOV MOV 2 Move indirect word memory to direct memory Move direct word memory to direct register MOVB Rb Rb Move direct byte GPR to direct GPR MOVB Rb data4 Move immediate byte data to direct GPR MOVB reg data Move immediate byte data to direct register MOVB Rb Rw Move indirect byte memory to direct GPR MOVB Rb Rw Move indirect byte memory to direct GPR and post increment source pointer by 1 MOVB Rw Rb Move direct byte GPR to indirect memory MOVB Rw Rb Pre decrement destination pointer by 1 and move direct byte GPR to indirect memory MOVB Rw Rw Move indirect byte memory to indirec
51. v rem res Tara eren I own o rem res momam ooon o 1 fal rr v rem res Taa erem et ZCIENLOE ELI PEL I H TEE cos o ooon wmm Tear s ol CoADD a B4A1 73C2 007241 AOC3 00E6045564 o o o f Ee mmmn ope pepe CoADD 0 BAAt A3C2 FF 8241 AOC3 FF 2604 5564 Boers lere tme sas a E j pee 31 130 172 ST10 FAMILY PROGRAMMING MANUAL CoASHR Accumulator Arithmetic Shift Right with Optional Round Group Shift Instructions Syntax CoASHRop1 CoASHR opl rnd Operation count opl C 0 DO WHILE count 0 ACC ACC gi n 0 38 count lt count 1 END WHILE IF rnd THEN ACC ACC 00008000nH MAL lt 0 END IF Data Types ACCUMULATOR Result 40 bit signed value Description Arithmetically shifts the ACC register right by as many times as specified by the operand op1 To preserve the sign of the ACC register the most significant bits of the result are filled with sign 0 if the original most significant bit was a 0 or with sign 1 if the original most significant bit was 1 Only shift values between 0 and 8 are allowed op1 can be either a 5 bit unsigned immediate data or the least significant 5 bits con sidered as unsigned data of any register directly or indirectly addressed operand Without rnd option the MS bit of the MCW register does not affect the result While with rn
52. 2 opl ACC tmp ACC Syntax CoSUB2R opl op2 Operation tmp lt 2 op2 opl ACC tmp ACC Data Types DOUBLE WORD Result 40 bit signed value Description Subtracts a 40 bit operand from the 40 bit Accumulator contents or vice versa when the R option is used and stores the result in the accumulator The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended The 2 option indicates that the 40 bit operand is also multiplied by 2 prior to being subtracted added from to the ACC negated ACC When the most significant bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is repeatable with indirect addressing modes and allows up to two parallel memory reads MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Note The E flag is set when the nine highest bits of the accumulator are not equal The SV flag is set when a 40 bit arithmetic overflow under
53. 2 times When the MRW register is used in the repeat instruction the 5 bit repeat field is set to 1 3 4 8 Shift value The shifter authorizes only 8 bit left right shifts Shift values must be between 0 8 inclusive 3 5 MAC instruction descriptions Each instruction is described in a standard format See MAC instruction conventions on page 126 for detailed information about the instruction con ventions The MAC instruction set is divided into 5 functional groups Multiply and Multiply Accumulate Instructions 40 bit Arithmetic Instructions Shift Instructions Compare Instructions Transfer Instructions The instructions are described in alphabetical order 127 172 ST10 FAMILY PROGRAMMING MANUAL CoABS Absolute Value Group 40 bit Arithmetic Instructions Syntax CoABS Operation ACC Abs ACC Syntax CoABS opl op2 Operation ACC Abs op2 opl Data Types ACCUMULATOR DOUBLE WORD Result 40 bit signed value Description Compute the absolute value of the Accumulator if no operands are specified or the absolute value of a 40 bit source operand and load the result in the Accumulator The 40 bit operand results from the con catenation of the two source operands op1 LSW and op2 MSW which is then sign extended This instruction is not repeatable MAC Flags N Z C SV E SL B x 0 x x N Set if the most significant bit of the result is set Cleared
54. 38 n 11ii 2 SUBC Rwy data 38 n 0 2 SUBC reg fdataig 36 RR did 4 SUBC reg mem 32 RR MM MM 4 SUBC mem reg 34 RR MM MM 4 118 172 er ST10 FAMILY PROGRAMMING MANUAL SUBCB Integer Subtraction with Carry Syntax SUBCB opl op2 Operation op1 opl op2 C Data Types BYTE Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic Flags Z V N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic S S S S S S S U U U U U U BCB BCB BCB BCB BCB BCB BCB Format Bytes Rby ROm 31 nm 2 Rba Rw 39 n 10ii 2 Rb Rwi 39 n 1lii 2 Rb data3 39 n 0 2 reg datay 37 RR 4 reg mem 33 RR MM MM 4 mem reg 35 RR MM MM 4 119 172 ST10 FAMILY PROGRAMMING MANUAL TRAP Sof
55. 4 SdNN9 goans nan 934 agns goaav goaav Uwe my Wan 934 my 9 p wg 934 WIN uqavo o3s 1134 SAON SdWr P p g mg 9 gejeq o3u mu wg Haavo 90 O3u SAON AON 8AON VdWr dl3H gelepg Bed Ymy g uaaavo 93S my Dtp my WAW 934 u sixa 1X9S u diXa AON 8SAON s134 u a e38 N3N B p wq mg 9 pi 9399 my TH uaavo o9 ZAAOW 1XOS AON 8AON vrivo 134 my 9 pg wq my mg sanr 134 AOW 8AON HT1vO9 i EET pperig pperig nan my my u SAON LGMAYS AON 8SAON oar my N3N My HMW SNP NdHMd AON 8SAON m SEE Tau ppelia nan Tu my TW AOW ERCI AOW 8AON ar ayo do 8uoO Seyepgt my O3u WAN Sheyep o3H my my my my 8qNV qQNV anv HOX HOX S8uOX HOX 8uOX erep mg O3H NIN 9 eyeps 53H Hmy AH my my dWO SdN9 dWO 8dNWNO ogns goans oans goans ogns mgogns ppeli8 pper feyep Mg AOWa 934 NIN 9telepg 53u tmy my my my Lid PpeL ans ans agns ans ganS dog Sqqv goaav odav goaav oqav aoaav Serep mg O3H NIN 9 eyeps OJH my AH my my ady gady aay aaav cp mg u s1x3 4 d LXA E g Q o a n 5 EN BCLR BlTaddrQ q BSET BlTaddrQ q 13 172 ST10 FAMILY PROGRAMMING MANUAL Table 8 lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the
56. ADDCB mem reg Add direct byte register to direct memory with Carry 2 8 4 6 8 12 4 CPL Rw Complement direct word GPR 2 6 2 3 4 6 2 CPLB Rb Complement direct byte GPR EIESESESENSESES DIV Rw Signed divide register MDL by direct GPR 20 24 20 21 22 24 2 16 16 bit DIVL Rw Signed long divide register MD by direct GPR 20 24 20 21 22 24 2 32 16 bit DIVLU Rw Unsigned long divide register MD by direct GPR 20 24 20 21 22 24 2 32 16 bit DIVU Rw Unsigned divide register MDL by direct GPR 20 24 20 21 22 24 2 16 16 bit MUL Rw Rw Signed multiply direct GPR by direct GPR 16 16 bit 14 2 MULU Rw Rw Unsigned multiply direct GPR by direct GPR 16 1 6 bit 1 N AJ eS sn U U B s 6 6 6 Subtract direct word GPR from direct GPR S Rw Rw Subtract indirect word memory from direct GPR S Rw Rw Subtract indirect word memory from direct GPR amp post increment source pointer by 2 UB i i UB i UB indi UB i UB i UB i UB i S Rb data Subtract immediate byte data from direct GPR S eg data Subtract immediate byte data from direct register reg S Rb Rw Subtract indirect byte memory from direct GPR reg B B post increment source pointer by 1 B B 2 17 172 ST10 FAMILY PROGRAMMING MANUAL Table 9 Arithmetic instructions continued M dis SUBB reg mem Subtract direct byte memory from direct register mem
57. Always cleared SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoMULu Rwy Rwy A3 nm 00 00 4 CoMULu Rwy Rwy A3 nm 08 00 4 CoMULu Rw Rwy rnd A3 nm 01 00 4 CoMULu IDX Rw 93 Xm 00 0 0qqq 4 CoMULu IDX Rw 93 Xm 08 0 0qqq 4 CoMULu IDX Rw rnd 93 Xm 01 0 0qqq 4 CoMULu Rwy RwQG 83 nm 00 0 0qqq 4 CoMULu Rw Rw 83 nm 08 0 0qqq 4 CoMULu Rw Rw rnd 83 nm 01 0 0qqq 4 156 172 yy ST10 FAMILY PROGRAMMING MANUAL Notes The result of CoMULu is never saturated whatever the value of MS bit is see multiplication examples below Examples CoMULu RO Rl rnd ACC RO R1 rnd CoMULu R2 R6 ACC R2 R6 R6 R6 2 CoMULu IDX0 R11 ACC IDX0 R11 R11 lt R11 2 CoMULu IDX1 R15 QR0 ACC IDX1 R15 R15 R15 QRO IDX1 IDX1 2 CoMULu IDX0 QX0 R9 rnd ACC IDXO R9 rnd R9 R9 2 IDXO IDX0 QXO Multiplication Examples ECNLILOLEIEGEGERENESEREZEES TEES EE s Et CR CR ER RE IRR gt s MP x MS x 7FFF ZFFFh o sr oon o o 0 ES ERE EC m ER EC CR ER REOR Eripe pes em Pe fo wes rers perm s on er o fo Le fo Lr Tere em E OOS CERE E R PE 0 S E is ky 157 172 ST10 FAMILY PROGRAMMING MANUAL
58. Byte Syntax BFLDH opl op2 op3 Operation tmp opl high byte tmp high byte tmp 70p2 v op3 opl tmp Data Types WORD Description Replaces those bits in the high byte of the destination word operand op1 which are selected by an 1 in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corre sponding bit in the OR mask op3 contains a 1 Flags E Z V C N 0 E Always cleared Z Set if the word result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the word result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes BFLDH bitoffo maskg datag 1A QQ 22 4 50 172 ky ST10 FAMILY PROGRAMMING MANUAL BFLDL Bit Field Low Byte Syntax BFLDL opl op2 op3 Operation tmp lt opl low byte tmp lt low byte tmp 70p2 v op3 0p1 tmp Data Types WORD Description Replaces those bits in the low byte of the destination word operand op1 which are selected by an 1 in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corre sponding bit in the OR mask op3 contains a 1 F
59. D Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes OV Rwy Rwy FO nm 2 OV Rw ftdata EO n 2 OV reg dataj E6 RR d 4 OV Rwy Rwy A8 nm 2 OV Rwy Rwyt 98 nm 2 OV Rw Rwy B8 nm 2 OV Rwq Rwy 88 nm 2 OV Rwyl Rwy C8 nm 2 OV Rwyt Rwy D8 nm 2 OV Rwyl Rwyt E8 nm 2 OV Rwy RwyQtfdata g D4 nm 4 OV Rw t data Rwy C4 nm 4 OV Rw mem 84 On MM MM 4 OV mem Rwa 94 On MM MM 4 OV reg mem F2 RR MM MM 4 OV mem reg F6 RR MM MM 4 ky 89 172 ST10 FAMILY PROGRAMMING MANUAL MOVB Move Data Syntax MOVB opl op2 Operation op1 op2 Data Types BYTE Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags E Z V C N E Set i
60. GRAMMING MANUAL CoMOV Memory to Memory Move Group Transfer Instructions Syntax CoMOV opl op2 Operation op1 op2 Data Types WORD Description Moves the contents of the memory location specified by the source operand op2 to the memory location specified by the destination operand op1 This instruction is repeatable Note that unlike for the other instructions IDX can address the entire memory This instruction does not affect the Mac Flags but mod ify the CPU Flags as any other MOV instruction CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise MAC Flags N Z C SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoMOV IDX Rw G Yes D3 Xm 00 rrrr rqqq 4 Examples Repeat 24 times CoMOV IDX1 QX0 R11 QR1 IDX1 R11 R11 R11 QRI1 IDX1 IDX1 QX0 ky 153 172 ST10 FAMILY PROGRAMMING MANUAL CoMUL Signed Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions
61. ILE count 0 AND Class B trap condition TRUE Next Instruction count count 1 END WHILE count 0 Data_Page DPPx AND SFR_range Standard Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence Note The EXTPR instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EXTPR Rwm data DC 11 m 2 EXTPR pag data D7 11 0 pp 0 00pp 4 76 172 ky ST10 FAMILY PROGRAMMING MANUAL EXTR Syntax Operation Description Begin EXTended Register Sequence EXTR opl
62. ILY PROGRAMMING MANUAL CoMACM R Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result 142 172 Multiply Accumulate Parallel Data Move amp Optional Round Multiply Multiply Accumulate Instructions CoMACM opl op2 IF MP 1 THEN tmp opl1 0p2 lt lt 1 ACC ACC tmp ELSE tmp opl op2 ACC ACC tmp END IF IDX IDXi CoMACM opl op2 rnd IF MP 1 THEN tmp opl op2 1 ACC ACC tmp 00 0000 8000 ELSE tmp opl op2 ACC ACC tmp 00 0000 8000 END IF MAL lt 0 IDX lt IDX CoMACM opl op2 IF MP 1 THEN tmp lt opl1 0p2 lt lt 1 ACC lt ACC tmp ELSE tmp opl op2 ACC ACC tmp END IF IDX IDXi CoMACMR opl op2 IF MP 1 THEN tmp lt opl1 0p2 lt lt 1 ACC tmp ACC ELSE tmp opl op2 ACC tmp ACC END IF IDX lt IDXi CoMACMR opl op2 rnd IF MP 1 THEN tmp lt opl1 0p2 lt lt 1 ACC tmp ACC 00 0000 8000 ELSE tmp opl op2 ACC tmp ACC 00 0000 8000 END IF MAL lt 0 IDX
63. L Set if the contents of the ACC is automatically saturated Not affected otherwise 140 172 ky Addressing Modes ST10 FAMILY PROGRAMMING MANUAL Mnemonic Rep CoMACsu Rwy Rwy No CoMACsu Rwy Rwy No CoMACsu Rwy RwQ rnd No CoMACRsu Rwy Rwy No CoMACRsu Rwy Rwy rnd No CoMACsu IDX Rw G Yes CoMACsu IDX Rw4G Yes CoMACsu IDX O Rw rnd Yes CoMACRsu IDX Rw Yes CoMACRsu IDX Rw rnd Yes CoMACsu Rw Rw Yes CoMACsu Rwy RwQG Yes CoMACsu Rwy Rw rnd Yes CoMACRsu Rw Rw Yes CoMACRsu Rwy Rw rnd Yes Examples CoMACsu R5 R8 rnd CoMACsu R2 R7 CoMACsu IDXO QXO R11 QRO Repeat 3 times CoMACsu IDX1 R9 Repeat MRW times CoMACsu R3 R7 QRO CoMACRsu IDX1 QX0 R4 rnd 2 Format Bytes A3 nm 50 00 4 A3 nm 60 00 4 A3 nm 51 00 4 A3 nm 70 00 4 A3 nm 71 00 4 93 Xm 50 rrrr rqqq 4 93 Xm 60 rrrr rqqq 4 93 Xm 51 rrrr rqqq 4 93 Xm 70 rrrr rqqq 4 93 Xm 71 rrrr rqqq 4 83 nm 50 rrrr rqqq 4 83 nm 60 rrrr rqqq 4 83 nm 51 rrrr rqqq 4 83 nm 70 rrrr rqqq 4 83 nm 71 rrrr rqqq 4 ACC ACC R5 R8 rnd ACC ACC R2 R7 ACC lt ACC IDX0 R11 R11 R11 QRO IDXO IDXO QX0 ACC ACC IDX1 R9 R2 u T 22 IDX1 IDX1 2 ACC ACC R3 R7 R7 R7 QRO ACC IDX1 R4 ACC IDX1 IDX1 QX0 141 172 ST10 FAM
64. Lus 170 172 ky ST10 FAMILY PROGRAMMING MANUAL Revision 4 revision 3 Instructions CoMULsu CoMULus Addressing modes corrected CoMAC r su CoMAC r us COMACM r su Function code in Table 30 corrected CoMAC r us CONOP CoSHL CoSHR CoASHR CoSTORE Instructions JBC and JNBS Condition flags corrected instructions and working register indexes Instruction CoSHL Description clarified Only shift values from 0 to 8 inclusive Instruction CoNOP IDX amp addressing mode and example removed Reference to this addressing mode removed from Table 29 Instruction BCLR Condition flag Z corrected MAC instruction descriptions Ordered Alphabetically Section 2 1 Addressing modes Paragraph added Section 1 2 1 Definition of measurement units Fcpu changed to 0 50MHz Revision 3 revision 2 CoSUB2r replaced CoSUBr2 In MAC instructions lower case r has replaced upper case R for optional repeat Revision 2 revision 1 Definition of measurement units on page 12 ALE Cycle Time corrected Integer Addition with Carry on page 59 instruction name changed from ADDBC to ADDCB ky 171 172 ST10 FAMILY PROGRAMMING MANUAL Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the produc
65. MENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FORMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singa
66. Mus IDX Rw4G Yes 93 Xm A8 rrrr rqqq 4 CoMACMus IDX Rw rnd Yes 93 Xm 99 rrrr rqqq 4 CoMACMRus IDX Rw4G Yes 93 Xm B8 rrrr rqqq 4 CoMACMRus IDX Rw rnd Yes 93 Xm B9 rrrr rqqq 4 Examples CoMACMus IDX1 QX0 R10 QR1 rnd ACC ACC IDX1 R10 rnd lt R10 QR1 IDX1 QX0 lt IDX1 IDX1 QXO Repeat 3 times CoMACMus CoMACMus IDXO QX0 R8 QR0 ACC IDX0 R8 E R8 QRO IDXO QX0 IDX0 IDX0 QXO0 Repeat MRW times CoMACMRus CoMACMRus IDX1 QX1 R7 QRO rnd IDX1 R7 ACC rnd R7 QRO IDX1 QX1 lt IDX1 IDX1 QX1 148 172 CoMACM R su ST10 FAMILY PROGRAMMING MANUAL Mix Multiply Accumulate Parallel Data Move amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMACMsu opl op2 Operation tmp lt op1 op2 ACC lt ACC tmp IDX IDX Syntax CoMACMsu opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 8000 MAL 0 IDX IDX Syntax CoMACMsu opl op2 Operation tmp lt gt opl op2 ACC ACC tmp IDX IDX Syntax CoMACMRsu opl op2 Operation tmp Ko opli op2 ACC tmp ACC IDX IDX Syntax CoMACMR
67. NUAL ROR Rotate Right Syntax ROR opl op2 Operation count op2 C g 0 V lt 0 DO WHILE count 0 V V v C C oplg opl Oad n 0 14 oplis lt C count lt count 1 END WHILE Data Types WORD Description Rotates the destination word operand op1 right by as many times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags E Z C N x S S E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the rotate operation a 1 is shifted out of the carry flag Cleared for a rotate count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic ROR Rwy Rwy ROR Rwa data 110 172 Format Bytes 2C nm 2 3C n 2 ST10 FAMILY PROGRAMMING MANUAL SCXT Switch Context Syntax SCXT opl op2 Operation tmp1 opl tmp2 0p2 SP SP 2 SP tmpl 0p1 tmp2 Data Types WORD Description Used to switch contexts for any register Switching context is a push and load operation The contents of the register specified by the f
68. RD Description Performs a 2 s complement binary addition of the source operand specified by op2 the destination oper and specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruc tion can be used to perform multiple precision arithmetic Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ADDC Rwy Rwy 10 nm 2 ADDC Rwa Rw 8 n 10ii 2 ADDC Rwa Rw 8 n llii 2 ADDC Rwy data 18 n 0 2 ADDC reg datay 6 RR 4 ADDC reg mem 2 RR MM MM 4 ADDC mem reg 4 RR MM MM 4 41 172 ST10 FAMILY PROGRAMMING MANUAL ADDCB Integer Addition with Carry Syntax ADDCB opl op2 Operation 0p1 opl op2 C Data Types BYTE Description Performs a 2 s complement binary addition of the source operand specified by op2 the destination oper and specified by op1 and the previously generated carry bit The sum is then stored in op1 This
69. ST10 FAMILY PROGRAMMING MANUAL Ref ST10FPM ST10 FAMILY PROGRAMMING MANUAL TABLE OF CONTENTS Page 1 INTRODUCTION L 3 2 STANDARD INSTRUCTION SET eese nennen nennen nnne nnns 4 2 1 ADDHRESSING MODENS u a tiani tete et t ette ee imet Eee ete xe iw a teen 4 2 1 1 Short adressing Modas u Q aS awa ener ennt ennt a enne sten nnns 4 2 1 2 Long addressing Mode ist ite ite EROR REPE IURATI 5 2 1 3 DPP override mecharism eeii teen EC TT 6 2 1 4 Indirect addressing modes U seer 6 2 1 5 Gonstants u uu EE a Ha Ea boot teu A A 7 2 1 6 Branch target addressing modes sse 7 2 2 INSTRUCTION EXECUTION TIMES essen ennemis 8 2 2 1 Definition of measurement units 9 2 2 2 Minimum state tiles oet Sau eet t o dt ree Ego ke EOD M wq aZ Doa poi merced 10 2 2 8 Additional state timos ret cte c t EORR RESO Ur eee Su REO asa ba HEE aaa db 10 2 3 INSTRUCTION SET SUMMARY u u u L Sau suu gagu Cara o KERAS a KTZ sassa 13 2 4 INSTRUCTION SET ORDERED BY FUNCTIONAL GROUP 15 2 5 INSTRUCTION SET ORDERED BY OPCODES sese eren 26 2 6 INSTRUCTION CONVENTIONS L l nennen nnn ninh nnn inneren 34 2 6 1 IMSTHUCTION MAM E 34 2 6 2 A M 34 2 6 3 Gicu ELTE 34 2 6 4 Data TYPOS EE 35 2 6 5 Derri s u ua ICD 35 2 6 6 G
70. Software Reset Syntax SRST Operation Software Reset Description This instruction is used to perform a software reset A software reset has the same effect on the micro controller as an externally applied hardware reset To insure that this instruction is not accidentally exe cuted it is implemented as a protected instruction Flags 0 E Always cleared Z Always cleared V Always cleared C Always cleared N Always cleared Addressing Modes Mnemonic Format Bytes SRST B7 48 B7 B7 4 114 172 er ST10 FAMILY PROGRAMMING MANUAL SRVWDT Service Watchdog Timer Syntax SRVWDT Operation Service Watchdog Timer Description This instruction services the Watchdog Timer It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence Once this instruction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accidentally executed it is imple mented as a protected instruction Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes SRVWDT A7 58 A7 A7 4 ky 115 172 ST10 FAMILY PROGRAMMING MANUAL SuB Integer Subtraction Syntax SUB opl op2 Operation op1 opl op2 Data Types WORD Description Performs a 2 s complement binary subtraction of the source operand specified by op2 from the dest
71. Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then the condition MP flag is set it is one bit left shifted then it is optionally negated prior being added subtracted to from the 40 bit ACC register content Finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The option is used to negate the specified product the R option is used to negate the accumulator content and finally the rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and allows up to two parallel memory reads 134 172 er ST10 FAMILY PROGRAMMING MANUAL MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Address
72. Unit Register MSW MAH MAL MAS MRW MCW ACC MAC Accumulator consisting of lowest byte of MSW MAH MAL Immediate constant the number of significant bits is represented by x 31 126 172 3 4 5 Instruction format The instruction format is the same as that of the standard instruction set In addition the following new symbols are used raes eaa X 4 bit IDX addressing mode encoding see following table 3 bit GPR offset encoding for new GPR indirect with offset encoding 5 bit repeat field wwwwiw 5 bit CoReg address for COSTORE instructions 4 bit immediate shift value 5 bit immediate shift value Table 31 IDX Addressing Mode Encoding and GPR offset Encoding IDXO QX0 IDXO QX1 IDXO QX1 ST10 FAMILY PROGRAMMING MANUAL Table 31 IDX Addressing Mode Encoding and GPR offset Encoding continued Addressing Mode 4 bit Encoding 3 4 6 Flag states rm meme 3 4 7 Repeated instruction syntax Repeatable instructions CoXXX are expressed as follows when repeated Repeat Repeat datas times CoXXX or MRW times CoXXX When MRW is invoked the instruction is repeated MRWA 1 times therefore the maximum num ber of times an instruction can be repeated is 8 192 213 times datas is an integer value specifying the number of times an instruction is repeated datas must be less than 32 Therefore CoXXX can only be repeated less than 3
73. a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMPI2 Rwa data 90 n 2 CMPI2 Rwy dataig 96 Fn 4 CMPI2 Rw mem 92 Fn MM MM 4 n 66 172 ky ST10 FAMILY PROGRAMMING MANUAL CPL Integer One s Complement Syntax CPL opi Operation 0p1 opl Data Types WORD Description Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 Flags E Z V C N 0 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CPL Rw 91 nO 2 ky 67 172 ST10 FAMILY PROGRAMMING MANUAL CPLB Integer One s Complement Syntax CPL opi Operation op1 opl Data Types BYTE Description Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 Flags E Z V C N 0 E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of
74. accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses Physical addresses are generated from indirect address pointers by the following algorithm 1 Calculate the physical address of the word GPR which is used as indirect address pointer by using the specified short address Rw and the current register bank base address CP GPRAddress CP 2 x ShortAddress 2 Pre decremented indirect address pointers Rw are decremented by a data type depen dent value A 1 for byte operations A 2 for word operations before the long 16 bit address is generated GPRAddress GPRAddress A optional step 3 Calculate the long 16 bit Rw datal6 if selected address by adding a constant value if selected to the content of the indirect address pointer Long Address GPR Address Constant 4 Calculate the physical 18 bit or 24 bit address using the resulting long address and the corre sponding DPP register content see long mem addressing modes Physical Address DPPi Long Address 3FFFh 5 Post Incremented indirect address pointers Rw are incremented by a data type depen dent value A 1 for byte operations A 2 for word operations GPR Address GPR Address A optional step 15 14 13 EXTER 16 bit Lon
75. affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes NOP CC 00 2 ky 97 172 ST10 FAMILY PROGRAMMING MANUAL OR Logical OR Syntax OR opl op2 Operation op1 opl v op2 Data Types WORD Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand spec ified by op1 The result is then stored in op1 Flags E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes OR Rwy Rwy 70 nm 2 OR Rwa Rw TD FOAI 2 OR Rwa Rw 78 n 11lii 2 OR Rwy datas 78 n 0O 2 OR reg Tdart ais 76 RR d 4 OR reg mem 72 RR MM MM 4 OR mem reg 74 RR MM MM 4 98 172 ky ORB Logical OR Syntax ORB Operation op1 Data Types BYTE Description lt ST10 FAMILY PROGRAMMING MANUAL opl op2 opl v op2 Performs a bitwise logical OR of the source operand specified by op2 and the destination operand spec ified by op1 The result is then stored in op1 Flags E Z V N 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z
76. affected N Not affected Addressing Modes Mnemonic Format Bytes JMPA cc caddr EA c0 MM MM 4 ky 83 172 ST10 FAMILY PROGRAMMING MANUAL JMP I Indirect Conditional Jump Syntax JMP 1 opl op2 Operation IF opl 1 THEN IP op2 ELSE ext Instruction END IF Description If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPI instruction is executed nor mally Condition Codes See Condition code Table 24 page 35 Flags E Z V N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format JMPI cc Rw 9C cn Bytes 84 172 ST10 FAMILY PROGRAMMING MANUAL JMPR Relative Conditional Jump Syntax JMPR opl op2 Operation IF opl 1 THEN IP IP sign extend op2 ELSE ext Instruction END IF Description If the condition specified by op1 is met program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction If the specified condition is not met program execution continues norm
77. ally with the instruction following the JMPR instruction Condition Codes See condition code Table 24 page 35 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JMPR cc rel cD rr 2 ky 85 172 ST10 FAMILY PROGRAMMING MANUAL JMPS Absolute Inter Segment Jump Syntax JMPS opl op2 Operation CSP lt opl IP lt op2 Description Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes JMPS seg caddr FA ss MM MM 4 86 172 ky ST10 FAMILY PROGRAMMING MANUAL JNB Relative Jump if Bit Clear Syntax JNB opl op2 Operation IF opl 0 THEN IP IP sign extend op2 ELSE Next Instruction END IF Data Types BIT Description If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calcu lation is the address of the instruction following the JNB instruction If the specified bit is set the instruc tion following the JNB instruction is
78. ate times Some operand accesses can extend the execu tion time of an instruction Tin Since the additional time Tiada is generally caused by internal instruc tion pipelining it may be possible to minimize the effect by rearranging the instruction sequences Simulators and emulators offer a high level of pro grammer support for program optimization The following operands require additional state times Internal ROM operand reads add 2 States Both byte and word operand reads always require 2 additional state times ST10 FAMILY PROGRAMMING MANUAL Internal RAM operand reads via indirect addressing modes Tiada 0 or 1 State Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause additional state time However reading an indirectly addressed internal RAM operand will extend the pro cessing time by 1 state time if the preceding instruction auto increments or auto decrements a GPR as shown in the following example MOV R1 RO auto increment RO In 1 MOV R3 R2 if R2 points into the internal RAM space Traga 1 State In this case the additional time can be avoided by putting another suitable instruction before the instruc tion 4 4 indirectly reading the internal RAM Internal SFR operand reads Tada 0 1 State or 2 States SFR read accesses do NOT usually require additional processing time In some rare cases however either one or two additional stat
79. case most of the instructions can be processed in just one machine cycle All external memory accesses are performed by the on chip External Bus Controller EBC which works in parallel with the CPU Instructions from external memory cannot be pro cessed as fast as instructions from the internal ROM because it is necessary to perform data transfers sequentially via the external interface In contrast to internal ROM program execution the time required to process an external program additionally depends on the length of the instruc tions and operands on the selected bus mode and on the duration of an external memory cycle Processing a program from the internal RAM space is not as fast as execution from the internal ROM area but it is flexible i e for loading tempo rary programs into the internal RAM via the chip s serial interface or end of line programming via the bootstrap loader The following description evaluates the minimum and maximum program execution times which is sufficient for most requirements For an exact determination of the instructions state times the facilities provided by simulators or emulators should be used This section defines measurement units summa rizes the minimum standard state times of the 16 bit microcontroller instructions and describes the exceptions from the standard timing ST10 FAMILY PROGRAMMING MANUAL 2 2 1 Definition of measurement units The following measurement uni
80. ces support an override mechanism for the DPP addressing scheme see section 2 1 3 DPP override mechanism Long addresses 16 bit are treated in two parts Bits 13 0 specify a 14 bit data page offset and bits 15 14 specify the Data Page Pointer 1 of 4 The DPP is used to generate the physical 24 bit address see Figure 1 Figure 1 Interpretation of a 16 bit long address ST10 FAMILY PROGRAMMING MANUAL All ST10 devices support an address space of up to 16MByte so only the lower ten bits of the selected DPP register content are concatenated with the 14 bit data page offset to build the physi cal address Note Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP regis ters are initialized so that all long addresses are directly mapped onto the identical physical addresses within seg ment 0 16 bit Long Address ee aes FF 0 14 bit page offset 24 bit Physical Address The long addressing mode is referred to by the mnemonic mem Table 2 Summary of long address modes Physical Address Long Address Range Scope of Access mem 3FFFh mem SFFFh mem S3FFFh mem S3FFFh 0000h 3FFFh 4000h 7FFFh 8000h BFFFh C000h FFFFh Any Word or Byte pag mem 3FFFh 0000h FFFFh 14 bit Any Word or Byte mem 0000h FFFFh 16 bit Any Word or Byte 5 172 ST10 FAMILY PROGRAMMING MANUAL 2 1 3 DPP override mechanism
81. cheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 A0 The value of op2 defines the length of the effected instruction sequence Note The EXTSR instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EXTSR Rwm data DC 10 m 2 EXTSR seg data D7 10 0 ss 00 4 ky 79 172 ST10 FAMILY PROGRAMMING MANUAL IDLE Enter Idle Mode Syntax IDLE Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occurs
82. count opl 1 lt opl lt 4 Disable interrupts and Class A traps SFR_range Extended DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count lt count 1 END WHILE count O SFR_range Standard Enable interrupts and traps Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The value of op1 defines the length of the effected instruction sequence Note The EXTR instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EXTR Ldart a D1 10 0 2 ky 77 172 ST10 FAMILY PROGRAMMING MANUAL EXTS Begin EXTended Segment Sequence Syntax EXTS opl op2 Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment opl DO WHILE count 0 AND Class B trap condition TRUE Next Instruction count count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified
83. d option and if the MS bit is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000p respectively This instruction is repeatable when op 1 is not an immediate operand MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry is generated rnd Cleared otherwise SV Set if an arithmetic overflow occurred rnd Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated rnd Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoASHR Rwy Yes A3 nn AA rrrr r000 4 CoASHR Rwy rnd Yes A3 nn BA rrrr r000 4 CoASHR fdatas No A3 00 A2 ssss s000 4 CoASHR fdatas rnd No A3 00 B2 ssss s000 4 CoASHR Rw Yes 83 mm AA rrrr rqgq 4 CoASHR Rw rnd Yes 83 mm BA rrrr rqqq 4 Examples CoASHR 3 rnd ACC ACC gt gt a 3 rnd CoASHR R3 ACC ACC gt gt a R3 4 0 CoASHR R10 QRO ACC ACC gt gt a R10 4 9 R10 R10 QRO ky 131 172 ST10 FAMILY PROGRAMMING MANUAL CoCMP Compare Group Compare Instructions Syntax CoCMP opl op2 Operation tmp op2 N opl ACC lt gt tmp Data Types DOUBLE WORD Description Subtracts a 40 bit signed operand from the 40 bit Accumulator content and update the N
84. d otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing Modes Mnemonic MOVBS RD z ROm MOVBS reg mem MOVBS mem reg Format D0 mn D2 RR MM MM D5 RR MM MM Bytes 2 4 4 91 172 ST10 FAMILY PROGRAMMING MANUAL MOVBZ Move Byte Zero Extend Syntax MOVBZ opl op2 Operation low byte opl op2 high byte opl 00 Data Types WORD BYTE Description Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags E Z V C N 0 E Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Always cleared Addressing Modes Mnemonic Format Bytes MOVBZ Rb Rs CO mn 2 MOVBZ reg mem C2 RR MM MM 4 MOVBZ mem reg C5 RR MM MM 4 92 72 ky ST10 FAMILY PROGRAMMING MANUAL MUL Signed Multiplication Syntax MUL opl op2 Operation MD lt opl op2 Data Types WORD Description Performs a 16 bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register Flags E Z C N S 0 E Always cleared Z Set if the result equals zero Cleared othe
85. ddr E2 RR MM MM 4 100 172 yy ST10 FAMILY PROGRAMMING MANUAL POP Pop Word from System Stack Syntax POP opl Operation tmp lt SP SP SP 2 opl tmp Data Types WORD Description Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two Flags E Z V C N E Set if the value of the popped word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the popped word is set Cleared otherwise Addressing Modes Mnemonic Format Bytes PGP reg FC RR 2 ky 101 172 ST10 FAMILY PROGRAMMING MANUAL PRIOR Prioritize Register Syntax PRIOR opl op2 Operation tmp op2 count Lemn DO WHILE tmp 5 1 AND count 15 AND op2 0 tmp lt tmpg i count lt count 1 END WHILE 0p1 count Data Types WORD Description This instruction stores a count value in the word operand specified by op1 indicating the number of single bit shifts required to normalize the operand op2 so that its most significant bit is equal to one If the source operand op2 equals zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared
86. ddresses are used to generate physical addresses Short bitoff addresses from 00h to 7Fh use 00 FDOOh as a base address therefore they specify the 128 highest internal RAM word locations 00 FD00h to 00 FDFEh Short bitoff addresses from 80h to EFh use 00 FF00h as a base address to specify the highest internal SFR word locations 00 FFOOh to 00 FFDEh or use 00 F100h as a base address to specify the highest internal ESFR word locations 00 F100h to 00 F1DEh bitoff accesses to the ESFR area require a preceding EXT R instruction to switch the base address For short bitoff addresses from FOh to FFh only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR bitaddr Any bit address is specified by a word address within the bit addressable memory space see bitoff and by a bit position bitpos within that word Thus bitaddr requires twelve bits in the instruction format Scope of Access Word 16 values Byte 16 values SFRs Word Low byte ESFRs Word Low byte GPRs Word 16 values GPRs Bytes 16 values Bit word offset 128 values Bit word offset 128 values Bit word offset 16 values Any single bit 2 1 2 Long addressing mode Long addressing mode uses one of the four DPP registers to specify a physical 18 bit or 24 bit address Any word or byte data within the entire address space can be accessed in this mode All devi
87. e times will be caused by particular SFR operations Reading an SFR immediately after an instruction which writes to the internal SFR space as shown in the following example I MOV TO 1000h write to Timer 0 n Pai ADD R3 Tl read from Timer 1 Tradd 1 State Reading the PSW register immediately after an instruction which implicitly updates the flags as shown in the following example T ADD RO 1000h implicit modification of PSW flags n Ina1 BAND Qr read from PSW Tradd 2 States Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitly writes to the SP register as shown in the following example MOV SP 0FBOOh explicit update of the stack pointer Lua SCXT Rl 1000h implicit decrement of the stack pointer Traga 2 States In each of these above cases the extra state times can be avoided by putting other suitable instructions before the instruction 4 reading the SFR External operand reads Tiada 1 ACT Any external operand reading via a 16 bit wide data bus requires one additional ALE Cycle Time Read ing word operands via an 8 bit wide data bus takes twice as much time 2 ALE Cycle Times as the read ing of byte operands External operand writes T aqq 0 State 1 ACT Writing an external operand via a 16 bit wide data bus takes one additional ALE Cycle Time For timing calculation of the external program parts
88. eared otherwise only set in case of 80004 by 8000 multiplication SL Not affected when MP or MS are cleared otherwise only set in case of 8000p by 8000p multipli cation 154 172 er Addressing Modes Mnemonic CoMUL CoMUL CoMUL CoMUL CoMUL CoMUL CoMUL CoMUL CoMUL Examples CoMUL CoMUL CoMUL CoMUL CoMUL ST10 FAMILY PROGRAMMING MANUAL Multiplication Examples EXE Tas al Cases MP 0 MS x MP 1 MS 0 MP 1 MS 1 MP 0 MS x MP 1 MS x MP 1 MS x MP 0 MS x MP 1 MS x MP 0 MS x 8000 7FFFp 4001p Rep Format Bytes Rwy Rwy A3 nm CO 00 4 Rw Rwy A3 nm C8 00 4 Rw Rwy rnd A3 nm Cl 00 4 IDX Rw G 93 Xm C0 0 0qqq 4 IDX Rw 93 Xm C8 0 0qqq 4 IDX Rw rnd O 93 Xm C1 0 0qqq 4 Rwy Rw O 83 nm CO 0 0qqq 4 Rw RwQG 83 nm C8 0 0qqq 4 Rw Rw rnd 83 nm C1 0 0qqq 4 RO Rl rnd ACC lt RO R1 rnd R2 R6 ACC lt R2 R6 R6 R6 2 IDXO QX1 R11 ACC IDXO R11 R11 lt R11 2 IDX0 IDXO QX1 IDX1 R15 QR0O ACC IDX1 R15 R15 R15 QRO IDX1 IDX1 2 IDX1 QX0 R9 QR1 rnd ACC IDX1 R9 rnd R9 R9 ORI IDX1 IDX1 QXO 80005550 400 5 008 sasa EXE E Cd RUNI TAFE o oo sein oov o 9 E EXE EE CENE M gW T INEI E E EN EL es
89. er word of the MD register MDH Flags E Z C N S 0 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes DIV Rwa 4B nn 2 70 172 ky ST10 FAMILY PROGRAMMING MANUAL DIVL 32 by 16 Signed Division Syntax DIVL opi Operation MDL MD opl MDH MD mod opl Data Types WORD DOUBLEWORD Description Performs an extended signed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags E Z C N S 0 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes DIVL Rw 6B nn 2 ky 71 172 ST10 FAMILY PROGRAMMING MANUAL DIVLU 32 by 16 Unsigned Division
90. es CoMULus Rwy Rwy A3 nm 80 00 4 CoMULus Rwy Rwy A3 nm 88 00 4 CoMULus Rwa Rwy rnd A3 nm 81 00 4 CoMULus IDX Rw 93 Xm 80 0 0qqq 4 CoMULus IDX Rw G 93 Xm 88 0 0qqq 4 CoMULus IDX Rw rnd 93 Xm 81 0 0qqq 4 CoMULus Rw Rw 83 nm 80 0 0qqq 4 CoMULus Rwy Rw 83 nm 88 0 0qqq 4 CoMULus Rw Rw rnd 83 nm 81 0 0qqq 4 158 172 yy ST10 FAMILY PROGRAMMING MANUAL Examples CoMULus RO Rl rna ACC RO R1 rnd CoMULus R2 R6 ACC R2 R6 R6 R6 2 CoMULus IDX1 QX0 R11 QR0 ACC IDX1 R11 R11 R11 QRO z IDX1 IDX1 QXO CoMULus IDX0 R15 ACC IDXO R15 CoMULus IDXO QX0 R9 OR1 rnd ACC IDX0O R9 rnd R9 R9 OR1 IDXO IDXO QXO Multiplication Examples NECLCNESGEGLIEKCSERESGEERENESESESET s n HEU o c REN ERN RC bass EE D MC ELK NEECHESENESEEEXES re Tee po To fe To fe caes may Fa o s mes re 9 e 91 ripe Tem pe T9 Po oe ky 159 172 ST10 FAMILY PROGRAMMING MANUAL CoMULsu Mixed Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULsu opl op2 Operation ACC opl op2 Syntax CoMULsu opl op2 Operation ACC lt opl op2 Syntax CoMULsu opl op2 rnd Operation ACC
91. es DOUBLE WORD Result 40 bit signed value Description Compares a signed 40 bit operand against the ACC register content The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended If the contents of the ACC register is smaller than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC register remains unchanged The MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes MAC Flags N Z C SV E SL 0 N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC register is changed Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMAX Rwy RWg No A3 nm 3A 00 4 CoMAX IDX Rw4G Yes 93 Xm 3A rrrr rqqq 4 CoMAX Rwy Rw Yes 83 nm 3A rrrr rqqq 4 Examples CoMAX IDX1 QX0 R11 QR1 ACC lt Max ACC R11 IDX1 R11 R11 QR1 IDX1 IDX1 QXO CoMAX R1 R10 ACC Max ACC R10 N R1 Repeat 23 times CoMAX CoMAX R5 R6 QRO ACC Max ACC R6 N R5 R6 R6 ORO ky 151 172 ST10 FAMILY PROGRAMMING MANUAL CoMIN Minimum Group Compare Instructions Syntax CoMIN o
92. f the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Addressing Modes Mnemonic Format Bytes OVB Rb Rbi Fl nm 2 OVB Rb data El n 2 OVB reg datais E7 RR 4 OVB Rb Rwy A9 nm 2 OVB Rba Rwyt 99 nm 2 OVB Rwa Rb B9 nm 2 OVB Rw Rb 89 nm 2 OVB Rwy Rwy C9 nm 2 OVB Rwat Rwy D9 nm 2 OVB Rwa Rwg E9 nm 2 OVB Rb Rwy t datay F4 nm 4 OVB Rw t data 6 RD E4 nm 4 OVB Rw mem A4 On MM MM 4 OVB mem Rwa B4 On MM MM 4 OVB reg mem F3 RR MM MM 4 OVB mem reg F7 RR MM MM 4 90 172 ky 1 THEN high byte opl high byte opl hn MOVBS Syntax MOVBS Operation low byte opl IF op2 ELSE END IF Data Types WORD BYTI Description ST10 FAMILY PROGRAMMING MANUAL Move Byte Sign Extend opl op2 op2 lt FF lt 00 Moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags E Z V N E Always cleared Z Set if the value of the source operand op2 equals zero Cleare
93. f this instruction the PWRDN instruction is only enabled when the non maskable interrupt pin NMI is in the low state Other wise this instruction has no effect Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes PWRDN 97 68 97 97 4 104 172 yy ST10 FAMILY PROGRAMMING MANUAL RET Return from Subroutine Syntax RET Operation IP lt SP SP lt SP 2 Description Returns from a subroutine The IP is popped from the system stack Execution resumes at the instruction following the CALL instruction in the calling routine Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes RET CB 00 2 ky 105 172 ST10 FAMILY PROGRAMMING MANUAL RETI Return from Interrupt Routine Syntax RETI Operation IP SP SP lt SP 2 IF SYSCON SGTDIS 0 THEN CSP lt SP SP e SE 2 END IF PSW lt SP SP lt SP 2 Description Returns from an interrupt routine The PSW IP and CSP are popped off the system stack Execution resumes at the instruction which had been interrupted The previous system state is restored after the PSW has been popped The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register
94. ffected by the MP mode flag contained in the MCW register option is used to negate the specified product R option is used to negate the accumu lator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL reg ister is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and allows up to two parallel memory reads MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise 138 172 yy ST10 FAMILY PROGRAMMING MANUAL Addressing Modes Mnemonic Rep Format Bytes CoMACus Rwy RWg No A3 nm 90 00 4 CoMACus Rwy Rwy No A3 nm AO 00 4 CoMACus Rwy RwQ rnd No A3 nm 91 00 4 CoMACRus Rwy Rwy No A3 nm BO 00 4 CoMACRus Rwy Rwy rnd No A3 nm Bl 00 4 CoMACus IDX Rw G Yes 93 Xm 90 rrrr rqqq 4 CoMACus IDX Rw Yes 93 Xm AO rrrr rqqq 4 CoMACus IDX Rw rnd Yes 93 Xm 91 rrrr rqqq 4 CoMACRus IDX Rw
95. flow occurs 168 172 yy ST10 FAMILY PROGRAMMING MANUAL Addressing Modes Mnemonic Rep Format Bytes CoSUB Rwy Rwy No A3 nm OA OO 4 CoSUBR Rwy Rwy No A3 nm 12 00 4 CoSUB2 Rwy Rwy No A3 nm 4A 00 4 CoSUB2R Rwy Rwy No A3 nm 52 00 4 CoSUB IDX Rw Yes 93 Xm OA rrrr rqqq 4 CoSUBR IDX Rw G Yes 93 Xm 12 rrrr rqqq 4 CoSUB2 IDX Rw4G Yes 93 Xm 4A rrrr rqqq 4 CoSUB2R IDX Rw G Yes 93 Xm 52 rrrr rqqq 4 CoSUB Rwy Rw Yes 83 nm OA rrrr rqqq 4 CoSUBR Rwy RwQG Yes 83 nm 12 rrrr rqqq 4 CoSUB2 Rw Rw Yes 83 nm 4A rrrr rqqq 4 CoSUB2R Rw RwQG Yes 83 nm 52 rrrr rqqq 4 Examples CoSUB RO R1 ACC ACC R1 N RO CoSUB2 R2 R6 ACC ACC 2 R6 R2 R6 R6 2 Repeat 3 times CoSUB CoSUB IDX1 QX1 R10 QRO ACC ACC R10 N IDX1 R10 R10 QRO IDX1 IDX1 QX1 Repeat MRW times CoSUB2R CoSUB2R R4 R8 QR1 ACC 2 R8 R4 ACC R8 R8 QR1 Subtraction Examples m us wi seeeeeo accom z V a 0 ise RH Eg REE r IE ss eo ho RRR gt sakaki I TR pedo pese eo CoSUB2 x RRR H 0073583D2A O 0 FO 9 x ERE 8 E 8 CoSUB2 0000 3000 7F FFFF FFFF CoSUB2 0001 0000 80 0000 0000 7F 9FFF FFFF 7F FFFF FFFE FF 8000 0000p 1 CoSUB FFFF FFFF 7FFFFFFFFF 8000000000 bud Mad nad
96. g Address pag 24 bit Physical Address EXTS R 16 bit Long Address seg 24 bit Physical Address 6 172 14 bit page offset 16 bit segment offset ST10 FAMILY PROGRAMMING MANUAL The following indirect addressing modes are pro vided Table 3 Table of indirect address modes Most instructions accept any GPR R15 RO0 as indirect address pointer Some instructions however only accept the lower four GPRs R3 R0 Rw The specified indirect address pointer is automatically incremented by 2 or 1 for word or byte data operations after the access Rw The specified indirect address pointer is automatically decremented by 2 or 1 for word or byte data operations before the access Rw data A 16 bit constant and the contents of the indirect address pointer are added before the long 16 bit address is calcu lated 2 1 5 Constants The ST10 Family instruction set supports the use of wordwide or bytewide immediate constants For optimum utilization of the available code stor age these constants are represented in the instruction formats by either 3 4 8 or 16 bits Therefore short constants are always zero extended while long constants can be trun Table 5 Branch target address summary Target Address Target Segment Valid Address Range TT IP 2 rel 1 CP 2 Rw cated to match the data format required for the operation Table 4 Table of constants Mnemon
97. gn extended and counts the relative dis tance in words The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack rep resents the return address of the calling routine The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction Condition Codes See condition code Table 24 page 35 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes CALLR rel BB rr 2 GI 59 172 ST10 FAMILY PROGRAMMING MANUAL Call Inter Segment Subroutine CALLS Syntax CALLS Operation SP SP SP SP CSP IP Description opl op2 A branch is taken to the absolute location specified by op2 within the segment specified by op1 The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address to the calling routine The previous value of the CSP is also placed on the system stack to insure correct return to the calling segment Condition Codes See condition code Table 24 page 35 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected
98. ic Word operation Byte operation Note Immediate constants are always signified by a leading number sign 2 1 6 Branch target addressing modes Jump and Call instructions use different address ing modes to specify the target address and seg ment Relative absolute and indirect modes can be used to update the Instruction Pointer register IP while the Code Segment Pointer register CSP can only be updated with an absolute value A special mode is provided to address the interrupt and trap jump vector table situated in the lowest portion of code segment O rel 00h 7Fh Rw 0 15 CSP seg seg 0 255 0000h 4 trapz CSP 0000h trapz 00h 7Fh 7 172 ST10 FAMILY PROGRAMMING MANUAL caddr Specifies an absolute 16 bit code address within the current segment Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of caddr must always contain a 0 otherwise a hardware trap would occur rel Represents an 8 bit signed word offset address relative to the current Instruction Pointer contents which points to the instruction after the branch instruction Depending on the offset address range either for ward rel 00h to 7Fh or backward rel 80h to FFh branches are possible The branch instruction itself is repeatedly exe cuted when rel 1 FF for a word sized branch instruction or rel 2 FEh for a dou
99. in the 40 bit ACC register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automat ically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and performs two parallel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table Addressing Mode Overwritten Address IDX QX no change IDX 2 IDX 2 IDX QX ST10 FAMILY PROGRAMMING MANUAL MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACMus IDX Rw G Yes 93 Xm 98 rrrr rqqq 4 CoMAC
100. ina tion operand specified by op1 The result is then stored in op1 Flags E Z V N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes SUB Rwy Rwy 20 nm 2 SUB Rwa Rw 28 n 10ii 2 SUB Rwa Rw 28 n llii 2 SUB Rwy dataj 28 n 0 2 SUB reg dataj 26 RR 4 SUB reg mem 22 RR MM MM 4 SUB mem reg 24 RR MM MM 4 116 172 yy ST10 FAMILY PROGRAMMING MANUAL SUBB Integer Subtraction Syntax SUBB opl op2 Operation op1 opl op2 Data Types BYTE Description Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destina tion operand specified by op1 The result is then stored in op1 Flags E Z V N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be represented in the specified data type Cleared
101. ing Modes Mnemonic CoMAC Rwy Rwy CoMAC Rwy Rwy CoMAC Rw Rwy rnd CoMACR Rwy RWg CoMACR Rw Rwy rnd CoMAC IDX Rw CoMAC IDX Rw G CoMAC IDX Rw rnd CoMACR IDX Rw CoMACR IDX Rw rnd CoMAC Rwy RwQG CoMAC Rwy Rw CoMAC Rw RwQ49 rnd CoMACR Rwy Rw CoMACR Rw Rw rnd Examples CoMAC R3 R4 rnd CoMAC R2 R6 CoMAC IDX0 QX0 R11 QRO0 Repeat 3 times CoMAC CoMAC IDX1 QX1 R9 QRI1 Repeat MRW times CoMAC CoMAC R3 R7 QRO CoMACR ky IDX1 R4 rnd Rep Format Bytes NO A3 nm DO 00 4 NO A3 nm EO 00 4 No A3 nm D1 00 4 NO A3 nm FO 00 4 No A3 nm F1 00 4 Yes 93 Xm DO rrrr rqqq 4 Yes 93 Xm EO rrrr rqqq 4 Yes 93 Xm D1 rrrr rqqq 4 Yes 93 Xm FO rrrr rqqq 4 Yes 93 Xm Fl rrrr rqqq 4 Yes 83 nm DO rrrr rqqq 4 Yes 83 nm EO rrrr rqqq 4 Yes 83 nm Dirrrr rqqq 4 Yes 83 nm FO rrrr rqqq 4 Yes 83 nm Fl rrrr rqqq 4 ACC ACC R3 R4 rnd ACC ACC R2 R6 R6 lt R6 2 ACC ACC IDX0 R11 R11 lt R11 ORD IDX0 IDX0 QX0 ACC ACC IDX1 R9 R9 R9 QR1 Ipx4j lt IDX1 QX1 ACC lt ACC R3 R7 R7 R7 ORO ACC IDX1 R4 ACC rnd R4 xm R4 2 135 172 ST10 FAMILY PROGRAMMING MANUAL CoMAC R u Unsigned Multiply Accumulate amp
102. ion to form common high level language FOR loops of any range Flags E Z V N B B x S x E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMPD1 Rwa data AO n 2 CMPD1 Rwy dataig A6 Fn 4 CMPD1 Rw mem A2 Fn MM MM 4 DE ky 63 172 ST10 FAMILY PROGRAMMING MANUAL CMPD2 Integer Compare amp Decrement by 2 Syntax CMPD2 opl op2 Operation op1 lt gt op2 op1 lt opl 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary sub traction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has com pleted the operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags E Z V N B B x S x E Set if the value of op2 re
103. irst operand op1 are pushed onto the stack That register is then loaded with the value specified by the second operand op2 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes SCXT reg f dataig C6 RR 4 SCXT reg mem D6 RR MM MM 4 ky 111 172 ST10 FAMILY PROGRAMMING MANUAL SHL Shift Left Syntax SHL opl op2 Operation count op2 C lt O DO WHILE count 0 C opl s oplg opl n21 15 oplo lt 0 count lt count b END WHILE Data Types WORD Description Shifts the destination word operand op1 left by as many times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The most significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags E Z V N S E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last most significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic SHL Rwy Rwy SHL Rwy data 112 172 Format Bytes 4C nm 2 5C n 2 ST10 FAMILY
104. j RB AR bl BR ATA WwW gt ojl o NI Ol G He M N N Q Gm l na dd I 31 28 172 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued Xw s Rwr Rwi or Rw Rw or Rw datas Rb Rwi or Rb Rw or Rbr datas bitaddrz z bitaddro q SHL Rw data sS O Rw Rwi or Rw Rw or Rwn datas Rb Rwi or Rb Rw or Rbr datas m s o wm j 99 mm _ j o jem O O s ORB Hex code 6 d o S 3 o 3 AJ 29 172 O O N Hew ode 9 Ieee ord e 9 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued R Rw Rwi or Rw Rw or Rwn datas Rb Rwi or Rb Rw or Rb datas e em a I o 2 El n dataig P Rb RWmt IS Hew ode NEAN ow ELA o E NEN a 2 30 172 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued Der lane mee ome x m pamm _ Low 3 k 2 m jema _ _ 1 79 mms ow pr Ca s m 2 ow jem L9 C CC CC C m ow uma ws mw 2 ww mam _ 1 31 172 ST10 FAMILY PROGRAMMING MANUAL Table 21 Instruction set ordered by Hex code continued gt Eq G e quem 0000 oe
105. jump is taken Table 6 Minimum instruction state times Unit ns Timin Timin ROM ROM 20MHz States CPU clk CALLI CALLA CALLS CALLR PCALL JB JBC JNB JNBS JMPS JMPA JMPI JMPR MUL MULU DIV DIVL DIVU DIVLU MOV B Rn Rm datais RET RETI RETP RETS TRAP All other instructions Instructions executed from the internal RAM require the same minimum time as they would if 10 172 they were fetched from the internal ROM plus an instruction length dependent number of state times as follows For 2 byte instructions Timin RAM Timin ROM 4 States For 4 byte instructions Timin RAM Tjmin ROM 6 States Unlike internal ROM program execution the mini mum time Timin ext to process an external instruction also depends on instruction length Timin ext is either 1 ALE Cycle Time for most of the 2 byte instructions or 2 ALE Cycle Times for most of the 4 byte instructions The following formula represents the minimum execution time of instructions fetched from an external memory via a 16 bit wide data bus For 2 byte instructions Timin ext 1 ACT Tijg ROM 2 States For 4 byte instructions Timin ext 2 ACTSs T in ROM 2 States For instructions fetched from an external memory via an 8 bit wide data bus the minimum number of required ALE Cycle Times is twice the number for those of a 16 bit wide bus Note 2 2 3 Additional st
106. l op2 rnd Operation tmp opl op2 ACC tmp ACC 00 0000 8000 MAL lt 0 Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed and unsigned 16 bit source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended and then it is optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product R option is used to negate the accumu lator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL reg ister is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and allows up to two parallel memory reads o MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise S
107. lags E Z V C N 0 E Always cleared Z Set if the word result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the word result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes BFLDL bitoffo maskg datag OA QQ Q 4 ky 51 172 ST10 FAMILY PROGRAMMING MANUAL BMOV Bit to Bit Move Syntax BMOV opl op2 Operation op1 op2 Data Types BIT Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly Flags E Z V C B 0 0 E Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOV bitaddr bitaddro q 4A QQ ZZ qz 4 52 172 ky ST10 FAMILY PROGRAMMING MANUAL BMOVN Bit to Bit Move amp Negate Syntax BMOVN opl op2 Operation op1 0p2 Data Types BIT Description Moves the complement of a single bit from the source operand specified by op2 into the destination oper and specified by op1 The source bit is examined and the flags are updated accordingly Flags E Z C N 0 B 0 0 B E Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always
108. lags N Z C SV E SL N Set if the m s b of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACMsu IDX Rw G Yes 93 Xm 58 rrrr rqqq 4 CoMACMsu IDX Rw4G Yes 93 Xm 68 rrrr rqqq 4 CoMACMsu IDX Rw rnd Yes 93 Xm 59 rrrr rqqq 4 CoMACMRsu IDX Rw Yes 93 Xm 78 rrrr rqqq 4 CoMACMRsu IDX Rw rnd Yes 93 Xm 79 rrrr rqqq 4 Example CoMACMsu IDX14QX0 R10 OR1 rnd ACC ACC IDX1 R10 rnd R10 R10 QR1 IDX1 QX0 IDX1 IDX1 IDX1 QX0 Repeat 3 times CoMACMsu CoMACMsu IDX0 QX0 R8 QRO rnd ACC ACC IDXO R8 R8 R8 ORO IDXO QX0 IDXO IDX0 IDX0 QX0 Repeat MRW times CoMACMRsu CoMACMRsu IDX1 QX1 R7 QRO rnd ACC IDX1 R7 ACC rnd R7 lt R7 ORO IDX1 QX1 IDX1 IDX1 IDX1 QX1 150 172 ky ST10 FAMILY PROGRAMMING MANUAL CoMAX Maximum Group Compare Instructions Syntax CoMAXopl op2 Operation tmp op2 N opl ACC max ACC tmp Data Typ
109. leared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes NEG Rw 81 nU 2 ky 95 172 ST10 FAMILY PROGRAMMING MANUAL NEGB Integer Two s Complement Syntax NEGB opl Operation op1 lt 0 op1 Data Types BYTE Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in opi Flags E Z V C N S E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes NEGB Rb Al nO 2 96 172 ky ST10 FAMILY PROGRAMMING MANUAL NOP No Operation Syntax NOP Operation No Operation Description This instruction causes a null operation to be performed A null operation causes no change in the status of the flags Flags E Z V C N E Not affected Z Not affected V Not
110. lel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table Addressing Mode Overwritten Address IDX no change IDX IDX 2 IDX QX ky 145 172 ST10 FAMILY PROGRAMMING MANUAL MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACMu IDX Rw G Yes 93 Xm 18 rrrr rqqq 4 CoMACMu IDX Rw4G Yes 93 Xm 28 rrrr rqqq 4 CoMACMu IDX O Rw rnd Yes 93 Xm 19 rrrr rqqq 4 CoMACMRu IDX Rw4G Yes 93 Xm 38 rrrr rqqq 4 CoMACMRu IDX O Rw rnd Yes 93 Xm 39 rrrr rqqq 4 Examples CoMACMu IDX1 QX0 R10 QR1 rnd ACC ACC IDX1 R10 rnd R10 R10 QR1 7 IDX1 QXO IDX1 IDX1 IDX1 QXO Repeat 3 times CoMACMu CoMACMu IDXO QX0 R8 ORO ACC ACC IDXO R8 R8 R8 QRO
111. m control or branch instructions CAUTION When using nested ATOMIC and EXTended instructions There is ONE counter to control the length of this sort of sequence i e issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with value of the new instruction N6 N5 N8 N7 High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte 1st word Internal Organization MSB 4 Bits in ascending order LSB 38 172 ky ST10 FAMILY PROGRAMMING MANUAL 2 8 Instruction descriptions This section contains a detailed description of each instruction listed in alphabetical order ADD Integer Addition Syntax ADD opl op2 Operation op1 opl op2 Data Types WORD Description Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared other wise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic For
112. main to complete the shift or rotate operation Temporary variable for an intermediate result Constant values due to the data format of the specified operation Carry flag in the PSW register 34 172 ky 2 6 4 Data types Specifies the particular data type according to the instruction Basically the following data types are used BIT BYTE WORD DOUBLEWORD Except for those instructions which extend byte data to word data all instructions have only one particular data type Note that the data types mentioned here do not take into account accesses to indirect address pointers or to the system stack which are always performed with word data Moreover no data type is specified for System Control Instructions and ST10 FAMILY PROGRAMMING MANUAL for those of the branch instructions which do not access any explicitly addressed data 2 6 5 Description Describes the operation of the instruction 2 6 6 Condition code The following table summarizes the 16 possible condition codes that can be used within Call and Branch instructions and shows the mnemonic abbreviations the test executed for a specific con dition and the 4 bit condition code number Table 24 Condition codes equal Not equal AND not end of th table Condition Code Mnemonic cc NIN II II Dae _ O O Zl Zl l lt II II II II lI II ol lol lol l E er a ee sop oo s NIN II II ag P cc UGT cc SLT cc SLE cc SGE
113. mat Bytes ADD Rwy Rwy 00 nm 2 ADD Rwa Rw 08 n 10ii 2 ADD Rwa Rw 08 n 11lii 2 ADD Rwy data3 08 n 0 2 ADD reg f dataig 06 RR 4 ADD reg mem 02 RR MM MM 4 ADD mem reg 04 RR MM MM 4 ky 39 172 ST10 FAMILY PROGRAMMING MANUAL ADDB Integer Addition Syntax ADDB opl op2 Operation op1 lt opl op2 Data Types BYTE Description Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most significant bit of the specified data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ADDB Rba Rb 01 nm 2 ADDB Rba Rwi 09 n 10ii 2 ADDB Rb Rwi 09 n 1lii 2 ADDB Rb data 09 n 0 2 ADDB reg datais 07 RR 4 ADDB reg mem 03 RR MM MM 4 ADDB mem reg 05 RR MM MM 4 40 172 ky ST10 FAMILY PROGRAMMING MANUAL ADDC Integer Addition with Carry Syntax ADDC opl op2 Operation 0p1 lt opl op2 C Data Types WO
114. metic Overflow occurred during operation Result equals zero Result does not equal zero m II for byte data E 0 description The flag is not affected by the operation The flag is cleared by the operation NOR AND XOR N lN l l OOI 2 2 II II II II lI II II II T Source operand represents the lowest negative number either 8000h for word data or 80h Source operand does not represent the lowest negative number for the specified data type The flag is set according to non standard rules Individual instruction pages or the ALU status flags The flag contains the logical NORing of the two specified bit operands The flag contains the logical ANDing of the two specified bit operands The flag contains the logical ORing of the two specified bit operands The flag contains the logical XORing of the two specified bit operands The flag contains the original value of the specified bit operand The flag contains the complemented value of the specified bit operand 31 36 172 ST10 FAMILY PROGRAMMING MANUAL 2 6 8 Addressing modes Mnemonic gives an example of which operands Specifies available combinations of addressing the instruction will accept modes The selected addressing mode combina tion is generally specified by the opcode of the Format specifies the format of the instruction as corresponding instruction used in the assembler listing Figure 3 shows However there are some arithmetic
115. nd multi plexed bus or an 8 bit demultiplexed and multiplexed bus These state time figures do not take into account possible wait states on external busses or possible additional state times induced by operand fetches The following notes apply to this summary Data addressing modes Rw Word GPR RO R1 R15 Rb Byte GPR RLO RHO RL7 RH7 reg SFR or GPR in case of a byte operation on an SFR only the low byte can be accessed via reg mem Direct word or byte memory location Indirect word or byte memory location Any word GPR can be used as indirect address pointer except for the arithmetic logical and compare instructions where only RO to R3 are allowed bitaddr Direct bit in the bit addressable memory area bitoff Direct word in the bit addressable mem ory area data Immediate constant the number of signif icant bits that can be user specified is given by the appendix x maskg Immediate 8 bit mask used for bit field modifications Multiply and divide operations The MDL and MDH registers are implicit source and or destination operands of the multiply and divide instructions Branch target addressing modes caddr Direct 16 bit jump target address Updates the Instruction Pointer seg Direct 8 bit segment address Updates the Code Segment Pointer rel Signed 8 bit jump target word offset address relative to the Instruction Pointer of the following instruction
116. ned double word instruction e g at location 12FEh Ini2 JMPR cc UC label provided that a cache jump is taken Tiada 2 States Ty 4 States If necessary these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses xxxOh xxx4h xxx8h xxxCh Testing Branch Conditions Tada 0 or 1 States NO extra time is usually required for a conditional branch instructions to decide whether a branch condi tion is met or not However an additional state time is required if the preceding instruction writes to the PSW register as shown in the following example I n BSET USRO implicit modification of PSW flags lui JMPR cc 2 label test condition flag in PSW Traqgqg 1 State In this case the extra state time can be intercepted by putting another suitable instruction before the con ditional branch instruction 12 172 ky ST10 FAMILY PROGRAMMING MANUAL 2 3 Instruction set summary The following table lists the instruction mnemonic by hex code with operand Table 7 Instruction mnemonic by hex code with operand rerep mg Wan 029 AOW SAON AOW IAOW Yelep my uqavo oau AOW aAOW Tod Zeyep e lexa Y LX3 OINOLY AON09 WAI o3u 53409 le my Z8AON 3uo1s09 zadWo 93809 my us 3YOLSCO WAI my Lado zddWO e wu loxa XXX00 emu my dO XXX00 WAI My WAW 934 8qNV 9UOX nwan 93
117. nificant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes AND Rwy Rwy 60 nm 2 AND Rwa Rw 68 n 10ii 2 AND Rwa Rw 68 n 11lii 2 AND Rwy data 68 n 0 2 AND reg fdataig 66 RR did 4 AND reg mem 62 RR MM MM 4 AND mem reg 64 RR MM MM 4 ky 43 172 ST10 FAMILY PROGRAMMING MANUAL ANDB Logical AND Syntax ANDB opl op2 Operation op1 opl op2 Data Types BYTE Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand spec ified by op1 The result is then stored in op1 Flags E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ANDB Rb ROn 61 nm 2 ANDB Rba Rw 69 n 10ii 2 ANDB Rba Rw 69 n 11lii 2 ANDB Rb data3 69 n 0 2 ANDB reg f dataig 67 RR 4 ANDB reg mem 63 RR MM MM 4 ANDB mem reg 65 RR MM MM 4 44 172 ky ST10 FAMILY PROGRAMMING MANUAL ASHR Arithmetic Shift Right Syntax ASHR opl op2 Operation count op2 V 0 C 0 DO WHILE count 0 V C v V C oplp Opla opi sr n20 14 count lt coun
118. ntains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BAND bitaddr bitaddro 6A QQ ZZ qz 4 ky 47 172 ST10 FAMILY PROGRAMMING MANUAL BCLR Bit Clear Syntax BCLR opl Operation op1 lt 0 Data Types BIT Description Clears the bit specified by op1 This instruction is primarily used for peripheral and system control Flags E Z V C B 0 E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes BCLR bitaddro q qE QQ 2 48 172 ST10 FAMILY PROGRAMMING MANUAL BCMP Bit to Bit Compare Syntax BCMP opl op2 Operation 0p1 lt gt op2 Data Types BIT Description Performs a single bit comparison of the source bit specified by operand op1 to the source bit specified by operand op2 No result is written by this instruction Only the flags are updated Flags E Z V C N NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Addressing Modes Mnemonic Format Bytes BCMP bitaddr bitaddro 2A QQ ZZ qz 4 ky 49 172 ST10 FAMILY PROGRAMMING MANUAL BFLDH Bit Field High
119. number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTS instruction sequence the value of op1 deter mines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indi rect address itself represents the 16 bit segment offset address bits A15 A0 The value of op2 defines the length of the effected instruction sequence Note The EXTS instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EXTS Rwm data DC OO m 2 EXTS seg data D7 0044 0 ss 00 4 78 172 ky ST10 FAMILY PROGRAMMING MANUAL EXTSR Begin EXTended Segment amp Register Sequence Syntax EXTSR opl op2 Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data_Segment opl AND SFR_range Extended DO WHILE count 0 AND Class B trap condition TRUE ext Instruction count count 1 END WHILE count 0 Data Page DPPx AND SFR range Standard Enable interrupts and traps Description Overrides the standard DPP addressing s
120. oMACR CoMACRu CoMACRus CoMACRsu CoMACR rnd CoMACRu rnd CoMACRus rnd CoMACRsu rnd Rwr Rwm IDX amp Rwm Rw Rw Rwy Rwm IDX amp Rw Rw Rwm RWm IDX amp Rwy 2 CoNEG CoNEG rnd CoRND CoSTORE Rw CoReg Rw CoReg Oxe Pwe 124 172 CoMACM CoMACMu CoMACMus CoMACMsu CoMACM CoMACMu CoMACMus CoMACMsu CoMAOM rnd CoMACMu rnd CoMACMus rnd CoMACMsu rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR rnd CoMACMRu rnd CoMACMRus rnd CoMACMRsu rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOAD CoLOAD2 CoLOAD2 CoCMP CoSHL CoSHR CoASHR a rnd IDX 8 Rw 9 Rwy Rwm IDX amp Rw Rw RWm Rwy Rwm IDX Rw 2 Rw RWm Rwy Rwm IDX Rw Rw RW The following table gives the MAC Function Code of each instruction This Function Code is the third byte of the new instruction and is used by the Table 30 MAC instruction function code hexa Fuion cede CO 40 C8 88 48 C1 01 81 41 10 50 EO 20 AO D1 11 91 51 FO 30 70 F1 31 B1 71 5A 32 72 B2 1A CA CoMUL CoMULu CoMULus CoMULsu CoMUL CoMULu CoMULus CoMULsu CoMUL rnd CoMULu rnd CoMULus rnd CoMULsu rnd CoMAC CoMACu CoMACus CoMACsu CoMAC CoMACu CoMACus CoMACsu CoMAC rnd CoMACu rnd CoMACus rnd CoMACsu rnd CoMACR CoMACRu CoMACRus CoMACRsu
121. of bytes Specifies the size of an instruc tion in bytes All ST10 instructions are either 2 or 4 bytes Instructions are classified as either single word or double word instructions see Figure 3 2 7 ATOMIC and EXTended instructions ATOMIC EXTR EXTP EXTS EXTPR EXTSR instructions disable standard and PEC interrupts and class A traps during a sequence of the follow ing 1 4 instructions The length of the sequence is determined by an operand op1 or op2 depend ing on the instruction The EXTended instructions also change the addressing mechanism during this sequence see detailed instruction descrip tion The ATOMIC and EXTended instructions become active immediately so no additional NOPs are required All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can Figure 3 Instruction format representation Representation in the Assembler Listing N4 N3 be used with the ATOMIC and EXTended instruc tions CAUTION When a Class B trap interrupts an ATOMIC or EXTended sequence this sequence is terminated the interrupt lock is removed and the standard condition is restored before the trap rou tine is executed The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under stan dard conditions CAUTION When using the ATOMIC and EXTended instructions with other syste
122. ointer by 2 AND mem Dive AND rede vos aaa winara oP afeafe afe 2 i indi ith di 2 2 2 2 4 4 16 bit Mux me 4 4 ANDB Rb Rb Bitwise AND direct byte GPR with direct GPR ANDB Rb Rw Bitwise AND indirect byte memory with direct GPR 2 18 172 yy ST10 FAMILY PROGRAMMING MANUAL Table 10 Logical instructions continued LE v Bitwise AND indirect byte memory with direct GPR and post increment source pointer by 1 Bitwise AND immediate byte data with direct GPR Bitwise AND immediate byte data with direct register Bitwise AND direct byte memory with direct register Bitwise AND direct byte register with direct memory Bitwise OR direct word GPR with direct GPR Bitwise OR indirect word memory with direct GPR OR Rw Rw Bitwise OR indirect word memory with direct GPR and post increment source pointer by 2 OR Rw data3 Bitwise OR immediate word data with direct GPR Bitwise OR immediate word data with direct register Bitwise OR direct word memory with direct register Bitwise OR direct word register with direct memory Bitwise OR direct byte GPR with direct GPR Bitwise OR indirect byte memory with direct GPR Bitwise OR indirect byte memory with direct GPR and post increment source pointer by 1 Bitwise OR immediate byte data with direct GPR Bitwise OR immediate byte data with direct register Bitwise OR direct byte memory with direct register Bitwise OR direct byte register with direct memory XOR R
123. ondition code 5 m davies D S SS RU icto voie dac HIRED O 35 2 6 7 aL mm ws a 36 2 6 8 Addressing fnodes coe ebat ie kg tbeecm ee gor trece tx gei arte E 37 2 7 ATOMIC AND EXTENDED INSTRUCTIONS 1 00 sse eee eee 38 2 8 INSTRUCTION DESCRIPTIONS annei an gae R Keav dL wawas q quas Ten vaok aysasqa eah 39 3 MAC INSTRUCTION SET UU czcedeced sededecessessasencuesssebcccenecesd 123 3 1 ADDRESSING MODES L uuu s ete tie Bet re EEEE S RAA 123 3 2 MAC INSTRUCTION EXECUTION TIME sese eee 124 3 3 MAC INSTRUCTION SET SUMMARY sse eee 124 3 4 MAC INSTRUCTION CONVENTIONS 0 0 sees eee 126 3 4 1 OPOTANS oi 126 3 4 2 ieri 126 3 4 8 Abbreviations T PX aag 126 3 4 4 Data addressing MOS sic sc seh 3 ee eR ere eoe e e KE 126 3 4 5 Instruction format l incendere rie nice d uod ee aee Po sec c 127 3 4 6 Flag States usun Wicks fee ceed ec S En Dee e fee te w fete od e Deer edd 127 3 4 7 Repeated instruction syntax u u u uuu nnns 127 3 4 8 Sess uy ya ua ay aqya Saa ia A 127 3 5 MAC INSTRUCTION DESCRIPTIONS e eee eee 127 4 REVISION HIS TOR Vaine lai retener tre itte a Saat E O E A 170 ky 1 172 ST10 FAMILY PROGRAMMING MANUAL 2 172 SZA ST10 ST10 FAMILY PROGRAMMING MANUAL 1 INTRODUCTION This programming manual details the instruction set for the ST10 family of products The manual is a
124. ory to direct register x 20 172 ST10 FAMILY PROGRAMMING MANUAL Table 12 Compare and loop instructions continued CMPD1 Rw puppe PEE S D i immediate word data to direct GPR and poo c GPR PEE S D i 1 CMPD1 Rw datajg Compare immediate word data to direct GPR and decrement GPR by 1 CMPD1 Rw mem Compare direct word memory to direct GPR and 2 4 12 4 decrement GPR by 1 CMPD2 Rw data Compare immediate word data to direct GPR and 2 2 3 4 2 decrement GPR by 2 CMPD2 Rw data g Compare immediate word data to direct GPR and 2 4 12 4 decrement GPR by 2 CMPD2 Rw mem Compare direct word memory to direct GPR and 2 4 12 4 decrement GPR by 2 CMPI1 Rw data Compare immediate word data to direct GPR and 2 2 31 4 2 increment GPR by 1 CMPI1 Rw datajg Compare immediate word data to direct GPR and 2 4 12 4 increment GPR by 1 CMPI1 Rw mem Compare direct word memory to direct GPR and 2 4 12 4 increment GPR by 1 CMPI2 Rw data4 Compare immediate word data to direct GPR and 2 21214 2 increment GPR by 2 CMPI2 Rw data4g Compare immediate word data to direct GPR and 2 4 12 4 increment GPR by 2 CMPI2 Rw mem Compare direct word memory to direct GPR and 2 4 12 increment GPR by 2 Table 13 Prioritize instructions gga 16 bit Mux PRIOR Rw Rw Determine number of shift cycles to normalize direct word 3 GPR and store result in direct word GPR ky 21 172 ST10 FAMILY PROGRAMMING MANUAL Table 14 Shift
125. otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes SUBB Rar Rbi 21 nm 2 SUBB Rba Rwi 29 n 10ii 2 SUBB Rba Rwi 29 n llii 2 SUBB Rb data 29 n 0 2 SUBB reg datay 27 RR 4 SUBB reg mem 23 RR MM MM 4 SUBB mem reg 25 RR MM MM 4 ky 117 172 ST10 FAMILY PROGRAMMING MANUAL SUBC Integer Subtraction with Carry Syntax SUBC opl op2 Operation op1 opl op2 C Data Types WORD Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic Flags E Z V N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes SUBC Rwy Rwy 30 nm 2 SUBC Rwy Rw 38 n 10ii 2 SUBC Rwy Rw
126. overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes DIVU Rw 5B nn 2 ky 73 172 ST10 FAMILY PROGRAMMING MANUAL EINIT End of Initialization Syntax EINIT Operation End of Initialization Description This instruction is used to signal the end of the initialization portion of a program After a reset the reset output pin RSTOUT is pulled low It remains low until the EINIT instruction has been executed at which time it goes high This enables the program to signal the external circuitry that it has successfully initial ized the microcontroller After the EINIT instruction has been executed execution of the Disable Watch dog Timer instruction DISWDT has no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EINIT B5 4A B5 B5 4 74 172 ky ST10 FAMILY PROGRAMMING MANUAL EXTP Begin EXTended Page Sequence Syntax EXTP opl op2 Operation count op2 1 lt S op2 lt 4 Disable interrupts and Class A traps Data Page opl DO WHILE count 0 AND Class B trap condition TRUE Ne
127. p Shift Instructions Syntax CoSHR opl Operation count opl C 0 DO WHILE count 0 ACC ACC 41 n 0 38 ACC39 0 count count 1 END WHILE Data Types ACCUMULATOR Result 40 bit signed value Description Shifts the ACC register right by as many times as specified by the operand op1 The most significant bits of the result are filled with zeros accordingly Only shift values contained between 0 and 8 are allowed opi can be either a 5 bit unsigned immediate data or the least significant 5 bits considered as unsigned data of any register directly or indirectly addressed operand The MS bit of the MCW register does not affect the result This instruction is repeatable when op 1 is not an immediate operand MAC Flags N Z C SV E SL P P 0 I B N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoSHR Rwy Yes A3 nn 9A rrrr r000 4 CoSHR fdatas No A3 00 92 ssss s000 4 CoSHR Rw Yes 83 mm 9A rrrr rqqq 4 Examples CoSHR 3 ACC ACC gt gt 3 CoSHR R3 ACC ACC gt gt R3 49 CoSHR R10 QRO ACC ACC gt gt R10 49 R10 R10 QRO 166 172 er ST10 FAMILY PROGRAMMING MANUAL CoSTORE Store a MAC Unit
128. p to two parallel memory reads oo MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise 136 172 yy ST10 FAMILY PROGRAMMING MANUAL Addressing Modes Mnemonic Rep Format Bytes CoMACu Rwy Rwy No A3 nm 10 00 4 CoMACu Rwy Rwy No A3 nm 20 00 4 CoMACu Rwy RwQ rnd No A3 nm 11 00 4 CoMACRu Rw Rwy No A3 nm 30 00 4 CoMACRu Rwy RwQ rnd No A3 nm 31 00 4 CoMACu IDX Rw Yes 93 Xm 10 rrrr rqqq 4 CoMACu IDX Rw Yes 93 Xm 20 rrrr rqqq 4 CoMACu IDX Rw rnd Yes 93 Xm 11 rrrr rqqq 4 CoMACRu IDX Rw Yes 93 Xm 30 rrrr rqqq 4 CoMACRu IDX Rw rnd Yes 93 Xm 31 rrrr rqqq 4 CoMACu Rwy Rw Yes 83 nm 10 rrrr rqqq 4 CoMACu Rw Rw Yes 83 nm 20 rrrr rqqgq 4 CoMACu Rwy Rw rnd Yes 83 nm 11 rrrr rqqq 4 CoMACRu Rw Rw Yes 83 nm 30 rrrr rqqq 4 CoMACRu Rw Rw rnd Yes 83 nm 31 rrrr rqqq 4 Examples CoMACu R5 R8 rnd ACC ACC R5 R8 rnd CoMACu R2 R7 ACC ACC R2 R7 CoMACu IDXO QX0 REL ORO ACC ACC IDXO R11 R11 R11 QRO
129. pl op2 Operation tmp op2 N opl ACC min ACC tmp Data Types DOUBLE WORD Result 40 bit signed value Description Compares a signed 40 bit operand against the ACC register content The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended If the contents of the ACC register is greater than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC register remains unchanged The MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes MAC Flags N Z C SV E SL z x 0 x N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC register is changed Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMIN Rwy Rwy No A3 nm 7A 00 4 CoMIN IDX Rw G Yes 93 Xm 7A rrrr rqqq 4 CoMIN Rwy Rw Yes 83 nm 7A rrrr rqqq 4 Examples CoMIN IDX1 QX0 R11 OR1 ACC lt min ACC R11 N IDX1 R11 R11 QR1 IDX1 IDX1 QXO CoMIN R1 R10 ACC min ACC R10 N R1 Repeat 23 times CoMIN CoMIN R5 R6 QRO ACC min ACC R6 N R5 R6 R6 QRO 152 172 er ST10 FAMILY PRO
130. pore Spain Sweden Switzerland United Kingdom United States of America www st com 31 172 172 DocID5869 Rev 5
131. presents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMPD2 Rwa data BO n 2 CMPD2 Rwy dataig B6 Fn 4 CMPD2 Rw mem B2 Fn MM MM 4 n7 64 172 ky ST10 FAMILY PROGRAMMING MANUAL CMP T 1 Integer Compare amp Increment by 1 Syntax CMP11 opl op2 Operation op1 lt gt op2 op1 lt opl 1 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary sub traction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has com pleted the operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags E Z V N B B x S x E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared other
132. pts and traps Description Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active so that no additional NOPs are required Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multi ple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC instruction Note The ATOMIC instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes ATOMIC fdata D1 OO 0 2 46 172 ky BAND Syntax Operation Data Types Description ST10 FAMILY PROGRAMMING MANUAL Bit Logical AND BAND opl op2 0p1 lt opl op2 BIT Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 Flags E Z V C N NOR OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Co
133. qq 4 CoLOAD2 IDX Rw 93 Xm 62 0 0qqq 4 CoLOAD2 IDX Rw 93 Xm 6A 0 0qqq 4 CoLOAD Rwy Rw 83 nm 22 0 0qqq 4 CoLOAD Rwy Rw 83 nm 2A 0 0qqq 4 CoLOAD2 Rwy Rw 83 nm 62 0 0qqq 4 CoLOAD2 Rwy Rw 83 nm 6A 0 0qqq 4 ky 133 172 ST10 FAMILY PROGRAMMING MANUAL CoMAC R Multiply Accumulate amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMAC opl op2 Operation IF MP 1 THEN tmp opl op2 lt lt 1 ACC ACC tmp ELSE tmp opl op2 ACC ACC tmp END IF Syntax CoMAC opl op2 rnd Operation IF MP 1 THEN tmp opl op2 1 ACC ACC tmp 00 0000 8000 ELSE tmp opl op2 ACC ACC tmp 00 0000 8000 END IF MAL O Syntax CoMAC opl op2 Operation IF MP 1 THEN tmp opl op2 1 ACC ACC tmp ELSE tmp opl op2 ACC ACC tmp END IF Syntax CoMACR opl op2 Operation IF MP 1 THEN tmp opl op2 1 ACC tmp ACC ELSE tmp opl op2 ACC tmp ACC END IF Syntax CoMACRopl op2 rnd Operation IF MP 1 THEN tmp opl op2 1 ACC tmp ACC 00 0000 8000 ELSE tmp opl op2 ACC tmp ACC 00 0000 8000 END IF MAL O Data
134. r Idle Mode aA PWRDN Enter Power Down Mode supposes NMI pin is low A SRST Software Reset 2 Service Watchdog Timer Note 1 The EXT instructions override the standard DPP addressing sheme A Ses pe Ese o GRIP GS SES a eles i B A Table 20 Miscellaneous instructions Null operation Null operation 25 172 ST10 FAMILY PROGRAMMING MANUAL 2 5 Instruction set ordered by opcodes The following pages list the instruction set ordered by their hexadecimal opcodes This is used to identify specific instructions when reading execut able code i e during the debugging phase Notes for Opcode Lists 1 Some instructions are encoded by means of additional bits in the operand field of the instruction xOh x7h Rw datagor Rb datag x8h xBh Rw Rw or Rb Rw xCh xFh Rw Rw or Rb Rwt For these instructions only the lowest four GPRs RO to R3 can be used as indirect address pointers 2 Some instructions are encoded by means of additional bits in the operand field of the instruc tion EXTS or EXTP ATOMIC 00xx XXXX 01xx XXXX Table 21 Instruction set ordered by Hex code Hex code ADD ADD ADD ADD ADD MUL ROL 26 172 O00xx xxxx EXTS or ATOMIC 10xx xxxx EXTSR or EXTR llxx xxxx EXTPR Notes on the JMPR instructions The condition code to be tested for the JMPR instructions is specified by the opcode Two
135. respectively This instruction is not repeatable MAC Flags N Z C SV E SL N Set if the m s b of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoNEG No A3 00 32 00 4 CoNEG rnd No A3 00 72 00 4 Examples CoNEG ACC lt 0 ACC ACC 0 ACC rnd SL a a cones x we ooreen 3 5 3 91 EH rreoocom 5 ABB 162 172 ST10 FAMILY PROGRAMMING MANUAL CoNOP No Operation Group 40 bit Arithmetic Instructions Syntax CoNOP Operation No Operation Description Modifies the address pointers without changing the internal MAC Unit registers MAC Flags N Z C SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoNOP Rw 2 Yes 93 1m 5A rrrr rqqq 4 CoNOP IDX amp Rw7 8 Yes 93 Xm 5A rrrr rqqq 4 Example CoNOP IDX0 QX1 R11 QR1 R11 R11 QR1 IDXO lt IDXO QX1 ky 163 172 ST10 FAMILY PROGRAMMING MANUAL CoRND Round Accumulator Group Shift Instructions Syntax
136. rranged in two sections Section 1 details the standard instruction set and includes all of the basic instructions Section 2 details the extension to the instruction set provided by the MAC The MAC instructions are only available to devices containing the MAC refer to the datasheet for device specific information In the standard instruction set addressing modes instruction execution times minimum state times and the causes of additional state times are defined Cross reference tables of instruction mnemonics hexadecimal opcode address modes and number of bytes are provided for the optimization of instruction sequences Instruction set tables ordered by functional group can be used to identify the best instruction for a given application Instruction set tables ordered by hexadecimal opcode can be used to identify September 2013 specific instructions when reading executable code i e during the de bugging phase Finally each instruction is described individually on a page of standard format using the conventions defined in this manual For ease of use the instructions are listed alphabetically The MAC instruction set is divided into its 5 functional groups Multiply and Multiply Accumulate 32 Bit Arithmetic Shift Compare and Transfer Instructions Two new addressing modes supply the MAC with up to 2 new operands per instruction Cross reference tables of MAC instruction mnemonics by address mode and MAC instruc
137. rwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes Rw OB nm 2 n m MUL Rw ky 93 172 ST10 FAMILY PROGRAMMING MANUAL MULU Unsigned Multiplication Syntax MULU opl op2 Operation MD opl op2 Data Types WORD Description Performs a 16 bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register Flags E Z C N S 0 E Always cleared Z Set if the result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes MULU Rw Rw 1B nm 2 n m 94 172 ky ST10 FAMILY PROGRAMMING MANUAL NEG Integer Two s Complement Syntax NEG opl Operation op1 lt 0 opl Data Types WORD Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in opi Flags E Z V N S E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero C
138. s The time Tin taken to process a single instruction consists of a minimum number Timin plus an additional number Tiada of instruction state times and or ALE Cycle Times Tin Timin Madd 9 172 ST10 FAMILY PROGRAMMING MANUAL 2 2 2 Minimum state times The table below shows the minimum number of state times required to process an instruction fetched from the internal ROM Timin ROM This table can also be used to calculate the mini mum number of state times for instructions fetched from the internal RAM Timin RAM or ALE Cycle Times for instructions fetched from the external memory Timin ext Most of the 16 bit microcontroller instructions except some branch multiplication division and a special move instructions require a minimum of two state times For internal ROM program execu tion execution time has no dependence on instruction length except for some special branch situations To evaluate the execution time for the injected tar get instruction of a cache jump instruction it can be considered as if it was executed from the inter nal ROM regardless of which memory area the rest of the current program is really fetched from For some of the branch instructions the table below represents both the standard number of state times i e the corresponding branch is taken and an additional Timin value in parenthe ses which refers to the case where either the branch condition is not met or a cache
139. s eight bits in the instruction format Short reg addresses from 00h to EFh always specify E SFRs In this case the factor A equals 2 and the base address is 00 F000h for the standard SFR area or 00 FEOOh for the extended ESFR area reg accesses to the ESFR area require a preceding EXT R instruction to switch the base address Depending on the opcode of an instruc tion either the total word for word operations or Table 1 Short addressing mode summary Physical Address E b CP CP b Rb 0 15 GPRS 2 reg 2 reg 2 reg OFh 1 reg 0Fh OOFDOOh 2 bitoff bitoff 00 FF00h 2 bitoff FFh bitoff CP 2 bitoff 0Fh bitoff Word offset as with bitoff bitoff Immediate bit position bitpos 4 172 Short Address Range 00h 80h F0h 00h FFh 0 15 the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR cannot be accessed by the reg address ing mode Short reg addresses from F0h to FFh always specify GPRs In this case only the lower four bits of reg are significant for physical address generation therefore it can be regarded as identical to the address generation described for the Rb and Rw addressing modes bitoff Specifies direct access to any word in the bit addressable memory space bitoff requires eight bits in the instruction format Depending on the specified bitoff range different base a
140. ster left by the number of times specified by the operand op1 The least significant bits of the result are filled with zeros Only shift values from 0 to 8 inclusive are allowed op1 can be either a 5 bit unsigned immediate data or the least significant 5 bits considered as unsigned data of any reg ister directly or indirectly addressed operand When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000p respectively This instruction is repeatable when op1 is not an immediate operand MAC Flags N Z C SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Carry flag is set according to the last most significant bit shifted out of ACC SV Set if the last shifted out bit is different from N E Set if the MAE is used Cleared otherwise SL Set if the content of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoSHL Rwy Yes A3 nn 8A rrrr r000 4 CoSHL fdatas No A3 00 82 ssss s000 4 CoSHL Rw Yes 83 mm 8A rrrr rqqq 4 Examples CoSHL 3 ACC ACC lt lt 3 CoSHL R3 ACC ACC lt lt R3 49 CoSHL R10 QRO ACC ACC R10 49 ORO ky 165 172 ST10 FAMILY PROGRAMMING MANUAL CoSHR Accumulator Logical Shift Right Grou
141. struction CoSTORE transfers a value from a MAC register to any location in memory This instruction uses a specific addressing mode for the MAC registers called CoReg The follow ing table gives the 5 bit addresses of the MAC registers corresponding to this CoReg addressing mode Unused addresses are reserved for future revisions see Table 28 Table 27 Pointer post modification for Rw and IDXi amp addressing modes i ID IRw stands for Note 1 IDX can only contain even values Therefore bit 0 always equals zero Table 28 MAC register addresses for CoReg MAC Unit Control Word 00101 u uan wow a MAC Unit Repeat Word 00110 123 172 ST10 FAMILY PROGRAMMING MANUAL 3 2 MAC Instruction Execution Time The instruction execution time for MAG instructions is calculated in the same way as that of the standard instruction set To calculate the 3 3 MAC instruction set summary Table 29 execution time for MAC instructions refer to Instruction execution times in Table 6 considering MAC instructions to be 4 byte instructions with a minimum state time number of 2 MAC instruction mnemonic by addressing mode and repeatability CoMUL CoMULu CoMULus CoMULsu CoMUL CoMULu CoMULus CoMULsu CoMUL rnd CoMULu rnd CoMULus rnd CoMULsu rnd CoMAC CoMACu CoMACus CoMACsu CoMAC CoMACu CoMACus CoMACsu CoMAC rnd CoMACu rnd CoMACus rnd CoMACsu rnd C
142. su opl op2 rnd Operation tmp lt op1 op2 ACC tmp ACC 00 0000 80004 MAL lt 0 IDX IDX Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended it is then optionally negated prior being added subtracted to from the 40 bit ACC regis ter content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automat ically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and performs two parallel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table Addressing Mode Overwritten Address IDX QX no change IDX 2 IDX 2 IDX QX ST10 FAMILY PROGRAMMING MANUAL MAC F
143. symbols summarized at the end of each single instruction description 2 6 3 Operation The following symbols are used to represent data movement arithmetic or logical operators see Table 22 Missing or existing parentheses signifies that the operand specifies an immediate constant value an address or a pointer to an address as follows opX Specifies the immediate constant value of opX opX Specifies the contents of opX opX4 Specifies the contents of bit n of opX opX Specifies the contents of the contents of opX i e opX is used as pointer to the actual operandi D operator op opx lt opy is MOVED into opX opx opy p is ADDED to opY opx opy p is SUBTRACTED from opX opx opy p is MULTIPLIED by opY Diadic operations opx opy opx v opy opx opy op is logically EXCLUSIVELY ORed with opY opx lt gt opy Monadic operations opx is COMPARED against opY operator opX logically COMPLEMENTED opx mod opy op is divided MODULO opY The following abbreviations are used to describe operands Table 23 Operand abbreviations Abbreviation CP Description Context Pointer register Code Segment Pointer register Instruction Pointer Overflow flag in the PSW register Segmentation Disable bit in the SYSCON register Temporary variable for an intermediate storage of the number of shift or rotate cycles which re
144. t 1 END WHILE Data Types WORD Description Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2 To preserve the sign of the original operand op1 the most significant bits of the result are filled with zeros if the original most significant bit was a 0 or with ones if the original most significant bit was a 1 The Overflow flag is used as a Rounding flag The least significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Z V N S S E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared for a shift count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes ASHR Rwy RWm AC nm 2 ASHR Rwa data BC n 2 ky 45 172 ST10 FAMILY PROGRAMMING MANUAL ATOMIC Begin ATOMIC Sequence Syntax ATOMIC opl Operation count opl 1 lt opl lt 4 Disable interrupts and Class A traps DO WHILE count 0 AND Class_B_trap_condition TRUE ext Instruction count count 1 END WHILE count 0 Enable interru
145. t memory MOVB Rw Rw Move indirect byte memory to indirect memory and post increment destination pointer by 1 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment source pointer by 1 MOVB Rb Rw datais Move indirect byte memory by base plus constant to direct GPR MOVB Rw datais Rb Move direct byte GPR to indirect memory by base plus constant Move direct word register to direct memory A N MOVB Rw mem Move direct byte memory to indirect memory MOVB mem Rw Move indirect byte memory to direct memory MOVB reg mem Move direct byte memory to direct register MOVB mem reg Move direct byte register to direct memory MOVBS Rw Rb Move direct byte GPR with sign extension to direct word GPR MOVBS reg mem Move direct byte memory with sign extension to direct word register MOVBS mem reg Move direct byte register with sign extension to direct word memory MOVBZ Rw Rb Move direct byte GPR with zero extension to direct word GPR MOVBZ reg mem Move direct byte memory with zero extension to direct word register N ae E a f ofiAa i E E E a llB jajla zu zx N N N N N N N A N N PM MI KM N N Aa n MOVBZ mem reg Move direct byte register with zero extension to direct word memory ky 23 172 ST10 FAMILY PROGRAMMING MANUAL Table 16 JumpandCalllnstructions continued CALLA cc caddr Call absolute subroutine if condition is met 2 10 8 6 4 8 6 CALLI cc Rw
146. the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CPLB Rb Bl n0 2 68 172 ky ST10 FAMILY PROGRAMMING MANUAL DISWDT Disable Watchdog Timer Syntax DISWDT Operation Disable the watchdog timer Description This instruction disables the watchdog timer The watchdog timer is enabled by a reset The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function Following a reset this instruction can be executed at any time until either a Service Watchdog Timer instruction SRVWDT or an End of Initialization instruction EINIT are executed Once one of these instructions has been executed the DISWDT instruction will have no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes DISWDT A5 5A A5 A5 4 ky 69 172 ST10 FAMILY PROGRAMMING MANUAL DIV 16 by 16 Signed Division Syntax DIV opi Operation MDL MDL opl MDH MDL mod opl Data Types WORD Description Performs a signed 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high ord
147. tion mnemonic by functional code can be used for quick reference As for the standard instruction set each instruction has been described individually in a standard format according to defined conventions For convenience the instructions are described in alphabetical order DocID5869 Rev 5 3 172 ST10 FAMILY PROGRAMMING MANUAL 2 STANDARD INSTRUCTION SET 2 1 Addressing Modes 2 1 1 Short adressing modes The ST10 family of devices use several powerful addressing modes for access to word byte and bit data This section describes short long and indi rect address modes constants and branch target addressing modes Short addressing modes use an implicit base offset address to specify the 24 bit physical address Short addressing modes give access to the GPR SFR or bit addressable memory spacePhysicalAddress BaseAddress A x ShortAddress Note A 1 for byte GPRs A 2 for word GPRs see Table 1 Rw Rb Specifies direct access to any GPR in the cur rently active context register bank Both Rw and Rb require four bits in the instruction format The base address of the current register bank is deter mined by the content of register CP Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a 4 bit byte GPR address relative to the base address CP reg Specifies direct access to any E SFR or GPR in the currently active context register bank reg require
148. tion tmp lt opl op2 ACC ACC tmp IDX 8 lt IDX Syntax CoMACMu opl op2 rnd Operation tmp opl op2 ACC ACC tmp 00 0000 8000 MAL lt U IDX IDX Syntax CoMACMu opl op2 Operation tmp lt opl op2 ACC ACC tmp IDX 89 IDX Syntax CoMACMRu opl op2 Operation tmp lt opl op2 ACC tmp ACC IDX 8 IDXj Syntax CoMACMRu opl op2 rnd Operation tmp lt a opl op2 ACC tmp ACC 00 0000 8000 MAL 0 IDX lt IDX Data Types DOUBLE WORD Result 40 bit signed value Description Multiplies the two signed 16 bit source operands op1 and op2 The unsigned 32 bit product is first zero extended then optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and performs two paral
149. ts and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE ANDIOR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIRE
150. ts are used to define instruction processing times fopul State ACT Tiot CPU operating frequency may vary from 1MHz to 80MH2z One state time is specified by one CPU clock period Therefore one State is used as the basic time unit because it represents the shortest period of time which has to be considered for instruction timing evaluations 1 State l cPuls for fcpy variable 50 ns for fcPuU 20MHz ALE Address Latch Enable Cycle Time specifies the time required to perform one external memory access One ALE Cycle Time consists of either two for demultiplexed external bus modes or three for multiplexed external bus modes state times plus a number of state times which is determined by the number of waitstates programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of the SYSCON BUSCONx registers For demultiplexed external bus modes 1 ACT 2 15 MCTO 1 MTTC States 100 n 900 ns for fGpy 20MHz For multiplexed external bus modes 1 ACT 3 15 MCTC 1 MTTO States 150ns 950ns for fcpuj 20MHz The total time Trot taken to process a particular part of a program can be calculated by the sum of the single instruction processing times Tin of the considered instructions plus an offset value of 6 state times which takes into account the solitary filling of the pipeline Ttot lt u Tia Tin 6 State
151. tware Trap Syntax TRAP opl Operation SP lt SP 2 SP PSW IF SYSCON SGTDIS 0 THEN SP lt a gt SB 3 SP lt CSP CSP 0 END IF SP Ese SB 2 SP c LE IP zero extend op1 4 Description Invokes a trap or interrupt routine based on the specified operand op1 The invoked routine is deter mined by branching to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI return from interrupt instruction is used to resume execution after the trap or interrupt routine has completed The CSP is pushed if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes TRAP trap7 9B t ttto 2 120 172 ky ST10 FAMILY PROGRAMMING MANUAL XOR Logical Exclusive OR Syntax XOR opl op2 Operation 0p1 opl GO op2 Data Types WORD Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 Flags E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negati
152. ve number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes XOR Rwy Rwy 50 nm 2 XOR Rwa Rw 58 n ilO0xi 2 XOR Rwa Rw 58 n l1lii 2 XOR Rwy data 58 n 0 2 XOR reg f dataig 56 RR 4 XOR reg mem 52 RR MM MM 4 XOR mem reg 54 RR MM MM 4 ky 121 172 ST10 FAMILY PROGRAMMING MANUAL XORB Logical Exclusive OR Syntax XORB op1 0p2 Operation 0p1 opl GO op2 Data Types BYTE Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 Flags E Z V C N 0 0 E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes XORB Rb RD 51 nm 2 XORB Rb Rw 59 n 10ii 2 XORB Rba Rw 59 ae l ia 2 XORB Rb data3 59 n 0 2 XORB reg fdataig 57 RR 4 XORB reg mem 53 RR MM MM 4 XORB mem reg 55 RR MM MM 4 122 172 ky 3 MAC INSTRUCTION SET This section describes the instruction set for the MAC
153. w Rw Bitwise XOR direct word GPR with direct GPR XOR Rw Rw Bitwise XOR indirect word memory with direct GPR Bitwise XOR indirect word memory with direct GPR and post increment source pointer by 2 Bitwise XOR immediate word data with direct GPR Bitwise XOR immediate word data with direct register Bitwise XOR direct word memory with direct register Bitwise XOR direct word register with direct memory Bitwise XOR direct byte GPR with direct GPR Bitwise XOR indirect byte memory with direct GPR XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR and post increment source pointer by 1 XORB Rb data3 Bitwise XOR immediate byte data with direct GPR XORB reg data Bitwise XOR immediate byte data with direct register XORB reg mem Bitwise XOR direct byte memory with direct register XORB mem reg Bitwise XOR direct byte register with direct memory 19 172 A El Pis s sss EE ESO E EE sara sp Ea Eo ss a n u ra S ST10 FAMILY PROGRAMMING MANUAL Table 11 Boolean bit map instructions continued Description BAND bitaddr bitaddr bitaddr Clear direct bit AND direct bit with direct bit m rom 16 bit N Mux UJ Oo E Em ES BCMP bitaddr bitaddr Compare direct bit to direct bit BFLDH Bitwise modify masked high byte of bit addressable direct 2 bitoff masks datas word memory with immediate data BFLDL Bitwise modify masked low byte of bit addressable direct bitoff
154. wise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes CMPI1 Rwa data 80 n 2 CMPI1 Rwy datay 86 Fn 4 CMPI1 Rwy mem 82 Fn MM MM 4 ky 65 172 ST10 FAMILY PROGRAMMING MANUAL CMP T 2 Integer Compare amp Increment by 2 Syntax CMP12 opl op2 Operation op1 lt gt op2 op1 lt opl 2 Data Types WORD Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary sub traction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has com pleted the operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range Flags E Z V N B B x S x E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if
155. xt Instruction count lt count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence Note The EXTP instruction must be used carefully see Section 2 7 ATOMIC and EXTended instruc tions on page 38 Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Modes Mnemonic Format Bytes EXTP Rwm data DC O1 m 2 EXTP pag data D7 01 0 pp 0 00pp 4 ky 75 172 ST10 FAMILY PROGRAMMING MANUAL EXTPR Begin EXTended Page amp Register Sequence Syntax EXTPR opl op2 Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data_Page opl AND SFR_range Extended DO WH

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