Home

NetFusion-EXP Libero Project Helper PDF

1. 51 Figure 44 Opening screen of FlashPro IDEA 52 Figure 45 Microsemi FlashPro4 ribbon connection n ener enne 53 Figure 46 FlashPro Programming Screen n eene 53 eee 9 research and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 About This Document This specification introduces the NetFusion EXP baseboard s Libero IDE starter project Whilst the project ZIP binary is provided as a downloadable target to the NetFusion EXP PCB using the open source IP project as a start point will aid and help the user s intended functional product and allow for a start point in their design customization process Intended Audience This document is fully intended to be viewed and reference by Nine Ways customers using the technology for larger designs and projects eee 98 research 908 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 1 Introduction Microsemi design and manufactured the SmartFusion2 FPGA Libero is the IDE software for programming and synthesizing IP cores Along with the bundle of uClinux firmware compilation tools this is the heart of the NetFusion EXP design process for Users Microsemi 1 1 Libero SoC IDE Version 11 x Derivatives Microsemi s Libero IDE software release for designing with Microsemi Rad Tolerant FPGAs Antifuse
2. Figure 26 APB3 fixed bus UART GPIO IO EXP slots and Counter Peripherals Although the APB3 core is used extensively this can be extended to allow any user instantiated core to be connected by adding another slave line to the core This can be obtained by double clicking on the core and editing the settings R Configuring CoreAHBLite_O CoreAHBLite 50100 _ Se n Configuration 2 Memory space 256MB addressable space apportioned into 16 slave slots each of size 16MB g Address range seen by slave connected to huge 2GB slot interface Allocate memory space to combined region slave Slot 0 Sti Slot 2 Slot 3 E Sot4 I Sots Sote 7 Sotz O Slots Fl 509 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Enable Master access MO can access slot 0 v 1 can access slot 0 2 can access slot 0 mn M3 can access slot 0 mn MO can access slot 1 EI M1 can access slot 1 M2 can access slot 1 M3 can access slot 1 DI can access slot 2 M1 can access slot 2 M2 can access slot 2 M3 can access slot 2 MO can access slot 3 n M1 can access slot 3 F1 M2 can access slot 3 a M3 can access slot 3 P can access slot 4 BD 1 can access slot 4 2 can access slot 4 M3 can access slot 4 P can access slot 5 1 can access slot 5
3. m Fam SmartFusion2 Die M2S050T Pkg 484FBGA Verilog Figure 31 SOM Module of the ARM MSS 39 eee 868 research 900 and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 NetFusion EXP ARM Cortex MSS Default Configuration CH Libero C Morethanip SmartFusion SO Project File Edit View Design Tools SmartDesign Help emot 2 50 E M25050 SOM FG484 TOP amp X 25 SOM MSS B 501 n 25 cp opp Q Q b R A NO m id iretur Er Er Susan y rg DHS yas E E ru MSS 1 1 209 Fam SmartFusion2 Die M2S050T Pkg 484FBGA Verilog Figure 32 Exploded View of the Modules in the NetFusion EXP ARM MSS The MSS in the heart of the SmartFusion2 NetFusion EXP design is defaulted and set to the exact current needs of the PCB product Modules 2C1 12 2 GPIO RTC and are disabled currently but there is nothing stopping the user from enabling and wiring out the modules to the SOM sheet The blue modules are currently enabled for
4. tbat 4 e d 3 g 5 EI z2 z28z 5 Fam SmartFusion2 Die 25050 Pkg 484FBGA Verilog Figure 21 Customized RESET logic 30 dol eee 9709 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 14 BIBUF Throughout the NetFusion EXP starter project s fabric logic design is scattered around Bi Directional macros These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion EXP PCB hardware where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below They are controlled by an output enable that drives the state of the output TI ES n anam a pi reset Lr LI FT 1 H LEE EES BIBUF 1 aur BENE d LL ue DO AL mo mum i EFI BIBUF 2 i BIBUF 17 go Dtm HE BIBUF li BIBUF 11 MAD w PAD Y D D r1 ri Figure 22 Bi Directional Fabric Macros for input output signals 31 eee 9 research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 15 CoreSF2Config The SmartFusion2 MSS p
5. es Configure Device gt Open Project im View Programmers oh x Programmer Programmer Port Programmer Programmer Name Type Status Enabled 1 80945 FlashPro4 usb80945 USB 2 0 Iv bx Programmer List Window Refresh Rescan for Programmers creating folder C dell a Driver 3 0 0 build 1 programmer 80945 FlashPro4 Created new project Na Va pro Im ATE errors Warnings A Info no programming file loaded SINGLE Figure 46 FlashPro Programming Screen 53 eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 In the drop down menus choose Configuration then select Load Programming File Chose your STP file to program NetFusion EXP Click on the main PROGRAM button center right of the above screen Wait for the programming to complete typically after several minutes If you cannot select the USB programmer correctly check it is plugged in and also click on Refresh Rescan for Programmers button towards the bottom of the screen above Important Note once the operation to program NetFusion EXP is complete the SmartFusion2 FPGA will re power and start automatically iol 54 eee research and development e NINE WAYS NetFusion EXP Li
6. COREAXI 0 el 22 3 3Q ococoooooooo0 OOOOOOOo0 ad Seks 22 22 S SSSRESSASQE 43 59 83 8 sesssssssss Seege d KE amp a ig uli x ul p T 25 BZ E Sg lt lt lt lt m x O x x 2 E Yu xalg 6 RE e oo z9 1 LI LLL Fam SmartFusion2 Die M25050T Pkg 484FBGA Verilog Figure 24 AMBA Memory Interfaces from ARM for an AXI bus 33 doy eee 9 research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 117 Core AHB Lite In the SOM sheet of the design there exists an IP core used for AHB lite memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AHB lite memory bus interface IP core that they wish to use All of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AHB core is instantiated as CoreAHBLite 0 in the SOM sheet design and currently has no intended functionality other than providing the user with a hook access point to the AHB ARM MSS system The AHB core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment Libero CAMorethanipXSmartFusion SON SU
7. um Hi LL E 1 d CAN TX MF B r F r MERE EN N M2F OR21 Bn ght DO Mam py ada lt lt ry idee Si iii m 1 Pod uuu E ili ia olo OR2 0 gF IP A YR Li I l i 1 l i T Fam SmartFusion2 Die M2S050T Pkg 484 FBGA Figure 17 CAN Controller Interface Logic io eee research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 10 CoreUARTapb As there is no way in the SmartFusion2 ARM MSS block for standard UART connections dev ttyS0 and dev ttyS1 already used the RS484 PCB hardware has to be controlled and handled from a fabric UART core This was instantiated as CoreUARTabp 0 and has an APB connection to the MSS block The uClinux device driver for this hardware access the core as a block of memory and the FIFO RX and TX data is stored in the fabric core The RX ad TX signals to the NetFusion EXP PCB hardware are TTL levels and then get converted to RS485 voltage signals in the electronics CY Libero C Morethanip SmartFusion SOI SR Project File Edit View Design Tools SmartDesign Help DeN 20 GE Egwos sow 63 25050 soM TOP X GEIER 25502 Fam SmartFusion2 De M2SOSOT Pkg 484FBGA Verilog Figure 18 RS485 UART IP core eee 98 research 900 and development e NINE
8. Properties Figure 42 Instantiating an Imported IP Core in your Fabric Design Whether you wish to instantiate into the SmartFusion2 fabric an imported 3rd party source code core from VHDL Verilog or it is from the vault downloaded from ACTEL the process to get the core into the design sheets is the same and relatively simple Even if the core is a macro as part of the ASIC area of the FPGA the process is the same no matter what area of the design it involves Simply move the left panel to select Design Hierarchy and then right click on the listed core of your choice Select Instantiate in M2S SOM or whichever sheet is displayed on the right pane of Libero IDE The core will appear in the design for you to move and anchor ready for connection routing Note f the core has errors the error report page will appear and the instantiation will not occur io eee 9 research 000 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 6 2 1 Building and Synthesizing the NetFusion EXP Design Open the Top Level SOM and the MSS sheets Start with the MSS and right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the SOM sheet Right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the Top Level sheet Right click Generate Component If
9. 24 eee 98 research 900 and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 8 BIBUF Bi Direction buffers for Daughter Card GPIO Throughout the NetFusion EXP starter project s fabric logic design is scattered around Bi Directional macros However the group shown below pertains to the bi directional switching capability of the IO lines for ALL 72 IO EXP daughter card signals These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion EXP daughter card slots where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below CY Libero CAMorethanipNSmartFusion SO eech Project File Edit View Design Tools SmartDesign Help E Ewi x 65 25050 50 6484 X amp smi H 2550 BIBUF 5 BIBUF 22 mD Y D BIBUF 27 Y Fam SmartFusion2 M2S050T Pkg 484FBGA Verilog Figure 16 Bi Directional Buffers for the Daughter Card Expansion IO slots Important Note the Libero logic design of this NetFusion EXP start project is capable of ALL 72 IO lines to the daughter card slots to support i
10. FCCC_0 XTLOSC_CCC_IN Figure 11 Clock PLL Macro Core The core as been instantiated as FCCC 0 There is also a LOCK output signal that is used by the MSS to determine when the PLL has settled and locked onto the desired output frequencies All clock outputs are digital square waves iol 20 deese e NetFusion EXP Libero Starter Project Helper V1 0 April 2015 SI FAB CCC Configurator 3 Figure 12 PLL Clock Macro Settings Output signal GLO is distributed to the memory bus and the MSS ARM block The main base clock frequency for the 166MHz ARM processor is scaled up inside the MSS block 21 dol eee 68 research 900 and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 5 Counter CoreGPIO NetFusion EXP PCB has an on board temperature sensor The output of which is a square wave signal that has a frequency is equivalent to degrees Kelvin down to absolute zero This signal is routed into the SmartFusion2 FPGA fabric and clocks the 16 bit counter counter16 0 The counter s 16 bit output value is wired into GPIO input coreGPIO 1 which is memory addressable from the ARM uClinux applications This serves as a simple 32 bit memory location to read and makes the software algorithm for determining the temperature incredibly simple Note the memory interface from the ARM MSS is an APB int
11. Monitor FPGA Fabric PLL Lock BASE PLL LOCK Cortex M3 and MSS Main Clock M3 CLK 166 MHz 166 000 MHz MSS CCC MDDR Clocks MDDR CLK M3_CLK 1 zl 166 000 MHz v DDR SMC FIC CLK MDDR_CLK 2 83 000 MHz MSS _0 1 Sub busses Clocks W Mock 83 000 V asiak w3ak 2 83 000 MHz FPGA Fabric Interface Clocks M guor 83 000 MHz W Ecick w3ak 7 83 000mHz Figure 36 MSS CCC Divider from the CLK_BASE with in ARM Sub System The main 166MHz clock into the MSS from the fabric is configured to be split up and if necessary divided down to the different areas of the sub system It is derived from the Div 2 83MHz from the PLL in the fabric In the case of NetFusion EXP and the Starter Pack Libero 11 X IDE project all peripherals memory controllers and fabric interfaces run at half the base clock frequency at 83MHz 5 6 RESET Controller amp Configuring RESET MSS RESET 1 0 100 Configuration Enable FPGA Fabric to MSS Reset MSS RESET N F2M V Enable FPGA Fabric to M3 Reset M3 RESET N Enable MSS to FPGA Fabric Reset MSS_RESET_N_M2F Iv eem EE Figure 37 Reset MSS Module NetFusion EXP by default enables the MSS RESET N F2M M3_RESET_N and the MSS RESET N 2 negative reset signals to come in from the SmartFusion2 FPGA fabric iol 44 o development e NINE WAYS NetFusion
12. it was built on the basic project supplied currently by Emcraft They designed and developed the M2S SOM F484 that is housed on the NetFusion EXP baseboard PCB Various IP cores were added to accommodate the need to support and facilitate the vast multitude of NetFusion EXP s PCB hardware available to the ARM MSS sub system in the SmartFusion2 FPGA on the Emcraft M2S SOM F484 housed on NetFusion EXP as one product As the MSS can only drive and support some of the pins on the SOM unit there was a requirement therefore to add more IP cores in the fabric to interface through the I O assignments to the PCB hardware not connected directly to the MSS These additional cores and the default statutory parts of the SOM design in the Fabric are described in the sub sections below 17 eee research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 2 ULPI UTMI OTG USB On the SmartFusion2 F484 package that is used with Emcraft s M2S SOM F484 System On Module the ULPI MSS interface is not supported However the UTMI OTG USB signals are supported As the track routing and the IC USB device on the NetFusion EXP PCB support ULPI an IP core in the fabric is require to convert between the two different USB On The Go protocols and signals This has been instantiated as ulpi port O This OTG core was used from OpenCores at http www opencores com and resides the NetFusion EXP st
13. 000 and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 This SOM sheet lower layer contains the ARM Cortex M3 MSS block and then all of the necessary associated IP core blocks to allow the processor the Emcraft SOM and the wider surrounding NetFusion EXP baseboard hardware to operate and be accessed FCCC o JN Gu Fr 5 VE EC MDDR DOR AXI I MCCC BASE Figure 7 Lower Level SOM sheet MSS block The next screenshot shows a rats nest but the following sub sections illustrate the different parts in more detail Note ncidentally the largest module center left is the MSS ARM cortex processor zoomed above 16 eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Libero C Morethanip SmartFusion SO Project File Edit View Design Tools SmartDesign Help De A i EJ mzs_som EEJM25059 sow FG484 TOP Mj S 50 9 9 SENSEN EIE 1 1 i i 1 H ai Kil Ge ae Tht du Fam SmartFusion2 Die 25050 Pkg 484FBGA Verilog Figure 8 Screenshot of Lower Level SOM sheet of the Starter Pack Libero Project 41 Emcraft Systems The above figure overview encapsulates the whole of the NetFusion EXP SOM sheet However
14. FPGAs and Legacy amp Discontinued Flash FPGAs and managing the entire design flow from design entry synthesis and simulation through place and route timing and power analysis PCN 1108 Silicon Family Support in Libero IDE Libero IDE Software Features Powerful project and design flow management Full suite of integrated design entry tools and methodologies e SmartDesign graphical SoC design creation with automatic abstraction to HDL e IP Core Catalog and configuration e User defined block creation flow for design re use Synplify Pro ME synthesis fully optimizes Microsemi FPGA device performance and area utilization Synphony Model Compiler ME performs high level synthesis optimizations within a Simulink environment eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 e Modelsim ME VHDL or Verilog behavioral post synthesis and post layout simulation capability Physical design implementation floor planning physical constraints and layout Timing driven and power driven place and route SmartTime environment for timing constraint management and analysis SmartPower provides comprehensive power analysis for actual and what if power scenarios Interface to FlashPro programmers Post route On Chip Debug Tools and Identify ME debugging software for Microsemi flash designs Silicon Explorer debugging software for Microsemi antifuse
15. WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 11 CoreSPIO 1 Running as separated IP cores instantiated in the fabric to achieve higher speed sampling by SPI software are SPI blocks These are CORESPI 0 and CORESPI 1 and use an APB interface to the ARM MSS sub system Each core has a 4 wire SPI bus routed out of the FPGA to the wider NetFusion EXP PCB hardware These SPI interfaces connect to DAC and ADC stereo IC devices This allows for audio to be sent and received from the PCB and the digital samples can be processed by the ARM processor from network traffic if necessary SPI is used as it is full duplex and runs at over 1MHz during operation However bottlenecks in the processor application code and also human audible hearing limitations keep realistic sampling operations around 10KHz Figure 19 Stereo Audio Line IN amp Line OUT eee 9 research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 112 Temperature Sensor Glue Logic The baseboard temperature sensor IC is mounted under the Emcraft SOM daughter card and monitors the temperature of the FPGA that can often be demanded to perform high switching tasks in the fabric of the device The sensor produces an output square wave in which the frequency in Hz is equal to the degrees Kelvin on the baseboard This is routed into the FPGA and the fabric and is represented on the SOM design s
16. all correspond with the pin out tracking assignments on the NetFusion EXP PCB product This means that you will not have to consider any of these assignments unless you are planning any major changes to the inherent default design This is very unlikely as you would need then to request changes to the PCB design However this section highlights the assignments in case you also want to make minor changes to the direction of the port default output values and or change internal SmartFusion2 FPGA pull up values VO Editor 25 SOM frog File Edit View Tools Help Ports Package Pins Package Viewer Port Name 1 Direction w UO Standard e PinNumber v Locked v Macro Cell 7 VO state in Flash Freeze mode v Resistor Pull IO available in Flash Freeze mode v Schm a IOEXPI Inout LVCMOS25 ki ADLIB BIBUF Bank7 TRISTATE None No m IOEXP2 Inout 1VCMOS25 K2 E ADLIB BIBUF Bank7 TRISTATE None No 2 IOEXP3 Inout LVCMOS25 MI CH ADLIB BIBUF Bank7 TRISTATE None No 124 IOEXP4 Inout LVCMOS25 ADLIB BIBUF Bank7 TRISTATE None No 5 10EXP5 Inout LVCMOS25 PL mi ADLIB BIBUF Bank7 TRISTATE None No E 26 IOEXP6 Inout LVCMOS25 RI bi ADLIB BIBUF Bank7 TRISTATE None No 27 IOEXP7 Inout LVCMOS25 P2 mi ADLIB BIBUF Bank7 TRISTATE None No 28 IOEXP8 Inout 1VCMOS25 P3 mi ADLIB BIBUF Bank7 TRISTATE None No 2 IOEXP9 Inout LVCMOS25 Ni E ADLIB BIBUF Bank7 TRI
17. designs 1 2 Installation Libero software is downloadable for free from http www microsemi com products fpga soc designresources design software libero soc downloads Some Libero features are optional during installation You can minimize the disk space required by only installing tools you use You must have a license to run Libero the license type that you obtain determines what devices you can use and what P is included The following license types exist for Libero Libero Platinum All devices and RTL IP Bundle Libero Gold Limited devices and Obfuscated IP Bundle View the complete descriptions of the above Libero installations at http www microsemi com products fpga soc design resources design software libero soc licensing View the IP Bundle contents at http www microsemi com products fpga soc design resources ip cores Libero installation is covered in Installing Libero Software on page 16 Note You must have Admin rights on the installation machine to install Libero SoC eee 9 research Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 1 3 Starting a Project and Basic Understanding Before attempting to modify or implement any project in Libero it is advised that you download and read the following PDF references System on Chip installation Libero SoC v11 X User s Guide Libero SoC Quick Start Guide for Software v10 0 Integrated
18. errors eliminate then perform previous instruction over again iol 50 eck development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Libero G NetFusion M2S SOM F484 CATS5 NetFusion F484 prjx Project File Edit View Design Tools SmartDesign Help SEL 25 5 o er Floorplan Constraints E b Verify Post Layout Implementation Generate Back Annotated Files B simulate Ch Verify Timing P Edit Design Hardware Configuration Jl Programming Connectivity and Interface Programmer Settings i Device I O States During Programming Configure Security and Programming Security Policy Manager Bitstream Configuration M Update eNVM Memory Content Program Design Generate Programming Data Debug De Update and Run HO Identify Run SmartDe Clean and Run All Figure 43 Selecting Full NetFusion EXP Synthesis and FPGA Programming Reading file mt Once you are ready to synthesize and program the SmartFusion2 FPGA on the M2S SOM F484 housed on NetFusion EXP select the option shown above Note This should take around 20 minutes on a standard Windows XP 7 8 PC However larger customized design will add significant time especially if the design has strict time constraints 51 eee research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 7 Using FlashPro4 IDE to Program NetFusion EX
19. ASIC3 SmartFusion and Fusion Macro Library Guide Provides descriptions of Microsemi library elements for Microsemi SmartFusion Fusion ProASIC3 and ProASIC3E device families Symbols truth tables and module counts if appropriate are included for all macros SmartFusion2 and IGLOO2 Block Flow User s Guide Describes how to create and integrate Blocks in Libero SoC for SmartFusion2 and IGLOO2 VHDL Vital Simulation Guide Contains information about using the ModelSim to simulate designs for Microsemi SoC devices Verilog Simulation Guide Contains information about interfacing the FPGA development software with Verilog simulation tools ViewDraw User s Guide Describes how to create designs in ViewDraw using menu commands toolbar buttons and by selecting and entering information on dialog boxes ViewDraw for Microsemi is not available on UNIX ModelSim ME Book Case Contains a User s Manual Command Reference and Tutorial These guides contain details about using ModelSim ME Libero s integrated simulation tool Refer to the documentation included with ModelSim ME for more information ModelSim ME documentation is also available at http www microsemi com products fpga soc design resources design software liberosoc Documents Synopsys Synplify Pro ME Documents include release notes user s guide tutorial reference manual and license configuration and set up Refer to the documentation included with Synopsys Synplify Pro for more
20. BGA Verilog Figure 23 APB feedback Bus for Peripheral Configuration by Software eee 9 research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 16 Core AXI In the SOM sheet of the design there exists an IP core used for AXI memory bus accessing It does not have any memory core attached as default when you open and view the project initially However this stub is the user to use to attach to any AXI memory bus interface IP core that they wish to use All of the signals not used are either tied LOW or HIGH if required for input signals and marked as unused if output signals The AXI core is instantiated as COREAXI 0 in the SOM sheet design and currently has no intended functionality other than providing the user with a hook access point to the AXI ARM MSS system The AXI core has an associated location in the overall ARM AHB matrix memory map and therefore attached IP cores can then have hardware address visibility from the ARM processor software environment Libero CAMorethanipSmartFusion SO 3 SOM F4 Fusion E Project File Edit View Design Tools SmartDesign Help 9 2 s x 65 25050 50 FG484 x 255 05 ARABIA HANO S se gag 5 lo a SC E 2 553 ZER Ja HSS
21. Builder Update o Added Independent PCle resets for M2S090 GL090 far hunsncina AUDI iin ko Log Warnings Fam De Pkg Figure 1 Libero 11 X IDE Boot Up Screen eee research 908 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 14 NetFusion EXP When purchasing any NetFusion EXP variant an important component of the overall product is the NetFusion EXP Libero starter project that is provided by Nine Ways Research amp Development Ltd This is downloadable from Nine Ways R amp D Ltd and when expanded into a target directory on your development PC provides an immediate project for your needs Instead of having to start and debug creating an ARM sub system with all of the supporting IP cores required to have a functioning NetFusion EXP PCB just use the provided project From installation you can program the IDE project once synthesized into your NetFusion EXP product using the FlashPro4 USB device This will provide the standard functionality in the Smartfusion2 FPGA fabric on the M2S SOM F484 SOM System On Module to see a working project In the software bundle to this product the uClinux device drivers will drive and control the hardware on the NetFusion EXP PCB through the IP cores in this project for the FPGA fabric Users can contact Nine Ways R amp D for special functionality to be developed and deployed but this
22. De M2S050T Pkg 484FBGA Figure 4 Example of Bottom List I O Ball Assignments The I O assignment dialog is selected from the I O Constraints anchor in Place and Route section below yntnesize AL synplify log 25 SOM srr run options txt e Compile Synthesize M2S SOM rwnetlist log gt Verify Post Synthesis Implementation A M2S SOM compil Simulate 25 SOM compilexml Sp Compile 25 SOM combinatio g Configure Flash Freeze Place and Route E Place and Route 25 SOM gp report 4 gt Edit Constraints A Generate Programmin PE VO Constraints i M2S_SOM_generatePr Timing Constraints Ay Run PROGRAM Action Qi Floorplan Constraints M2S SOM PROGR 4 b Verify Post Layout Implementation ef Generate Back Annotated Files Simulate Verify Timing Verify Power 4 gt Edit Design Hardware Configuration e constrainttiM25 SOM FG484 TOP designer 68 constrainM2S SOM FG484 synthesis 8 Floorplan Constraints Implement Design 14 eee 9 research Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 NetFusion EXP Libero 11 X IDE SoC Top Level Within the NetFusion EXP starter Libero project the 25 SOM Top Level sheet illustrates the lower modules to the design just before the I O ports go out to the real world PCB The ports labeled in this sheet correspond to the I O assignments shown in the previous s
23. Development Environment installation Libero IDE and Software Installation and Licensing Guide Libero IDE License Troubleshooting Guide Note Press CNTL and click to download the links 1 3 1 Libero 11 X IDE First Launch Projet File Edit View Design Tools Help rN e Doe 4 DD lt E startPage 4 New l Open Lib 2 Recent Projects ero System on Chip C Morethanip Smart 3PSWITCH F484 Cltlerethanb Smat LletFusons84 Welcome To Microsemi s Libero SoC v11 4 Software F484 Libero SoC is a comprehensive software suite for designing with Microsemi s SmartFusion2 and SmartFusion SoC FPGAs and IGLOO2 IGLOO ProASIC3 and Fusion FPGA families Visit the Documents tab on your device page at www microsemi com to obtain silicon Datasheets Silicon User s Guides Tutorials and Application Notes Development Kits and Starter Kits are available from the Microsemi website Welcome to Libero SoC What s New in Libero SoC Libero SoC Quickstart Libero SoC Interface Description Libero SoC Release Notes on the Web Libero Ul Enhancements New Tool flow for Simulation Support for VHDL Constructs like Records Array of Arrays ecc Libero Tutorials Non IDE Flow New HDL Text Editor Product Tutorals New Reporting Structure Training Webcasts Dynamic On Die Termination ODT added in DDR Mode Microsemi SoC Website Design Entry and Implementation Learn more e System
24. E Project File Edit View Design Tools SmartDesign Help 3g M Edw sow 63 2505 50 X KEIER IP PARKA AND E EE i L AO 1 Dozo i SADO 85 ELE OO ple L y 9 amp l VE HP li audo 59 DH x 11957 PF LIO CoreAHBLite s Ei CH oo Fv CELL 25 I i Kg Be 5 e z i I C L TL IL I r pusa II i TII Po S 11111 al 5 i e 5 1 S Fam SmartFusion2 De M2S050T Pkg 484FBGA Verilog Figure 25 AMBA Memory Interfaces from ARM for an AHB Lite bus io eee 9 research Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 18 Core APB3 The SOM sheet design has a useful APB3 core instantiated as CoreAPB3 0 which is by default used to collate and connect various important cores to the ARM MSS memory map Currently the temperature sensor counter GPIO CoreGPIO 1 the main GPIO core CoreGPIO 0 the UART core CoreUARTapb 0 the two audio SPI cores CORESPI 0 CORESPI_1 the SPI baseboard device IC chip select logic CoreGPIO 2 and finally the IO Expansion GPIO for the EXP daughter card slots CoreGPIO 3 CoreGPIO 4 CoreGPIO 5 PSP Sb HORTA 50
25. E FABRIC u u e eee eit e re ERE Le HL ovo eua d Per uae a 49 6 2 1 Building and Synthesizing the NetFusion EXP Design seem 50 7 USING FLASHPRO4 IDE TO PROGRAM NETFUSION EXP u u 52 8 REFERENCES u 55 uu 56 10 DOCUMENT HISTORY nn tante eti sa tatan aia Dna au LU SER RES DX e eL NERA Ra RB Dna aD Du ki 57 eee research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 List of Figures Figure 1 Libero 11 X IDE Boot Up Gereen eene ener nennen eren e enne 8 Figure 2 Libero Updating IP Core in the 12 Figure Example of Top List I O Ball Assignments I nennen nens 13 Figure 4 Example of Bottom List I O Ball Assignments nennen 14 Figure 5 Selecting the Constraints eese 14 Figure 6 NetFusion EXP Top Level Sheet 15 Figure 7 Lower Level SOM sheet MSS block a sss 16 Figure 8 Screenshot of Lower Level SOM sheet of the Starter Pack Libero 17 Figure 9 ULPI UTMI USB Converter IP Core 18 Figure 10 SmartFusion2 Reset Controller IP Core 19 Figure 11 Clock PLL Macr
26. EXP Libero Starter Project Helper V1 0 April 2015 This gives more functionality to the user However if it is not a required functionality when the design is customized then they can be de selected 57 FIC 0 EK Mss Fabric Interface Controller FIC 0 Configurator MSS To FPGA Fabric Interface Interface Type NNN Use Master Interface Use Slave Interface mi Advanced AHBLite Options Use Bypass Mode AHBLite only Expose Master Identity Port 7 FPGA Fabric Address Regions MSS Master View FIC32 0 FIC32 1 Fabric Region 0 0x30000000 Ox3FFFFFFF Fabric Region 1 0 50000000 Ox5FFFFFFF Fabric Region 2 0x70000000 Ox7FFFFFFF C Fabric Region 3 0 80000000 Ox8FFFFFFF 5 Fabric Region 4 0 90000000 OxSFFFFFFF Fabric Region 5 0xF0000000 OxFFFFFFFF Figure 38 AHB APB Fabric Interface 1 The NetFusion EXP FIC 0 has been chosen to be assigned for the AHB Lite fabric interface It is a MASTER which connects to the SLAVES in the fabric as the ARM processor has complete control By default the AHB Lite only interfaces to the AMBA DMA Controller used for 3rd party Ethernet IP cores Although the DMA Controller uses AXI for the main data throughput the AHB Lite is used to access the configuration registers Note you will observe that Fabric Region 2 0x7000000 Ox7FFFFFF has been allocated to the next FIC 1 block next sub section The configuration on the left
27. M2 can access slot 5 M3 can access slot 5 MO can access slot 6 E M1 can access slot 6 M2 can access slot 6 m M3 can access slot 6 M0 can access slot 7 m M1 can access slot 7 mi M2 can access slot 7 m M3 can access slot 7 m Le E 1 Figure 27 Editing the APB3 core settings Please Note the previous AXI and AHB Lite cores can be edited and changed with exactly the same method by double clicking on the cores themselves eee research 900 and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 19 AXI AHB Lite 8 APB3 default Memory Mapped Settings SI Configuring COREAXI 0 COREAXI 2 1 101 i x Configuration 7 Memory space Memory space oa Ee lege elei eil AXI data width Enable master access can access slave slot 0 MO can access slave slot 1 can access slave slot2 MO can access slave slot 3 p MO can access slave slot 4 MO can access slave slot 5 can access slave slot6 MO can access slave slot 7 MO can access slave sota MO can access slave slot9 can access slave slot 10 MO can access slave slot 11 can access slave slot 12 can access slave slot 13 can access slave slot 14 can access slave slot 15 Select AXI channel ID width Testbench License Help kaj Figure 28 Defaul
28. Nn Ready Fam SmartFusion2 Die 250507 Pkg 484 FBGA Figure 3 Example of Top List I O Ball Assignments research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 File Edit ew Tools Help 275 ees WOtdtr PortName A Direction Standard Pin Number Locked BankName 1 O state Flash Freeze mode Resistor Pull 1 0 available in Flash Freeze mode Schmitt Trigger Odt static Odtimp Ohm Low Power Exit InputDelay Slew TRISTATE None No off off off CLKOUT Input OTG DATAO Inout DATA1 Inout pense OTG DATA4 oe DATAS a ELE ELE EL ELE EL TRISTATE None off TRISTATE None off Off TRISTATE None off off TRISTATE None off off TRISTATE None off off TRISTATE None off off off off off off off off Date DATA Joe NXT TRISTATE None TRISTATE None TRISTATE None 3199199 9 9 9 9 9 9 TRISTATE None off SIS TRISTATE None TRISTATE TRISTATE off off off off off off off Sj IS S S E off Bl V Ports Package Pins JM Package Viewer J Ready Fam SmartFusion2
29. O nennen enses 23 47 NETFUSION EXP IO EXP DAUGHTER CARD 24 4 8 BIBUF BI DIRECTION BUFFERS FOR DAUGHTER CARD Glo 25 4 09 GAN I GONTROMWER uu T uu eege 26 4 10 METER 27 4 11 Ee WEE 28 4 12 TEMPERATURE SENSOR GLUE Loo 29 4 13 COORDINATED PRES IPA A TE TTT 30 4 14 211218 TEE 31 4 15 ell rel 32 4 16 ses AERE 33 417 sss tj 225 TE TETTE TTT TETTE 34 4 18 CORE AP EE 35 4 19 AXI AHB LITE APB3 DEFAULT MEMORY MAPPED SETTINGS aa 36 4 20 SMARTFUSION2 MSS L uu l Seege EEN SEENEN Ee 39 5 NETFUSION EXP ARM CORTEX MSS DEFAULT CONFIGURATION 40 CAN CONTROLLER ua hee ee ieee S yku AA Ru eld 40 52 Eegeregie 41 539 USB EE 42 54A TE TEE 43 5 9 Uc oc t 44 56 RESET CONTROLLER TT T 44 SM os 45 si sos 46 59 IC PERIPHERAL INITIALIZATION siisescicssskactiasedecacasdeacdcesedetacessdacdva vadi d aka 47 eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 6 ADDING IP CORES FROM VERILOG VHDL I u nnns nnne nn nnne nn 48 6 1 IMPORTING SOURCE FILES sesa a ea EC RE XLI Ln Pu E EET o EO ERR Re abla 48 6 2 INSTANTIATINGIINTO TH
30. P Install and make use of FlashPro IDE on Windows XP 7 8 OS to allow for the stand alone programming of the baseboard without the need for launching installing or using the full Libero 11 X SoC IDE 22 FlashPro ES File Edit View Tools Programmers Configuration Customize Help Dau Bea CHEN lt gt Microsemi ri A Version 11 4 1 17 Release 11 4 5 1 Te Errors Warnings Info 7 Ready No project loaded Figure 44 Opening screen of FlashPro IDE Launch the IDE so that you see the above screen Also if you have just installed the IDE ensure that you have also installed the FlashPro4 USB device driver in the Windows Device Manager Note the device driver should be automatically installed with the FlashPro installation which is downloadable from the Microsemi website iol 52 eee o research e 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Ensure that the NetFusion EXP PCB has the ribbon cable attached from the FlashPro4 USB programmer below Mo pOlduseld KugeO TI Figure 45 Microsemi FlashPro4 ribbon connection On the FlashPro IDE screen click on New Project Enter any project name and make sure you have write permissions to the selected directory you choose a FlashPro al a File Edit View Tools Programmers Configuration Customize Help
31. STATE None No 30 IOEXP10 Inout LVCMOS25 N3 E ADLIB BIBUF Bank TRISTATE None No 31 IOEXP11 Inout LVCMOS25 M2 E ADLIB BIBUF Bank7 TRISTATE None No 32 IOEXP12 Inout LVCMOS25 P4 mi ADLIB BIBUF Bank7 TRISTATE None No 33 IOEXP13 Inout LVCMOS25 ri ADLIB BIBUF Bank7 TRISTATE None No 34 10EXP14 Inout LVCMOS25 2 i ADLIB BIBUF Bank TRISTATE None No 135 IOEXPI5 Inout LVCMOS25 u mi ADLIB BIBUF Bank7 TRISTATE None No 36 IOEXP16 Inout LVCMOS25 B EZ ADLIB BIBUF Bank7 TRISTATE None No 37 IOEXP17 Inout LVCMOS25 5 E ADLIB BIBUF Bank7 TRISTATE None No 38 IOEXP18 Inout LVCMOS25 NS mi ADLIB BIBUF Bank7 TRISTATE None No 39 10EXP19 Inout LVCMOS25 K4 mi ADLIB BIBUF Bank7 TRISTATE None No 140 IOEXP20 Inout LVCMOS25 N6 E ADLIB BIBUF Bank7 TRISTATE None No 41 IOEXP21 Inout LVCMOS25 K5 E ADLIB BIBUF Bank TRISTATE None No 142 IOEXP22 Inout LVCMOS25 M5 2 ADLIB BIBUF Bank7 TRISTATE None No IOEXP23 Inout LVCMOS25 P6 E ADLIB BIBUF Bank7 TRISTATE None No 144 IOEXP24 Inout LVCMOS25 v ADLIB BIBUF Bank TRISTATE None No 45 IOEXP25 Inout LVTTL Kia gI ADLIB BIBUF Bank3 TRISTATE None No EI IOEXP26 Inout lVTTL Bl E ADLIB BIBUF Banka TRISTATE None No IOEXP27 Inout lVTTL B2 E ADLIB BIBUF Banka TRISTATE None No 48 IOEXP28 Inout ADLIB BIBUF Banka TRISTATE None No 49 IOEXP29 Inout lVTTL A2 mi ADLIB BIBUF Banka TRISTATE None No 50 IOEXP30 Inout WTTL ADLIB BIBUF Banka TRISTATE None No IOFXP3I Inout In Lm Ei ADLIR RIRUE Rana TRISTATF None
32. als in the MSS itself It seems overkill but that is the architecture we are ruled by it seems In the case of NetFusion EXP we configure the FIC 0 and FIC 1 fabric interface controllers and also select the AXI Slave interface for the MDDR block Important Note do not ever remove this feature from the design of NetFusion EXP The system will not operate if deleted iol AT eee research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 6 Adding IP Cores from Verilog VHDL 6 1 Importing Source Files Libero C NetFusion M2S SOM F484 CAT5 NetFusion F484 prjx n Edit View an Tools cx I E 25 50 x E M25050 SOM FG484 5 x Create Design 4 amp System Builder amp Configure MSS Create Constraints gt 1 0 Constraints constraint jo M2S050_SOM_FG484_ constraint io M2S_SOM io pdc 69 constraint io M2S_SOM_FG484_TO Timing Constraints synthesis M25 SOM sdc sdc constraintIM25 SOM FG484 S constraintIM25 SOM FG484 Qi Floorplan Constraints Design gt Synthesize Verify Post Synthesis Implement Figure 41 Importing a single Verilog VHDL file into the NetFusion EXP Libero Project From time to time you may want to deviate from the default NetFusion EXP Libero 11 X Starter Project If you need to add catalogue cores especially for the
33. an de select the Fabric Interface and the SOM sheet will adjust accordingly Important You will have to remove and delete the instantiated DMA Controller however Note NetFusion EXP has to follow the architecture of the SOM F484 so this is primarily based upon the Emcraft starter project for this block 41 SES eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 3 USB EN MSS USB Configurator r Configuration Interface Selection options IO Group Selection UTMI LINE STATE UTMI RX DATA g eu UTMI TX READY UTMI RX VALID UTMI RX ACTIVE H Click on a signal row to see the preview UTMI RX ERROR g UTMI_VBUS_VALID UTMI_AVALID UTMI_SESSION_END g UTMI HOST DISCONNECT JE JE g 4 UTMI_ID_DIG Figure 34 USB OTG UTMI Host Controller NetFusion EXP does utilize on the PCB hardware an OTG USB interface In the fabric the ULPI is converted to UTMI and then connected to this MSS internal block The ARM uClinux application code will be able to access this USB block as a block of memory registers and device drivers will be able to control the USB OTG as a USB stack Note the UTMI signals do not get routed to the I O pins directly but the fabric for the use of the ULPI UTMI converter IP core 42 dol eee 9709 res
34. ani development NetFusion EXP Libero Starter Project Helper V1 0 April 2015 NetFusion EXP Libero Starter Project Helper User Guide iol eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Table of Contents 1 INTRODUCTION MEE 6 1 4 LIBERO SOC IDE VERSION 11 X DERMATWES 6 4 2 IINSFA DATION cient e on e ot vat nie ites ede neat me gr ba la a ab A ok onla suba davito 7 1 3 STARTING A PROJECT AND BASIC UNDERSTANDING a 8 1 3 1 Libero 11 X IDE First Launch 8 LE NETEUSIONF EX IAA dee EE ENEE Eege Seed 9 15 PRODUCT DEVELOPMENT 9 1 6 DOCUMENTATION CHECKUST 10 2 DOWNLOADING NEW IP CORE S INTO THE LIBERO IDE INSTALLATION 12 3 NETFUSION EXP LIBERO I O ASSIGNMENTS ss sese sssssssssunannsnnessssusnunnnnnnnnussusnnnnnnnnnnnsss 13 4 NETFUSION EXP LIBERO 11 X IDE SOC TOP LEVEL 15 41 vabo e ed avon 17 42 JUEPI UTMIOTGUSB iit terapeuta er vebo ans eh ee anie s bO degan anc qaquy 18 4 35 Tels TEE 19 CR MN e e EE 20 45 COUNTER EE 22 4 6 NETFUSION EXP BASEBOARD PERIPHERAL COREGPI
35. arter project s hdl sub directory Y Libero C Morethanip SmartFusion O Project File Edit View Design Tools SmartDesign Help Dee oro Fle Edw E 25050 SOM FG484 TOP X 25 52 0 Sa d ulpi port 0 utmi databus16 8 utmi txready ERR HH utmi reset utmi rxvalid PTL TT SS DELOJ um ipee E Uu uuuLE HHTTTTTT utmi termselect utmi rxerror T HF utmi tkvalid ulpi data out 7 0 EJ ZEN H i data wo upi data out B H TT ulpi data in 7 data out 6 Kr T i TIE ulpi data in 6 ulpi data out 5 FFEFFEEO L ulpi data in 5 ulpi data out 4 TITT 4 Fo ulpi_data_in 4 ulpi data out 3 Kr ta sot ulpi data in 3 ulpi data out 2 KIT TT 8 ulpi data in 2 ulpi data out 1 9 17 We CT ulpi data in 1 ulpi data out 0 eEE PETITO am ulpi data in O utmi linestate 1 0 gt TTTTTTTTTTTTT True utmi opmode 1 0 utmi datain 7 0 r 1 utmi dataout 7 0 1 HH LI Fam SmartFusion2 Die M2SOSOT Pkg 484FBGA Verilog Figure 9 ULPI UTMI USB Converter IP Core oD eee 9 research and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 3 CoreSF2Reset This core is used to co ordinate the reset across all of the FPGA in strict timed sequenc
36. bero Starter Project Helper V1 0 April 2015 8 References Please refer to online documented support at the Microsemi reference center For M2S SOM F484 hardware documents please visit the Emcraft hardware for the SOM F484 If you need Libero 11 X references from Emcraft this will illustrate the default designs that NetFusion EXP was built from in order to achieve the baseboard functionality iol 55 Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper 9 Contact Nine Ways Research 8 Development Ltd V1 0 April 2015 E Mail pbates Dnineways co uk Internet www nineways co uk UK Unit A 3 iDCentre Lathkill House rtc Business Park London Road Derby DE24 8UP United Kingdom 44 0 1332 258847 44 0 1332 258823 iol 56 98 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 10 Document History Document Change Notices DCO Version Description Created Changed By Date Version 1 0 Initial Release according to Paul Bates Nine Ways 23rd April 2015 Version 1 0 Copyright Nine Ways R amp D Ltd 2015 All Rights Reserved 57
37. d if master address width gt 32 bits Indirect Addressing Not in use Allocate memory space to combined region slave Slot3 Slot 7 Slot 11 Slot 15 Slot 3 Slot 7 Slot 11 Slot 15 Soto O Sot Slot 2 Slot 4 Slot 5 Slot 6 slots Soto 5 Slot 10 7 Slot 12 E Slot 13 Slot 14 E Enabled APB Slave Slots Soto V Soti Vi Slot2 V Slot 4 V slot 5 V Slote V V Slot 9 Slot 10 Slot 12 Slot 13 Slot 14 1 Testbench User License Obfuscated 7 RTL Figure 30 Default APB Configuration Important Note as a Libero 11 X designer and developer the user may change these defaults and added or remove memory accessible IP cores to from the fabric 38 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper 4 20 SmartFusion2 MSS In the SOM layer sheet of the NetFusion EXP starter project the MSS ARM processor main core is situated in the middle and is shown below If you double click on the MSS block it will expanded and create another window in Libero 11 X on screen Note Refer to the next section for the MSS documentation V1 0 April 2015 Libero CAMorethanipNSmartFusion SO Project File Edit View Design Tools SmartDesign He
38. e It is important for the peripheral logic to be released after the MSS ARM processor and then the fabric logic following the MSS This is a standard Libero ACTEL core from the vault The EXT_RESET_OUT signal is routed out of the FPGA device to the NetFusion EXP PCB The input to this core is the POWER_ON_RESET_N This core was instantiated as CoreSF2Reset_0 Libero CAMorethanipNSmartFusion SOI Project File Edit View Design Tools SmartDesign Help Dee Om omit EJ som sx E M25050 SOM FG484 TOP amp X 2250 l CoreSF2Reset 0 I T MSS RESET N M2F MSS RESET NE F2M POWER ON RESET N EXT RESET INN USER FAB RESET IN N SE A RCOSC 25 50VHZ CONFIG DONE _ CLR INIT DONE Fam SmartFusion2 De 25050 Pkg 484FBGA Verilog Figure 10 SmartFusion2 Reset Controller IP Core eee 98 research 908 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 44 FCCC The entire FPGA sub system comprising of the MSS ARM processor and the main fabric run on clocks all generated from this core It is the main coordination of the clock lines that are distributed The input is 12MHz from an off chip crystal IC The CCC PLL divides down the 12MHz source by 12 to 1MHz Then this is multiplied up by differing amounts for GLO You can add more clock PLL lines as you wish when you are modifying the design
39. e for creating and modifying timing physical and netlist optimization constraints in Libero SoC including families and file formats supported for each constraint It also describes how to create and modify I O constraints with the I O Attribute Editor before compiling your design SmartPower User s Guide Describes how to use SmartPower for power analysis SmartTime User s Guide Describes how to use SmartTime for timing analysis and how to set clock constraints Tcl Command Reference Lists all the Tcl commands and parameters for the Microsemi software tools Analog System Builder FlashROM and Flash Memory System Builder User s Guide Describes how to use the FlashROM generator the Analog System Builder and the Flash Memory System Builder SmartGen Cores Reference Guide Provides descriptions of cores that can be generated from the Catalog using the SmartGen Core Builder iol 10 eee research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 FlashPro User s Guide Contains information about how to program your devices using the FlashPro software and device programmer FlashPro is not available on UNIX SmartFusion2 and IGLOO2 Macro Library Guide Provides descriptions of Microsemi library elements for the Microsemi SmartFusion2 and IGLOO2 device families Symbols truth tables and module counts if appropriate are included for all macros IGLOO Pro
40. eGPIO 3 coreGPIO 4 coreGPIO 5 instantiated block and as a basic example for the user and all 72 GPIOs for the expansion daughter card are connected to these cores for the ARM processor software to handle It will in most cases of user development be changed from this processor visible design to a bespoke customer logic design but the initial design in this provided Libero project allows simple initial software testing and probing before major design changes are implemented The CoreGPIO blocks are visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver Libero C Morethanip SmartFusion 50 log Project File Edit View Design Tools SmartDesign Help t ax E 25050 SOM FG484 TOP X 8 se ore SO KANO 1 H BIBUF 53 pm da na ez SH zu EG pm og EX E Es ul ESI i E Fam SmartFusion2 De 25050 Pkg 484FBGA Figure 15 Main CoreGPIO for the Daughter Card Expansion IO slots iol
41. earch and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 4 Ethernet EK Mss Ethernet MAC Configurator Interface MII Fabric e Line Speed 100 Management Interface Mt TXD 3 0 7 4 MII TX EN MII TX ER f 1 MII RXD 3 0 MII RX ER MII RX DV Click on a signal row to see the preview MII CRS MII COL 1 7 4 TX Figure 35 MSS MAC for 10 100 Ethernet Using SOM PHY This is a very strategic and important module in the MSS of the SmartFusion2 of NetFusion EXP The RJ45 Ethernet connector on the NetFusion EXP PCB is routed directly to the PHY on the M2S SOM F484 which in turn connects into the SmartFusion2 FPGA and directly into the ARM MSS Once in the MSS the Ethernet MAC receives the connections which then provide a memory interface internally for the ARM uClinux device drivers for the network interfaces Note The connections route to the fabric before going up through to the I O assignments It is important to emphasize that with NetFusion EXP all of the Daughter Card Expander GPIO that routes into the SOM sheet of the starter project and terminates at unused block 0 eee 98 research 900 and Q development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 5 MSS CCC Clock Source BASE 83 000 MHz IV
42. ection This sheet is effectively the linkage from the inner SOM design see next section up to the I O balls of the SmartFusion2 FPGA 7 Libero C Morethanip SmartFusion SOI Project File Edit View Design Tools SmartDesign Help Jee OS OBE Edm sow s x Ewososo SOM rese x 6 Poo PAARSKHANO M2S SOM 0 RESET USER FAB RESET nm GSA 1 PADS QIIMMUART 1 PADS statt r 4PEIRS485 4 MMUART 0 DNDSb EJMMUART 0 PADS VACBI r PADSEJ EsIMDDR_BADS IM DEVRST_N XTL mi D Fam SmartFusion2 De 250507 Pkg 484FBGA Verilog Figure 6 NetFusion EXP Top Level Sheet When lower level SOM sheets are built and prepared they propagate information up automatically to this higher sheet New ports suddenly appear and you must then compile this sheet before the main synthesis Note you can instantiate normal IP cores into this top sheet if you wish and it makes sense according to your design requirements This is just the starter project so everything by default is kept in the lower SOM module But this can change rapidly as your customization starts to take effect The lower SOM sheet of the NetFusion EXP starter Libero project contains all of the default designs and linkage 15 ud research o
43. erface counter16 0 clkout reset counter 15 0 Figure 13 Temperature Sensor Logic 22 eee research 000 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 6 NetFusion EXP Baseboard Peripheral CoreGPIO The vast majority of the hardware on the NetFusion EXP PCB is connected through this core The obvious exceptions are the Ethernet pathways RS485 UART and the SPI audio input output However all of the 2C Relays I O expanders Real Time clock IC voltage monitor expansion I O and all other slow speed communications are handled through this coreGP O 0 instantiated block It is visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver LIIE lt TH CoreGPIO 0 ERRER E eR A T Rx x Corel x f 83383 38 T 2230 XXXXXX TE Kat ee UI Figure 14 Main PCB GPIO Interface with APB bus from the ARM Processor MSS block iol 23 eee 9 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 7 NetFusion EXP IO EXP Daughter Card GPIO The IO EXP Daughter Card expansion slots on the NetFusion EXP PCB are connected through these cores The expansion slot functionality is handled through cor
44. fabric macros then download using the vault Also as illustrated above you also may wish to import 3rd party source IP cores To do this on the panel on the left of the Libero IDE right click on Create HDL and then select mport Files This will bring the Verilog VHDL into the main system You can check if the source code has syntax errors and is valid for the synthesizer Libero 11 XSynplify Pro that Libero 11 X uses This mechanism enables the NetFusion EXP project to be customized and built on for a user s system requirement iol 48 eee 9709 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 6 2 Instantiating into the Fabric Q Libero C WetFusion M2S SOM F484 CAT5NetFusion F484 prjx Project File Edit View Design Tools SmartDesign Help SaS o Al Design Hierarchy Gw amp gwososo sow rese TOP x E e bd gt EE 4 9 o eM work A XTLOSC FAB osc_comps v EN RCOSC 1MHZ FAB osc comps v RCOSC 1MHZ osc comps v M2S050 SOM FG484 TOP M2S SOM EN 25 SOM COREAXI 0 COREAXI cor EB CoreGPIO coregpio v EI CoreSF2Config coresf2config v A CoreSF2Reset coresf2reset v EN CORESPI corespi v Create I O Constraint from Module COREAHELITE 3X Remove Core Definition COREAPE3 LIE Mi COREAXI OBF Delete from Project CORESPI LIB Delete from Disk and Project
45. heet as TEMP SENSOR This in turn clocks the counter16 0 which has a 16 bit register output and can be read into the ARM software environment via the CoreGPIO 1 APB3 core Although this read value wraps around 16 bit values the software can use a one second timer to run comparisons and then calculate the temperature in Kelvin counter16 0 reset counter 15 d INT 15 0 Figure 20 Temp Sensor Counter Logic eee 9709 research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 13 Coordinated RESET The customized IP core instantiated as mtip reset 1 coordinates a longer reset pulse than the power on reset core often provides The source SYSRESET 0 feeds into the mtip reset 1 which then provides an output to the whole SOM sheet design This includes the ARM MSS block memory cores GPIO and all peripherals Libero CAMorethanipASmartFusion SOl 7 Ps Project File Edit View Design Tools SmartDesign Help DEN e O0 B Suz sow 65 u2s050_SOM_FG484 TOP B 92 EN FIC 2 Al SYSRESET 0 DEVRST POWER ON RESET FIC 2 APB M MDDR DER AXI SLAVE APB SLAVE FIC 2 APB MASTER M2S SOM MSS 0 RC2A AC E 2 88
46. information Synopsys Synplify Pro ME documentation is also available at http www microsemi com products fpga soc design resources design software libero soc documents iol 11 eee 9709 research 900 and development e NetFusion EXP Libero Starter Project Helper V1 0 April 2015 2 Downloading New IP Core s into the Libero IDE Installation on SO Project File Edit View Design Tools SmartDesign Hep 5 i 3 lt Q of E Eu Ei 25050 SOM FG484 amp X 6 BEDA nj 25 2 AR AAA HR Fam SmartFusion2 Die M25050T Pkg 484FBGA Verilog Figure 2 Libero Updating IP Core in the Vault When you first load the NetFusion EXP starter project into the IDE the most likely occurrence to happen is a system message warning you to update New IP Cores This is because the design includes cores that you possibly do not have on your vault on your local hard drive Click YES to proceed and let the download process complete Note this may take several minutes and you MUST have a network connection and gateway to the internet 12 eee research and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 3 NetFusion EXP Libero I O Assignments The NetFusion EXP Libero starter project is delivered already with the I O balls of the FPGA assigned ready for the user These
47. lp Dee ns Gus SOM FG484 TOP 22 25 5 050 Q Q hO HB A NO ESS 555 592 pe AER a M2S SOM MSS 0 MCOC CLK BASE FIC 2 AFB M FRESET ra MCOC_CLK BASE PLL LOCK RC 2 M S PRESET_N NAI S COMM BLK INTI MSS RESET N F2M MSS RESET H 5 M3 RESET N WD DOR CORE RESET MSS INT M2F15 0 n DOR AXI RMW 871 FADSE INT 2 1501 1 FADSEJ LK MSS uv ag MMUART 1 7 e mtip reset 1 I MSS INT F2M 14 MMUART 1 RXD wsS NTF2413 MMLART_0_PADSE reset ext resetn MSSINTF2M12 MAC BRICE MSS NTF2M411 MAC MI TXI FA MSS NT F2M 10 MAC 1 MSS INT F249 MILTX INT FMS MAC RXD 3 0 MSS NLF2M7 MAC RX ER MSS INT FMS DV MISS INT FMS MAC MI CRS LP MSINTFMA MI COL MSS NTF243 MAC MI RCQOK ISS INT 2 MAC WD INTE MAC MILMDC MSS INT F2M 0 MAC MI MDO EN MAC MI MIL MDOR Pen MDDR DOS TMATCH 0 MOOR CAS WR MDDR N RA WO MOOR CS MDOR ODT TH BE EE EE MOOR F MDDR RESET N BA MORWEN P MDER ADRIEN BA MDDR BA MDDR DOS TMATCH O IN E Tw ONO 1
48. nn enne ener 35 Figure 28 Default AXI 36 Figure 29 Default AHB Lite Configuration essere enne enne rennen enne 37 Figure 30 Default APB Configuration essere 38 Figure 31 SOM Module of the ARM ME 39 Figure 32 Exploded View of the Modules in the NetFusion EXP ARM MSS 40 Figure 33 MDDR MSS Controlling LPDDR Memory with AXI from 41 Figure 34 USB OTG UTMI Host Controller AA 42 Figure 35 MSS MAC for 10 100 Ethernet Using 43 Figure 36 MSS CCC Divider from the CLK BASE with in ARM Sub System 44 Figure 37 Reset MSS Module 44 Figure 38 AHB APB Fabric Interface fl 45 Figure 39 APB3 AHB Lite Fabric Interface 2 46 Figure 40 APB Peripheral Hardware Confiouration 47 Figure 41 Importing a single Verilog VHDL file into the NetFusion EXP Libero 48 Figure 42 Instantiating an Imported IP Core in your Fabric Design 49 Figure 43 Selecting Full NetFusion EXP Synthesis and FPGA
49. nput or output configuration As the user customizes and changes the design this may become more specific to input or output depending the required design Additionally some daughter card s themselves may have input only or output only circuitry present which means if the user is keeping this starter project design they will still have to configure the associated GPIO core to reflect the I O setup 25 eee 9 research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 4 9 CAN Controller The CAN transceiver on the NetFusion EXP baseboard PCB is connected to the CAN Controller inside the MSS block either directly for the RX and TX or via OR gate logic for the enable lines These are instantiated as OR2 0 OR2 1 and serve as a mask to either allow bus bus2 or both to be used during transmission The masks are controlled by signals from the small GPIO core CoreGPIO 2 The signals from the GPIO core to mask the enable lines ensures that application software controls the dual bus behavior for the CAN interface on NetFusion EXP Corresponding GPIO bits that are cleared disable that CAN bus and those which are set enable it E CAMore Dawes Se I E wos sow m x EJ m2s050_s0M_FG484 TOP M BoP oo BAA VOD U IIVI _7N V IN 3 LE T Eii USB UTMI VCONTROL 3 00 rg CAN FABRICEI d ra CAN RX F2M
50. o Core 20 Figure 12 PLL Clock Macro Settings enne nete trennen enne 21 Figure 13 Temperature Sensor Logic sse enne ener innere trennt rennen rennen 22 Figure 14 Main PCB GPIO Interface with APB bus from the ARM Processor MSS block 23 Figure 15 Main CoreGPIO for the Daughter Card Expansion slots sese 24 Figure 16 Bi Directional Buffers for the Daughter Card Expansion IO 10 25 Figure 17 CAN Controller Interface Logic nennen enne enne rennen nee 26 Figure 18 R8485 UART IP core enne 27 Figure 19 Stereo Audio Line IN amp Line OUT 28 Figure 20 Temp Sensor Counter Loge 29 Figure 21 Customized RESET logic essent enne enne trennen trennen nne 30 Figure 22 Bi Directional Fabric Macros for input output signals 31 Figure 23 APB feedback Bus for Peripheral Configuration by Software 32 Figure 24 AMBA Memory Interfaces from ARM for an AXI 33 Figure 25 AMBA Memory Interfaces from ARM for an AHB Lite 34 Figure 26 APB3 fixed bus UART GPIO IO EXP slots and Counter Peripherals 35 Figure 27 Editing the APB3 core settings
51. onnected in the SOM sheet layer to GPIO SPI UART USB I2C etc as standard in the starter project If you decide to write and author your own IP cores in Verilog or VHDL you can drop and place the code into the Project Dir hdl directory Note Once you have started to customize and tailor the project to your own needs and functionality obviously renaming the project is easy just rename the project directory and inside that directory just rename the prj file Close and re open the Libero IDE eee research and development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 1 6 Documentation Checklist Libero SoC User s Guide Explains how to use the Libero SoC Project Manager including Designer and SmartDesign SmartFusion2 and IGLOO2 SmartTime I O Editor and ChipPlanner User s Guide Provides details about using SmartTime for timing analysis placing macros floor planning and viewing chip resources for SmartFusion2 MultiView Navigator User s Guide includes documentation for ChipPlanner PinEditor UO Attribute Editor and NetlistViewer in MVN Provides details about placing macros floor planning and viewing chip resources contains information about using NetlistViewer in the MultiView Navigator to view your netlist describes how to use the PinEditor in MVN describes how to use the I O Attribute Editor tool Design Constraints User s Guide Provides a complete referenc
52. panel above selects mapping for both FIC 0 and FIC 1 NetFusion EXP assigns Fabric Region 2 to the APB memory interface so that the UART SPI and GPIO can be accessed in the fabric otherwise only this AHB Lite interface would be mapped which would severely limit the NetFusion EXP functionality and capability lol 45 9900000 _ Ot NetFusion EXP Libero Starter Project Helper V1 0 April 2015 58 FIC1 Mss Fabric Interface Controller FIC 1 Configurator I Figure 39 APB3 AHB Lite Fabric Interface 2 Using the configuration from the previous FIC_0 block previous this MSS module enables the APB interface to access the GPIO SPI and UART in the NetFusion EXP SmartFusion2 fabric Note this is also an APB Master as the ARM processor has complete control io 46 development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 9 FIC 2 Peripheral Initialization cortex zl Fabric DDR and or SERDES Blocks Iv wok li ONFIG PRESET Figure 40 APB Peripheral Hardware Configuration As described earlier in this document the SmartFusion2 FPGA is setup and primarily configured by boot up software executed by the ARM processor This can be bare metal code or early boot code from uClinux called u boot This MSS module block enables the signals to connect a feedback APB interface from the ARM processor to the other peripher
53. rocessor sub system always as standard has a default CoreSF2Config block Which loops back an APB bus out and then back into the MSS block This seems at first strange and can be very confusing However it is the inherent architecture of the FPGA ASIC area that most of the peripheral devices inside the MSS ARM processor core are not actually controlled by the selections made in the Libero 11 X IDE It is the software in u boot during boot up that configures If say for instance an AHB Lite interface is selected in Libero then this does not configure the SmartFusion2 FPGA itself It saves a configuration file that can be included by software in either bare metal programming or the u boot from Emcraft uClinux environment Only when the boot up code access the APB feedback bus CoreSF2Config 0 and manipulates hardware peripheral memory address does the peripherals in the MSS get the correct mode of operation intended for them C Libero C Morethanip SmartFusion SO a Project File Edit View Design Tools SmartDesign Help E Edw m x 65 5050 SOM FG484 TOP X Bedo mse or e a el mag w 42 gt 2 gt lt Iz 2 lt lt lt lt Bu B 96 3 0 NETT 20 pe m E o8 o CoreSF2Config_0 age 2118 9 gt L se gol Q Kil II j I Il LLL o f Fam SmartFusion2 Die M2S050T Pkg 484F
54. serves as an addition to this starter Libero 11 X IDE project Moreover in conjunction with MorethanIP GmbH customized and locked down projects can be tailored for customer requests but that also is separate to this project 1 5 Product Development At the point where the Libero IDE SoC has been installed the NetFusion EXP starter project has been downloaded and exploded into a target directory on your PC the project has been loaded synthesized programmed and shown to be running on the NetFusion EXP PCB product you are ready to begin your development As standard the main fast Ethernet pathways into the SmartFusion2 FPGA fabric are wired in through the FPGA ball I O assigned the I O editor brought down through the Top Level and then into the SOM level of the design in the project They then terminate at a dummy IP core for all un assigned wires this makes life a lot easier for the developer knowing that all the NetFusion EXP traces coming into the M2S SOM F484 are wired into the SOM level of the fabric design Changes are therefore quick and easy to then re assign in that lower level sheet to new instantiated IP cores of the user s choice The category of wires left terminated and not used are the GMII Ethernet pathways Users can download and use Vendor specific MAC SWITCH cores or chose to privately purchase cores from reputable design houses such as MorethanIP All other used hardware on the NetFusion EXP PCB is wired and c
55. t AXI Configuration research 900 and development e NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Configuration r Memory space Memory space Address rani 0x00000000 0x7FFFFFFF 0 80000000 0xFFFFFFFF r Allocate memory space to combined region slave Soto Sot2 Sot3 Setz Slot 7 Slot 8 Slot 10 Slot 11 Slot 12 Slot 14 Slot 15 Enable Master access can access slot 0 1 can access slot 0 M2 can access slot 0 M3 can access slot 0 can access slot 1 1 can access slot 1 M2 can access slot 1 M3 can access slot 1 can access slot 2 1 can access slot 2 M2 can access slot 2 M3 can access slot 2 can access slot 3 MI can access slot 3 M2 can access slot 3 M3 can access slot 3 can access slot 4 MI can access slot 4 M2 can access slot 4 M3 can access slot 4 Hep Figure 29 Default AHB Lite Configuration eee 9709 research 900 and 5 development e NINE WAYS Et Configuring CoreAPB3 0 CoreAPB3 NetFusion EXP Libero Starter Project Helper V1 0 April 2015 Configuration Data Width Configuration APB Master Data Bus Width 9 32bit 16bit D 8bit Address Configuration Number of address bits driven by master E z Position in slave address of upper 4bits of master address 27 24 Ignore
56. the NetFusion EXP design as they have functional requirements and the signals are wired out to the SOM sheet then if necessary up to the I O assignments then out of the FPGA device itself 51 CAN Controller The CAN Controller shown in the above block handles the processing of the data streams in and out of the two transceiver buses The uCLinux environment is capable of supporting the hardware and is represented as a file descriptor in the typical UNIX way eee 98 research 900 and Q development NINE WAYS NetFusion EXP Libero Starter Project Helper V1 0 April 2015 5 2 MDDR Import Configuration Export Configuration Restore Defaults General Memory Initialization Memory Timing Memory Type kee zl Data Width 16 SECDED Enabled ArbitrationScheme mp3 rz HghstPiotyD 2 Address Mapping ROW BANK COLUMN Fabric Interface Settings Use an AXI interface C Use an AHBLite Interface C Use two AHELite Interfaces Figure 33 MDDR MSS Controlling LPDDR Memory with AXI from Fabric The MDDR has been configured to use a single data rate LPDDR SDRAM device on the M2S SOM F484 using 16 bit data width Priority has been given to the AXI master interface from the fabric where the default connection is to the AMBA DMA Controller for 3rd party MACs and Ethernet SWITCH If you do not wish to keep the DMA Controller or any AXI interface for that matter then you c

NetFusion-EXP Libero Project Helper PDF

Contents

Download Pdf Manuals

Related Search

Related Contents