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User`s Manual 10.97 8-Bit CMOS Microcontroller http

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1. 8 1 to 8 4 Block diagram ud tm ERA 8 1 Refreshing of the WDT 8 4 Registers WDCON and WDTREL 8 2 Reset operation 8 4 Starting of the WDT 8 3 Time out periods 8 3 WDGON slo fx Meee te BS feta 3 7 3 9 8 2 VV DIC 4 tons He ctun a ah Etant ta 3 9 8 2 WDTBSEL lt a ao 3 8 8 2 WDIREL 53552155 pila 3 7 3 8 8 2 WT Se anid nic RES beds 3 9 8 2 MIEL S er eerie Dn 3 9 X AMAR rra e Et 3 3 3 9 XRAM operati0N oo 3 3 Accessing twith DPTR 3 4 Accessing with RO R1 3 4 Enable disable control 3 3 Semiconductor Group 12 6 1997 10 01
2. ADDATH ADDATL D94 DAH v vv Conversion Clock finc Prescaler 32 16 8 4 Input Clock fy Start of Conversion Write to Internal ADDATL Bus Shaded bit locations are not used in ADC functions MCB02616 Figure 6 39 Block Diagram A D Converter Semiconductor Group 6 99 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 2 A D Converter Registers This section describes the bits functions of all registers which are used by the A D converter Special Function Registers ADDATH Address D9 Reset Value 00y Special Function Registers ADDATL Address DA Reset Value OOXXXXXXpg Bit No MSB LSB 7 6 5 4 3 2 1 0 Bog MSB ae 7 6 5 4 3 2 ADDATH LSB DAH 1 0 ADDATL The registers ADDATH and ADDATL hold the 10 bit conversion result in left justified data format The most significant bit of the 10 bit conversion result is bit 7 of ADDATH The least significant bit of the 10 bit conversion result is bit 6 of ADDATL To get a 10 bit conversion result both ADDAT register must be read If an 8 bit conversion result is required only the reading of ADDATH is necessary The data remains in ADDAT until it is overwritten by the next converted data ADDAT can be read or written under software control If the A D converter of the C504 is not used register ADDATH can be used as an additional general purpose registe
3. ATO 0 0 2 Start of CT1 Duty Cycles CC 0 100 CC 1 87 5 CC 4 50 ER 2 e O 5 Q O Dm wo e c 2D aD gt Q gt OS lt CC 7 12 5 CC 7 0 NS r CC 0 CC 1 CC 4 CC or COUT COINI Bit is 1 Active Low Signals e z CC 7 N CC Content of the CC H CC L Compare Registers CCP Content of the CCPH CCPL Period Register CT1O Content of the CT1OFH CT1OFL Offset Register MCT03357 Figure 6 21 Compare Timer 1 Mode 0 In the example above compare timer 1 counts from 0000y up to 00074 value stored in CCPH CCPL The offset registers CT1OFH CT10FL have a value of 00004 If programmed in compare mode two output signals are assigned to the related CAPCOM channel x CCx and COUTx The mode select bits in the SFRs CMSELO and CMSEL1 define which of these two outputs will be Semiconductor Group 6 36 1997 10 01 SIEMENS On Chip Peripheral Components C504 controlled by the CAPCOM channel In figure 6 21 only the CCx signal is shown but the same or the inverted waveform can be generated at the COUTx outputs After reset all CCx COUTx pins are at high level driven by a weak pullup With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level which is defined by the bits in SFR COINI In figure 6 21 the upper
4. Typ 18 us Max 34us The RC oscillator will already run at a Voc below 4 25V lower specification limit Therefore at slower Vcc rise times the delay time will be less than the two values given above After the on chip oscillator has finally started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of max 768 cycles of the RC oscillator clock in order to allow the oscillation of the on chip oscillator to stabilize figure 5 2 Il Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset request is released figure 5 2 IIl However an externally applied reset still remains active figure 5 2 IV and the device does not start program execution figure 5 2 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence Using a crystal or ceramic resonator for clock generation the external reset signal must be hold active at least until the on chip oscillator has started and the internal watchdog reset phase is completed after phase III in figure 5 2 When an external clock generator is used phase ll is very short Therefo
5. 6 2 Timers Counters The C504 contains three 16 bit timers counters which are useful in many applications for timing and counting In timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 12 oscillator periods the counter rate is 1 12 of the oscillator frequency In counter function the register is incremented in response to a 1 to 0 transition falling edge at its corresponding external input pin TO or T1 alternate functions of P3 4 and P3 5 resp In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles 24 oscillator periods to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it must be held for at least one full machine cycle 6 2 1 Timer Counter 0 and 1 Timer counter 0 and 1 of the C504 are fully compatible with timer counter 0 and 1 of the C501 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1
6. 8 2 Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of typ 1 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Fast internal reset after power on The oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started The oscillator watchdog unit also works identically to the monitoring function Control of external wake up from software power down mode When the power down mode is left by a low level at the INTO pin the oscillator watchdog unit assures that the microcontroller resumes operation execution of the power down wake up interrupt with the nominal clock rate In the power down mode the RC oscillator and the on chip oscillator are stopped Both oscillators are started again when power down mode is released When the on chip oscillator has a higher frequency than the RC oscillator the microcontroller starts operation after a final del
7. In the counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin T2 P1 0 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes two machine cycles to recognize a 1 to 0 transition the maximum count rate is 1 24 of the oscillator frequency To ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle Semiconductor Group 6 25 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 2 1 Timer Counter 2 Registers Totally six special function registers control the timer counter 0 and 1 operation TL2 TH2 and RC2L RC2H counter and reload capture registers low and high part T2CON and T2MOD control and mode select registers Special Function Register TL2 Address CC j Reset Value 00y Special Function Register TH2 Address CDy Reset Value 00y Special Function Register RC2L Address CAH Reset Value 00y Special Function Register RC2H Address CBy Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 CCy u 6 iD 4 3 2 A 0 TL2 CDy 7 6 5 4 EO 2 1 0 TH2 CAH 7 6 5 4 EC 2 1 0
8. SIEMENS On Chip Peripheral Components C504 6 2 1 3 Mode 1 Mode 1 is the same as mode 0 except that the timer register is running with all 16 bits Mode 1 is shown in figure 6 13 y CT 0 n Interrupt 2 0 THO TFO A 8 Bits 8 Bits CT 1 P3 4 T0 P3 2 INTO Control MCS02095 Figure 6 13 Timer Counter 0 Mode 1 16 Bit Timer Counter Semiconductor Group 6 22 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 1 4 Mode 2 Mode 2 configures the timer register as an 8 bit counter TLO with automatic reload as shown in figure 6 14 Overflow from TLO not only sets TFO but also reloads TLO with the contents of THO which is preset by software The reload leaves THO unchanged Interrupt TFO P3 4 T0 Reload Gate P3 2 INTO MCB021 40 Figure 6 14 Timer Counter 0 1 Mode 2 8 Bit Timer Counter with Auto Reload Semiconductor Group 6 23 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 1 5 Mode 3 Mode 3 has different effects on timer O and timer 1 Timer 1 in mode 3 simply holds its count The effect is the same as setting TR1 0 Timer 0 in mode 3 establishes TLO and THO as two separate counters The logic for mode 3 on timer 0 is shown in figure 6 15 TLO uses the timer 0 control bits C T Gate TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from timer 1 Thus THO now controls
9. Semiconductor Group 6 50 1997 10 01 SIEMENS On Chip Peripheral Components C504 Capture Compare Channel Mode Select Registers The capture compare channels of the CAPCOM unit can operate individually either in compare mode or in capture mode The CMSELO and CMSEL1 registers contain the mode select bits for the CAPCOM unit Special Function Register CMSELO Address E3y Reset Value 00y Special Function Register CMSEL1 Address E444 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL BSH age 42 4 10 03 02 o1 00 CMSELO SSS eS V CAPCOM CAPCOM Channel 1 Channel 0 7 6 5 4 3 2 1 0 CMSEL CMSEL CMSEL CMSEL J F7 CAPCOM Channel 2 Bit Function ESMC Enable software controlled multi channel PWM modes If ESMC 0 switching of the follower state in 4 5 6 phase multi channel PWM mode is controlled by compare timer 1 reaching its period value If ESMC 1 switching of the follower state in 4 5 6 phase multi channel PWM mode is controlled by bit NMCS NMCS Next multi channel PWM state Setting bit NMCS with ESMC set will select the follower state in the 4 5 6 phase multi channel PWM mode which is taken into account at the output pins when compare timer 1 is 0 Bit NMCS is reset by hardware in the next clock cycle after it has been set CMSELx3 Switching compare timer 2 output si
10. Set by hardware when an external interrupt 2 is detected In edge triggered mode this bit is reset by hardware when the interrupt is serviced Semiconductor Group 7 14 1997 10 01 SIEMENS Interrupt System C504 Bit Function IXETF External interrupt edge trigger mode selection IXETR x 0 2 refers to INTO INT2 IXETF IxETR Function 0 0 INTx inputs are not sensitive for either rising or falling edge 0 1 INTx operates in rising edge triggered mode 1 0 INTx operates in falling edge triggered mode default after reset 1 1 INTx operates in falling and rising edge triggered mode 7 6 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higer priority is already in progress the additional wait time obviously d
11. 00y Special Function Register TL1 Address 8By Reset Value 00y Special Function Register TH1 Address 8D Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 0 8AH u 6 iD 4 3 2 0 TLO 8Cy Ti 6 5 4 EO 2 0 THO 8By 7 6 5 4 3 2 0 TL1 8DH 7 6 5 4 d 2 0 TH1 Bit Function TLx 7 0 Timer counter 0 1 low register 20 1 x 0 Operating Mode Description 0 TLx holds the 5 bit prescaler value 1 TLx holds the lower 8 bit part of the 16 bit timer counter value 2 TLx holds the 8 bit timer counter value 3 TLO holds the 8 bit timer counter value TL1 is not used THx 7 0 Timer counter 0 1 high register al Operating Mode Description 0 THx holds the 8 bit timer counter value 1 THx holds the higher 8 bit part of the 16 bit timer counter value 2 THx holds the 8 bit reload value 3 THO holds the 8 bit timer value TH1 is not used Semiconductor Group 6 18 1997 10 01 SIEMENS On Chip Peripheral Components C504 Special Function Register TCON Address 884 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8DyH 8Ch 8By 8AH 89H 88H 88H TF1 TR1 TFO TRO 1E1 IT1 IEO ITO TCON The shaded bits are not used in controlling timer counter 0 and 1 Bit Function TRO Timer O run control bit Set cleared by software to turn timer counter 0 ON OFF TFO Timer 0 overflow flag Set by hardware on timer counter overflow Cleared by hardware when
12. 11 15 Operating mode 2 and 3 6 95 to 6 97 External clock timing 11 15 RegisterS 6 83 to 6 84 Lock bit access timing 11 19 SMO Gat bs sees ts atodos 3 8 6 84 Program memory read cycle 11 14 SMT x Raesent o 3 8 6 84 Programming mode read cycle 11 18 SMS soie baa e Pp C soa 3 8 6 84 Programming mode write cycle 11 17 SMOD Aids utt past saves 3 8 6 85 Protected ROM OTP verify timing 11 21 Cj ME ae So ta she tds E 2 3 3 6 3 8 ROM verification mode 1 11 20 Semiconductor Group 12 5 1997 10 01 SIEMENS nee C504 ROM verification mode 2 11 21 Resta ER AYEDAE AS 3 3 Unprotected ROM verify timing 11 20 Version byte access timing 11 19 EE PEE 3 6 3 8 6 18 A ted ts 3 6 3 8 6 18 dg iet eiie emo edt teat 6s 3 7 3 9 6 26 MMOD ET 3 6 3 8 6 20 A ade pte a eee EXE 3 8 6 19 MPM no doy ane punte a aay derants ses 3 8 6 19 Rn C PRU ETE ER eae 3 9 6 25 6 27 TRGOBN e ia Er eod dake 3 7 3 9 6 46 6 60 TREND Svr ccoo cosida 3 9 6 60 TREN ce tC ewe EX 3 9 6 60 TIBEN2 gt reed 3 9 6 60 TRENS 24 srta da Seach 3 9 6 60 TREN A ay o e os 3 9 6 60 TRENS cerit opni eee Dates 3 9 6 60 TRE rae epa Rie ee aad 3 9 6 60 PERPEN c acostada 3 9 6 60 A Spas 3 9 V Version bytes 10 11 10 12 Version registers 10 11 10 12 VROT ae a Cec bb e cartel earth 3 11 VAN coire E E E 3 11 VRZ St es ee aaa ee dla ci 3 11 W Watchdog timer
13. 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of timer O TH1 and TL1 for timer 1 respectively The operating modes are described and shown for timer 0 If not explicitly noted this applies also to timer 1 Semiconductor Group 6 17 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 1 1 Timer Counter 0 and 1 Registers Totally six special function registers control the timer counter 0 and 1 operation TLO THO and TL1 TH1 counter registers low and high part TCON and TMOD control and mode select registers Special Function Register TLO Address 8Aq Reset Value 00y Special Function Register THO Address 8C Reset Value
14. BCM1 BCMO BCON Bit Function BCMP In multi channel PWM mode Machine polarity If BCMP is set and multi channel PWM mode is selected PWM1 0 0 0 all enabled compare outputs COUTx and CCx are switched to the compare timer 2 output signal during their active phase If BCMP is cleared only the COUTx outputs are switched to the compare timer 2 output signal during the active phase in multi channel PWM mode CMSELx3 must be set for that functionality BCEM In block commutation mode Error mode select bit If BCEM is set in block commutation mode in rotate right or rotate left mode additionally a wrong follower condition causes the setting of BCERR if EBCE is set Semiconductor Group 6 68 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function PWM1 Multi channel PWM mode selection PWMO These bits select the operating mode of the multi channel PWM modes PWM1 PWMO Function 0 0 Block commutation mode for hall sensor inputs 0 1 4 phase multi channel PWM mode 1 0 5 phase multi channel PWM mode 1 1 6 phase multi channel PWM mode EBCE Enable interrupt of block commutation mode error If EBCE is set the emergency interrupt for a block commutation mode error condition of the CCU is enabled In block commutation mode an emergency error condition occurs if a false signal state at INT2 INTO or a wrong follower state if selected by bit BCEM is detected see also table 6
15. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA an additional conversion error of 1 2 LSB is permissible During the conversion the ADC s capacitance must be repeatedly charged or discharged The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time The maximum internal resistance results from the programmed conversion timing Not 100 tested but guaranteed by design characterization Semiconductor Group 11 7 1997 10 01 Device Specifications C504 SIEMENS 11 4 AC Characteristics for C504 L C504 2R C504 2E Voc 5 V 10 15 Vas 0 V T 0 to 70 C T 40 to 85 C T 40 to 110 C for the SAH C504 T 40 to 125 C for the SAK C504 C for port O ALE and PSEN outputs 100 pF C for all other outputs 80 pF for the SAB C504 for the SAF C504 Program Memory Characteristics Parameter Symbol Limit Values Unit 12 MHz clock Variable Clock l tc c 3 5 MHz to 12 MHz min max min max ALE pulse width fu 127 2t c 40 ns Address setup to ALE AVLL 43 toric 40 ns Address hold after ALE f LAX 30 torc 23 ns ALE low to valid instr in fy 233 Atc c 100 ns ALE to PSEN he 58 tac 25 l ns PSEN pulse w
16. eu in a in PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid 4 One Machine Cycle One Machine Cycle gt S1 s2 s3 s4 s5 se st s2 sa s4 s5 S6 B AP y 0 p RD po PCH PCH DPH OUT OR PCH OUT OUT P2 OUT OUT DATA ARHAR H ou 08 A A A PCL OUT DPL or Ri PCL OUT valid valid valid MCD02575 Figure 4 1 External Program Memory Execution Semiconductor Group 4 3 1997 10 01 SIEMENS External Bus Interface C504 4 4 ALE Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from PO into an external latch during fetches from external memory The address byte is valid at the negative transition of ALE For that purpose ALE is activated twice every machine cycle This activation takes place even if the cycle involves no external fetch The only time no ALE pulse comes out is during an access to external data memory when RD WR signals are active The first ALE of the second cycle of a MOVX instruction is missing see figure 4 1 b Consequently in any system that does not use data memory ALE is activated at a constant rate of 1 6 of the oscillator frequency and can be used for external clocking or timing purposes The C504 allows to switch off the ALE output signal If the internal ROM is used EA 1 and ALE is switched off by EALE 0 ALE will only go acti
17. level at the reset pin for a specific time to effect a complete reset Semiconductor Group 5 1 1997 10 01 SIEMENS Reset System Reset C504 The time required for a reset operation is the oscillator start up time plus 2 machine cycles which under normal conditions must be at least 10 20 ms for a crystal oscillator This requirement is typically met using a capacitor of 4 7 to 10 uF The same considerations apply if the reset signal is generated externally figure 5 1 b In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive MCS03352 Figure 5 1 Reset Circuitries A correct reset leaves the processor in a defined state The program execution starts at location 0000 After reset is internally accomplished the port latches of ports 0 1 2 and 3 default in FFH This leaves port 0 floating since it is an open drain port when not used as data address bus All other I O port lines ports 1 to 3 output a one 1 The contents of the internal RAM and XRAM of the C504 is not affected by a reset After power up the contents are undefined while it remains unchanged during a reset if the power supply is not turned off Semiconductor Group 5 2 1997 10 01 SIEMENS Reset System Reset C504 5 2 Fast Internal Reset after Power On The C504 uses the oscillator watchdog unit for a fast internal reset procedure after power
18. logically operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 2 2 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the XTAL2 oscillator signals and the ALE address latch enable signal are shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 Executing of a one cycle instruction begins at S1P2 when the op code is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If itis a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 2 2 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C504 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory Du
19. 0 P1 0 ANO 0 0 1 P1 1 AN1 0 1 0 P1 2 AN2 0 1 1 P1 3 AN3 1 0 0 P3 2 AN4 1 0 1 P3 3 AN5 1 1 0 P3 4 AN6 1 1 1 P3 5 AN7 Semiconductor Group 6 101 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function ADCL1 A D converter clock prescaler selection ADCLO ADCL1 and ADCLO select the prescaler ratio for the A D conversion clock fapc Depending on the clock rate fosc of the C504 fapc must be adjusted in a way that the resulting conversion clock fApc is less or equal 2 MHz see section 6 5 3 The prescaler ratio is selected according the following table ADCL1 ADCLO Prescaler Ratio 0 0 divide by 4 0 1 divide by 8 default after reset 1 0 divide by 16 1 1 divide by 32 EADC Enable A D converter interrupt If EADC 0 the A D converter interrupt is disabled Note Generally before entering the power down mode an A D conversion in progress must be stopped If a single A D conversion is running it must be terminated by polling the BSY bit or waiting for the A D conversion interrupt In continuous conversion mode bit ADM must be cleared and the last A D conversion must be terminated before entering the power down mode A single A D conversion is started by writing to SFR ADDATL with dummy data A continuous conversion is started under the following conditions By setting bit ADM during a running single A D conversion By setting bit ADM when at least one A D conversion
20. 10 7 1997 10 01 SIEMENS OTP Memory Operation C504 Figure 10 5 shows a waveform example of the program read mode access for several OTP memory bytes In this example OTP memory locations 3FDy to 400y are programmed Thereafter OTP memory locations 4004 and 3FDy are read PMSELLO Z 1 Y PALE 3FD 3FE 3FF 400 3FD 400 w Joa Je F o o je Y Port 0 Data 1 Data 2 Data 3 zz Data 4 A Data 4 zz Data 1 V7 ZA ZA ZA m mL MCT03364 Figure 10 5 Typical OTP Memory Programming Verify Access Waveform Semiconductor Group 10 8 1997 10 01 SIEMENS OTP Memory Operation C504 10 6 Lock Bits Programming Read The C504 2E has two programmable lock bits which when programmed according tabie 10 3 provide four levels of protection for the on chip OTP program memory Table 10 3 Lock Bit Protection Types Lock Bits at D1 DO Protection Protection Type D1 DO Level 1 1 Level 0 The OTP lock feature is disabled During normal operation of the C504 2E the state of the EA pin is not latched on reset 1 0 Level 1 During normal operation of the C504 2E MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset An OTP memory read operation is only possible according to ROM OTP verification mode 2 Further programming of the OTP memory is disabled reprogramming security 0 1 Level 2 Same as level 1 but also
21. 9 6 62 6 65 GOTEEN rata ettet 3 10 6 57 CPU CGN c Slew ch washes horde 3 10 6 59 Accumulator 2 2 CORA 1 loe tele 3 10 6 54 BSOS o as 2 3 GULREN IAE den date deb d 3 10 6 57 Basic timing e sso dest tr eie ied 2 4 e Ca Lek rud p iLnDEd PIS 3 10 6 55 Fetch execute diagram 2 5 GUSFEN tai bd Ren 3 10 6 57 Functionality 22k RR yn 2 2 GOA eod RPIERRSIAASFRESS 3 10 6 59 Program status word 2 2 GUB Las x n An contest ert 3 10 6 54 Stack pointer llus 2 3 CO2REN 22 tado dis 3 10 6 57 CPU HB oie ad di 2 5 CCHO ie C tese is ats 3 7 3 9 6 46 6 53 CT1ICON eda 3 7 3 10 6 46 6 47 CO Lat n 3 7 3 9 6 46 6 53 OTIPOS erat Ex REEK bis 3 10 6 54 Mc m 3 7 3 9 6 46 6 53 A re te eena deney 3 10 6 54 GUIE icd 3 6 3 7 3 10 6 46 6 56 CT1OFH ois 3 7 3 10 6 46 6 50 GOIR rm E 3 7 3 10 6 46 6 54 STOP ueteres 3 7 3 10 6 46 6 50 010 0 oss qu Rx 3 7 3 9 6 46 6 53 Gl Rian diets Rin aie ae Ras 3 10 6 48 LS By s o4 oec 3 7 3 9 6 46 6 53 CTIRES ia vada 3 10 6 48 COLA iios dte 3 7 3 9 6 46 6 53 CT2CON iorum 3 7 3 9 6 62 6 63 GOPLEH aset teat 3 7 3 10 6 46 6 49 A t o c dn 3 9 6 63 CCP Lic esas 3 7 3 10 6 46 6 49 pul cp 3 9 6 64 OE Cute verse teca 3 9 3 10 6 47 6 64 GT2RES aa ecu Eu Bar un 3 9 6 64 CIT Swede gan socle a n 3 9 3 10 6 47 6 64 CTI ga A doe Rents eaten 3 10 6 47 GER js ag nie 3 9 3 10 6 47 6 64 A HEC n 2 3 3 9 OMP2H ES 3 7 3 10
22. ADM MX2 MX1 MXO 0000p D94 ADDATH 00y 9 7 6 5 4 3 2 DAy ADDATL 00XX XXXXp DCH ADCON1 01XX ADCL1 ADCLO MX2 MX1 MXO X000p DEW CCPL 00H 6 5 4 d 2 1 0 DFy CCPH 00H 6 5 4 3 2 1 0 E0y ACC 00H E 6 5 4 2d 2 A 0 Ely CTICON 0001 CTM ETRP STE1 CT1 CT1R CLK2 CLK1 CLKO 0000p RES E24 COINI FFH COUT COUT COUT CC2I COUT CC11 COUT CCOl 3l XI 2l 11 Ol E34 CMSELO 00y CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 E44 OMSEL1 00H ESMC NMCS 0 0 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 E54 CCIR 00H CT1FP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR E64 CT1OFL 00H 7 6 5 4 3 2 1 0 E7y CT1OFH 00y 7 6 5 4 3 2 1 0 FOH B 00H 7 6 5 4 2d 2 1 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers Semiconductor Group 3 10 1997 10 01 SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset FCH VRO C5H 1 1 0 0 0 1 0 1 3 4 FDy VR1 044 0 0 0 0 0 1 0 0 3 4 84y 5 7 FEH VR2 6 Y 6 5 4 3 2 1 0 3 4 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SF
23. CCLO 00y 7 6 5 4 3 2 1 0 C34 CCHO 00H uh 6 5 4 3 2 1 0 C44 CCL1 00y d 6 5 4 3 2 al 0 C54 CCH1 00y 7 6 5 4 3 2 4 0 C6H CCL2 00H Y 6 5 4 3 2 1 0 C74 CCH2 00y 7 6 5 4 3 2 1 0 C8y T2CON 00y TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 C94 T2MOD XXXX DCEN XXX0p CAy RC2L 00y 7 6 5 4 id 2 1 0 CBH RC2H 00y 7 6 5 4 3 2 H 0 CC TL2 00H E 6 5 4 3 2 1 0 CDy TH2 004 d 6 5 4 3 2 1 0 CFy TRCON 00y TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TRENO DOW PSW 00H CY AC FO RS1 RSO OV F1 P D24 CP2L 00y E 6 5 4 3 2 E 0 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 10 01 SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset D3y CP2H XXXX 1 0 XX00p D44 CMP2L 00H v 6 5 4 3 2 1 D5j CMP2H XXXX 1 XX00p D6y CCIE 00H ECTP ECTC CC2 CC2 CC1 CC1 CCO CCO FEN REN FEN REN FEN REN D74 BCON 00H BCMP PWM1 PWMO EBCE BCERR BCEN BCM1 BCMO BCEM D8y ADCONO XX00 ADC BSY
24. CT10FH CT1OFL offset registers MCTO2602 Compare Timer 1 with Offset not equal 0 Mode 0 Semiconductor Group 6 38 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 3 CAPCOM Unit Operating Mode 1 Using compare timer 1 in operating mode 1 two symmetric output signals with constant dead time torr at each signal transition can be generated per channel Figure 6 23 shows the operating mode 1 timing in detail Count Value CT1 CT10FF A CCP 7 Period Reg CT10F 2 Offset Reg Start of CT1 wm CCx CC 5 COIN Bit 0 COUTx CC 5 COINI Bit 0 COUTx CC 5 COINI Bit 1 2s CC content of the CCxH CCxL compare registers CCP content of the CCPH CCPL period register CT10F content of the CTIOFH CT1OFL offset registers MCTO2603 Figure 6 23 Compare Timer 1 with Offset 0 Dead Time Mode 1 In the example above compare timer 1 counts from 0000y up to 00074 value stored in period register CCPH CCPL and then counts down again to 00004 The maximum and minimum 0000H values of the compare timer 1 occur always once in the count value sequence In the example shown in figure 6 23 the offset registers have a value of 00024 With the programming of the CMSEL1 or CMSELO registers all affected compare outputs are switched to push pull mode and start driving an initial level whic
25. Chapter 3 4 XRAM Operation moved from chapter 4 to chapter 3 3 11 Version register information added 3 85 2 5 1 Figure 5 2 Reset Circuitries added 4 6 to 4 8 4 8to 4 10 Chapter 4 6 4 7 ROM Protection enhanced for OTP verification 5 4 5 3 Figure 5 3 5 2 corrected 5 6 5 7 Chapter 5 4 Oscillator and Clock Circuit added 6 7 6 7 Figure 6 5 corrected modified sentence During this time the P2 SFR remains unchanged while the PO SFR has 1 s written to it 6 8 Figure 6 6 added 6 8 6 9 Figure 6 6 6 7 corrected also text in paragraph The pullup FET p1 of 2nd sentence modified activated for one state 6 14 6 13 Figure 6 11 6 10 corrected 6 18 Timer 0 1 count register definitions added 6 26 Timer 2 count and reload capture register definitions added 6 33 6 31 Figure 6 19 corrected 6 36 6 34 Figure 6 21 corrected 6 42 6 40 Sentence below table added 6 41 6 39 Invalid characters in formulas corrected x 6 45 6 43 Note in figure 6 26 below added 6 50 6 48 1 paragraph 2nd line or CCx and COUTx added 6 51 6 49 Description of the two new CMSEL1 bits ESMC and NMCS added 6 52 6 50 CMSEL table upper 4 lines or analog input pins deleted see note 6 58 6 56 Paragraph with active passive state definition moved from 6 70 6 68 6 70 6 68 Text in last but one paragraph modified Ch 6 3 4 Ch 6 3 4 New wording 4 phase multi channel PWM mode instead o
26. Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON E RSYSCON TCON RTCON TCON RTCON Enhanced Hooks Interface Circuit Optional m 1 0 Ports Port3 Port 1 RPort2 RPort0Q TEA TALE TPSEN Target System Interface MCS02647 Figure 4 2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C500 MCU Semiconductor Group 4 5 1997 10 01 SIEMENS External Bus Interface C504 4 6 ROM OTP Protection for C504 2R C504 2E The C504 2R ROM version allows to protect the
27. Internal Bus MCS02105 Figure 6 38a Serial Interface Mode 2 and 3 Functional Diagram Semiconductor Group 6 96 1997 10 01 SIEMENS On Chip Peripheral Components C504 Transmit MCT02587 a n n aw Nm Do 9 Zs gt Write to SBUF Bit Detector Sample Times Receive Stop Bit Gen Figure 6 38b Serial Interface Mode 2 and 3 Timing Diagram Semiconductor Group 6 97 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 10 bit A D Converter The C504 includes a high performance high speed 10 bit A D Converter ADC with 8 analog input channels It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors The A D converter provides the following features 8 multiplexed input channels port 1 3 which can also be used as digital outputs inputs 10 bit resolution Single or continuous conversion mode Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built in hidden calibration of offset and linearity errors The externally applied reference voltage range has to be held on a fixed value within the specifications The main functional blocks of the A D converter are shown in figure 6 39 6 5 1 A D Converter Operation An internal start of a single A D conversion is triggered by a write to
28. Introduction C504 1 1 Pin Configuration This section describes the pin configration of the C504 in the P MQFP 44 package 33 32 31 30 29 28 27 26 25 24 23 P0 3 AD3 34 P0 2 AD2 35 P0 1 AD1 36 P0 0 ADO 37 V AREF 38 C504 LM VGND 39 C504 2RM P1 0 ANO T2 40 C504 2EM P1 1 AN1 T2EX 41 P1 2 AN2 CCO 42 P1 3 AN3 COUTO 43 P1 4 CC1 40 12 P1 5 COUT1 P1 6 CC2 P1 7 COUT2 Figure 1 3 Pin Configuration top view Semiconductor Group 1 4 P3 1 TxD P3 2 AN4 INTO P3 3 AN5 INT1 P3 4 ANG TO P3 5 AN7 T1 P24 A12 P2 3 A11 P2 2 M0 P2 1 A9 P2 0 A8 Voc Vss XTAL1 XTAL2 P3 7 RD P3 6 WR INT2 MCP02532 1997 10 01 SIEMENS Introduction C504 1 2 Pin Definitions and Functions This section describes all external signals of the C504 with its function Table 1 1 Pin Definitions and Functions Symbol Pin Number l O Function P MQFP 44 P1 0 P1 7 40 44 O Port 1 1 3 is an 8 bit bidirectional port Port pins can be used for digital input output P1 0 P1 3 can also be used as analog inputs of the A D converter As secondary digital functions port 1 contains the timer 2 pins and the capture compare inputs outputs Port 1 pins are assigned to b
29. OTP memory read operation using ROM verification mode 2 is disabled 0 0 Level 3 Same as level 2 but additionally external code execution by setting EA low during normal operation of the C504 2E is no more possible External code execution which is initiated by an internal program e g by an internal jump instruction above the ROM boundary is still possible Note A 1 means that the lock bit is unprogrammed 0 means that lock bit is programmed For a OTP verify operation at protection level 1 the C504 2E must be put into the ROM verification mode 2 If a device is programmed with protection level 2 or 3 it is no more possible to verify the OTP content of a customer rejected FAR OTP device When a protection level has been activated by programming of the lock bits the basic programming mode must be left for activation of the protection mechanisms This means after the activation of a protection level further OTP program verify operations are still possible if the basic programming mode is maintained The state of the lock bits can always be read if protection level 0 is selected If protection level 1 to 3 has been programmed and the programming mode has been left it is no more possible to enter the programming mode In this case also the lock bits cannot be read anymore Figure 10 6 shows the waveform of a lock bit write read access For a simple drawing the PROG pulse is shortened In reality for lock bit pr
30. Output Control Compare Registers COUTXI CMP2H CMP2L COINI 6 Pulse fsc Programmable Prescaler fT Period Registers De COUTSI 10 Bit Up Counter CP2H CP2L P COINI 7 Control Register CT2CON CT2 Value A gya NS of N CP2H CP2L CMP2H CMP2L Stat of CT2 4 COUT3 COUT3I 0 COUT3 COUT3I 1 MCT02607 Figure 6 27 COMP Unit Block Diagram and Pulse Generation Scheme The COMP unit has a 10 bit up counter compare timer 2 CT2 which starts counting from 000y up to the value stored in the period register and then is again reset This compare timer 2 operation is equal to the operating mode 0 of compare timer 1 When the count value of CT2 matches the value Semiconductor Group 6 61 1997 10 01 SIEMENS On Chip Peripheral Components C504 stored in the compare registers CMP2H CMP2L COUTS toggles its logic state When compare timer 2 is reset to 0004 COUTS toggles again its logic state COUTS is only an output pin After a reset operation COUTS drives a high level as defined by the reset value 21 of bit COUTS of SFR COINI When compare timer 2 is running bit CT2R in SFR CT2CON is set bit ECT2O in SFR CT2CON allows the disconnection of COUTS from compare timer 2 signal generation In this case the logic value of COUTSI bit COINI 7 is put to the COUT3 output When ECT2O is set thereafter the compare timer 2 output signal is again switched to the COUTS output In
31. PSEN EA Wu RESET MCTO2594 Figure 4 4 ROM Verification Mode 2 ROM OTP verification mode 2 is selected if the inputs PSEN EA and ALE are put to the specified logic levels With RESET going inactive the ROM OTP verification mode 2 sequence is started The C504 outputs an ALE signal with a period of 12 foc and expects data bytes at port 0 The data bytes at port 0 are assigned to the ROM addresses in the following way 1 Data Byte content of internal ROM OTP address 00004 2 Data Byte content of internal ROM OTP address 0001 y 3 Data Byte content of internal ROM OTP address 00024 16 Data Byte content of internal ROM OTP address 000FH The C504 does not output any address information during the ROM OTP verification mode 2 The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the falling edge of RESET With each following ALE pulse the ROM OTP address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally Semiconductor Group 4 7 1997 10 01 SIEMENS External Bus Interface C504 Between two ALE pulses the data at port 0 is latched at 6 foc after ALE rising edge and compared internally with the ROM OTP content of the actual address If an verify error is detected the error condition is stored internally After each 16th data byte the cumulated verify result pass or
32. Period Registers The compare timer 1 period registers CCPH and CCPL store the 16 bit value for the compare timer 1 count period CCPH holds the high byte of the 16 bit period value and CCPL holds the low byte If CCPH CCPL is written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 0000 operating mode 1 When the compare timer 1 period registers are read always shadow latches are accessed Special Function Register CCPL Address DE Reset Value 00y Special Function Register CCPH Address DF Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 DEH Y 6 5 4 3 2 1 LSB CCPL DFH MSB 6 5 4 3 e 0 CCPH Bit Function CCPL 7 0 Compare timer 1 period value low byte The 8 bit value in the CCPL register is the low byte of the 16 bit period value of compare timer 1 shadow latch CCPH 7 0 Compare timer 1 period value high byte The 8 bit value in the CCPH register is the high byte of the 16 bit period value of compare timer 1 Shadow latch Semiconductor Group 6 49 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Timer 1 Offset Registers The CT1OFH and CT1OFL registers contain the value for the compare timer 1 CT1OFH holds the high byte of the 16 bit offset value and CT1OFL holds the low byte For the dete
33. RI must be cleared by software Semiconductor Group 6 84 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 3 Baud Rates There are several possibilities to generate the baud rate clock for the serial interface depending on the mode in which it is operated To clearify the terminology something should be said about the differences between baud rate clock and baud rate The serial interface requires a clock rate which is 16 times the baud rate for the internal synchronization Therefore the baud rate generators have to provide a baud rate clock to the serial interface which there divided by 16 results in the actual baud rate However all formulas given in the following section are already include the factor and calculate the final baud rate The baud rate generation is further controlled by bit SMOD which is located in SFR PCON Special Function Register PCON Address 87g Reset Value 000X0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS Geil GFO PDE IDLE PCON The functions of the shaded bits are not described in this section Symbol Function SMOD Baud rate double bit When set the baud rate of the serial channel in mode 1 2 3 is doubled Mode 0 The baud rate in mode 0 is fixed Mode 0 baud rate oscillator frequency 12 fosc 12 Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON 8
34. Reg with Count 4 CCx Reg 1 Value Start of CT CCx Reg 1 CCP 2 _ min 200 ns 40 MHz clock rate MCTO2604 Figure 6 24 Maximum Period and Resolution of the Compare Timer 1 Unit Semiconductor Group 6 40 1997 10 01 SIEMENS On Chip Peripheral Components C504 Table 6 5 shows the resolution and the period value range which depend on the selected compare timer 1 input clock prescaler ratio Table 6 5 Resolution and Period of the Compare Timer 1 at fosc 40 MHz Compare Operating Mode 0 Operating Mode 1 Timer Resolution Period Resolution Period Input Clock fosc 2 50 ns 100ns 3 28 ms 50 ns 200 ns 6 55 ms fosc 4 100 ns 200 ns 6 55 ms 100 ns 400 ns 13 11 ms fosc 8 200 ns 400 ns 13 11 ms 200 ns 800 ns 26 21 ms fosc 16 400 ns 800 ns 26 21 ms 400 ns 1 6 us 52 43 ms fosc 32 800 ns 1 6 us 52 43 ms 800 ns 3 2 us 104 86 ms fosc 64 1 6 us 3 2 us 104 86 ms 1 6 us 6 4 us 209 71 ms fosc 128 3 2 us 6 4 us 209 72 ms 3 2 us 12 8 us 419 42 ms fosc 256 6 4 us 12 8 us 419 43 ms 6 4 us 25 6 us 838 85 ms Compare timer 1 period and duty cycle values can be calculated using the formulas below In these formulas the following abbreviations are used pv period value stored in the period registers CCPH CCPL ov Offset value stored in the offset registers CT1T OFH CT1OFL cv compare value stored in the capture compare registers CCHx
35. Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IENO IEN1 Register IENO also contains the global disable bit EA which can be cleared to disable all interrupts at once Some interrupts sources have further enable bits e g EXEN2 ECTR etc Such interrupt enable bits are controlled by specific bits in the SFRs of the corresponding peripheral units described in chapter 6 The IENO register contains the general enable disable flags of the external interrupts O and 1 the timer interrupts the USART interrupt and the AD converter interrupt The external interrupt 2 and the four interrupts of the CCU are enabled disabled by bits in the IEN1 register After reset the enable bits of IEO and IE1 are set to 0 That means that the corresponding interrupts are disabled Special Function Registers IENO Address A814 Reset Value 0X000000p Bit No MSB LSB AFH AEH ADH ACH ABH AAH A9H A8H A8H EA ET2 ES ET1 EX1 ETO EX0 IENO Bit Function EA Disables all Interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit Reserved bits for future use ET2 Timer 2 interrupt enable If ET2 1 the Timer 2 interrupt is enabled ES Serial channel interrupt enable If ES 1 the Serial C
36. SIEMENS Index C504 12 Index Note Bold page numbers refer to the main definition Dios antena qq re 2 3 3 6 3 10 part of SFRs or SFR bits Basic CPU timing sux ena sn 2 4 A BOEM ss danen e 3 10 6 68 A D converter o u eagen POENA esas ERE AREER 3 10 6 09 Analog input pin selection 6 109 EGER os sehe uaa penas 3 10 6 69 Block diagram 25 22 0L 6 99 BCMO 0 nn 3 10 6 69 Calibration mechanisms 6 108 BOM1 seen 6 e 3 10 6 69 Clock selection 6 103 BONE rs 910 6768 Conversion timing 6 104 to 6 107 BCON E eng 37 310 6 68 Conversion time calculation 6 106 Block A 2 1 A E A ope o a Gol Bh te Sort as 3 10 6 101 System clock relationship 6 105 General operation 6 98 oe re 3 8 6 20 Registers 6 100 to 6 102 GIA Aedes nay oe a Dados 3 9 6 27 A D converter characteristics 11 6 to 11 7 Capture compare unit CCU 6 32 to 6 81 Absolute maximum ratings 11 1 1 channel COMP unit 6 61 to 6 66 AC eraa dies aue qan ated 2 3 3 9 Block diagram 6 61 AC characteristics Pulse generation 6 61 12 MHz timing 11 8 to 11 9 Registers 6 62 to 6 66 24 MHz timing 11 10 to 11 11 Compare registers 6 66 40 MHztiming 11 12 to 11 13 CT2 control register 6 63 Data memory read cycle 11 14 Period registers 6 65 Data memory wri
37. SIEMENS Power Saving Modes C504 9 1 Idle Mode In the idle mode the oscillator of the C504 continues to run but the CPU is gated off from the clock signal However the interrupt system the serial port the A D converter and all timers with the exception of the watchdog timer are further provided with the clock The CPU status is preserved in its entirety the stack pointer program counter program status word accumulator and all other registers maintain their data during idle mode The reduction of power consumption which can be achieved by this feature depends on the number of peripherals running If all timers are stopped and the A D converter and the serial interface are not running the maximum power reduction can be achieved This state is also the test condition for the idle mode Zec So the user has to take care which peripheral should continue to run and which has to be stopped during idle mode Also the state of all port pins either the pins controlled by their latches or controlled by their secondary functions depends on the status of the controller when entering idle mode Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on This applies to the serial interface in case it cannot finish reception or transmission during normal operation Th
38. TERO rana Semester ete re 3 8 6 19 Fle ie enue Ai ECL uw 3 8 6 84 TET e hari ee eh owe a wane 3 8 6 19 RMAP oru pebebh teda us 3 5 3 9 WESS obs edd vovv de oes 3 9 6 27 ROM OTP protection 4 6 A See don ae ete a oe 3 6 3 8 6 18 Protected ROM verification example 4 8 TET d Ra ttm 3 6 3 8 6 18 Protected ROM verifiy timimg 4 7 Til a tad 3 7 3 9 6 26 Protected ROM OTP mode 4 7 A AN 3 8 6 84 Unprotected ROM mode 4 6 Timer counter 6 17 to 6 31 Unprotected ROM verifiy timimg 4 6 Timer counter OD and 1 6 17 to 6 24 A A dea e odio aeta 2 3 3 9 Mode 0 13 bit timer counter 6 21 RSI xen io nie 2 3 3 9 Mode 1 16 bit timer counter 6 22 EX Lose ee tob Seb ie eddy ee 3 9 Mode 2 8 bit rel timer counter 6 23 Mode 3 two 8 bit timer counter 6 24 SBUE E ais ieee pete aa 3 6 3 8 6 84 Registers 6 18 to 6 20 GOON ECOUTER 3 6 3 8 6 84 Timer counter 2 6 25 to 6 31 Serial interface USART 6 82 to 6 97 16 bit auto reload mode 6 28 to 6 30 Baudrate generation 6 85 to 6 88 16 bit capture mode 6 31 with timer lacio alt 6 86 Operating modes 6 25 with timer seves odas 6 87 Registers 6 26 to 6 28 Multiprocessor communication 6 83 Timings Operating mode 0 6 89 to 6 91 Data memory read cycle 11 14 Operating mode 1 6 92 to 6 94 Data memory write cycle
39. Table 6 13 Timer 1 Generated Commonly Used Baud Rates Baud Rate Josce SMOD Timer 1 C T Mode Reload Value Mode 0 max 1 MHz 12 MHz X X X X Mode 2 max 375 K 12 MHz 1 X X X Modes 1 3 62 5K 12 MHz 1 0 2 FFH 19 2 K 11 059 MHz 1 0 2 FDH 9 6 K 11 059 MHz 0 0 2 FDH 4 8 K 11 059 MHz 0 0 2 FAH 2 4 K 11 059 MHz 0 0 2 Fay 1 2K 11 059 MHz 0 0 2 ESH 110 6 MHz 0 0 2 72H 110 12 MHz 0 0 1 FEEBy Semiconductor Group 6 86 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 3 2 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and or RCLK in T2CON Note then the baud rates for transmit and receive can be simultaneously different Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode as shown in figure 6 35 Timer 1 Overflow c T2 E Control P1 0 T2 Interrupt EXEN2 MCS02586 Figure 6 35 Timer 2 in Baud Rate Generator Mode The baud rate generator mode is similar to the auto reload mode in that rollover in TH2 causes the timer 2 registers to be reloaded with the 16 bit value in registers RC2H and RC2L which are preset by software Now the baud rates in modes 1 and 3 are determined by timer 2 s overflow rate as follows Modes 1 3 baud rate timer 2 overflow rate 16 Semiconductor Group 6 87 1997 10 01 SIEMENS On Chip Peripheral Components C504 The timer can be configured for either timer or counter ope
40. WR is activated and remains there until after WR is deactivated In a read cycle the incoming byte is accepted at port 0 before the read strobe is deactivated Program memory Signal PSEN functions as a read strobe External Program Memory Access The external program memory is accessed under two conditions whenever signal EA is active or whenever the program counter PC contains a number that is larger than 3FFFy This requires the ROM less version C504 L to have EA wired low to allow the lower 16K program bytes to be fetched from external memory When the CPU is executing out of external program memory all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose I O The contents of the port 2 SFR however is not affected During external program memory fetches port 2 lines output the high byte of the PC and during accesses to external data memory they output either DPH or the port 2 SFR depending on whether the external data memory access is aMOVX DPTR or a MOVX Ri Since the C504 L has no internal program memory accesses to program memory are always external and port 2 is at all times dedicated to output the high order address byte This means that port 0 and port 2 of the C504 L can never be used as general purpose I O This also applies to the C504 2R or C504 2E when they operat only with an external program memory 4 2 PSEN Program Store Enable The read strobe for external
41. active only input high state IH steady output high state SOH p2 and p3 active forced output high state FOH p1 p2 and p3 active output low state OL n1 active If a pin is used as input and a low level is applied it will be in IL state if a high level is applied it will switch to IH state If the latch is loaded with 0 the pin will be in OL state If the latch holds a 0 and is loaded with 1 the pin will enter FOH state for two cycles and then switch to SOH state If the latch holds a 1 and is reloaded with a 1 no state change will occur At the beginning of power on reset the pins will be in IL state latch is set to 1 voltage level on pin is below of the trip point of p3 Depending on the voltage level and load applied to the pin it will remain in this state or will switch to IH SOH state If itis used as output the weak pull up p2 will pull the voltage level at the pin above p3 s trip point after some time and p3 will turn on and provide a strong 1 Note however that if the load exceeds the drive capability of p2 Z1 the pin might remain in the IL state and provide a week 1 until the first O to 1 transition on the latch occurs Until this the output level might stay below the trip point of the external circuitry The same is true if a pin is used as bidirectional line and the external circuitry is switched from outpout to input when the pin is held at 0 and the load then exceeds the p2 d
42. are stopped and only the contents of the on chip RAM XRAM and the SFR s are maintained The port pins which are controlled by their port latches output the values that are held by their SFR s The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode ALE and PSEN hold at logic low level see table 9 1 The power down mode can be left either by an active reset signal or by a low signal at the INTO pin Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state Using the INTO pin for power down mode maintains the state of the SFRs which has been frozen when power down mode is entered In the power down mode of operation V can be reduced to minimize power consumption It must be ensured however that is Vec not reduced before the power down mode is invoked and that Voc is restored to its normal operating level before the power down mode is terminated 9 2 1 Invoking Power Down Mode The power down mode is entered by two consecutive instructions The first instruction has to set the flag bit PDE PCON 1 and must not set bit PDS PCON 6 the following instruction has to set the start bit PDS PCON 6 and must not set bit PDE PCON 1 The hardware ensures that a concurrent setting of both bits PDE and PDS does not initiate the power down mode Bits PDE and PDS will automatically be cleared aft
43. bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag The program control section controls the sequence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU Semiconductor Group 2 2 1997 10 01 SIEMENS Fundamental Structure C504 Special Function Register PSW Address DOj Reset Value 00y Bit No MSB LSB D7y D6y D5y D4y D3y D2y Diy DOy DOy CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RS1 Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Bank 0 selected data address 00y 07y 0 1 Bank 1 selected data address 08y 0F y 1 0 Bank 2 selecte
44. clock at the XTAL1 and XTAL2 pins The RESET signal must be active for at least one machine cycle after this time the C504 remains in its reset state as long as the signal is active When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle Then the processor starts its address output when configured for external ROM in the following state 5 phase 1 One phase later state 5 phase 2 the first falling edge at pin ALE occurs Figure 5 3 shows this timing for a configuration with EA O external program memory Thus between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles I One Machine Cycle gt S5 S6 St s2 S3 S4 S5 S6 L f Pe pipes Pek Dd Pd TD 2 S6 1 S4 5 1 S4 S2 S3 MEM OQ i E ALE MCT02092 Figure 5 3 CPU Timing after Reset Semiconductor Group 5 5 1997 10 01 SIEMENS Reset System Reset C504 5 4 Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single stage on chip inverter which can be configured with off chip components as a pierce oscillator The oscillator in any case drives the internal clock generator The clock generator provides the internal clock signals to the chip These signals define the internal phases states and machine cycle
45. compare match interrupt has a low priority PCT2 Compare timer 2 interrupt priority level If PCT2 0 the compare timer interrupt has a low priority PCEM CCU emergency interrupt priority level If PCEM 0 the CCU trap interrupt has a low priority PX2 External interrupt 2 priority level If PX2 0 the external interrupt 2 has a low priority PADC A D converter interrupt priority level If PADC 0 the A D Converter interrupt has a low priority A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence vertical and horizontal as shown in table 7 2 below If e g the external interrupt O and the A D converter interrupt have the same priority and if they are active simultaneously the external interrupt O will be serviced first Table 7 2 Interrupt Source Structure Interrupt Source Priority High Priority Low Priority External Interrupt O A D Converter High Timer 0 Interrupt External Interrupt 2 External Interr
46. control modes are supported which are either controlled by software or by hardware hall sensors 16 Bit Capture Compare Unit CAPCOM y Mode Trap Initialization TECPH ep Select Registers Registers CMSELO CMSEL1 COINI TREN Offset Register CC Channel 0 CT10FH CT1OFL CCHO CCLO Port CC Channel 1 Compare Cont colt Yos 16 Bit CC Channel 2 CcH2 coa A Prescaler Cntrl Register CT1CON 10 Bit Compare Unit COMP Period Register CP2H CP2L compare Compare Reg gt COUT3 Hen CMP2H CMP2L Prescaler Block Commutation Cntrl Register Control CT2CON BCON MCB02598 Figure 6 18 Block Diagram of the Capture Compare Unit CCU Semiconductor Group 6 32 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 1 General Capture Compare Unit Operation The compare timer 1 and 2 are free running processor clock coupled 16 bit 10 bit timers which have each a count rate with a maximum of fosc 2 up to fosc 256 The compare timer operations with its possible compare output signal waveforms are shown in figure 6 19 Compare Timer 1 Operating Mode 0 a Standard PWM Edge Aligned b Standard PWM Single Edge Aligned with programmable dead time torr Period Period Value Value Compare Compare Value Value Offset 1 0000 y COUT Compare Timer 1 Operating Mode 1 c Symetrical PWM Center Aligned d Symet
47. fetches is PSEN PSEN is not activated for internal fetches When the CPU is accessing external program memory PSEN is activated twice every cycle except during a MOVX instruction no matter whether or not the byte fetched is actually needed for the current instruction When PSEN is activated its timing is not the same as for RD A complete RD cycle including activation and deactivation of ALE and RD takes 12 oscillator periods A complete PSEN cycle including activation and deactivation of ALE and PSEN takes 6 oscillator periods The execution sequence for these two types of read cycles is shown in figure 4 1 a and b 4 3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data In the C504 the external program and data memory spaces can be combined by AND ing PSEN and RD A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory Since the PSEN cycle is faster than the RD cycle the external memory needs to be fast enough to adapt to the PSEN cycle Semiconductor Group 4 2 1997 10 01 SIEMENS External Bus Interface C504 lt One Machine Cycle One Machine Cycle gt S1 s2 s3 s4 s5 se st s2 s3 s4 S5 S6 A RD without MOVX pp PCH PCH PCH PCH PCH OUT OUT OUT OUT OUT Po OR Hot in i A
48. frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received stop bit 1 If either of these two condtions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bit goes into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for a 1 to 0 transition in RXD Semiconductor Group 6 92 1997 10 01 SIEMENS On Chip Peripheral Components C504 Internal Bus i Shift Data TX Control TI Send Serial Port Interrupt gt 16 1 to 0 RI Load Transition SBUF Detector RX Control 11 Bit gt Ew Input Shift Register 9Bits 1FF y Shit Load SBUF Read SBUF Internal Bus MCS02103 Figure 6 37a Serial Interface Mode 1 Functional Diagram Semiconductor Group 6 93 1997 10 01 SIEMENS On Chip Peripheral Components C504 Transmit MCT02104 pa o YN o oc c JI Bit Detector Sa
49. instruction float after PSEN fs 32 fac 10 Ins Address valid after PSEN texav 18 toc 5 ns Address to valid instr in tavy 148 Stoc 60 ns Address float to PSEN basen 0 0 ns Interfacing the C504 to devices with float times up to 37 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 11 10 1997 10 01 SIEMENS Device Specifications C504 AC Characteristics for C504 L24 C504 2R24 C504 2E24 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz clock Variable Clock 1 tcerc 3 5 MHz to 24 MHz min max min max RD pulse width fa RH 180 6tac 70 ns WR pulse width fwLwH 180 6tac 70 ns Address hold after ALE LLaxe 56 2tac 27 ns RD to valid data in fai pv 118 Stoic 90 Ins Data hold after RD RHDX 0 0 ns Data float after RD tRHpz 63 2tac 20 ns ALE to valid data in fiLov 200 8t 9 133 ns Address to valid data in lavov 220 9t cg 155 ns ALE to WR or RD fiw 75 175 Stoic 50 3fcerc 50 ns Address valid to WR Tavwe 67 Ateo 97 ns WR or RD high to ALE high WHLH 17 67 fac 25 tgg 25 ns Data valid to WR transition favwx 5 tac 37 l ns Data setup before WR low 170 7tore 122
50. is left when INTO goes low With INTO low the internal RC oscillator is started INTO is then latched by the RC oscillator clock signal Therefore INTO should be held at low level for at least 10 us latch phase After this delay INTO can be set again to high level if required Thereafter the oscillator watchdog unit controls the wake up procedure in its start up phase The oscillator watchdog unit starts operation as described in section 8 2 1 When the on chip oscillator clock is detected for stable nominal frequency the microcontroller further waits for a delay of typically 5 ms and then starts again with its operation initiating the power down wake up interrupt The interrupt address of the first instruction to be executed after wake up is 007By After the RETI instruction of the power down wake up interrupt routine has been executed the instruction which follows the initiating power down mode double instruction sequence will be executed The peripheral units timer 0 1 2 CCU and WDT are frozen until end of phase 4 All interrupts of the C504 are disabled from phase 2 until the end of phase 4 Other Interrupts can be first handled after the RETI instruction of the wake up interrupt routine Semiconductor Group 9 7 1997 10 01 SIEMENS OTP Memory Operation C504 10 OTP Memory Operation The C504 2E is the OTP version in the C504 microcontroller with a 16K byte one time programmable OTP program memory With the C504 2E f
51. is reset by hardware CLK2 Compare timer 1 input clock selection CLK1 The input clock for the compare timer 1 is derived from the clock rate fosc of CLKO the C504 via a programmable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function 0 0 0 Compare timer 1 input clock is fog 2 0 0 1 Compare timer 1 input clock is fosc 4 0 1 0 Compare timer 1 input clock is fosc 8 0 1 1 Compare timer 1 input clock is fosc 16 1 0 0 Compare timer 1 input clock is fosc 32 1 0 1 Compare timer 1 input clock is fosc 64 1 1 0 Compare timer 1 input clock is fosc 128 1 1 1 Compare timer 1 input clock is fosc 256 Semiconductor Group 6 47 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function CT1RES Compare timer 1 reset control CT1R Compare timer 1 run stop control These two bits control the start stop and reset function of compare timer 1 CT1RES is used to reset the compare timer and CT1R is used to start and stop the compare timer 1 The following table shows the functions of these two bits CTARES CT1R Function 0 0 Compare timer 1 is stopped and holds its value the compare outputs stay in the logic state as they are 1 0 Compare timer 1 is stopped and reset compare outputs are set to the logic state as defined in SFR COINI default after reset 0 0 gt 1 Compare timer 1 starts Before CT1R is set the first time
52. is set by hardware if the trap function is enabled TRPEN 1 and the CTRAP level becomes active low If enabled an interrupt is generated when THF is set TRF must be reset by software TREN5 0 Trap enable control bits Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are assigned to the COUTx compare outputs TRENx 0 Compare channel output provides CAPCOM output signal in trap state TRENx 1 Compare channel output is enabled to set the logic level of the compare output CCx or COUTx in the trap state to a logic state as defined by the corresponding bits of the COINI register When writing TRENO 5 bit TRF should be set to 0 Otherwise setting TRENO 5 will generate a software trap interrupt Semiconductor Group 6 60 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 3 Compare COMP Unit Operation The Capture Compare Unit CCU of the C504 also provides an 10 bit Compare Unit COMP which operates as a single channel pulse generator with a pulse width modulated output signal This output signal is available at the output pin COUT3 of the C504 In the combined multi channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx or CCx Figure 6 27 shows the block diagram and the pulse generation scheme of the COMP unit e g initial value of COUTS is set to 0 To CAPCOM
53. logic state During the up counting phase CCx will change the logic state when the compare timer value is equal to the compare register value and COUTx will change the logic state when the compare timer value plus the offset value matches the value stored in the compare register In figure 6 22 the waveforms a and b show an example for a waveform of two signals with a constant delay of their rising edge A compare register value of 3 is assumed Using inverted signal polarity SFR COINI signal c can be generated at COUTx If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register a static 1 or a static 0 depending on COINI content will be generated at COUTx see figure 6 22 d and e Therefore CCx will also stay at a static level if the compare register value is greater than the value stored in the period register Semiconductor Group 6 37 1997 10 01 SIEMENS On Chip Peripheral Components C504 Count Value CCP 7 Period Reg CTIOF 2 Offset Reg gt CT1OF CCP CT10F COUTx Figure 6 22 CC CCP CT10F CT1 CT10FF A p 0 100 content of the CCxH CCxL compare registers content of the CCPH CCPL period register content of the
54. ns Data hold after WR wHox 15 tac 27 l ns Address float after RD RLAZ 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 24 MHz min max Oscillator period feel 41 7 294 ns High time cucx 12 tore feicx ns Low time cicx 12 toro fcucx ns Rise time cicH 12 ns Fall time LoHcL 12 ns Semiconductor Group 11 11 1997 10 01 Device Specifications C504 SIEMENS 11 6 AC Characteristics for C504 L40 C504 2R40 C504 2E40 Vec 5 V 10 15 Vas 0 V T 0 to 70 C for the SAB C504 T 40 to 85 C for the SAF C504 C for port O ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz clock Variable Clock 1 terc 3 5 MHz to 40 MHz min max min max ALE pulse width fu 35 2toac 15 ns Address setup to ALE AVLL 10 toc 15 ns Address hold after ALE uLax 10 terc 15 ns ALE low to valid instr in fiy 55 Ata c 45 Ins ALE to PSEN fip 10 toro 15 ns PSEN pulse width foit 60 3tac 15 ns PSEN to valid instr in fpu 25 3tcic 50 ns Input instruction hold after PSEN xk 0 0 ns Input instruction float after PSEN EA 20 toc 5 ns Address valid after PSEN hu 20 tec 5 ns Address to valid instr in Laviv 65 5feic 60 ns
55. ns WR or RD high to ALE high twa 43 128 Wip 40 dene e407 ns Data valid to WR transition favwx 33 tac 50 l ns Data setup before WR low 433 7tore 150 ns Data hold after WR wHox 33 tac 50 l ns Address float after RD RLAZ 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 12 MHz min max Oscillator period feel 83 3 294 ns High time cHcx 20 tore feicx ns Low time feLcx 20 toto fcucx ns Rise time cicH 20 ns Fall time cucL 20 ns Semiconductor Group 11 9 1997 10 01 SIEMENS Device Specifications C504 11 5 AC Characteristics for C504 L24 C504 2R24 C504 2E24 Vec 5 V 10 15 Vas 0 V T 0 to 70 C for the SAB C504 T 40 to 85 C for the SAF C504 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Program Memory Characteristics Parameter Symbol Limit Values Unit 24 MHz clock Variable Clock T tcrc 3 5 MHz to 24 MHz min max min max ALE pulse width fu 43 2torc 40 ns Address setup to ALE AVLL 17 terc 25 ns Address hold after ALE tax 17 torc 25 ns ALE low to valid instr in fiy 80 4tg c 87 Ins ALE to PSEN Tus 22 tac 20 l ns PSEN pulse width farsn 95 3ferci 30 ns PSEN to valid instr in fpu 60 Stoic 65 ns Input instruction hold after PSEN Lay 0 0 ns Input
56. or register indirect addressing the upper 128 bytes of RAM can be accessed through register indirect addressing the special function registers are accessible through direct addressing Four 8 register banks each bank consisting of eight 8 bit multi purpose registers occupy locations 0 through 1Fy in the lower RAM area The next 16 bytes locations 204 through 2FH contain 128 directly addressable bit locations The stack can be located anywhere in the internal data memory address space and the stack depth can be expanded up to 256 bytes The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16 bit or an 8 bit address 3 3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in chapter 2 This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing With register addressing the instruction op code indicates which register is to be used For indirect addressing RO and R1 are used as pointer or index register to address internal or external memory e g MOV RO Reset initializes the
57. serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt requests The polling cycle LCALL sequence is illustrated in figure 7 3 gt lt S5P2 D al 1 Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCT01859 Figure 7 3 Interrupt Response Timing Diagram Semiconductor Group 7 10 1997 10 01 SIEMENS Interrupt System C504 Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7 3 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The hardware clears the external interrupt flags IENO and IEN1 only if they were transition activated The hardware generated LCALL pushes the contents of the program counter onto the stack but it does not save the PSW and reloads the program counter with an address that depends on the source of the interrupt being vectored
58. stops Semiconductor Group 6 20 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 1 2 Mode 0 Putting either timer counter 0 1 into mode O configures it as an 8 bit timer counter with a divide by 32 prescaler Figure 6 12 shows the mode 0 operation In this mode the timer register is configured as a 13 bit register As the count rolls over from all 1 s to all 0 s it sets the timer overflow flag TFO The overflow flag TFO then can be used to request an interrupt The counted input is enabled to the timer when TRO 1 and either Gate 0 or INTO 1 setting Gate 1 allows the timer to be controlled by external input INTO to facilitate pulse width measurements TRO is a control bit in the special function register TCON Gate is in TMOD The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Setting the run flag TRO does not clear the registers Mode 0 operation is the same for timer O as for timer 1 Substitute TRO TFO THO TLO and INTO for the corresponding timer 1 signals in figure 6 12 There are two different gate bits one for timer 1 TMOD 7 and one for timer 0 TMOD 3 C T 0 EM ero TLO THO TFO Interrupt A 5 Bits 8 Bits CT 1 P3 4 T0 Gate O P3 2 INTO Control MCS02583 Figure 6 12 Timer Counter 0 Mode 0 13 Bit Timer Counter Semiconductor Group 6 21 1997 10 01
59. the timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When timer 0 is in mode 3 timer 1 can be turned on and off by switching it out of and into its own mode 3 or can still be used by the serial channel as a baud rate generator or in fact in any application not requiring an interrupt from timer 1 itself fosc 12 y ibn TLO Interrupt e ero TFO A 8 Bits C T 1 P3 4 T0 Control P3 2 INTO MCS02096 Interrupt l 8 Bits Control Figure 6 15 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Semiconductor Group 6 24 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 2 Timer Counter 2 Timer 2 is a 16 bit timer counter which can operate as timer or counter It has three operating modes 16 bit auto reload mode up or down counting 16 bit capture mode Baudrate generator see 6 4 3 Baud Rates The modes are selected by bits in the SFR T2CON as shown in table 6 4 Table 6 4 Timer Counter 2 Operating Modes RCLK TCLK CP RL2 TR2 Mode 0 0 16 bit auto reload 16 bit capture Baud rate generator OFF O A A 0 1 1 X X X Timer 2 consists of two 8 bit registers TH2 and TL2 In the timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 1 12 of the oscillator frequency
60. the CMSEL register should be programmed enable capture compare functions 1 0 1 Compare timer 1 starts running from count value 0000y compare outputs are set to the logic state as defined in SFR COINI 0 1 0 Compare timer 1 is stopped and holds its value the compare outputs drive their actual logic state 1 1 gt 0 Compare timer 1 is stopped and reset to 0000p compare outputs are set to the logic state as defined in SFR COINI Note for capture mode Setting CT1R 0 and CT1RES 1 after a capture event will destroy the value stored in the capture register CCx Therefore CT1RES should be set to 0 in capture mode Reason if CT1R 0 and CT1RES 1 all shadow registers are transparent switched directly to the real registers Note When software power down mode is entered with CT1RES bit of SFR CT1CON set the compare timer 1 is reset after the execution of a wake up from power down mode procedure When CT1RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 1 is not reset Depending on the state of bit CT1R at power down mode entry the compare timer 1 either stops CT1R 0 or continues CT1R 1 counting after a wake up from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 48 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Timer 1
61. the combined multi channel PWM modes and in the burst mode the compare timer 2 output signal can be also switched to the CAPCOM output pins COUTO COUT1 and COUTS In these modes the polarity of the modulated output signal at COUT2 0 can be inverted by setting bit COUTXI COINI 6 6 3 3 1 COMP Registers The COMP unit has five SFRs which are listed in table 6 7 Table 6 7 Special Function Registers of the COMP Unit Unit Symbol Description Address COMP CT2CON Compare timer 2 control register C1H Compare CP2L Compare timer 2 period register low byte D2H Unit CP2H Compare timer 2 period register high byte D3y CMP2L Compare timer 2 compare register low byte D4y CMP2H Compare timer 2 compare register high byte D5y The compare timer 2 period and compare registers store a 10 bit value organized in two bytes For proper synchronization purposes these registers are not written directly Each value of a write operation to these registers is stored in shadow latches The transfer of these shadow latches into the real registers is synchronized with the compare timer 2 value 0004 and controlled by bit STE2 When the period or compare value is changed by writing the corresponding SFR the setting of bit STE2 CT2CON 5 enables the write transfer of the shadow registers into the real registers This shadow latch transfer happens when the compare timer 2 reaches the count value OOOH the next time after STE2 has been set With the automat
62. the standard port driver circuitry whereas in address output function it works similar to Port 0 circuitry Semiconductor Group 6 8 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 3 Detailed Output Driver Circuitry In fact the pullups mentioned before and included in figure 6 2 6 4 and 6 5 are pullup arrangements The differences of the port types available in the C504 is described in the next sections 6 1 3 1 Type B Port Driver Circuitry Figure 6 7 shows the output driver circuit of the type B multifunctional digital I O port lines The basic circuitry of these ports is shown in figure 6 4 The pullup arrangement of type B port lines has one n channel pulldown FET and three pullup FETs Delay 1 State Input Data Read Pin MCS03230 Figure 6 7 Driver Circuit of Type B Port Pins The pulldown FET n1 is of n channel type It is a very strong driver transistor which is capable of sinking high currents o it is only activated if a 0 is programmed to the port pin A short circuit to Vc must be avoided if the transistor is turned on since the high current might destroy the FET This also means that no 0 must be programmed into the latch of a pin that is used as inpu The pullup FET p1 is of p channel type It is activated for one state S1 if a 0 to 1 transition is programmed to the port pin i e a 1 is programmed to the p
63. the total conversion time but can be useful in applications which have voltage sources with higher input resistances for the analog inputs increased sample phase Prescaler 4 Prescaler 8 Prescaler 16 E E A E 34 4 lj pri Ispop r 1545 peat gt focs 3 5 10 20 30 40 MHz MCT02621 Figure 6 43 Minimum A D Conversion Time in Relation to System Clock Semiconductor Group 6 107 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 5 A D Converter Calibration The C504 A D converter includes hidden internal calibration mechanisms which assure a save functionality of the A D converter according to the DC characteristics The A D converter calibration is implemented in a way that a user program which executes A D conversions is not affected by its operation Further the user program has no control on the calibration mechanism The calibration itself executes two basic functions Offset calibration compensation of the offset error of the internal comparator Linearity calibration correction of the binary weighted capacitor network The A D converter calibration operates in two phases calibration after a reset operation and calibration at each A D conversion The calibration phases are controlled by a state machine in the A D converter This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM After a r
64. to 0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L respectively In addition the transition at T2EX causes bit EXF2 in SFR T2CON to be set The EXF2 bit like TF2 can generate an interrupt The capture mode is illustrated in figure 6 18 c T2 0 Control C T2 1 Overflow Timer 2 Transition Interrupt Detection Control P1 1 Mo T2EX MCT02437 Figure 6 18 Timer 2 in Capture Mode The baud rate generator mode is selected by RCLK 1 and or TCLK 1 in SFR T2CON It will be described in conjunction with the serial port Semiconductor Group 6 31 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 Capture Compare Unit CCU The Capture Compare Unit CCU of the C504 has been designed for applications which have a demand for digital signal generation and or event capturing e g pulse width modulation pulse width measuring It consists of a 16 bit 3 channel capture compare unit CAPCOM and a 10 bit 1 channel compare unit COMP In compare mode the CAPCOM unit provides two output signals per channel which can have inverted signal polarity and non overlapping pulse transitions The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals For motor control applications both units CAPCOM and COMP may generate versatile multichannel PWM signals For brushless DC motors dedicated
65. to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS If software power down mode is activated the RC oscillator and the on chip oscillator is stopped Both oscillators are again started in power down mode when a low level is detected at the INTO input pin and when bit EWPD in SFR PCON 1 is set wake up from power down mode enabled After the start up phase of the watchdog circuitry in power down mode a power down mode wake up interrupt is generated instead of an internal reset 8 2 2 Fast Internal Reset after Power On The C504 can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally the members of the 8051 family e g SAB 80C52 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the C504 the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the f
66. to high to reach the maximum accuracy ida pue Conversion Clock fjpc A D Converter Clock Prescaler Input Clock fq Conditions fapcmex lt 2MHz f 208 1 2 2tac MCS02617 MCU System Clock Prescaler fApc Rate fosc Ratio MHz 3 5 MHz 4 438 12 MHz 4 1 5 16 MHz 4 2 24 MHz 8 1 5 32 MHz 8 2 40 MHz 16 Figure 6 40 A D Converter Clock Selection The duration of an A D conversion is a multiple of the period of the f y clock signal The calculation of the A D conversion time is shown in the next section Semiconductor Group 6 103 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 4 A D Conversion Timing An A D conversion is internally started by writing into the SFR ADDATL with dummy data A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress The conversion begins with the next machine cycle and the BSY flag in SFR ADCONO will be set The A D conversion procedure is divided into three parts Sample phase ts used for sampling the analog input voltage Conversion phase tco used for the A D conversion includes calibration Write result phase twp used for writing the conversion result into the ADDAT registers The total A D conversion time is defined by tapcc which is the sum of the two phase times tg and tco The duration of the three phases of an A D conversion is specified by its spec
67. too Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged Semiconductor Group 7 11 1997 10 01 SIEMENS Interrupt System C504 7 5 External Interrupts The external interrupts 0 1 and 2 can be programmed to be level activated or transition activated by setting or clearing bit ITO IT1 or IT2 respectively in register TCON or ITCON If ITx 0 x 2 0 or 1 external interrupt x is triggered by a detected low level at the INTx pin If ITx 1 external interrupt x is edge triggered Further in edge triggered mode two bits of the ITCON register define the type of signal transition for which the external interrupt inputs are sensitive Edge triggered interrupt can be activated for an interrupt input signal at the rising edge at the falling edge or at both signal t
68. transitions in active phase at COUTx COINI Bit 1 COINI Bit 0 Compare Timer 1 Compare Timer 1 Mode 0 gt Mode 0 Compare Timer 2 Compare Timer 2 Output Signal Output Signal CCx VOTA ce EVV COUTx COUT 1 COUT VW salis COUT COUTH 0 COUT MAMMA COUTTS Active Phase MCT03358 Figure 6 30 Compare Timer 2 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 1 Semiconductor Group 6 72 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 4 3 Block Commutation PWM Mode In block commutation mode the INTO 2 inputs are sampled once each processor cycle If the input signal combination at INTO 2 changes its state the outputs CCx and COUT are set to their new state according to table 6 9 Table 6 9 Block Commutation Control Table Mode INTO INT2 CCO CC2 COUTO COUT2 BCM1 BCMO Inputs Outputs Outputs INTO INT1 INT2 CCO CC1 CC2 COUTO COUT1 COUT2 Rotate left 1 0 0 0 inactive inactive inactive inactive inactive inactive Rotate right 1 1 1 inactive inactive inactive inactive inactive inactive Rotate left 1 0 1 inactive inactive active active inactive inactive 1 0 0 inactive active inactive active inactive inactive 1 1 0 inactive active inactive inactive inactive active 0 1 0 active inactive inactive inactive inactive acti
69. 0 6 101 EU ooa Pour POS A ice e 3 8 9 1 Emulation CONCept 4 5 Di rd DEA EMEN 3 8 9 1 EE SOUS O Led 3 8 7 14 Bo MOb ee MS Sas A gn Tene eo 3 8 7 14 BNO seo fa ecient acl ed nr MEE Re TE A 3 8 7 14 zi MEN 3 8 7 5 ENG eerie eT 3 6 3 8 7 5 eee oes EE 3 8 7 5 EN 3 6 3 8 6 101 7 6 PIRR E SAT INTOS E A 3 9 E ino irs DERE ie SRM ANTI 551 tesetuneter tei 3 9 En chon te peso sepsis ise Interrupt system 7 1 to 7 15 A eats 3 8 7 5 dame etnia ode 7 2 7 3 EXA C OE A 350 158 Entry sequence timing 7 10 Execution of instructions 2 4 External Interrupts 7 12 EXENA cuate debe cura adi Ak 3 9 6 27 EGGellevel OIN eso ses 2 3 zd UNI E E 3 9 AT Interrupt detection 7 13 External bus interface 4 1 to 4 4 ITCON register 7 14 ALE signal A PARIETE of General structure 7 4 ALE switch off control 4 4 Handling procedure 7 10 Overlapping of data program memory 4 2 Priority within level structure 7 8 Program memory access 4 2 HOdlSIOIS aire rss ia 7 5 to 7 8 Program data memory timing 4 3 Enable registers 75 1 PSEN signal ac oett cd ea 4 2 Priority registers 17 78 POGONE daa as Request flagS 7 9 F Response time 7 15 KERE 2 3 3 9 Sources and vector addresses 7 4 E Sese aw E Sacks 2 3 3 9 IOS vous OA 3 6 3 9 7
70. 0 25 Internal resistance of Rie ts 500 kQ fsin ns 99 analog source 0 25 ADC input capacitance Can 50 pF 6 Notes see next page Clock calculation table ClockPrescaler ADCL1 0 tapc ts tapcc Ratio 32 1 1 S2Xtin 64XtiN 384 x tin 16 1 0 16Xtiy 32Xxty 192 x tj 8 Oo 1 8 X tin 16xtm 96X thy 4 0 0 4 X tin 8 X tin 48 X tin Further timing conditions tapc min 500 ns tin 2 fosc 2 teLcL Semiconductor Group 11 6 1997 10 01 SIEMENS Device Specifications C504 Notes 1 e g 6 Vain May exceed Vacno OF Varer up to the absolute maximum ratings However the conversion result in these cases will be X000y or X3FFy respectively During the sample time the input capacitance Can can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach their final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result This parameter includes the sample time ts the time for determining the digital result and the time for the calibration Values for the conversion clock t4pc depend on programming and can be taken from the table on the previous page Tyg is tested at Varer 5 0 V Vagnp 0 V Voc 4 9 V It is guaranteed by design characterization for all other voltages within the defined voltage range
71. 0H Y 6 5 4 3 2 A 8BH TL1 00H Y 6 5 4 3 2 1 8Cy ITHO 00H 7 6 5 4 3 2 al 8Dy THI 004 7 6 5 4 3 2 1 9042 Pi FFH i 6 5 4 E 2 T2EX T2 90429 P1ANA XXXX EAN3 EAN2 EAN1 EANO 1111p 984 SCON 00H SMO SM1 SM2 REN TB8 RB8 TI RI 99 SBUF XXy 7 6 S 4 3 2 1 0 9Ay ITCON 0010 IT2 IE2 IZETF 2ETR METF METR IOETF IOETR 1010p A0 P2 EE 6 i5 4 3 2 1 0 A84 IENO 0X00 EA E ES Emi EX1 ETO EXO 0000p A94 IEN1 XX00 ECT1 ECCM ECT2 ECEM EX2 EADC 0000p 1 X means that the value is undefined and the location is reserved 2 Bit addressable special function registers 3 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 10 01 SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses cont d Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 after Reset BOW P3 FFy RD WR T1 TO INT1 INTO TxD RxD BOy P3ANA XX11 EAN7 EAN6 EAN5 EAN4 11XXp Bi SYSCON XX10 EALE RMAP XMAP XXX0p B84 IPO XX00 PT2 PS PT1 PX1 PTO PXO 0000p B9y IP1 XX00 PCT1 PCCM PCT2 PCEM PX2 PADC 0000p COW WDCON XXXX OWDS WDTS WDT SWDT 0000p Ciy CT2ZCON 0001 CT2P ECT2O STE2 CT2 CT2R CLK2 CLK1 CLKO 0000p RES C24
72. 1 Channel 0 Bit Function COUTSI COUTS initial logic level This bit defines the initial logic state of the output COUT3 before compare timer 2 is started the first time Further COUTSI defines the logic state of output COUT3 when bit ECT2O CT2CON 6 is reset COUTS3 disabled COUTXI Compare timer 1 output signal inversion in burst and block commutation When COUTXI is set the output signal of compare timer 2 which is wired to the compare outputs COUTx x 0 2 in burst or block commutation mode is inverted Semiconductor Group 6 58 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function CCxl COUTxI Compare output initial value compare output level in trap condition x 0 2 Bits at even bit positions 0 2 4 are assigned to the CCx compare outputs Bits at odd bit positions 1 3 5 are assigned to the COUTx compare outputs CCxl COUTxI 2 0 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts driving an initial value of O when this CCx COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSELO CMSEL1 registers If the compare timer runs and a bit of register TREN is set a compare channel output will be switched to 0 level in trap state CCxl COUTxI 1 If compare timer 1 is not running after reset an output CCx COUTx x 0 2 is switched into push pull mode and starts drivi
73. 1 can be used for PWM signal generation compare mode in order to modulate the outputs It can be further used for example for timer based interrupt generation The waveforms of a PWM output signal in the multi channel PWM modes can be selected as shown in figure 6 29 static low or high during active phase or as shown in figure 6 30 compare timer 2 controlled modulation during active phase Figure 6 35 shows for the 5 pole PWM timing the possible waveforms of the active phase when the software controlled state switching in the multi channel PWM modes is selected 5 Phase Multi Channel PWM Mode Rotate Left Mode BCM1 0 1 0 with COINI XX111111p Bit 1 Setting Bit NMCS NMCS 0 by software cco COUT1 CC2 COUTO COUT2 7 State No Static level during active phase Compare timer 2 modulation at CCx and COUTx outputs during active phase at CCx and COUTx output Active Phase MCT03359 Figure 6 35 Software Controlled State Switching in 5 Phase Multi Channel PWM Mode Semiconductor Group 6 80 1997 10 01 SIEMENS On Chip Peripheral Components C504 Static level during active phase When bit ESMC in SFR CMSEL1 is set static active or passive output levels during the active phase of a multi phase PWM timing are generated when the following conditions are met The 16 bit offset register of compare timer 1 must be 00004 CT1OFH CT1OFL 00 static active compare values 0000
74. 10 01 SIEMENS On Chip Peripheral Components C504 a Trap Function in CAPCOM Operating Mode 0 Period CT1 CT10FF Value Compare r Value CTI Offset p CCx Yj Trap ate YY COUTx Wi Trap State to CTRAP b Trap Function in CAPCOM Operating Mode 1 Period CT1 CT1OFF Value Compare Value Offset P VIA to MCT02606 Note The state of the CCx and COUTx signals in trap state is defined by the corresponding bits in COINI Figure 6 26 Trap Function of the CAPCOM Unit Semiconductor Group 6 45 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 8 CAPCOM Registers The CAPCOM unit of the C504 contains several special function registers Table 6 6 gives an overview of the CAPCOM related registers Table 6 6 Special Function Registers of the CAPCOM Unit Unit Symbol Description Address CAPCOM CT1CON Compare timer 1 control register Ely Capture CCPL Compare timer 1 period register low byte DEH Compare CCPH Compare timer 1 period register high byte DFH Unit CT1OFL Compare timer 1 offset register low byte E6y CT1OFH Compare timer 1 offset register high byte E7y CMSELO Capture compare mode select register 0 E3y CMSEL1 Capture compare mode select register 1 E4y CCLO Capture compare register 0 low byte C2H CCHO Capture compare register 0 high byte C3y CCL1 Capture compare register 1 low byte C4y CCH 1 C
75. 12 External clock source 5 7 Output input sample timing 6 14 On chip oscillator circuitry Rer tat ae dee feel tort e 5 7 Read modify write operation ots 6 16 Recommended oscillator circuit 5 6 11 22 Types and structures 6 1 Oscillator watchdog 8 5 to 8 7 Port O circuitIy o 6 5 Block diagraM ooooooocccooo 8 6 Port 1 3 circuitry o eee 6 6 Fast power on reset 8 7 Port 2 circuitry 0 6 7 OTP memory of the C504 2E 10 1 to 10 12 Standard I O port circuitry 6 3 to 6 4 Access mode selection 10 6 Power saving modes 9 1 to 9 7 Basic mode selection 10 5 Behaviour of external pins 9 3 Lock bitaccess 10 9 Idle mode 9 3 to 9 4 OTP memory protection levels 10 9 Power down mode 9 5 to 9 7 Pin configuration usu aee 10 2 Entering oc merecen ird 9 5 Pin definitions and functions 10 3 10 4 External wake up timing 9 6 Program read operation 10 7 10 8 Functionality secre ulate rare aye aie 9 5 Programming mode 10 1 Termination bea 9 6 Version byte access 10 11 Register PCON 9 1 OM surcos ia aia au 2 3 3 9 Register PCON1 9 2 OWDS 2 eee eee ee 3 9 8 2 Program memory 0000 3 2 Ou siataceud O 3 9 7 7 Pesaran ates ew eee ee 2 3 3 9 PSEN SIGNAL pica ori 4 2 A Bibaeds ok Bis 3 6 3 8 6 5
76. 30 35 MHz 40 fosc Figure 11 1 ICC Diagram Semiconductor Group 11 4 1997 10 01 SIEMENS Device Specifications C504 Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode C504 2R Toc yp 0 98 X fosc 4 3 9 C504 2bE Toc yp 0 63 X fosc 4 5 75 Toc max 0 85 X fosc 4 7 5 Idle mode C504 2R Toe typ 0 51 X fosc 2 35 C504 2E Loop 0 24 x foso 6 5 Toc max 0 30 X fosc 8 86 Note fosc is the oscillator frequency in MHz Icc values are given in mA Semiconductor Group 11 5 1997 10 01 SIEMENS Device Specifications C504 11 3 A D Converter Characteristics Vcc 5 V 10 15 96 Vss 0 V T 0 to 70 C for the SAB C504 Vss 0 1 V lt Vacuno S Vss 0 2 V T 40 to 110 C for the SAH C504 T 40 to 125 C for the SAK C504 Parameter Symbol Limit Values Unit Test Condition min max Analog input voltage Van Viano Vanes V P Sample time ts 64X fp ns Prescaler 32 32 X tn Prescaler 16 16 X f Prescaler 8 8 X fy Prescaler 4 Conversion cycle time tapec 384 X ty ns Prescaler 32 192 X tin Prescaler 16 96 X tn Prescaler 8 48 X tin Prescaler 4 3 Total unadjusted error Tue 2 LSB Vgg 0 5V lt Vin Vcc 0 5V 4 4 LSB Vss lt Vin lt Vss 0 5V Voc 0 5V lt Vin lt Voc 4 Internal resistance of M fapc 250 kQ tape in ns 99 reference voltage source
77. 40 5 V 11 RESET and CTRAP 0 9 Input high voltage to XTAL1 Vim 0 7 Voc Voo 0 5 IV Input high voltage to RESET and Vo 0 6 Voc Voc 0 5 IV CTRAP Output low voltage ports 1 2 3 Vor 0 45 V To 1 6 mA COUT3 Output low voltage port 0 ALE Vo 0 45 V Ig 3 2 mA PSEN Output high voltage ports 1 2 3 Vo 2 4 V Toy 80 uA 0 9 Voc Tou 10 uA Output high voltage ports 1 3 pins Vou 0 9 Voc V Tou 800 uA in push pull mode and COUT3 Output high voltage port 0 in Vouz 2 4 V Toy 800 LA 2 external bus mode ALE PSEN 0 9 Voc low 80 uA Logic 0 input current ports 1 2 3 Ji 10 50 uA Vin 0 45 V Logical 1 to 0 transition current IH 65 650 uA Vn 2V ports 1 2 3 Input leakage current port 0 EA J 1 uA 0 45 lt Vn lt Voc Pin capacitance Cio 10 pF f 1 MHz Ta 25 C Overload current Tov 5 mA 7 8 Programming voltage C504 2E Vpp 10 9 12 1 V 11 5 V 595 19 Notes see next page Semiconductor Group 11 2 1997 10 01 SIEMENS Device Specifications C504 Power Supply Current Parameter Symbol Limit Values Unit Test Condition typ max Active mode C504 2R 24 MHz cc 27 4 35 9 mA 40 MHz Ieg 43 1 57 2 mA C504 2E 24 MHz Ic 20 9 279 mA 40 MHz Ice 31 0 415 IMA Idle mode C504 2R 24 MHz Joc 14 6 193 mA 5 40 MHz Ic 22 4 31 3 mA C504 2E 24 MHz J Joc 12 3 16 1 mA 40
78. 5 7 3 2 Interrupt Priority Registers llle 7 7 7 3 3 Interrupt Request Flags ss ica ee ed ood ER EpL Id ER were bate eee ee 7 9 7 4 How Interrupts are Hafidled iussu o E de Reedy Peeewky ss 7 10 7 5 External Interf ple cua ert O wee ee ae ERR ORAN ING 7 12 7 6 Interrupt Response Time uo eee E hr Peewee en tee UE e E ad 7 15 8 Fall Sate Mechanisms er c os Eau e ee ee ee a keep dus 8 1 8 1 Programmable Watchdog Timer asses ese sk REX UR UE EREXGASES 8 1 8 1 1 Refreshing the Watchdog Timer 0000 c eee eee ee 8 4 8 1 2 Watchdog Reset and Watchdog Status Flag WDTS 2 005 8 4 8 2 Oscillator Watchdog Unit aon oo daa Rak Piet OS whee da EP YI 8 5 8 2 1 Detailed Description of the Oscillator Watchdog Unit 04 8 6 8 2 2 Fast Internal Reset after Power On 0000 cents 8 7 9 Power Saving Modes Lui feed ee lid a 9 1 9 1 PP O 9 3 9 2 Power Down M d iey ss xac arn AEE REE DEERE EEDE ETA ed 9 5 9 2 1 Invoking Power Down Mode 000 aaee 9 5 9 2 2 Exit from Power DOWwn wos scat coats Sua eaaa 9 6 10 OTP Memory Operation 000 e eee eee eee 10 1 10 1 Programming Configuration 90 20 acm Pinte eph on CR e dias 10 1 10 2 Pie GONTOQUIAUIONN GE ac bres Bic th eot dia t Le Een d 10 2 10 3 EB Derblllols sad outer ai deeds mto qute a 10 3 10 4 Programming Mode Selection illii 10 5 10 4 1 Basic Programming Mode Selection 00 0 0 ce
79. 6 62 6 66 CMP2L 3 7 3 10 6 62 6 66 Data memory nnno 0 00 cee 3 2 CMSELO 3 7 3 10 6 46 6 51 DC characteristics 11 2 to 11 5 CMSELOO 0005 3 10 6 52 DGEN Baek Sat educa taken 3 9 6 28 CMSELO1 05 3 10 6 52 Device Characteristics 11 1 to 11 23 CMSEL02 esses 3 10 6 52 DPH 2 cece cence 3 6 3 8 Semiconductor Group 12 2 1997 10 01 SIEMENS nee C504 DP apse hesd he Sa eed ER ahs 3 6 3 8 Fast power on reset 5 3 E ESAS a A A A 1 2 D rio a Ae Sian 3 8 7 5 Functional units 1 1 BADG LL ooo LLL LLL 3 8 6 102 7 6 Fundamental structure 2 1 BADB ste o ere apran e tae n 39 44 G EANO Sen a t dde 3 8 6 109 A ea tay mes 3 8 6 20 EAN T cora tasa 3 8 6 109 General purpose registers 3 2 EAN Zaiat Peter dena 3 8 6 109 GE uc cep xac eR ERR EE Dlg 3 8 9 1 EAN O suis sie erase 3 8 6 109 cof 3 8 9 1 EANA oou std Beste els datos 3 9 6 109 H BEANS 6 ee eee eee ee 3 9 6 109 Hardware reset 5 1 to 5 5 PANG comic stuart eon 3 9 6 109 J PANT Cisne shee siet diets 3 9 6 109 VO DOFIS a essen en Mor DA adu 6 1 to 6 16 a Moor seseses A Uu E niin aaten abit hie alin 3 8 7 15 MI LE a S MONET EUN 3 8 7 15 POEM ries cheb tos e TOTO E 3 8 7 15 BOUT eh caun were See Stee ias A ne ee 3 8 7 15 du ee eee reas O lA 3 8 7 15 EE A ON 3 8 7 15 Ep cesa OOO JADO Lista eese ee avs 3 1
80. 7 Fail save mechanisms 8 1 to 8 7 Semiconductor Group 12 3 1997 10 01 SIEMENS Index C504 Plisson CPU ibus 3 6 3 9 7 8 Po nea tattle de oia 3 6 3 8 6 7 E 3 8 7 14 O ad Sora dedos 3 6 3 9 6 6 EL co sth atte pe Uta eae 3 8 7 14 P38ANA 3 6 3 9 6 1 6 109 M2 ah teeth dated eth sea 3 8 7 14 Package information 11 23 ITCON ts cr Etat ete 3 6 3 8 7 14 PADO us so Pto li Mr rd 3 9 7 8 Parallel l O tke x RR 6 1 to 6 16 Logic symbol 24 duo Oed beer 1 3 PCOM 0 eee eee eee 3 9 7 8 PCEM casita danes 3 9 7 8 VIN A NP sg Bop ota Sra De Ai OR HERO edad 0000 Nas Suis O82 Memory map ooo cece cece cece ee 3 4 POTI rias ie oad t ee bays 3 9 7 8 Memory organization 3 1 Oe pecto ia ne Data memory gt oouo conu 3 2 PDE uses 3 8 9 1 General purpose registers 3 2 EDS Adorn Vee ERI oa Memory Map 3 4 Pin configuration Up ee e e eene 1 4 Program memory ooo 3 2 Pin definitions and functions 1 5to 1 8 MXO ca ocr balada 3 10 6 101 PONS A e 6 1 to 6 16 MAA 3 10 6 101 Alternate functions cr 6 2 O PAN ato ete 3 10 6 101 Loading ano IMErACMG siars a 6 15 Output drivers circuitry 6 9 Mixed digital analog I O pins 6 11 NMOS nn 6 eee eee nnn 3 10 6 51 Multifunctional digital 1 O pins 6 9 Push pull digital analog I O pins 6 12 Oscillator operation 5 6 to 5 7 Push pull digital O pins 6
81. 714 If SMOD 0 which is the value on reset the baud rate is fosc 64 If SMOD 1 the baud rate is fosc 32 Mode 2 baud rate 28 09 64x fogc Modes 1 and 3 The baud rates in mode1 and 3 are determined by the timer overflow rate These baud rates can be determined by timer 1 or by timer 2 or by both one for transmit and the other for receive Semiconductor Group 6 85 1997 10 01 On Chip Peripheral Components C504 SIEMENS 6 4 3 1 Using Timer 1 to Generate Baud Rates When timer 1 is used as the baud rate generator the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows Modes 1 3 baud rate 28M0D 32x timer 1 overflow rate The timer 1 interrupt should be disabled in this application The timer itself can be configured for either timer or counter operation and in any of its 3 running modes In the most typical applications it is configured for timer operation in the auto reload mode high nibble of TMOD 0010B In that case the baud rate is given by the formula Modes 1 3 baud rate 29V P 32xf os J 12x 256 TH1 One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled and configuring the timer to run as a 16 bit timer high nibble of TMOD 0001B and using the timer 1 interrupt to do a 16 bit software reload Table 6 13 lists commonly used baud rates and how they can be obtained from timer 1
82. 9 BCERR Block commutation mode error flag In block commutation mode BCERR is set in rotate right or rotate left mode if after a transition at INTx all INTx inputs are at high or low level Additionally in rotate right or rotate left mode a wrong follower condition according table 6 9 can cause the setting of BCERR see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 the setting of BCERR will generate a CCU emergency interrupt BCERR must be reset by software BCEN Block commutation enable If BCEN is set the multi channel PWM modes of the CAPCOM unit as selected by the bits PWM1 PWMO are enabled for operation Before BCEN bit is set all required PWM compare outputs should be programmed to operate as compare outputs by writing the registers CMSEL1 CMSELO BCM1 Multi channel PWM mode output pattern selection BCMO Additionally to bits PWM1 and PWMO these two control bits select the output signal pattern in all multi channel PWM modes The detailed signal pattern information is given in table 6 9 to table 6 12 BCM1 BCMO Function 0 0 Idle mode 0 1 Rotate right mode 1 0 Rotate left mode 1 1 Slow down mode Note When a multi channel PWM mode is initiated the first time after reset BCON must be written twice first write operation with bit BCEN cleared and all other bits set cleared as required BCM1 0 must be 0 0 for idle mode followed by a second writ
83. ADDATL instruction The start procedure itself is independent of the value which is written to ADDATL When single conversion mode is selected bit ADM 0 only one A D conversion is performed In continuous mode bit ADM 1 after completion of an A D conversion a new A D conversion is triggered automatically until bit ADM is reset The busy flag BSY ADCONO 4 is automatically set when an A D conversion is in progress After completion of the conversion it is reset by hardware This flag can be read only a write has no effect The interrupt request flag IADC IRCONO 0 is set when an A D conversion is completed The bits MXO to MX in special function register ADCONO and ADCON 1 are used for selection of the analog input channel The bits MXO to MX2 are represented in both registers ADCONO and ADCON 1 however these bits are present only once Therefore there are two methods of selecting an analog input channel If a new channel is selected in ADCON1 the change is automatically done in the corresponding bits MXO to MX2 in ADCONO and vice versa Four lines of port 1 and 3 each are dual purpose input output ports These pins can be used either for digital I O functions or as the analog inputs If less than 8 analog inputs are required the unused analog inputs at port 1 or 3 are free for digital I O functions Semiconductor Group 6 98 1997 10 01 SIEMENS On Chip Peripheral Components C504 IEN1 A91 P1ANA 90g MX2 MXO
84. AN7 EAN6 EAN5 EAN4 P3ANA Bit Function EAN3 0 Enable analog port 1 inputs If EANx x 3 0 is cleared port pin P1 x is enabled for operation as an analog input If EANx is set port pin P1 x is enabled for digital I O function default after reset EAN7 4 Enable analog port 1 input If EANx x 7 4 is cleared port pin P3 x 2 is enabled for operation as an analog input If EANx is set port pin P3 x 2 is enabled for digital I O function default after reset Reserved bits Semiconductor Group 6 109 1997 10 01 SIEMENS Interrupt System C504 7 Interrupt System The C504 provides 12 interrupt sources with two priority levels Eight interrupts can be generated by the on chip peripherals timer 0 timer 1 timer 2 serial interface A D converter and capture compare unit and four interrupts may be triggered externally P1 1 T2EX P3 2 INTO P3 3 INT1 and P3 6 INT2 If the capture compare unit is not used in an application its capture features can be used to provide additional 3 external interrupt inputs An additional non maskable 13th interrupt is reserved for the external wake up from power down mode feature Compared with the C501 the functionality of the external interrupts is extended In the edge triggered mode of the external interrupts it is possible to select between a falling a rising or a falling and rising edge interrupt trigger condition The capture compare unit provides four ne
85. ATL If continuous conversion is selected bit ADM set the next conversion is started with the beginning of the machine cycle which follows the writre result cycle Semiconductor Group 6 105 1997 10 01 On Chip Peripheral Components C504 SIEMENS The BSY bit is set at the beginning of the first A D conversion machine cycle and reset at the beginning of the write result cycle If continuous conversion is selected BSY is again set with the beginning of the machine cycle which follows the write result cycle The interrupt flag IADC is set at the end of the A D conversion If the A D converter interrupt is enabled and the A D converter interrupt is priorized to be serviced immediately the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle IADC must be reset by software Depending on the application typically there are three methods to handle the A D conversion in the C504 Software delay The machine cycles of the A D conversion are counted and the program executes a software delay e g NOPs before reading the A D conversion result in the write result cycle This is the fastest method to get the result of an A D conversion Polling BSY bit The BSY bit is polled and the program waits until BSY 0 Attention a polling JB instruction which is two machine cycles long possibly may not recognize the BSY 0 condition during the write result cycle in
86. Address float to PSEN Lp 5 5 ns Interfacing the C504 to devices with float times up to 25 ns is permissible This limited bus contention will not cause any damage to port O drivers Semiconductor Group 11 12 1997 10 01 SIEMENS Device Specifications C504 AC Characteristics for C504 L40 C504 2R40 C504 2E40 cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 40 MHz clock Variable Clock 1 tcerc 3 5 MHz to 40 MHz min max min max RD pulse width fa RH 120 614 0 30 ns WR pulse width fwLwH 120 6tac 30 ns Address hold after ALE LLaxe 35 2tac 15 ns RD to valid data in fai pv 75 5tac 50 ns Data hold after RD RHDX 0 0 ns Data float after RD tRHpz 38 2tac 12 ns ALE to valid data in fiLov 150 8tcrc 50 fns Address to valid data in lavov 150 Woo 75 ns ALE to WR or RD fii we 60 90 Store 15 3fcerc 15 ns Address valid to WR Tavwe 70 feiei 30 ns WR or RD high to ALE high fwn 10 40 Fee 15 f x15 ns Data valid to WR transition favwx 5 tac 20 l ns Data setup before WR low 125 Ttec 50 ns Data hold after WR wHox 5 tac 20 l ns Address float after RD RLAZ 0 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq 3 5 MHz to 40 MHz mi
87. CCLx Operating Mode 0 Period value pv 1 Duty cycle of CCx outputs x x 100 pv Duty cycle of COUTx outputs ov OV x 100 pv 1 Operating Mode 1 Period value 2xpv cv Duty cycle of CCx outputs x 100 Duty cycle of COUTx outputs zr SEV 400 Semiconductor Group 6 41 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 5 Burst Mode of CAPCOM COMP Unit In the burst mode both units of the CCU are combined in a way that the CAPCOM outputs COUTx or CCx and COUTx controlled by bit BCMP in SFR BCON are modulated by the output signal of the COMP unit Using the burst mode the CAPCOM unit operates in compare mode and the COMP unit provides a PWM signal which is switched to the COUTx outputs This PWM signal typically has a higher frequency than the compare output signal of the CAPCOM unit Figure 6 25 shows the waveform generation using the burst mode Count Value A Period Register Compare Timer 1 CT1OFF 0 Compare Register Start of CTI gt Time COUTx COINI 1 CMSELx3 0 Burst Mode COUTx Disabled COINI 0 Compare ANMAAAS AAAAZP ANAS AAAMAM AA Timer 9 VvVvwwvvvvvwwvvvvwwvwvwwvwwwWwWwWv COUTS JAMnnnnr nmnnnh e COUTx oT LLL seat CO LN LA COUT COUTx SORT COINI 0 ia ULL ULL COUTXI Note If the Bits COUT3l and COUTXI in the COINI register are identical COUT3 and the burst signals at COUTx have the s
88. Chip Peripheral Components C504 down counting reload value Toggle osc c T2 0 Control Y Timer 2 Interrupt P1 0 72 P1 1 T2EX 1 UP 02DOWN RC2H RC2L up counting reload value MCS02585 Figure 6 17 Timer 2 Auto Reload Mode DCEN 1 A logic 1 at T2EX makes timer 2 count up The timer will overflow at FFFFY and set the TF2 bit This overflow also causes the 16 bit value in RC2H and RC2L to be reloaded into the timer registers TH2 and TL2 respectively A logic 0 at T2EX makes timer 2 count down Now the timer underflows when TH2 and TL2 equal the values stored in RC2H and RC2L The underflow sets the TF2 bit and causes FFFFy to be reloaded into the timer registers The EXF2 bit toggles whenever timer 2 overflows or underflows This bit can be used as a 17th bit of resolution if desired In this operating mode EXF2 does not flag an interrupt Note P1 1 T2EX is sampled during S5P2 of every machine cycle The next increment decrement of timer 2 will be done during S3P1 in the next cycle Semiconductor Group 6 30 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 2 2 2 Capture In the capture mode there are two options selected by bit EXEN2 in SFR T2CON If EXEN2 0 timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in SFR T2CON This bit can be used to generate an interrupt If EXEN2 1 timer 2 still does the above but with added feature that a 1
89. F signal The transmision begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse occurs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift register Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left of TB8 and all positions to the left of that contain zeroes This conditon flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after WRITE to SBUF Reception is initiated by a detected 1 to 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves valid it is shifted into the input shift regis
90. L setup to PROG or PRD ENS 10 ns PMSEL hold after PROG or PRD lomi 10 ns PROG pulse width Ion 100 us PRD pulse width SE 100 ns Address to valid data out PAD 75 ns PRD to valid data out Ton 20 ns Data hold after PRD frou 0 ns Data float after PRD Tube 20 ns PROG high between two consecutive PROG few 1 us low pulses PRD high between two consecutive PRD low tpyis 100 ns pulses XTAL clock period toke 3 5 12 MHz Note Vpp 11 5 V 5 is valid for devices with version byte 2 02H or higher Devices with version byte 2 01H must be programmed with Vpp 12 V 5 Semiconductor Group 11 16 1997 10 01 SIEMENS Device Specifications C504 PMSEL1 0 M A MCT03369 Notes PRD must be high during a programming write cycle Figure 11 6 Programming Code Byte Write Cycle Timing Semiconductor Group 11 17 1997 10 01 SIEMENS Device Specifications C504 t Paw t pus tras PAH E TIO A_K PAD PDH MITE MN oor jy t PRD t PDF t PWH PCS PRW t PCH _ rt MCT03370 Notes PROG must be high during a programming read cycle Figure 11 7 Verify Code Byte Read Cycle Timing Semiconductor Group 11 18 1997 10 01 SIEMENS Device Specifications C504 MCT03371 Note PALE should be low during a lock bit read write cycle Figure 11 8 Lock Bit Access Timing PMSELI 0 ZA L H Uy MCT03372
91. L2 N C RESET EA Vas PortO Voc all other pins are disconnected 6 Overload conditions occur if the standard operating conditions are exeeded ie the voltage on any pin exeeds the specified range i e Voy gt Voc 0 5 V or Voy lt Vss 0 5 V The supply voltage Vcc and Vss must remain within the specified limits The absolute sum of input currents on all port pins may not exceed 50 mA 7 Not 100 tested guaranteed by design characterization 8 The typical cc values are periodically measured at T4 25 C and Voc 5 V but not 100 tested 9 The maximum Tec values are measured under worst case conditions T 0 C or 40 C and Voc 5 5 V 10 This Vpp specification is valid for devices with version byte 2 02H or higher Devices with version byte 2 01H must be programmed with Vpp 12V 5 11 For the C504 2E ES AA step the Vi min for EA is 0 8 Voc Semiconductor Group 11 3 1997 10 01 SIEMENS Device Specifications C504 MCD03367 C504 2R Active Mode gt de _ _ _ _ Lame P Idle Mode _ _ o A 7 _ ad o 7 5 10 15 20 25 30 35 MHz 40 fosc MCD03368 C504 2E Active Mode Active Mode _ Idle Mode Idle Mode L1 Ma Ales Lp Lp I 15 20 25
92. LE and IDLS will automatically be cleared after being set If one of these register bits is read the value that appears is 0 This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer s task of system protection without effect Note PCON is not a bit addressable register so the above mentioned sequence for entering the idle mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000001B Set bit IDLE bit IDLS must not be set ORL PCON 00100000B Set bit IDLS bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and normally the instruction to be executed following the RETI instruction will be the one following the instruction that sets the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Semiconductor Group 9 4 1997 10 01 SIEMENS Power Saving Modes C504 9 2 Power Down Mode In the power down mode the RC osciillator and the on chip oscillator which operates with the XTAL pins is stopped Therefore all functions of the microcontroller
93. M disabled XMAP 1 XRAM enabled If XRAM is enabled 8 bit MOVX instructions using Ri always access the internal XRAM and do not generate external bus cycles If XRAM is enabled 16 bit MOVX instructions using DPTR access the XRAM if the address is in the range of FFOOL to FFFFy and do not generate external bus cycles in this address range 3 4 4 Reset Operation of the XRAM The content of the XRAM is not affected by a reset After power up the content is undefined while it remains unchanged during and after a reset as long as the power supply is not turned off If a reset occurs during a write operation to XRAM the content of a XRAM memory location depends on the cycle in which the active reset signal is detected MOVX is a 2 cycle instruction Reset during 1st cycle The new value will not be written to XRAM The old value is not affected Reset during 2nd cycle The old value in XRAM is overwritten by the new value After reset the access to the XRAM is disabled bit XMAP of SYSCON 0 Semiconductor Group 3 3 1997 10 01 SIEM ENS Memory Organization C504 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode The XRAM can be accessed by two read write instructions which use the 16 bit DPTR for indirect addressing These instructions are MOVX A QDPTR Read MOVX DPTR A Write Using these instructions with the XRAM disabled implies that port 0 is used as address low data bus port 2 for high a
94. MHz lc 16 1 20 9 mA Power down mode C504 2R Ipp 1 30 WA Vec 2 5 5 V9 C504 2E Ipp 35 60 uA At EA Vpp C504 2E Tocp 30 mA in prog mode Notes 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input 2 Capacitive loading on ports O and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0 9 Voc specification when the address lines are stabilizing 3 Ipp power down mode is measured under following conditions EA PortO Vec RESET Vss XTAL2 N C XTAL1 Vss Vagnp Vss all other pins are disconnected 4 cc active mode is measured with XTAL1 driven with ci cH toHcL 5ns j Vi Vss 0 5 V Vin Voc 0 5 V XTAL2 N C EA Port0 Porti RESET Voc all other pins are disconnected would be slightly higher if a crystal oscillator is used appr 1 mA 5 Zcc idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with ci cH toHcL 5 ns Vi Vss 0 5 V Vin Voc 0 5 V XTA
95. MO SM1 Selected operating mode 0 0 Serial mode 0 Shift register fixed baud rate fosc 12 0 1 Serial mode 1 8 bit UART variable baud rate 1 0 Serial mode 2 9 bit UART fixed baud rate fosc 32 or fosc 64 1 1 Serial mode 3 9 bit UART variable baud rate SM2 Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3 if SM2 is set to 1 then RIO will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 REN Enable receiver of serial port 0 Enables serial reception Set by software to enable serial reception Cleared by software to disable serial reception TB8 Serial port transmitter bit 9 TB8 Is the 9th data bit that will be transmitted in modes 2 and 3 Set or cleared by software as desired RB8 Serial port receiver bit 9 In modes 2 and 3 RB8 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI Serial port transmitter interrupt flag Tl is set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes in any serial transmission TI must be cleared by software RI Serial port receiver interrupt flag RIO is set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes in any serial reception exception see SM2
96. N1 4 P1 6 CC2 CCIR 4 oO CC2REN CCIE0 4 oO CCIRS CC2FEN CCIE0 5 Compare Timer 1 Interrupt CCIR 7 CCIE 7 Compare Timer 2 CCIR 6 CCIE 6 Eid IEN1 5 Interrupt CT2CON 7 CCU Emergency Interrupt Z TRCON 6 CT1CON 6 IEN1 3 Y Bit addressable Request Flag is cleared by hardware Figure 7 2 BCON 3 BCON 4 Interrupt Request Sources Part 2 Semiconductor Group IEN1 2 MCB02596 7 3 1997 10 01 Interrupt System C504 SIEMENS 7 1 Interrupt Structure A common mechanism is used to generate the various interrupts Each interrupt source has its own request flag s located in a special function register e g TCON T2CON SCON ADCONO Provided the peripheral or external source meets the condition for an interrupt the dedicated request flag is set whether an interrupt is enabled or not For example each timer 0 overflow sets the corresponding request flag TFO If it is already set it retains a one 1 But the interrupt is not necessarily serviced Now each interrupt requested by the corresponding flag can individually be enabled or disabled by the enable bits in the SFRs IENO and IEN1 This determines whether the interrupt will actually be performed In addition there is a global enable bit for all interrupts which when cleared disables all interrupts independent of their individual enable bits 7 2 Interrupt Sources and Ve
97. Note PROG must be high during a programming read cycle Figure 11 9 Version Byte Read Timing Semiconductor Group 11 19 1997 10 01 SIEMENS Device Specifications C504 11 8 ROM OTP Verification Characteristics for C504 2R C504 2E ROM Verification Mode 1 C504 2R only Parameter Symbol Limit Values Unit min max Address to valid data Tavav 10 tac ns P1 0 P1 7 P2 0 P2 5 Address tavov Port 0 Data OUT Address P1 0 P1 7 AO A7 Inputs P2 6 P2 7 PSEN Vas P2 0 P24 A8 A13 ALE EA Vj Data P0 0 P0 7 DO D7 RESET Vi MCT03428 Figure 11 10 ROM Verification Mode 1 Semiconductor Group 11 20 1997 10 01 SIEMENS Device Specifications C504 ROM OTP Verification Mode 2 Parameter Symbol Limit Values Unit min typ max ALE pulse width Lawo 2 tool ns ALE period Lacy 12 toe ns Data valid after ALE Tova 4 tore ns Data stable after ALE Losa 8 faic ns P3 5 setup to ALE low las teLcL B ns Oscillator frequency lac 4 6 MHz AAA Data vid MCT02613 Figure 11 11 ROM Verification Mode 2 Semiconductor Group 11 21 1997 10 01 SIEMENS Device Specifications C504 0 2 Voc 0 9 Test Points 0 45 V MCT00039 AC Inputs during testing are driven at Vo 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measurements are made at Vi ni for a logic 1 and V
98. POW ee eh oe ode bo do da 2 3 3 6 3 9 Eo a tea cogi e dd e ones 3 6 3 8 6 6 POs hie ate du a LO ate 3 9 7 7 PIANA 3 6 3 8 6 1 6 109 PET se o ar te id 3 9 7 7 Semiconductor Group 12 4 1997 10 01 SIEMENS C504 PL 22sec steed he A eed NE ATE 3 9 7 7 Special function registers 3 5 PWMO Leite 3 10 6 69 Access with RMAP 3 5 PAI s css SO exis Weed aoe has 3 10 6 69 Table address ordered 3 8 to 3 11 PXQ S hu a ere ed aoe eats 3 9 7 7 Table functional order 3 6 to 3 7 EX MAC uM Re uero E dU ies 3 9 7 7 SET dass odo s oM dA tito 3 10 6 47 X2 vit ote idest ecd ides 3 9 7 8 STE2 eu f ex RI Ra ee Ry SS 3 9 6 63 SWEET E cz eia sale trea rst gs 3 9 8 2 ABS ee o Ue weet aoe gh 3 8 6 84 SYSCON 3 3 3 5 3 6 3 9 4 4 RCZ PM 3 7 3 9 6 26 HI Bi lee ate des 3 7 3 9 6 26 PO bera ae C dnd ME Se 3 9 BOIS 2 gene dite dai daas 3 9 6 27 MTG deme A mese mean dea Shadi aged 3 9 Ps Senate eue an aed nt fc dett 3 9 qe x tere Oho A M MOS ates OEA a 3 8 Recommended oscillator circuit 5 6 11 22 J2GON 26 y vimus 3 7 3 9 6 27 REN S ewan sad 3 Sarees aed Rut 3 8 6 84 DoD C EIE 3 8 ROSSO tit temet ete atte aah teet 5 1 T2MQOBD eeu 3 7 3 9 6 28 Fast power on reset 5 3 MB Gees nis ss 3 8 6 84 Hardware reset timing 5 5 TOLEK rc EE 3 9 6 27 Power on reset timing 5 4 TECON AA an 3 6 3 8 6 19 7 14 Reset circuitries 5 2
99. R addresses of the version bytes in normal mode are identical to the addresses which are used in programming mode Therefore in normal operating mode of the C504 2E or C504 2R the SFR locations which hold the version bytes are also referenced as version registers Semiconductor Group 10 11 1997 10 01 SIEMENS OTP Memory Operation C504 The steppings of the C504 contain the following version byte register information Table 10 4 Version Register Byte Content Stepping Version Byte 0 VRO mapped addr FCH Version Byte 1 VR1 mapped addr FD Version Byte 2 VR2 mapped addr FEy C504 2R AC Step C5H 04y 01h C504 2E ES AA C5H 84H 01H Step C504 2E AB Step C5H 84H 02H Future steppings of the C504 will typically have a different version byte 2 incremented value Semiconductor Group 10 12 1997 10 01 SIEMENS Device Specifications C504 11 Device Specifications 11 1 Absolute Maximum Ratings Ambient temperature under bias Ta ccooonncnccccccnnncccnonancnnnnncnonananannncnnnnncnnnnnns 0 C to 70 C Storage temperature Tai iere te e e Dev eee cla tere ed 65 C to 150 C Voltage on Vec pins with respect to ground Vss ccoooooccccnnncconanananaccnoncnonannnnnos 0 5V to 6 5 V Voltage on any pin with respect to ground Vgs cccooooccccnnnncconananancncnnncnnnaannnnos 0 5 V to Voc 0 5 V Input current on any pin during overload condition ooooooocccc
100. R SYSCON must be set 4 These SFRs are read only registers 5 044 is valid for the C504 2R 84y is valid for the C504 2E 6 Semiconductor Group The content of this SFR varies with the actual step of the C504 see also table 10 4 in chapter 10 1997 10 01 SIEMENS External Bus Interface C504 4 External Bus Interface The C504 allows for external memory expansion To accomplish this the external bus interface common to most 8051 based controllers is employed 4 1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively This distinction is made by hardware accesses to external program memory use the signal PSEN program store enable as a read strobe Accesses to external data memory use RD and WR to strobe the memory alternate functions of P3 7 and P3 6 Port O and port 2 with exceptions are used to provide data and address signals In this section only the port O and port 2 functions relevant to external memory accesses are described Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri Role of PO and P2 as Data Address Bus When used for accessing external memory port O provides the data byte time multiplexed with the low byte of the address In this state port 0 is disconnected from
101. RC2L CBy we 6 5 4 2d 2 1 0 RC2H Bit Function TL2 7 0 Timer 2 value low byte The TL2 register holds the 8 bit low part of the 16 bit timer 2 count value TH2 7 0 Timer 2 value high byte The TH2 register holds the 8 bit high part of the 16 bit timer 2 count value RC2L 7 0 Reload capture timer 2 register low byte RC2L holds the 8 bit low byte of the 16 bit timer 2 reload or capture value RC2H 7 0 Reload capture timer 2 register high byte RC2H holds the 8 bit high byte of the 16 bit timer 2 reload or capture value Semiconductor Group 6 26 1997 10 01 SIEMENS On Chip Peripheral Components C504 Special Function Register T2CON Address C8 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy CEH CDy CCy CBy CAH C9H4 C8y C8y TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 T2CON Bit Function TF2 Timer 2 Overflow Flag Set by a timer 2 overflow Must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 Timer 2 External Flag Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the timer 2 interrupt routine EXF2 must be cleared by software EXF2 does not cause an interrupt in up down counter mode DCEN 1 SFR T2MOD RCLK Receive Clock Enable When set causes the serial port to use timer 2 overflow pulses for its receive clock in seria
102. SEL the logic state of PROG and EA Vpp is internally latched These two signals are now used as programming write pulse signal PROG and as programming voltage input pin Vpp After the falling edge of PSEL PSEL must stay at 0 state during all programming operations Note If protection level 1 to 3 has been programmed see section 10 6 and the programming mode has been left it is no more possible to enter the programming mode 10 4 2 OTP Memory Access Mode Selection When the C504 2E has been put into the programming mode using the basic programming mode selection several access modes of the OTP memory programming interface are available The conditions for the different control signals of these access modes are listed in table 10 2 Table 10 2 Access Modes Selection EA PMSEL Address Data Access Mode Vpp PROG PRD 1 0 Port 2 Port 0 Program OTP memory byte Vpp LJ H H H AO0 7 DO 7 Read OTP memory byte Vin H LI A8 15 Program OTP lock bits Ve LT H H L D1 DO see Read OTP lock bits Via H Lr table 10 3 Read OTP version byte Vin H LY IL H Byte addr DO 7 of version byte The access modes from the table above are basically selected by setting the two PMSEL1 0 lines to the required logic level The PROG and PRD signal are the write and read strobe signal Data is transfered via port O and addresses are applied to port 2 The following sections describes the detail
103. SIEMENS Since Apri 1 1009 Siemens Semiconductor n fi n e 0 n A Technologies The next revision of this document will be updated accordingly C504 8 Bit CM OS M icrocontroller User s M anual 10 97 Edition 1997 10 01 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Munchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of tran
104. The basic waveforms of these three compare timer 1 controlled PWM modes are shown the following three figures 6 32 to 6 34 The figures show waveforms for different COINI values with the resulting active inactive phases and rotate right rotate left condition All three figures assume that compare timer 1 operates with 100 duty cycle compare and offset registers 00004 and without compare timer 2 modulation Compare timer 1 duty cycles less than 100 or compare timer 2 modulation in the multi channel PWM modes are shown in figures 6 29 and 6 30 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111p Start rag A al al e be e lll eal Timer 1 gt cco COUT1 Low Active bom ux g ES OS EE RS EE COUT2 State No 1 2 3 4 1 2 3 4 1 2 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000g Start Timer 1 gt cco COUT High Active EH ew as e sees ue COUT2 State No 2 1 4 5 2 1 4 3 2 MCT02612 Figure 6 32 Basic Compare Timer 1 Controlled 4 Phase PWM Timing Semiconductor Group 6 75 1997 10 01 SIEMENS On Chip Peripheral Components C504 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111p Start nee OA Timer 1 gt CCO COUTO COUT2 State No 1 2 3 4 5 1 2 3 4 5 1 b Timing in rotate right
105. U 0 0002 eren 6 32 6 3 1 General Capture Compare Unit Operation 000000 cee eee 6 33 6 3 2 CAPCOM Unit Operation s ui tut raro 6 35 6 3 2 1 CAPCOM Unit Clocking Scheme 0000 cece eee 6 35 6 3 2 2 CAPCOM Unit Operating Mode Di 1 seb be Pe ERE Eee Ree ale ba es 6 36 6 3 2 3 CAPCOM Unit Operating Mode 1 oooocoocccccc 6 39 6 3 2 4 CAPCOM Unit Timing Relationships 0 000 e eee eee 6 40 6 3 2 5 Burst Mode of CAPCOM COMP Unit 2 000 00 eee eee 6 42 6 3 2 6 CAPCOM Unit in Capture Mode nananana anana 6 43 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode 5 6 44 6 3 2 8 CARCOM Registers os nes ice Lote kw S ausa ise da Dis du do Aa 6 46 6 3 3 Compare COMP Unit Operation liis 6 61 6 3 3 1 COMP REGIS Cle tenes strate e ue S RU REN Ret NOIL ened SOL us QUE SUR IE oa 6 62 6 3 4 Combined Multi Channel PWM Modes lisse eser 6 67 6 3 4 1 Control Register BOON sir ole eh Ce a ER A e iran 6 68 6 3 4 2 Signal Generation in Multi Channel PWM Modes 0000 eee eee 6 70 6 3 4 3 Block Commutation PWM Mode ooococcccoo es 6 73 6 3 4 4 Compare Timer 1 Controlled Multi Channel PWM ModesS 6 75 6 3 4 5 Software Controlled State Switching in Multi Channel PWM Modes 6 80 6 3 4 6 Trap Function in Multi Channel Block Commutation Mode 6 81 6 4 Serial Interface USART i24 xxvm ERES EET te a c
106. UT1 CC2 COUTO CC1 COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive inactive inactive 2 1 0 7 1 active active inactive inactive inactive inactive 5 2 0 7 2 inactive active active inactive inactive inactive 1 3 0 7 3 inactive inactive active active inactive inactive 2 4 0 7 4 inactive inactive inactive active active inactive 3 5 0 7 5 inactive inactive inactive inactive active active 4 6 0 7 6 active inactive inactive inactive inactive active 5 1 0 7 7 inactive active inactive active inactive active 2 1 0 7 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Semiconductor Group 6 79 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 4 5 Software Controlled State Switching in Multi Channel PWM Modes In the 4 5 6 phase multi channel PWM modes the compare timer 1 overflow controlled switching of the follower state can be switched off Instead of the compare timer 1 overflow a setting of bit NMCS in SFR CMSEL1 selects the follower state which is defined in the tables 6 10 to 6 12 Bit ESMC in SFR CMSEL1 enables the software controlled state switching If this software controlled 4 5 6 phase multi channel PWM mode generation is selected the compare timer
107. aia tetas 6 82 6 4 1 Multiprocessor Communications lisse 6 83 6 4 2 sgridl ParbegislerS eub ede ene EQUI Ku EI are cae S E d es 6 83 6 4 3 Baud a8 uio ceno our seb vp gott dia e pieds Ge eiut riu aa 6 85 6 4 3 1 Using Timer 1 to Generate Baud Rates 00 00 cece eee eee 6 86 6 4 3 2 Using Timer 2 to Generate Baud Rates 0 0 eee 6 87 6 4 4 Details about Mode D ces ugcp ez wy gut eai hse pea nba Ae eee eae we 6 89 6 4 5 Details about Mode T soccer etd awa ethan eee bene RR 6 92 6 4 6 Details about Modes 2 and 3 nut oars ed ewe e deg eta at eae 6 95 6 5 10 bit A D Converter cuts gate tee tus dows a o 6 98 6 5 1 A D Gonverter Operation vacia eR Mee ale Aoc bd Be ea 6 98 6 5 2 A D Gonverter Registers evitas ae cb ER DEL wader ess 6 100 6 5 3 A D Converter Clock Selection 0000 cee eee 6 103 Semiconductor Group 1 2 1997 10 01 SIEMENS General Information C504 Table of Contents Page 6 5 4 A D Conversion Ting 5 io gees eae Uke E ee SR RSI EN ee 6 104 6 5 5 A D Converter Calibration sue x rias Deke bose Bette REN RE RERO 6 108 6 5 6 A D Converter Analog Input Selection liliis 6 109 7 Interrupt System bc eee cee err m me xem rex x Mim aimed am ea 7 1 7 1 Interrupt Str ct re c oy du tee im eee oe Ue E ee A x E ets 7 4 7 2 Interrupt Sources and Vectors yea aaa eRe 7 4 7 3 Interrupt Registers sss ERE REXCRE ras 7 5 7 3 1 Interrupt Enable Registers esco e balay Adee 7
108. al I O pin or analog input pin Capture mode enabled CCx is configured as a capture input and a rising edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input and a falling edge at CCx transfers compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Capture mode enabled CCx is configured as a capture input Rising and falling edge at CCx transfer the compare timer 1 content into the capture register COUTx is a normal I O pin or analog input pin Note only CCO COUTO can be analog inputs if not selected as compare output In compare mode the two output signals of a CAPCOM channel can be enabled selectively In capture mode the type of signal transition which will generate a capture event can be chosen Semiconductor Group 6 52 1997 10 01 SIEMENS On Chip Peripheral Components C504 Capture Compare Registers of CAPCOM Unit The capture compare registers are 16 bit registers organized as two 8 bit byte wide registers Each of the three CAPCOM channels has one capture compare register In compare mode they hold a compare value which typically defines the duty cycle of the output signals In capture mode the actual compare timer 1 value is transferred into the capture compare registers at a capture event If CCLx CCHx is written alway
109. ame polarity MCTO2605 Figure 6 25 Burst Mode Operation The burst mode of a COUTx output is enabled by the bit CMSELx3 which is located in the mode select registers CMSELO and CMSEL1 Figure 6 25 shows four CAPCOM output signals with different initial logic states with burst mode disabled CMSELx3 0 and burst mode enabled CMSELx3 1 Generally the CCx outputs cannot operate in burst mode Optionally the signal at COUTx may have inverted polarity than the PWM signal which is available at pin COUT3 Semiconductor Group 6 42 1997 10 01 SIEMENS On Chip Peripheral Components C504 Depending on the corresponding initial compare output level bit in COINI either a low or high level for the non modulated state at the COUTx pins can be selected Burst mode can be enabled in both operating modes of the compare timer 1 The burst mode as shown in figure 6 25 is only valid if the block commutation mode of the CCU is disabled bit BCEN of SFR BCON cleared The modulation of the compare output signals at COUTx is switched on COUTS signal is switched to COUTx when the compare timer 1 content plus the value stored in the compare timer 1 offset register is equal or greater than the value stored in the compare register of CAPCOM channel x 6 3 2 6 CAPCOM Unit in Capture Mode The three channels of the CAPCOM unit can be individually programmed to operate in capture mode In capture mode each CAPCOM channel offers one captu
110. and 3 are configured as digital inputs The analog function of the specific port 1 and port 3 pins is enabled by bits in the SFRs P1ANA and P3ANA Writing a O to a bit position of P1ANA or P3ANA assigns the corresponding pin to operate as analog input Semiconductor Group 6 1 1997 10 01 SIEMENS On Chip Peripheral Components C504 Note P1ANA and P3ANA are mapped SFRs and can be only accessed if bit RMAP in SFR SYSCON is set description see chapter 6 5 4 Type D and E port lines can be switched to push pull drive capability when they are used as compare outputs of the CAPCOM unit As already mentioned port 1 and 3 are provided for multiple alternate functions These second and third functions of the port 1 and 3 lines are listed in table 6 2 Table 6 2 Alternate Functions of Port 1 and 3 Port Second third Port Function Function Type P1 0 ANO T2 C Analog input channel 0 input to counter 2 AN1 T2EX C Analog input channel 1 capture reload trigger of timer 2 up down count P1 2 AN2 CCO E Analog input channel 2 CAPCOM channel 0 input output P1 3 AN3 COUTO E Analog input channel 3 CAPCOM channel 0 output P1 4 CC 1 D CAPCOM channel 1 input output P1 5 COUT1 D CAPCOM channel 1 output P1 6 CC2 D CAPCOM channel 2 input output P1 7 COUT2 D CAPCOM channel 2 output P3 0 RxD B Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD B Serial port s transmitter data out
111. and forces the controller to a predefined default state The hardware reset function can also be used during normal operation in order to restart the device This is particularly done when the power down mode is to be terminated Additionally to the hardware reset which is applied externally to the C504 there are two internal reset sources the watchdog timer and the oscillator watchdog The chapter at hand only deals with the external hardware reset The reset input is an active high input An internal Schmitt trigger is used at the input for noise rejection Since the reset is synchronized internally the RESET pin must be held high for at least two machine cycle 24 oscillator periods while the oscillator is running With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again During reset pins ALE and PSEN are configured as inputs and should not be stimulated externally An external stimulation at these lines during reset activates several test modes which are reserved for test purposes This in turn may cause unpredictable output operations at several port pins At the reset pin a pulldown resistor is internally connected to Vas to allow a power up reset with an external capacitor only An automatic reset can be obtained when Vec is applied by connecting the reset pin to Voc via a capacitor After Voc has been turned on the capacitor must hold the voltage
112. apture compare register 1 high byte C5H CCL2 Capture compare register 2 low byte C6y CCH2 Capture compare register 2 high byte C7y CCIR Capture compare interrupt request flag register E5y CCIE Capture compare interrupt enable register D6H COINI Compare output initialization register E2y TRCON Trap enable register CFy The following sections describe the CAPCOM registers in detail Writing the CAPCOM Period Offset Compare Registers on the Fly If compare timer 1 is running period offset or compare registers can be written with modified values for generating new periods or duty cycles of the compare output signals For proper synchronization purposes a special mechanism for updating of the 16 bit offset period and compare registers is implemented in the C504 This mechanism is based on shadow latches When new values for offset period or compare registers have been written into the shadow latches the real register update operation must be initiated by setting bit STE1 shadow transfer enable in SFR CT1CON When this bit is set the content of the shadow latches is transferred to the real registers under the following conditions Compare timer 1 operating mode 0 Compare timer 1 has reached the period value stored in the CCPH CCPL registers Compare timer 1 operating mode 1 Compare timer 1 has reached the count value 0000y When the register transfer has been executed STE1 is reset by hardware So the software can re
113. are reset will be initiated The software can be designed such that the watchdog times out if the program does not work properly It also times out if a software error is based on hardware related problems The Watchdog Timer in the C504 is a 15 bit timer which is incremented by a count rate of either Sovere 2 Ot fcvoie 32 fovere fogc 12 That is the machine clock is divided by a series of arrangement of two prescalers a divide by two and a divide by 16 prescaler The divide by 16 prescaler is enabled by setting bit WDTPSEL bit 7 of SFR WDTREL From the 15 bit Watchdog Timer count value only the upper 7 bits can be programmed Figure 8 1 shows the block diagram of the programmable Watchdog Timer WDT Reset Request WDCON COy Y gt Jowosfwors wor swor Control Logic External HW Reset MCS01771 Figure 8 1 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 8 1 1997 10 01 SIEMENS Fail Safe Mechanisms C504 Special Function Register WDTREL Address 86 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 864 WDT Nachod Timer Bielosd Register WDTREL H PSEL pas AE apum Bit Function WDTPSEL Watchdog timer prescaler select bit When set the watchdog timer is clocked through an additional divide by 16 prescaler WDTREL 6 0 Seven bit reload value for the high byte of the watchdog timer This value is loaded to WDTH when a
114. are timer 1 Compare timer 1 is the timing base for all compare and capture capabilities of the CAPCOM unit The input clock for compare timer 1 is directly coupled to the system clock of the C504 Its frequency can be selected via three bits of the CT1CON register in a range of fosc 2 up to fosc 256 For the understanding of the following timing diagrams figure 6 20 shows the internal clocking scheme of the CAPCOM unit The internal input clock of the CAPCOM unit is a symmetrical clock with 50 duty cycle The clock transitions edges of the CAPCOM internal input clock are used for different actions at clock edge 1 the compare timer 1 is clocked to the next count value and with clock edge 2 the compare outputs CCx and COUTx are toggled set to the new logic level if required A D D min 50 ns 40 MHz clock rate NK fosc 2 2 i ee amp LI LILI LI LILI LS D a fosc 8 o 2 fosc 16 CD increment decrement of compare timer 1 2 change modify logic level at CCx COUTx MCD02600 Figure 6 20 CAPCOM Unit Clocking Scheme Generally the CAPCOM clocking scheme shown above is also valid for the COMP compare timer 2 unit Semiconductor Group 6 35 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 2 CAPCOM Unit Operating Mode 0 Figure 6 21 shows the CAPCOM unit timing in operating mode 0 in detail CT1 Value CCP 7 A Period Reg CT1OFF 0 Offset Reg
115. arted immediately when power down mode is entered Semiconductor Group 9 5 1997 10 01 SIEMENS Power Saving Modes C504 9 2 2 Exit from Power Down If power down mode is exit via a hardware reset the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed The reset signal that terminates the power down mode also restarts the RC oscillator and the on chip oscillatror The reset operation should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset Figure 9 1 shows the procedure which must is executed when power down mode is left via the INTO wake up capability Execution of Power Down Latch Watchdog Circuit Interrupt Mode Phase Oscillator Start up Phase at 007By 1 2 3 4 Sms typ RETI Instruction 10 us min Detailed Timing of Beginning of Phase 4 ALE yyy valid Address Dt BRA stn MCT02597 Figure 9 1 Wake up from Power Down Mode Procedure Semiconductor Group 9 6 1997 10 01 SIEMENS Power Saving Modes C504 When the power down mode wake up capability has been enabled bit EWPD in SFR PCON1 set prior to entering power down mode the power down mode can be exit via INTO while executing the following procedure 1 2 In power down mode pin INTO must be held at high level Power down mode
116. as the address data bus When used as inputs it must be noted that the ports 2 and 3 are not floating but have internal pullup transistors The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin the parameters and J in the DC characteristics specify these currents Port O as well as the input only port 1 however have floating inputs when used for digital input Semiconductor Group 6 15 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 6 Read Modify Write Feature of Ports 2 and 3 Some port reading instructions read the latch and others read the pin The instructions reading the latch rather than the pin read a value possibly change it and then rewrite it to the latch These are called read modify write instructions which are listed in table 6 3 If the destination is a port ora port pin these instructions read the latch rather than the pin Note that all other instructions which can be used to read a port exclusively read the port pin In any case reading from latch or pin resp is performed by reading the SFR PO P2 and P3 for example MOV A P3 reads the value from port 3 pins while ANL P3 40AAH reads from the latch modifies the value and writes it back to the latch It is not obvious that the last three instructions in table 6 3 are read modify write instructions but they are The reason is that they read the port byte all 8 bits modif
117. ast programming cycles are achieved 1 byte in 100 usec Also several levels of OTP memory protection can be selected The basic functionality of the C504 2E as microcontroller is identical to the C504 2R ROM part or C504 L romless part functionality Therefore the programmable C504 2E typically can be used for prototype system design as a replacement for the ROM based C504 2R microcontroller 10 1 Programming Configuration During normal program execution the C504 2E behaves like the C504 2R C504 L For programming of the device the C504 2E must be put into the programming mode This typically is done not in system but in a special programming hardware In the programming mode the C504 2E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address data information control lines and an external 11 5 V programming voltage In the programming mode port O provides the bidirectional data lines and port 2 is used for the multiplexed address inputs The upper address information at port 2 is latched with the signal PALE For basic programming mode selection the inputs RESET PSEN EA Vpp ALE PMSEL1 0 and PSEL are used Further the inputs PMSEL1 0 are required to select the access types e g program verify data write lock bits in the programming mode In programming mode V c Vss and a clock signal at the XTAL pins must be applied to the C504 2E The 11 5 V external programming voltage is in
118. ay of typ 1 ms in order to allow the on chip oscillator to stabilize Note The oscillator watchdog unit is always enabled Semiconductor Group 8 5 1997 10 01 SIEMENS Fail Safe Mechanisms C504 8 2 1 Detailed Description of the Oscillator Watchdog Unit Figure 8 2 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator Power Down Mode Activated Power Down Mode Control d Control Wake Up Interrupt Logic Logic Internal Reset e Start Stop RC Oscillator fre Frequency Comparator On Chip Oscillator WDCON COH i pes NGS gt Internal o Clock MCB02578 Figure 8 2 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same ti
119. bined multi channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by the interrupt inputs INTO to INT2 block commutation mode or by the operation of compare timer 1 or by software multi channel PWM mode In the active phase of a combined multi channel PWM mode compare timer 1 compare output signal or the compare timer 2 output signal or both can be switched selectively to the CCx or COUTx PWM output lines The combined multi channel PWM modes are controlled by the BCON block commutation control register Figure 6 28 shows the block diagram of the multi channel PWM mode logic which is integrated in the C504 CCU Emergency Interrupt ft Combined Trap Control Multi Channel PWM Control BCON Port 1 Control Capture Channel 0 in Interrupt Capture Mode Logic Period 16 Bit 10 Bit Comp Match Compare Compare gt COUT3 Interrupt Timer 1 Timer 2 MCB02608 Figure 6 28 Block Diagram of the Combined Multi Channel PWM Modes in the C504 In block commutation mode a well defined incoming digital signal pattern of e g hall sensor signals which are applied to the INTO 2 inputs is sampled Each transition at the INTO 2 inputs results in a change of the state of the PWM outputs In block commutation mode all six PWM output signals CCx and COUTx x 0 2 are outputs According to a block commutation table table 6 9 the outputs CCx are put either to a low or high
120. bits in COINI If CT1RES 0 compare timer 1 continues its operation but no compare output signal will be generated If CT1RES 1 compare timer 1 is reset when CTRAP becomes active When CTRAP is sampled inactive high again the compare channel outputs are synchronously switched to the compare channel output signal generation when compare timer 1 has reached the count value 00004 The trap function is controlled by bits in the TRCON register The general enable function of the external CTRAP signal is controlled by one bit TRPEN Further each CAPCOM compare channel output can be enabled disabled selectively for trap function Figure 6 26 shows the trap function for the two outputs CCx and COUTx of one compare channel x The timing diagram implies that the trap function is enabled at the CCx and COUTx outputs At reference point 1 in figure 6 26 CT RAP becomes active and at reference point 2 the trap state is released again synchronously to the compare timer 1 count state 0000p If the trap function is enabled and CTRAP becomes active bit TRF trap flag in SFR TRCON is set and a CCU emergency interrupt will be generated if the related interrupt enable bits are set The flag TRF is level sensitive and must be cleared by software The trap function used in block commutation mode differs from the trap function described above Especially the synchronization scheme is different see section 6 3 4 6 Semiconductor Group 6 44 1997
121. capture compare match interrupt flags are set by hardware and must be cleared by software A capture compare match interrupt is generated with the setting of a CCxR bit x 0 2 if the corresponding enable bits are set The compare timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR CCIR Special Function Register CCIR Address E5 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 ES CT1IFP CT1FC CC2F CC2R CC1F CC1R CCOF CCOR CCIR CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function CT1FP Compare timer 1 period flag Compare timer 1 operating mode 0 CT1FP is set if compare timer 1 reaches the period value Compare timer 1 operating mode 1 CT1FP is set if compare timer 1 reaches the period value and changes the count direction from up to down counting Bit CT1FP must be cleared by software If compare timer 1 interrupt is enabled the setting of CT1FP will generate a compare timer 1 interrupt CT1FC Compare timer 1 count direction change flag This flag can only be set if compare timer 1 runs in operating mode 1 CTM 1 CT1FC is set when compare timer 1 reaches count value 00004 and changes the count direction from down to up counting If compare timer 1 interrupt is enabled the setting of CT1FC will generate a compare timer 1 interrupt Bit CT1FC must be cleared by software CCxR Capture compare match on up count flag x 0 2 Capture Mode CCxR
122. cess modes in programming mode PMSEL1 0 must satisfy a setup time to the rising edge of PALE When the logic level of PMSEL1 0 is changed PALE must be at low level PMSEL1 PMSELO Access Mode 0 0 Reserved 0 1 1 Read version bytes 1 0 Program read lock bits 1 Program read OTP memory byte Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 10 3 Programming mode read strobe This input is used for read access control for OTP memory read version byte read and lock bit read operations PALE Programming address latch enable PALE is used to latch the high address lines The high address lines must satisfy a setup and hold time to from the falling edge of PALE PALE must be at low level when the logic level of PMSEL1 0 is changed XTAL2 XTAL2 Output of the inverting oscillator amplifier XTAL1 XTAL1 Input to the oscillator amplifier 2 Input O Output Semiconductor Group 10 3 1997 10 01 SIEMENS OTP Memory Operation C504 Table 10 1 Pin Definitions and Functions of the C504 2E in Programming Mode cont d Symbol Pin Number I O Function P MQFP 44 Vss 16 Circuit ground potential must be applied in programming mode Voc 17 Power supply terminal must be applied in programming mode P2 0 7 18 25 Address lines P2 0 7 are used as multiplexe
123. ch it is possible to access the OTP memory through the programming interface logic Further after selection of the basic programming mode OTP memory accesses are executed by using one of the access modes These access modes are OTP memory byte program read version byte read and program read lock byte operations 10 4 1 Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 10 3 Voc RESET YY m PMSEL1 0 YM MMMM PROG A o YM YM EA Vep Ui AA Ready for access AGA EN PRD Uf D Vpp mode selection 77 During this period signals are not actively driven MCT03362 Figure 10 3 Basic Programming Mode Selection Semiconductor Group 10 5 1997 10 01 SIEMENS OTP Memory Operation C504 The basic programming mode is selected by executing the following steps With a stable Vcc a clock signal is applied to the XTAL pins the RESET pin is set to 1 level and the PSEN pin is set to 0 level PROG PALE PMSEL1 and EA Vpp are set to O level PRD PSEL and PMSELO are set to 1 level PSEL is set to from 1 to O level and thereafter PROG is switched to 1 level PMSEL1 0 can now be changed after EA Vpp has been set to V high level or to Vpp the OTP memory is ready for access The pins RESET and PSEN must stay at 1 respectively O static signal level during the whole programming mode With a falling edge of P
124. chine cycle When an instruction reads a value from a port pin e g MOV A P1 the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions Figure 6 11 illustrates this port timing It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an edge e g when used as counter input In this case an edge is detected when the sampled value differs from the value that was sampled the cycle before Therefore there must be met certain requirements on the pulse length of signals in order to avoid signal edges not being detected The minimum time period of high and low level is one machine cycle which guarantees that this logic level is noticed by the port at least once S3 P2 P2 P1 led Haran eel i P1 active for 1 State driver transistor HH Port Old Data X New Data MCT03231 Figure 6 11 Port Timing Semiconductor Group 6 14 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 5 Port Loading and Interfacing The output buffers of ports 2 and 3 can drive TTL inputs directly The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the C504 The corresponding parameters are Vo and Voy The same applies to port 0 output buffers They do however require external pullups to drive floating inputs except when being used
125. cognize when the register transfer has occurred When compare timer 1 is started by setting the run bit CT1R the first time after reset a shadow register transfer into the real registers is automatically executed In this case STE1 must not be set Semiconductor Group 6 46 1997 10 01 On Chip Peripheral Components C504 SIEMENS Compare Timer 1 Control Register The 16 bit compare timer 1 is controlled by the bits of the CT1CON register With this register the count mode the trap interrupt enable the compare timer start stop and reset and the timer input clock rate is controlled Special Function Register CT1CON Address El y Reset Value 00010000p Bit No MSB LSB 7 6 5 4 3 2 1 0 Ely CTM ETRP STE1 CT1RES CT1R CLK2 CLK1 CLKO CT1CON Bit Function CTM Compare timer 1 operating mode selection CTM 0 selects operating mode 0 up count and CTM 1 selects operating mode 1 up down count for compare timer 1 ETRP CCU emergency trap interrupt enable If ETRP 1 the emergency interrupt for the CCU trap signal is enabled STE1 CAPCOM unit shadow latch transfer enable When STE1 is set the content of the compare timer 1 period compare and offset registers CCPH CCPL CCHx CCLx CT1OFH CT1OFL is transferred to its real registers when compare timer 1 reaches the next time the period value operating mode 0 or value 0000y operating mode 1 After the shadow transfer event STE1
126. content of the internal ROM against read out by non authorized people The type of ROM protection protected or unprotected is fixed with the ROM mask Therefore the customer of a C504 2R ROM version has to define whether ROM protection has to be selected or not The C504 2E OTP version allows also program memory protection in several levels see chapter 10 6 The program memory protection for the C504 2E can be activated after programming of the device The C504 2R devices which operate from internal ROM are always checked for correct ROM content during production test Therefore unprotected and also protected ROMs must provide a procedure to verify the ROM content In ROM verification mode 1 which is used to verify unprotected ROMs a ROM address is applied externally to the C504 2R and the ROM data byte is output at port 0 ROM verification mode 2 which is used to verify ROM protected devices operates different ROM addresses are generated internally and the expected data bytes must be applied externally to the device by the manufacturer or by the customer and are compared internally with the data bytes from the ROM After 16 byte verify operations the state of the P3 5 pin shows whether the last 16 bytes have been verified correctly This mechanism provides a very high security of ROM protection Only the owner of the ROM code and the manufacturer who know the content of the ROM can read out and verify it with less effort 4 6 1 Unprot
127. ction of a compare match event which results in changing polarity of a COUTx compare output signal the content of CT1OFH CT10OFL is always added to the actual value of the compare timer 1 The value stored in the offset registers has no effect on the signal generation at the CCx compare outputs If the compare timer 1 offset registers are written always shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 00001 operating mode 1 When the compare timer 1 offset registers are read always shadow latches are accessed Special Function Register CT1OFL Address E6y Reset Value 00y Special Function Register CT1OFH Address E7 y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 E6y d 6 5 4 3 2 1 LSB CTIOFL E7H MSB 6 5 4 3 2 1 0 CT1OFH Bit Function CT1OFL 7 0 8 bit compare timer 1 offset value low byte The 8 bit value in the CT1OFL register is the low part of the offset value for compare timer 1 shadow latch CT10FH 7 0 8 bit compare timer 1 offset value high byte The 8 bit value in the CT1OFH register is the high part of the offset value for compare timer 1 shadow latch In order to generate correct dead times for PWM signals the offset value stored in CT1OFH CT1OFL must be lower than the values stored in the compare registers
128. ctors Each interrupt source has an interrupt vector address associated This vector address is accessed first if the corresponding interrupt is serviced More details about the interrupt servicing are given in section 7 4 Table 7 1 lists these interrupts Table 7 1 Interrupt Vector Addresses Request Flags Interrupt Source Vector Address IEO External interrupt 0 0003H TFO Timer 0 interrupt 000By IE1 External interrupt 1 0013H TF1 Timer 1 interrupt 001By RI TI Serial port interrupt 0023H TF2 EXF2 Timer 2 interrupt 002By IADC A D converter interrupt 0043y IE2 External interrupt 2 004By TRF BCERR CAPCOM emergency interrupt 0053H CT2P Compare timer 2 interrupt 005By CCOF CC2F CCOR CC2R Capture compare match interrupt 0063H CT1FP CT1FC Compare timer 1 interrupt 006By Power down interrupt 007By A special interrupt source is the power down mode interrupt This interrupt is automatically enabled when the C504 is in power down mode and bit EWPD enable wake up from power down mode in SFR PCON1 is set If these two conditions are met and when the oscillator watchdog unit start up phase after a wake up condition INTO 0 is finished the C504 starts with an interrupt at address 007By All other interrupts are now disabled until the RETI instruction of the power down interrupt routine has been executed Semiconductor Group 7 4 1997 10 01 SIEMENS Interrupt System C504 7 3 Interrupt Registers 7 3 1 Interrupt Enable
129. cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition at S5P2 of the preceeding cycle the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine provided this hardware generated LCALL is not blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to registers IEO IE1 or IPO IP1 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IENO IEN1 or IPO IP1 then at least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the CPU The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the previous machine cycle Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be
130. d data address 10y 17y 1 1 Bank 3 selected data address 18y 1Fy OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Set cleared by hardware after each instruction to indicate an odd even number of one bits in the accumulator i e even parity B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 3 1997 10 01 SIEMENS Fundamental Structure C504 2 2 CPU Timing A machine cycle consists of 6 states 12 oscillator periods Each state is divided into a phase 1 half during which the phase 1 clock is active and a phase 2 half during which the phase 2 clock is active Thus a machine cycle consists of 12 oscillator periods numbered S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Each state lasts for two oscillator periods Typically arithmetic and
131. d address input lines AO A7 and A8 A13 A8 A13 must be latched with PALE PSEN 26 Program store enable This input must be at static O level during the whole programming mode PROG 27 Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG EA V pp 29 External access programming voltage This pin must be at 11 5 V Vpp voltage level during programming of an OTP memory byte or lock bit During an OTP memory read operation this pin must be at high level Vip This pin is also used for basic programming mode selection At basic programming mode selection a low level must be applied to EA Vpp P0 7 0 30 37 lO Data lines 0 7 During programming mode data bytes are read or written from or to the C504 2E via the bidirectional D7 0 data lines which are located at port O N C 1 3 6 11 13 Not Connected 28 38 44 These pins should not be connected in programming mode 2 Input O Output Semiconductor Group 10 4 1997 10 01 SIEMENS OTP Memory Operation C504 10 4 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts Basic programming mode selection Access mode selection With the basic programming mode selection the device is put into the mode in whi
132. d into push pull mode and starts driving an initial logic level as defined by the bits of the COINI register The value of the bits of COINI may be is further selectively switched to the compare outputs during the trap state Bit COUTXI controls an inverter for the COMP unit output signal when it is wired to the CCx and COUTx outputs in burst or multi channel PWM mode COUTSI defines the initial logic level at COUTS before compare timer 2 is started as well as the logic state when COUTS is disabled by setting bit ECT2O in SFR CT2CON see figure 6 27 The COINI register should be written prior to the starting of the compare timers Any write operation to the COINI register when the compare timer is running will affect the compare output signals immediately and drive the logic value as defined by the bits of COINI A PWM output signal of the C504 basically consists of two phases an inactive phase and an active phase The inactive phase of a PWM output signal is defined by the bit in the register COINI A 1 in a bit location 0 to 5 of COINI defines the high level of the corresponding PWM compare output signal as its inactive phase With a 0 in a bit location of COINI a low level is selected as inactive phase Special Function Register COINI Address E2 Reset Value FFy Bit No MSB LSB 7 6 5 4 3 2 1 0 E2H COUT3I COUTXI COUT2I CC2l COUT1I CCil COUTO ccol COINI CAPCOM CAPCOM CAPCOM Channel 2 Channel
133. ddress output and two lines of port 3 P3 6 WR INT2 P3 7 RD for control to access up to 64 KB of external memory If the XRAM is enabled and if the effective address stored in DPTR is in the range of 0000y to FEFFy these instruction will access external memory If XRAM is enabled and if the address is within FFOOy to FFFFy the physically internal XRAM of the C504 will be accessed External memory which is located in this address range cannot be accessed in this case because no external bus cycles will generated Therefore port 0 2 and 3 can be used as general purpose O if only the XRAM memory space is addressed by the user program 3 4 3 Accesses to XRAM using the Registers RO R1 8 bit Addressing Mode The C504 architecture provides also instructions for accesses to external data memory and XRAM which use an 8 bit address indirect addressing with registers RO or R1 These instructions are MOVX A QhRi Read MOVX QhRiA Write Using these instructions with the XRAM disabled implies that port 0 is used as address data bus port 2 for high address output and two lines of port 3 P3 6 WR INT2 P3 7 RD for control Normally these instructions are used to access 256 byte pages of external memory If the XRAM is enabled these instruction will only access the internal XRAM External memory cannot be accessed in this case because no external bus cycle will be generated Therefore port 0 2 and 3 can be used as standard O if only
134. e actions occur at S1P1 of the 10th machine cycle after WRITE to SBUF Reception is initiated by the condition REN 1 and R1 0 At S6P2 of the next machine cycle the RX control unit writes the bits 1111 1110 to the receive shift register and in the next clock phase activates RECEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shifted to the left one position The value that comes in from the right is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bit comes in from the right 1s shift out to the left When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register it flags the RX control block to do one last shift and load SBUF At S1P1 of the 10th machine cycle after the write to SCON that cleared RI RECEIVE is cleared and RI is set Semiconductor Group 6 89 1997 10 01 SIEMENS On Chip Peripheral Components C504 Internal Bus RXD P3 0 Alt Output Function TXD P3 1 Alt Output Serial Function Port Interrupt Start RI Receive RX Control RXD P30 Alt Input Function Read SBUF Internal Bus 2 MCS02101 Figure 6 36a Serial Interface Mode 0 Functional Diag
135. e control signals ALE and PSEN hold at logic high levels Table 9 1 Status of External Pins During Idle and Power Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT2 Data Data Address Data PORT3 Data alternate Data last output Data alternate Data last output outputs outputs Semiconductor Group 9 3 1997 10 01 SIEMENS Power Saving Modes C504 As in normal operation mode the ports can be used as inputs during idle mode Thus a capture or reload operation can be triggered the timers can be used to count external events and external interrupts will be detected The idle mode is a useful feature which makes it possible to freeze the processor s status either for a predefined time or until an external event reverts the controller to normal operation as discussed below The watchdog timer is the only peripheral which is automatically stopped during idle mode The idle mode is entered by two consecutive instructions The first instruction sets the flag bit IDLE PCON 0 and must not set bit IDLS PCON 5 the following instruction sets the start bit IDLS PCON 5 and must not set bit IDLE PCON 0 The hardware ensures that a concurrent setting of both bits IDLE and IDLS does not initiate the idle mode Bits ID
136. e eee eee 10 5 10 4 2 OTP Memory Access Mode Selection 0002 cece eee eee 10 6 10 5 Program Read OTP Memory Bytes 0 00 e eee eee eee 10 7 10 6 Lock Bits Programming Read unu beets Le pi kde Biba as eee ee 10 9 10 7 ACCESS of Version BYIGS custo e hod atksad avis tlie ou eed A oot fee 10 11 11 Device Specifications 2 5ecm nate weet sesame ee Ree 11 1 11 1 Absolute Maximum Ratings v2 5 sore eee e dee oh ee Mee 11 1 11 2 DE Characteristics etus ae eem E DONG teense Wun d ee MR eee Bees QUO Oe 11 2 11 3 A D Converter Characteristics liliis 11 6 11 4 AC Characteristics for C504 L C504 2R C504 2E 2 eee 11 8 11 5 AC Characteristics for C504 L24 C504 2R24 C504 2E24 11 10 11 6 AC Characteristics for C504 L40 C504 2R40 C504 2E40 11 12 11 7 AC Characteristics of Programming Mode 0 000 e eee eee eee 11 16 Semiconductor Group l 3 1997 10 01 SIEMENS General Information C504 Table of Contents Page 11 8 ROM OTP Verification Characteristics for C504 2R C504 2E 11 20 11 9 Package IntormaltlOni a shes goede edeeniaedG a 11 23 12 ls APA cout eee ee ERES E eae eee RE eee ets 12 1 13 Microelectronics Training Center 0000 cece ee eee eee eee 13 1 Information on Literature Semiconductor Group Addresses Semiconductor Group 4 1997 10 01 SIEMEN Introduction P C504 1 Introduction The C504 is a modified and ex
137. e operation with the same BCON bit pattern of the first write operation but with BCEN set After this second BCON write operation compare timer 1 can be started setting CT1R in CT1CON and thereafter BCM1 0 can be put into another mode than idle mode Semiconductor Group 6 69 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 4 2 Signal Generation in Multi Channel PWM Modes The multi channel PWM modes of the C504 use the pins CCx and COUTx for compare output signal generation Before signal generation of a multi channel PWM mode can be started the COINI register should be programmed with the logic value of the multi channel PWM inactive phase After this the output pins which are required for the multi channel PWM signal generation must be programmed to operate as compare outputs by writing the mode select registers CMSELO and CMSEL1 Table 6 8 shows the CMSELO CMSEL1 register bits which are required for the full operation of the multi channel PWM modes Table 6 8 Programming of Multi Channel PWM Compare Outputs Multi Channel PWM Mode CMSEL1 CMSELO Block commutation XXXX YO11p Y011 YO11p 6 phase multi channel PWM 5 phase multi channel PWM Y010 YO11p 4 phase multi channel PWM Y010 YOO1p Note The abbreviation X means don t care The abrevation Y bit CMSELx 3 represents the burst mode bit If Y 0 the signal generation at the COUTx pins is controlled by compare timer 1 If Y 1 the signal
138. e used as analog inputs via the register P1ANA The functions are assigned to the pins of port 1 as follows 40 P1 0 ANO T2 Analog input channel 0 input to counter 2 41 P1 1 AN1 T2EX Analog input channel 1 capture reload trigger of timer 2 up down count 42 P1 2 AN2 CC0 X Analog input channel 2 input output of capture compare channel 0 43 P1 3 AN3 COUTO Analog input channel 3 output of capture compare channel 0 44 P1 4 CC1 Input output of capture compare channel 1 1 P1 5 COUT1 Output of capture compare channel 1 2 P1 6 CC2 Input output of capture compare channel 2 3 P1 7 COUT2 Output of capture compare channel 2 RESET 4 RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vas permits power on reset using only an external capacitor to Voc Input O Output Semiconductor Group 1 5 1997 10 01 IE Introduction SIEMENS i Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number O Function P MQFP 44 P3 0 P3 7 5 7 13 O Port3 is an 8 bit bidirectional port P3 0 RxD and P3 1 TxD operate as defined for the C501 P3 2 to P3 7 contain the external interrupt inputs timer inputs input and as an additional optinal function four of the analog inputs of the A D converter Port 3 pins are assigned to be used as analog inputs by the bits of SFR P3ANA P3 6 WR can be assig
139. ected ROM Mode If the ROM is unprotected the ROM verification mode 1 as shown in figure 4 3 is used to read out the content of the ROM see also the AC specifications in chapter 10 not valid for C504 2E P1 0 P1 7 27 0 P25 Data OUT Inputs PSEN P2 6 Vos ALE EA Vy UNS CS a RESET Wy MCD02593 Figure 4 3 ROM Verification Mode 1 ROM verification mode 1 is selected if the inouts PSEN ALE EA and RESET are put to the specified logic level P2 6 and P2 7 must be held at low level Whenever the 14 bit address of the internal ROM byte to be read is applied to the port 1 and port 2 after a delay time port 0 outputs the content of the addressed internal program memory cell In ROM verification mode 1 the C504 2R must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines Semiconductor Group 4 6 1997 10 01 SIEMENS External Bus Interface C504 4 6 2 Protected ROM OTP Mode If the C504 2R ROM is protected by mask or C504 2E OTP in protection level 1 the ROM OTP verification mode 2 as shown in figure 4 4 is used to verify the content of the ROM OTP The detailed timing characteristics of the ROM OTP verification mode is shown in the AC specifications chapter 11 RESET BD 1 ALE Pulse affer Reset 7A i Data for Data for Data for Data for Data for Data for Addr X 16 Addr 0 Addr 1 Addr 2 Addr X 16 1 Addr X 16 1 Low Verify Error Hihg Verity OK Inputs ALE Kes
140. ection 6 3 4 for more detailed information Mode 2 9 Bit USART Fixed Baud Rate 11 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmit the 9th data bit TB8 in SCON can be assigned to the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On receive the 9th data bit goes into RB8 in special function register SCON while the stop bit is ignored The baud rate is programmable to either z or of the oscillator frequency See section 6 3 5 for more detailed information Mode 3 9 Bit USART Variable Baud Rate 11 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is variable See section 6 3 5 for more detailed information In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incomming start bit if REN 1 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other mode
141. el specific interrupts can be generated at a match event between compare register content and compare timer 1 count value during the up or down counting phase of compare timer 1 In capture mode capture channel specific interrupts can be generated selectively at rising or falling or both edges of the capture input signals at CCx Special Function Registers CCIE Address D6y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D6y ECTP ECTC CC2FEN CC2REN CC1FEN CC1REN CCOFEN CCOREN CCIE Bit Function ECTP Enable compare timer 1 period interrupt If ECTP 0 the compare timer 1 period interrupt is disabled Compare timer 1 operating mode 0 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value Compare timer 1 operating mode 1 If ECTP 1 an interrupt is generated when compare timer 1 reaches the period value and changes the count direction from up to down counting ECTC Enable compare timer 1 count direction change interrupt status If ECTC 0 the compare timer 1 count change interrupt is disabled Compare timer 1 operating mode 0 Bit has no effect on the interrupt generation Compare timer 1 operating mode 1 If ECTC 1 an interrupt is generated when compare timer 1 reaches count value 0000y and changes its count direction from down to up counting Semiconductor Group 6 56 1997 10 01 SIEMENS On Chip Peripheral C
142. ely after reset After the reset calibration a second calibration mechanism is initiated This calibration is coupled to each A D conversion With this second calibration mechanism alternatively offset and linearity calibration values stored in the calibration RAM are always checked when an A D conversion is executed and corrected if required Semiconductor Group 6 108 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 6 A D Converter Analog Input Selection The analog inputs are located at port 1 and port 3 4 lines on each port The corresponding port 1 and port 3 pins have a port structure which allows to use it either as digital I Os or analog inputs see section 6 1 3 2 and 6 1 3 4 The analog input function of these digital analog port lines is selected via the registers P1ANA and P3ANA These two registers are mapped registers and can be accessed when bit RMAP in SFR SYSCON is set when writing to its address 90y or BOW If the specific bit location of P1 ANA or P3ANA is set the corresponding port line is configured as an digital input With a O in the bit location the port line operates as analog port Special Function Registers P1ANA Mapped Address 90 Reset Value XXXX1111p Special Function Registers P3ANA Mapped Address B0 Reset Value XX1111XXp Bit No MSB LSB 7 6 5 4 3 2 1 0 90H EAN3 EAN2 EAN1 EANO P1ANA Bow E
143. epends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to the registers IEN or IP the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 7 15 1997 10 01 SIEMENS Fail Safe Mechanisms C504 8 Fail Safe Mechanisms The C504 offers enhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 512 us up to approx 1 1 s at 12 MHz an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also provides the clock for a fast internal reset after power on 8 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear the watchdog within a previously programmed time period If the software fails to do this periodical refresh of the Watchdog Timer an internal hardw
144. er Condition Register 9AH 00101010 Ports PO Port 0 80H FFH P1 Port 1 90H FFH P1ANA Port 1 Analog Input Selection Register 904 29 XXXX1111p P2 Port 2 A0y FFH P3 Port 3 Boy FFH P3ANA Port 3 Analog Input Selection Register BOQ 9 XX1111XXp A D ADCONO A D Converter Control Register 0 D8y XX000000p Converter ADCON A D Converter Control Register 1 DCH 01XXX000p ADDATH A D Converter Data Register High Byte D9H 00H ADDATL A D Converter Data Register Low Byte DAH 00XXXXXXp P1ANA Port 1 Analog Input Selection Register 90y XXXX1111p PSANA Port 3 Analog Input Selection Register BOH 9 XX1111XXp Serial PCON Power Control Register 87H 000X0000p Channels SBUF Serial Channel Buffer Register 99H XXH 9 SCON _ Serial Channel Control Register 98H 00H Timer 0 TCON Timer 0 1 Control Register 88H 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 89H 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 10 01 SIEMENS Memory Organization C504 Table 3 1 Special Function Registe
145. er having been set and the value shown by reading one of these bits is always 0 This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly freeze the chip s activity in an undesired status PCON is not a bit addressable register so the above mentioned sequence for entering the power down mode is obtained by byte handling instructions as shown in the following example ORL PCON 00000010B set bit PDE bit PDS must not be set ORL PCON 01000000B set bit PDS bit PDE must not be set enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode When the double instruction sequence shown above is used and when bit EWPD in SFR PCON1 is 0 the power down mode can only be left by a reset operation If the external wake up from power down capability should be used its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above ORL SYSCON 00010000B set RMAP ORL PCON 1 280H enable external wake up from power down by setting EWPD ANL SYSCON 211101111B reset RMAP for future SFR accesses Notes Before entering the power down mode an A D conversion in progress should be stopped Further the port latch of SFR P3 2 P3 2 INTO pin should contain a 1 pin operates as input Otherwise the wake up sequence discussed in the next chapter will be st
146. eset operation the A D calibration is automatically started This reset calibration phase which takes 3328 fapc clocks alternating offset and linearity calibration is executed Therefore at 12 MHz oscillator frequency and with the default after reset prescaler value of 8 a reset calibration time of approx 4 4 ms is reached For achieving a proper reset calibration the fApc prescaler value must satisfy the condition fapc max 2 MHz If this condition is not met at a specific oscillator frequency with the default prescaler value after reset the fApc prescaler must be adjusted immediately after reset by setting bits ADCL1 and ADCLO im SFR ADCON 1 to a suitable value After the reset calibration phase the A D converter is calibrated according to its DC characteristics Nevertheless during the reset calibration phase single or continuous A D can be executed In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A D conversion Therefore interrupting the reset calibration phase by A D conversions extends the total reset calibration time If the specified total unadjusted error TUE has to be valid for an A D conversion it is recommended to start the first A D conversions after reset when the reset calibration phase is finished Depending on the oscillator frequency used the reset calibration phase can be possibly shortened by setting ADCL1 and ADCLO prescaler value to its final value immediat
147. every six oscillator periodes except during external data memory accesses Remains high during internal program execution ALE 27 O The Address Latch Enable output is used for latching the low byte of the address into external memory during normal operation It is activated every six oscillator periodes except during an external data memory access When instructions are executed from internal ROM EA 1 the ALE generation can be disabled by bit EALE in SFR SYSCON 2 Input O Output Semiconductor Group 1 7 1997 10 01 IE Introduction SIEMENS ia Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number l O Function P MQFP 44 COUT3 28 O 10 Bit compare channel output This pin is used for the output signal of the 10 bit compare timer 2 unit COUT3 can be disabled and set to a high or low state EA 29 External Access Enable When held at high level instructions are fetched from the internal ROM C504 2R only when the PC is less than 40004 When held at low level the C504 fetches all instructions from external program memory For the C504 L this pin must be tied low P0 0 P0 7 30 37 O Porto is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and in that state can be used as high impendance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory In this application i
148. f 4 pole 6 80 6 81 New chapter 6 3 4 5 added 7 3 7 3 Figure 7 2 7 1b address of bit EA in corrected 7 14 7 13 External interrupts description of the TCON bits added 9 1 9 1 Corrected text in 1st paragraph PCON PCON1 have differert addr 11 2 10 2 Vpp specification added 11 3 11 4 11 3 New improved lcc specification added 11 15 to AC charcteristics of programming mode added 11 18 Ch 12 Ch 11 Improved index with bold page numbers for main reference pages several several Writing errors corrected Semiconductor Group SIEMENS General Information C504 Table of Contents Page 1 Introduction esc scious ee oleae te Sie eae cu E gee M 1 1 1 1 Pin Configuration ssec vibus ice Sete cei Date Pee ete eee eae bade dead 1 4 1 2 Pin Definitions and Functions sso250esS ese 65 65S As 1 5 2 Fundamental Structure 0 000 e eee eee eee 2 1 2 1 A aU de desire At elt es tag 2 2 2 2 GPU TIMING urs aur ateta atic ecneautate CREER Gere ial aw aia are DATE IR CREATURE Ter 2 4 3 Memory Organization A AA 3 1 3 1 Program Memory Code Space viril rabia 3 2 3 2 Data Memory Data Space an io dd ya E A de cR do 3 2 3 3 General Purpose Registers nananana eea 3 2 3 4 XRAM Operation 2 5 84 Si OW Dod toe net Ce elas OR ar a la and eaae on 3 3 3 4 1 Reset Operation of the XRAM 00 0c cee eee eee 3 3 3 4 2 Accesses to XRAM using the DPTR 16 bit Addressing Mode 3 4 3 4 3 Accesses t
149. fail of the last 16 verify operations is output at P3 5 P3 5 is always set or cleared after each 16 byte block of the verify sequence In ROM OTP verification mode 2 the C504 must be provided with a system clock at the XTAL pins Figure 4 5 shows an application example of a external circuitry which allows to verify a protected ROM OTP inside the C504 in ROM OTP verification mode 2 With RESET going inactive the C504 starts the ROM OTP verify sequence Its ALE is clocking an 14 bit address counter This counter generates the addresses for an external EPROM which is programmed with the content of the internal protected ROM OTP The verify detect logic typically displays the state of the verify error output P3 5 P3 5 can be latched with the falling edge of ALE When the last byte of the internal ROM OTP has been handled the C504 starts generating a PSEN signal This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM OTP verification CY Address Counter C504 2R C504 2E Compare Code MCB02595 Figure 4 5 ROM OTP Verification Mode 2 External Circuitry Example Semiconductor Group 4 8 1997 10 01 SIEMENS Reset System Reset C504 5 Reset and System Clock Operation 5 1 Hardware Reset Operation The hardware reset function incorporated in the C504 allows an easy automatic start up at a minimum of additional hardware
150. five waveforms are assigned to a CCx pin with the appropriate bit in COINI cleared while the lower five waveforms are assigned to a CCx pin with the appropriate bit in COINI set When the count value of the compare timer 1 is incremented and the new value matches with the value stored in the corresponding compare register the related compare output changes its logic state When the compare timer is reset to 0000p the related compare output changes its logic state again With the scheme shown in figure 6 21 output waveforms with duty cycles between 0 and 100 can be generated For a compare register value of 0000 the output will remain at high level COINI bit 0 or low level COINI bit 1 representing a duty cycle of 100 If the value stored in the compare register is higher than the value of the period register a low level COINI bit 0 or high level COINI bit 1 corresponds to a duty cycle of 0 Figure 6 22 shows the waveform generation in operating mode 0 when the offset register has a value which is not equal 00004 example CT1OFH CT10OFL 00024 Using compare timer 1 with an offset value not equal 0 is used to generate single edge aligned signals with a constant delay between one of the two signal transitions Compare timer 1 always counts from 0000 up to the value stored in CCP also if the value in the offset register is not equal 0 With reset count value 0000p of the compare timer 1 the CCx and COUTx will always change their
151. g addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren t being addressed leave their SM2s set and go on about their business ignoring the incoming data bytes SM2 has no effect in mode 0 and in mode 1 can be used to check the validity of the stop bit In a mode 1 reception if SM2 1 the receive interrupt will not be activated unless a valid stop bit is received 6 4 2 Serial Port Registers The serial port control and status register is the special function register SCON This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and RB8 and the serial port interrupt bits Tl and RI SBUF is the receive and transmit buffer of serial interface 0 Writing to SBUF loads the transmit register and initiates transmission Reading out SBUF accesses a physically separate receive register Semiconductor Group 6 83 1997 10 01 SIEMENS On Chip Peripheral Components C504 Special Function Register SCON Address 98 Reset Value 00 Special Function Register SBUF Address 99 Reset Value XXy BitNo MSB LSB 9Fy 9Ey 9Dy 9CH 9BH 9AH 99H 98H 98H SMO SM1 SM2 REN TB8 RB8 TI RI SCON 7 6 5 4 3 2 1 0 99H Serial Interface 0 Buffer Register SBUF Bit Function SMO Serial port 0 operating mode selection bits SM1 S
152. generation at the COUTx pins is also controlled by compare timer 1 but modulated by compare timer 2 Output signals during the active phase An active phase of a compare output signal in multi channel PWM mode can be controlled either by the CAPCOM unit compare timer 1 and or modulated by compare timer 2 The selection is done by bit CMSELx 3 see note below table 6 8 Figure 6 29 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 1 Compare timer 1 may operate either in mode 0 or mode 1 In multu phase mode the block commutation logic switches from one state to the next state when compare timer 1 reaches the value 0000p As an active phase lasts always two states the duration of an active phase is determined by compare timer 1 reaching 0000 twice As shown in figure 6 29a a compare output signal CCx or COUTx of a CAPCOM channel is either at low or high level during the whole active phase when the value stored in the compare timer 1 offset registers CT1OFH CT1OFL and the value stored in its compare registers CCHx CCLx is equal 00004 When the compare value is not equal 0000y and less or equal the period value the active phase of the related compare output signal CCx or COUTx is controlled by the CAPCOM unit as shown in figure 6 29b Semiconductor Group 6 70 1997 10 01 SIEMENS On Chip Peripheral Components C504 a No transitions in active phase offset and co
153. gnal to COUTx x 0 2 If CMSELx3 is set and compare mode is selected for the outputs COUTx the output signal of the 10 bit compare unit typically a higher frequency signal is switched modulated to the COUTx pin The state of the corresponding COINI bit at the start of compare timer 1 defines the logic level of the CAPCOM channel output signal at iwhich the COMP output signal is output to COUTx COINI is set The COMP output is switched to COUTx during the low phase of the CAPCOM channel X signal COINI is cleared The COMP output is switched to COUTx during the high phase of the CAPCOM channel X signal Semiconductor Group 6 51 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function CMSELx2 0 CAPCOM capture compare mode enable bits x 0 2 The CMSEL registers are used to select enable the operating mode and the output input pin configuration of the capture compare channels Each CAPCOM channel can be programmed individually either for compare or capture operation CMSEL x2 CMSEL x1 CMSEL x0 Mode Compare outputs disabled No compare output signal is generated CCx and COUTx are normal I O pins Compare output on pin CCx enabled COUTx is normal I O pin Compare output on pin COUTx enabled CCx is normal I O pin Compare outputs on pins CCx and COUTx enabled Capture mode enabled signal transitions at CCx do not generate a capture event COUTx is a norm
154. h is defined by the bits in SFR COINI Equal to operating mode 0 two compare output signals are assigned to the related CAPCOM channel CCx and COUTx The compare outputs CCx change their state if a match of compare timer 1 content and the corresponding compare register occurs The compare outputs COUTx change their state when a match of compare timer 1 content plus the value stored in the offset registers and the corresponding compare register has occurred If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register a static 1 or a static O depending on COINI content will be generated at COUTx In the same way CCx will also stay at a static level is the compare register value is greater than the value stored in the period register Semiconductor Group 6 39 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 4 CAPCOM Unit Timing Relationships Depending on the operating mode of the compare timer 1 compare output signals can be generated with a maximum period and resolution as shown in figure 6 24 This example also demonstrates the reloading of the compare and period registers which occurs when compare timer 1 reaches the count value 0000 Operating Mode 0 Load Reg with Load Reg with Count A CCx Reg 2 CCx Reg 2 Value Start of CT CC xReg 1 CCP 1 min 100 ns 8 40 MHz clock rate Operating Mode 1 Load
155. hannel interrupt is enabled ET1 Timer 1 overflow interrupt enable If ET1 1 the Timer 1 interrupt is enabled EX1 External interrupt 1 enable If EX1 1 the external interrupt 1 is enabled ETO Timer 0 overflow interrupt enable If ETO 1 the Timer 0 interrupt is enabled EXO External interrupt 0 enable If EXO 1 the external interrupt 0 is enabled Semiconductor Group 7 5 1997 10 01 SIEMENS Interrupt System C504 Special Function Registers IEN1 Address A9j Reset Value XX000000p Bit No MSB LSB 7 5 4 3 2 1 0 A9H ECT1 ECCM ECT2 ECEM EX2 EADC IEN1 Bit Function Reserved bits for future use ECT1 Compare Timer 1 Interrupt enable If ECT1 1 the compare timer 1 interrupt is enabled ECCM Capture compare match interrupt If ECCM 1 the capture compare interrupt is enabled ECT2 Compare timer 2 interrupt enable If ECT2 1 the compare timer 2 interrupt is enabled ECEM CCU emergency interrupt enable If ECEM 1 the emergency interrupt of the CCU is enabled EX2 Timer 2 Interrupt Enable If EX2 1 the external interrupt 2 is enabled EADC A D converter interrupt enable If EADC 1 the A D Converter interrupt is enabled Semiconductor Group 7 6 1997 10 01 SIEMENS Interrupt System C504 7 3 2 Interrupt Prioritiy Registers Each interrupt source can also be individually programmed to one of two priority levels b
156. has occured after the last reset operation By writing ADDATL with dummy data after bit ADM has been set before if no A D conversion has occured after the last reset operation When bit ADM is reset by software in continuous conversion mode the just running A D conversion is stopped after its end Semiconductor Group 6 102 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 5 3 A D Converter Clock Selection The ADC uses two clock signals for operation the conversion clock fApc 1 tapc and the input clock fi 21 tjN Both clock signals are derived from the C504 system clock fosc which is applied at the XTAL pins The input clock fiy is always fosc 2 while the conversion clock must be adapted to the input clock fosc The conversion clock is limited to a maximum frequency of 2 MHz Therefore the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz The prescaler ratio is selected by the bits ADCL1 and ADCLO of SFR ADCON1 The table in figure 6 40 shows the prescaler ratio which must be selected for typical system clock rates Up to 16 MHz system clock the prescaler ratio 4 is selected Up to 32 MHz a prescaler ratio of at least 8 must be selected and beyond 32 MHz the prescaler ratio 16 has to be selected The prescaler ratio 32 can be selected when the maximum performance of the A D converter is not necessarily required or the input impedance of the analog source is
157. he inverting oscillator amplifier XTAL1 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed P2 0 P2 7 18 25 O Port 2 is a bidirectional I O port with internal pullup resistors Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current J in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup resistors when issuing 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register PSEN 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated
158. her modes All other trap functions of the multi channel PWM modes are identical as described in chapter 6 3 2 7 Semiconductor Group 6 81 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 Serial Interface USART The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The serial port receive and transmit registers are both accessed at special function register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register The serial port can operate in 4 modes one synchronous mode three asynchronous modes Mode 0 Shift Register Synchronous Mode Serial data enters and exits through RXD TXD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at of the oscillator frequency See section 6 3 3 for more detailed information Mode 1 8 Bit USART Variable Baud Rate 10 bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in special function register SCON The baud rate is variable See s
159. how an A D conversion is embedded into the microcontroller cycle scheme using the relation 6 x t y 1 instruction cycle It also shows the behaviour of the busy flag BSY and the interrupt flag IADC during an A D conversion Prescaler Selection Write Result Cycle ADCL1 ADCLO MOV ADDATL 0 1 Instruction Cycle MOV A ADDATL 055900 IO A CC GA GA RE A A Start of next Start of A D i Conversion in tance x continuous mode A D Conversion Cycle py Write ADDAT BSY Bit IF 7 T 7 Cont Conv Single Conv SS esp Conversion Cycle 2 IADC Bit First Instruction of an Interrupt Routine MCT02620 Figure 6 42 A D Conversion Timing in Relation to Processor Cycles Depending on the selected prescaler ratio see figure 6 40 four different relationships between machine cycles and A D conversion are possible The A D conversion is started when SFR ADDATL is written with dummy data This write operation may take one or two machine cycles In figure 6 42 the instruction MOV ADDATL 0 starts the A D conversion machine cycle X 1 and X The total A D conversion sample conversion and calibration phase is finished with the end of the 8th 16th 32th or 64th machine cycle after the A D conversion start In the next machine cycle the conversion result is written into the ADDAT registers and can be read in the same cycle by an instruction e g MOV A ADD
160. ic transfer of the shadow latches to the real registers bit STE2 is reset by hardware When the compare timer 2 period and compare registers are initialized after reset bit STE2 must also be set to enable the shadow latch transfer when compare timer 2 is started the first time Note Read operations with the compare timer 2 period and compare registers always access the shadow registers and not the real registers Semiconductor Group 6 62 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Control Register The 10 bit compare timer 2 is controlled by the bits of the CT2CON register With this register the count mode the timer input clock rate and the compare timer reset function is controlled Special Function Register CT2CON Address C1 Reset Value 00010000B Bit No MSB LSB 6 5 4 3 2 1 0 Ciy CT2P ECT2O STE2 CT2RES CT2R CLK2 CLK1 CLKO CT2CON Bit Function CT2P Compare timer 2 period flag When the compare timer 2 value matches with the compare timer 2 period register value bit CT2P is set If the compare timer 2 interrupt is enabled the setting of CT2P will generate a compare timer 2 interrupt Bit CT2P must be cleared by software ECT2O Enable compare timer 2 output When ECT20 is cleared and compare timer 2 is running output COUTS is put into the logic state as defined by bit COUTSI which is located in SFR COINI 6 When ECT20 is set and c
161. idth foit 215 l 3tac 35 ns PSEN to valid instr in iy 150 3tcre 100 ns Input instruction hold after PSEN devin 0 0 ns Input instruction float after PSEN tpxiz 63 foie 20 ns Address valid after PSEN A 75 toc 8 ns Address to valid instr in tavy 302 Stoic 115 ns Address float to PSEN Loa 0 0 ns Interfacing the C504 to devices with float times up to 75 ns is permissible This limited bus contention will not cause any damage to port O drivers Semiconductor Group 1997 10 01 SIEMENS Device Specifications C504 AC Characteristics for C504 L C504 2R C504 2E cont d External Data Memory Characteristics Parameter Symbol Limit Values Unit 12 MHz clock Variable Clock 1 tcrc 3 5 MHz to 12 MHz min max min max RD pulse width fa RH 400 Gforce 100 ns WR pulse width fwLwH 400 Gforce 100 ns Address hold after ALE fiLax2 114 2tac 53 ns RD to valid data in fRLDv 252 Stoic 165 ns Data hold after RD RHDX 0 0 ns Data float after RD tRHpz 97 2tac 70 ns ALE to valid data in fiLov 517 8toic 150 ns Address to valid data in Tavov 585 9t cg 165 ns ALE to WR or RD fiw 200 300 Stoic 50 3fcrc 50 ns Address valid to WR or RD Tavwe 203 Afore 130
162. ific timing parameter as shown in figure 6 41 Start of Result is written A D Conversion into ADDAT BSY Bit Conversion Phase Write Result Phase fyr a fco fanc fwr fin A D Conversion Cycle Time tance ts fco PS Prescaler Value MCT02619 Prescaler Ratio ts tco PS 2x PS x tin 32 64 x tin 16 32 X tin 8 16 x tin 4 8 X tin Figure 6 41 A D Conversion Timing Sample Time ts During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted The analog voltage is internally fed to a voltage comparator With beginning of the sample phase the BSY bit in SFR ADCONO is set Semiconductor Group 6 104 1997 10 01 SIEMENS On Chip Peripheral Components C504 Conversion Time tco During the conversion time the analog voltage is converted into a 10 bit digital value using the successive approximation technique with a binary weighted capacitor network During an A D conversion also a calibration takes place During this calibration alternating offset and linearity calibration cycles are executed see also section 6 5 5 At the end of the conversion time the BSY bit is reset and the IADC bit in SFR ADCONO is set indicating an A D converter interrupt condition Write Result Time twp At the result phase the conversion result is written into the ADDAT registers Figure 6 42 shows
163. inactive active active inactive 2 4 0 5 4 inactive inactive active active 3 1 0 5 5 inactive active inactive active 2 1 0 5 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Table 6 11 5 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO COUT1 CC2 COUTO COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive inactive 2 1 0 6 1 active inactive inactive inactive active 5 2 0 6 2 active active inactive inactive inactive 1 3 0 6 3 inactive active active inactive inactive 2 4 0 6 4 inactive inactive active active inactive 3 5 0 6 5 inactive inactive inactive active active 4 1 0 6 6 inactive active inactive active active 2 1 0 6 Note In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI During the active phase the PWM outputs can be modulated by CT1 and or CT2 Semiconductor Group 6 78 1997 10 01 SIEMENS On Chip Peripheral Components C504 Table 6 12 6 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO CCO CO
164. is set at a low to high transition rising edge of the corresponding CCx capture input signal Compare Mode CCxXR is set if the compare timer 1 value matches the compare register CCx value during the up count phase Semiconductor Group 6 54 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function CCxF Capture compare match on down count flag x 0 2 Capture Mode CC xF is set at a high to low transition falling edge of the corresponding CCx capture input signal Compare Mode CCxF is set if the compare timer 1 value matches the compare register CCx value during the down count phase only in compare timer 1 operating mode 1 Semiconductor Group 6 55 1997 10 01 SIEMENS On Chip Peripheral Components C504 Capture Compare Interrupt Enable Register The bits of the interrupt enable register CCIE control the specific interrupt enable disable functions of the CAPCOM part of the capture compare unit The bits ECTP and ECTC control the compare timer 1 period count change interrupt Depending on the mode in which compare timer 1 is running interrupts can be generated at a period match or a count direction change event The lower 6 bits of CCIE are the CAPCOM channel specific interrupt enable disable control bits for the capture or compare match interrupt The functions of these bits depend on the selected mode capture or compare of a capture compare channel In compare mode compare chann
165. it shift register to TXD The first shift pulse occurs one bit time after that As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10th divide by 16 rollover after WRITE to SBUF Reception is initiated by a detected 1 to 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset and 1FFy is written into the input shift register and reception of the rest of the frame will proceed The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at latest 2 of the 3 samples This is done for the noise rejection If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection or false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the
166. its own port latch and the address data signal drives both FETs in the port 0 output buffers Thus in this application the port O pins are not open drain outputs and do not require external pullup resistors During any access to external memory the CPU writes FF to the port 0 latch the special function register thus obliterating whatever information the port 0 SFR may have been holding Whenever a 16 bit address is used the high byte of the address comes out on port 2 where it is held for the duration of the read or write cycle During this time the port 2 lines are disconnected from the port 2 latch the special function register Thus the port 2 latch does not have to contain 1s and the contents of the port 2 SFR are not modified If an 8 bit address is used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle This will facilitate paging It should be noted that if a port 2 pin outputs an address bit that is a 1 strong pullups will be used for the entire read write cycle and not only for two oscillator periods Semiconductor Group 4 1 1997 10 01 SIEMENS External Bus Interface C504 Timing The timing of the external bus interface in particular the relationship between the control signals ALE PSEN RD WR and information on port 0 and port 2 is illustrated in figure 4 1 a and b Data memory in a write cycle the data byte to be written appears on port 0 just before
167. l port modes 1 and 3 RCLK 0 causes timer 1 overflows to be used for the receive clock TCLK Transmit Clock Enable When set causes the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3 TCLK O causes timer 1 overflow to be used for the transmit clock EXEN2 Timer 2 External Enable When set allows a capture or reload to occur as a result of a negative transition on pin T2EX P1 1 if timer 2 is not being used to clock the serial port EXEN2 0 causes timer 2 to ignore events at T2EX TR2 Start Stop Control for Timer 2 TR2 1 starts timer 2 C T2 Timer or Counter Select for Timer 2 C T2 0 for timer function C T2 1 for external event counter falling edge triggered CP RL2 Capture Reload Select CP RL2 1 causes captures to occur an negative transitions at pin T2EX if EXEN2 1 CP RL2 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at pin T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on timer 2 overflow Semiconductor Group 6 27 1997 10 01 SIEMENS On Chip Peripheral Components C504 Special Function Register T2MOD Address C91 Reset Value XXXX XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 C9H DCEN T2MOD Bit Function Not implemented reserved for future use DCEN Whe
168. ly compatible to standard 8051 microcontroller Up to 40 MHz external operating frequency 16K byte on chip program memory C504 2R ROM version with optional ROM protection C504 2E programmable OTP version C504 L without on chip program memory alternatively up to 64K byte external program memory e 256x8 RAM e 256x8 XRAM e Four 8 bit ports 2 ports with mixed analog digital I O capability Three 16 bit timers counters timer 2 with up down counter feature Capture compare unit for PWM signal generation and signal capturing 3 channel 16 bit capture compare unit 1 channel 10 bit compare unit e USART 10 bit A D Converter with 8 multiplexed inputs Twelve interrupt sources with two priority levels On chip emulation support logic Enhanced Hooks Technology Programmable 15 bit Watchdog Timer e Oscillator Watchdog Fast Power On Reset Power Saving Modes e M QFP 44 package e Temperature ranges SAB C504 T 0 to 70 C SAF C504 T4 40to 85 C SAH C504 T4 40to 110 C max operating frequency TBD SAK C504 T4 40to 125 C max operating frequency 12 MHz Semiconductor Group 1 2 1997 10 01 SIEMENS Introduction C504 Figure 1 2 Logic Symbol Semiconductor Group Port 0 8 Bit Digital 1 0 Port 1 8 Bit Digital 1 0 g 4 Bit Analog Inputs gt Port 2 8 Bit Digital 1 0 Port 3 K gt 8 Bit Digital 1 0 4 Bit Analog Inputs MCLO2590 1997 10 01 SIEMENS
169. margin but is optional if Vo of the driving gate corresponds to the V specification of XTAL1 C504 N C XTAL2 External Clock XTAL1 Signal MCS03355 Figure 5 6 External Clock Source Semiconductor Group 5 7 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 On Chip Peripheral Components 6 1 Parallel I O The C504 has four 8 bit I O ports Port 0 is an open drain bidirectional I O port while ports 1 to 3 are quasi bidirectional I O ports with internal pullup resistors That means when configured as inputs ports 1 to 3 will be pulled high and will source current when externally pulled low Port 0 will float when configured as input The output drivers of port O and 2 and the input buffers of port O are also used for accessing external memory In this application port 0 outputs the low byte of the external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the external memory address when the address is 16 bits wide Otherwise the port 2 pins continue emitting the P2 SFR contents In this function port 0 is not an open drain port but uses a strong internal pullup FET 6 1 1 Port Structures The C504 generally allows digital I O on 32 lines grouped into 4 bidirectional 8 bit ports Each port bit consists of a latch an output driver and an input buffer Read and write accesses to the I O ports PO P3 are performed via their corresponding special function regi
170. me Out Period Comments fose 12 MHz fosc 24 MHz 00H 65 535 ms 32 768 ms This is the default value 80H 14s 0 55 s Maximum time period 7FH 512 us 256 us Minimum time period Starting the Watchdog Timer The Watchdog Timer can be started by software bit SWDT in SFR WDCON but it cannot be stopped during active mode of the device If the software fails to clear the watchdog timer an internal reset will be initiated The reset cause external reset or reset caused by the watchdog can be examined by software status flag WDTS in WDCON is set A refresh of the watchdog timer is done by setting bits WDT SFR WDCON and SWDT consecutively This double instruction sequence has been implemented to increase system security It must be noted however that the watchdog timer is halted during the idle mode and power down mode of the processor see section Power Saving Modes Therefore it is possible to use the idle mode in combination with the watchdog timer function But even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally Semiconductor Group 8 3 1997 10 01 SIEMENS Fail Safe Mechanisms C504 8 1 1 Refreshing the Watchdog Timer At the same time the Watchdog Timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the Watchdog Timer cannot be stopped by software but can be refreshed to the reload value only by first setti
171. me the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag Semiconductor Group 8 6 1997 10 01 SIEMENS Fail Safe Mechanisms C504 WDTS is not reset the Watchdog Timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occured The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases the reset request If no external reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Furthermore the status flag OWDS is set if the oscillator watchdog was active The status flag can be evaluated by software
172. mode BCM1 0 0 1 with COINI XX000000g Start Timer 1 gt ECO COUTO COUT2 State No 2 1 5 4 3 2 1 5 4 5 2 MCTO2614 Figure 6 33 Basic Compare Timer 1 Controlled 5 Phase PWM Timing Semiconductor Group 6 76 1997 10 01 SIEMENS On Chip Peripheral Components C504 a Timing in rotate left mode BCM1 0 1 0 with COINI XX111111 B Start Compare Timer 1 gt CCO COUT2 State No 1 2 3 4 5 6 1 2 3 4 5 b Timing in rotate right mode BCM1 0 0 1 with COINI XX000000p Start Compare Timer 1 gt cco COUT2 State No 2 1 6 5 4 3 2 1 6 5 4 MCT02615 Figure 6 34 Basic Compare Timer 1 Controlled 6 Phase PWM Timing Semiconductor Group 6 77 1997 10 01 SIEMENS On Chip Peripheral Components C504 Table 6 10 to 6 12 show as state tables the basic signal pattern definitions of the three multi channel PWM modes They also include the information of the slow down mode and the idle mode bits BMC1 0 0 0 and 1 1 Table 6 10 4 Phase PWM Timing State Table Actual State and PWM Phase Follower State No No Output Signals BCM1 BCMO cco COUT1 CC2 COUT2 0 1 1 0 0 0 1 1 0 inactive inactive inactive inactive 2 1 0 5 1 active inactive inactive active 4 2 0 5 2 active active inactive inactive 1 3 0 5 3
173. mpare timer 2 is derived from the clock rate fosc of CLKO the C504 via a programmable prescaler The following table shows the programmable prescaler ratios CLK2 CLK1 CLKO Function Compare timer 2 input clock is fosc 2 Compare timer 2 input clock is fosc 4 Compare timer 2 input clock is fosc 8 Compare timer 2 input clock is fosc 16 Compare timer 2 input clock is fosc 32 Compare timer 2 input clock is fosc 64 Compare timer 2 input clock is fosc 128 S oO O oO a 0O0 OD CO A O JO O 0O Compare timer 2 input clock is fosc 256 Note With a reset operation external or internal compare timer 2 is reset 000 4 and stopped When software power down mode is entered with CT2RES bit of SFR CT2CON set the compare timer 2 is reset after the execution of a wake up from power down mode procedure When CT2RES is cleared before software power down mode is entered and a wake up from power down mode procedure has been executed the compare timer 2 is not reset Depending on the state of bit CT2R at power down mode entry the compare timer 2 either stops CT2R 0 or continues CT2R 1 counting after a wake up from power down mode procedure Further details of the power down mode are described in chapter 9 2 Semiconductor Group 6 64 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Period Registers The com
174. mpare value 0 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COINI Bit 1 AA BE HN AAMA E p Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COINI Bit 0 AAA b CAPCOM transitions in active phase 0 lt compare value lt period value offset value 0 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COINI Bit 1 YY hctive Phase Figure 6 29 Compare Timer 1 Mode 0 CCx COUTx Compare Timer 1 Mode 1 CCx COUTx COIN Bit 0 Compare Timer 1 Controlled Active Phase of the Multi Channel PWM Modes with CMSELx 3 0 Semiconductor Group MCT02609 1997 10 01 SIEMENS On Chip Peripheral Components C504 Figure 6 30 shows the different possibilities for controlling the active phase of a compare output signal using compare timer 2 In this operating mode which is selected when bit CMSELx 3 is set the compare timer 2 output signal is switched to the COUTx or CCx outputs during the active phase of a multi channel PWM signal Bit BCMP BCON 7 defines whether only COUTx or COUTx and CCx are modulated by the compare timer 2 output signal Depending on the bits COUT3I and COUTXI of COINI the polarity of COUT3 and the switched CCx COUTx active phase signal can be identical or inverted Bit CMSELx 3 1 Compare timer 2
175. mple Times Figure 6 37b Serial Interface Mode 1 Timing Diagram Semiconductor Group 6 94 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 6 Details about Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On transmit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the 9th data bit goes into RB8 in SCON The baud rate is programmable to either 1 32 or 1 64 the oscillator frequency in mode 2 When bit SMOD in SFR PCON 871 is set the baud rate is fosc 32 Mode 3 may have a variable baud rate generated from either timer 1 or 2 depending on the state of TCLK and RCLK SFR T2CON Figure 6 38a shows a functional diagram of the serial port in modes 2 and 3 The receive portion is exactly the same as in mode 1 The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register The associated timings for transmit receive are illustrated in figure 6 38b Transmission is initiated by any instruction that uses SBUF as a destination register The WRITE to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the WRITE to SBU
176. n IE1 External interrupt 1 request flag Set by hardware when an external interrupt 1 is detected In edge triggered mode this bit is reset by hardware when the interrupt is serviced IT1 External interrupt 1 level edge trigger control flag If IT1 0 low level triggered mode for external interrupt 1 is selected If IT1 1 edge triggered mode for external interrupt 1 is selected In this mode bits IXETF and IxETR in SFR ITCON further define the type of the interrupt sensitive edge rising or and falling of external interrupt 1 IEO External interrupt O request flag Set by hardware when an external interrupt 0 is detected In edge triggered mode this bit is reset by hardware when the interrupt is serviced ITO External interrupt O level edge trigger control flag If ITO 0 low level triggered mode for external interrupt 0 is selected If ITO 1 edge triggered mode for external interrupt 0 is selected In this mode bits IXETF and IxETR in SFR ITCON further define the type of the interrupt sensitive edge rising or and falling of external interrupt 0 IT2 External interrupt 2 level edge trigger control flag If IT2 0 low level triggered mode for external interrupt 2 is selected If IT2 2 1 edge triggered mode for external interrupt 2 is selected In this mode bits IXETF and IxETR in SFR ITCON further define the type of the interrupt sensitive edge rising or and falling of external interrupt 2 IE2 External interrupt 2 request flag
177. n max Oscillator period Toei 25 294 ns High time cHcx 10 tore feicx ns Low time feLcx 10 toro toucx ns Rise time cicH 10 ns Fall time cucL 10 ns Semiconductor Group 11 13 1997 10 01 SIEMENS Device Specifications C504 hu MCT00096 Figure 11 2 Program Memory Read Cycle WW NN A0 A7 DatalN JMI 3 trom PCL tavov i P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00097 Figure 11 3 Data Memory Read Cycle Semiconductor Group 11 14 1997 10 01 SIEMENS Device Specifications C504 A0 A7 from UV A0 A7 Ri or DPL Data OUT KA trom PCL DUM tavwL a P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH MCT00098 Figure 11 4 Data Memory Write Cycle Vg 0 5V MCT00033 Figure 11 5 External Clock Cycle Semiconductor Group 11 15 1997 10 01 SIEMENS Device Specifications C504 11 7 AC Characteristics of Programming Mode Vcc 25V 1096 Vpp 11 5V 5 T 25C 10 Parameter Symbol Limit Values Unit min max ALE pulse width paw 35 ns PMSEL setup to ALE rising edge tems 10 Address setup to ALE PROG or PRD falling tpas 10 ns edge Address hold after ALE PROG or PRD tran 10 ns falling edge Address data setup to PROG or PRD tros 100 ns Address data hold after PROG or PRD tech 0 ns PMSE
178. n ncocacccanancccnonannno 10 mA to 10 mA Absolute sum of all input currents during overload condition 100 mA Power dissIDalOh So do Sce ote ebbe Road do eth TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Vin gt Vcc or Vin lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings Semiconductor Group 11 1 1997 10 01 SIEMENS Device Specifications C504 11 2 DC Characteristics Voc 5 V 10 15 Vas 0 V T 0 to 70 C T4 40 to 85 C T 40to 110 C T 40to 125 C for the SAB C504 for the SAF C504 for the SAH C504 for the SAK C504 Parameter Symbol Limit Values Unit Test Condition min max Input low voltage except EA Vi 0 5 0 2Voco IV RESET CTRAP 0 1 Input low voltage EA Vii 0 5 0 2 Vo IV 0 3 Input low voltage RESET Vio 0 5 0 2 Voec IV CTRAP 0 1 Input high voltage except XTAL1 Vi 0 2 Voo Voc
179. n set this bit allows timer 2 to be configured as an up down counter 6 2 2 1 Auto Reload Up or Down Counter Timer 2 can be programmed to count up or down when configured in its 16 bit auto reload mode This feature is invoked by a bit named DCEN Down Counter Enable SFR T2MOD 0C9y When DCEN is set timer 2 can count up or down depending on the value of pin T2EX P1 1 Figure 6 16 shows timer 2 automatically counting up when DCEN 0 In this mode there are two options selectable by bit EXEN2 in SFR T2CON Semiconductor Group 6 28 1997 10 01 SIEMENS On Chip Peripheral Components C504 Overflow Transition 21 Timer 2 Detection Control Interrupt P1 1 e MCSO2584 EXEN2 Figure 6 16 Timer 2 Auto Reload Mode DCEN 0 If EXEN2 0 timer 2 counts up to FFFFy and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16 bit value in RC2H and RC2L The values in RC2H and RC2L are preset by software If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at the external input T2EX P1 1 This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an timer 2 interrupt if enabled Setting the DCEN bit enables timer 2 to count up or down as shown in figure 6 17 In this mode the T2EX pin controls the direction of count Semiconductor Group 6 29 1997 10 01 SIEMENS On
180. n the SFR ITCON SFR ITCON can be used to generate additional interrupts at an INTO 2 signal transition Semiconductor Group 6 73 1997 10 01 SIEMENS On Chip Peripheral Components C504 Figure 6 31 gives an example of a block commutation mode timing only COUTx outputs are modulated with compare timer 2 output signal It shows the rotate left case BCM1 BCMO 1 0 and rotate right case BCM1 BCMO 0 1 For the timing shown in figure 6 31 the COINI register is set to XX111111p This means that a high level is defined as inactive phase The CMSELx 3 bits in the CMSELO CMSEL1 registers must also be set compare timer 2 switched to COUTx during active phase The timing shown below is directly derived from table 6 9 a Block commutation mode timing in rotate left mode BCM1 0 1 0 1 1 1 0 0 0 Input Signals Output Signals b Block commutation mode timing in rotate right mode BCM1 0 0 1 1 1 1 0 0 0 Input Signals Output Signals MCTO2611 Figure 6 31 Block Commutation Mode Timing Semiconductor Group 6 74 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 4 4 Compare Timer 1 Controlled Multi Channel PWM Modes Using the multi channel PWM modes of the C504 several compare timer 1 controlled PWM waveforms can be generated 4 phase multi channel PWM waveforms 5 phase multi channel PWM waveforms 6 phase multi channel PWM waveforms
181. na for a logic O Figure 11 12 AC Testing Input Output Waveforms Timing Reference Points Vo 0 1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded Vo Vo level occurs Ig Ig4 2 X 20 mA Figure 11 13 AC Testing Float Waveforms Crystal Oscillator Mode Driving from External Source External Oscillator Signal LT 3 5 40 MHz C C 20pF 10 pF incl stray capacitance MCS02579 Figure 11 14 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 11 22 1997 10 01 SIEMENS Device Specifications C504 11 9 Package Information P MQFP 44 SMD Plastic Metric Quad Flat Package H CARO t 0 88 0 5 10 bi pogentaange O 44 PU Index Marking 1 L1 Q 5x45 1 Does not include plastic or metal protrusion of 0 25 max per side GPM05622 Figure 11 15 P MQFP 44 Package Outline Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Semiconductor Group 11 23 1997 10 01
182. nal Int Bus Port Write Driver to Circuit Latch MCS01822 Figure 6 1 Basic Structure of a Port Circuitry Semiconductor Group 6 3 1997 10 01 SIEMENS On Chip Peripheral Components C504 Port 1 2 and 3 output drivers have internal pullup FET s see figure 6 2 Each I O line can be used independently as an input or output To be used as an input the port bit must contain a one 1 that means for figure 6 2 Q 0 which turns off the output driver FET n1 Then for ports 1 2 and 3 the pin is pulled high by the internal pullups but can be pulled low by an external source When externally pulled low the port pins source current Z or For this reason these ports are sometimes called quasi bidirectional Vec Internal Pull Up Arrangement Int Bus n v MCS01823 Figure 6 2 Basic Output Driver Circuit of Ports 1 2 and 3 Semiconductor Group 6 4 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 2 1 Port 0 Circuitry Port 0 in contrast to ports 1 2 and 3 is considered as true bidirectional because the port 0 pins float when configured as inputs Thus this port differs in not having internal pullups The pullup FET in the PO output driver see figure 6 3 is used only when the port is emitting 1 s during the external memory accesses Otherwise the pullup is always off Consequently PO lines that are used as output port lines are open drain lines Writing a 1 to
183. nal ous tosta id be TOES 4 4 Basic operating modes 6 33 Block diagram 5 2 Rs 6 32 General operation 6 33 Semiconductor Group 12 1 1997 10 01 SIEMENS Index C504 Multi channel PWM modes 6 67 to 6 81 CMSELOS sat acd aed 3 10 6 51 4 5 6 phase PWM mode 6 75 to 6 81 CMSELT a ioc 3 7 3 10 6 46 6 51 4 phase PWM timing 6 75 CMSEL10 anta as e ES 3 10 6 52 5 phase PWM timing 6 76 OMSBLTL 2 aia da 3 10 6 52 6 phase PWM timing 6 77 GMSELT2 02 a ees Mie 3 10 6 52 Block commutation mode 6 73 6 74 GMSEL13 prerada tw xx 3 10 6 51 Block diagram 6 67 GMSEL20 iiiter reta 3 10 6 52 Control register BCON 6 68 GMSEL2 deca sed 3 10 6 52 Output waveforms 6 71 6 72 CMSEL22 eese 3 10 6 52 PWM state tables 6 78 6 79 CMSEL23 arras 3 10 6 51 Signal generation 6 70 COINI 3 7 3 10 6 46 6 58 State switching by software 6 80 COUTO circa edades 3 10 6 59 Trap TUNCHON vcre Ee cs 6 81 COUT ERR 3 10 6 59 GOOF sane ree ne esie rn 3 10 6 55 GOUT2 oeenn go utm eu 3 10 6 59 GOGOFPEN rata vm dea 3 10 6 57 GOUTS S seth oa Beo RS 3 10 6 58 o a ID e oh n e 3 10 6 59 GOLPDXI casino at rrt 3 10 6 58 CGCOR ss duet exist NUR o deck 3 10 6 54 PPR cores xx e dn 3 9 6 25 6 27 GGOREN o eua an Cu a 3 10 6 57 CPOE vein gece tk 3 7 3 10 6 62 6 65 GOTE url upeed era tds 3 10 6 55 PAs oai adita nocti 3 7 3
184. nductor Group 6 12 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 3 4 Type E Port Driver Circuitry The type E ports are a combination of type C and type D port drivers They combine push pull driving characteristic with the capability to select the port pin for analog input function The push pull driver characteristic is only enabled used when the corresponding port lines are used as compare outputs The analog function is selected by the bits in the SFRs P1ANA and P3ANA The push pull mixed digital analog port structure is illustrated in figure 6 10 Delay Enable 2 Osc Periodes Push Pull Enable Analog Input bits of SFR P1ANA or SFR P3ANA Input Data read pin v To A D Converter MCS02582 Figure 6 10 Driver Circuit of Type E Port Pins Semiconductor Group 6 13 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 4 Port Timing When executing an instruction that changes the value of a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction However port latches are only sampled by their output buffers during phase 1 of any clock period during phase 2 the output buffer holds the value it noticed during the previous phase 1 Consequently the new value in the port latch will not appear at the output pin until the next phase 1 which will be at S1P1 of the next ma
185. ned as a third interrupt input The functions are assigned to the pins of port 3 as follows 5 P3 0 RxD Receiver data input asynch or data input output synch of serial interface 7 P3 1 TxD Transmitter data output asynch or clock output synch of serial interface 8 P3 2 AN4 INTO Analog input channel 4 external interrupt O input timer O gate control input 9 P3 3 AN5 INT1 Analog input channel 5 external interrupt 1 input timer 1 gate control input 10 P3 4 AN6 TO Analog input channel 6 timer 0 counter input 11 P3 5 AN7 T1 Analog input channel 7 timer 1 counter input 12 P3 6 WR INT2 WR control output latches the data byte from port 0 into the external data memory external interrupt 2 input 13 P3 7 RD RD control output enables the external data memory CTRAP 6 CCU Trap Input With CTRAP low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register if they are enabled by the bits in SFR TRCON CTRAP is an input pin with an internal pullup resistor For power saving reasons the signal source which drives the CTRAP input should be at high or floating level during power down mode Input O Output Semiconductor Group 1 6 1997 10 01 IE Introduction SIEMENS i Table 1 1 Pin Definitions and Functions cont d Symbol Pin Number l O Function P MQFP 44 XTAL2 14 XTAL2 Output of t
186. ng an initial value of 1 when this CCx COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSELO CMSEL1 registers If the compare timer runs and a bit of register TREN is set a compare channel output will be switched to 1 level in trap state The COINI values are only valid for capture compare outputs which are enabled for compare mode operation Semiconductor Group 6 59 1997 10 01 SIEMENS On Chip Peripheral Components C504 Trap Enable Register The trap enable register TREN is used to enable selectively the compare outputs of the three CAPCOM channels for switching it into high or low level in the trap state as defined by the bits of the COINI register Additionally for a general enable of the trap function bit TRPEN must be set The TRF flag indicates when an low level is detected at the CTRAP input signal Special Function Register TRCON Address CFy Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 CFy TRPEN TRF TRENS TREN4 TRENS TREN2 TREN1 TRENO TRCON V IN V N V CAPCOM CAPCOM CAPCOM Channel 2 Channel 1 Channel 0 Bit Function TRPEN External CTRAP trap function enable bit This bit is a general enable bit for the trap function of the CTRAP input signal TRPEN 0 External trap input CTRAP is disabled default after reset TRPEN 1 External trap input CTRAP is enabled TRF Trap flag TRF
187. ng bit WDT WDCON and by the next instruction setting SWDT WDCON Bit WDT will automatically be cleared during the third machine cycle after having been set This double instruction refresh of the Watchdog Timer is implemented to minimize the chance of an unintentional reset of the watchdog unit When the Watchdog Timer is started or refreshed its non accessible lower 8 bits stored in WDTL see figure 8 1 are reset to 00H The reload register WDTREL can be written at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the Watchdog Timer Thus a wrong reload value caused by a possible distortion during the write operation to WDTREL can be corrected by software 8 1 2 Watchdog Reset and Watchdog Status Flag WDTS If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCy The duration of the reset signal then depends on the prescaler selection either 8 or 128 cycles This internal reset differs from an external one in so far as the Watchdog Timer is not disabled and bit WDTS is set The WDTS is a flip flop which is set by a Watchdog Timer reset and can be cleared by an external hardware reset Bit WDTS allows the software to examine from which source the reset was activated The bit WDTS can also be cleared by software Semiconductor Group 8 4 1997 10 01 SIEMENS Fail Safe Mechanisms C504
188. o XRAM using the Registers RO R1 8 bit Addressing Mode 3 4 3 5 Special F nction Registers xia sede REESE a aa ee Nd ees 3 5 4 External Bus Interface i eco RR RR IRR RES 4 1 4 1 Accessing External Memory 000 cece eee tee eee 4 1 4 2 PSEN Program Store Enable s t acs aes wad pb eet sig ote eee RO t e eds 4 2 4 3 Overlapping External Data and Program Memory Spaces 5 4 2 4 4 ALE Address Latch Enable 0 0 00 cc ees 4 4 4 5 Enhanced Hooks Emulation Concept illii 4 5 4 6 ROM OTP Protection for C504 2R C504 2E 1 ee 4 6 4 6 1 Unprotected HOM Mode i539 v ERRARELLTRE yada tea ri 4 6 4 6 2 Protected HOM OTP MOUS i xyanoerERIREUSEXERRERSRRR RERO EVER XS 4 7 5 Reset and System Clock Operation 200 cece e eee eee eee 5 1 5 1 Hardware Reset Operation cux Lak fed ON ee ee ee ew ee ER 5 1 5 2 Fast Internal Reset after Power On 00 00 cece tees 5 3 5 3 Hardware Reset Timing Js d ore ts te manm e tns ut Ale att eal t 5 5 5 4 Oscillator and Clock Circuit eno rated hace dido a ebur poti don Badd med 5 6 6 On Chip Peripheral Components o occccoccno eee 6 1 6 1 Parallel er pean tints ca RE NO 6 1 6 1 1 AE AAA see ot eed Der ae ie Ox Sf en pde qu Whale Sta ut i ta 6 1 6 1 2 Standard MO Port Circuitry Lernen dere Dre aei Dei esed e oca 6 3 6 1 2 1 Port O CCU sermon tae te eet e eese e Eb aate eae eo deed un 6 5 6 1 2 2 Portland Port 3 Circuitry es
189. ode 0 Serial data enters and exists through RXD TXD outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at fosc 12 Figure 6 36a shows a simplyfied functional diagram of the serial port in mode 0 The associated timing is illustrated in figure 6 36b Transmission is initiated by any instruction that uses SBUF as a destination register The WRITE to SBUF signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission The internal timing is such that one full machine cycle will elapse between WRITE to SBUF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S8 S4 and S5 of every machine cycle and high during S6 S1 and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initialy loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX control block to do one last shift and then deactivate SEND and set TI Both of thes
190. ogramming a 100us PROG low pulsw must be applied Semiconductor Group 10 9 1997 10 01 SIEMENS OTP Memory Operation C504 PMSEL1 0 PALE Port 0 D1 DO PROG PRD MCT03365 The example shows the programming and reading of a protection level 1 Figure 10 6 Write Read Lock Bit Waveform Semiconductor Group 10 10 1997 10 01 SIEMENS OTP Memory Operation C504 10 7 Access of Version Bytes The C504 2E and C504 2R provide three version bytes at address locations FCH FDy and FEy The information stored in the version bytes is defined by the mask of each microcontroller step Therefore the version bytes can be read but not written The three version bytes hold information as manufacturer code device type and stepping code For reading of the version bytes the control lines must be used according table 10 2 and figure 10 7 The address of the version byte must be applied at the port 1 address lines PALE must not be activated PMSEL1 0 ZZ PALE Pre ZA ro ro FE Port 0 Miner V A Ver 1 KA Ver 2 77 PROG PRD MCT03366 Figure 10 7 Read Version Byte s Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specifc device characteristics such as OTP size etc Note The 3 version bytes are implemented in a way that they can be also read during normal program execution mode as a mapped SFR when bit RMAP in SFR SYSCON is set The SF
191. old gt 1 Machine Cycle b Transition Activated Interrupt High Level Threshold E TAN n 0 IxETF 1 x 4 gt 1 Machine Cycle gt 1 Machine Cycle Low Level Threshold gt lt gt Transition to be detected High Level Threshold IxETR 1 A Low Level Threshold MCT02577 Figure 7 4 External Interrupt Detection The edge triggered interrupt mode selection for all three dedicated external interrupts and two INT2 control bits are selected in the SFR ITCON External Interrupt Trigger Condition Register The edge trigger mode selection is defined in a way default value of ITCON after reset that their function is upward compatible to the basic external interrupt functionality of the C501 The INT2 enable bit EX2 is located in IEN1 and the INT2 priority bit is located in IP2 The level edge control bit and the IE2 flag for INT2 is located in ITCON Semiconductor Group 7 13 1997 10 01 SIEMENS Interrupt System C504 Special Function Register TCON Address 884 Reset Value 00y Special Function Registers ITCON Address 9A Reset Value 00101010B Bit No MSB LSB 7 6 5 4 3 2 1 0 8Fy 8Ey 8DH 8CH 8By 8AH 89H 88H 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO TCON 9AH IT2 IE2 I2ETF I2ETR HETF HETR IOETF IOETR ITCON INT2 INT1 INTO The shaded bits are not used for external interrupt control Bit Functio
192. ollowing the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip This allows correct resetting of the part and brings all ports to the defined state The delay time between power on and correct reset state is max 34 us more details see chapter 5 2 Semiconductor Group 8 7 1997 10 01 SIEMENS Power Saving Modes C504 9 Power Saving Modes The C504 allows two power saving modes of the device Idle mode Power down mode The functions of the power saving modes are controlled by bits which are located in the special function registers PCON und PCON1 PCON is located at address 874 PCON1 is located in the mapped SFR area and is accessed with RMAP 1 Bit RMAP is located in SFR SYSCON B14 bit 4 The bits PDE PDS and IDLE IDLS located in SFR PCON select the power down mode or the idle mode respectively If the power down mode and the idle mode are set at the same time power down takes precedence Furthermore register PCON contains two general purpose flags For example the flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle Then an instruction that activates idle can also set one or both flag bit
193. ompare timer 2 is running the compare timer 2 output COUT3 is enabled and outputs the PWM signal of the COMP unit STE2 COMP unit shadow latch transfer enable When STE2 is set the content of the compare timer 2 period and compare latches CP2H CP2L CMP2H CMP2L is transferred to its real registers when compare timer 2 reaches the next time the period value After the shadow transfer event STE2 is reset by hardware Semiconductor Group 6 63 1997 10 01 SIEMENS On Chip Peripheral Components C504 Bit Function CT2RES Compare timer 2 reset control CT2R Compare timer 2 run stop control These two bits controls the start stop and reset function of the compare timer 2 CT2RES is used to reset the compare timer and CT2R is used to start and stop the compare timer 2 The following table shows the functions of these two bits CT2RES CT2R Function 0 0 Compare timer 2 is stopped compare output COUT3 stays in the logic state as it is 0 1 Compare timer 2 is running If CT2R is set the first time after reset COUT3 is set to the logic state as defined by bit COUTSI of SFR COINI 1 0 Compare timer 2 is stopped and reset The output COUTS is set to the logic state as defined by bit COUTSI of SFR COINI default after reset 1 1 Compare timer 2 is further running Note ECT2O must be set for COUTS signal output enable CLK2 Compare timer 2 input clock selection CLK1 The input clock for the co
194. omponents C504 Bit Function CCxREN x 0 2 Capture compare rising edge interrupt enable Capture Mode If CCxREN is set an interrupt is generated at a low to high transition rising edge of the corresponding CCx input signal Compare Mode If CCxREN is set an interrupt is generated if the compare timer 1 value matches the compare register CCx value during the up counting phase of the compare timer 1 This function is available in both compare timer 1 operating modes CCxFEN x 0 2 Capture compare falling edge interrupt enable Capture Mode If CCXFEN is set an interrupt is generated at a high to low transition falling edge of the corresponding CCx input signal Compare Mode If CCxFEN is set an interrupt is generated only in compare timer mode 1 if the compare timer 1 value matches the compare register CCx value during the down counting phase of the compare timer 1 This function is available only in compare timer 1 operating mode 1 Semiconductor Group 6 57 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Output Initialization Register COINI The six lower bits of the COINI register define the initial values passive levels of the port 1 lines which are programmed to be used as a compare output If an output of the CAPCOM unit is enabled for compare mode operation by writing the corresponding bit combination into the CMSELO CMSEL1 registers the compare output is switche
195. on Figure 5 1 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 10 ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the C504 the oscillator watchdog unit avoids this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state see figure 5 2 Under worst case conditions fast Voc rise time e g 1us measured from Vec 4 25 V up to stable port condition the delay between power on and the correct port reset state is
196. ort latch which contained a O The extra pullup can drive a similar current as the pulldown FET n1 This provides a fast transition of the logic levels at the pin The pullup FET p2 is of p channel type It is always activated when a 1 is in the port latch thus providing the logic high output level This pullup FET sources a much lower current than p1 therefore the pin may also be tied to ground e g when used as input with logic low input level Semiconductor Group 6 9 1997 10 01 SIEMENS On Chip Peripheral Components C504 The pullup FET p3 is of p channel type It is only activated if the voltage at the port pin is higher than approximately 1 0 to 1 5 V This provides an additional pullup current if a logic high level shall be output at the pin and the voltage is not forced lower than approximately 1 0 to 1 5 V However this transistor is turned off if the pin is driven to a logic low level e g when used as input In this configuration only the weak pullup FET p2 is active which sources the current 7 If in addition the pullup FET p3 is activated a higher current can be sourced 1 Thus an additional power consumption can be avoided if port pins are used as inputs with a low level applied However the driving capability is stronger if a logic high level is output The described activating and deactivating of the four different transistors translates into four states the pins can be input low state IL p2
197. pare timer 2 period registers CP2L CP2H hold the 10 bit value for the compare timer 2 period When the compare timer 2 value is equal to the value stored in the period register the COUTS signal changes from inactive to active state If CP2H CP2L is written only shadow latches are written The content of these latches is transferred to the real registers at compare timer count value 000y using bit STE2 of SFR CT2CON When the compare timer 2 period registers CP2L CP2H are read always the shadow registers are accessed Special Function Register CP2L Address D2 4 Reset Value 00y Special Function Register CP2H Address D3 Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D2y Y 6 Es 4 3 2 1 0 CP2L D3H A 0 CP2H Bit Function CP2L 7 0 Compare timer 2 period low byte The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 shadow latch CP2H 1 0 Compare timer 2 period high bits The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 shadow latch Reserved bits Semiconductor Group 6 65 1997 10 01 SIEMENS On Chip Peripheral Components C504 Compare Timer 2 Compare Registers The compare registers CMP2H CMP2L of compare timer 2 hold the 10 bit compare value which defines the duty cycle of the output signal at COUT3 When the compare timer 2 value is equal to the value sto
198. processor vectors to interrupt routine TR1 Timer 1 run control bit Set cleared by software to turn timer counter 1 ON OFF TF1 Timer 1 overflow flag Set by hardware on timer counter overflow Cleared by hardware when processor vectors to interrupt routine 1997 10 01 Semiconductor Group 6 19 SIEMENS On Chip Peripheral Components C504 Special Function Register TMOD Address 894 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 894 GATE C T M1 MO GATE C T M1 MO TMOD Timer 1 Control Timer 0 Control Bit Function GATE Gating control When set timer counter x is enabled only while INT x pin is high and TRx control bit is set When cleared timer x is enabled whenever TRx control bit is set C T Counter or timer select bit Set for counter operation input from Tx input pin Cleared for timer operation input from internal system clock M1 Mode select bits MO M1 MO Function 0 0 8 bit timer counter THx operates as 8 bit timer counter TLx serves as 5 bit prescaler 0 1 16 bit timer counter THx and TLx are cascaded there is no prescaler 1 0 8 bit auto reload timer counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 Timer O TLO is an 8 bit timer counter controlled by the standard timer O control bits THO is an 8 bit timer only controlled by timer 1 control bits Timer 1 Timer counter 1
199. put asynchronous or data clock output synchronous P3 2 AN4 INTO C Analog input channel 4 External interrupt O input timer O gate control P3 3 AN5 INT1 C Analog input channel 5 External interrupt 1 input timer 1 gate control P3 4 ANG TO C Analog input channel 6 Timer 0 external counter input P3 5 AN7 Tl C Analog input channel 7 Timer 1 external counter input P3 6 WR INT2 B External data memory write strobe External interrupt 2 input P3 7 RD B External data momory read strobe Prior to the description of the port type specific port configurations the general port structure is described in the next section Semiconductor Group 6 2 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 2 Standard I O Port Circuitry Figure 6 1 shows a functional diagram of a typical bit latch and I O buffer which is the core of each of the four l O ports The bit latch one bit in the port s SFR is represented as a type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read from a port i e from the corresponding port SFR PO P2 P3 activate the read latch signal while others activate the read pin sig
200. put through the EA Vpp pin Figure 10 1 shows the pins of the C504 2E which are required for controlling of the OTP programming mode P20 7 PALE PMSELO PMSEL1 C504 2E RESET PSEN PSEL MCS03360 Figure 10 1 C504 2E Programming Mode Configuration Semiconductor Group 10 1 1997 10 01 SIEMENS OTP Memory Operation C504 10 2 Pin Configuration Figure 10 2 shows the detailed pin configuration of the C504 2E in programming mode PTT A5 A13 Co 34 M1 M2 35 A31 Att 36 A21 M10 37 M 1 A9 38 A01 A8 39 C504 2E Voc 40 Vos 41 XTAL1 42 XTAL2 43 N C 40 N C 1234567 MCP03361 Figure 10 2 Pin Configuration of the C504 2E in Programming Mode Top View Semiconductor Group 10 2 1997 10 01 SIEMENS OTP Memory Operation C504 10 3 Pin Definitions The following table 10 1 contains the functional description of all C504 2E pins which are required for OTP memory programming Table 10 1 Pin Definitions and Functions of the C504 2E in Programming Mode Symbol Pin Number P MQFP 44 1 0 Function RESET 4 Reset This input must be at static 1 active level during the whole programming mode PMSELO PMSEL1 al Programming mode selection pins These pins are used to select the different ac
201. r Semiconductor Group 6 100 1997 10 01 SIEMENS On Chip Peripheral Components C504 Special Function Registers ADCONO Address D8 Reset Value XX000000p Special Function Registers ADCON1 Address DC Reset Value 01XXX000p Special Function Registers IEN1 Address A9y Reset Value XX000000p Bit No MSB LSB 7 6 5 4 3 2 1 0 D8H ADC BSY ADM MX2 MX1 MXO ADCONO DCH ADCL1 ADCLO MX2 MX1 MXO ADCON1 A9H ECT1 ECCM ECT2 ECEM EX2 EADC IEN1 The shaded bits are not used for A D converter control Bit Function Reserved bits for future use IADC A D converter interrupt request flag Set by hardware at the end of a A D conversion Must be cleared by software BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D conversion mode When set a continous A D conversion is selected If cleared during a running A D conversion the conversion is stopped at its end MX2 MXO A D converter input channel select bits Bits MX2 0 can be written or read either in ADCONO or ADCON1 The channel selection done by writing to ADCON 1 0 overwrites the selection in ADCON 0 1 when ADCON 1 0 is written after ADCON 0 1 The analog inputs are selected according the following table MX2 MX1 MXO0 Selected Analog Input 0 0
202. ram Semiconductor Group 6 90 1997 10 01 SIEMENS On Chip Peripheral Components C504 Transmit Receive MCT02102 cc G E 2 zZ Q e 99 2 2 Write to SBUF TXD Shift Clock TXD Shift Clock Figure 6 36b Serial Interface Mode 0 Timing Diagram Semiconductor Group 6 91 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 5 Details about Mode 1 Ten bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in SCON The baud rate is determined either by the timer 1 overflow rate or the timer 2 overflow rate or both one for transmit and the other for receive Figure 6 37a shows a simplified functional diagram of the serial port in mode 1 The assiociated timings for transmit receive are illustrated in figure 6 37b Transmission is initiated by an instruction that uses SBUF as a destination register The WRITE to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested Transmission starts at the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the WRITE to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transm
203. ransitions In edge triggered mode if successive samples of the INTx pin show a different logic level in two consequent machine cycles the corresponding interrupt request flag IEx in TCON ITCON is set Flag bit IEx 1 then requests the interrupt If the external interrupt 0 1 or 2 is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1 1 T2EX but only if bit EXEN2 is set Since the external interrupt pins are sampled once in each machine cycle an input low should be held for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated for negative transitions the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle to ensure that a negative transition falling edge is recognized so that the corresponding interrupt request flag will be set see figure 7 3 In edge triggered mode the external interrupt request flags will automatically be cleared by the CPU when the service routine is called Semiconductor Group 7 12 1997 10 01 SIEMENS Interrupt System C504 a Level Activated Interrupt Low Level Thresh
204. ration In the most typical applications itis configured for timer operation C T2 0 Timer operation is a little different for timer 2 when its being used as a baud rate generator Normally as a timer it would increment every machine cycle thus at fosc 12 As a baud rate generator however it increments every state time foso 2 In that case the baud rate is given by the formula Modes 1 3 baud rate fog 32x 65536 RC2H RC2L where RC2H RC2L is the content of RC2H and RC2L taken as a 16 bit unsigned integer Note that the rollover in TH2 does not set TF2 and will not generate an interrupt Therefore the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode Note too that if EXEN2 is set a 1 to 0 transition in T2EX can be used as an extra external interrupt if desired It should be noted that when timer 2 is running TR2 1 in timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the timer is being incremented every state time and the results of a read or write may not be accurate The RC registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors Turn the timer off clear TR2 before accessing the timer 2 or RC registers in this case Semiconductor Group 6 88 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 4 Details about M
205. re an external reset time of typically 1 ms is sufficient in most applications Generally for reset time generation at power on an external capacitor can be applied to the RESET pin Semiconductor Group 5 3 1997 10 01 C504 Reset System Reset SIEMENS L6020V9N uojnoex3 f joubisjasay xe uDJ604q jo DIS jo esnooeq Jesey ul su DWWad Hod sej9 89 M 280 Aq aouanbas lage josey ui _ SHOS OSO diy9 uQ Spog JD jesey JOPD IDSQ DY Wo 4901 gt srl yg XDW srg dA Spo jepun UY JeMog Figure 5 2 Power On Reset Timing of the C504 1997 10 01 5 4 Semiconductor Group SIEMENS Reset System Reset C504 5 3 Hardware Reset Timing This section describes the timing of the hardware reset signal The input pin RESET is sampled once during each machine cycle This happens in state 5 phase 2 Thus the external reset signal is synchronized to the internal CPU timing When the reset is found active high level the internal reset procedure is started It needs two complete machine cycles to put the complete device to its correct reset state i e all special function registers contain their default values the port latches contain 1 s etc Note that this reset procedure is also performed if there is no clock available at the device This is done by the oscillator watchdog which provides an auxiliary clock for performing a perfect reset without
206. re input at pin CCx Compare timer 1 runs either in operating mode 0 or 1 A rising or and falling edge at CCx will copy the actual value of the compare timer 1 into the compare capture registers Interrupts can be generated selectively at each transition of the capture input signal The capture mode is selected by writing the mode select registers CMSEL1 and CMSELO with the appropriate values The bit combinations in CMSELO and CMSEL1 also define the signal transition type falling rising edge which generates a capture event If a CAPCOM channel is enabled for capture mode its CCx input is sampled with 2 teLcL fosc 2 half external CPU clock rate Consecutive capture events generated through signal transitions at a CCx capture input overwrite the corresponding 16 bit compare capture register contents This must be regarded when successive signal transitions are processed Semiconductor Group 6 43 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode When a channel of the CAPCOM unit operates in compare mode its output lines can be decoupled in trap mode from the CAPCOM pulse generation The trap mode is controlled by the external signal CTRAP The CTRAP signal is sampled once each 2nd oscillator clock cycle If a low is detected the trap flag TRF of register TRCON is set and CCx or COUTx compare outputs are switched immediately to the logic inactive state as defined by the
207. red in the CMP2H CMP2L register the COUT3 signal changes from passive to active state If CMP2H CMP2L is written only shadow latches are written The content of these latches is transferred to the real registers when compare timer count value 000 is reached and bit STE2 of SFR CT2CON has been set When the compare CMP2H CMP2L registers are read always the shadow registers are accessed Special Function Registers CMP2L Address D4py Reset Value 00y Special Function Registers CMP2H Address D5y Reset Value XXXXXX00p Bit No MSB LSB 7 6 5 4 3 2 1 0 D4y 7 6 ES 4 3 2 1 0 CMP2L D5H 1 0 CMP2H Bit Function CMP2L 7 0 Compare value low byte for compare timer 2 The CMP2L register holds the lower 8 bits of the 10 bit compare value for compare timer 2 CMP2H 1 0 Compare value high bits for compare timer 2 The CMP2H register holds most significant two bits of the 10 bit compare value for compare timer 2 Reserved bits Semiconductor Group 6 66 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 4 Combined Multi Channel PWM Modes The CCU of the C504 has been designed to support also motor control or inverter applications which have a demand for specific multi channel PWM signal generation In these combined multi channel PWM modes the CAPCOM unit compare timer 1 and the COMP unit compare timer 2 of the C504 CCU are working together In the com
208. refresh is triggered by a consecutive setting of bits WDT and SWDT Special Function Register WDCON Address CO Reset Value XXXX 0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 COy OWDS WDTS WDT SWDT WDCON Bit Function Not implemented Reserved for future use OWDS Oscillator Watchdog Timer Status Flag Set by hardware when an oscillator watchdog reset occured Can be set and cleared by software WDTS Watchdog Timer Status Flag Set by hardware when a Watchdog Timer reset occured Can be cleared and set by software WDT Watchdog Timer Refresh Flag Set to initiate a refresh of the watchdog timer Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer SWDT Watchdog Timer Start Flag Set to activate the Watchdog Timer When directly set after setting WDT a watchdog timer refresh is performed Semiconductor Group 8 2 1997 10 01 SIEMENS Fail Safe Mechanisms C504 Immediately after start the Watchdog Timer is initialized to the reload value programmed to WDTREL O WDTREL 6 After an external HW reset an oscillator watchdog power on reset or a watchdog timer reset register WDTREL is cleared to 00 The lower seven bits of WDTREL can be loaded by software at any time Examples given for 12 and 24 MHz external oscillator frequency Table 8 1 Watchdog Timer Time Out Periods WDTREL Ti
209. registers are to be accessed the bit RMAP must be cleared set by software respectively each There are also 128 directly addressable bits available within each SFR area standard and mapped SFR area All SFRs with addresses where address bits 0 2 are 0 e g 80H 8814 90H 98y F8y FF are bitaddressable The 63 special function register SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals The SFRs of the C504 are listed in table 3 1 and table 3 2 In table 3 1 they are organized in groups which refer to the functional blocks of the C504 Table 3 2 illustrates the contents of the SFRs in numeric order of their addresses Semiconductor Group 3 5 1997 10 01 SIEMENS Memory Organization C504 Table 3 1 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator E0y 00H B B Register FO 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H PSW Program Status Word Register DOW 00H SP Stack Pointer 81H 07H SYSCON System Control Register BiH XX10XXX0p Interrupt IENO Interrupt Enable Register 0 A8y 0X000000p System IEN1 Interrupt Enable Register 1 A9H XX000000p CCIE Capture Compare Interrupt Enable Reg D6y 00H IPO Interrupt Priority Register 0 B8y XX000000p IP1 Interrupt Priority Register 1 B9y XX000000p ITCON Interrupt Trigg
210. rical PWM Center Aligned with programmable dead time off Period Period Value Value e Compare A Compare Value Value Offset 0000 y GG COINI 0 COUT COINI 1 PR y Interrupts can be generated MCT03356 Figure 6 19 Basic Operating Modes of the CAPCOM Unit Semiconductor Group 6 33 1997 10 01 SIEMENS On Chip Peripheral Components C504 Both compare timers start counting upwards from 0000y up to a count value stored in the period registers If the value stored in the period register is reached they are reset operating mode 0 both compare timers or the count direction is changed from up counting to down counting operating mode 1 only compare timer 1 Using operating mode 0 edge aligned PWM signals can be generated Using operating mode 1 center aligned PWM signals can be generated Compare timer 1 can be programmed for both operating modes while compare timer 2 always works in operating mode 0 with one output signal COUTS Figure 6 19 a and c shows the function of these basic operating modes Compare timer 1 has an additional 16 bit offset register which consists of the high byte stored in CT10FH and the low byte stored in CT1OFL If the value stored in CT1OFF is O the compare timer operates as shown in figure 6 19 a and c If the value stored in CT1OFF is not zero the compare timer operates as shown in figure 6 19 b and d In operating mode 0 compare timer 1 is always reset af
211. ring a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 2 2 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction Semiconductor Group 2 4 1997 10 01 Fundamental Structure C504 SIEMENS O eo ERR P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P4 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 Read Opcode Read next Opcode Discard Read next Opcode Again STSISTSTSTST 77 a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd b Opcode Byte SISTSISISIs b 2 Byte 1 Cycle Instruction e g ADD A Data Read next Opcode Read next Opcode Again 4 Read In Opcode Read next Opcode Discard SET c 1 Byte 2 Cycle Instruction e g INC DPTR Read next Opcode Again 4 Read next Opcode No Fetch No Fetch Discard c No ALE STSTSTATSISTSISISTSTSIS d MOVX 1 Byte 2 Cycle Read Opcode MOVX MCB01816 Access External Memory Figure 2 2 Fetch Execute Sequence Semiconductor Group 1997 10 01 SIEM ENS Memory Organization C504 3 Memory Organization The C504 CPU manipulates operands in the following four address spaces up to 64 Kbyte of internal external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory a 128 byte special function register area Figure 3 1 illustrates the memory address
212. rive capabilities If the load exceeds the pin can be forced to 1 by writing a 0 followed by a 1 to the port pin Semiconductor Group 6 10 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 3 2 Type C Port Driver Circuitry Figure 6 8 shows the port driver circuit of the type C mixed digital analog I O port lines of the C504 The analog function is selected by the bits in the SFRs P1ANA and P3ANA Delay 2 Osc Periodes Enable Analog Input bits of SFR P1ANA or SFR P3ANA Input Data read pin Converter MCS02580 Figure 6 8 Driver Circuit of Type C Port Pins Semiconductor Group 6 11 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 3 3 Type D Port Driver Circuitry The driver and control structure of the port pins used for compare output functions have a port structure which allows a true push pull output driving capability Type D This output driver characteristic is only enabled used when the corresponding port lines are used as compare outputs The analog function is selected by the bits in the SFRs P1ANA and P3ANA The push pull port structure is illustrated in figure 6 9 Delay Enable 2 Osc Periodes Push Pull Input Data read pin MCS02581 Figure 6 9 Driver Circuit of Type D Port Pins Semico
213. rocessor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz crystal 58 of the instructions execute in 1 0 us 40 MHz 300 ns The CPU Central Processing Unit of the C504 consists of the instruction decoder the arithmetic section and the program control section Each program instruction is decoded by the instruction decoder This unit generates the internal signals controlling the functions of the individual units within the CPU They have an effect on the source and destination of data transfers and control the ALU processing The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear completement jump if not set jump if set and clear and move to from carry Between any addressable
214. rs Functional Blocks cont d Block Symbol Name Address Contents after Reset Timer 2 T2CON Timer 2 Control Register C8y 00H T2MOD Timer 2 Mode Register C9H XXXXXXXOp RC2H Timer 2 Reload Capture Register High Byte CBy 00H RC2L Timer 2 Reload Capture Register Low Byte CAy 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H Capture CT1CON Compare timer 1 control register Ely 000100008 Compare CCPL Compare timer 1 period register low byte DEH 00H Unit CCPH Compare timer 1 period register high byte DFy 00H CT1OFL Compare timer 1 offset register low byte E6H 00H CT1OFH Compare timer 1 offset register high byte E7y 00H CMSELO Capture compare mode select register 0 E3y 00H CMSEL1 Capture compare mode select register 1 E4y 00H COINI Compare output initialization register E2H FFH TRCON Trap enable control register CFy 00H CCLO Capture compare register 0 low byte C2H 00H CCHO Capture compare register 0 high byte C3y 00H CCL1 Capture compare register 1 low byte C4y 00H CCH 1 Capture compare register 1 high byte C5H 00H CCL2 Capture compare register 2 low byte C6y 00H CCH2 Capture compare register 2 high byte C7y 00H CCIR Capture compare interrupt request flag reg ESH 00H CCIE Capture compare interrupt enable register D6y 00H CT2CON Compare timer 2 control register Ciy 00010000 CP2L Compare timer 2 period register low byte D2y 00H CP2H Compare timer 2 period regi
215. s Figure 5 4 shows the recommended oscillator circuit C 20 pF 10 pF for crystal operation MCS03353 Figure 5 4 Recommended Oscillator Circuit In this application the on chip oscillator is used as a crystal controlled positive reactance oscillator a more detailed schematic is given in figure 5 5 It is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip The crystal specifications and capacitances are non critical In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal A ceramic resonator can be used in place of the crystal in cost critical applications If a ceramic resonator is used the two capacitors normally have different values depending on the oscillator frequency We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors Semiconductor Group 5 6 1997 10 01 SIEMENS Reset System Reset C504 lt To internal e Ld gt E timing circuitry XTAL2 fF Gia 03 ede Crystal or ceramic resonator Resistor is only in the C504 2E MCS03354 Figure 5 5 On Chip Oscillator Circuiry To drive the C504 with an external clock source the external clock signal has to be applied to XTAL1 as shown in figure 5 6 XTAL2 has to be left unconnected A pullup resistor is suggested to increase the noise
216. s When idle is terminated by an interrupt the interrupt service routine can examine the flag bits Special Function Register PCON Address 87g Reset Value 000X0000p Bit No MSB LSB 7 6 5 4 3 2 1 0 874 SMOD PDS IDLS GF GFO PDE IDLE PCON The function of the shaded bit is not described in this section Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode Not implemented Reserved for future use GF1 General purpose flag GFO General purpose flag PDE Power down enable bit When set starting of the power down is enabled IDLE Idle mode enable bit When set starting of the idle mode is enabled Semiconductor Group 9 1 1997 10 01 SIEMENS Power Saving Modes C504 Special Function Register PCON1 Mapped Address 88H Reset Value OXXXXXXXp Bit No MSB LSB 7 6 5 4 3 2 1 0 884 EWPD o PCON1 Symbol Function Reserved for future use EWPD External wake up from power down enable bit Setting EWPD before entering power down mode enables the external wake up from power down mode capability via the pin INTO more details see section 9 2 Semiconductor Group 9 2 1997 10 01
217. s by the incoming start bit if REN 1 The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed The corresponding interrupt request flags for serial interface O are TI or RI resp See chapter 7 of this user manual for more details about the interrupt structure The interrupt request flags Tl and RI can also be used for polling the serial interface 0 if the serial interrupt is not to be used i e serial interrupt O not enabled Semiconductor Group 6 82 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 4 14 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is beein
218. s of the different access modes Semiconductor Group 10 6 1997 10 01 SIEMENS OTP Memory Operation C504 10 5 Program Read OTP Memory Bytes The program read OTP memory byte access mode is defined by PMSEL1 0 1 1 It is initiated when the PMSEL1 0 1 1 is valid at the rising edge of PALE With the falling edge of PALE the upper addresses A8 A13 of the 14 bit OTP memory address are latched After A8 A13 has been latched AO A7 is put on the address bus port 2 AO A7 must be stable when PROG is low or PRD is low If subsequent OTP address locations are accessed with constant address information at the high address lines A8 13 A8 A13 must only be latched once page address mechanism Figure 10 4 shows a typical OTP memory programming cycle with a following OTP memory read operation In this example A0 A13 of the read operation are identical to A8 A13 of the preceeding programming operation PMSEL1 0 1 1 Port 2 X A0 A7 Port 0 Do D7 min 100 us it 100 ns a PRD MCT03363 Figure 10 4 Programming Verify OTP Memory Access Waveform If the address lines A8 A13 must be updated PALE must be activated for the latching of the new A8 A13 value Control address and data information must only be switched when the PROG and PRD signals are at high level The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode Semiconductor Group
219. s or address data bus for use in external memory accesses In this application they cannot be used as general purpose l O even if not all address lines are used externally The switching is done by an internal control signal dependent on the input level at the EA pin and or the contents of the program counter If the ports are configured as an address data bus the port latches are disconnected from the driver circuit During this time the P2 SFR remains unchanged while the PO SFR has 1 s written to it Being an address data bus port 0 uses a pullup FET as shown in figure 6 5 When a 16 bit address is used port 2 uses the additional strong pullups p1 figure 6 6 to emit 1 s for the entire external memory cycle instead of the weak ones p2 and p3 used during normal port activity Addr Control Internal Pull Up Arrangement Int Bus Write to Latch MCS03228 Figure 6 5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses port 0 can be used for I O functions Note during MOVX accesses to the internal XRAM no external bus cycles are generated Semiconductor Group 6 7 1997 10 01 SIEMENS On Chip Peripheral Components C504 Control MUX 1 State Input Data Read Pin lt MCS03229 Figure 6 6 Port 2 Pull up Arrangement Port 2 in I O function works similar to
220. s shadow latches are loaded The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value operating mode 0 or count value 0000 operating mode 1 When the capture compare registers are read always the real registers are accessed because of capture mode Special Function Registers CCLO CCHO Addresses C2y C3H Reset Value 00y Special Function Registers CCL1 CCH1 Addresses C4y C5H Reset Value 00y Special Function Registers CCL2 CCH2 Addresses C6y C7y Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 C2y y 6 5 4 3 2 1 LSB CCLO C3y MSB 6 5 4 3 2 1 0 CCHO C4y Y 6 5 4 3 2 1 LSB CCL1 C5H MSB 6 5 4 3 2 1 0 CCH1 C6y y 6 5 4 3 2 1 LSB CCL2 C7H MSB 6 5 4 3 2 1 0 CCH2 Bit Function CCLx 7 0 Capture compare value low byte x 0 2 The 8 bit value in the CCLx register is the low part of the 16 bit capture compare value of channel x CCHx 7 0 Capture compare value high byte x 0 2 The 8 bit value in the CCHx register is the low part of the 16 bit capture compare value of channel x Semiconductor Group 6 53 1997 10 01 SIEMENS On Chip Peripheral Components C504 Capture Compare Interrupt Request Flags Register The interrupt flags of the CAPCOM capture compare match and compare timer 1 interrupt are located in the register CCIR All CAPCOM
221. spaces of the C504 FFFF y Internal XRAM FFOO y FEFF y External Indirect Direct Address Address Internal apeciol RAM a egister External Internal External Internal EA 1 EA 0 RAM 0000 y 004 Code Space Data Space Internal Data Space MCD02592 Figure 3 1 C504 Memory Map Semiconductor Group 3 1 1997 10 01 SIEM ENS Memory Organization C504 3 1 Program Memory Code Space The C504 2R has 16 Kbytes of read only program memory while the C504 L has no internal program memory The C504 2E provides 16 Kbytes of OTP program memory The program memory can be externally expanded up to 64 Kbytes If the EA pin is held high the C504 executes out of internal ROM unless the program counter address exceeds 3FFFy Locations 4000y through FFFFy are then fetched from the external program memory If the EA pin is held low the C504 fetches all instructions from the external program memory 3 2 Data Memory Data Space The data memory address space consists of an internal and an external memory space The internal data memory is divided into three physically separate and distinct blocks the lower 128 bytes of RAM the upper 128 bytes of RAM and the 128 byte special function register SFR area While the upper 128 bytes of data memory and the SFR area share the same address locations they are accessed through different addressing modes The lower 128 bytes of data memory can be accessed through direct
222. sport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs incurred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain human life If they fail it is reasonable to assume that the health of the user may be endan gered SIEMENS General Information C504 C504 Data Sheet Revision History 1997 10 01 Previous Releases 06 96 Original Version Page new Page prev Subjects changes since last revision version version general C504 2E OTP version included new chapter 10 C504 2E AC DC characteristics are now in chapter 11 1 1 1 1 Figure 1 1 completed 1 4 1 4 Figure 1 3 completed 1 6 1 6 RESET pin desc for the duration of two machine cycl corrected 2 1 2 1 Figure 2 1 completed 3 3 3 4 4 6 4 7
223. stack pointer to location 074 and increments it once to start from location 08 4 which is also the first register RO of register bank 1 Thus if one is going to use more than one register bank the SP should be initialized to a different location of the RAM which is not used for data storage Semiconductor Group 3 2 1997 10 01 SIEM ENS Memory Organization C504 3 4 XRAM Operation The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space but is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM The C504 maps 256 bytes of the external data space into the on chip XRAM Especially when using the 8 bit addressing modes this could prevent access to the external memory extension and might induce problems when porting software Therefore it is possible to enable and disable the on chip XRAM using the bit XMAP in SFR SYSCON When the XRAM is disabled default after reset all external data memory accesses will go to the external data memory area Special Function Register SYSCON Address B1 4 Reset Value XX10XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 Bly 7 EALE RMAP XMAP SYSCON The functions of the shaded bits are not described in this section Bit Function Not implemented Reserved for future use XMAP Enable XRAM XMAP 0 XRA
224. state while the outputs COUTx are switched to the PWM signal which is generated by the 10 bit compare timer 2 COMP unit Semiconductor Group 6 67 1997 10 01 SIEMENS On Chip Peripheral Components C504 For monitoring of sensor input signal timing in block commutation mode the signal transitions at INTO 2 can also generate an interrupt if enabled and a capture event at channel 0 of the CAPCOM unit compare timer 1 For emergency cases trap function of CTRAP input signal the six outputs CCx and COUTx can be put selectively to its inactive phase COINI At the multi channel PWM modes of the C504 a change of the PWM output states active or inactive is triggered by compare timer 1 which is running either in operating mode 0 or 1 If its count value reaches 0000y the PWM output signal changes its state according to a well defined state table The multi channel PWM modes are split up into three modes 4 phase multi channel PWM mode 4 PWM output signals 5 phase multi channel PWM mode 5 PWM output signals 6 phase multi channel PWM mode 6 PWM output signals 6 3 4 1 Control Register BCON The BCON register controls the selection of multi channel PWM modes It also contains the block commutation interrupt enable and status bit flag Special Function Register BCON Address D7 Reset Value 00y Bit No MSB LSB 7 6 5 4 3 2 1 0 D74 B amp ME PWM1 PWMO EBCE BCERR BCEN
225. ster high byte D3y XXXXXX00p CMP2L Compare timer 2 compare register low byte D4y 00H CMP2H Compare timer 2 compare register high byte D5y XXXXXX00p BCON _ Block commutation control register D7y 00H Watchdog WDCON Watchdog Timer Control Register Coy XXXX0000p WDTREL Watchdog Timer Reload Register 86H 00H Power PCON Power Control Register 87H 000X0000p Save Mode PCON1 Power Control Register 1 88p OXXXXXXXp 9 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is undefined and the location is reserved 4 SFR is located in the mapped SFR area For accessing this SFR bit RMAP in SFR SYSCON must be set Semiconductor Group 1997 10 01 SIEMENS Memory Organization C504 Table 3 2 Contents of the SFRs SFRs in numeric order of their addresses Addr Register Content Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 after Reset 804 PO FFH 7 6 5 4 5 2 1 0 814 SP 07H 7 6 5 4 3 2 d 0 82H DPL 00H 7 6 5 4 3 2 1 0 834 DPH 00H i 6 5 4 3 2 E 0 86H WDTREL 00H WDT 6 5 4 3 2 1 0 PSEL 87H PCON 000X SMOD PDS IDLS GF1 GFO PDE IDLE 0000p 88 2 TCON 00H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 88 29 PCON1 OXXX EWPD E XXXXp 894 TMOD 00y GATE C T M1 MO GATE C T M1 Mo 8AH TLO 0
226. sters Depending on the specific ports multiple functions are assigned to the port pins Therefore the parallel I O ports of the C504 can be grouped into five different types which are listed in table 6 1 Table 6 1 C504 Port Structures Type Description A Standard digital I O ports which can be also used for external address data bus Standard multifunctional digital I O port lines Mixed digital analog I O port lines with programmable analog input function Standard digital I O port lines with push pull drive capability mo ou Mixed digital analog I O port lines with push pull drive capability and programmable analog input function Type A and B port pins are standard C501 compatible I O port lines which can be used for digital I O The type A ports port 0 and port 2 are also designed for accessing external data or program memory Type B port lines are located at port 3 and provide alternate functions for the serial interface or are used as control outputs during external data memory accesses The C504 provides eight analog input lines which are realized as mixed digital analog inputs The 8 analog inputs are split into two groups of four inputs each Four analog inputs ANO AN3 are located at the port 1 pins P1 0 to P1 3 and the other four analog inputs AN4 AN7 are located at the port 3 pins P3 2 to P3 5 type C and type E port lines After reset all analog inputs are disabled and the related pins of port 1
227. t uses strong internal pullup resistors when issuing 1 s Port O also outputs the code bytes during program verification in the C504 2R External pullup resistors are required during program ROM verification Vaner 38 Reference voltage for the A D converter VAGND 39 Reference ground for the A D converter Vas 16 Ground 0V Voc 17 Power Supply 5V 2 Input O Output Semiconductor Group 1 8 1997 10 01 SIEMENS Fundamental Structure C504 2 Fundamental Structure The C504 basically is fully compatible to the architecture of the standard 8051 microcontroller family Especially it is functionally upward compatible with the SAB 80C52 C501 microcontrollers While maintaining all architectural and operational characteristics of the SAB 80C52 C501 the C504 incorporates a genuine 10 bit A D Converter a capture compare unit a XRAM data memory as well as some enhancements in the Timer 2 and Fail Save Mechanism Unit Figure 2 1 shows a block diagram of the C504 ia Port 0 8 Bit Digital I O Port 1 gt 8 Bit Digital 1 0 4 Bit Analog Inputs Port 2 ELS Port 3 gt 8 Bit Digital I O 4 Bit Analog Inputs Emulation Support Logic MCB02591 Figure 2 1 Block Diagram of the C504 Semiconductor Group 2 1 1997 10 01 SIEMENS Fundamental Structure C504 2 1 CPU The C504 is efficient both as a controller and as an arithmetic p
228. te cycle 11 15 Survey ordi Redi es 6 62 External clock timing 11 15 3 channel CAPCOM unit 6 35 to 6 60 Lock bit access timing 11 19 Burst mode 000 6 42 Program memory read cycle 11 14 Capture mode 6 43 Programming mode 11 16 Clocking scheme 6 35 Programming mode read cycle 11 18 Operating mode 0 6 36 to 6 38 Programming mode write cycle 11 17 Operating mode 1 6 39 Protected ROM OTP verify timing 11 21 Period and resolution 6 40 to 6 41 Unprotected ROM verify timing 11 20 Registers 6 46 to 6 60 Version byte access timing 11 19 Capture compare registers 6 53 AC Testing CT1 control register 6 47 Float waveforms o o 11 22 Interrupt enable register 6 56 Input output waveforms 11 22 Interrupt request register 6 54 ACCT nn oboe uu eee 2 2 3 6 3 10 Mode select registers 6 51 ADGEO iste S TU S aequi 6 102 Offset registers 6 50 ADCL1 oL 3 10 6 102 Output initialization register 6 58 ADCONO 3 6 3 10 6 101 Period registers 6 49 ADCONT ze cie 04 3 6 3 10 6 101 Survey enn n nnl 6 46 ADDATI qi Er eon 3 6 3 10 6 100 Trap enable register 6 60 ADDATE S i soos ron 3 6 3 10 6 100 Write on the fly 6 46 ADM AAA 3 10 6 101 Trap function 6 44 ALE sig
229. tended version of the C501 Microcontroller Its enhanced functionality especially the capture compare unit CCU allows to use the MCU in motor control applications Further the C504 is compatible with the SAB 80C52 C501 microcontrollers and can replace it in existing applications The C504 2R contains a non volatile 16Kx8 read only program memory a volatile on chip 512x8 read write data memory four 8 bit wide ports three 16 bit timers counters a 16 bit capture compare unit a 10 bit compare timer a twelve source two priority level interrupt structure a serial port versatile fail save mechanisms on chip emulation support logic and a genuine 10 bit A D converter The C504 L is identical to the C504 2R except that it lacks the on chip program memory The C504 2E is the OTP version in the C504 microcontroller with a 16Kx8 one time programmable OTP program memory The term C504 refers to all versions within this documentation unless otherwise noted Oscillator Watchdog 10 Bit ADC 1 0 Timer 2 gt 8 Bit Digital I O 168 4 Bit Analog Inputs Capture Compare 1 0 10 Bit Compare Unit 2 2 yo o pm o Qa a gt 92 ce S s 2 E LLI g lt 2 E O ROM OTP 8 Bit Digital I O Watchdog Timer 16kx8 gt 4 Bit Analog Inputs MCB02589 Figure 1 1 C504 Functional Units Semiconductor Group 1 1 1997 10 01 IEMEN Introduction gt gt C504 Listed below is a summary of the main features of the C504 Ful
230. ter and reception of the rest of the frame will proceed As data bit come from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in modes 2 and 3 is a 9 bit register it flags the RX control block to do one last shift load SBUF and RB8 and to set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bit goes into SBUF One bit time later whether the above conditions were met or not the unit goes back to looking for a 1 to 0 transition at the RXD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI Semiconductor Group 6 95 1997 10 01 SIEMENS On Chip Peripheral Components C504 Internal Bus y Stop Bit Shift gt Start Generation Data TX Control TX Clock Tl Send Serial gt 1 Port Interrupt a Er Sample 1 to 0 RX Clock RI Load r Transition Start SBUF RX Control 11 Bit gt E Input Shift Register 9Bits Shift v z Detector 1FF i Shift Load SBUF Read SBUF
231. ter its value has been equal to the value stored in period register In operating mode 1 the count direction of the compare timer is changed from up to down counting when its value has reached the value stored in the period register The count direction is changed from down to up counting when the compare timer value has reached 00004 Generally the compare outputs CCx are always assigned to a match condition with the compare timer value directly while the compare outputs COUTx are assigned to a match condition with the compare timer value plus the offset value Therefore signal waveforms with non overlapping signal transitions as shown in figure 6 19 b and d can be generated Further the initial logic output level of the CAPCOM channel outputs when used in compare mode can be selected This allows to generate waveforms with inverting signal polarities In capture mode of the CAPCOM unit the value of compare timer 1 is stored in the capture registers if a signal transition occurs at pins CCx The compare unit COMP is a 10 bit compare unit which can be used to generate a pulse width modulated signal This PWM output signal drives the output pin COUTS In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs The block commutation control logic allows to generate versatile multi channel PWM output signals In one of theses modes the block commutation mode signal transitions at the three external interr
232. the continuous conversion mode A D conversion interrupt After the start of an A D conversion the A D converter interrupt is enabled The result of the A D conversion is read in the interrupt service routine If other C504 interrupts are enabled the interrupt latency must be regarded Therefore this software method is the slowest method to get the result of an A D conversion Depending on the oscillator frequency of the C504 and the selected divider ratio of the A D converter prescaler the total time of an A D conversion is calculated according figure 6 41 and table 6 14 Figure 6 43 on the next page shows the minimum A D conversion time in relation to the oscillator frequency fosc The minimum conversion time is 6 us which can be achieved at fosc of 16 or 32 MHz Table 6 14 A D Conversion Time for Dedicated System Clock Rates fosc MHz Prescaler fApc MHz Sample Time Total Conversion Ratio PS ts us Time tApcc us 3 5 4 438 4 57 27 43 12 4 1 5 1 33 8 16 4 2 1 6 24 8 1 5 1 33 8 32 8 2 1 6 40 16 1 25 1 6 9 6 Semiconductor Group 6 106 1997 10 01 SIEMENS On Chip Peripheral Components C504 Note The prescaler ratios in table 6 14 are mimimum values At system clock rates fosc up to 16 MHz the divider ratio 8 16 or 32 can also be used At system clock rates between 16 and 32 MHz the divider ratios 16 and 32 can be used Using higher divider ratios than required increases
233. the internal XRAM is used Semiconductor Group 3 4 1997 10 01 SIEM ENS Memory Organization C504 3 5 Special Function Registers The registers except the program counter and the four general purpose register banks reside in the special function register area The special function register area consists of two portions the standard special function register area and the mapped special function register area Three special function registers of the C504 PCON1 P1ANA P3ANA are located in the mapped special function register area For accessing the mapped special function register area bit RMAP in special function register SYSCON must be set All other special function registers of the C504 are located in the standard special function register area Special Function Register SYSCON Address B1 Reset Value XX10XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 BiH x EALE RMAP XMAP SYSCON The functions of the shaded bits are not described in this section Bit Function Not implemented Reserved for future use RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled RMAP 1 The access to the mapped special function register area is enabled As long as bit RMAP is set mapped special function registers can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped
234. the port latch leaves both output FETs off and the pin floats In that condition it can be used as high impedance input If port O is configured as general I O port and has to emit logic high level 1 external pullups are required Addr Data Control Int Bus Write to Latch MCS02434 Figure 6 3 Port 0 Circuitry Semiconductor Group 6 5 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 2 2 Port 1 and Port 3 Circuitry The pins of ports 1 and 3 are multifunctional They are port pins and also serve to implement special features as listed in table 6 2 Figure 6 4 shows a functional diagram of a port latch with alternate function To pass the alternate function to the output pin and vice versa however the gate between the latch and driver circuit must be open Thus to use the alternate input or output functions the corresponding bit latch in the port SFR has to contain a one 1 otherwise the pulldown FET is on and the port pin is stuck at 0 After reset all port latches contain ones 1 Alternate V Output ES Function Internal Pull Up Arrangement e o Pin Int Bus MCS01827 Alternate Input Function Figure 6 4 Ports 1 and 3 Semiconductor Group 6 6 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 1 2 3 Port 2 Circuitry As shown in figure 6 3 and below in figure 6 5 the output drivers of ports 0 and 2 can be switched to an internal addres
235. trena eni cure ohana eels TE re pcr PO bein Ru 6 6 6 1 2 3 POESIE doo M SRL OA bd cud Prec tte at Pes c e mut 6 7 6 1 3 Detailed Output Driver Circuitry liliis 6 9 6 1 3 1 Type B Port Driver Circuitry 0 us qe e edere RR ANE EG 6 9 6 1 3 2 Type C Port D ver CIFCUITD Lua sve Rd ie dE al Pete nee bad Rt 6 11 6 1 3 3 Typer D Por Driver CIE Guil orienta aora 6 12 6 1 3 4 Type E Port Driver CIrCUll V v c ERR ete ve ek ER Dx C x ERR 6 13 6 1 4 POET TIM ud as oros is a a e da 6 14 6 1 5 Port Loading and Interfacing ou iata t s en a ea rex ree UR 6 15 Semiconductor Group l 1 1997 10 01 SIEMENS General Information C504 Table of Contents Page 6 1 6 Read Modify Write Feature of Ports 2and 3 00 eee eee 6 16 6 2 Timers COUDIBIS iot RR CR ten REC Orbe tend Beda PE RR belle take 6 17 6 2 1 Eimer Counter Oana siu eb claros es 6 17 6 2 1 1 Timer Counter O and 1 Registers liliis 6 18 6 2 1 2 jx wc ee de Bander Scan oes Ga el de oe oS eae hace Soa 6 21 6 2 1 3 PAGS se deca da MC do ls ed o A uM Ce 6 22 6 2 1 4 Mode 20 reload o ote ct Na i t ar etal ol a di dot sue f 6 23 6 2 1 5 Modelos wets Fees iaa ea a E 6 24 6 2 2 Timer Counter 2 rica ore aa e AA tears 6 25 6 2 2 1 Timer Counter 2 Registers llle 6 26 6 2 2 2 Auto Reload Up or Down Counter o oocccccccc 6 28 6 2 2 3 A s God esae det ae Dent dd tue Dre eS dud afr eee uf pata ma Eu 6 31 6 3 Capture Compare Unit CC
236. upt 1 CCU Emergency Interrupt Timer 1 Interrupt Compare Timer 2 Interrupt Serial Channel Capture Compare Match Interrupt Timer 2 Interrupt Compare Timer 1 Interrupt Low Semiconductor Group 1997 10 01 SIEMENS Interrupt System C504 7 3 3 Interrupt Request Flags The interrupt request flags are located in different SFRs Table 7 3 shows the bit locations of the interrupt request flags More detailed information about the interrupt request flags is given in the sections of chapter 6 which describe the corresponding peripheral unit in detail Table 7 3 Locations of the Interrupt Request Flags Interrupt Sources Request SFR Byte Bit Flags Address Address External Interrupt 0 IEO TCON 88H 88H A D converter IADC ADC ADCONO D8y DDy Timer 0 Interrupt TFO TCON 88H 8Dy External Interrupt 1 IE1 TCON 88H 8By Timer 1 Interrupt TF1 TCON 88H 8FH Serial Channel RI SCON 98H 98H TI SCON 98H 99H Timer 2 Interrupt TF2 T2CON C8y CFH EXF2 T2CON C84 CEH External Interrupt 2 IT2 ITCON 9AH 9AH 7 Capture Compare Match Interrupt CCxR CCIR ESH ESH 0 2 4 CCxF CCIR ESy ESy 1 3 5 Compare Timer 1 Interrupt CT1FP CCIR ESH ESH 7 CT1FC CCIR ESy ES5y 6 Compare Timer 2 Interrupt CT2P CT2CON D2H D2H 7 CCU Emergency Interrupt TRF TRCON E7y E7y 6 BCERR BCON D7H D7y 3 Semiconductor Group 7 9 1997 10 01 SIEMENS Interrupt System C504 7 4 How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine
237. upt inputs are used to trigger the PWM signal generation logic Depending on these signal transitions the six I O lines of the CAPCOM unit which are decoupled in block commutation mode from the three capture compare channels are driven as static or PWM modulated outputs CAPCOM channel 0 can be used in block commutation mode for a capture operation speed measurement which is triggered by each transition at the external interrupt inputs Further the multi channel PWM mode signal generation can be also triggered by the period of compare timer 1 These operating modes are referenced as multi channel PWM modes Using the CTRAP input signal of the C504 the compare outputs can be put immediately into their passive state defined in COINI register and released again The CCU unit has four main interrupt sources with their specific interrupt vectors Interrupts can be generated at the compare timer 1 period match or count change events at the compare timer 2 period match event at a CAPCOM compare match or capture event and at a CAPCOM emergency event An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected All interrupt sources can be enabled disabled individually Semiconductor Group 6 34 1997 10 01 SIEMENS On Chip Peripheral Components C504 6 3 2 CAPCOM Unit Operation 6 3 2 1 CAPCOM Unit Clocking Scheme The CAPCOM unit is basically controlled by the 16 bit comp
238. ve 0 1 1 active inactive inactive inactive active inactive 0 0 1 inactive inactive active inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle 2 X X X inactive inactive inactive inactive inactive inactive 1 If one of these two combinations of INTx signals is detected in rotate left or rotate right mode bit BCERR flag is set If enabled a CCU emergency interrupt can be generated When these states error states are reached immediately idle state is entered 2 Idle state is also entered when a wrong follower is detected if bit BCON 7 BCEM is set When idle state is entered the BCERR flag is always set Idle state can only be left when the BCERR flag is reset by software In block commutation mode CAPCOM channel 0 is automatically configured for capture mode In block commutation mode any signal transition at INTO 2 generates a capture pulse for CAPCOM channel 0 CCHO CCLO independently on the selected INTO 2 signal transition type rising or falling edge as defined i
239. ve during external data memory accesses MOVX instructions and code memory accesses with an address greater than 3FFFy external code memory fetches If EA 0 the ALE generation is always enabled and the bit EALE has no effect After a hardware reset the ALE generation is enabled Special Function Register SYSCON Address B1 4 Reset Value XX10XXX0p Bit No MSB LSB 7 6 5 4 3 2 1 0 Bly EALE RMAP XMAP SYSCON The function of the shaded bit is not described in this section Bit Function Not implemented Reserved for future use EALE Enable ALE output EALE 0 ALE generation is disabled disables ALE signal generation during internal code memory accesses EA 1 With EA 1 ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 3FFFy EALE 1 ALE generation is enabled If EA 0 the ALE generation is always enabled and the bit EALE has no effect on the ALE generation Semiconductor Group 4 4 1997 10 01 SIEMENS External Bus Interface C504 4 5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers Emulation of on chip ROM based programs is possible too Each production chip has built in logic for the support of the Enhanced
240. w interrupt vectors an interrupt vector for the compare timer 1 reset count direction change event an interrupt vector for the compare timer 2 reset event an interrupt vector for a capture or compare match event and an interrupt vector for two emergency conditions of the CAPCOM unit trap and block commutation error Figure 7 1 and 2 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections Semiconductor Group 7 1 1997 10 01 SIEMENS Interrupt System C504 Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow P1 1 AN1 T2EX T2CON La 1 e e Z o e O e z EJE TCON 3 IENO 2 Q e Zz No e e Zz on ADCON 5 Bit addressable IEN1 0 C l Request Flag is cleared by hardware A D Converter Figure 7 1 Interrupt Request Sources Part 1 Semiconductor Group 7 2 Low Priority High Priority MCS02576 1997 10 01 SIEMENS Interrupt System C504 P3 6 WR INT2 Low Priority CON 7 TCON 4 TCON 5 E ITCON 6 EX IEN1 1 High Priority gt 1 P1 2 AN2 CCO CCIR 0 eo CCOREN CCIE0 0 oO CCRT CCOFEN CCIEO 1 eo P1 4 CC1 CCIR2 CC1REN CCIE0 2 Capture Compare Match Interrupt CCIR 3 oO CC1FEN CCIE0 3 IE
241. y Static passive compare values gt period value The bits CMSELx3 x 0 2 in the SFRs CMSELO CMSEL1 must be O The logic state of the inactive active phases at the CCx and COUTx outputs is defined by the bits in SFR COINI Compare timer 2 controlled active phase at COUTx When bit ESMC in SFR CMSEL1 is set compare timer 2 controlled output levels at COUTx during the active phase of a multi pole PWM timing are generated when the following conditions are met The 16 bit offset register of compare timer 1 must be 00004 CT1OFH CT1OFL 001 The 16 bit capture compare registers must be 0000H CCLO CCHO CCL1 CCH1 CCL2 CCH2 004 Bits CMSELx3 x 0 2 in the SFRs CMSELO CMSEL1 must be set Compare timer 2 must be enabled and initialized for compare output signal generation Both the CCx and the COUTx outputs can be controlled by compare timer 2 A combination of outputs modulated by compare timer 1 and or compare timer 2 is supported 6 3 4 6 Trap Function in Multi Channel Block Commutation Mode The trap function in the block commutation mode operates comparable to the trap function as described in chapter Table 6 3 2 7 Trap Function of the CAPCOM Unit in Compare Mode on page 44 But there is one difference when CTRAP becomes inactive high the CCx and COUTx outputs are again switched back to the PWM pulse generation when compare timer 2 reaches the count value 000y instead of compare timer 1 in all ot
242. y setting or clearing a bit in the SFRs IPO or IP1 interrupt priority O low priority 1 high priority Special Function Register IPO Address B8 Reset Value XX000000p Bit No MSB LSB 7 5 4 3 2 1 0 B8y PT2 PS PT1 PX1 PTO PXO IPO Bit Function Reserved bits for future use PT2 Timer 2 interrupt priority level If PT2 0 the Timer 2 interrupt has a low priority PS Serial channel interrupt priority level If PS 0 the Serial Channel interrupt has a low priority PT1 Timer 1 overflow interrupt priority level If PT1 0 the Timer 1 interrupt has a low priority PX1 External interrupt 1 priority level If PX1 0 the external interrupt 1 has a low priority PTO Timer 0 overflow interrupt priority level If PTO 0 the Timer 0 interrupt has a low priority PXO External interrupt 0 priority level If PXO O the external interrupt O has a low priority Semiconductor Group 7 7 1997 10 01 SIEMENS Interrupt System C504 Special Function Register IP1 Address B9 Reset Value XX000000p Bit No MSB LSB 7 6 5 4 3 2 1 0 B9y n PCT1 PCCM PCT2 PCEM PX2 PADC IP1 Bit Function Reserved bits for future use PCT1 Compare timer 1 interrupt priority level If PCT1 0 the compare timer interrupt has a low priority PCCM Capture compare match interrupt priority level If PCCM 0 the capture
243. y the addressed bit then write the complete byte back to the latch Table 6 3 Read Modify Write Instructions Instruction Function ANL Logic AND e g ANL P1 A ORL Logic OR e g ORL P2 A XRL Logic exclusive OR e g XRL P3 A JBC Jump if bit is set and clear bit e g JBC P1 1 LABEL CPL Complement bit e g CPL P3 0 INC Increment byte e g INC P4 DEC Decrement byte e g DEC P5 DJNZ Decrement and jump if not zero e g DJNZ P3 EL MOV Px y C Move carry bit to bit y of port x CLR Px y Clear bit y of port x SETB Px y Set bit y of port x The reason why read modify write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned on If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transitor approx 0 7 V i e a logic low level and interpret it as 0 For example when modifying a port bit by a SETB or CLR instruction another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch However reading the latch rater than the pin will return the correct value of 1 Semiconductor Group 6 16 1997 10 01 SIEMENS On Chip Peripheral Components C504

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