V1742_REV0 722KB Mar 08 2011 04:39:37 PM
Contents
1. 14 2 5 1 DAI T 14 2 6 INTERNAL COMPONENTS ccccsesssssccseceessssscsescececsesseessesecessesssesssssseseessssssssseseessnsssssesessesesesssesseseeeses 14 27 TECHNICAL SPECIFICATIONS 16 3 FUNCTIONAL DESCRIPTION S wisssscnsscssscessxcccsseveccessavosesenavesseussessvescsssasexcersssenecesustessssseccsstentecsevsstessersse 17 3 1 cANATEOG INPUT STAGE E EHE LEN CH Tee av e T EE CHEN NE 17 3 2 DOMINO RING 5 202 00 17 3 3 18 24 CLOCK DISTRIBUTION 19 3 4 1 Multi board synchronization 20 29 IDATASCORRECTION a s 21 3 5 1 21 3 5 2 Index sampling correction a Rte 22 3 5 3 TUNE sete 22 36 JEXENTSI2. 48 5 INSTALLATION aa sv soosse s 49 Jil POWER ON SEQUENGE ___ _ __ 49 52 POWERON STATUS Lis E E EEE a Qd as 49 5 3 HIRMWARE UPGRADE iier debet eie perpeti e e eei coda pee herir ti e orig bebe Peoria 49 NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 CAEN ls for Discovery Document type Title Revision date Revision Users Manual MUT 1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 LIST OF FIGURES Fic 1 1 1742 BLOCK DIAGRAM 9 FIG 2 1 MOD 1742 FRONT PANEL meteo cue e VY u p 11 BIG 2 2 MCX CONNECTOR 12 FIG 2 3 AMP CLK IN OUT CONNECTOR 12 FIG 2 4 PROGRAMMABLE IN OUT CONNECTOR cesscceseeecsseceeeeecaeceeceecaeceeeecsaeceeeecaeceeeecsaeceeeeecsaeceeeeesnaeenses 13 BIG 2 LC OPTICAL CONNECTOR 13 FIG 2 6 ROTARY AND DIP SWITCHES LOCATION c ccsssccesseecsseceeeeecsaeceseeecsaeceneeesaeceeneecsaeceeeecaeeeeeeecaeceeeeesnaeenees 15 FIG 3 ANALOG INPUT DIAGRAM Qu aa
3. 17 FIG 3 2 INPUT DIAGRAM 18 BIG 3 3 TRO LOGIC BLOCK DIAGRAM Se Exe euo Die peek danse 19 FIG 3 4 CLOCK DISTRIBUTION DIAGRAM 20 FIG 3 5 SAMPLED WAVEFORM AND NOISE HISTOGRAM BEFORE CELL OFFSET CORRECTION 21 FIG 3 6 SAMPLED WAVEFORM AND NOISE HISTOGRAM AFTER CELL OFFSET 21 FIG 3 7 SAMPLED WAVEFORM AND NOISE HISTOGRAM AFTER INDEX SAMPLING CORRECTION 22 FIG 3 8 SAMPLED TRO SIGNAL GRO AND BEFORE TIME 22 FIG 3 9 SAMPLED TRO SIGNAL GRO AND AFTER TIME CORRECTION 1 24 2 2 00 00 000000000000000000 4 23 Fic 3 10 INL TIME PROFILE OF DRS CHIPS 0 AND BEFORE TIME 23 Fic 3 11 INL TIME PROFILE OF DRS CHIPS 0 AND 1 AFTER TIME 44400 0440 0000 80 010000000000 24 FIG 3 12 EVENT FORMAT coner 25 FIG 3 13 GROUP DATA 26 Fic 3 14 BLOCK DIAGRAM OF TRIGGER MANAGEMENT 27 PIG 3 15 FPGA TEST WAVEEORM EE S Eee sve eee eee epe sess 29 FIG 3 16 A24 ADD
4. 50 Fig 3 1 Analog input diagram Domino Ring Sampling The analog input signals are continuously sampled into the DRS4s Domino Ring Sampler which consists of an on chip inverter chain domino wave circuit generating a maximum 5GS s sampling frequency 2 5GS s and 1GS s frequencies can be also programmed see 4 21 No external sampling clock is required This signal opens write switches in all 9 sampling channels where the differential input signals are sampled 1024 sampling capacitance cells per channel After being started the domino wave runs continuously in a circular fashion after the end of the ring samples are over written until decoupled from the write switches by a trigger signal which freezes the currently stored signal in the sampling capacitance cells Subsequently the cells are multiplexed into the 12 bit ADCs whose output are stored by the FPGA into the Digital Memory Buffer and ready for readout in the shape of events data A 16bit DAC allow to add up to 1V DC offset in order to preserve the full dynamic range also with uni polar positive or negative input signals Filename Number of pages Page 17 00103 09 V 1742x MUTx 00 V1742 REVO 50 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 3 NPO 16bit 8 D
5. 0x20 constant2 0 010 0x83 constant1 OxF014 0x84 constantO OxF018 0x01 c_code OxFO1C 0x43 r_code OxF020 0x52 oui2 024 0x00 oui 028 0x40 ouiO OxFO2C OxE6 vers OxF030 71742 VX1742 0x70 board2 OxF034 V1742 0x00 VX1742 0x01 board1 OxF038 0 06 OxFO3C revis3 040 0x00 revis2 OxF044 0x00 revis1 048 0x00 revisO OxFO4C 0x01 sernum1 OxFO80 0x00 sernumO OxF084 0x16 These data are written into one Flash page at Power ON the Flash content 15 loaded into the Configuration RAM where it is available for readout 4 3 Group n Channel Threshold 0x1n80 r w Bit Function 31 0 reserved 4 4 Group n Status 0x1n88 r Bit Function 8 DRS Chips Busy 7 Group Odd PLL Lock 6 Group Even PLL Lock 5 reserved 4 Group Odd Enable 3 Group Even Enable 2 SPI Bus Busy 1 Busy 0 SPI ready 1 Memory empty 0 Memory full 4 5 Daughter board FW revision 0x1n8C Bit Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 37 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Bits 31 16 contain the Rev
6. 4 46 NPO Scratch 20 Bit Function 31 0 Scratch to be used to write read words for VME test purposes Filename Number of pages 00103 09 V 1742 MUTx 00 V1742 REVO 50 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 47 Software Reset OxEF24 w 4 48 4 49 4 50 4 51 NPO Bit Function A write access to this register causes a board reset the acquisition 31 0 is stopped all the registers are set to the default settings and all data are cleared Software Clear OXEF28 w Bit Function 31 0 A write access to this register causes a data clear the registers setting is not modified Flash Enable OxEF2C r w Bit Function 0 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool Flash Data OxEF30 r w Bit Function 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool Configuration Reload OxEF34 w Bit Function 31 0 Awrite access to this register causes a software reset see 0 a reload of Configuration ROM parameters and PLL reconfiguration Filename Number of pages 00103 09 V 1742x MUTx 00 V1742 REVO 50
7. Filename Number of pages Page 8 00103 09 V 1742 MUTx 00 V1742 REVO 50 CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Table 1 1 Mod V1742 versions Model Code SRAM Memory Form factor V1742 WV1742BXAAAA 128 event ch 6U VME64 V1742B WV1742XAAAAA 1024 event ch 6U VME64 VX1742 WVX1742BXAAA 128 event ch 6U VME64X VX1742B WVX1742XAAAA 1024 event ch 6U VME64X 1 2 Block Diagram FRONT PANEL BUFFERS VME 2 press o T muc a lt m 500MHz g or gt ROC FPGA Readout control VME interface control Optical link control Trigger control External interface control Fig 1 1 Mod V1742 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742 REVO 50 9 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 Technical specifications 2 1 Packaging and Compliancy The module is housed in a 6U high 1U wide VME unit The board hosts the VME P1 and P
8. 00 S5 TROO HI S N 1 TROO S N 2 TROO S N 3 TROO HI 31 30 TRIGGER TIME TAG Fig 3 13 Group Data Format In the Group Event Description Word yellow in the figure above the following fields are shown Bit 29 20 Start Index Cell of DRS4 related to this event Bit 17 16 sampling frequency 00 5GS s 01 2 5GS s 10 1GS s 11 used Bit 12 tr 0 TRn signal not present in readout 1 TRn signal present in readout Bit 11 0 Size related to channel 0 7 number of 32 bit words when each channel has 1024 samples Size Ch 0 7 is If readout of TRn is disabled data related to such channel light blue in figure above are not present in the event if readout of TRn is enabled data size related to such channel is Size TRn Size Ch 0 7 8 Trigger Time Tag records the Trigger arrival time each bin has a 8 5ns width 3 6 1 Memory FULL management Bits of Acquisition Control register see 4 23 allows to select Memory FULL management mode NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 26 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 7 NPO TRG IN In Normal Mode the board becomes full whenever all buffers are full otherwise Always one buffer free mode it is possible to always keep one buffer free board be
9. A2818 A3818 Allows data alignment and consistency across multiple V1742 modules CLK_IN allows the synchronization to a common clock source S_IN ensures start acquisition times alignment Firmware can be upgraded via VME Optical Link VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast CyclesTransfer rate 60 5 MBLT64 100MB s 2eVME 160MB s 2eSST Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in VME crate with a BLT access Libraries C and LabView Demos and Software tools for Windows and Linux NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REVO 50 16 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 Functional description 3 1 3 2 NPO Analog input stage Input dynamic is 1Vpp on single ended MCX coaxial connectors Zin 50 Ohm A 16bit DAC allows to add up to 1V DC offset in order to preserve the full dynamic range also with uni polar positive or negative input signal The input bandwidth ranges from DC to 500 MHz Input Dynamic Range 1 Vpp MCX Input 1 50 Positive Unipolar DAC FSR 12 bit 0 50 Vref FPGA 16 bit 090 Negative Unipolar DAC 0 Bipolar DAC FSR 2 DRS4 AWW
10. CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ocsssccsssccasiessescesessedescenccssosonscdsesecessoseussSeassvsstonsedenseesssenseosedsbnecedesssesecdescsessnecacsses 8 1 15 OVERVIEW Zur gu 8 1 2 BE CK aiias 9 2 TECHNICAL SPECIFICA TIONS 10 21 PACKAGING AND COMPLIANCY a 10 2 2 POWER REQUIREMENTS 10 23 NUES A 11 24 EXTERNALCONNECTOBS ettet tenente __ ___ _ __ 12 2 4 1 INPUT CONKECIONS u 12 2 4 2 CONTROL u uu uQ 12 2 4 3 ADC REFERENCE CLOCK cCOnhheClOFs eoe te eee eee etae suco ene ares cu oa Ene uu M Qu W SAR asas 12 2 4 4 Digital T O Connect ete Hr ep Eve Lese toe pas 13 2 4 5 Optical LINK pa 13 2 5 OTHER FRONT PANEL COMPONENTS 0040 0 0 0
11. The TRO and TR1 are actually analog inputs but they are also TTL NIM compatible in order to use them as low latency external trigger signals it is necessary to set properly the Configuration Register Local TRn Trigger Enable bit see 83 3 Once the acquisition is triggered in one of the ways described above digitization takes place as described in S 3 2 Mezzanines Mother Board Memory TRG OUT Buffers N Acquisition Logic 5 8 8 Digital Enable Mask Thresholds TRO e TR1 VME Local Bus Interface Interface Fig 3 14 Block diagram of Trigger management Filename Number of pages Page 00103 09 1742 00 V1742_REVO 50 27 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 7 1 Trigger distribution 3 8 NPO The OR of all the enabled trigger sources after being synchronized with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG_OUT connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signa
12. w Bit Function Bits set to 1 means that the corresponding bits in the Group 31 0 Configuration register are set to 0 4 19 Buffer Organization 0x800C Bit Function 31 0 reserved always set to 0 4 20 Custom Size 0 8020 Bit Function 00 1024 sample ch 1 0 01 520 sample ch 10 256 sample ch 11 136 sample ch This register must not be written while acquisition is running 4 21 Initial test wave value 0x807C Bit Function 11 0 Test wave start value 4 22 Sampling Frequency 0x80D8 Bit Function 00 5 GS s 01 2 5 GS s 1 0 10 1 GS s 11 reserved do not use This register must not be written while acquisition is running NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REV0 50 41 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 23 Acquisition Control 0x8100 r w Bit Function 0 Normal Mode default board becomes full whenever all buffers are full see S 4 19 1 Always keep one buffer free board becomes full whenever N 1 buffers are full nr of blocks see 4 19 4 reserved 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 3 5 0 Acquisition STOP 2 1 Acquisition RUN allows to RUN STOP Acquisition 1 0 reserved Bit 2 allows to Run and Stop data acquisition
13. 34 Set Monitor DAC 0x8138 r w Bit Function 31 0 reserved 4 35 Board Info 0x8140 Bit Function 15 8 Memory size Mbyte Group 7 0 Board Type 0x06 4 36 Monitor Mode 0x8144 r w Bit Function 31 0 reserved 4 37 Event Size 0x814C r Bit Function 31 0 Nr of 32 bit words in the next event NPO Filename 00103 09 V1742x MUTx 00 V1742 REVO Number of pages Page 50 45 Tools for Discovery i Document type Title Revision date Revision User s Manual MUT Mod V 1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 38 VME Control r w Bit Function 0 Release On Register Access Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 6 0 RELOC Disabled BA is selected via Rotary Switch see 2 6 1 RELOC Enabled BA is selected via RELOC register see 4 42 5 0 ALIGN64 Disabled 1 ALIGN64 Enabled see S 3 13 1 2 0 BERR Not Enabled the module sends a DTACK signal until the CPU inquires the module 1 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 3 0 Optical Link interrupt disabled 1 Optical Link interrupt enabled 2 0 Interrupt level 07 interrupt disabled Bit 7 this setting is valid only for interrupts
14. 4 41 4 42 4 43 4 44 4 45 Title Revision date Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 CST Base Address and Control OxEFOC r w Bit Function Allows to set up the board for daisy chaining 00 disabled board 9 8 01 last board 10 first board 11 intermediate These bits contain the most significant bits of the MCST CBLT 7 0 address of the module set via VME i e the address used in MCST CBLT operations Relocation Address OxEF10 r w Bit Function These bits contains the A31 A16 bits of the address of the module 15 0 it can be set via VME for a relocation of the Base Address of the module Interrupt Status ID OxEF14 r w Bit Function 31 0 This register contains the STATUS ID that the module places on the VME data bus during the Interrupt Acknowledge cycle Interrupt Event Number OxEF18 r w Bit Function 9 0 INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events gt INTERRUPT EVENT NUMBER BLT Event Number OxEF1C r w Bit Function 7 0 This register defines the maximum number of events that can be transferred in a Block Transfer Cycle after which the board asserts the Bus Error to stop the transfer Allowed setting is between 0 meaning no limit and 255
15. 9 R W 38 4 9 DRS4 TEMPERATURE 2 2 2 21100240000000 000000000000000000000000500050500 38 4 10 CHANNEL N DAC SEL 0XINA4 R W 38 4 11 GROUP N CHANNEL TRIGGER MASK R W 39 4 12 MEMORY CALIBRATION TABLES ENABLE 39 4 13 MEMORY CALIBRATION TABLES DATA 0X1NDO R W 39 4 14 GROUP N TR THRESHOLD OXI NDA R W 39 4 15 GROUP N DC OFFSET R W 39 4 16 GROUP CONFIGURATION REGISTER 0X8000 R W a 40 4 17 GROUP CONFIGURATION BIT SET OX8004 W 41 4 18 GROUP CONFIGURATION BIT CLEAR 0X8008 W 41 4 19 BUFFER ORGANIZATION OX800C R W 2 4 1 412412 00 00000000 41 4 20 CUSTOM SIZE 0 8020 41 4 21 INITIAL TEST WAVE VALUE 0 807 2 2 1 2 2 2 4 004000000000000000000000000000000000000000000000000 41 4 22 SAMPLI
16. Page 48 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 5 Installation The Mod V1742 fits into all GU VME crates VX1742 versions require VME64X compliant crates Use only crates with forced cooling air flow the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion removal A CAUTION USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEAT MAY DAMAGE THE MODULE A CAUTION ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 5 1 Power ON sequence To power ON the board follow this procedure 1 insert the V1742 board into the crate 2 power up the crate 5 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration see 0 5 3 Firmware upgrade CAEN provides a firmware upgrade tool that can be used with either VME or optical link paths Download the software package application notes and user manual available at www caen it website path Products FrontEnd VME Digitizer V1742 then follow the instructions for installation and usage NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 49 for Discovery Document type Title Revision date Revis
17. TRG CLK are NIM I O Levels 1 TRG CLK TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only 15 7 6 4 31 Group Enable Mask 0 8120 r w Bit Function 3 0 Group 3 disabled 1 Group enabled 2 0 Group 2 disabled 1 Group 2 enabled 1 0 1 disabled 1 Group 1 enabled 0 0 0 disabled 1 Group 0 enabled Enabled groups provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 44 CAEN Document type Title User s Manual MUT 4 32 Bit Revision date Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Revision ROC FPGA Firmware Revision 0x8124 r Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 4 33 Event Stored 0x812C Bit Function 31 0 This register contains the number of events currently stored in the Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 4
18. continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0x0000 0x0FFC The events are readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is completed the relevant memory buffer becomes free and ready to be written again old data are lost After the last word in an event the first word Header of the subsequent event is readout It is not possible to readout an event partially NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 31 CAEN als for Disco ve ry Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 NPO 3 13 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in 3 5 We sug
19. external via front panel signal or an internal via local oscillator source selection is performed via dip switch SW1 see 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway REF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details available on http www analog com Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 19 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Fig 3 4 Clock distribution diagram 3 4 1 Multi board synchronization To be implemented NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REVO 50 20 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 5 Data correction Three types of data correction are required in order to compensate for unavoidable construction differences in the DRS4 chips All boards are factory calibrated during production test and correction parameters are saved on board see 5 3 Application software provided by CAEN recovers automatically the calibration parameters and runs them in order to c
20. when such bit is set to 1 the board enters Run mode and a Memory Reset see 3 10 2 is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected 5 4 24 Acquisition Status 0x8104 r Bit Function Board ready for acquisition PLL and ADCs are synchronized correctly 0 not ready 1 ready 8 This bit should be checked after software reset to ensure that the board will enter immediately run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag see 2 5 1 0 PLL loss of lock 7 1 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see 4 39 PLL Bypass mode see 2 5 1 6 0 No bypass mode 1 Bypass mode Clock source see 2 6 5 0 Internal 1 External 4 EVENT FULL it is set to 1 as the maximum nr of events to be read is reached 3 EVENT READY it is set to 1 as at least one event is available to readout 0 RUN off 2 1 RUNon 1 0 reserved NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 42 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 25 Software Trigger 0x8108 w Bit Function 31 0 A write acce
21. 0 1 0 4110 TOTAL EVENT SIZE LWORDS BOARD ID PATTERN GR MASK EVENT COUNTER EVENT TIME TAG GROUP 1 EVENT DESCRIPTION WORD GROUP 1 CHANNEL DATA GROUP 1 GROUP 1 TRIGGER TIME TAG GROUP 1 EVENT DESCRIPTION WORD n GROUP 1 CHANNEL DATA c GROUP 1 TRIGGER TIME TAG Fig 3 12 Event Format The Header is composed by four words namely Size of the event number of 32 bit words Board ID GEO 16 bit pattern latched on the LVDS I O one trigger arrives Group Mask 1 Groups participating to event ex GR2 and GR3 participating Gr_Mask OxC this information must be used by the software to acknowledge what Group the samples are coming from the first event contains the samples from the Group with the lowest number Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see 4 20 Trigger Time Tag It is 32 bit counter 31 bit count 1 overflow bit which is reset either as acquisition starts or via front panel Reset signal see 5 0 and is incremented at each sampling clock hit It is the trigger time reference Each group is composed by 8 analog channels group 0 channel 0 7 group 1 channel 8 15 etc and by the special channel TRn such signal is common to two groups it can be used as Local Trigger or digitized and stored with the data for high resolution timing analysis between the ADC channels and
22. 00 0 800 1600 2400 3200 4000 4800 Fig 3 15 FPGA test waveform Since an event is made up of up to 1024 samples the test event samples only a portion of the sawtooth the start point of the sampling can be programmed via Initial Test Wave Value register see 5 4 21 for example if this register is set to then the channels in the even groups sample the ramp between 255 and 1278 the channels in the odd groups instead sample the complementary value therefore between 3840 and 2817 3 10 Reset Clear and Default Configuration 3 10 1 Global Reset Global Reset is performed at Power ON of the module or via a VME RESET SYS RES see 5 4 47 It allows to clear the data off the Output Buffer the event counter and performs a FPGAs global reset which restores the FPGAs to the default configuration It initializes all counters to their initial state and clears all detected error conditions 3 10 2 Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a write access to Software Clear Register see S 4 48 or with a pulse sent to the front panel Memory Clear input see 3 8 NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 29 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 10 3 Timer Reset The Timer Reset allows
23. 2 connectors and fits into both VME VME64 standard and V430 backplanes VX1742 versions fit into VME64X compliant crates In all cases only well ventilated crates must be used 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1742 power requirements 5 5 5A 12 V 200 mA 12V 300 mA NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 10 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 3 Front Panel Mod V1742 z J Y Y Z Y EE N w Y Y Y 2 amp C Y EN 32 CH 12 BIT 5 GS s DIGITIZER Fig 2 1 Mod 1742 front panel NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 11 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 4 External connectors 2 4 1 INPUT connectors CHO Fig 2 2 MCX connector Function Analog input single ended Zin 50 Ohm TR 1 0 Fast TRG input Zin 50 Ohm Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER Suggested plug MCX 50 2 16 type Suggested cable RG174 type 2 4 2 CONTROL connectors Function e TRG OUT Local trigger outp
24. 30 3 11 1 3 Address relocation tron tte eR 31 3 12 DATA TRANSFER CAPABILITIES na 31 3 13 EVENTS READOUT Sa ness 31 31 3 13 1 1 SINGLE 32 3 13 1 2 BLOCK TRANSFER 032 064 2eVME 32 3 13 1 3 CHAINED BLOCK TRANSFER D32 D64 33 J132 Event Pollin scott E epi recae 33 3 14 iO auo M DI cc 33 3 15 SOFTWARE TOOLS Etuis RES ER Roe PU RENS ERU 33 Ae 35 4 1 REGISTERS ADDRESS sscccsssssssccesssecnsceesssecnsecesssvensceesssscnaecesssenseesssevonsecessevensesessssonsesensevensesenes 35 4 2 CONFIGURATION ROM 0 000 0 084 36 4 3 GROUP N CHANNEL THRESHOLD 0 1180 37 44 GROUP N STATUS OXING SER Geass anne 37 4 5 DAUGHTER BOARD FW REVISION 8 37 4 6 GROUP N BUFFER OCCUPANCY OX1N94 R 38 4 7 GROUP N CHANNEL DC OFFSET OX1N98 38 4 8 GROUP N ADC CONFIGURATION
25. D OxEF08 A24 A32 32 X X MULTICAST BASE ADDRESS amp CONTROL OxEFOC A24 A32 032 X RELOCATION ADDRESS OxEF10 A24 A32 032 X INTERRUPT STATUS ID OxEF14 A24 A32 032 X INTERRUPT EVENT NUMBER OxEF18 A24 A32 032 X X BLT EVENT NUMBER OxEF1C A24 A32 032 X X SCRATCH OxEF20 A24 A32 032 X X SW RESET OxEF24 A24 A32 032 W SW CLEAR OxEF28 A24 A32 032 W FLASH ENABLE OxEF2C A24 A32 032 X FLASH DATA OxEF30 A24 A32 032 X CONFIGURATION RELOAD OxEF34 A24 A32 032 W CONFIGURATION ROM 0 000 A24 A32 032 R 4 2 Configuration ROM 0 000 0 084 The following registers contain some module s information they are D32 accessible read only manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 36 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Table 4 2 ROM Address Map for the Model V1742 Description Address Content checksum OxFOOO 4 checksum length2 0 004 0x00 checksum length1 0 008 0x00 checksum_lengthO
26. E and Optical Link simultaneously Software tools CAEN provides a library designed to control all kind of digitizer models the CAENDigitizer available for both Linux and Windows platform 32 and 64Bits The library is oriented to C C programmers and for Labview developers The CAENDigitizer is in its turn implemented on a lower level library the CAENComm as described in the picture below Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 33 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 Application Leyer Hi level Layer Low level Layer Driver Layer Fig 3 21 Block diagram of the software tools Demo software applications that use CAENDigitizer library and tools to upgrade the digitizers firmware based on the CAENComm library are also available all demos and high level programs are provided with their source code and can be used as a starting point for the development of User specific applications For more information about the CAENDigitizer the CAENComm and all the high level software for this digitizer please see www caen it website Software download section NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 34 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Cap
27. NFIGURATION BIT SET 0x8004 A24 A32 032 W X X Group CONFIGURATION BIT CLEAR 0x8008 A24 A32 032 W BUFFER ORGANIZATION 0 800 A24 A32 032 X X CUSTOM SIZE 0x8020 A24 A32 032 X X INITIAL TEST WAVE 0x807C A24 A32 032 X X SAMPLING FREQUENCY 0 8008 24 32 032 X X ACQUISITION CONTROL 0x8100 A24 A32 032 X X ACQUISITION STATUS 0x8104 A24 A32 D32 R X X SW TRIGGER 0x8108 A24 A32 032 W TRIGGER SOURCE ENABLE MASK 0x810C A24 A32 032 X X FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 A24 A32 032 X X POST TRIGGER SETTING 0x8114 A24 A32 032 X X FRONT PANEL I O DATA 0x8118 A24 A32 032 FRONT PANEL I O CONTROL 0x811C A24 A32 032 X X Group ENABLE MASK 0x8120 A24 A32 032 X X ROC FPGA FIRMWARE REVISION 0x8124 A24 A32 032 NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 35 CAEN ols for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 REGISTER NAME ADDRESS ASIZE DSIZE MODE 55 RES CLR EVENT STORED 0x812C A24 A32 032 X X SET MONITOR DAC 0x8138 A24 A32 032 X X BOARD INFO 0x8140 A24 A32 D32 R MONITOR MODE 0x8144 A24 A32 032 X X EVENT SIZE 0x814C A24 A32 D32 R X X X VME CONTROL OxEFOO A24 A32 032 5 5 0 4 A24 A32 032 R BOARD I
28. NG FREQUENCY 0X80D8 41 NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REVO 50 4 CAEN Document um Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 23 ACQUISITION CONTROL 0 8 100 22 1 12 2 2 4 44 4 2 2 400402000000000000000000000000000000000000000 42 4 24 ACQUISITION STATUS 0 8104 42 4 25 SOFTWARE TRIGGER 0 8 108 43 4 26 TRIGGER SOURCE ENABLE MASK 0X810C R W nennen nennen nennen nennen ne 43 4 27 FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 R W 43 4 28 POST TRIGGER SETTING 0 8114 R W 43 4 29 FRONT PANEL I O DATA 0 8118 R W 44 4 30 FRONT PANEL I O CONTROL 0X81 1C 44 4 31 GROUP ENABLE MASK 0X8120 8 0 40 0 0020002 00000000000000000000000000000000000 entere enne nns 44 4 32 ROC FPGA FIRMWARE REVISION 0X8124 45 4 33 EVENT STORED OX812C 45 4 34 SET MONITOR DAC 0xX8138 R W aE EE E E EE SEAS E 45 4 35 BOARDINEO
29. RESSING costed pas 50 FIG 3 172A 32 Np bai NI 30 FIG 3 18 CR CSR ADDRESSING cive sedea rrio anaa 31 FIG 3 19 SOFTWARE RELOCATION OF BASE ADDRESS scccsssecesscesssecesneesseeceseeeeseeceneesnaeceseeesaeeceeneseneeceaeeesneeesaes 31 FIG 3 20 EXAMPLE OF BLT READOUT 32 FIG 3 21 BLOCK DIAGRAM OF THE SOFTWARE 5 34 LIST OF TABLES TABLET 1 MOD V 1742 VERSIONS cete rre ERR X ee e 9 TABLE 2 1 MODEL 1742 POWER 5 228 10 TABLE 2 2 FRONT I MIB E 14 NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742 REVO 50 6 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 TABLE 2 3 MOD V1742 TECHNICAL SPECIFICATIONS 16 TABLE 3 1 FRONT PANEL I OS DEFAULT SETTING 28 TABLE 4 1 ADDRESS MAP FOR THE MODEL V1742 e n eee nnn 35 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL 174 37 NPO Filename Number of pages Page 7 00103 09 1742 00 V1742 REVO 50 Too
30. RON nI Technical Information Manual Revision n 0 4 February 2011 MOD V1742 32 2 CH 12 BIT 5 GS s DIGITIZER MANUAL REV 0 NPO 00103 09 V1742x MUTx 00 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards
31. RS4 1 L i L lt DWBIE DIGITAL Analog Input 4T FPGA MEMORY BUFFER TRn Input G ADC 12bit C 16bit Fig 3 2 Input diagram Detailed documentation of the DRS4 is available at http drs web psi ch TRO and TR1 Inputs The module features two fast trigger inputs TRO and TR1 with extended level amplitude TTL NIM compatible TRO is common to group 0 ch 7 0 and 1 ch 15 8 TR1 to group 2 ch 23 16 and 3 ch 31 24 TRn signals can be used as external triggers see 3 7 Moreover they can be also sampled into the DRS4s analog memory buffers for applications where high resolution timing and time analysis with a common reference signal like a trigger or system clock is required this is achieved through the Configuration Register Signal TRn Readout Enable bit setting see 4 12 allows to store TRO input with samples coming from group 0 and 1 and TR1 with those from group 2 and 3 To properly handle bipolar signals and also unipolar positive or negative signal a 16 bit DAC allow you to add a DC offset to TRn offset value can be programmed via Group n DC Offset register see 4 7 When the TRn signals are used as trigger they are processed by an internal comparator whose threshold can be programmed via Group TRn Threshold register see 5 0 as the threshold is exceeded the FPGA triggers the DRS4 s and samples digitizing takes place The trigger signals c
32. RUGIUBE e es Cute 25 3 6 1 Memory FULL 26 2 7 TRIGGER MANAGEMENT uu l u u u osles soso epe ee 27 3 7 1 Trigger distribution eese esee esent enne 28 26 FRONT PANEL I OS iue DEDI 28 3 9 ten aee vende vue Pu gea aen Vene vn tese ven a ve E e 29 3 10 RESET CLEAR AND DEFAULT 29 29 3102 Memory 29 RES 30 3 11 VMEBUS m T 30 NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 3 CAEN Tools for Discovery Document type Title Revision date Revision Users Manual MUT 1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 14 Addressing capabilities 30 3 11 1 1 30 3 11 1 2 CR CSR 400658555 EH GRE
33. SR space indicating the slot number in the crate the recognized Address Modifier for this cycle is 2F This feature is implemented only on versions with 160pin connectors NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 30 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 31 2423 19118 1615 0 GEO OFFSET Fig 3 18 CR CSR addressing 3 11 1 3 Address relocation Relocation Address register see 4 42 allows to set via software the board Base Address valid values 7 0 Such register allows to overwrite the rotary switches settings its setting is enabled via VME Control Register see S 4 34 The used addresses are 31 2423 1615 0 OFFSET N lt software ADER ADERL relocation 31 24 23 1615 0 OFFSET d software ADERL relocation Fig 3 19 Software relocation of base address 3 12 Data transfer capabilities The board supports D32 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST 3 13 Events readout 3 13 1 Sequential readout The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can
34. TAO R 45 4 36 MONITOR MODE 0X8 144 R W nennen enne tnn nn susunan 45 4 37 EVENT SIZE OXS TAC ea ve 45 4 38 VME CONTROL 46 4 39 STAT S OXEFO4 C 46 4 40 BOARD ID 46 4 41 MCST BASE ADDRESS AND CONTROL OXEFOC R W a 47 4 42 RELOCATION ADDRESS OXEF10 R W 47 4 43 INTERRUPT STATUS ID OXEF14 2 4400040000 47 4 44 INTERRUPT EVENT NUMBER OXEF18 4 400120 000000100000000000000000000000050000 47 4 45 BLT EVENT NUMBER 8 47 4 46 SCRATCH OXEE20 R W J ueber d eet eo eoi 47 4 47 SOFTWARE RESET XBE24 e eb cases ede ea PE 48 4 48 SOFTWARE CLEAR OXEF28 W 48 449 FLASH ENABLE 2 R W 48 4 50 FLASH DATA XEE30 R W 48 4 51 CONFIGURATION RELOAD OXEF34 W
35. acitor Digitizer 04 02 2011 0 4 VME Interface The following sections will describe in detail the board s VME accessible registers content Registers whose name begins with Group n are referred to channel groups with index n in the address going from 0 to 3 each group is composed by eight subsequent channels N B bit fields that are not described in the register bit map are reserved and must not be over written by the User 4 1 Registers address map Table 4 1 Address Map for the Model V1742 REGISTER NAME ADDRESS ASIZE DSIZE MODE H_RES S_RES CLR EVENT READOUT BUFFER 0 0000 0 A24 A32 A64 D32 R Group Channel THRESHOLD 0x1n80 A24 A32 032 X X Group n STATUS 0x1n88 A24 A32 032 X X Daughter board FW revision Ox1n8C A24 A32 D32 R Group n BUFFER OCCUPANCY 0x1n94 A24 A32 032 R X X X Group n Channel DC offset 0x1n98 A24 A32 032 X X Group n DAC SEL 1 4 24 32 032 X X DRS4 n Temperature Ox1nAO A24 A32 032 R X X Group n CHANNEL TRIGGER ENABLE MASK Ox1nA8 A24 A32 032 X X Memory Calibration Tables ENABLE Ox1nCC A24 A32 032 Memory Calibration Tables DATA Ox1nDO A24 A32 032 Group n TR THRESHOLD Ox1nD4 A24 A32 032 R W X X Group n TR DC offset Ox1nDC A24 A32 032 X X Group CONFIGURATION 0x8000 A24 A32 032 X X Group CO
36. an be sensed either on the leading or the trailing edge depending on Configuration register setting see 4 12 Filename Number of pages Page 18 00103 09 V 1742 MUTx 00 V1742 REVO 50 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 4 NPO 4 GROUP 1 GROUP 0 DIGITAL FPGA MEMORY TRO Input 5 epe DRS4 4 BUFFER ADC 12bit COMP 4 16bit Fig 3 3 TRO logic block diagram Clock Distribution The module V1742 features a PLL for clock synthesis with a selectable internal or external reference clock source Multi board synchronization can be done by driving a clock on CLOCK IN input allowing all DRS4s to run synchronously with this external reference All analog inputs will be sampled at the same time without time drift allows high resolution timing and time analysis across multiple V1742 The module clock is provided by OSC CLK and REF CLK OSC CLK is a fixed 50MHz clock provided by an on board oscillator it handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure below REF CLK handles trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an
37. broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only n mode interrupt status can be removed by accessing VME Control register see 0 and disabling the active interrupt level n ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level gt 0 via VME Control register 4 4 39 VME Status OxEF04 Bit Function 3 0 VME FIFO not empty 1 VME FIFO empty 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register out 1 reserved 0 0 No Data Ready 1 Event Ready 4 40 Board ID 8 r w Bit Function 4 0 GEO VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 46 CAEN Document type User s Manual MUT
38. comes full whenever N 1buffers are full with N 7 nr of blocks In Normal Mode the board waits until one buffer is filled since FULL status is exited whether the trigger is overlapped or not The board exits FULL status at the moment which the last datum from the last channel participating to the event is read In Always one buffer free mode one buffer cannot be used therefore it is NOT POSSIBLE with this mode to set Buffer Code to 0000 see 4 19 but this allows to eliminate dead time when FULL status is exited Trigger management Signal digitization can be triggered basically in two ways e Common trigger a trigger produced via software via VME or Optical Link or sent via front panel TRG_IN signal NIM TTL signal on LEMO connector 50 Ohm impedance In this case all the channels in a board share the same trigger e Low latency trigger a logic level fed directly into the DRS4 via the front panel TRn signals In this case one TRn signal triggers two groups TRO for Groups 0 and 1 TR1 for Groups 2 and 3 As a trigger signal arrives the ADC analog buffers related to that trigger are frozen and then digitized with a 12bit resolution into the digital memory buffer During analog to digital conversion process the V1742 cannot handles other triggers this Dead Time is larger if also TRO and or TR1 input channels are sampled together with the analog inputs see 53 3
39. d Input range 1 Vpp Bandwidth gt 500MHz Programmable DAC for Offset Adjust x ch adjustment range 1V Sampling frequency Programmable 5 2 5 1GS s MCX 50 Ohm NIM TTL fast local trigger TRO for 15 TR1 for ch 16 31 and high resolution timing reference Based on DRS4 chip Switched capacitor ADC 1024 storage cells per channels simultaneously sampled at 5 2 5 1GS s selectable on all channels After trigger analog samples are digitized by external ADC 12 bit 110 5 Analog inputs only 181s Analog inputs TRO TR1 inputs sampling clock generation supports two operating modes PLL mode internal reference 50 MHz local oscillator PLL mode external reference on CLK_IN Jitter lt 100ppm Freq 50 MHz IN AMP Modu 11 AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available on request Jitter lt 100ppm TRG_IN LEMO 50 Ohm NIM TTL S_IN LEMO 50 Ohm NIM TTL 1 Altera Cyclone EP3C16 for 16 1 channels 128 event ch 1024 samples per event Multi Event Buffer with independent read and write access Common Trigger TRG_IN External signal Software from VME or Optical Link Fast local trigger Fast local trigger TRO and TR1 with individual programmable analog threshold CAEN proprietary protocol up to 80 MB s transfer rate Daisy chainable it is possible to connect up to 8 32 ADC modules to a single Optical Link Controller Mod
40. ecifications LC type connector to be used with Multimode 62 5 125 cable with LC connectors on both sides see also 3 14 CAEN provides optical fiber cables with a duplex connector on the A2818 side and two simplex connectors on the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s TX RX daisy chainable NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 13 CAEN for Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 5 Other front panel components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Colour Function DTACK green VME read write access to the board CLK_IN green External clock enabled NIM green Standard selection for CLK I O TRG OUT TRG IN S IN TTL green Standard selection for CLK I O TRG OUT TRG IN S IN LINK green yellow Network present Data transfer activity PLL LOCK green The PLL is locked to the reference clock PLL BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL LOCK LED is turned off RUN green RUN bit set see 4 24 TRG green Trigger accepted DRDY green E
41. gest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event 3 13 1 2 BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register see 4 45 Event Size 4 Group Size 16 bytes Group Size depends on Custom Size setting see 4 20 and whether TRn signals are stored in the event or not Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable BERR signal during BLT32 cycles in order to end the cycle avoiding filler readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below READOUT DATA 0 BUFFERS 1 2 3 Group size 1024 bytes BERR enabled BLT size 16384 bytes N 4 Fig 3 20 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGN64 bit in the VME Control register see S 4 34 MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are mu
42. h ofiundsampcorr txt histo_ch0_ofSindsampeon oe 1 300 R 0 200 400 600 800 1000 2075 2080 2085 Samples counts Fig 3 7 Sampled waveform and noise histogram after index sampling correction 3 5 3 Time correction The sampling sequence is handled by the DRS4 through 1024 physical delay lines the unavoidable construction differences between such delay lines must be compensated through a time calibration The following figures show the fast trigger signal TRO sampled by the DRS chip related to Group 0 and 1 and the integral non linearity INL time profile of DRS chips before and after correction 3500 T T T T wave tr gr notimecorr txt wave tr gr1 notimecorrtxt m 3000 f 2500 2000 ADC counts 1500 WC 1000 500 0 200 400 600 800 1000 Samples Fig 3 8 Sampled TRO signal GRO and before time correction NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 22 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3500 T T T T wave tr gr timecorrtx wave 971 timecorrtx 3000 2500 2000 ADC counts 1500 1000 F 500 0 200 400 600 800 1000 Samples F
43. he size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point where the previous cycle has ended 3 13 2 Event Polling 3 14 3 15 NPO A read access to Event Size register see 4 36 allows polling the number of 32 bit words composing the next event to be read this permits to perform a properly sized according to the Event Size information BLT readout from the Memory Event Buffer Optical Link The board houses a daisy chainable Optical Link communication path which uses optical fiber cables as physical transmission line able to transfer data at 80 MB s therefore it is possible to connect up to eight V1742 to a single Optical Link Controller for more information see www caen it path Products Front End PCI PCIe Optical Controller The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 see 0 allows to enable the module to broadcast an interrupt request on the Optical Link the enabled Optical Link Controllers propagate the interrupt on the PCI bus as a request from the Optical Link is sensed VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having higher priority anyway it is better to avoid accessing the board via VM
44. ig 3 9 Sampled TRO signal in GRO and after time correction 08 T T T T TimelNL 5GHz TimelN 5GHz txt Noise 0 6 0 200 400 600 800 1000 Samples Fig 3 10 INL time profile of DRS chips 0 and 1 before time correction NPO Filename Number of pages Page 00103 09 1742 00 V1742 REVO 50 23 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 ResidualTimelNL 5GHz chip tx ResidualTimelNL 5GHz chipi tx 0 200 400 600 800 1000 Samples Fig 3 11 INL time profile of DRS chips 0 and 1 after time correction NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REV0 50 24 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 6 Event structure An event is structured as follows Header four 32 bit words Data variable size and format The event can be readout either via VME or Optical Link data format is 32 bit word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1
45. ion User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 WARNING in case of programming failures the board can store two firmware versions caled STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the JP2 jumper see S 2 6 which can be placed either on the STD position left or in the BKP position right Please contact CAEN at support frontend a caen it for instructions in order to restore the backup image Once the board is successfully powered with backup firmware the standard firmware image can be reprogrammed NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 50
46. ision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 0112 June 2010 is 0xA6120103 4 6 Group n Buffer Occupancy 0x1n94 r Bit Function 10 0 Occupied buffers 0 1024 4 7 Group n Channel DC offset 0x1n98 r w Bit Function 19 16 Channel index from 0x0 to 0x7 only one DAC ch or OxF all DAC ch 15 0 DAC Data The input DC offset can be adjusted group per group and channel per channel by means of a programmable 16bit DAC there is a DAC serving each group 8 channels Default value 0 8 00 about OmV for input bipolar signals The channel index field bits 19 16 is used only in write access In read access channel index must be set on CH DAC SEL register see Channel DAC Select register For example in order to set the DAC Value 0 6 00 for channel 15 channel 7 of group 1 a write access to address 0x1198 with value 76 must be performed In order to readout the channel 15 DAC Value a write access to address 0x11A4 with value 0x7 must be performed and then a read access to address 0x1198 4 8 Group n ADC Configuration 0x1n9C r w Bit Function 31 0 reserved 4 9 DRS4 temperature 0 1 Bit Function 7 0 DRS4 temperature from 0 C to 127 C 4 10 Channel n DAC SEL 0x1nA4 Bit Function 3 0 DAC Channel index for read
47. l has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal Front Panel I Os V1742 is provided with 16 programmable general purpose LVDS I O signals Signals can be programmed via VME see 4 29 and 4 30 Default configuration is Table 3 1 Front Panel I Os default setting Nr Direction Description 0 out Group 0 Trigger Request 1 out Group Trigger Request 2 out Group 2 Trigger Request 3 out Group 3 Trigger Request 4 5 z 6 7 8 Memory Full 9 out Event Data Ready 10 out Channels Trigger 11 out RUN Status 12 in Trigger Time Tag Reset active low 13 in Memory Clear active low 14 RESERVED 15 RESERVED Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 28 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 9 Test pattern generator The FPGA can emulate the ADC and write into memory a sawtooth signal for test purposes It can be enabled via Group Configuration register see S 4 16 The following figure shows the test waveforms for even and odd groups respectively Even channel test wave 4800 4095 4000 3200 2400 1600 800 0 0 800 1600 2400 3200 4000 4800 Odd channel test wave 4800 4095 4000 3200 2400 1600 8
48. ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 1 General description 1 1 NPO Overview The Mod V1742 is a VME board housing two 16 1Channels 12bit 5GS s Switched Capacitor Digitizer sections based on DRS4 Domino Ring Sampler chip with 1 Vpp input dynamic range on single ended MCX coaxial connectors A VME64X mechanics version Mod VX1742 is also available The DC offset is adjustable via 16bit DAC x 1V range on each channel and allows tot sample either bipolar Vin 0 5V or unipolar full positive Vin 0 1V or negative Vin 0 1V analog input swing without losing dynamic resolution The analog input signals are continuously sampled into the DRS4s in a circular analog memory buffer 1024 cells default sampling frequency is 5GS s 2 5GS s and 1GS s frequencies can be also programmed As a trigger signal arrives all analog memory buffers are frozen and subsequently digitized with a 12bit resolution into a digital memory buffer The digital memory 128 events deep for each channel where 1 event 1024x12bit allows to store subsequent events even if the readout is not yet started Moreover since the digital memory buffers work like FIFOs the readout activity from VME or Optical Link does not affect write operations of subsequent events A common board trigger can be provided via VME or Optical Link o
49. ltiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals DS and DTACK to complete data cycle Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 32 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 13 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1742 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CBLT is based on the passing of a token between the boards it is necessary to verify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or last MCST Base Address and Control Register see 4 41 A common Base Address is then defined via the same register when a BLT cycle is executed at the address CBLT_Base 0 0000 OxOFFC the first board starts to transfer its data driving DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If t
50. orrect the stored data events 3 5 1 Cell offset correction Unavoidable construction differences between the analog memory cells see 3 1 require an amplitude calibration algorithm The following images show the sampled waveform and noise histogram before and after correction 25 wave_ch0_nocorection tar histo_ch0_nocorrection 229 2 20 0 2000 st 1950 x 5 200 400 600 Eo 1000 Fig 3 5 Sampled waveform and noise histogram before cell offset correction 2100 M r 1 r 300 wave_ch0_effsetcarrection bf histo ch cfsetcorectionor L1 250 F 2045 2090 2075 200 800 1000 2075 2080 2065 I 2050 2095 2100 Sarees Fig 3 6 Sampled waveform and noise histogram after cell offset correction NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742 REVO 50 21 CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 3 5 2 Index sampling correction It has been observed a fixed pattern noise introduced by the DRS4 over the last samples 30 samples in a waveform therefore the index sampling correction is necessary this correction actually reduces this noise thus anytime the best accuracy is required the last 30 samples should be rejected ave c
51. out from OxO to 0x7 For example in order to read the channel 15 DAC Value a write access to address 0x11A4 with value 0x7 channel 15 is channel 7 of group 1 must be performed and then a read access to address 0x1198 NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 38 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 11 Group Channel Trigger Mask 0x1nA8 r w Bit Function 31 0 reserved 4 12 Memory Calibration Tables Enable 0x1nCC Bit Function 0 0 Memory Calibration Tables ENABLED 1 Memory Calibration Tables DISABLED This register allows to access the memory location where calibration data are stored see 5 3 5 CAUTION before writing this register it is necessary to verify that SPI Bus Busy Flag in the Status register S 4 4 is 0 and in any case its use is reserved to experienced Users since a wrong value written in the Memory Calibration Data will erase the module s calibration pattern 4 13 Memory Calibration Tables Data 0x1nD0 Bit Function 7 0 Data to be serialized or read from Memory Tables calibration This register allows to access the memory location where calibration data are stored see 3 5 CAUTION before writing this register it is necessary to verify that SPI Bus Busy Flag in the Sta
52. r by TRG IN input Two special fast analog trigger inputs TRO and TR1 TTL NIM levels compatible can be used as lo latency external trigger signals These special inputs can be also sampled into the DRS4s analog memory buffers for applications where high resolution timing and time analysis with a common reference signal like a trigger or system clock is required During analog to digital conversion process the V1742 cannot handles other triggers this is called Dead Time Dead time will be increased if also TRO and or TR1 channels are sampled in the acquisition of the analog inputs The module V1742 features a PLL for clock synthesis with a selectable internal or external reference clock source Multi board synchronization can be done by driving a clock on CLOCK IN input allowing all DRS4s to run synchronously with this external reference All analog inputs will be sampled at the same time without time drift allows high resolution timing and time analysis across multiple V1742 The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer D32 32 64 bit Block Transfer BLT MBLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The board houses a daisy chainable Optical Link able to transfer data at 80 MB s thus it is possible to connect up to 8 ADC boards 256 16 ADC channels to a single Optical Link Controller Mod A2818 Optical Link and VME access are internally arbitrated
53. ss to this location generates a trigger via software 4 26 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 0 reserved EXTERNAL TRIGGER ENABLE bit30 enables the board to accept the TRG_IN SW TRIGGER ENABLE bit 31 enables the board to accept the software trigger see 4 25 4 27 Front Panel Trigger Out Enable Mask 0x8110 r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 4 reserved 3 0 Group 3 trigger disabled 1 Group 3 trigger enabled 2 0 Group 2 trigger disabled 1 Group 2 trigger enabled 1 0 Group 1 trigger disabled 1 Group 1 trigger enabled 0 0 Group 0 trigger disabled 1 Group 0 trigger enabled This register bits 3 0 enable the groups to generate a trigger as the relevant TRn signal signal TRO for group 0 1 and TR1 for group 2 3 exceeds the set threshold see 4 12 EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG_OUT SW TRIGGER ENABLE bit 31 enables the board to broadcast a software trigger see 4 25 4 28 Post Trigger Setting 0x8114 r w Bit Function 31 0 Size of the post trigger window The register value sets the size of the po
54. st trigger window expressed in step of about 8 5ns the maximum value for the post trigger is Ox7F Number of pages Page NPO Filename 43 00103 09 V 1742 MUTx 00 V1742 REVO 50 Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 29 Front Panel I O Data 0x8118 Bit Function 15 0 Front Panel I O Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outputs 4 30 Front Panel I O Control 0x811C r w Bit Function 0 I O Normal operations TRG OUT signals outside trigger presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see 4 26 1 Test Mode TRG OUT is a logic level set via bit 14 14 1 TRG OUT Test Mode set to 1 0 TRG OUT Test Mode set to 0 13 8 reserved 00 General Purpose I O 01 Programmed I O 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field 5 0 LVDS I O 15 12 are inputs 1 LVDS I O 15 12 are outputs 4 0 LVDS 11 8 are inputs 1 LVDS I O 11 8 outputs 3 0 2 LVDS I O 7 4 are inputs 1 2 LVDS I O 7 4 are outputs 2 0 LVDS I O 3 0 are inputs 1 2 LVDS I O 3 0 are outputs 0 panel output signals TRG OUT CLKOUT enabled 1 13 panel output signals TRG OUT CLKOUT enabled in high impedance 0 0
55. te write 0x1000 at address 0x10DC or 0x11DC write 0x7300 at address 0x10D4 or 0x11D4 write 0x1000 at address 0x12DC or 0x13DC write 0x7300 at address 0x12D4 or 0x13D4 If you are working with TRn TTL signal TR0 DC Offset 0x4000 write 0x4000 at address 0x10DC or 0x11DC TRO Threshold 0x7300 write 0x7300 at address 0x10D4 or 0x11D4 TR1 DC Offset 0x4000 write 0x4000 at address 0x12DC or 0x13DC TR1 Threshold 0x7300 write 0x7300 at address 0x12D4 or 0x13D4 Group Configuration Register 0x8000 r w Revision 0 Bit Function Select monitor signal from daughter board 0000 no signal 31 28 0001 all fast trigger 0010 accepted fast trigger 0011 busy 27 13 reserved MUST ALWAYS BE SET TO 0 TRn Trigger Enable when this bit is 1 TRn signal is used as local trigger 0 TRn Local Trigger disabled Default 1 TRn Local Trigger enabled 12 Signal TRn Readout Enable when this bit is 1 signal TRn is present in data readout 0 Signal TRn Readout disabled Default 1 Signal TRn Readout enabled 11 10 9 reserved MUST ALWAYS BE SET TO 0 8 Individual Trigger must be 1 7 reserved MUST ALWAYS BE SET TO 0 TR Trigger polarity 6 0 Rising Edge Default 1 Falling Edge 5 reserved MUST ALWAYS BE SET TO 0 4 reserved MUST ALWAYS BE SET TO 1 Test Mode when this bit is 1 the ADC samples are replaced by a 3 saw
56. the TRn itself NPO Filename Number of pages Page 00103 09 1742 00 V1742_REVO 50 25 CAEN Document type User s Manual MUT Title Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer Revision date Revision 04 02 2011 0 TRO can trigger Group 0 and Group 1 can be stored with data from Group 0 therefore the stored waveform will be labelled as 00 and with data from Group 1 therefore the stored waveform will be labelled as Tr01 TR1 can trigger Group 2 and Group 3 and can be stored with data from Group 2 therefore the stored waveform will be labelled as Tr12 and with data from Group 3 therefore the stored waveform will be labelled as Tr13 The part of an event related to each group has the following format example of Group 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10198 7 6 5 4 3 2 4 START INDEX CELL 0 0 FREQ O 0 0 TR SIZE CH 0 7 50 2 LO 50 1 S0 CHO S0 CH5 LO 50 4 50 S0 CH2 HI S0 CH7 S0 CH6 50 5 51 2 LO 51 1 51 S1 CH5 LO S1 CH4 S1 CH3 S1 CH2 HI S1 CH7 S1 CH6 51 5 S N 1 CH7 S N 1 CH6 S N 1 CH5 HI 52 00 LO 51 00 50 00 S5 TROO LO S4 TROO S3 TROO S2 TROO HI 57 00 56
57. to initialize the timer which allows to tag an event The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input see 3 8 3 11 VMEBus interface The module is provided with a fully compliant VME64 VME64X interface see 1 1 whose main features are EUROCARD 90 Format J1 P1 and J2 P2 with either 160 pins 5 rows or 96 3 rows connectors A24 A32 and CR CSR address modes D32 BLT MBLT 2eVME 2eSST data modes MCST write capability CBLT data transfers interrupter Configuration ROM 3 11 1 Addressing capabilities 3 11 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four rotary switches see S 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range 0x000000 OxFF0000 A24 mode 31 4 23 1615 0 OFFSET I SW4 SW5 E Fig 3 16 24 addressing 0 00000000 lt gt 0 0000 A32 mode 31 24 23 1615 0 OFFSET n I SW2 SW3 11 5004 sws Fig 3 17 A32 addressing The Base Address of the module is selected through four rotary switches see 2 6 then it is validated only with either a Power ON cycle or a System Reset see 0 3 11 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23 19 of CR C
58. tooth generated by the FPGA 0 Normal mode data from the DRS4 and ADC Default 12 Test Mode emulated data from the sawtooth generator 2 0 reserved MUST ALWAYS BE SET TO 0 There are three ways to write the content of the Configuration Register The use of the Bit Set Clear modes are recommended when concurrent processes can access the register this prevents a process to operate on the content of the register while another process has already changed it The read access to the Control Register Normal Write at address 0x8000 the content of the register is fully overwritten by the new data Bit Set Mode at address 0x8004 writing 1 one bit will set that bit writing 0 leaves the bit unchanged Bit Clear Mode at address 0x8008 writing 1 in one bit will clear that bit writing 0 leaves the bit unchanged can be done at 0x8000 address Filename Number of pages 00103 09 V 1742x MUTx 00 V1742 REVO 50 Page 40 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 4 17 Group Configuration Bit Set 0x8004 w Bit Function Bits set to 1 means that the corresponding bits in the Group 31 0 Configuration register are set to 1 4 18 Group Configuration Bit Clear 0x8008
59. tus register S 4 4 is 0 and in any case its use is reserved to experienced Users since a wrong value written in the Memory Calibration Data will erase the module s calibration pattern 4 14 Group n TR Threshold 0x1nD4 Bit Function 15 0 Threshold The threshold on TRn for local trigger generation can be set by a programmable 16bit DAC One TRn signal is common to two groups therefore for example write access to either 0x10D4 or 0x11D4 leads to the same setting for TRO input For TRn Threshold setting example see the paragraph below 4 15 Group n TR DC offset 0x1nDC r w Bit Function 15 0 DC Offset The TRn signal offset can be set by means of a programmable 16bit DAC For example in order to set the TRO signal common to groups 0 and 1 DC offset value to 0 6 00 a write access to address 0x10DC with value 0x56C00 must be performed One TR signal is common to two groups therefore for example write access to either 0x10DC or 0x11DC leads to the same setting Level setting example If you are working with TRn NIM signal NPO Filename Number of pages Page 00103 09 V 1742 MUTx 00 V1742 REVO 50 39 Tools for Discovery Document type User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 4 16 NPO TRO DC Offset 0x1000 TRO Threshold 0x7300 TR1 DC Offset 0x1000 TR1 Threshold 0x7300 Title Revision da
60. ut NIM TTL on Rt 50 Ohm e TRG IN External trigger input NIM TTL Zin 50 Ohm SYNC SAMPLE START S IN Sample front panel input NIM TTL Zin 50 Ohm 5 DAC output 1Vpp on Rt 50 Ohm Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors GND CLK Fig 2 3 AMP CLK IN OUT Connector CLK_IN Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdiff 100 Ohm Mechanical specifications AMP 3 102203 4 connector CLK_OUT Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 100 Ohm Mechanical specifications AMP 3 102203 4 connector NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 12 CAEN for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 4 4 Digital connectors r 9 9 6 t Q lt r Fig 2 4 Programmable IN OUT Connector Function N 16 programmable differential LVDS I O signals Zdiff_in 110 Ohm Four Independent signal group 0 3 4 7 8 11 12 15 In Out direction control Lowest couple 0 highest couple not connected See also 3 8 Mechanical specifications 3M 7634 5002 34 pin Header Connector 2 4 5 Optical LINK connector LINK TX red wrap RX black wrap Fig 2 5 LC Optical Connector Mechanical sp
61. vent data depending on acquisition mode are present in the Output Buffer BUSY red All the buffers are full OUT LVDS green Signal group OUT direction enabled 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Set the VME base address of the module SW3 CLOCK SOURCE Type Dip Switch Function Not Used SW1 FW Type Dip Switch Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD NPO Filename Number of pages Page 00103 09 V 1742x MUTx 00 V1742 REVO 50 14 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 AL E 02 RE _____ 2 Elias x r BELS 3579 PHI ml ticle reams Fig 2 6 Rotary and dip switches location NPO Filename Number of pages Page 00103 09 V1742x MUTx 00 V1742_REVO 50 15 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1742 3242 Ch 12bit 5GS s Switched Capacitor Digitizer 04 02 2011 0 2 7 Technical specifications table Table 2 3 Mod V1742 technical specifications 1 unit wide VME module 32 channels MCX 50 Ohm Single ende
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