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V862 User Manual

1. 8 10 PEEL ese 10 2 1 1 The input current to current 12 2 1 2 MEDIE 12 2 2 ANALOG TO DIGITAL CONVERSION 222 14 2 3 ZERO ae aenea 14 2 4 OVERFLOW 8 1 EAR Er EREE T are 16 2 5 MULTIPLE EVENT BUFFER MBB e dae Hsec dE dae oe E e ede PERIERE 16 916 5 EVENT ORE 17 Zela BUSY LOG C 18 2 6 18 20 JHASTCLEAR Z 19 3 5 e dta 20 E E 20 3 2 POWER REOUIREMEN
2. 2 3 0 TESTWORD 31 16 Fig 4 28 Test Word_High Register 4 30 Memory Test Word_Low Register Base Address 0x103A write only This register allows to set the lower 16 bits of the Test Word see above 7 6 5 4 Co 15114113112 ihe 9 2110 TESTWORD 15 0 Fig 4 29 Test Word_Low Register NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 54 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 4 31 Crate Select Register Base Address 0x103C read write This register contains the number of the crate which the board is plugged into This register must be filled at board initialisation and will be part of the data word see 4 5 0171 Fig 4 30 Crate Select Register 4 32 Test Event Write Register Base Address 0x103E write only This register is used in Acquisition Test Mode and its content constitutes the test event to be written in the MEB A write access to this register allows the User to write a set of 32 data into a 32 word TEST FIFO As the Bit 6 TEST ACQ of the Bit Set 2 Register see 4 26 is set to 1 and the Acquisition Test Mode is consequently selected these data are directly written in the MEB constituting an event which can be used to test the module and or the acquisition
3. 120 152 ns 4 60 92 ns 1 VME cycle timing D16 mode A 2 VME Cycle timing in BLT CBLT mode The figure below reports the Data Select DSO or DS1 Data Acknowledge VME cycle in BLT CBLT mode and relative timing The theoretical minimum duration of the VME cycle in BLT CBLT mode is 60 15 ns DS 1 Fig A 2 VME cycle timing in BLT CBLT mode NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 68 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 VME Cycle timing MBLT CBLT64 mode The figure below reports the Data Select DS Data Acknowledge DTACK VME cycle in MBLT CBLT64 mode and relative timing The theoretical minimum duration of the VME cycle in MBLT CBLT64 mode is 120 15 ns 1 108 1204152 ns 15ns 1 108 DTACK a 1 1 5 108 T 1 Fig A 3 VME cycle timing in MBLT CBLT64 mode NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 69
4. 56 4 37 SLIDE CONSTANT REGISTER PEDE ERE Vae esee oper yes ke Svante Er eda Pen es 57 4 38 57 4 39 BAD REGISTER Em 57 4 40 THRESHOLDS rete e a aai a aa e 57 4 41 ROM MEMORY 58 5 OPERATING 59 SEE uci d de EV C REPE 59 2 9 INSTALLATION d ERE 59 9 3 POWERON SEQUENCE Senos e eta Bep coe ePaper 60 94 POWERON EX V 60 3 9 OPERATION SEQUENCE 60 2 0 PESEMODES E E 61 5 6 1 Random Memory Access Test 62 5 002 Acquisition Test Mode isi eee 62 Xle BLOCK TRANSFER MODE ere eer eno eene ee TE AA EAEE ENE SE AEAEE E 63 5 8 ADVANCED SETTING AND READOUT MODES 64 5 8 1 Chained Block Transfer Modes isciani aeiae i apaan ie a ea aa ae EESE es 64 5 8 2
5. 0 4 414000000 000 0 0000000 000000000502 13 FIG 2 5 BLOCK DIAGRAM OF THE SLIDING SCALE SECTION 14 FIG 2 6 ZERO SUPPRESSION BIT 8 OF BIT SET 2 REGISTER 0 DEFAULT 5 15 FIG 2 7 ZERO SUPPRESSION BIT 8 OF BIT SET 2 5 rennen enne 15 FIG 2 8 MULTI EVENT BUFFER WRITE POINTER AND READ POINTER 2 17 FIG 2 9 FAST CEEAR WINDOW FE EE 19 FIG 3 12 MODEL V 862 d VI Em 21 E1G 3 2 INPUT CONNECTOR BLOCK A E RE TRU RE TERCER Hodie 22 FIG 3 3 CONTROL CONNECTOR PIN 55 2 2 1 20 20 0001 enne en tentent intent tenter ene 24 FIG 3 4 COMPONENT LOCATION COMPONENT 8 0 4 640000000050 000000000002 27 FIG 3 5 COMPONENTS LOCATION SOLDERING SIDE ccssescecesssececsseeececseceecsesaeeecsesaeeeceneeeeeeaeeecsesaeeesseeeeeneaaes 28 FIG 4 1 BINARY HEXADECIMAL REPRESENTATION OF THE BOARD ADDRESS IN GEO 31 FIG 4 2 BINARY HEXADECIMAL REPRESENTATION OF BIT SET 1 REGISTER ADDRESS IN GEO MODE 31 E16 4 5 BASE GBO ADDRESSING EXAMPLE eene a siea E EET ERE EE EE e eo 32 Fic 4 4 MCST CBLT ADDRESSING EXAMPLE 34 4 5 MEB THE HEADER e deri REV SENE EE e aeo
6. SER ERI FEVER ETE 13 TABLE 3 1 MODEL V862 POWER 5 20 TABLE 3 2 MODEL V862 MAIN TECHNICAL SPECIFICATIONS s ccssseceseeeessecesecesseeceneeeneeceseeesaeeceeneeenseceeeeeneeesees 29 TABLE 4 1 MODULE RECOGNISED ADDRESS MODIFIER esee ener entere inneren entretenir enne 30 TABLE 4 2 ADDRESS MAP FOR THE MODEL V 8602 esses eene teni trennen trennen 36 TABLE 4 3 ADDRESS MAP IN OPERATION eese eene entere enne entente entente entree enne 37 TABLE 4 4 ADDRESS MAP MCST OPERATIONS sccesceesseceseceessecesneecnsecesceessaeceeneesnaeceteessaecenersnaecereseneeeeaes 37 TABLE 4 5 ROM ADDRESS MAP FOR THE MODEL V862 esses eene nennen tenter entere eterne enne 58 NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 7 CAEN Document type User s Manual MUT Title Mod 862 32 channel Individual Gate Revision date 04 11 2009 Revision 8 1 General description 1 1 Overview The Model V862 is 1 unit wide VME 6U module housing 32 Charge to Digital Conversion channels with current integrating negative inputs positive voltage inputs available on request Each channel has an independent gate input GATE i in logical AND with a COMMON GATE input the input charge on the i th channel is converted to a voltage level by a QA
7. ess 4 18 MCST CBLT CONTROL REGISTER 4 19 EVENT TRIGGER REGISTER eene 4 20 STATUS REGISTER 2 4 2 EVENT COUNTER LOW REGISTER 4 22 EVENT COUNTER HIGH REGISTER 4 23 INCREMENT EVENT REGISTER eene 4 24 INCREMENT OFFSET REGISTER 4 25 FAST CLEAR WINDOW REGISTER 4 26 BIT SET 2 REGISTER 4 27 BIT CLEAR 2 5 44081 4 28 W MEMORY TEST ADDRESS REGISTER 4 29 MEMORY TEST WORD HIGH REGISTER 4 30 MEMORY TEST WORD LOW REGISTER 4 3 CRATE SELECT REGISTER eene NPO Filename 00102 97 V862x MUTx 08 V862 REV8 DOC Revision date Revision 04 11 2009 8 Number of pages Page 69 4 Disc Donnen ma i Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 4 32 TEST EVENT WRITE REGISTER 55 4 33 EVENT COUNTER RESET REGISTER i aE EA aeS a 56 4 34 PED REGISTER 5 56 4 35 R MEMORY TEST ADDRESS REGISTER 56 4 36 SW COMM REGISTER e
8. 29 Mu IN 30 4 1 GATE 30 D QAC 30 4 CONTROL LOGIC GATE 31 QAC 31 ence pese DUAL PORT MEMORY ACQUISITION CONTROL VME INTERFACE Front panel Fig 1 2 Model V862 Block Diagram NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 9 VME BUS CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 2 Principles of operation 2 1 NPO The board has 32 channel inputs 50 impedance negative polarity DC coupling 32 independent GATE i inputs ECL and one COMMON GATE input ECL NIM The integrated currents received from the i th channel input when both the GATE i and COMMON GATE signal are active are converted into voltage levels by the QAC sections and then multiplexed and digitized by two fast 12 bit ADC modules Only the values that are above a programmable threshold see 2 3 do not cause overflow see 2 4 and are not killed see 2 3 will be stored in a dual port data memory accessible via VME In the following functional sections and operation principles of the module are described in some detail The block diagram of the module can be found in Fig 1 2 QAC sections The module hosts 32 QAC sections a simplified block diagram of a QAC section is reported in Fig 2 1 The GATE i and the COMMON GATE signals cl
9. 9 9 0408 Read Write NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 36 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 gister content Address Interrupt Level 0x100A Interrupt Vector 0x100C Status Register 1 0x100E Control Register 1 k 0 1010 ADER High 0x1012 0x1014 Single Shot Reset 0x1016 MCST CBLT Ctrl 0x101A Event Trigger Register 0x1020 Read Write Status Register 2 0x1022 Read only Event Counter L 0 1024 Read only Event Counter_H Y 9 0 1026 Increment Event 221 0 1028 Increment Offset 0x102A Load Test Register 0x102C FCLR Window 0x102E Bit Set 2 0x1032 Read Write Bit Clear 2 0x1034 W Memory Test Address 0x1036 Memory Test Word_High Memory Test Word_Low Crate Select Test Event Write Event Counter Reset 0x1038 0 103 0 103 0 103 0 1040 0 1060 Test Address 0x1064 SW Comm 0 1068 0x1070 BAD 0x1072 Thresholds 0x1080 0x10BF 9 not all bits are reset with the same type of RESET see the description of the relevant register for details Write access is allowed only in AMNESIA cases see 4 13 i e when there is PAUX The ROM address map is from 0x8000 to OxFFFF refer to 4 41 Table 4 3 Address Map in CBLT operation
10. BUFFER 15 Fig 2 8 Multi Event Buffer Write pointer and Read pointer The MEB can be either in a Full a Not empty or an Empty status When the 5MSB of the Read pointer and the 5MSB of the Write pointer are different i e point to different events the MEB is in Not empty status When the Read pointer and the Write pointer are equal the MEB can be either in a Full or an Empty status The MEB is full or empty according to the last increment pointer operation performed if the last increment is the one of the Write pointer the MEB is Full if the last increment is the one of the Read pointer the MEB is Empty The status of the MEB is monitored via two Registers the Status Register 1 and the Status Register 2 see 4 13 and 4 20 respectively After the conversion the accepted data i e the converted values above the programmed threshold not causing overflow and not killed are stored in the active event buffer i e the one pointed by the write pointer in subsequent 32 bit words These are organised in events Each event consists of a Header see Fig 4 5 a block of data words Fig 4 6 and an End Of Block EOB word Fig 4 7 Each event contains thus from a minimum of 3 32 bit words Header one data word and EOB to a maximum of 34 32 bit words Header 32 data words and In case there are no accepted data the User can choose to store anyway in the MEB the Header and th
11. 54 FIG 4 28 TEST WORD HIGH REGISTER eiue nan o EU 54 FIG 4 29 TEST WORD LOW REGISTER 54 F1G 4 30 CRATE SELECT REGISTER ehe Pee LEER a PR EEUU Fe HR pae eee 55 FIG 4 31 TEST EVENT WRITE 55 FIG 4 327 PED REGISTER ppe E 56 FIG 4 33 R MEMORY TEST ADDRESS 56 FIG 4 34 SLIDE CONSTANT REGISTER ccssccesscecsseceeneecaccesncecssccsneeceacceseeecsacessneecsaececneecsaceseneecsaseseneecsaeeeeneeee 57 FIG 4 35 AAD REGISTER tse erbe eben aa e ous o ebbe reete ren be 57 FIG 4 36 BADD REGISTER EI 57 FIG 4 37 THRESHOLD 8 12 222 2 2 58 FIG A 1 VME CYCLE TIMING IN D16 MODE c cceccesseeeceseeenecoeecseeeneeeneesnesecesecseceaecsaeceaecaeecaeecaeeeseseneeenenerenarees 68 FIG A 2 VME CYCLE TIMING IN BLT CBLT 68 FIG A 3 VME CYCLE TIMING IN 69 LIST OF TABLES TABLE 1 1 VERSIONS AVAILABLE FOR THE MODEL V862 8 TABLE 2 J IPED VALUES
12. 8 bit 1 SLIDE SUBTRACTION D ENABLE 8 bit 8 bit 1 0 SLIDE ENABLE 5 5 UP SLIDE COUNTER CONSTANT Fig 2 5 Block diagram of the sliding scale section Zero suppression The output of the ADC is fed to a threshold comparator to perform the zero suppression If the converted value from a channel is greater than or equal to the relevant low threshold value set via VME in the Thresholds memory Base Address 0x1080 0 10 see 5 4 40 the result is fed to the dual port memory and will be available for the readout If the converted value is lower than the threshold the value is stored in the memory only if the LOW TRESHOLD PROG bit of the Bit Set 2 Register is set to 1 see 4 26 The fact that the converted value was under the threshold is also flagged in the datum stored Filename Number of pages Page 14 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 NPO the memory where the bit 13 UNDERTHRESHOLD of the 16 bit data word is set to 1 see 4 5 The Thresholds memory allows to set a low threshold value for each channel Default setting corresponds to thresholds not defined By setting the bit 8 in the Bit Set 2 Register it is possible to program the Threshol
13. Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 Function they allow the insertion of the Bus termination on the relevant line The 110 Q termination must be inserted the lines of the last board of the chain In order to insert the termination on given line both the positive and the negative DIP switches must be set refer to Fig 3 4 Right position dot visible the termination is inserted on the relevant line Left position dot not visible the termination is not inserted 3 6 3 Jumpers J12 Function it allows to select board behaviour in response to a BUSY status Position A high data acquisition is stopped as soon as any of the boards on the CONTROL Bus is BUSY Position B low data acquisition is stopped as the board is BUSY independently from the status of the other boards on the CONTROL Bus Refer to Fig 3 4 for the exact location of the jumper on the PCB and its setting NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 26 CAEN Tools for Discover Document type Title User s Manual MUT Mod V862 32 channel Individual Gate QDC Revision date Revision 04 11 2009 8 Rotary switches for VME address selection Base address bit lt 19 16 gt Ba
14. Multicast Commands E A A E 65 55 E 66 APPENDIX 67 VME INTERFACE TIMING 67 VME CYCLE TIMING IN D16 D32 MODE 2 a Aa E 68 2 VME CYCLE TIMING IN BLT MODE 68 VME CYCLE TIMING IN MBLT CBLT64 69 NPO 00102 97 V862x MUTx 08 Filename V862_REV8 DOC Number of pages Page 69 5 CAEN ls for Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 LIST OF FIGURES Fic 1 1 MODEL TYPE LABEL EXAMPLE V 862 7 8 FIG 1 2 MODEL V862 BLOCK DIAGRAM cesccecsssceeseecsseceeeeecaeceneecaaeceeeecaaeceseeecsaeceseeecnaeceeeecaaeceeeeeenaecneeeeenaeens 9 2 1 SIMPLIFIED BLOCK DIAGRAM OF THE QAC 5 10 FIG 2 2 SIGNAL CONVERSION TIMING 2 fee soe eei en esaet inre peste Eee spe 11 FIG 2 3 INPUT STAGE SIMPLIFIED MODEL ccssssccecesssecessnsecseseececsscceceesseseceenseeecesseecessaesesseneececsessecsesneeensnaes 12 FIG 2 4 IPED uA VS IPED REGISTER SETTING
15. Refer to Fig 3 5 for the exact location of these pads on the PCB and their settings MM GND Soldering pad to connect the 1 of the CONTROL connector to the DIGITAL GROUND 59 Soldering pad to connect the pin2 of the CONTROL connector to the VEE power supply 5V p Fig 3 5 Components location soldering side NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 28 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 3 7 Technical specifications table Table 3 2 Model V862 main technical specifications Packaging 6U high 1U wide VME unit version AA requires the V430 backplane Power requirements Refer to Table 3 1 Input signals 32 channels 50 impedance negative polarity DC coupling Individual gate 32 differential ECL signals Resolution 12 bit Integral non linearity 0 1 of Full Scale Range uniformity Interchannel Isolation gt 60 0 002 count mV 5V 0 01 count mV 5V Power rejection 0 0046 count mV 12V 0 0012 count mV 12V Conversion time 5 7 us for all channels GATE COMMON input NIM signal high impedance active high differential ECL input signals GATE common enabling signal for current integration RST resets QAC sections MEB status and control registers VETO inhibits the conversion of
16. 04 11 2009 8 4 41 NPO THRESHOLD VALUE Fig 4 37 Threshold Register KILL K allows to abort memorisation of the data from the relevant channel 0 channel data are memorised 1 channel data memorisation is aborted THRESHOLD VALUE see 2 3 Default settings are not defined Please note that the KILL option can be used for channel disabling N B the threshold values are reset only with a hardware reset and when the board is switched off ROM memory Base Address 0x8000 OxFFFE read only It contains some useful information according to the table below such as e manufacturer identifier IEEE OUI e Version purchased version of the Mod V862 e Board Board identifier 862 e Revision hardware revision identifier Serial MSB serial number MSB e Serial LSB serial number LSB Table 4 5 ROM Address Map for the Model V862 Description Address OUI MSB 0x8026 OUI 0 802 OUI LSB 0 802 Version 0x8032 BOARD ID MSB 0x8036 BOARD ID 0 803 BOARD ID LSB 0 803 Revision 0 804 Serial 5 Ox8F02 Serial LSB Ox8F06 Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 58 Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 5 Operating modes 5 1 Safety information This section contains the fundamental safety rules for the i
17. 1 see 5 4 26 the Reset is released via the Bit Clear 2 Register see S 4 27 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 0 see 5 4 14 Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 18 for Disco Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 2 9 NPO The Software RESET performs the same actions as the data RESET and moreover it resets the registers marked in the column SR Software Reset in Table 4 2 This type of RESET can be forwarded in three ways 1 setting the Bit 7 SOFTWARE RESET of the Bit Set 1 Register to 1 see S 4 9 this sets the module to a permanent RESET status which is released only via write access with the relevant bit set to 1 to the Bit Clear Register 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 1 see 8 4 14 3 performing a write access to the Single Shot Reset Register see S 4 17 the RESET lasts as long as the write access itself The Hardware RESET performs the same actions as the Software RESET and moreover it resets further registers All the registers reset by a Hardware RESET are marked in the column HR Hardware Reset in Table 4 2 This type of RESET is performed 1 at Power ON of the module 2 viaa VME RESET SYS RES At power O
18. 108 79 205 11502 220 121 25 235 127 55 250 133 77 255 135 88 90 00 80 00 70 00 60 00 2 50 00 40 00 30 00 20 00 10 00 0 00 0 50 100 150 200 250 300 Iped register DAC count Fig 2 4 Iped uA Vs IPED Register setting NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 13 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 2 2 Analog to digital conversion 2 3 NPO The output of each QAC section is multiplexed by group of 4 channels and subsequently converted by two fast 12 bit ADCs each of which operates the conversion on a group of 16 channels Block A and Block B ADCs The ADC section supports the sliding scale technique to reduce the differential non linearity see references 1 2 This technique see Fig 2 5 consists in adding a known value to the analog level to be converted thus spanning different ADC conversion regions with the same analog value The known level is then digitally subtracted after the conversion and the final value is sent to the threshold comparator If the sliding scale is enabled it reduces slightly the dynamic range of the ADC the 12 bit digital output is valid from 0 to 3840 while the values from 3841 to 4095 not correct OVER gt gt to the Control Logic A From MUXes 12 bit D to the memories 0 4 bit
19. A write access with a bit to 1 sets the relevant bit to 1 in the register A write access with the bit set to O does not clear the register content the Bit Clear 2 Register must be used see 8 4 27 A read access returns the status of the register The register content is the following Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 51 CAEN Document type Title User s Manual MUT Revision date Revision Mod 862 32 channel Individual Gate QDC 04 11 2009 8 151413 MEM TEST OFFLINE CLEAR DATA OVER RANGE PROG LOW TRESHOLD PROG Not used TEST ACQ SLD ENABLE STEP TH Not used Not used AUTO INCR EMPTY PROG SLD_SUB ENABLE ALL TRG Fig 4 26 Bit set 2 register MEM TEST Test bit allows to select the Random Memory Access Test Mode see 5 6 1 0 normal mode default 1 Random Memory Access Test Mode selected it is possible to write directly into the memory OFFLINE Offline bit allows to select the ADC controller s status 0 ADC controller online default 1 ADC controller offline no conversion is performed CLEAR DATA Allows to generate a reset signal which clears the data the write and read pointers the event counter and the QAC sections 0 no data reset is generated default 1 a data reset signal is generated OVER RANGE Allows to disable overflow suppression see also 5 2 4 0 over range check enabled only the da
20. BOARD and only the LAST BOARD bit set to 1 in the MCST Control Register see S 4 8 Conversely all intermediate boards must have both the FIRST BOARD and the LAST BOARD bits set either to 1 or to O 5 8 1 Chained Block Transfer Mode Once set the address of the boards as described in the above section the boards can be accessed in Chained Block Transfer mode see This mode allows for sequential readout of a certain number of contiguous boards in a VME crate A CBLT access is allowed with the BLT32 and MBLT64 address modifiers only CBLT32 and CBLT64 accesses respectively N B The CBLT operation can be performed only for the readout of the Multi Event Buffer its address in CBLT mode corresponds to the set of offsets listed in 4 4 to be added to the address common to all boards set by the User via the MCST CBLT Address Register which contains the most significant bits of the address see 4 8 Filename Number of pages Page 64 00102 97 V862x MUTx 08 V862_REV8 DOC 69 for Disco Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 NPO The User must perform a number of CBLT accesses that allows for the readout of all data in all boards of the chain in all possible occupancy conditions E g if the User has a chain of 10 boards the total number of words for a given event lies between 0 i e no data and 34x10 340 32 bit words
21. Eb AK 46 FIG 4 18 ADER HIGH 5 47 Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 6 Ws for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate 04 11 2009 8 PIG 4 JOVADER LOW REGISTER 2 2220 47 E1G 4 20 MCST ADDRESS REGISTER eere ee reto epo cv 47 FIG 4 21 EVENT TRIGGER 1 48 FIGs 422 STATUS REGISTER 2 25 aiae Er aE AE RAEE nn 49 FIG 4 23 EVENT COUNTER LOW REGISTER sccessceessecesceecaeceseeecaeceseeecsaeceeeecsaeceeneeesaeceeeecsaeeeeneeenaeceneeenaeeeeee 49 FIG 4 24 EVENT COUNTER HIGH REGISTER torre voit seen 50 FIG 4 25 FAST CLEAR WINDOW REGISTER sccessceeseceseeecsaeceneecaaeceeeeecsaeceeeecnaeceeneecsaeceeeeesaeeeeneecnaeceeneesnaeeeees 51 FIG 4 26 BIT SET 2 5 52 FIG 4 27 W MEMORY TEST ADDRESS REGISTER
22. Mod Mod supply V862 AA V862 AC NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 20 CAEN Document type Title User s Manual MUT Mod V862 32 channel Individual Gate QDC 3 3 Front Panel CAE Mod V862 DTACK VME selected LED gt PWR overcurrent power on status LED termination status LED Block INPUT connector Ch 16 31 PWR switch Block A INPUT connector Ch 0 15 GATE COMMON NIM input connector CONTROL connector gt DTACK 31 ove PWR TERM gt 2 gt 2 BUSY RST DRDY VETO BUSY e DRDY 32 CH INDIVIDUAL GATE Revision date Revision 04 11 2009 8 BUSY status LED 4 not used 44 Data Ready LED Fig 3 1 Model V862 front panel NPO Filename 00102 97 V862x MUTx 08 V862_REV8 DOC Number of pages Page 69 21 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 3 4 External connectors The location of the connectors is shown in Fig 3 1 Their function and electro mechanical specifications are listed in the following subsec
23. Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 2 4 2 5 NPO If the result of the comparison is true and the Bit 4 LOW THRESHOLD PROG of the Bit Set 2 Register is set to 0 data are skipped If the Bit 4 of the Bit Set 2 Register is set to 1 the true result of the comparison is signaled by Bit 13 UNDERTHRESHOLD 1 in the loaded data 16 bit word The content of the Threshold Register includes also a KILL bit which allows to abort the memorisation of the datum even if it is higher than the threshold set in the register This bit can thus be used to disable some channels Refer to 4 40 for further details The threshold values are lost only after switching the board off a reset operation does not affect the threshold values Overflow suppression The overflow suppression allows to abort the memorisation of data which originated an ADC overflow The control logic provides to check if the output of the ADC is in overflow and in the case the value is not stored in the memory The overflow suppression can be disabled by means of the OVER RANGE PROG bit of the Bit Set 2 Register see 4 26 if this bit is set to 1 all the data independently from the fact that they caused ADC overflow or not are stored in the memory In this case the 16 bit word stored in the memory will have the bit 12 OVERFLOW set to 1 see 4 5 Multiple Event Buffer MEB After the
24. control bus is terminated If only some lines are terminated it is off It also lights up orange for a while at power ON to indicate that the board is configuring OVC PWR Colour green orange 3 5 2 Switches PWR Function it lights up green when the board is inserted into the crate and the crate is powered up when it is orange it indicates that there is an over current status in this case remove the overload source switch the module off and then switch it on again Type miniature flush plunger push button switch Function after the insertion of the board into the crate it allows to turn the board ON OFF by pushing it with a pin Refer to 5 3 for the power ON procedure 3 6 Internal hardware components The V862 module is constituted by a motherboard with a piggy back board plugged into it see also Fig 1 2 where the functional blocks hosted on the piggy back board are pointed out In the following some hardware setting components located on the boards are listed Refer to Fig 3 4 and Fig 3 5 for their exact location on the PCB and their settings 3 6 2 Switches ROTARY SWITCHES TERM ON NPO 00102 97 V862x MUTx 08 Filename Type 4 rotary switches Function they allow to select the VME address of the module Please refer to Fig 3 4 for their settings Type 14 DIP switches a couple positive and negative for each control signal Number of pages Page V862_REV8 DOC 69 25 CAEN
25. conversion if there is at least one converted value above the programmed threshold not causing overflow and not killed the control logic stores it in the Multi Event Buffer The Multi Event Buffer is a Dual Port Memory 34 Words event which can store up to 32 events It is mapped at the VME address Base Address 0x0000 0x07FC see also 4 5 In order to trace the event flow two pointers Read and Write pointer are employed The Read Pointer points to the active read buffer The Write pointer is incremented automatically via hardware at the end of the channels conversion while the Read pointer can be either incremented automatically AUTO INCR bit of the Bit Set 2 Register set to 1 see 4 26 or via write access to one of two dummy registers Increment Event and Increment Offset Registers see 4 23 4 24 These allow to move the readout pointer to the next event in the output buffer or to the next word respectively A read write access to any location within the MEB memory segment results in a read write operation at the location marked by the Read Write pointer Filename Number of pages Page 16 00102 97 V862x MUTx 08 V862_REV8 DOC 69 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 WRITE POINTER READ POINTER BUFFERO gt BUFFER 1 BUFFER 2 BUFFER 14
26. e SERRE E ERE VEU EE MER RE 38 FIG 4 6 MEB THE DATA WORD FORMAT 22 2 2 04 0 0 38 Fic 4 7 MEB THE END 38 FIG 4 82 MEB NOT VALID DATUM EP 40 FIG 4 9 MULTI EVENT BUFFER DATA STRUCTURE 0 2 2 2 2 0 0 nennen en nnne tnnt en retener en nene tne 40 FIG 4 10 FIRMWARE REVISION REGISTER scccesscessseceeeeesseeceeeesseeceeeeecsaeceeneeeaeeceeeeecaaeceeeeecaaeceeeecnaeceeneesnaeeeee 41 FIG 4 11 GEOGRAPHICAL ADDRESS REGISTER s csesceceseeeeseeceseeesseecsaceeeneecsaceesncecseceeeneecaeeeeneeceeereneeceatereneeesaes 41 FIG 4 12 MCST CBLT ADDRESS 5 42 FIG 4 19 BIT SETI REGISTER s 43 FIG 4 14 INTERRUPT LEVEL REGISTER 44 FIG 4 15 INTERRUPT VECTOR 1 44 FiG 4 16 STATUS REGISTER l PT 44 BIG 4 17 CONTROL REGISTER spe vedere vr pas EE EYE obe
27. i e each board has an event each event consists of a Header 32 data End of Block In order to be sure that a BERR is generated the User must thus perform 11 CBLT accesses of 34 word each In CBLT32 mode the first board of the chain starts sending data if there are any i e if it is not purged see 5 4 13 as it has sent all data and the EOB is met the board becomes purged i e the relevant bit PURGED of the Status Register 1 is set to 1 This implies that the board will not be involved in the CBLT access any more since it has already sent all the required data At this point the IACKOUT line is asserted and the next board if not purged starts sending data As the last board receives the token and is purged it asserts a BERR which acts as a data readout completion flag In CBLT64 mode the accesses work as in the CBLT32 one except for the fact that the address is acknowledged during the first cycle and consequently a DTACK is asserted at least once CBLT mode the Read Pointer must be incremented automatically if the AUTOINC ENABLE bit is set to 1 in the Bit Set 2 Register see S 4 26 the Read Pointer is automatically incremented with the readout of the End Of Block word of each board if the AUTOINC ENABLE bit is set to 0 the Read Pointer is not automatically incremented and only the Header of the first word is read N B Please note that according to the VME standard a Chained Block Transfer readout can be performed wit
28. of the module 1 15 41321110 9 81716 514131211 0 LAST BOARD FIRST BOARD Fig 4 20 MCST Address Register NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 47 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 LAST BOARD Last Board flag bit valid in CBLT and MCST modes only FIRST BOARD First Board flag bit valid in CBLT and MCST modes only The status of the boards according to the bit value is the following BOARD STATUS FIRST BOARD LAST BOARD bit bit Board disabled in CBLT or MCST chain 0 9 First board in CBLT or MCST chain Last board MCST chain Active intermediate board MCST chain Bits 2 to 15 are meaningless 4 19 Event Trigger Register Base Address 0x1020 read write This register contains a 5 bit value set by the User when the number of events stored in the memory equals this value an interrupt request is generated Default setting is 0 in this case the interrupt generation is disabled See also 4 2 EV TRG 4 0 Fig 4 21 Event Trigger Register 4 20 Status Register 2 Base Address 0x1022 read only This register contains further information on the status of the module MEB and on the type of piggy back p
29. or to the Increment Offset Register see below 4 24 Increment Offset Register NPO Base Address 0x102A write only A write access to this dummy register increments the readout pointer of one position next word same event if EOB is not encountered next event if EOB is encountered Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 50 Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 In particular if the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 5 4 26 the readout pointer is no more automatically incremented but it can be incremented via write access to this register or to the Increment Event Register see above 4 25 Fast Clear Window Register Base Address 0 102 read write For the definition of the Fast Clear window refer to Fig 2 9 By writing a 10 bit number N to this register it is possible to set the Fast Clear window width Tec in the range 7 38 5 us 1 32 us steps according to the following relation Tec us N x 7 us where 1 32 ERGO N number of 32 MHz clock cycles Fig 4 25 Fast Clear Window Register Please note that the maximum allowed value for is 3F0 which leads to Tec 38 5 us 4 26 Bit Set 2 Register NPO Base Address 0x1032 read write This register allows to set the operation mode of the module
30. power ON the board follow this procedure 1 insert the V862 board into the crate as the board is inserted the OVC PWR green LED lights up indicating that the board is powered if the TERM LED BUSY LED and DRDY LED are off press the flush plunger PWR micro switch on the front panel by inserting into it a pin as this switch is pressed the TERM LED lights up orange the BUSY LED becomes red and the DRDY LED becomes yellow this indicates that the board is turned on and is configuring if the TERM LED BUSY LED and DRDY LED are on it means that the board is already ON and is configuring the board can be on or off as it is inserted into the crate depending on how it was when it was extracted after a short time the BUSY and DRDY LEDs will light off and the TERM LED will become either red or green or off according to the status of the terminations on the PCB of the board this indicates that the board is ready to acquire data N B if the OVC PWR LED becomes orange instead of being green there is an overload and the over current protection is now running In order to acquire data it is necessary to remove the overload source then turn the board off and switch it on again Sometimes it may happen that the OVC PWR LED is orange as soon as the board is inserted in the crate this is due to the fact that the board has been just misplaced into the crate In this case extract the board and insert it again into the crate 5 4 Powe r
31. readout of the last word in the Output Buffer default 1 The module sends all data to the CPU until the first word end of first event is reached afterwards it will send no valid data If BERR_VME is enabled a Bus Error is generated at the readout of the EOB word Programmable Reset Mode setting bit 0 the front panel RESET acts only on data data reset default 1 the front panel RESET acts on the module software reset N B This bit is cleared only via hardware reset Bus Error enable bit Used in Block Transfer mode only 0 the module sends a DTACK signal until the CPU inquires the module default 1 the module is enabled to generate a Bus error to finish a block transfer Allows to add a 32 bit dummy word marked as not valid datum see 4 5 to an event which is made up of an odd number of words during BLT32 and CBLT32 data readout In fact some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd so it is necessary to add a dummy word which will be then eventually removed via software in order to avoid data loss It is used in BLT32 and CBLT32 and is available in Firmware Rev 6 02 and later 0 no dummy word added default 1 dummy word added when the number of words is odd Bits 7 to 15 are meaningless This register is reset both via software and via hardware reset see 2 8 except for the bit 4 PROG RESET which is reset only vi
32. software Each 16 bit test word see the figure below contains a 12 bit value acting as the ADC converted value and an OV bit which indicates the possible overflow The 32 test data corresponding to the data from the 32 channels must be written in this TEST FIFO in the same order as they are read from the MEB that is e test datum for the channel 0 e test datum for the channel 16 e test datum for the channel 1 e test datum for the channel 30 e test datum for the channel 15 e test datum for the channel 31 For further details on the use of this register in Acquisition Test Mode please refer to 5 6 2 N B please note that the User must write at least and not more than 32 test words Actually since the words are written in a 32 word TEST FIFO if the User writes less than 32 words some words will be not defined on the other hand if the User writes more than 32 words some words will be overwritten TEST ADC CONVERTED VALUE 11 0 Fig 4 31 Test Event Write Register NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 55 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 4 33 Event Counter Reset Register Base Address 0x1040 write only A VME write access to this dummy register clears the Event Counter 4 34 Iped Register Base Address 0x1060 read write only This register allows to
33. that the number of events stored in the memory decreases and becomes less than the value written in the Event Trigger Register Data transfer capability The internal registers are accessible in D16 mode unless otherwise specified Access in D32 BLT32 MBLT64 CBLT32 and CBLT64 is available for the MEB Register address map The Address map for the Model V862 is listed in Table 4 2 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address The Table gives also information about the effects of RESET on the registers In particular column 2 through 4 refer to the following RESET operations D R 2 Data RESET S R gt Software RESET H R 2 Hardware RESET If a register has a mark in these columns it means that the relevant RESET operation resets that register For further details on the RESET Logic please refer to S 2 8 Table 4 3 and 4 4 list register addresses offset in CBLT and MCST operations respectively The ROM address map is reported in Table 4 5 p 58 Table 4 2 Address Map for the Model V862 Register content DR SR Addres Access mode Output Buffer 0 0000 0 07 Read only D32 D64 Firmware Revision 0 1000 Read only Geo Address 0402 Read Write MCST CBLT Address v 0404 BitSet 7 9 9 0406 Read Write Bit ceard
34. when the MEB is not ready to accept data MEB Full or when the board is in Random Memory Access Test mode see 5 6 1 On the occurrence of one of these conditions the front panel BUSY signal CONTROL bus is active the red BUSY LED is on and the bit 2 BUSY and bit 3 GLOBAL BUSY of the Status Register 1 are set to 1 see 4 13 The BUSY LED lights up also while the board is configuring power ON Actually each module sets to 1 its BUSY output after the leading edge of a pulse on the GATE input and releases it to 0 at the end of the conversion sequence When the module is busy it does not accept another GATE pulse The jumper J12 placed on the PCB see Fig 3 4 allows to select board behaviour in response to a BUSY status if this jumper is set to EXTBSY the acquisition is stopped as soon as any of the boards on the Control bus is BUSY if the jumper is set to INTBSY acquisition is stopped as the board is BUSY Reset Logic Three different types of RESET operations can be distinguished according to the effects they have on the module and particularly on the registers These are e TypeA Data RESET e TypeB Software RESET e Hardware RESET The Data RESET clears the data in the output buffer resets the read and write pointers the event counter and the QAC sections It does not affect the registers This type of RESET can be forwarded in two ways 1 setting the 2 CLEAR DATA of the Bit Set 2 Register to
35. whole acquisition system by writing a set of 32 data in an internal FIFO which are then transferred to the output buffer at each COMMON GATE pulse for the readout The test modes will be described in detail in the following subsections Filename Number of pages Page 61 00102 97 862 08 V862_REV8 DOC 69 CAEN Document type User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 NPO Title Revision date Revision 5 6 1 Random Memory Access Test Mode This test mode allows the User to write and read a word in the output buffer To perform such test follow these steps 1 2 Set to 1 the Bit 0 of the Bit Set 2 Register see 4 26 Write into the W Memory Test Address Register see 4 28 the 11 bit address where to write the test word Write the high and low part of the 32 bit test word respectively in the Testword_High and Testword_Low Registers see 4 29 and 4 30 As the Testword_Low register is accessed the whole test word is written into the memory Write in the R Test Address Register see 4 35 the 11 bit reading memory address and read out the buffer please note that this address must be different from the write address written in the W Memory Test Address Register N B please note that the R Memory Test Address must be different from the W Memory Test Address at any step of the procedure If the User tries to write an address in one of these registers that
36. 0 the board is inactive Board status Board position in the chain F_B bit L B bit inactive 0 0 active last 0 1 active first 1 0 active intermediate 1 1 Please note that in a chain there must be one and only one first board i e a board with F_B bit set to 1 and the L_B bit set to 0 and one and only one ast board i e a board with F_B bit set to 0 and the L_B bit set to 1 The complete address in A32 mode is A 31 24 MCST CBLT Address A 23 16 00 A 15 0 offset In MCST CBLT operation it is possible to define more chains in the same crate but each chain must have an address different from the other N B In CBLT operation the data coming from different boards are tagged with the HEADER and with the EOB words containing the GEO address in the 5 MSB see Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 33 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 5 4 5 In the versions without the PAUX connector it is up to the User to write the GEO address in the GEO register this operation is allowed only if the PAUX is not present before executing the CBLT operation If the GEO address is not written in the relevant register before performing the CBLT operation it will not be possible to identify the module which the data are coming from 4 1 5 MCST CBLT addressing e
37. 1 31 2111 0 LEV lt 2 0 gt Fig 4 14 Interrupt Level Register 4 12 Interrupt Vector Register Base Address 0x100C read write This register contains the STATUS ID that the V862 INTERRUPTER places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is 0x00 1511411311211111019 8 7 6 51413 21110 Interrupt STATUS ID Fig 4 15 Interrupt Vector Register 4 13 Status Register 1 Base 0x100E read only This register contains information on the status of the module TERM ON and TERM OFF refer to the terminations of the CONTROL bus lines the last module in a chain controlled via the front panel CONTROL connector must have these terminations ON while all the others must have them OFF The insertion or removal of the terminations is performed via internal DIP switches see Fig 3 4 The BUSY and DATA READY signals are available both for the individually addressed module and as a global readout of a system of many units connected together via the CONTROL bus t5 ha his haa 10 9 8 7 6 5 41 31 21 11 0 DREADY GLOBAL DREADY BUSY GLOBAL BUSY AMNESIA PURGED TERM ON TERM OFF EVRDY Fig 4 16 Status Register 1 Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 44 for Discovery Document type Title Revision date Re
38. ADC 11 0 Fig 4 6 MEB the data word format 22 12 22 4 0 fofo EVENT COUNTER 23 0 NPO 00102 97 862 08 V862_REV8 DOC 69 38 Fig 4 7 MEB the End Of Block Filename Number of pages Page CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 Header content The bits 31 27 contains the GEO address The bits 26 24 identify the type of word 010 header The bits 23 16 identify the crate number according to the content of the Crate Select Register see 5 4 31 The bits 13 8 contain the number of memorised channels Datum content The bits 31 27 contains the GEO address The bits 26 24 identify the type of word 000 datum The bits 21 16 identify the number of the channel which the data are coming from The bit 13 is the UNDERTHRESHOLD bit 0 the datum is over the threshold fixed in the relevant register see S 4 36 1 the datum is under the threshold fixed in the relevant register it is actually possible to make the datum be written in the MEB even if itis under the threshold by using the bits 3 and 4 of the Bit Set 2 Register see S 4 26 The bit 12 is the OVERFLOW bit 0 gt ADC not in overflow condition 1 gt ADC in overflow The bits 11 0 contain the converted datum EOB content The bits 31 27 contains the GEO address The
39. C Charge to Amplitude Conversion section when both the GATE i and COMMON GATE signal are active Input range is 0 400 pC The outputs of the QAC sections are multiplexed and subsequently converted by two fast 12 bit ADCs 5 7 us for 32 channels The ADCs use a sliding scale technique to reduce the differential non linearity The Mod V862 offers a 32 event buffer memory programmable zero suppression and trigger counter complete the features of the unit The module works A24 A32 mode The data transfer occurs D16 D32 BLT32 MBLT64 or CBLT32 CBLT64 mode The unit also supports the Multicast commands The board is available both for standard and V430 VME crates and is equipped with a special circuitry live insertion that allows the User to insert it or remove into or from the crate without switching off Table 1 1 Versions available for the Model V862 Version Number of channels PAUX connector 5 V DC DC converter V862 AA 32 yes no V862 AC 32 no yes NPO 00102 97 V 862x MUTx 08 WV862XACAAAA MAY 9th 2002 Fig 1 1 Model type label example V862 AC RIF N DATE A label on the printed board soldering side indicates the module s version see Fig 1 1 all the versions share the same features except where indicated The version with the PAUX connector requires the V430 backplane 3 Model available exclusively on request Filename Number
40. CBLT address register Default setting i e at power ON or after hardware reset is OxAA Bit Set 1 Register Base Address 0x1006 read write This register allows to set the RESET logic of the module and to enable the change of the base address via VME A write access with the bits to 1 sets the relevant bits to 1 in the register i e writing Ox10 to this register sets the SEL ADDR bit to 1 A write access with the bits set to 0 does Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 42 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 NOT clear the register content in other words when 1 is written into one particular bit such bit is set to 1 if O is written the bit remains unchanged In order to clear the register content the Bit Clear 1 Register must be used see 4 10 A read access returns the status of this register The register content is the following BERR FLAG SEL ADDR SOFT RESET Fig 4 13 Bit Set 1 Register BERR FLAG Bus Error Flag Bit meaningful in BLT CBLT modes only The User may set this flag for test purposes only Its content is cleared both via an hardware and via a software reset 0 board has not generated a Bus Error default 1 board has generated a Bus Error SELECT ADDRESS Select Address bit 0 base address is selected via Rotary Switch
41. IM std input signals high impedance min width 10 ns If this input is used a 50 Q termination is required in daisy chain configuration the termination must be inserted on the last board of the chain GATE COMMON 3 5 1 Displays Function input signal common to all channels acting as the temporal window within which the individually gated inputs are integrated This signal is internally OR wired with the GATE of the CONTROL connector Other front panel components The front panel refer to Fig 3 1 hosts the following LEDs DTACK Filename V862_REV8 DOC 69 Colour green Function DATA ACKNOWLEDGE command it lights up each time a VME access is performed Number of pages Page 24 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 BUSY Colour red Function it lights up each time the module is performing a conversion or resetting the analog section or in memory TEST mode or when the Multi Event Buffer is full it also lights up for a while at power ON to indicate that the board is configuring DRDY Colour yellow Function it lights up when at least one event is present in the output buffer it also lights up for a while at power ON to indicate that the board is configuring TERM Colour orange green red Function it lights up green when all the lines of the control bus are terminated red when no line of the
42. N or after a reset the module must thus be initialised FAST CLEAR The FAST CLEAR of the module can be performed via the relevant front panel signal on the CONTROL connector see 8 3 4 2 A FAST CLEAR signal generated at any time within the FAST CLEAR window i e between the leading edge of the GATE signal and the end of the programmable time value set in the Fast Clear Window Register see 8 4 25 aborts the conversion Its minimum width must be 30 ns N B since a FAST CLEAR operation implies a CLEAR CONVERSION cycle a new GATE signal is accepted only if it occurs at least 600 ns after the leading edge of the FAST CLEAR signal I 7 39us FAST CLEAR window gt Fig 2 9 Fast Clear window Filename Number of pages Page 19 00102 97 862 08 V862_REV8 DOC 69 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 3 Technical specifications 3 1 Packaging The Model V862 is housed in a 6U high 1U wide VME unit The board hosts the VME P1 P2 connectors and depending on the version the PAUX connector The version equipped with the PAUX connector V862 AA requires the VME V430 backplane 3 2 Power requirements The power requirements of the versions available for the V862 module are as follows Table 3 1 Model V862 power requirements Power
43. ON status At power ON the module is in the following status the Event Counter is set to 0 the Output buffer is cleared the Read and Write Pointer are cleared i e Buffer 0 is pointed the Interrupt Level is set to 0 0 in this case interrupt generation is disabled and the Interrupt Vector is set to 0x0 the values in the threshold memory not defined see 5 4 40 the MCST CBLT address is set to OxAA Moreover all other registers marked in the column HR Hardware RESET in Table 4 2 are cleared or set to the default value At power on or after a hardware reset see 5 2 8 the module must thus be initialised 5 5 Operation sequence After the power ON sequence the module is in the status described above NPO Filename Number of pages Page 60 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 for Disco Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 5 6 NPO Please note that the threshold values are not defined after power ON and consequently before starting the operation of the module it is necessary to set a threshold value for each channel in the Threshold memory refer to 4 40 If the module is not BUSY a COMMON GATE input pulse causes the following 1 starts the Charge to Amplitude Conversion of the individually gated inputs 2 increments the event counter according to the User s settings see 2 6 3 sets th
44. Register content Type Output Buffer 0x0000 0x07FF Read only D32 D64 Table 4 4 Address Map in MCST operations BitSet1 0406 Write only 6 Filename Number of pages Page 00102 97 V862x MUTx 08 V862 REV8 DOC 69 37 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 4 5 BitSet2 0x102 Write only 016 Write only SWcomm 0408 0 6 Memory Event Buffer MEB Base Address 0x0000 0x07FC read only This register allows the User to access the Multiple Event Buffer to readout the converted values The MEB contains the output data organised in 32 bit words The data in the MEB are organised in events Each event consists of e the header that contains the geographical address the crate number and the number of converted channels e or more data words each of which contains the geographical address the number of the channel the Under Threshold UN bit the Overflow OV bit and the 12 bit converted value e the End Of Block EOB which contains the geographical address and the event counter GEOJ4 0 CRATE 7 0 0 0 Fig 4 5 the Header 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 GEO 4 0 01010 da UNIOV
45. Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 6 References 1 C Cottini E Gatti V Svelto A new method of analog to digital conversion NIM vol 24 p 241 1963 2 C Cottini E Gatti V Svelto A sliding scale analog to digital converter for pulse height analisys in Proc Int Symp Nuclear Paris Nov 1963 3 G Bianchetti et al Specification for VMEbus CRATE Type V430 CERN EP January 1990 4 VME64 extensions draft standard Vita 1 1 199x draft 1 8 June 13 1997 5 VMEBus for Physics Application Recommendations amp Guidelines Vita23 199x draft 1 0 22 May 1997 Both documents are available from URL http www vita com NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 66 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 APPENDIX A VME interface timing NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 67 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 VME Cycle timing D16 D32 mode The figure below reports the Data Select DSO DS1 Data Acknowledge VME cycle D16 mode and relative timing The theoretical minimum duration of the VME cycle in D16 D32 mode is 120 60 ns
46. TS 5555 20 1 55 60 21 3 4 EXTERNAL 8 22 3 4 1 22 3 4 2 CONTROE 5 eire ue oou 23 3 4 3 GATE COMMON connectors a 24 3 5 OTHER FRONT PANEL COMPONENTS 000 0 00 0 000 0 24 3 5 1 DISPLAYS D 24 3 5 2 NITET 25 3 6 INTERNAL HARDWARE COMPONENTS 0 2000 25 3 6 2 NIIT cM 25 IOI 26 3 6 4 Solde rino 28 3 7 TECHNICAL SPECIFICATIONS TABLE 29 4 VME INTERFACE 30 4 1 ADDRESSING CAPABILITY 30 4 1 1 Addressi
47. Table 4 1 Table 4 1 Module recognised Address Modifier A M Description 24 supervisory block transfer BLT Ox3D A24 supervisory data access 0 3 24 supervisory 64 bit block transfer MBLT 0x3B A24 non privileged block transfer BLT 0x39 A24 non privileged User data access 0x38 A24 non privileged 64 bit block transfer MBLT Ox2F Configuration Rom Control amp Status Register CR CSR A32 supervisory block transfer BLT 0x0D A32 supervisory data access 0 0 A32 supervisory 64 bit block transfer MBLT 0x0B A32 non privileged block transfer BLT 0x09 A32 non privileged data access 0x08 A32 non privileged 64 bit block transfer MBLT The Base Address can be selected in the range 0x000000 0 0000 24 0x00000000 gt 0OXxFFFF0000 A32 mode The Base Address of the module can be fixed in two ways e by four rotary switches by writing the Base Address in the ADER HIGH and ADER LOW registers The 4 rotary switches for Base Address selection are housed on two piggy back boards plugged into the main printed circuit board see Fig 3 4 NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 30 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 To use this addressing mode the bit 4 of the Bit Set 1 Register se
48. Technical Information Manual Revision n 8 4 November 2009 MOD V862 series 32 CHANNEL INDIVIDUAL GATE QDCs NPO 00102 97 V862x MUTx 08 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 TABLE OF CONTENTS L 6 5 8 14 E 8 1 2 JBLEOCKDIAGRAM ete e ve 9 2 PRINCIPLES OF OPERATION ves ceecus cess oes esae
49. This is obtained by using a gate of fixed width 100ns and reading the digital ADC value with the input signal disconnected therefore only is integrated The integration capacitance is 100 pF the QAC output is 1mV per count Table 2 1 shows that below 55 DAC counts the channel is decoupled and provides no output Our advice is not to set the Register see 5 4 34 below 60 counts in order to guarantee the channels to be coupled anyway if the User wishes to have the channels coupled precisely with the minimum possible then it is necessary to set the Register between 50 and 60 DAC counts and to increase the gate in order to check that Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 12 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 the readout counts grows as the gate grows if this does not happen then Iped Register must be increased Table 2 1 Iped values Dac Measure Measure offset gate Iped count count count pA 0 53 24 10 53 21 20 53 20 30 53 21 40 53 22 50 53 19 55 53 61 60 55 13 65 56 96 70 58 98 75 60 96 80 63 03 90 67 12 100 71 23 115 77 45 130 83 77 145 90 02 160 96 26 175 102 53 190
50. a hardware reset NPO 00102 97 V862x MUTx 08 Filename Number of pages Page V862_REV8 DOC 69 46 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 4 15 Address Decoder High Register Base Address 0x1012 read write This register contains the A31 A24 bits of the address of the module it can be set via VME for a relocation of the Base Address of the module The register content is the following N 15h14 10 9 8 6 151413121110 31 24 Fig 4 18 ADER HIGH Register 4 16 Address Decoder Low Register Base Address 0x1014 read write This register contains the A23 A16 bits of the address of the module it can be set via VME for a relocation of the Base Address of the module The register content is the following 1514 10 9 8 6 51413121110 A 23 16 Fig 4 19 ADER LOW Register 4 17 Single Shot Reset Register Base Address 0x1016 write only A write access to this dummy register performs a module reset This register must be used very carefully and for debugging purposes only In order to reset the board it is recommended to use the Bit Set 1 Register see 4 9 4 18 MCST CBLT Control Register Base Address 0x101A write only This register allows performing some general MCST CBLT settings
51. ate QDC 04 11 2009 8 4 22 This register is reset via the Event Counter Reset Register see S 4 33 or via a software or hardware reset see 8 2 8 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a data reset see S 2 8 Event Counter High Register Base 0x1026 read only It contains the 8 MSB of the 24 bit event counter The event counter can work in two different ways see also S 2 6 1 it counts all events 2 itcounts only the accepted events The two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 8 4 26 EVENT CNT HIGH 8 MSB of the 24 bit Event Counter 5 Fig 4 24 Event Counter High Register This register is reset via the Event Counter Reset Register see 4 33 or via a software or hardware reset see 2 8 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a data reset see 2 8 4 23 Increment Event Register Base Address 0x1028 write only A write access to this dummy register sets the readout pointer on the next event in the MEB at the first address In particular if the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 4 26 the readout pointer is no more automatically incremented but it can be incremented via a write access to this register
52. bits 26 24 identify the type of word 100 gt The bits 23 0 contain the 24 bit event counter value see 4 21 The bits 31 27 always contains the GEO address except for the not valid datum see Fig 4 8 The bits 26 24 identify the type of word according to the following e 010 gt header e 000 gt valid datum e 100 gt end of block e 110 gt not valid datum e others gt reserved If a read access is performed to the MEB when it is empty the readout will provide a NOT VALID DATUM arranged as shown in Fig 4 8 NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 39 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 Fig 4 8 not valid datum The sequence followed to store the data in the MEB is as follows CHANNEL 0 CHANNEL 16 CHANNEL 1 CHANNEL 17 CHANNEL 2 CHANNEL 15 CHANNEL 31 Please note that some of the above channel data may be missing in the sequence this is due either to overflow or under threshold conditions which caused these data not to be stored or to User s settings to kill some channels Fig 4 9 shows an example of the Multi Event Buffer structure in case of zero suppression enabled and with event counter set so as to count all events see 2 6 The first event written in the active Event Buf
53. d values in 16 ADC counts steps over the entire full scale range or in 2 ADC counts steps over 1 8 of full scale range In more detail if Bit 8 0 default value the comparison is performed between the 8 MSB of each 12 bit converted value and the 8 bit threshold value which is stored in the relevant register as illustrated in Fig 2 5 The threshold values can be programmed over the entire full scale range ADC converted value from the channel n Threshold value for the channel n Fig 2 6 Zero suppression Bit 8 of Bit Set 2 Register 0 default setting if Bit 8 1 in the Bit Set 2 Register the comparison is performed between the bit 1 8 of each 12 bit converted value and the 8 bit threshold value which is stored in the relevant register as illustrated in the figure below converted value is under threshold if the value written in the 1 8 bits is smaller than the threshold value and 9 11 bits are 0 The threshold values can be programmed over 1 8 of full scale range ADC converted value from the channel n Threshold value for the channel n Fig 2 7 Zero suppression Bit 8 of Bit Set 2 Register 1 The comparison is resumed in the following table Bit 8 of Bit Set 2 Register Comparison 1 ADC CONVERTED VALUE lt THRESHOLD VALUE x 2 0 ADC CONVERTED VALUE lt THRESHOLD VALUE x 16 Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 15 CAEN Document type
54. default 1 base address is selected via internal ADER registers SOFTW RESET Sets the module to a permanent RESET status The RESET is released only via write access with the relevant bit set to 1 in the Bit Clear Register see 4 10 This register is reset via a hardware reset see S 2 8 Only the bit 3 BERR FLAG is reset both via hardware reset and software reset 4 10 Bit Clear 1 Register Base Address 0x1008 read write This register allows to clear the bits in the above described Bit Set 1 Register A write access with a bit set to 1 resets that bit e g writing 0x8 to this register resets the BERR FLAG bit A write access with the bits set to 0 does NOT clear the register content other words when 1 is written into one particular bit such bit is set to 0 cleared if O is written the bit remains unchanged The structure of the register is identical to the Bit Set 1 Register A read access returns the status of the register 4 11 Interrupt Level Register Base Address 0x100A read write The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is OxO In this case interrupt generation is disabled NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 43 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 15 14 13 12 11 10 9 8 7 6 51 4
55. e Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 4 37 Slide constant Register Base Address 0x106A read write Fig 4 34 Slide Constant Register This register contains a 8 bit value corresponding to the constant to which is set the sliding scale DAC when the sliding scale is disabled by means of the SLD_ENABLE bit of the Bit Set 2 Register refer to 4 26 4 38 AAD Register Base Address 0x1070 read only This register contains the value converted by the ADC of the Block A refer to the block diagram of Fig 1 2 BLOCK CONVERTED VALUE 11 0 Fig 4 35 AAD Register 4 39 BAD Register Base Address 0x1072 read only This register contains the value converted by the ADC of the Block B Refer to the block diagram of Fig 1 2 EQ BLOCK B CONVERTED VALUE 11 0 Fig 4 36 BAD Register 4 40 Thresholds Memory Base Address 0x1080 Ox10BE read write This register contains the low threshold and kill option for each channel The address is different for each channel chO gt 0 1080 ch1 gt 0x1082 ch30 gt 0 10 ch31 gt Ox10BE Each threshold is as shown in the figure NPO Filename 00102 97 V862x MUTx 08 Number of pages Page V862 REV8 DOC 69 57 Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate
56. e 4 9 must be set to 0 This is also the default setting The module Base Address can be also fixed by using the Ader_High and Ader_Low Registers These two registers set respectively the A 31 24 and the A 23 16 VME address bits see 4 15 and 4 16 To use this addressing mode bit 4 of the Bit Set 1 Register see 4 9 must be set to 1 4 1 2 Addressing via GEOgraphical address The module works in A24 mode only The Address Modifiers codes recognised by the module are AM 0x2F A24 GEO access All registers except for the MEB i e the CR CSR area can be accessed via geographical addressing The geographical address is automatically read out at each RESET from the SN5 SN1 lines of the PAUX connector Each slot of the VME crate is identified by the status of the SN5 SN1 lines for example the slot 5 will have these lines respectively at 00101 and consequently the module inserted in the slot 5 will have a GEO address set to 00101 see Fig 4 1 The complete address in A24 mode for geographical addressing is A 31 24 don t care A 23 19 GEO A 18 16 0 15 0 offset The following two figures show the binary and the hexadecimal representation of respectively the board Address and a Register Address Bit Set 1 Register in GEO addressing mode Binary representation Hexadecimal representation 9 6 817 0 0 o 010 Bi
57. e is suggested only if the VME CPU can handle the Bus Error BERR in an effective way N B Please note that according to the VME standard a Block Transfer readout can be performed with 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more BLT operations This limit is not due to the board itself but only to the VME standard if it is possible to disable or delay the timeout of the BUS Timer BTO x a Block Transfer readout with more than 256 read cycles can be performed as well 5 8 Advanced Setting and Readout Modes NPO Chained Block Transfer CBLT and Multicast MCST operations allow to enhance the set and readout time of the 32 channels These operations allow accessing several boards at the same time CBLT operations are used for reading cycles only while MCST operations are used for write cycles only For further details on the CBLT MCST addressing mode please refer to 5 4 1 4 and 5 4 1 5 In order to perform CBLT and MCST operations the higher Base Address bits of all the involved modules i e bits 31 to 24 must be set in common to all boards via the MCST CBLT Address Register see S 4 8 This means that all boards must have the same setting on bits 31 to 24 The resulting MCST CBLT Base Address for all boards is MCST CBLT Base Address 000000 Once the addresses have been set the first and last board in a chain must have respectively only the FIRST
58. e BUSY output signal to 1 If neither RESET nor FAST CLEAR occur refer to 2 8and 2 9 to abort the Charge to Amplitude Conversion the control logic starts the following conversion sequence 1 The outputs of the QAC sections are multiplexed and sampled 2 The control logic checks if there are accepted data among the converted values according to the User s settings zero suppression overflow suppression and KILL option see 2 3 and 2 4 a if there are accepted data these are stored in the active event buffer together with a Header and an EOB b if there are no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 0 default setting see 4 26 no data will be written in the output buffer if there are no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 1 see 4 26 the Header and EOB only will be written in the output buffer 3 If the MEB is not full the QAC sections and the BUSY are cleared and the module is ready for the next acquisition if the MEB is full the module doesn t accept any COMMON GATE and BUSY is not cleared Test Modes Two different test modes can be enabled e Random Memory Access Test Mode e Acquisition Test Mode The first test mode operation is enabled via the Bit 0 of the Bit Set 2 Register and allows to write directly into the buffer The second test mode is enabled via the Bit 6 of the Bit Set 2 Register and allows to test the
59. e EOB relative to the event see EMPTY PROG bit of the Bit Set 2 Register see 4 26 in this case the event is constituted by 2 32 bit words only 2 6 Event Counter The module houses a 24 bit counter that counts the number of GATE signals that the module has received The Event Counter can work in two different modes which can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 4 26 Mode A ALL TRG 1 it counts all events default Mode B ALL TRG 0 it counts only the accepted events NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 17 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 2 7 2 8 In the first case Mode the Event Counter is increased each time a pulse is sent through the GATE input In the second case Mode B the Event Counter is increased each time a pulse sent through the GATE input is accepted i e VETO FCLR and BUSY are not active The value of the Event Counter is stored in the EOB of the Multi Event Buffer see 4 5 The Event Counter is also stored in two registers the Event Counter_Low and Event Counter_High Registers which respectively contain the 16LSBs and the 8MSBs of the Event Counter see 4 21 and 4 22 Busy Logic The board is BUSY either during the conversion sequence or during the reset of the analog section or
60. e QDC 04 11 2009 8 Example of Access via Base Address vme write 0xEE001004 A32 D16 set MCST Address 0xAA for board 1 vme_write 0xCC111004 OxAA A32 D16 set MCST Address 0xAA for board 2 vme_write 0xBC341004 OxAA A32 D16 set MCST Address 0xAA for board 3 vme_write 0xDD711004 OxAA A32 D16 set MCST Address 0xAA for board 4 vme write 0 00101 0x02 A32 D16 set board 1 First write 0 11101 0x03 A32 D16 set board 2 Active vme write 0xBC34101A 0x00 A32 D16 set board 3 Inactive write 0 71101 0x01 A32 D16 set board 4 Last vme write 0 001006 0x80 A32 D16 perform a RESET on all the boards Example of Access via geographical address vme write 0x181004 OxAA GEO D16 set MCST Address 0xAA for board 1 vme write 0x301004 OxAA GEO D16 set MCST Address 0xAA for board 2 vme write 0x481004 OxAA GEO D16 set MCST Address 0xAA for board 3 vme write 0x511004 GEO D16 set MCST Address 0xAA for board 4 vme write 0x18101A 0x02 GEO D16 set board 1 First vme write 0x30101A 0x03 GEO D16 set board 2 Active vme write 0x48101A 0x00 GEO D16 set board 3 Inactive write 0x51101A 0x01 GEO D16 set board 4 Last vme write 0 001006 0x80 A32 D16 perform a RESET on all the boards N B there must be always o
61. ecifications diff ECL input signal active high high impedance Function temporal window common to all channels within which the individually gated inputs are accepted Electrical specifications diff ECL input signal active high high impedance Function inhibits the conversion of the QAC signals Electrical specifications ECL input output signal high impedance Function indicates that the board is either converting or resetting or in MEMORY TEST mode or the MEB is full BUSY status is also flagged by the bit 2 of the Status Register 1 when several boards are daisy chained the wired OR and wired NAND of BUSY signals can be read respectively on the BUSY and BUSY lines of the CONTROL bus and the status of the BUSY bidirectional line is flagged by the bit 3 of the Status Register 1 see S 4 13 Number of pages Page V862 REV8 DOC 69 23 CAEN Document type User s Manual MUT 3 5 NPO 00102 97 V862x MUTx 08 Title Mod 862 32 channel Individual Gate Revision date Revision 04 11 2009 8 FCLR FCLR RST A RST DRDY DRDY COM not used COM not used Tug VETO ur BUSY BUSY not connected Fig 3 3 CONTROL connector pin assignment 3 4 3 GATE COMMON connectors Mechanical specifications two bridged 00 type LEMO connectors Electrical specifications N
62. er 0 default indicates that the number in the Event Trigger Register see S 4 19 is smaller than the number of events stored in the memory 1 indicates that the number in the Event Trigger Register see 8 4 19 is greater than or equal to the number of events stored in the memory and an interrupt request has been generated with interrupt level different from 0 see S 4 2 3 N B the condition in which both TERM ON and TERM OFF bits are equal to 0 indicates an uncommon termination status e g some terminations on and other are off NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 45 CAEN Document type User s Manual MUT Title Revision date Revision Mod 862 32 channel Individual Gate 04 11 2009 8 4 14 Control Register 1 Base Address 01010 read write This register allows performing some module s general settings 15 14 13 1211111019 18 7 6 5 4 3 2 1 0 BERR ENABLE ALIGN 64 BLKEND PROG RESET BERR ENABLE ALIGN64 Fig 4 17 Control Register 1 End of Block bit Used in Block Transfer modes only 0 The module sends all requested data to the CPU when the Output Buffer is empty it will send no valid data If BERR_VME is enabled see bit 5 below BERR ENABLE a Bus Error is generated with the
63. ess used for MCST and CBLT operations is the same i e throughout this User s Manual the MCST Base Address identifies the same Address used both for MCST commands in Write only and the CBLT Readout in Read only for the MEB only The MCST Base Address must be set in a different way from the ordinary Base Address Its most significant byte i e bits 31 through 24 must be written in the MCST CBLT Address Register see 4 8 and must be set in common to all boards belonging to the MCST CBLT chain i e all boards must have the same setting of the MCST CBLT Base Address on bits 31 through 24 The default setting is OxAA In CBLT and MCST operations the IACKIN IACKOUT daisy chain is used to pass a token from a board to the following one The board which has received the token stores sends the data from to the master via CBLT MCST access No empty slots must thus be left between the boards or in alternative empty slots can be left only in case VME crates with automatic IACKIN IACKOUT short circuiting are used Once the addresses have been set the first and last board in a chain must have respectively only the FIRST BOARD F B and only the LAST BOARD L B bit set to 1 in the MCST Control Register see S 4 18 On the contrary all intermediate boards must have both the FIRST BOARD and the LAST BOARD bits set to 1 active intermediate or both the FIRST BOARD and the LAST BOARD bits set to 0 inactive By default these bits are set to
64. fer Write pointer n is that relative to the GATE n 5 during which two channels 2 and 5 were over the programmed threshold the stored event is constituted by a Header the data relative to the two channels and the End of Block word at the end of all converted data of the relevant Event During GATE n 6 and n 7 no channels were in the selected range The next event written in the following active Event Buffer Write pointer n 1 is that relative to the GATE n 8 it consists of the Header the data relative to three channels 0 17 and 3 and the End of Block word at the end of all converted data fe O Write Pointer 010 CHANNEL 2 ADC COUNTS N GEO EVENT COUNTER m Write ADC COUNTS Pointer N 1 ADC COUNTS GATE 8 ADC COUNTS EVENT COUNTER 143 Fig 4 9 Multi Event Buffer data structure example NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 40 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 N B in the versions which do not have the PAUX connector the GEO address must be written by the User via a write access to the relevant register see 4 6 If this operation is not performed it will be not possible to identify which module the data are coming from when the CBLT access is used 4 6 Firmware Revision Register Base Address 0x1000
65. h 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more CBLT operations This limit is not due to the board itself but only to the VME standard it is actually possible to performed a CBLT readout with more than 256 read cycles if the timeout of the BUS Timer BTO x is disabled or delayed If the latter action is not allowed and the CBLT readout stops before having read all data the new CBLT cycle will start from where the token was left in the previous cycle this goes on until the last board is reached and all data read so that a BERR is generated 5 8 2 Multicast Commands Once set the address of the boards as described 8 5 8 the boards can be accessed in Multicast Commands MCST mode The MCST mode allows to write in the registers of several boards at the same time by accessing a dummy Address only once The latter is composed by the MCST Base Address plus the offset of the relevant register according to the list shown 5 4 4 Refer to 5 4 1 4 for details on MCST addressing mode MCST access can be meaningless even if possible for the setting parameters depending on the individual channel characteristics N B the MCST CBLT Address Register must NEVER be accessed in MCST mode since this can affect the CBLT and MCST operations themselves Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 65 CAEN Document type Title Revision date
66. hannel Individual Gate QDC 04 11 2009 8 NPO 2 1 1 The input current to current converter The input current to current converter negative inputs is shown in Fig 2 3 it uses a differential amplifier and a bipolar transistor thus creating a virtual ground at the negative input terminal A minimum bias current is required to flow through the transistor T1 in order to e Ensure 1 to operate in the linear region even for small input signals e Linearly process small positive input currents This bias current is provided by the Ip 500 pA and l VME programmable current generators see figure below MN CLEAR COMMON 502 GATE to a OUTPUT to multiplexer INPUT SIGNAL In T 500 eem PROGRAMMABLE CURRENT h GENERATOR v Fig 2 3 Input stage simplified model 2 1 2 Pedestal The QDC pedestal is the value readout when no input signal is present open inputs It is mainly due to the lp current see 4 34 integrated by the capacitor C when a GATE signal is applied It is worth noting that the QDC pedestal does not depend linearly on GATE width as shown in 2 1 2 1 When the maximum dynamic range is needed it is possible to program so that Ip is close to zero see also 6 4 34 for further details 2 1 2 1 Pedestal current setting The following trace reports the graph of the Iped current in pA as a function of the IPED Register setting
67. hold value see 4 40 1 the comparison is performed between the bit 1 8 of each 12 bit converted value and the 8 bit threshold value AUTO INCR Allows to enable disable the automatic increment of the readout pointer 0 the read pointer is not incremented automatically but only by a write access to the Increment Event or Increment Offset Registers see 4 23 and 4 24 1 the read pointer is incremented automatically default EMPTY PROG Allows to choose if writing the header and EOB when there are no accepted channels 0 when there are no accepted channels nothing is written in the MEB default 1 when there accepted channels the Header and the EOB are anyway written in the MEB SLIDE_SUB ENABLE Allows to change operation mode for the sliding scale 0 the sliding scale works normally default 1 the subtraction section of the sliding scale is disabled test purposes only ALL TRG Allows to choose how to increment the event counter 0 event counter incremented only on accepted triggers 1 event counter incremented on all triggers default 4 27 Bit Clear 2 Register Base Address 0x1034 write only This register allows clearing the bits of the Bit Set 2 Register 4 26 A write access with a bit set to 1 resets that bit e g writing 0 4 to this register resets the CLEAR DATA bit A write access with the bits set to 0 does NOT clear the register content The structure of the register is iden
68. ince the words are written in a circular FIFO if the Filename Number of pages Page 62 00102 97 V862x MUTx 08 V862_REV8 DOC 69 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 User writes less than 32 words some words will be not defined on the other hand if the User writes more than 32 words some words will be overwritten 4 Set to 1 the Bit6 TEST ACQ of the Bit Set 2 Register see 4 26 this action resets again the write pointer in the FIFO and releases the read pointer 5 Send a set of COMMON GATE input signals at each COMMON GATE signal the data previously written in the FIFO will be transferred to the output buffer The data will be read via VME in the same order as they were written into the FIFO test data word for the channel 0 test data word for the channel 16 test data word for the channel 1 test data word for the channel 30 test data word for the channel 15 test data word for the channel 31 N B To operate in normal mode again the Bit 6 of the Bit Set 2 Register must be set again to 0 5 7 Block Transfer Mode The module supports the Standard BLT32 and MBLT64 modes A standard readout in Block Transfer mode for example consists of a readout of the Header for the relevant event and a Block Transfer readout of the number of data words relative to the event the number of data words referring t
69. is equal to the address contained in the other register write cycles step 3 above will not write the correct value 5 6 2 Acquisition Test Mode This test mode allows the User to simulate the real operation of the board without using any channel input signals but just writing the data into a FIFO via an appropriate register Test Event Write Register see 4 32 and reading them after a COMMON GATE signal To operate the acquisition test follow these steps 1 Set to 1 the 6 TEST of the Set 2 Register see 4 26 this action selects the Acquisition Test Mode and resets the write pointer in the FIFO Set to 0 the Bit6 TEST of the Bit Set 2 Register see 5 4 26 this action resets the read pointer in the FIFO and releases the write pointer Write 32 data words each word consisting of a 13 bit word corresponding to the ADC converted value the overflow bit see 5 4 32 in the Test Event Write Register Base Address 0x103E These 32 data constitute the event to obtain as output of the 32 channels The 32 test data must be written in this FIFO in the same order as they will be read from the output buffer that is e test datum for the channel 0 e test datum for the channel 16 e test datum for the channel 1 e test datum for the channel 30 e test datum for the channel 15 e test datum for the channel 31 N B please note that the User must write at least and not more than 32 test words Actually s
70. lugged into the main board NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 48 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 1511411311211111019 8 BUFFER EMPTY BUFFER FULL RESERVED DSELO DSEL1 CSELO CSEL1 Fig 4 22 Status Register 2 BUFFER EMPTY Indicates if the MEB is empty 0 buffer not empty 1 buffer empty BUFFER FULL Indicates if the MEB is full 0 buffer not full 1 buffer full CSEL1 CSELO DSEL1 DSELO Indicate the type of piggy back plugged into the board In the case of the version V862AA and AC the value is 0010 32 channel QDC 4 21 Event Counter_Low Register Base Address 0x1024 read only It contains the 16 LSBs of the event counter The event counter can work in two different ways see also 2 6 1 it counts all events 2 itcounts only the accepted events The two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 8 4 26 EVENT CNT LOW 16 LSB of the 24 bit Event Counter 918176 5 4 3 2 1 9 Event Counter Low Fig 4 23 Event Counter Low Register NPO Filename Number of pages 00102 97 V862x MUTx 08 V862_REV8 DOC 69 Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual G
71. nary representation 1006 offset Hexadecimal representation Fig 4 2 Binary Hexadecimal representation of Bit Set 1 Register Address in GEO mode NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 31 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 NPO N B In the case of versions where the SN5 SN1 lines are not available i e the versions without the PAUX connector addressing via geographical address is not possible Although in these versions it is possible to perform a write access to the GEO Register see S 4 6 for data identification during CBLT operation see S 4 1 4 it is incorrect to use the GEO Register for addressing purposes when there is no PAUX 4 1 3 Base GEO addressing examples The following is an example of Base GEO Addressing for two V862 boards inserted in a VME crate BOARD1 BOARD2 Upper Rotary Switches Lower bytes of Address 00 11 Lower Rotary Switches Slots Lo 9 bytes in the crate of Address EE 20121 Ko 21314 5 e 8 2 8 papse ne Fig 4 3 Addressing Example 1 If the board 1 and board 2 respectively inserted in the slots 5 and 8 with the rotary switches for VME Base Addressing set as sho
72. ne and only one FIRST BOARD and one and only one LAST BOARD 4 2 Interrupter capability The Mod V862 features a VME INTERRUPTER The INTERRUPTER responds to 8 bit 16 bit and 32 bit Interrupt Acknowledge cycles by providing an 8 bit STATUS ID on the VME data lines 000 007 4 2 1 Interrupt Status ID The interrupt STATUS ID is 8 bit wide and it is contained in the 8LSB of the Interrupt Vector Register see 5 4 12 The register is available at the VME address Base Address 0x100C 4 2 2 Interrupt Level The interrupt level corresponds to the value stored in the 3LSB of the Interrupt Level Register see 5 4 11 The register is available at the VME address Base Address 0 100 If the 3LSB of this register are set to 0 the Interrupt generation is disabled NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 35 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 4 2 3 Interrupt Generation An Interrupt is generated when the number of events stored in the memory equals the value written the Event Trigger Register at the VME address Base Address 0x1020 see S 4 19 If the value in Event Trigger Register is set to O the interrupt is disabled default setting 4 2 4 Interrupt Request Release 4 3 4 4 The INTERRUPTER removes its Interrupt request when a Read Access is performed to the MEB so
73. ng via Base Address 30 NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 3 for Discovery Document type Title User s Manual MUT Mod V862 32 channel Individual Gate QDC 4 1 2 Addressing via GEOgraphical address 4 1 3 Base GEO addressing examples 4 1 4 MCST CBLT addressing 4 1 5 MCST CBLT addressing examples 4 2 INTERRUPTER 4 2 1 Interrupt Status ID eese 4 2 2 Interrupt Level eese 4 2 3 Interrupt Generation eese 4 2 4 Interrupt Request Release sess 4 3 TRANSFER CAPABILITY eene 4 4 REGISTER ADDRESS 4 5 MEMORY EVENT BUFFER MEB 4 6 FIRMWARE REVISION REGISTER 47 GEO ADDRESS REGISTER eere 4 8 MCST CBLT ADDRESS 49 BIT SET 1 5 4 4 022424 4 10 BIT CLEAR 1 REGISTER eere 4 11 INTERRUPT LEVEL REGISTER eene 4 12 INTERRUPT VECTOR REGISTER 4 13 STATUS REGISTER 1 ertet restet 4 14 CONTROL REGISTER 4 15 ADDRESS DECODER HIGH REGISTER 4 16 ADDRESS DECODER LOW REGISTER 4 17 SINGLE SHOT RESET REGISTER
74. nstallation and operation of the module Read thoroughly this section before starting any procedure of installation or operation of the product Product Damage Precautions Use Proper Power Source Do not operate this product from a power source that applies more than the voltage specified Provide Proper Ventilation To prevent product overheating provide proper ventilation Do Not Operate With Suspected Failures If you suspect there is damage to this product have it inspected by qualified service personnel 5 2 Installation The V862 board must be inserted in a V430 VME 6U crate if the purchased version is equipped with a PAUX connector If the version does not have the PAUX connector it can be inserted into a standard VME 6U crate Refer to Table 1 1 for details on the various versions Please note that all versions of the board support live insertion extraction into from the crate i e it is possible to insert or extract them from the crate without turning the crate off Moreover it is possible to switch the board off by the relevant PWR switch see 3 5 2 without cutting the interrupt chain off ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 59 CAEN Document type User s Manual MUT Title Revision date Revision Mod 862 32 channel Individual Gate QDC 04 11 2009 8 5 3 Power ON sequence To
75. o the event is the CNT number in the Header see 4 5 A more efficient readout in Block Transfer mode can be performed by using the BLOCK END and BERR ENABLE bits of the Control Register 1 see 4 14 Some examples of this type of readout in Block Transfer mode are as follows Example A Example B Example C Example D NPO 00102 97 V862x MUTx 08 BLOCK END 0 BERR_ENABLE 0 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all data stored in the buffer as the buffer is empty the module will send only not valid data BLOCK END 0 BERR_ENABLE 1 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all events stored in the buffer as the buffer is empty a BERR is generated BLOCK END 1 BERR_ENABLE 0 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event after the readout of the EOB the module will send only not valid data BLOCK END 1 BERR_ENABLE 1 Filename Number of pages Page V862_REV8 DOC 69 63 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event as the EOB is encountered a BERR is generated The use of the BERR ENABLE bit Examples B and D abov
76. of pages Page V862 REV8 DOC 69 8 ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 1 2 Block diagram Piggy back board GATES QAC 0 SATE 1 8262 BLOCK A Lay GATE 3j 3 12 bit ADC 12 amp sliding ove scale IN 12 GATE 12 3 QAC 12 IN 13 13 QAC 13 MUX wap 4 1 14 14 i ie 7 THRESHOLD gt QAC 15 COMPARATOR GATE 15 IN 16 GATE 1 16 vem b 17 GATE 1 i QAC 18 BLOCK B GATE 1 2 1 12 bit ADC 12 GATE 1 19 amp sliding OVR scale ss 28 29
77. ose the switches SW1 and SW2 thus allowing the input current to flow through an integrator The integrator output is amplified and fed to the multiplexer As the SW1 and SW2 are open again the signal is digitised by the 12 bit ADCs After digitisation the SW3 switch is closed clearing the charge integrated into the capacitor C The signal conversion timing is shown in Fig 2 2 DT aes SW3 CLEAR 4 QAC OUT to multiplexer SW2 i SWI COMMON GATE CURRENT VIRTUAL CURRENT GROUND 500 CONVERTER Rin VAW a a 5 Fig 2 1 Simplified block diagram of the section Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 10 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 i th INPUT 2 i th GATE n COMMON GATE A i th QAC OUTPUT CLEAR BUSY WRITE x94 7 MEM WE DRDY CONVERSION LOGIC STATE Q settling digitiza time tion 160 le 600 ns gt lt 6 us lt 600 ns Fig 2 2 Signal conversion timing NPO Filename Number of pages Page 00102 97 862 08 V862_REV8 DOC 69 11 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 c
78. program on 8 bits the current for all channels to set the channel s pedestal It is worth noting that the channel s pedestal linearly depends on gate width The following relation holds for the pedestal current see 2 1 2 Ip l4 lo where lo 500 uA and is VME programmable via the register the 1 current can be programmed up to roughly 583 uA corresponding to PEDESTAL 255 The default value is PEDESTAL 180 For correct operation the User should pay attention to set 42 10 it is recommended to program PEDESTAL gt 60 For example PEDESTAL 180 corresponds to 1 551 uA typ and thus 51 if the gate width is 200 ns this Ip current gives a QDC pedestal of approximately 160 counts or 0 8 counts ns Iped 7 0 Fig 4 32 Iped Register 4 35 R Memory Test Address Register Base Address 0x1064 write only This register contains the address of the MEB from which data can be read for the memory test R TEST ADDRESS 10 0 Fig 4 33 R Memory Test Address Register N B The MEB is a FIFO so the read address R Test Address Register must be different from the write address W Test Address Register 4 36 SW Comm Register Base Address 0x1068 write only A write access to this dummy register causes a conversion for test purposes NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 56 CAEN Document type Titl
79. read only This register contains a 16 bit value identifying the firmware revision The 16 bit value corresponds to 4 hexadecimal figures which give the firmware revision number For example in the figure is shown the register content for the firmware release Rev 01 03 Binary representation Hexadecimal representation Fig 4 10 Firmware Revision Register 4 7 GEO Address Register Base Address 0x1002 read write write cycles are allowed only for the version without PAUX connector This register contains the geographical address of the module i e the slot number picked up from the JAUX connector on the VME backplane The register is filled up upon arrival of a RESET The register content is the following JEU GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 4 11 Geographical address register GEO 4 0 corresponds to A23 A19 in the address space of the CR CSR area each slot has a relevant number whose binary encoding consists of the GEO ADDR 4 to 0 NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 41 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 4 8 4 9 NPO In the versions without the PAUX connector this register can be also written see also AMNESIA bit in the Status Register 1 refer to 5 4 13 The bits of the GEO Address register are
80. se address bit lt 23 20 gt Base address bit lt 27 24 gt Base address bit lt 31 28 gt DIP switches for BUS termination insertion TERM ON COM not used COM not used VETO FCLR RST IRST BUSY BUSY DRDY DRDY NPO Filename V862_REV8 DOC 00102 97 V862x MUTx 08 Right position dot visible termination ON Left position dot not visible termination OFF Jumper for BUSY mode selection J12 7 412 5 Position EXTBSY acquisition is stopped as any board on the Bus is BUSY Position B INTBSY acquisition is stopped as the board is BUSY Fig 3 4 Component Location component side Number of pages Page 69 27 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 3 6 4 Soldering pads S9 VEE Function it allows to connect the second pin of the CONTROL connector to the VEE power supply 5 V No Soldering default the pin 2 of the CONTROL connector is not connected Soldering the pin 2 of the CONTROL connector is connected to VEE power supply 5 V 10 GND Function it allows to connect the first pin of the CONTROL connector to the DIGITAL GROUND No Soldering default the pin 1 of the CONTROL connector is not connected Soldering the pin 1 of the CONTROL connector is connected to the digital ground
81. set to 1 by default In CBLT operation it is up to the User to write the correct GEO address of the module in this register before operating so that the GEO address will be contained in the HEADER and the EOB words for data identification If a write access to the GEO register is performed in the versions with the PAUX connector the module does not respond and the bus will go in timeout N B In the case of versions where the SN5 SN1 lines are not available i e the versions without the PAUX connector addressing via geographical address is not available Although in these versions it is possible to perform a write access to the GEO Address Register for data identification during CBLT operation see S 4 1 4 avoid to use the GEO Register for addressing purposes when there is no PAUX N B after a write access to the GEO register it is necessary to perform a reset to make the change active MCST CBLT Address Register Base Address 0x1004 read write This register contains the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations Refer to S 4 1 4 for details about MCST CBLT addressing mode The register content is the following 15 14 13 12111 10 9 8 7 6 5 4 3121 110 E MCST CBLT ADDR 0 MCST CBLT ADDR 1 MCST CBLT ADDR 2 MCST CBLT ADDR 3 MCST CBLT ADDR 4 MCST CBLT ADDR 5 MCST CBLT ADDR 6 MCST CBLT ADDR 7 Fig 4 12 MCST
82. ta not causing the ADC overflow are written into the MEB overflow suppression default 1 over range check disabled all the data are written into the MEB no overflow suppression LOW THRESHOLD Allows to disable zero suppression see also 2 3 0 low threshold check enabled only data above the threshold are written into the MEB zero suppression default 1 low threshold check disabled all the data are written into the NPO 00102 97 V862x MUTx 08 MEB no zero suppression Filename Number of pages Page V862_REV8 DOC 69 52 for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 TEST ACQ Allows to select the Acquisition Test Mode see 5 6 2 0 normal operation mode i e the data to be stored in the buffer are the real data default 1 Acquisition Test Mode selected i e the data to be stored in the buffer are taken from an internal FIFO Test Event Write Register see 4 32 SLIDE ENABLE Allows to enable disable the sliding scale 0 the sliding scale is disabled and the DAC of the sliding scale is set with a constant value Slide Constant see 4 37 1 the sliding scale is enabled default STEP TH Allows to set the comparison between the converted values and the threshold for Zero Suppression see 2 3 0 the comparison is performed between the 8 MSB of each 12 bit converted value and the 8 bit thres
83. the QAC signals FCLR FAST CLEAR of QAC sections differential ECL output signals BUSY indicates the presence of data DRDY board full resetting converting or in MEMORY TEST mode Displays DTACK green LED lights up at each VME access BUSY red LED alight during conversion reset or Memory Test mode or as the MEB is full DRDY yellow LED alight as there is one event in the MEB TERM orange green red LED alight according to line terminations status OVC PWR green orange LED green at board insertion if orange it indicates that there is an over current status Specifications measured on Mod V862 version AA employing a VME crate WIENER UEV5020 with Control inputs Control outputs UEP5021 power supply lt measured from 5 to 95 of Full Scale Range NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 29 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate 04 11 2009 8 4 VME interface 4 1 Addressing capability The modules can be addressed in three different ways specifically 1 via Base Address 2 via GEOgraphical address 3 via Multicast Chained Block Transfer addressing mode 4 1 1 Addressing via Base Address The module works in A24 A32 mode This implies that the module s address must be specified in a word of 24 or 32 bit The Address Modifier codes recognised by the module are summarised in
84. tical to the Bit Set 2 Register NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 53 CAEN Document type Title Revision date Revision User s Manual MUT Mod 862 32 channel Individual Gate QDC 04 11 2009 8 4 28 W Memory Test Address Register Base Address 0x1036 write only This register contains the address of the memory on which data can be written for the memory test 18 para aa 10 9 8 7 6 514 3 2 0 W TEST ADDRESS 10 0 Fig 4 27 W Memory Test Address Register N B The MEB is a FIFO so the read address R Memory Test Address Register must be different from the write address W memory Test Address Register 4 29 Memory Test Word_High Register Base Address 0x1038 write only The Memory Test Word is a 32 bit word used for the memory test The higher 16 bits are set via this register while the lower 16 bits are set via the Test Word_Low Register These registers are used in TEST mode as follows set the module in test mode see bit 0 of the Bit Set 2 Register 4 26 write the memory address see 4 28 write the 16 MSBs in the TESTWORD HIGH register write the 16 LSBs in the TESTWORD LOW register o With the latter operation the 32 bit pattern is transferred to the memory If operations 3 and 4 are inverted the content of the 16 MSBs may be meaningless 17161514 15 1413 12 ihe 9
85. tions 3 4 1 INPUT connectors Mechanical specifications two 17 17 pin RN 50 68 15 1 type connectors pin assignment shown in Fig 3 2 Electrical specifications negative input signals positive on request 50 O impedance Input range 0 400 The 16 ang 17 higher pair of pins of each connector is connected to ground BLOCK A INPUT Input signals from channel 0 through channel 15 Individual gate from channel 0 through channel 15 BLOCK B INPUT Input signals from channel 16 through channel 31 Individual gate from channel 0 through channel 15 gnd 4 gnd Igate 15 1 15 1 L4 w v 2 ogo Igate 1 8 vin 1 Igate 1 1 Igate 0 gt 4 Vin 0 Igate 0 1 e Vin 0 Fig 3 2 INPUT connector BLOCK A N B individual gates must preceed input signals to be integrated of 15 ns at least NPO Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 22 CAEN Document type User s Manual MUT Title Revision date Revision Mod V862 32 channel Individual Gate QDC 04 11 2009 8 3 4 2 CONTROL connector Mechanical specifications two 8 8 pin 3M 3408 5202 Header type connectors Pin assignment is shown in Fig 3 3 The 1st lower pair of pins is not connected they can be optionally connected to VEE 5 V or to DIGITAL GND b
86. vision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 DREADY Indicates that there are data at least 1 event in the MEB GLOBAL DREADY BUSY GLOBAL BUSY AMNESIA PURGED TERM ON TERM OFF EVRDY 0 No Data Ready 1 Data Ready Indicates that at least one module in the chain has data in the MEB OR of the READY signal of each module in the chain 0 module has Data Ready 1 Atleast one module has Data Ready Busy status indicates that either a conversion is in progress or the board is resetting or the MEB is full or the board is in MEMORY TEST mode 0 Module not Busy 1 Module Busy Indicates that at least a module in a chain is BUSY OR of the BUSY signal of each module in the chain 0 module is Busy 1 Atleast one module is Busy Indicates that no GEO address was picked from the VME connectors 0 GEOis picked from the JAUX 1 GEO is not available from the JAUX it can be written in the GEO Address Register see S 4 7 for MCST operation during a CBLT operation it indicates that the board is purged i e the board has finished to send data 0 the board is not purged 1 the board is purged Termination ON bit 0 notall Control Bus Terminations are ON 1 Control Bus Terminations are ON Termination OFF bit 0 notall Control Bus Terminations are OFF 1 Control Bus Terminations are OFF is a flag for the Event Trigger Regist
87. wn in the figure the complete address of the registers of the two boards will be as follows Board 1 Base addressing A32 OxEEO000000 offset Base addressing A24 0x000000 offset GEO addressing A24 0x280000 offset MEB excluded Board 2 Base addressing A32 0 110000 offset Base addressing A24 0x110000 offset GEO addressing A24 0x400000 offset MEB excluded 4 1 4 MCST CBLT addressing When the Multicast Chained Block Transfer addressing mode is adopted the module works in A32 mode only The Address Modifiers codes recognised by the module are AM ZOxOF A32 supervisory block transfer AM 0x0D A32 supervisory data access MCST 0 0 2 User block transfer CBLT 0 09 A32 User data access MCST Filename Number of pages Page 00102 97 V 862x MUTx 08 V862 REV8 DOC 69 32 CAEN Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gate QDC 04 11 2009 8 NPO The boards be accessed in Multicast Commands mode MCST mode see 41 that allows to write in the registers of several boards at the same time by accessing the MCST Base Address in A32 only once The boards can be accessed in Chained Block Transfer mode CBLT mode see 4 that allows to readout sequentially a certain number of contiguous boards in a VME crate This access is allowed in BLT32 and BLT64 modes only to the MCST Base Address N B The Base Addr
88. xamples The following is an example of MCST and CBLT addressing for four V862 boards plugged into a VME crate To access the boards the steps to be performed are as follows 1 Set the MCST address see 5 4 8 for all boards via VME Base Address geographical addressing if available 2 Setthe bits F B and L B of the MCST Control Register see 8 4 18 according to the operational status active or inactive of each board and to its position in the chain first intermediate or last 3 Write or read the boards via MCST CBLT addressing An example of User procedures which can be used to perform a write access is vme write address data addr mode data mode which contain the following parameters Address the complete address i e Base Address offset Data the data to be either written or read Addr_mode the addressing mode A24 or A32 Data_mode the data mode D16 D32 or D64 BOARD 1 BOARD 2 BOARD 3 BOARD 4 Upper Rotary Switches Lower bytes of Address Lower Rotary Switches Upper bytes of Address Slots dd in the crate 1 0 24 Fig 4 4 MCST CBLT Addressing Example In the following two software examples using the above mentioned procedures are listed NPO Filename Number of pages Page 00102 97 V862x MUTx 08 V862_REV8 DOC 69 34 Is for Discovery Document type Title Revision date Revision User s Manual MUT Mod V862 32 channel Individual Gat
89. y means of a soldering pad on the Printed Circuit Board Refer to 3 6 4 for further details All the control lines described below can be 110 Q terminated on board via internal DIP switches please refer to 3 5 2 for further details FCLR RST DRDY COM GATE VETO BUSY NPO 00102 97 V862x MUTx 08 Filename Electrical specifications diff ECL input signal active high high impedance min width 30 ns Function FAST CLEAR signal accepted if sent within the so called FAST CLEAR window see Fig 2 8 it clears the QAC sections of the unit and aborts completely the conversion in progress Electrical specifications diff ECL input signal active high high impedance min width 30 ns Function clears the QAC sections resets the Multi Event Buffer status stops pending ADCs conversions depending on the User s settings see PROG RESET 4 14 may clear the control registers Electrical specifications diff ECL input output signal high impedance Function indicates the presence of data in the output buffer of the board DATA READY status is also flagged by the bit 0 of the Status Register 1 when several boards are daisy chained the wired OR and wired NAND of DATA READY signals can be read respectively on the DRDY and DRDY lines of the CONTROL bus and the status of the DRDY bidirectional line is flagged by the bit 1 of the Status Register 1 see 8 4 13 not used Electrical sp

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