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MIPS32® M4K™ Processor Core Software User`s Manual

1. Encode Latch Compare Generate Any Causey d Request Interrupt Causepcy ze RIPL A Request Statuspp E j gt Statusgg Statusppo s Interrupt 5g Interrupt Service Exception Started p B o IntCtl y 3 VS amp Requested z Seige S Exception 5 IPL amp Vector Offset g _r 2 2 Number BB i c a ogee 3 Eoo E MH 3 5 E pi lo n 3 A a 6 Shadow Set B pe amp lS 2 Number S O E zz A typical software handler for EIC interrupt mode bypasses the entire sequence of code following the IVexception label shown for the compatibility mode handler above Instead the hardware performs the prioritization dispatching directly to the interrupt processing routine Unlike the compatibility mode examples an EIC interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers As such the SimpleInterrupt code shown above need not save the GPRs A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set It also need only copy Causegmyp to Status p to prevent lower priority interrupts from interrupting the handler Such a routine might look as follows NestedException Nested exceptions typically requi
2. RESTORE SAVE ry bits 7 5 0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111 JRC ra JALRC hi Table 11 11 MIPS16e RR Encoding of the ry Field when funct CNVT ry bits 7 5 7 000 001 010 011 100 101 110 111 ZEB ZEH B 2 SEB SEH p MIPS32 M4K Processor Core Software User s Manual Revision 02 03 231 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS16e Application Specific Extension to the MIPS32 Instruction Set 11 2 Instruction Listing Table 11 12 through 11 19 list the MIPS16e instruction set Table 11 12 MIPS16e Load and Store Instructions Extensible Mnemonic Instruction Instruction LB Load Byte Yes LBU Load Byte Unsigned Yes LH Load Halfword Yes LHU Load Halfword Unsigned Yes LW Load Word Yes SB Store Byte Yes SH Store Halfword Yes SW Store Word Yes Table 11 13 MIPS16e Save and Restore Instructions Mnemonic RESTORE Instruction Restore Registers and Deallocate Stack Frame Extensible Instruction SAVE Save Registers and Setup Stack Frame Table 11 14 MIPS16e ALU Immediate Instructions Mnemonic ADDIU CMPI Instruction Add Immediate Unsigned Compare Immediate Extensible Instruction Yes Yes LI SLTI SLTIU Load Immediate Set on Less Than Immediate Set on Less Than Immediate Unsigned Yes Yes Yes
3. Fields Read Name Bits Description Write Reset State BEV 22 Controls the location of exception vectors R W 1 Encoding Meaning 0 Normal 1 Bootstrap TS 21 TLB shutdown R 0 Since the M4K core does not contain a TLB this bit is ignored on write and read as 0 SR 20 Indicates that the entry through the reset exception vector R W 1 for Soft was due to a Soft Reset Reset 0 other wise Encoding Meaning 0 Not Soft Reset NMI or Reset 1 Soft Reset Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition NMI 19 Indicates that the entry through the reset exception vector R W 1 for NMI 0 was due to an NMI otherwise Encoding Meaning 0 Not NMI Soft Reset or Reset 1 NMI Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition R 18 Reserved Ignored on write and read as zero R 0 CEE 17 CorExtend Enable Implementation dependent If CorEx R W Undefined tend block indicates that this bit should be used any attempt to execute a CorExtend instruction with this bit cleared will result in a CorExtend Unusable exception This bit is reserved if CorExtend is not present R 16 Reserved Ignored on write and read as zero R 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 91 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Table 5 7 Status Register Field Descriptions Continued Fie
4. sess nennen 115 Table 5 24 UserTraceData Register Field Descriptions 1 inet tmo enee ccu iie s 116 Table 5 25 TraceBPC Register Field Descriptions enceinte entrata aiea 117 Table 5 26 Debug2 Register Field Descriptors acierto tq cde a Ia OBS DE 118 Table 5 27 DEPC Register ORTISESa2 cor nanie aiaa oa E aA e Toss iuter de E srsDLEE 119 Table 5 28 ErrorEPC Register Field DesctHpbioh e ucooept cene poete EEN 120 Table 5 29 DeSave Register Field Description reiten erret eene nata et ttr te ke terna da 120 Table 8 1 Debug Control Register Field Descriptions esses nnne nennen nnne 128 Table 8 2 Addresses for Instruction Breakpoint Registers ener 134 Table 8 3 BS Register Field DGSCFEIHORS sss ito EI E nete De E Rape Seb tee EI Des Ur eadhdeuie ERR ES E e Sepdes pe nsa sad EGO 134 Table 8 4 BAn Register Field Descriptions uoa etate tree ta ita port a ena a ner Rcx ta pes exka npa Rc ebd net ead 135 Table 8 5 6Mn Register Field IDescriptlOl1S croire eio den ancsayasnvacdec a Pape eprdscRDS Se E M RE UNaG 135 Table 8 6 JBAS Dn Register Fleld DescripftiORS ori aset tiu eee tonc saa et Pete teneas ER dite dug 136 Table 8 7 158Cn Register Field Descriptions ure cete erp nip ENE e iiubc etes x soe ies alerte use ERSR 136 Table 8 8 JBCCn Register Field DescrlpltiOns u s anoche tk teresa E Exe cora Nera aaa oLa anadai 137 Table 8 10 Ad
5. An kes ee EX HW5 amp W p7 NM Statusg HW4 8 Pol MG IntCtlys Hw3 6 p ims HW2 Tp vl im i Vector S Exception Hwi IL p T TE gt E Number b 5 Vector Offset hes tna 3 IP1 TMI gi Eg Causey SRSMap Shadow Set Number A typical software handler for vectored interrupt mode bypasses the entire sequence of code following the IVexcep tion label shown for the compatibility mode handler above Instead the hardware performs the prioritization dis patching directly to the interrupt processing routine Unlike the compatibility mode examples a vectored interrupt MIPS32 M4K Processor Core Software User s Manual Revision 02 03 61 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 62 handler may take advantage of a dedicated GPR shadow set to avoid saving any registers As such the SimpleInter rupt code shown above need not save the GPRs A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exceptio n routine in the GPR shadow set dedicated to the interrupt or in another shadow set Such a routine might look as follows Nes F F F FH F ua tedException Nested exceptions typically require saving the EPC Status and SRSCtl registers setting up the appropriate GPR shadow set for the routine dis
6. Status Register Bit Value Address Bit Segment Value EXL ERL UM Name Address Range Segment Size 32 bit 0 0 1 useg 0x0000_0000 gt 2 GByte A 31 20 Ox7FFF FFFF 23 bytes 46 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation All valid user mode virtual addresses have their most significant bit cleared to 0 indicating that user mode can only access the lower half of the virtual memory map Any attempt to reference an address with the most significant bit set while in user mode causes an address error exception The system maps all references to useg through the FM 3 2 3 Kernel Mode The processor operates in Kernel mode when the DM bit in the Debug register is 0 and the Status register contains one or more of the following values e UM 0 e ERL 1 e EXL 1 When a non debug exception is detected EXL or ERL will be set and the processor will enter Kernel mode At the end of the exception handler routine an Exception Return ERET instruction is generally executed The ERET instruction jumps to the Exception PC clears ERL and clears EXL if ERL 0 This may return the processor to User mode Kernel mode virtual address space is divided into regions differentiated by the high order bits of the virtual address as shown in Figure 3 4 Also Table 3 2 lists the characteristics of the Kernel mode segments MI
7. 8 11 5 TCBTW Register Reg 4 The TCBTW register is used to read Trace Words from the on chip trace memory The TW read is the one pointed to by the 7CBADP register A side effect of reading the TCBTW register is that the TCBRDP register increments to the next TW in the on chip trace memory If TCBRDP is at the max size of the on chip trace memory the increment wraps back to address zero This register is reserved if on chip trace memory is not implemented The format of the TCBTW register is shown below and the field is described in Table 8 44 TCBTW Register Format 63 0 Data Table 8 44 TCBTW Register Field Descriptions Read W Reset men Description rite State MIPS32 M4K Processor Core Software User s Manual Revision 02 03 189 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 8 11 6 TCBRDP Register Reg 5 The TCBRDP register is the address pointer to on chip trace memory It points to the TW read when reading the TCBTW register When writing the TCBCONTROLBRgy bit to 1 this pointer is reset to the current value of TCBSTP This register is reserved if on chip trace memory is not implemented The format of the TCBRDP register is shown below and the field is described in Table 8 45 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always zero TCBRDP Regi
8. e Section 8 4 Test Access Port TAP e Section 8 5 EJTAG TAP Registers e Section 8 6 TAP Processor Accesses e Section 8 7 Trace Mechanisms e Section 8 8 iFlowtrace Mechanism e Section 8 9 EJTAG Trace e Section 8 10 PDtrace Registers Software Control e Section 8 11 Trace Control Block TCB Registers Hardware Control e Section 8 12 EJTAG Trace Enabling e Section 8 13 TCB Trigger logic e Section 8 14 EJTAG Trace Cycle by Cycle Behavior e Section 8 15 TCB On Chip Trace Memory MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 127 EJTAG Debug Support in the M4K Core 8 1 Debug Control Register 31 30 The Debug Control Register DCR register controls and provides information about debug issues and is always pro vided with the CPU core The register is memory mapped in drseg at offset 0x0 The DataBrk and InstBrk bits indicate if hardware breakpoints are included in the implementation and debug soft ware is expected to read hardware breakpoint registers for additional information Hardware and software interrupts are maskable for non debug mode with the NTE bit which works in addition to the other mechanisms for interrupt masking and enabling NMI is maskable in non debug mode with the NMIE bit and a pending NMI is indicated through the NMIP bit The SRE bit al
9. ssssss 33 Figure 2 T3 D Pipeline Branch Delay us aoc cos Pretorio hpr SEE Ep EnsexeenbexpexSekba ONNEEN EE 34 Figure 2 14 IU Pipeline Data DVDaSS xuxasanuteenstibrens toupasa aside ed bQEF atqddedpr apiid dtes is pra RUN UNE fS 34 Figure 2 15 1U Pipeline M to E Bypass i dieit art hid ene p E tei eei totae e tane eei E iwiaiecied staniteisatnnaccatneaneizensintd 35 Figure 2 16 1U Pipeline Ato E Data DypasS it pr etat Een ba epos ENN 35 Figure 2 17210 Pipeline Slip atten a MEE iso ea tr tp ibtd eR Pa Pee REX ese R e Ra preteen Pe exa rarae ANNALEN 36 Figure 2 18 Coprocessor 2 Interface Transactions uscire ito ec putee sheds ute tuderedtnc ud tus sei intu Aa 37 Figufe 2 1 9 Instruction Cache MISS SIID aactor aereis cea Up atate ro at uices ees ee ute i let pa ce EP rea E Lise M eL IUS 38 Figure 3 T Address Translation During SRAM ACCESS iter tetra eI Rea Re a ERR RR ases Rau RENE ERRR Dane 43 Figure 3 2 M4K processor core Virtual Memory Map ssssesssssssseseeeeeenenene nennen nennen nsns trennen sistens 45 Figure 3 9 User Mode Virtual Address Spa868 iioii irr itia scs reine ph a de Scr aun Kir RE sd bu e AR 46 Figure 3 4 Kernel Mode Virtual Address Space c ie te bue Ie or dace Lose o Ek aaa dd MEAE EIE 48 Figure 3 5 Debug Mode Virtual Address Space tte ttti esten E nedadeaseiets 50 Figure 3 6 FM Memory Map ERL 0 in the M4K Processor Core ssssssseeeeenennnmeenen nnns 52
10. Probe Enable This bit reflects the ProbEn bit in the EJTAG Control regis ter 0 No accesses to dmseg allowed 1 EJTAG probe services accesses to dmseg R Same value as ProbEn in ECR see Table 9 4 8 2 Hardware Breakpoints Hardware breakpoints provide for the comparison by hardware of executed instructions and data load store transac tions It is possible to set instruction breakpoints on addresses even in ROM area Data breakpoints can be set to cause a debug exception on a specific data transaction Instruction and data hardware breakpoints are alike for many aspects and are thus described in parallel in the following The term hardware is not generally added to breakpoint unless required to distinguish it from a software breakpoint There are two types of simple hardware breakpoints implemented in the M4K core Instruction breakpoints and Data breakpoints The M4K core may also contain a complex breakpoint unit A core may be configured with the following breakpoint options No data or instruction breakpoints without complex break support e Two instruction and one data breakpoint without complex break support MIPS326 M4K Processor Core Software User s Manual Revision 02 03 129 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core e Four instruction and two data breakpoints without complex break support e Six instruction and two data breakpoints
11. Table 11 15 MIPS16e Arithmetic Two or Three Operand Register Instructions Mnemonic Instruction Extensible Instruction ADDU Add Unsigned AND AND CMP 232 Compare MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 11 2 Instruction Listing Table 11 15 MIPS16e Arithmetic Two or Three Operand Register Instructions Extensible Mnemonic Instruction Instruction Sign Extend Byte Sign Extend Halfword Set on Less Than Set on Less Than Unsigned Subtract Unsigned Exclusive OR Zero Extend Byte Zero Extend Halfword Table 11 16 MIPS16e Special Instructions Extensible Mnemonic Instruction Instruction BREAK Breakpoint No Extensible Mnemonic Instruction Instruction DIVU Divide Unsigned MFHI Move From HI MFLO Move From LO MULT Multiply MULTU Multiply Unsigned MIPS32 M4K Processor Core Software User s Manual Revision 02 03 233 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS16e Application Specific Extension to the MIPS32 Instruction Set Table 11 18 MIPS16e Jump and Branch Instructions enone momonon maen Instruction Branch Unconditional C BNEZ Branch on Not Equal to Zero on Not Branch on Not Equal to Zero to Zero E Branch on T Equal to Zero BE M BTNEZ Branch on T Not Equal to Zero Yes Jump and Link
12. Table 5 4 BadVAddr Register Field Description Fields Read Wr Name Bits Description ite Reset State BadVAddr 31 0 Bad virtual address R Undefined 5 2 3 Count Register CPO Register 9 Select 0 The Count register acts as a timer incrementing at a constant rate whether or not an instruction is executed retired or any forward progress is made through the pipeline The counter increments every other clock if the DC bit in the Cause register is 0 The Count register can be written for functional or diagnostic purposes including at reset or to synchronize proces sors By writing the CountDM bit in the Debug register it is possible to control whether the Count register continues incrementing while the processor is in debug mode Figure 5 3 Count Register Format 31 0 Count Table 5 5 Count Register Field Description Fields Read Wr Name Bits Description ite Reset State Count 31 0 Interval counter R W Undefined 88 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 4 Compare Register CPO Register 11 Select 0 The Compare register acts in conjunction with the Count register to implement a timer and timer interrupt function The timer interrupt is an output of the cores The Compare register maintains a stable value and does not change on its own
13. 1 2 2 3 Coprocessor 2 Interface CP2 The optional coprocessor 2 CP2 interface provides a full featured interface for a coprocessor It provides full sup port for all the MIPS32 COP2 instructions with the exception of the 64 bit Load Store instructions LDC2 SDC2 The CP2 interface can provide access to a graphics accelerator coprocessor or a simple register file There is no sup port for the floating point coprocessor COPI which requires 64 bit data transfers Refer to Chapter 10 M4K Processor Core Instructions on page 207 for more information on the Coprocessor 2 supported instructions 2 2 4 CorExtend User Defined Instructions UDI This optional module contains support for CorExtend user defined instructions These instructions must be defined at build time for the M4K core Access to UDI requires a separate license from MIPS and the core is then referred to as the M4K Pro core When licensed 16 instructions in the opcode map are available for UDI and each instruction can have single or multi cycle latency A UDI instruction can operate on any one or two general purpose registers or immediate data contained within the instruction and can write the result of each instruction back to a general purpose register or local register Implementation details for UDI can be found in other documents available from MIPS Refer to Table 10 3 Special2 Opcode Encoding of Function Field for a specification of the opcode map
14. DB value match The match on the address part DB addr match depends on the virtual address of the transaction ADDR and the accessed bytes BYTELANE where BYTELANB 0 is 1 only if the byte at bits 7 0 on the bus is accessed and BYTELANE 1 is 1 only if the byte at bits 15 8 is accessed etc The DB addr match is shown below DB addr match all 1 s DBMnyg ADDR DBAnpg amp amp all O s gt BAI amp BYTELANE The size of DBCngA and BYTELANE is 4 bits Data value compare is included in the match condition for the data breakpoint depending on the bytes BYTELANE as described above accessed by the transaction and the contents of breakpoint registers The DB no value compare is shown below DB no value compare MIPS32 M4K Processor Core Software User s Manual Revision 02 03 131 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 132 all 1 s DBCng y DBCnga BYTELANE The size of DBCng yy DBCngA and BYTELANE is 4 bits In case a data value compare is required DB no value compare is false then the data value from the data bus DATA is compared and masked with the registers for the data breakpoint The DBC yy bit inverts the sense of the match if set the value match term will be high if the data value is not the same as the data in the DB Vn register The endianess
15. Jump and Link Register Jump and Link Register Compact Jump and Link Exchange Jump Register Jump Register Compact Table 11 19 MIPS16e Shift Instructions Extensible Instruction Shift Right Arithmetic SRAV Shift Right Arithmetic Variable SLL shit Left Shift Left Logical Shift Left EE AINSI Variable Shift Right Logical SRLV Shift Right Logical Variable 234 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Appendix A Revision History Change bars vertical lines in the margins of this document indicate significant changes in the document since its last release Change bars are removed for changes that are more than one revision old This document may refer to Architecture specifications for example instruction set descriptions and EJTAG register definitions and change bars in these sections indicate changes since the previous version of the relevant Architecture document Revision 00 90 Date Description June 27 2002 Preliminary release 01 00 August 28 2002 Initial commercial release Removed TLB related instruction descriptions from Chapter 10 M4K Processor Core Instructions on page 207 The associ ated opcodes are shown as reserved in Table 10 9 Updated HSS field in SRSCt register to show possible values Added description of MT field in Config register that was
16. Processor Core Software User s Manual Revision 02 03 201 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 8 15 2 Trace From Mode In the Trace From mode tracing begins when the processor enters into a processor mode which is defined to be traced or when an EJTAG hardware breakpoint trace trigger turns on tracing Trace collection is stopped when the buffer is full The TCB then signals buffer full using TCBCONTROLBpp When external software polling this register finds the TCBCONTROLBg g bit set it can then read out the internal trace memory Saving the trace into the internal buffer will re commence again only when the TCBCONTROLBpp bit is reset and if the core is sending valid trace data i e PDO_lamTracing not equal 0 8 15 3 Trace To Mode In the Trace To mode the TCB keeps writing into the internal trace memory wrapping over and overwriting the old est information until the processor is reaches an end of trace condition End of trace is reached by leaving the proces sor mode which is traced or when an EJTAG hardware breakpoint trace trigger turns tracing off At this point the on chip trace buffer is then dumped out in a manner similar to that described above in 8 15 2 Trace From Mode 202 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 9 Instruction Set Overview
17. e Multiply and divide calculations proceed in the MDU If the calculation completes before the IU moves the instruction past the M stage then the MDU holds the result in a temporary register until the IU moves the instruc tions to the A stage and it is consequently known that it won t be killed 2 1 4 A Stage Align During the Align stage e A separate aligner aligns loaded data with its word boundary e A MUL operation makes the result available for writeback The actual register writeback is performed in the W stage e From this stage load data or a result from the MDU are available in the E stage for bypassing MIPS32 M4K Processor Core Software User s Manual Revision 02 03 25 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core 2 1 5 W Stage Writeback During the Writeback stage Forregister to register or load instructions the result is written back to the register file 2 2 Multiply Divide Operations The M4K core implement the standard MIPS IITM multiply and divide instructions Additionally several new instruc tions were standardized in the MIPS32 architecture for enhanced performance The targeted multiply instruction MUL specifies that multiply results be placed in the general purpose register file instead of the HI LO register pair By avoiding the explicit MFLO instruction required when using the LO register and by supporting multiple destination register
18. e Section 4 2 Exception Priority e Section 4 3 Interrupts e Section 4 4 GPR Shadow Registers e Section 4 5 Exception Vector Locations e Section 4 6 General Exception Processing e Section 4 7 Debug Exception Processing e Section 4 8 Exceptions e Section 4 9 Exception Handling and Servicing Flowcharts 4 1 Exception Conditions When an exception condition occurs the relevant instruction and all those that follow it in the pipeline are cancelled Accordingly any stall conditions and any later exception conditions that may have referenced this instruction are inhibited there is no benefit in servicing stalls for a cancelled instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 55 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core When an exception condition is detected on an instruction fetch the core aborts that instruction and all instructions that follow When this instruction reaches the W stage the exception flag causes it to write various CPO registers with the exception state change the current program counter PC to the appropriate exception vector address and clear the exception bits of earlier pipeline stages This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing Thus the value in the EPC ErrorEPC for errors
19. 0 19 17 Reserved Must be written as zero returns zero on read R 0 RM 16 Read on chip trace memory R WI1 0 When written to 1 the read address pointer of the on chip memory is set to point to the oldest memory location written since the last reset of pointers Subsequent access to the TCBTW register through the TCBDATA register will automatically increment the read pointer TCBRDP register after each read Note The read pointer does not auto increment if the WR field is one When the write pointer is reached this bit is automatically reset to 0 and the TCBTW register will read all zeros Once set to 1 writing 1 again will have no effect The bit is reset by setting the TR bit or by reading the last Trace word in TCBTW This bit is reserved if on chip memory is not implemented TR 15 Trace memory reset R W1 0 When written to one the address pointers for the on chip trace memory are reset to zero Also the RM bit is reset to 0 This bit is automatically de asserted back to 0 when the reset is completed This bit is reserved if on chip memory is not implemented BF 14 Buffer Full indicator that the TCB uses to communicate to R 0 external software in the situation that the on chip trace memory is being deployed in the trace from and trace to mode See 8 15 TCB On Chip Trace Memory This bit is cleared when writing 1 to the TR bit This bit is reserved if on chip memory is not implemented 184
20. 23 4 TraceBPC 5 2 21 TraceBPC Register CPO Register 23 Select 4 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 179 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 8 11 Trace Control Block TCB Registers Hardware Control The TCB registers used to control its operation are listed in Table 8 37 and Table 8 38 These registers are accessed via the EJTAG TAP interface Table 8 37 TCB EJTAG registers EJTAG Register Name Reference Implemented 0x10 TCBCONTROLA 8 11 1 TCBCONTROLA Register on page 180 TCBCONTROLB 8 11 2 TCBCONTROLB Register on page 183 TCBDATA 8 11 3 TCBDATA Register on page 187 Table 8 38 Registers selected by TCBCONTROLB TCBCONTROLBgE a field Reference Implemented 0 TCBCONFIG TCBCONFIG Register Reg 0 on page 188 Yes 4 TCBTW Register Reg 4 on page 189 Yes 5 TCBRDP TCBRDP Register Reg 5 on page 190 if a a 6 TCBWRP TCBWRP Register Reg 6 on page 190 Otherwise No 7 TCBSTP TCBSTP Register Reg 7 on page 190 16 23 TCBTRIGx TCBTRIGx Register Reg 16 23 on page 191 Only the number indicated by TCBCONFIGTg1G are implemented 8 11 1 TCBCONTROLA Register The TCB is responsible for asserting or de asserting the trace input control signals on the PDtrace interface to the core s tracing logic Most of the control is done using the TCBCONTROLA register
21. Core Block Diagram e Power Management Optional blocks include e Enhanced JTAG EJTAG Controller e MIPS16e support e Coprocessor 2 Interface CP2 CorExtendQ User Defined Instructions UDI Figure 1 1 shows a block diagram of a M4K core Figure 1 1 M4K Processor Core Block Diagram VF UDI Execution Core RF ALU Shift SRAM I F System Coprocessor i Opi Coprocessor 2 F ixed R equired Optional 1 2 1 Required Logic Blocks The following subsections describe the various required logic blocks of the M4K processor core 1 2 1 1 Execution Unit Off On Chip Trace I F Off Chip Debug Dual or Unified On chip SRAM The core execution unit implements a load store architecture with single cycle Arithmetic Logic Unit ALU opera tions logical shift add subtract and an autonomous multiply divide unit The core contains thirty two 32 bit gen eral purpose registers GPRs used for scalar integer operations and address calculation Optionally one or three additional register file shadow sets each containing thirty two registers can be added to minimize context switching overhead during interrupt exception processing The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline The execution unit includes e 32 bit adder used for calculating the data address MIPS32 M4K Processor
22. MIPS32 Instruction Set for the M4K core on page 210 9 4 2 Overview of Branch Instructions All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16 bit offset shifted left 2 bits and sign extended to 32 bits All branches occur with a delay of one instruction If a conditional branch likely is not taken the instruction in the delay slot is nullified Branches jumps ERET and DERET instructions should not be placed in the delay slot of a branch or jump 9 5 Control Instructions Control instructions allow the software to initiate traps they are always R type 9 6 Coprocessor Instructions 206 CPO instructions perform operations on the System Control Coprocessor registers to manipulate the memory manage ment and exception handling facilities of the processor Refer to Chapter 10 M4K Processor Core Instructions on page 207 for a listing of CPO instructions MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 10 M4K Processor Core Instructions This chapter supplements the MIPS32 Architecture Reference Manual by describing instruction behavior that is spe cific to a MIPS32 MAK processor core The chapter is divided into the following sections e Section 10 1 Understanding the Instruction Descriptions e Section 10 2 M4K Opcode Map e S
23. Ox Copyright 2002 2008 MIPS Technologies Inc All rights reserved 147 EJTAG Debug Support in the M4K Core 31 STCni Register Format 0 Table 8 25 STCi Register Field Descriptions Fields pies ee 2l Read Wr Name Bit s Description ite Reset State Count 31 0 Current counter value R W 0 8 3 Complex Breakpoint Usage 8 3 1 Checking for Presence of Complex Break Support Software should verify that the complex breakpoint hardware is implemented prior to attempting to use it The full sequence of steps is shown below for general use Spots where the a M4K core has restricted behavior are noted 1 148 Read the Config Ep bit to check for the presence of EJTAG logic EJTAG logic is always present on a M4K core Read the Debugywopcg bit to check for the presence of the Debug Control Register DCR The DCR will always be implemented on a M4K core Read the DCHgpr bit to check for the presence of any complex break and trigger features Read the CBTControl register to check for the presence of each individual feature If a MAK core implements any complex break and trigger features it will implement all of them If Pass Counters are implemented they may not be implemented for all break channels and may have different counter sizes To determine the size and presence of each pass counter software can write 1 to each of the IBPCn and DBPCn registers and read it back If a M4K core implements pas
24. Reset State Must be written with zero returns zero on read Each bit in this field enables access by the RDHWR instruction to a particular hardware register which may not be an actual register If bit n in this field is a 1 access is enabled to hardware register n If bit n of this field is a 0 access is disabled See the RDHWR instruction for a list of valid hard ware registers MIPS32 M4K Processor Core Software User s Manual Revision 02 03 87 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Privileged software may determine which of the hardware registers are accessible by the RDHWR instruction In doing so a register may be virtualized at the cost of handling a Reserved Instruction Exception interpreting the instruction and returning the virtualized value For example if it is not desirable to provide direct access to the Count register access to that register may be individually disabled and the return value can be virtualized by the operating system 5 2 2 BadVAddr Register CPO Register 8 Select 0 The BadVAdor register is a read only register that captures the most recent virtual address that caused the following exception e Address error AdEL or AdES The BadVAddar register does not capture address information for bus errors since they are not addressing errors Figure 5 2 BadVAddr Register Format 31 0 BadVAddr
25. There is only one exception to this and that is the Branch on Coprocessor conditions BC2 instruction All branch instructions including the regular BEQ BNE etc must be resolved in E stage The M4K core does not have branch prediction logic and thus the target address must be available before the end of E stage The BC2 instruction has to follow the same protocol as all other coprocessor 2 instructions on the CP2 Interface All core interface operations belonging to the E M and A stages will have to occur in the E stage for BC2 instructions This means that a BC2 instructions always slips for a minimum of 2 cycles in E stage Any delay in return of branch information from the Coprocessor 2 will add to the number of slip cycles All other Coprocessor 2 instructions can operate without slips provided that all control and data information from the Coprocessor 2 is transferred in the M stage 2 8 Interlock Handling Smooth pipeline flow is interrupted when cache misses occur or when data dependencies are detected Interruptions handled entirely in hardware such as cache misses are referred to as interlocks At each cycle interlock conditions are checked for all active instructions Table 2 4 lists the types of pipeline interlocks for the M4K processor core Table 2 4 Pipeline Interlocks Interlock Type Sources Slip Stage I side SRAM Stall SRAM Access not complete Instruction Producer consumer hazards Hardware Dependencies MDU BC2 wai
26. e Power down mode triggered by WAIT instruction e Support for software controlled clock divider e Support for extensive use of fine grain clock gating e EJTAG Debug Support e CPU control with start stop and single stepping e Software breakpoints via the SDBBP instruction e Optional simple hardware breakpoints on virtual addresses 4 instruction and 2 data breakpoints 2 instruc tion and 1 data breakpoint or no breakpoints e Optional complex hardware breakpoints with 6 instruction and 2 data simple breakpoints plus ability to specify combinations of breakpoints for more specific break conditions e Optional Test Access Port TAP facilitates high speed download of application code e Optional trace hardware to enable real time tracing of executed code 1 2 M4K Core Block Diagram The M4K core contains both required and optional blocks as shown in the block diagram in Figure 1 1 Required blocks are the lightly shaded areas of the block diagram and are always present in any core implementation Optional blocks may be added to the base core depending on the needs of a specific implementation The required blocks are as follows e Execution Unit e Multiply Divide Unit MDU e System Control Coprocessor CPO e Memory Management Unit MMU e Cache Controller e SRAM Interface MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 1 2 M4K
27. rently being written and is used to select the appropri ate interpretation of the TraceControl2gyp field Encoding Meaning 0 Trace data is being sent to an on chip trace buffer 1 Trace Data is being sent to an off chip trace buffer MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 115 CPO Registers of the M4K Core Table 5 23 TraceControl2 Register Field Descriptions Continued Fields Description Reset State Used to indicate the synchronization period Undefined The period in cycles between which the periodic syn chronization information is to be sent is defined as shown below for both when the trace buffer is on chip and off chip SyP On chip Off chip 000 3 001 23 010 24 011 100 101 110 111 The On chip column value is used when the trace data is being written to an on chip trace buffer e g TraceControl2ygy 0 Conversely the Off chip column is used when the trace data is being written to an off chip trace buffer e g TraceControl2rgy 1 5 2 20 User Trace Data Register CPO Register 23 Select 3 A software write to any bits in the UserTraceData register will trigger a trace record to be written indicating a type 1 or type 2 user format The type is based on the UT bit in the TraceControl register This register cannot be
28. A debug software breakpoint exception occurs when an SDBBP instruction is executed The DEPC register and DBD bit in the Debug register will indicate the SDBBP instruction that caused the debug exception Debug Register Debug Status Bit Set DBp Additional State Saved None Entry Vector Used Debug exception vector 4 8 10 Execution Exception System Call The system call exception is one of the nine execution exceptions All of these exceptions have the same priority A system call exception occurs when a SYSCALL instruction is executed Cause Register ExcCode Value Sys MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 8 Exceptions Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 11 Execution Exception Breakpoint The breakpoint exception is one of the nine execution exceptions All of these exceptions have the same priority A breakpoint exception occurs when a BREAK instruction is executed Cause Register ExcCode Value Bp Additional State Saved None Entry Vector Used General exception vector offset 0x 180 4 8 12 Execution Exception Reserved Instruction The reserved instruction exception is one of the nine execution exceptions All of these exceptions have the same pri ority A reserved instruction exception occurs when a reserved or undefined major opcode or
29. An instruction immedi ately following a load instruction will if it has the same source register as was the target of the load cause an instruc tion interlock pipeline slip in the E stage see 2 10 Instruction Interlocks on page 38 If an instruction following the load by 1 or 2 cycles uses the data from the load the A to E bypass see Figure 2 14 serves to reduce or avoid stall cycles An instruction flow of this is shown in Figure 2 16 Figure 2 16 IU Pipeline A to E Data bypass One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle Load Instruction E M A W Data bypass from A to E M A Consumer of Load Data Instruction LLL One Clock Load Delay 2 6 2 Move from HI LO and CPO Delay As indicated in Figure 2 14 not only load data but also data moved from the HI or LO registers MFHI MFLO and data moved from CPO MFCO enters the IU Pipeline in the A stage That is data is not available in the integer pipe line until early in the A stage The A to E bypass is available for this data But as for Loads an instruction following immediately after one of these move instructions must be paused for one cycle if the target of the move is among the sources of that following instruction This then causes an interlock slip in the E stage see 2 10 Instruction Interlocks on page 38 An interlock slip after a MFHI is illustrated in Figure 2 17 MIPS326 M4K Processor Core Software User
30. DC IV and WP fields all fields in the Cause register are read only Release 2 of the Architecture added optional support for an External Interrupt Controller EIC interrupt mode in which P7 are interpreted as the Requested Interrupt Priority Level RIPL Figure 5 9 shows the format of the Cause register Table 5 12 describes the Cause register fields Figure 5 9 Cause Register Format 31 30 29 28 27 26 25 24 23 22 21 16 15 10 9 8 7 6 B 1 0 BDITI CE DCPCI 0 IV WP 0 IP7 IP2 IP1 IPO 0 Exc Code 0 RIPL Table 5 12 Cause Register Field Descriptions Fields Read Wri Name Bits Description te Reset State BD TI CE 31 30 29 28 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Indicates whether the last exception taken occurred in a branch delay slot Encoding Meaning 0 Not in delay slot 1 In delay slot The processor updates BD only if Statusgx was zero when the exception occurred Timer Interrupt This bit denotes whether a timer inter rupt is pending analogous to the IP bits for other inter rupt types Encoding Meaning 0 No timer interrupt is pending 1 Timer interrupt is pending The state of the TI bit is available on the external core interface as the S Timerlnt signal Coprocessor unit number referenced when a Coproces sor Unusable
31. IP7 IP2 15 10 Indicates an interrupt is pending R Undefined Bit Name Meaning 15 IP7 Hardware interrupt 5 14 IP6 Hardware interrupt 4 13 IPS Hardware interrupt 3 12 IP4 Hardware interrupt 2 11 IP3 Hardware interrupt 1 10 IP2 Hardware interrupt 0 If EIC interrupt mode is not enabled timer interrupts are combined in a system dependent way with any hard ware interrupt If EIC interrupt mode is enabled these bits take on a different meaning and are interpreted as the RIPL field described below See 4 3 Interrupts on page 57 for a general descrip tion of interrupt processing RIPL 15 10 Requested Interrupt Priority Level R Undefined If EIC interrupt mode is enabled this field is the encoded 0 63 value of the requested interrupt A value of zero indicates that no interrupt is requested If EIC interrupt mode is not enabled these bits take on a different meaning and are interpreted as the IP7 IP2 bits described above IP1 IPO 9 8 Controls the request for software interrupts R W Undefined Bit Name Meaning 9 IP1 Request software interrupt 1 8 IPO Request software interrupt 0 These bits are exported to an external interrupt control ler for prioritization in EIC interrupt mode with other interrupt sources The state of these bits is available on the external core interface as the S SWint 1 0 bus ExcCode 6 2 Exception code see Table 5 13 R Undefined 0 25 24 Must be written as zero returns zero on read
32. Refer to Chapter 3 Memory Management of the M4K Core on page 43 for more information on the FMT Figure 1 2 shows how the address translation mechanism interacts with SRAM access Figure 1 2 Address Translation During a SRAM Access Virtual Physical Instruction Address Address Gand lator Em Instn SRAM FMT Data Data SRAM Address gt Calculator Virtual Pall s cie Address ress 1 2 1 5 SRAM Interface Instead of caches the M4K core contains an interface to SRAM style memories that can be tightly coupled to the core This permits deterministic response time with less area than is typically required for caches The SRAM inter face includes separate unidirectional 32 bit buses for address read data and write data Dual or Unified Interfaces The SRAM interface includes a build time option to select either dual or unified instruction and data interfaces The dual interface enables independent connection to instruction and data devices It generally yields the highest perfor mance since the pipeline can generate simultaneous I and D requests which are then serviced in parallel For simpler or cost sensitive systems it is also possible to combine the I and D interfaces into a common interface that services both types of requests If I and D requests occur simultaneously priority is given to the D side Backstalling Typically read or write transactions will complete in a single cycle If
33. Refer to Table 5 17 for the field encoding This field controls the cacheability of the kuseg and useg address segments in FM implementations Refer to Table 5 17 for the field encoding FM R W 1 FM 010 FM 010 UDI Must be written as 0 Returns zero on reads This bit indicates that CorExtend User Defined Instructions have been implemented 0 No User Defined Instructions are implemented 1 User Defined Instructions are implemented 0 Preset SB Indicates whether SimpleBE bus mode is enabled Set via SI SimpleBE 0 input pin 0 No reserved byte enables on SRAM interface 1 Only simple byte enables allowed on SRAM interface Externally Set MDU This bit indicates the type of Multiply Divide Unit present 0 Fast high performance MDU 1 Iterative area efficient MDU Must be written as 0 Returns zero on reads Preset 0 DS BE AT 14 13 Dual SRAM interface 0 Unified instruction data SRAM interface 1 Dual instruction data SRAM interfaces Indicates the endian mode in which the processor is run ning Set via S _Endian input pin 0 Little endian 1 Big endian Architecture type implemented by the processor This field is always 00 to indicate the MIPS32 architecture Preset Externally Set 00 AR 12 10 Architecture revision level This field is always 001 to indi cate MIPS32 Release 2 0 Release 1 Release2 2 7 Reserved
34. Statusyp 1 ERET Return from Exception if SR 2 PC ErrorEPC else PC EPC SR 1 0 SR 2 0 LL 0 EXT Extract Bit Field Rt ExtractField Rs msbd lsb INS Insert Bit Field Rt InsertField Rt Rs msb sb 212 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M4K core Table 10 10 Instruction Set Continued Instruction Description Function J Unconditional Jump PC PC 31 28 Il offset lt lt 2 JAL Jump and Link GPR 31 PC 8 PC PC 31 28 Il offset lt lt 2 JALR Jump and Link Register Rd PC 8 PC Rs JALR HB Jump and Link Register with Hazard Barrier Rd PC 8 PC Rs Stall until all execution and instruc tion hazards are cleared JR Jump Register PC Rs JR HB Jump Register with Hazard Barrier PC Rs Stall until all execution and instruc tion hazards are cleared LB Load Byte Rt byte Mem Rs offset LBU Unsigned Load Byte Rt ubyte Mem Rs offset LH Load Halfword Rt half Mem Rs offset LHU Unsigned Load Halfword Rt uhalf Mem Rs offset LL Load Linked Word Rt Mem Rs offset LL 1 LLAdr Rs offset LUI Load Upper Immediate Rt immediate lt lt 16 LW Load Word Rt Mem Rs offset LWC2 Load Word To Coprocessor 2 CPR 2 n 0 Mem Rs offset LWL Load Word Left See LWL instruction LWR Load Word Right See LWR instruction MADD Multiply Add HI LO int
35. addu k0 kO k1 Compute target from base and offset JE ko Jump to specific exception routine nop Each interrupt processing routine processes a specific interrupt analogous to those reached in VI or EIC interrupt mode Since each processing routine is dedicated to a particular interrupt line it has the context to know which line was asserted Each processing routine may need to look further to determine the actual source of the interrupt if multiple interrupt requests are ORed together on a single IP line Once that task is performed the interrupt may be processed in one of two ways Completely at interrupt level e g a simply UART interrupt The SimpleInterrupt routine below is an example of this type By saving sufficient state and re enabling other interrupts In this case the software model determines which interrupts are disabled during the processing of this interrupt Typically this is either the single StatusIM bit that corresponds to the interrupt being processed or some collection of other Status bits so that lower priority interrupts are also disabled The NestedInterrupt routine below is an example of this type SimpleInterrupt Process the device interrupt here and clear the interupt request at the device In order to do this some registers may need to be saved and restored The coprocessor 0 state is such that an ERET will simple return to the interrupted code
36. and the EJTAG Control register between 7Dland TDO It can be used in particular if switching instructions in the instruction register takes too many TCK cycles The first bit shifted out is bit 0 Figure 8 2 Concatenation of the EJTAG Address Data and Control Registers TDI 3 Address 0 E Data 0 En EJ TAG Control 0 TDO 8 4 3 8 EJTAGBOOT Instruction When the EJTAGBOOT instruction is given and the Update IR state is left then the reset values of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 1 after a hard or soft reset This EJTAGBOOT indication is effective until a NORMALBOOT instruction is given TRST_WNis asserted or a ris ing edge of TCK occurs when the TAP controller is in Test Logic Reset state Itis possible to make the CPU go into debug mode just after a hard or soft reset without fetching or executing any instructions from the normal memory area This can be used for download of code to a system which have no code in ROM The Bypass register is selected when the EJTAGBOOT instruction is given 8 4 3 9 NORMALBOOT Instruction When the NORMALBOOT instruction is given and the Update IR state is left then the reset value of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 0 after hard or soft reset MIPS32 M4K Processor Core Software User s Manual Revision 02 03 157 Copyright 2002 2008 MIPS Technologies Inc All rights
37. and the reset state of the field For the read write properties of the field the following notation is used Table 5 2 CPO Register Field Types Read Write Notation Hardware Interpretation Software Interpretation R W A field in which all bits are readable and writable by software and potentially by hardware Hardware updates of this field are visible by software reads Software updates of this field are visi ble by hardware reads If the reset state of this field is Undefined either software or hardware must initialize the value before the first read will return a predictable value This should not be confused with the formal definition of UNDEFINED behavior MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 2 CPO Register Field Types Continued Read Write Notation Hardware Interpretation Software Interpretation R A field that is either static or is updated only by A field to which the value written by software is hardware ignored by hardware Software may write any If the Reset State of this field is either O or value to this field without affecting hardware Preset hardware initializes this field to zero or behavior Software reads of this field return the to the appropriate state respectively on pow last value updated by hardware erup If the
38. lowing instruction sees the enabled state and reacts accordingly 8 3 3 Usage of Pass Counters Pass counters specify that the breakpoint conditions must match N times before the breakpoint action will be enabled e Controlled by writing to the per breakpoint pass counter register e Resets to 0 e Writing to a non zero value enables the pass counter When enabled each time the breakpoint conditions match the counter will be decremented by 1 After the counter value reaches 0 the breakpoint action breakpoint excep tion trigger or complex break enable will occur on any subsequent matches and the counter will not decrement further The action does not occur on the match that causes the 1 20 counter decrement e Ifthe breakpoint also has priming conditions and or data qualified specified the pass counter will only decre ment when the priming and or qualified conditions have been met e fa data breakpoint is configured to be a tuple breakpoint the data pass counter will only decrement on instruc tions where both the instruction and data break conditions match The pass counter for the instruction break involved in a tuple should not be enabled if the tuple is enabled e Once a pass counter has been enabled it will be treated as enabled until the pass counter is explicitly written to 0 Namely breakpoint exceptions will continue to be taken imprecisely until the pass counter is disabled by writing to 0 e The counter register will be upd
39. rnadexBit Index Addrtngexpit 1 0ffsetBit Figure 10 1 Usage of Address Fields to Select Index and Way uS IndexBit 5 OffsetBit 0 A TLB Refill and TLB Invalid both with cause code equal TLBL exception can occur on any operation For index operations where the address is used to index the cache but need not match the cache tag software should use unmapped addresses to avoid TLB exceptions This instruction never causes TLB Modified exceptions nor TLB Refill exceptions with a cause code of TLBS The effective address may be an arbitrarily aligned by address The CACHE instruction never causes an Address Error Exception due to an non aligned address A Cache Error exception may occur as a by product of some operations performed by this instruction For example if a Writeback operation detects a cache or bus error during the processing of the operation that error is reported via a Cache Error exception Similarly a Bus Error Exception may occur if a bus operation invoked by this instruction is MIPS32 M4K Processor Core Software User s Manual Revision 02 03 217 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Perform Cache Operation terminated in an error However cache error exceptions must not be triggered by an Index Load Tag or Index Store tag operation as these operations are used for initialization and diagnostic purposes Bits 17 16 of the instruction specify the cache on whi
40. rt 5 bit target source destination register or branch condition immediate 16 bit immediate value branch displacement or address displacement target 26 bit jump target address rd 5 bit destination register specifier sa 5 bit shift amount funct 6 bit function field 9 2 Load and Store Instructions 9 2 1 Scheduling a Load Delay Slot A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction The instruction slot immediately following this delayed load instruction is referred to as the load delay slot In a M4K core the instruction immediately following a load instruction can use the contents of the loaded register however in such cases hardware interlocks insert additional real cycles Although not required the scheduling of load delay slots can be desirable both for performance and R Series processor compatibility 9 2 2 Defining Access Types Access type indicates the size of a core data item to be loaded or stored set by the load or store instruction opcode Regardless of access type or byte ordering endianness the address given specifies the low order byte in the addressed field For a big endian configuration the low order byte is the most significant byte for a little endian con figuration the low order byte is the least significant byte 204 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 M
41. see comment under ProbEn bit The ProbTrap should not be set to 1 for debug exception vector in EJTAG memory unless the ProbEn bit is also set to 1 to indicate that the EJTAG memory may be accessed The read value indicates the effective value to the CPU due to synchronization issues between T CK and CPU clock domains however it is ensured that change of the ProbTrap bit prior to setting the EjtagBrk bit will have effect for the EjtagBrk The reset value of the bit depends on whether the EJTAG BOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 Res reserved R 0 164 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Table 8 30 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State EjtagBrk EJTAG Break Oor 1 Setting this bit to 1 causes a debug exception to the pro from cessor unless the CPU was in debug mode or another EJTAGBOOT debug exception occurred When the debug exception occurs the processor core clock is restarted if the CPU was in low power mode This bit is cleared by hardware when the debug exception is taken The reset value of the bit depends on whether the EJTAG BOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 Res
42. such as a divide to be partially masked by system stalls and or other integer unit instructions The MDU consists of a 32x16 booth encoded multiplier array a carry propagate adder result accumulation registers HI and LO multiply and divide state machines and all necessary multiplexers and control logic The first number shown 32 of 32x16 represents the rs operand The second number 16 of 32x16 represents the rt operand The core only checks the latter rt operand value to determine how many times the operation must pass through the mul tiplier array The 16x16 and 32x16 operations pass through the multiplier array once A 32x32 operation passes through the multiplier array twice The MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorithm with an early in detection of sign exten sion on the dividend rs Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights r
43. urable based on control and status registers This allows the interrupt controller to be more specific or more general as a function of the system environment and needs The external interrupt controller prioritizes its interrupt requests and produces the priority level and vector number of the highest priority interrupt to be serviced The priority level called the Requested Interrupt Priority Level RIPL is a 6 bit encoded value in the range 0 63 inclusive A value of 0 indicates that no interrupt requests are pending The values 1 63 represent the lowest 1 to highest 63 RIPL for the interrupt to be serviced The interrupt controller passes this value on the 6 hardware interrupt lines which are treated as an encoded value in EIC interrupt mode The vector number that the interrupt should be serviced with is also passed to the core Statusypy which overlays Status m2 is interpreted as the Interrupt Priority Level IPL at which the processor is currently operating with a value of zero indicating that no interrupt is currently being serviced When the interrupt controller requests service for an interrupt the processor compares RIPL with Status p to determine if the requested interrupt has higher priority than the current IPL If RIPL is strictly greater than Sfatus p and interrupts are enabled Statusy 1 Statusgyx 0 and Statusgg 0 an interrupt request is signaled to the pipeline When the processor starts the interrupt ex
44. 0 0 21 16 7 1 0 Table 5 13 Cause Register ExcCode Field Exception Code Value Decimal Hexadecimal Mnemonic Description 0 16 00 Int Interrupt 1 3 16 00 16 03 Reserved 4 16 04 AdEL Address error exception load or instruction fetch MIPS326 M4K Processor Core Software User s Manual Revision 02 03 101 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Table 5 13 Cause Register ExcCode Field Continued Exception Code Value Decimal Hexadecimal Mnemonic Description 5 16 05 AdES Address error exception store 6 1606 IBE Buserrorexception instruction fetch 7 16 07 DBE Bus error exception data reference load or store 8 16 08 Sys Syscall exception 9 16809 Bp Breakpointexception 10 16 0a RI Reserved instruction exception 11 16 0b CpU Coprocessor Unusable exception nm 16 0 Ov Arithmetic Overflow excepion 13 16 0d Tr Trap exception 14 15 16 0e 16 0f Reserved 16 1680 IS Implementation Specific Exception I COP2 17 16511 CEU CorExtend Unusable 18 16412 C2E Coprocessor 2 exceptions 19 31 1683268f Reserved 5 2 10 Exception Program Counter CPO Register 14 Select 0 The Exception Program Counter EPC is a read write register that contains the address at which processing resumes after an exception has been serviced
45. 1 Implementation Dependent Code 100000 6 1 19 6 Format WAIT MIPS32 Purpose Enter Standby Mode Wait for Event Description The WAIT instruction forces the core into low power mode The pipeline is stalled and when all external requests are completed the processor s main clock is stopped The processor will restart when reset S Reset or SI ColdHeset is signaled or a non masked interrupt is taken S NMI SI Int or EJ DINT Note that the M4K core does not use the code field in this instruction If the pipeline restarts as the result of an enabled interrupt that interrupt is taken between the WAIT instruction and the following instruction EPC for the interrupt points at the instruction following the WAIT instruction Restrictions The operation of the processor is UNDEFINED if a WAIT instruction is placed in the delay slot of a branch or a jump If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled Operation I Enter lower power mode I 1 Potential interrupt taken here Exceptions Coprocessor Unusable Exception MIPS32 M4K Processor Core Software User s Manual Revision 02 03 227 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 228 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 11 MIPS16e Application Specific Extension to the MIPS32 Instruction S
46. 10 Register Reset SIdIOs rods pepea dicii Sitom deem bucEdneniu sin dddu atas it enin d nrtaasee i ftd Lares 193 812 EJT AG Trace Enablifigs e eo teta e rat tice etiara ret ote ri rreeer reer rr Ls ce ENT eer terre rrr 194 8 12 1 Trace Trigger from EJTAG Hardware Instruction Data Breakpoints ssssssss 194 812 2 Turhing OMP Drace M TaGC Enraiar iaa aara ae 194 8 12 39 Turning Olt PDtrace M TraCE siine E E EAE 195 ad24 TGB Tace Enabling rean A AEEA ES 196 2125 Tacng a Resor EOS plOu cored Leite PO ME petedadied obi ep CLOS gU ieledegee ce 196 5 13 TOB Trigger OGG soccer voccm credite sced er up excu aki go rode xe n iiaae becas any e AETR 197 8 13 1 moger Unis OVS WOW ii dace terit andre Dar n a aste x uc Exec fd eds E tease dep UTR u E d ERS 197 mese MOJEr SOUS ll ememere C 198 8 19 9 Trigger Gontrol DD oit o eoe SE REIS e RUPEE RISE Sides Ur natadetaa Octo in eteieeeab accede 198 Sm EE sarei ACTON erp e S 198 8 19 5 Simultaneous TTIBOOIS asiste teca patio a a tiet en usas etate D prisdad un DI p aM Ades 198 8 14 EJTAG Trace Gycle by Gycle BeliaViOf sace us tis aeta pe e dto s EE E osxe E tana tei aus eec e fasce ENTRIES 199 8 14 1 Fito Logic in PDtrace and TOB Modules inre nto tete ab een bac ebe o v xbE E ated 199 8 14 2 Handling of Fifo Overflow in the PDtrace Module ssssseeeeeenneeeenenennnn nnn 200 8 14 9 Handling of Fito Overflow im the TOBus eoe die edere a 200 8 14 4 Adding
47. 10 8 COPO Encoding of rs Field Table 10 9 COPO Encoding of Function Field When rs CO function bits 2 0 bits 5 3 000 0 1 2 3 4 5 6 7 10 3 MIPS32 Instruction Set for the M4K core This section describes the MIPS32 instructions for the M4K cores Table 10 10 lists the instructions in alphabetical order Instructions that have implementation dependent behavior are described afterwards The descriptions for other instructions exist in the architecture reference manual and are not duplicated here Table 10 10 Instruction Set Instruction Description Function ADD Integer Add Rd Rs Rt ADDI Integer Add Immediate Rt Rs Immed ADDIU Unsigned Integer Add Immediate Rt Rs y Immed ADDU Unsigned Integer Add Rd Rs y Rt AND Logical AND Rd Rs amp Rt ANDI Logical AND Immediate Rt Rs amp 046 Il Immed B Unconditional Branch PC int offset Assembler idiom for BEQ 10 r0 offset BAL Branch and Link GPR 31 PC 8 Assembler idiom for BGEZAL 10 offset PC int offset BC2F Branch On COP2 Condition False if COP2Condition cc 0 PC int offset 210 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M4K core Table 10 10 Instruction Set Continued
48. 16 0380 16 0500 16 0800 16 0E00 7 16 02E0 16 03C0 16 0580 16 0900 16 1000 61 16 09A0 16 1140 16 2080 16 3F00 16 7C00 62 16 09CO 16 1180 16 2100 16 4000 16 7E00 63 16 09E0 16 11C0 16 2180 16 4100 16 8000 The general equation for the exception vector offset for a vectored interrupt is MIPS32 M4K Processor Core Software User s Manual Revision 02 03 65 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core vectorOffset lt 164200 vectorNumber x IntCtlyg 2 00000 When using large vector spacing and EIC mode the offset value can overlap with bits that are specified in the EBase register Software must ensure that any overlapping bits are specified as 0 in EBase This implementation ORs together the offset and base registers but it is architecturally undefined and software should not rely on this behavior 4 4 GPR Shadow Registers 66 Release 2 of the Architecture optionally removes the need to save and restore GPRs on entry to high priority inter rupts or exceptions and to provide specified processor modes with the same capability This is done by introducing multiple copies of the GPRs called shadow sets and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception The normal GPRs are logically considered shadow set zero The number of GPR shadow sets is a bui
49. 2 23 Debug Exception Program Counter Register CPO Register 24 Select 0 5 2 24 ErrorEPC GPO Register 30 Select 0 eres tar soc ARES 5 2 25 DeSave Register GPO Register dil Select 0 iere t ere E ornare tea esee i eai Chapter 6 Hardware and Software Initialization of the M4K Core 6 1 Hardware Initialized Processor State sssssseeeeenenenneneme menn nnnnn nnn nnne nennen sm EKGroIo oec crim e T E 61 2 BUS State MACHINES encanar erae dpa sirve Lee varese ea icd Eod pure rfe aer 5 1 3 Static Configuration Inpulssssas iei iouis eoo nee aecpideivlas ae es Us Ia ee ed Unc OE A Cle FOI Address cescsctescedaacancatantcatexaaceactueincs hagnsaaaiudaaualaditaauaGiaadaacntantwabacmnatecasauamenaatuadstanandicieimealantananne 6 2 Software Initialized Processor Stale c iri rti pbi t Peto tr ese rica pane deicjaaaeaviaadga eviasa FE aN p 2 d ROIS UC FUE usciti Street ian E oes erecta et ce a suc tiras 6 2 2 Coprocessor O Stale isrann tentis timi eden H Eo Eedv tai N deleted e rob PE Ro S Chapter 7 Power Management of the M4K Core eseeeeeeeeeeeeee eene nnne nnne nnn 7 15 Regist r Gontrolled Power Management oor coire teinte tero tere but caca ate one rubrique d ane 1 2 Instruction Controlled Power Management ictor ipeo eode sebaed ettet eco ed ede Seda sede ee iv adenine Chapter 8 EJTAG Debug Support in t
50. 2002 2008 MIPS Technologies Inc All rights reserved 2 1 Pipeline Stages 2 1 2 E Stage Execution During the Execution stage e Operands are fetched from the register file e Operands from the M and A stage are bypassed to this stage e The Arithmetic Logic Unit ALU begins the arithmetic or logical operation for register to register instructions e The ALU calculates the data virtual address for load and store instructions and the MMU performs the fixed vir tual to physical address translation e The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions e Instruction logic selects an instruction address and the MMU performs the fixed virtual to physical address translation e All multiply divide operations begin in this stage 2 1 3 M Stage Memory Fetch During the Memory Fetch stage e The arithmetic or logic ALU operation completes e The data SRAM access is performed for load and store instructions e A 16x16 or 32x16 MUL operation completes in the array and stalls for one clock in the M stage to complete the carry propagate add in the M stage high performance MDU option e A 32x32 MUL operation stalls for two clocks in the M stage to complete the second cycle of the array and the carry propagate add in the M stage high performance MDU option e A multiply operation stalls the MDU pipeline for 31 cycles in the M stage area efficient MDU option
51. All rights reserved 215 M4K Processor Core Instructions Table 10 10 Instruction Set Continued Instruction Description Function XOR Exclusive OR Rd Rs Rt XORI Exclusive OR Immediate Rt Rs uns Immed 216 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Perform Cache Operation CACHE 31 26 25 21 20 16 15 0 CACHE 101111 base op offset 6 5 5 16 Format CACHE op offset base MIPS32 Purpose Perform Cache Operation To perform the cache operation specified by op Description CACHE is always treated as a NOP on the M4K core as long as access to Coprocessor 0 is enabled since it does not contain caches The 16 bit offset is sign extended and added to the contents of the base register to form an effective address The effective address is used in one of the following ways based on the operation to be performed and the type of cache as described in the following table Table 10 1 Usage of Effective Address Operation Requires an Usage of Effective Address Assuming that the total cache size in bytes is CS the associativity is A and the number of bytes per tag is BPT the following calculations give the fields of the address which specify the way and the index OffsetBit Log2 BPT IndexBit lt Log2 CS A WayBit lt IndexBit Ceiling Log2 A Way lt AdGrwaysit i
52. Branch INStUCTIONS s coii ec edo eoa A eb c eres Gero eixibx ee LR i NN 206 25 Gonitl InetfetlOf T8 sacas taco cuo pao eric a DURER ubi o reU exu Md cT Las cU dub te tos UIS gum ELE 206 9 6 Goprocessor NSIUCHONS csi eec ideato a a Ade Renta lee ete eda 206 Chapter 10 M4K Processor Core Instructions eeeeeeeeeeeeee eene 207 10 1 Understanding the Instruction Descriptions nnns 207 10 2 MAK Opcode ro m 207 10 32 MIPS32 Instr ction Set tor the MAKI GOETG era actora pitur rer x redo teer rt A E EENES 210 CACHE arren n A N A 217 E RA EE T ETAO A T AE E UEM A E N E E E T TA 220 PREF can a sede ind pecs a dc etre eee ei 222 E EAA ar ee Cn ae re eer rete erty URS ERE 224 ING sae ER 226 rU I 227 Chapter 11 MIPS16e Application Specific Extension to the MIPS32 Instruction Set 229 10 35 Miste ction Bit ENCON iieri erii ehe tipa eaep tco ode scene Pas Ed ue du ipu adde KE em cix UBds 229 T3 2 Instit on EISE DICES ss ae reetereene aterm A er ert tern eter rs etree rrr rererrrr gerenstrrcercerrerree tren crt 232 Appendix A Revision HISIONy wasiciscsssactncecesscccssscicacencsssanecendesinunescoccanenteananestevensecwasenecasieesctanestanenionces 235 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 7 Copyright 2002 2008 MIPS Technologies Inc All rights reserved List of Figures Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5
53. Break Store Undefined exception was taken Imprecise data breaks only occur on complex breakpoints DDBLImpr Indicates that an imprecise Debug Data Break Load Undefined exception was taken Imprecise data breaks only occur on complex breakpoints Ver EJTAG version 010 DExcCode Indicates the cause of the latest exception in debug Undefined mode The field is encoded as the ExcCode field in the Cause register for those normal exceptions that may occur in debug mode Value is undefined after a debug exception Indicates whether the single step feature controllable by the SSt bit is available in this implementation 0 Single step feature available 1 No single step feature available R Controls if debug single step exception is enabled 0 No debug single step exception enabled 1 Debug single step exception enabled Reserved Must be written as zeros returns zeros on reads DIBImpr Indicates that an Imprecise debug instruction break Undefined exception occurred due to a complex breakpoint Cleared on exception in debug mode Indicates that a debug interrupt exception occurred Undefined Cleared on exception in debug mode 0 No debug interrupt exception 1 Debug interrupt exception MIPS32 M4K Processor Core Software User s Manual Revision 02 03 111 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Table 5 21 Debug Registe
54. Config is set This bit will read as 0 if no coprocessor is present CUI 29 Controls access to Coprocessor 1 COPI is not supported R 0 This bit cannot be written and will read as 0 CUO 28 Controls access to coprocessor 0 R W Undefined 0 access not allowed 1 access allowed Coprocessor 0 is always usable when the processor is run ning in kernel mode independent of the state of the CUO bit RP 27 Enables reduced power mode The state of the RP bit is R W 0 for Cold available on the external core interface as the S _AP sig Reset only nal FR 26 This bit is related to floating point registers Since the M4K R 0 core does not contain a floating point unit this bit is ignored on write and read as zero RE 25 Used to enable reverse endian memory references while R W Undefined the processor is running in user mode Encoding Meaning 0 User mode uses configured endianness 1 User mode uses reversed endianness Neither Debug Mode nor Kernel Mode nor Supervisor Mode references are affected by the state of this bit R 24 23 Reserved This field is ignored on write and read as 0 R 0 90 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 7 Status Register Field Descriptions Continued
55. Control Unit 7 Trigger Control Unit 1 Trigger Control Unit 0 Priority OR function Depending on the trigger action the Action strobes must pass through a priority function or an OR gate P riority OR function Trigger Action Unit MIPS32 M4K Processor Core Software User s Manual Revision 02 03 197 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 198 8 13 2 Trigger Source Unit The TCB has three trigger sources 1 Chip level trigger input TC_ChipTrigIn 2 Probe trigger input TR_TRIGIN 3 Debug Mode DM entry indication from the processor core The input triggers are all rising edge triggers and the Trigger Source Units convert the edge into a single cycle strobe to the Trigger Control Units 8 13 3 Trigger Control Units Up to eight Trigger Control Units are possible Each of them has its own Trigger Control Register TCBTRIGx X 0 7 Each of these registers controls the trigger fire mechanism for the unit Each unit has all of the Trigger Sources as possible trigger event and they can fire one or more of the Trigger Actions This is all defined in the Trig ger Control register TCBTRIGx see 8 11 9 TCBTRIGx Register Reg 16 23 on page 191 8 13 4 Trigger Action Unit The TCB has four possible trigger actions 1 Chip level trigger output TC ChipTrigOul 2 Probe trigger output TR_TRIGOUT 3 Trace information
56. Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 17 Introduction to the MIPS32 M4K Processor Core ok e Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation e Loadaligner e Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results e Zero One detect unit for implementing the CLZ and CLO instructions e ALU for performing bitwise logical operations e Shifter and Store aligner 2 1 2 Multiply Divide Unit MDU The Multiply Divide unit performs multiply divide operations Two configuration options exist for the MDU select able at build time an area efficient iterative MDU and a higher performance 32x16 array The MDU consists of an iterative or32x16 multiplier result accumulation registers HI and LO multiply and divide state machines and all multiplexers and control logic required to perform these functions The high performance pipelined MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply opera tions Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clo
57. Cycle Accurate Information to the Trace ssssssssseseseeeeennen nnns 201 8 15 TGB On CRhipIrace Memon y suse tees pet ted o a rest dum ot tO du PO Ea 201 8 154 On Ghip Trace MEMORY SIZe occi proci omee th os pece xu tbe o ddia aana aia 201 MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 835 2 Trace From MOGDG inea nena te Pobre vas EE brennt bro eee Ede ardore era d ete 202 B O38 c r 202 Chapter 9 Instruction Set Overview aos cas soe a anced g nrc o ccc eset an enn nne kta nca eran an eae Ree 203 9 4 CPU Instruction Formals cuc reactive s ix be i EIEPrcee etra dO o me iix bla Maroon essai ti dia pix te Saxa rei Lau PER Iud dde 203 9 2 Load and Store IRStFUCUOTIS udo asus caede ttes toe t a Ux as cT e Sax Rd epa DR a ei 204 92 3 Scheduling a load Delay Sob ie Ro Reni deer bd DUd Ala PRESE Hide Riedel a 204 92 2 Benning ACCESS TVDOS ctt ette tesoro e deere iene eset e ease tu tos 204 9 9 Computational IMSHUGCHGMS 5 ead ieeso eid edo a ee beaebiodptet ese tedu E P E 205 9 3 1 Cycle Timing for Multiply and Divide Instructions sssssseseeeenemeenn n 206 9 4 Jump and Branch Instft elionms ssscica odes cessor eode creen A nte Piae tacente ripe Dd S ocu PACEM Irem eaves 206 9 41 Overview Ol JUMPS TMICHONS cash ito sonet a con tex e etii Ree quidein ted ut aeebde 206 9 4 2 Overview Of
58. DERET are instructions which have an unpredictable target address These will have full delta PC values included in the trace information Also treated as unpredictable are PC changes which occur due to exceptions such as an interrupt reset etc Trace regeneration software is required to know the static program image in memory in order to reproduce the dynamic flow with the above information But this is usually not a problem Only the virtual value of the PC is used Physical memory location will typically differ Itis possible to turn on PC delta full information for all branches but this should not normally be necessary As a safety check for trace regeneration software a periodic synchronization with a full PC is sent The period of this syn chronization is cycle based and programmable 8 9 4 Load Store Address and Data Trace Information In addition to PC flow it is possible to get information on the load store addresses as well as the data read written When enabled the following information is optionally added to the trace e When load address tracing is on the full load address of the first load instruction is traced indicated by the load flag For subsequent loads a dynamically determined delta to the previous load address is traced to com press the information which must be sent When store address tracing is on the full store address of the first store instruction is traced indicated by the store flag For subsequ
59. Descriptions ssssssssssssssessseeeeenee nennen nnne nene nennen 98 Table 5 12 Cause Register Field DescfiptlOng uuia ort eerte dine n rri ee tex rapere aie RAEN 99 Table 5 19 Cause Register ExcGode Fic vases reet irr eise ancaugesnvecdesduanyadnad a E ds CHR SEEN QAM UNA 101 Table 5 14 EPC Register Field Descriptio iade ood esee bete epu eto ecen ende aA ta dax t iE esee ee 103 Table 5 15 PRId Register Field Descriptions ucro sacer xcs etta petu adipe sepe ento bepoaste tuens bube n dep E ei Pu RUMP asegeece 103 Table 5 16 EBase Register Field Descriptors oorr Erat ornata da eec ia rr pex inrecectenpeeccceeiees 104 Table 5 17 Cache Coherency ATTIDUELOS cuiii sittar aaa a duce epe ees dM d EpUF I ERE DAS 106 Table 5 18 Config Register Field Descriptions Select 1 esssssssssseseseeeeeeeneenn nne 106 Table 5 20 Configs Register Field Descripliolis ncc coii ettet a aa 108 Table 5 19 Config Register Field Descriptions Select 1 0 2 ee ceeeeccceceeeeeeeeeeeeeeeeeeeeeeeeeceeeeseaaeseeeeeeesaeeneeneeess 108 10 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Table 5 21 Debug Register Field DescripliOriS aao retire eter t aperte E emer cix egere Ra ALE PIRE UR 110 Table 5 22 TraceControl Register Field Descriptions sssisss osiossa a nnne 112 Table 5 23 TraceControl2 Register Field Descriptions
60. Figure 2 6 MAK Processor Core Block Digian serinin ona a RE NN NEA 17 Address Translation During a SRAM ACCESS ceescecceteceeenceeeeeeeeeneeeeaeeeeeaaeeeeaeeeesaaessneeeeesaeeseeneeess 19 M4K Core Pipeline Stages with high performance MDU sssseemeeenns 24 M4K Core Pipeline Stages with area efficient MDU seems 24 MDU Pipeline Behavior During Multiply Operations sse 28 MDU Pipeline Flow During a 32x16 Multiply Operation sssseeeeemenenn n 29 MDU Pipeline Flow During a 32x32 Multiply Operation sessseeeneennnns 30 High Performance MDU Pipeline Flow During a 8 bit Divide DIV Operation sssses 30 Figure 2 7 High Performance MDU Pipeline Flow During a 16 bit Divide DIV Operation 30 Figure 2 8 High Performance MDU Pipeline Flow During a 24 bit Divide DIV Operation 31 Figure 2 9 High Performance MDU Pipeline Flow During a 32 bit Divide DIV Operation 31 Figure 2 10 M4K Area Efficient MDU Pipeline Flow During a Multiply Operation seeeeeeesss 32 Figure 2 11 M4KC Area Efficient MDU Pipeline Flow During a Multiply Accumulate Operation de Figure 2 12 M4K Area Efficient MDU Pipeline Flow During a Divide DIV Operation
61. MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 5 2 8 SRSMap Register CPO Register 12 Select 3 Table 5 10 Sources for new SRSCtlcess on an Exception or Interrupt Exception Al SRSuss Exception SRSCtlgss Non Vectored Inter Causejy 0 SRSCtlgss Treat as exception rupt Vectored Interrupt Causeyy 1 and SRSMapygernum Source is internal map register Config3ypic 0 and for VECTNUM see Table 4 3 Config3yjnt 1 Vectored EIC Inter Causeyy 1 and SRSCtlgicss Source is external interrupt con rupt Config3ypic 1 troller The SRSMap register contains 8 4 bit fields that provide the mapping from an vector number to the shadow set num ber to use when servicing such an interrupt The values from this register are not used for a non interrupt exception or a non vectored interrupt Causejy 0 or IntCtlys 0 In such cases the shadow set number comes from SRSCtless If SRSCtlyssis zero the results of a software read or write of this register are UNPREDICTABLE The operation of the processor is UNDEFINED if a value is written to any field in this register that is greater than the value of SRSCitlyss The SRSMap register contains the shadow register set numbers for vector numbers 7 0 The same shadow set num ber can be established for multiple interrupt vectors creating a many to one mapping from a vector to a single shadow register set number Figure 5 8 shows the format of
62. MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 30 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State ProbEn Probe Enable R W Oor 1 This bit indicates to the CPU if the EJTAG memory is from handled by the probe so processor accesses are answered EJTAGBOOT 0 The probe does not handle EJTAG memory transac tions 1 The probe does handle EJTAG memory transactions It is an error by the software controlling the probe if it sets the ProbTrap bit to 1 but resets the ProbEn to 0 The operation of the processor is UNDEFINED in this case The ProbEn bit is reflected as a read only bit in the ProbEn bit bit 0 in the Debug Control Register DCR The read value indicates the effective value in the DCR due to synchronization issues between TCK and CPU clock domains however it is ensured that change of the ProbEn prior to setting the EjtagBrk bit will have effect for the debug handler executed due to the debug excep tion The reset value of the bit depends on whether the EJTAG BOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 ProbTrap Probe Trap R W Oor 1 This bit controls the location of the debug exception vec from tor EJTAGBOOT 0 In normal memory 0xBFC0 0480 1 In EJTAG memory at OxFF20 0200 in dmseg Valid setting of the ProbTrap bit depends on the setting of the ProbEn bit
63. Must be written as zero returns zero on read R 0 Data breakpoint ASID value for compares 8 2 8 5 Data Breakpoint Control n DBCn Register 0x2118 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Control n DBCn register controls the setup of data breakpoint n DBCn Register Format 31 24 23 22 18 17 14 13 12 11 8 7 4 3 2 1 0 Re AstDuse Res BAI NoSB NoLB Res BLM Res TE iv BE 140 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 15 DBCn Register Field Descriptions Fields Name Bits Description Read Write Reset State Res 31 24 Must be written as zero returns zero on reads R 0 ASIDuse 23 Use ASID value in compare for data breakpoint n R 0 0 Don t use ASID value in compare 1 Use ASID value in compare Res 22 18 Must be written as zero returns zero on reads R 0 BAI 17 14 Byte access ignore controls ignore of access to a specific R W Undefined byte BAI 0 ignores access to byte at bits 7 0 of the data bus BAI 1 ignores access to byte at bits 15 8 etc 0 Condition depends on access to corresponding byte 1 Access for corresponding byte is ignored NoSB 13 Controls if condition for data breakpoint is not fulfilled R W Undefined on a store transaction 0 Condition may be fulfilled on store tr
64. Probe interface works in double data rate DDR mode a 1 2 ratio indicates one data packet sent per core clock rising edge This bit is reserved if off chip trace option is not implemented MIPS32 M4K Processor Core Software User s Manual Revision 02 03 185 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 186 Table 8 40 TCBCONTROLB Register Field Descriptions Continued Fields Name Bits Description Read Wr ite Reset State Cal 7 6 3 Calibrate off chip trace interface If set to one the off chip trace pins will produce the following pattern in consecutive trace clock cycles If more than 4 data pins exist the pattern is replicated for each set of 4 pins The pattern repeats from top to bottom until the Cal bit is de asserted Calibrations pattern 4 bits of TR DATA pins nr FH i IE gt o 2 o LJ o 2 vo o g 2 2 D E c s o 2 2 c i Note The clock source of the TCB and PIB must be running This bit is reserved if off chip trace option is not implemented Reserved Must be written as zero returns zero on read R W 0 CA OfC Cycle accurate trace When set to 1 the trace will include stall information When set to 0 the trace will exclude stall information and remove bit zero from all transmi
65. Rs int Rt MFCO Move From Coprocessor 0 Rt CPR O n sel MFC2 Move From Coprocessor 2 Rt CPR 2 n sels 9 MFHC2 Move From High Word Coprocessor2 Rt CPR 2 n sel gs 3 MFHI Move From HI Rd HI MFLO Move From LO Rd LO MOVN Move Conditional on Not Zero if GPR rt 4 0 then GPR rd GPR rs MOVZ Move Conditional on Zero if GPR rt 0 then GPR rd GPR rs MSUB Multiply Subtract HI LO int Rs int Rt MSUBU Multiply Subtract Unsigned HI LO uns Rs uns Rt MTCO Move To Coprocessor 0 CPR O n sel Rt MTC2 Move To Coprocessor 2 CPR 2 n sel 3 9 Rt MTHC2 Move To High Word Coprocessor 2 CPR 2 n sel g3_ 32 Rt MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 213 M4K Processor Core Instructions Table 10 10 Instruction Set Continued Instruction Description Function MTHI Move To HI HI Rs MTLO Move To LO LO Rs MUL Multiply with register write HI LO Unpredictable Rd LO MULT Integer Multiply HI LO int Rs int Rd NOP No Operation Assembler idiom for SLL r0 r0 r0 NOR Logical NOR Rd Rs Rt OR Logical OR Rd zRsIRt ORI Logical OR Immediate Rt Rs Immed PREF Prefetch Nop RDHWR Read HardWare Register Rt HWR Rd RDPGPR Read GPR from Previous Shadow Set Rd SGPR SRSCtlpgg Rt ROTR Rotate Word Right Rd Rt 4 0 ll Rt sa ROTRV Rotate Word Rig
66. Rs 31 PC int offset MIPS32 M4K Processor Core Software User s Manual Revision 02 03 211 Copyright 2002 2008 MIPS Technologies Inc All rights reserved M4K Processor Core Instructions Table 10 10 Instruction Set Continued Instruction Description Function BLTZALL Branch on Less Than Zero And Link Likely GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction BLTZL Branch on Less Than Zero Likely if Rs 31 PC int offset else Ignore Next Instruction BNE Branch on Not Equal if Rs Rt PC int offset BNEL Branch on Not Equal Likely if Rs Rt PC int offset else Ignore Next Instruction BREAK Breakpoint Break Exception CACHE Cache Operation See Cache Description CFC2 Move Control Word From Coprocessor 2 Rt CCR 2 n CLO Count Leading Ones Rd NumLeadingOnes Rs CLZ Count Leading Zeroes Rd NumLeadingZeroes Rs COPO Coprocessor 0 Operation See Coprocessor Description COP2 Coprocessor 2 Operation See Coprocessor 2 Description CTC2 Move Control Word To Coprocessor 2 CCR 2 n Rt DERET Return from Debug Exception PC DEPC Exit Debug Mode DI Disable Interrupts Rt Status Status p 0 DIV Divide LO int Rs int Rt HI int Rs int Rt DIVU Unsigned Divide LO uns Rs uns Rt HI uns Rs uns Rt EHB Execution Hazard Barrier Stall until execution hazards are cleared EI Enable Interrupts Rt Status
67. SASMap Register CPO Register 12 Select8 iie ierit acne die eoe sa ERR nee 98 5 2 9 Cause Register CPO Register 19 Select 0 cus ette sieh esed doa sucer siete sre etra teda d 99 5 2 10 Exception Program Counter CPO Register 14 Select 0 sss 102 5 2 11 Processor Identification CPO Register 15 Select 0 103 5 212 EBase Register CPO Register 15 Select 1 tenia hr Haste Pere et ers 104 5 2 13 Config Register CPO Register 16 Select 0 ee recidere eire er no Posee reda duree 105 5 2 14 Contig Register CPO Register 16 Select 1 eei eo eoe eot eb eei theese 106 5 2 15 Config2 Register CPO Register 16 Select 2 107 5 2 16 Contigs Register CPO Register 16 Select 3 iota terit tenis 108 5 2 17 Debug Register CPO Register 23 Select 0 sessssssssssssseee nennen nenas 109 5 2 18 Trace Control Register CPO Register 23 Select 1 eere ertet etie dea kr s era bera 112 4 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 19 Trace Control2 Register CPO Register 23 Select 2 0 0 cccecesceceeeeeseneeeeeeeeeeeaeeeeeeeeeeaeeneneeeess 5 2 20 User Trace Data Register CPO Register 23 Select 3 5 2 21 TraceBPC Register CPO Register 23 Select 4 cite reet eese de nieeiecerteeds 5 2 22 Debug2 Register CPO Register 23 Select 6 sssssssssssssssseseeeeeennen nnns 5
68. Select Chip Identification data register 0x03 Select Implementation register 0x08 ADDRESS Select Address register 0x09 DATA Select Data register 0x0A CONTROL Select EJTAG Control register 0x0B ALL Select the Address Data and EJTAG Control registers 0x0C EJTAGBOOT Set EjtagBrk ProbEn and ProbTrap to 1 as reset value 0x0D NORMALBOOT Set EjtagBrk ProbEn and ProbTrap to 0 as reset value OxOE FASTDATA Selects the Data and Fastdata registers 0x10 TCBCONTROLA Selects the TCBTCONTROLA register in the Trace Control Block 0x11 TCBCONTROLB Selects the TCBTCONTROLB register in the Trace Control Block 0x12 TCBDATA Selects the TCBDATA register in the Trace Control Block Ox1F BYPASS Bypass mode 8 4 3 1 BYPASS Instruction The required BYPASS instruction allows the processor to remain in a functional mode and selects the Bypass register to be connected between TDI and TDO The BYPASS instruction allows serial data to be transferred through the pro cessor from TDI to TDO without affecting its operation The bit code of this instruction is defined to be all ones by the IEEE 1149 1 standard Any unused instruction is defaulted to the BYPASS instruction 8 4 3 2 IDCODE Instruction The IDCODE instruction allows the processor to remain in its functional mode and selects the Device Identification ID register to be connected between TD and TDO The Device ID register is a 32 bit shift register containing infor mation regarding the IC manufacturer
69. The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 10 EPC Register Format 31 0 EPC Table 5 14 EPC Register Field Description Fields Read Wri Name Bit s Description te Reset State EPC 31 0 Exception Program Counter R W Undefined 5 2 11 Processor Identification CPO Register 15 Select 0 The Processor Identification PRId register is a 32 bit read only register that contains information identifying the manufacturer manufacturer options processor identification and revision level of the processor Figure 5 11 PRid Register Format 31 24 23 16 15 8 7 5 4 2 1 0 R Company ID Processor ID Revision Table 5 15 PRId Register Field Descriptions Fields poo Read W Name Bit s Description rite Reset State R 31 24 Reserved Must be ignored on write and read as zero R 0 Company ID 23 16 Identifies the company that designed or manufactured the R 1 processor In the M4K this field contains a value of 1 to indicate MIPS Technologies Inc Processor ID 15 8 Identifies the type of processor This field allows software R 0x87 to distinguish between the various types of MIPS Technol ogies processors Revision 7 0 Specifies the revision number of the processor This field R Preset allows software to distinguish between one revision and another of the same processor type This field is broken up into the following three s
70. To mode 00 for the Type field to control on chip trace fill The write value of this bit always controls the behavior of this trig ger When this trigger fires the read value will change to indicate if the trigger action was ever suppressed If so the read value will be 11 If the write value was 11 the read value is always 11 This special read value is valid until the TCBTRIGx register is written Fire Once When set this trigger will not re fire until the TR bit is de asserted When de asserted this trigger will fire each time one of the trigger sources indicates trigger TR Trigger happened When set this trigger fired since the TR bit was last written 0 This bit is used to inspect whether the trigger fired since this bit was last written zero When set all the trigger source bits bit 4 to 13 will change their read value to indicate if the particular bit was the source to fire this trigger Only enabled trigger sources can set the read value but more than one is possible Also when set the Type field and the Trace field will have read val ues which indicate if the trigger action was ever suppressed by a higher priority trigger R WO 8 11 10 Register Reset State Reset state for all register fields is entered when either of the following occur MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 193 EJTA
71. Trace Modules in the M4K Core ssssssssessssssseseneneenne nennen nennen nnns en nensi nennen 175 Figure 6 7 TCB Trigger Processing OVOFVIGW s occisa sec ertt eter este eoe oe Leto eet EAE dadais 197 Figure 9d Instruction FONAS obtain oe inu E CUOI N 204 Figure 10 1 Usage of Address Fields to Select Index and Way sssssssseeseeneen nenne 217 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 9 Copyright 2002 2008 MIPS Technologies Inc All rights reserved List of Tables Table 2 1 MDU Instruction Latencies High Performance MDU ccccccesesceeeeeeeeeesaeeeeeeeeeeeaeseeeeeeesaeeneeaeeeeaas 27 Table 2 2 MDU Instruction Repeat Rates High Performance MDU ccccccceeeeeeeeeeeeeeeeeeeeeaeeeceeeeeseaeeeeeaeeteaas 28 Table 2 3 M4K Core Instruction Latencies Area Efficient MDU ccccccseeseeeeeeeeeeeeeeeeeeeeaeeeseeeeeseaeeeeeeeeeaas 31 Table 2 4 Pipeline InterlOCKS oes eines d a INANE QN s Rede Ad Re AMAN EPUM ed A DRE ES ERE UR MA pi ReER IR dU xS dER 37 Table 2 5 Instruction InterloGKS 2 aai rotta preter AEA itae PER Ree ea bere kV peret I SERES nuanced IMS 39 Table 2 6 Execution Pazalts uino tope do eR eO RE Pati Aa E EDS Rd fat nex rb OIL De ned dea 40 Table 2 7 Instruction PIazalds ucii ocior spero n proce tia brote t E xke ene gr peor ki ba oa anro Rr SERM n pec E ERR A NAKER uaa 40 Table 2 8 Hazard Instruction LISUFIQ s sacco Rasen On ado
72. Trace enabling and disabling from software is similar to the hardware method with the exception that the bits in the control register are used instead of the input enable signals from the TCB The TraceControlzg bit controls whether hardware via the TCB or software via the TraceControl register controls tracing functionality Trace is turned on when the following expression evaluates true TraceControlpg and TraceControlg or not TraceControlpg and TCBCONTROLAg and MatchEnable or TriggerEnable where MatchEnable c TraceControl s and TraceControly and UserMode or TraceControly and KernelMode or TraceControlg and ExceptionMode or TraceControly and DebugMode MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 12 EJTAG Trace Enabling or not TraceControl g and TCBCONTROLA and UserMode or TCBCONTROLA and KernelMode or TCBCONTROLA and ExceptionMode or TCBCONTROLAgy and DebugMode and where TriggerEnable c DBCigg and DBSss 1 and TraceBPCpg and TraceBPCpgpon 1 or IBCigg and IBSgs i and TraceBPCig and TraceBPCigponji 1 As seen in the expression above trace can be turned on only if the master switch TraceControlo or TCBCONTROLAg is first asserted Once this is asserted there are two ways to turn on tracin
73. UNA t oer PEG EH Dg ee tetra Plein gute denda aM Cu EUER Eu iode 68 Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception sssssesssseeeeeeenn nne 69 Table 4 9 Debug Exception Vector Addiesses rere ees kenn ten xen es a EEA 71 Table 4 10 Register States an lInterrupt EXCODLDOT icio rt tote acted rene pi ee te acce aas 75 Table 4 11 CPO Register States on an Address Exception Error esssssssssssseseeeeneen nnns 76 Table 4 12 Register States on a Coprocessor Unusable Exception ssssssssseeeeeeeenenenn 78 Table 5 1 GPO Registers ayrisi ai a A a A A 85 Table 5 2 CPO Register Field Typos cenina ie e aa Aa A ER 86 Table 5 9 HWREna Register Field Descriptions o occ Erben aa N AEN 87 Table 5 4 BadVAdar Register Field Descriptio sssini iaoiai 88 Table 5 5 Count Register Field DescriptiOEi ccce per cczaazeussnceeldarrectacsdeavadediseincacendeeteahadeadseeguatangesce 88 Table 5 6 Compare Register Field Description ssssssssssssssssese ener enne nennen nnn 89 Table 5 7 Status Register Field DescrlpliOftsi iuret hr ei Retour S EE SEE ai 90 Table 5 8 IntCi Register Field Description S asiriarren naidaan ba eva t on Pe RR patere nnt aaaea 94 Table 5 9 SRSCt Begister Field Descriptions ueste paci sssetet cesa A 95 Table 5 10 Sources for new SRSCtless on an Exception or Interrupt ssssssseeeeen 98 Table 5 11 SRSMap Register Field
74. User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP The states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the protocol sequences The first action that occurs when either block is entered is a capture operation For the data regis ters the Capture DR state is used to capture or parallel load the data into the selected serial data path In the Instruc tion register the Capture IR state is used to capture status information into the Instruction register From the Capture states the TAP transitions to either the Shift or Exit states Normally the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in Follow ing the Shift state the TAP either returns to the Run Test Idle state via the Exit and Update states or enters the Pause state via Exit The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation such as refilling a host memory buffer is performed From the Pause state shifting can resume by re entering the Shift state via the Exit2 state or terminate by entering the Run Test Idle state via the Exit2 and Update states Upon entering the data or Instruction register scan blocks shadow latches in the selected scan path are forc
75. a TLB based MMU this register is used to define an ASID value to be used in the match expres sion On the M4K processor this register is reserved and reads as 0 IBASIDn Register Format 31 8 7 0 Res ASID Table 8 6 BASIDn Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State Res 31 8 Must be written as zero returns zero on read R 0 ASID 7 0 Instruction breakpoint ASID value for a compare R 0 8 2 7 5 Instruction Breakpoint Control n BCn Register 0x1118 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Control n BCn register controls the setup of instruction breakpoint n IBCn Register Format 31 24 23 22 3 2 1 0 BE Res ASIDuse Res TE Res Table 8 7 BCn Register Field Descriptions Description Read Write Reset State 31 24 Must be written as zero returns zero on read R ASIDuse Use ASID value in compare for instruction breakpoint n 0 Don t use ASID value in compare 1 Use ASID value in compare Must be written as zero returns zero on read R Must be written as zero returns zero on read R Use instruction breakpoint n as breakpoint 0 Don t use it as breakpoint 1 Use it as breakpoint 3 Use instruction breakpoint n as triggerpoint 0 Don t use it as triggerpoint 1 Use it as triggerpoint 136 MIPS32 M4K Processor Core Sof
76. an instruction must cause a Reserved Instruction Exception SPECIAL2 encodings or coprocessor instruction encodings for a coprocessor to which access is allowed or a Coprocessor Unusable Exception coprocessor instruction encodings for a coprocessor to which access is not allowed o Field codes marked with this symbol represent an EJTAG support instruction and implementation of this encoding is optional for each implementation If the encoding is not implemented execut ing such an instruction must cause a Reserved Instruction Exception If the encoding is imple mented it must match the instruction encoding as shown in the table Operation or field codes marked with this symbol are reserved for MIPS Application Specific Extensions If the ASE is not implemented executing such an instruction must cause a Reserved Instruction Exception o Operation or field codes marked with this symbol are obsolete and will be removed from a future revision of the MIPS64 ISA Software should avoid using these operation or field codes MIPS32 M4K Processor Core Software User s Manual Revision 02 03 229 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS16e Application Specific Extension to the MIPS32 Instruction Set 230 Table 11 2 MIPS16e Encoding of the Opcode Field opcode bits 13 11 1 3 6 001 O11 110 ADDIUSP ADDIUPC JAL X 6 SHIFT RRI A 6 ADDIU 8 SLTIU L CMPI I LWSP LW LBU LHU LW
77. an exception or non vectored interrupt to a shadow set is done by writing to the ESS field of the SRSCtl register When an exception or interrupt occurs the value of SRSCtlcgg is copied to SHSCtlpss and SHSCtlossis set to the value taken from the appropriate source On an ERET the value of SRSCtlpssis copied back into SRSCtlcss to restore the shadow set of the mode to which control returns More precisely the rules for updating the fields in the SRSCt register on an interrupt or exception are as follows 1 No field in the SRSCtl register is updated if any of the following conditions is true In this case steps 2 and 3 are skipped e The exception is one that sets Status gpu Reset Soft Reset or NMI e The exception causes entry into EJTAG Debug Mode e Statusgey 1 e Statusey 1 2 SRSCtiogg is copied to SRHSCtlpss 3 SRSCtlcggis updated from one of the following sources MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 5 Exception Vector Locations e The appropriate field of the SRSMap register based on IPL if the exception is an interrupt Causey 1 Contig3 yeic 0 and Config3 yint 1 These are the conditions for a vectored interrupt e The E CSS field of the SRSCt register if the exception is an interrupt Cause y 1 and Config3yg c 1 These are the conditions for a vectored EIC interrupt e The ESS field of the SRSCtl regis
78. and Multiply Accumulate instructions i F l Divide Divide instructions I Mult Macc 3x3 CPA MDU Res Rdy 2 Sign Adjust Last stage of Divide is a sign adjust l l l l l l l MDU Res Rdy Result can be read from MDU wee 0j EL Sue MD Res Rd One or more cycles Figure 2 2 shows the operations performed in each pipeline stage of the M4K processor core when the area efficient multiplier is present Figure 2 2 M4K Core Pipeline Stages with area efficient MDU E M A W SRAM read l A gt E Bypass 1 Dec Instruction Decode l l Regnd Register file read ac AC2 Instruction Address Calculation stage 1 and 2 ALUO Arithmetic Logic and Shift operations DAC Data Address Calculation 3 D SRAM read i D SRAM Align Load data aligner wo p AoEBypass i Regw Register file write muL MUL instruction Multiply Divide Multiply Multiply Acc And Divide MDU Res Rdy Result can be read from MDU pu To res l l Multiply Divide MDUResRd i i One or more cycles WDU Pipeli IU Pipelin 2 1 1 I Stage Instruction Fetch During the Instruction fetch stage e An instruction is fetched from the instruction SRAM e MIPS16e instructions are converted into MIPS32 like instructions 24 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright
79. are zero This is provided the On bit bit 0 is also set This field is ignored on the M4K core because there is no 182 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 11 Trace Control Block TCB Registers Hardware Control Table 8 39 TCBCONTROLA Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State Mode 3 1 When tracing is turned on this signal specifies what informa R W Undefined tion is to be traced by the core Mode Trace Mode 000 Trace PC 001 Trace PC and load address 010 Trace PC and store address O11 Trace PC and both load store addresses 100 Trace PC and load data 101 Trace PC and load address and data 110 Trace PC and store address and data 111 Trace PC and both load store address and data The VModes field determines which of these encodings are supported by the processor The operation of the processor is UNPREDICTABLE if Mode is set to a value which is not supported by the processor This field defines the value on the PD TraceMode signal On 0 This is the global trace enable switch to the core When zero R W 0 tracing from the core is always disabled unless enabled by core internal software override of the PD input pins When set to one tracing is enabled whenever the other enabling functions are also true This
80. available for user defined instructions MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline of the M4K Core The M4K processor core implements a 5 stage pipeline similar to the original R3000 pipeline The pipeline allows the processor to achieve high frequency while minimizing device complexity reducing both cost and power con sumption This chapter contains the following sections e Section 2 1 Pipeline Stages e Section 22 Multiply Divide Operations e Section 2 3 MDU Pipeline High Performance MDU e Section 2 4 MDU Pipeline Area Efficient MDU e Section 2 5 Branch Delay e Section 2 6 Data Bypassing e Section 2 8 Interlock Handling e Section 2 9 Slip Conditions Section 2 10 Instruction Interlocks e Section 2 11 Hazards 2 1 Pipeline Stages The pipeline consists of five stages e Instruction I stage Execution E stage e Memory M stage Align A stage Writeback W stage A MAK core implements a Bypass mechanism that allows the result of an operation to be sent directly to the instruction that needs it without having to write the result to the register and then read it back The M4K soft core includes a build time option that determines the type of multiply divide unit MDU imple mented The MDU can be either a high performance array or an
81. be re executed after returning from the debug handler Debug Register Debug Status Bit Set DDBL for a load instruction or DDBS for a store instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 79 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core Additional State Saved None Entry Vector Used Debug exception vector 4 8 20 Complex Break Exception A complex data break exception occurs when the complex hardware breakpoint detects an enabled breakpoint Com plex breaks are taken imprecisely the instruction that actually caused the exception is allowed to complete and the DEPC register and DBD bit in the Debug register point to a following instruction Debug Register Debug Status Bit Set DIBImpr DDBLImpr and or DDBSImpr Additional State Saved Debug fields indicate which type s of complex breakpoints were detected Entry Vector Used Debug exception vector 4 9 Exception Handling and Servicing Flowcharts 80 The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers e General exceptions and their exception handler e Reset soft rese t and NMI exceptions and a guideline to their handler e Debug exceptions MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 9 Exception Handling a
82. be returned For improved efficiency however the core will fetch 32 bits of instruction data whenever the address is word aligned Thus for sequential MIPS16e code fetches only occur for every other instruction resulting in better performance and reduced system power Connecting to Narrower Devices The instruction and data read buses are always 32 bits in width To facilitate connection to narrower memories the SRAM interface protocol includes input byte enables that can be used by system logic to signal validity as partial read data becomes available The input byte enables conditionally register the incoming read data bytes within the core and thus eliminate the need for external registers to gather the entire 32 bits of data External muxes are required to redirect the narrower data to the appropriate byte lanes Lock Mechanism The SRAM interface includes a protocol to identify a locked sequence and is used in conjunction with the LL SC atomic read modify write semaphore instructions Sync Mechanism The interface includes a protocol that externalizes the execution of the SYNC instruction External logic might choose to use this information to enforce memory ordering between various elements in the system External Call Indication The interface has an indication when a fetch is for the target of a call type instruction like JAL or BAL A system with prefetching might choose to save prefetched instructions to be executed when there i
83. be set up to start and stop counting based on a trigger from instruction breakpoints 8 2 4 Conditions for Matching Breakpoints A number of conditions must be fulfilled in order for a breakpoint to match on an executed instruction or a data trans action and the conditions for matching instruction and data breakpoints are described below The breakpoints only match for instructions executed in non debug mode thus never on instructions executed in debug mode The match of an enabled breakpoint can either generate a debug exception or a trigger indication The BE and or TE bits in the BCn or DBCn registers are used to enable the breakpoints MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Debug software should not configure breakpoints to compare on an ASID value unless a TLB is present in the imple mentation 8 2 4 1 Conditions for Matching Instruction Breakpoints When an instruction breakpoint is enabled that breakpoint is evaluated for the address of every executed instruction in non debug mode including execution of instructions at an address causing an address error on an instruction fetch The breakpoint is not evaluated on instructions from a speculative fetch or execution nor for addresses which are unaligned with an executed instruction A breakpoint match depends on the virtual address of the executed instructi
84. bit in the data breakpoint registers is set to indicate that the match occurred The match is precise in that the debug exception or trigger occurs on the instruction that caused the break point to match 8 2 3 Features of Complex Breakpoints The complex breakpoint unit utilizes the instruction and data breakpoint hardware and looks for more specific match ing conditions There are several different types of enabling that allow more exact breakpoint specification Tuples add an additional condition to data breakpoints of requiring an instruction breakpoint on the same instructions Pass counters are counters that decrement each time a matching breakpoint condition is taken Once the counter reaches 0 the break or trigger effect of the breakpoint is enabled Priming allows a breakpoint to only be enabled once another trigger condition has been detected Data qualification allows instruction breakpoints to only be enabled once a corre sponding load data triggerpoint has matched both address and data Data qualified breakpoints are also disabled if a load is executed that matches on the address portion of the triggerpoint but has a mismatching data value The com plex breakpoint features can be combined to create very complex sequences to match on In addition to the breakpoint logic the complex break unit also includes a Stopwatch Timer block This counter can be used to measure time spent in various sections It can either be free running or it can
85. chap aii Men usum a RP DIPL EKRPEE 95 SRSMap Register Offfigls usce opea eio us eaae tates eR Stores RAS dM se esu N 98 Figure 5 9 Cause Register FOTITiISl ui cei ie Str aunt oido tera Sete EE o Velo En eS hee UepE oem S RE DEDI REIS 99 Figure 5 10 EPC Register FOFIal cnet reet ert aet nere mee RES MUERE EP reap Rp ea toa ke Pa rod eda 103 Figure S 1 FRA Register FONNAL 2c cxacu trees pera edic sida oie iun tama lan tutnud iode faci ntatdeix bnrdfent bns 103 Figure 5 12 EBase Register Formal iiie etes dee neri re enl no eue ARR SER du FM ad eU daa FA REA SERRA REPRE TELA 104 Figure 5 13 Contig Register Format Select O 2 ciet espe te edu E A incdeane Pen En o Ea cRd ud Rpre ep as ur Debe a a EuRS 105 Figure 5 14 Config Register Field DeserliptiOlnis s iiio taro betreten ctr par a Enc extet aia thun ardeat annida 105 8 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Contig Register Format Select 1 rrt otra to e XR xeu eR en ir tix poor char bna petet po ctia 106 v Gonfig2 Register Format Select 2 4d pese a een E a E 107 CONTIGS Register FOLtTial 2 2 2 222 tice eter E ed t isceet tete Ls ce EA ts tU PLUIE 108 Deb g Register Format sssini ooo eeto uie teo satan echh E Cet Roo Hbc Dd utis Ssquo E ebo deo fa 110 raceControl Register Format zscxaspecexsxiua eset utputa
86. counter ADDI T2 T1 1 increment SC T2 TO try to store checking for atomicity BEQ T2 0 L1 4 if not atomic 0 try again NOP branch delay slot Exceptions between the LL and SC cause SC to fail so persistent exceptions must be avoided Some examples of these are arithmetic operations that trap system calls and floating point operations that trap or require software emu lation assistance LL and SC function on a single processor for cached noncoherent memory so that parallel programs can be run on uniprocessor systems that do not support cached coherent memory access types MIPS32 M4K Processor Core Software User s Manual Revision 02 03 225 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Synchronize Shared Memory SYNC 31 26 25 21 20 16 15 11 10 0 SPECIAL 0 A SYNC 000000 00 0000 0000 0000 0 Yp 001111 6 15 5 6 Format SYNC stype 0 implied MIPS32 Purpose Synchronize Shared Memory To order loads and stores Description Simple Description SYNC affects only uncached and cached coherent loads and stores The loads and stores that occur before the SYNC must be completed before the loads and stores after the SYNC are allowed to start Loads are completed when the destination register is written Stores are completed when the stored value is visi ble to every other processor in the system SYNC is required potentially in conjunction with SSNOP in Release 1 of the Archi
87. device type and version code Accessing the Identification Register does not interfere with the operation of the processor Also access to the Identification Register is immediately available via a TAP data scan operation after power up when the TAP has been reset with on chip power on or through the optional TRST_N pin MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP 8 4 3 3 IMPCODE Instruction This instruction selects the Implementation register for output which is always 32 bits 8 4 3 4 ADDRESS Instruction This instruction is used to select the Address register to be connected between TD and TDO The EJTAG Probe shifts 32 bits through the TDI pin into the Address register and shifts out the captured address via the TDO pin 8 4 3 5 DATA Instruction This instruction is used to select the Data register to be connected between TD and TDO The EJTAG Probe shifts 32 bits of TDI data into the Data register and shifts out the captured data via the TDO pin 8 4 3 6 CONTROL Instruction This instruction is used to select the EJTAG Control register to be connected between TD and TDO The EJTAG Probe shifts 32 bits of TDI data into the EJTAG Control register and shifts out the EJTAG Control register bits via TDO 8 4 3 7 ALL Instruction This instruction is used to select the concatenation of the Address and Data register
88. down mode is through execution of the WAIT instruction If the bus is idle at the time the WAIT instruction reaches the M stage of the pipeline the internal clocks are suspended and the pipeline is frozen However the internal timer and some of the input pins S ni 5 0 S NMI SI Reset SI ColdHeset and EJ DINT continue to run If the bus is not idle at the time the WAIT instruction reaches the M stage the pipeline stalls until the bus becomes idle at which time the clocks are stopped Once the CPU is in instruc tion controlled power management mode any enabled interrupt NMI debug interrupt or reset condition causes the CPU to exit this mode and resume normal operation While the part is in this low power mode the S SLEEP signal is asserted to indicate to external agents what the state of the chip is MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 8 EJTAG Debug Support in the M4K Core The EJTAG debug logic in the M4K processor core provides three optional modules 1 Hardware breakpoints 2 Test Access Port TAP for a dedicated connection to a debug host 3 Tracing of program counter data address data value trace to On chip memory or to a Trace probe These features are covered in the following sections e Section 8 1 Debug Control Register e Section 8 2 Hardware Breakpoints e Section 8 3 Complex Breakpoint Usage
89. e Stop tracing when a bus error is detected so that the trace buffer contains the code sequence leading up to the error MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 10 PDtrace Registers Software Control Note that trace triggers are independent from EJTAG triggerpoints and the presence or absence of trace triggers does not impact the ability to start or stop trace with triggerpoints 8 9 9 Cycle by Cycle Information All of the trace information listed in 8 9 3 Trace Information and 8 9 4 Load Store Address and Data Trace Information will be collected from the PDtrace interface by the TCB The trace will then be compressed and aligned to fit in 64 bit trace words with no loss of information It is possible to exclude include the exact cycle by cycle relationship between each instruction If excluded the number of bits required in the trace information from the TCB is reduced and each trace word will only contain information from completing instructions 8 9 10 Trace Message Format The TCB collects trace information every cycle from the PDtrace interface This information is collected into six different Trace Formats TF1 to TF6 One important feature is that all Trace Formats have at least one non zero bit 8 9 11 Trace Word Format After the PDtrace data has been turned into Trace Formats the trace information must be st
90. each of the breakpoints are listed in Table 8 23 e The priming breakpoint must have xBCnrg or xBCCnggr set e Once the priming condition has been seen the primed breakpoint will remain primed until its xBCCn register is written e The primed state is stored with the breakpoint being primed and not with the breakpoint that is doing the prim ing e Each Prime condition is the comparator output after it has been qualified by its own Prime condition data quali fication and pass counter Using this several stages of priming are possible e g data cycle D followed by instruction A followed by instruction B N times followed by instruction C 8 3 6 Usage of Data Qualified Breakpoints Each of the instruction breakpoints can be set to be data qualified In qualified mode a breakpoint will recognize its conditions only after the specified data breakpoint matches both address and data If the data breakpoint matches address but has a mismatch on the data value the instruction breakpoint will be unqualified and will not match until a subsequent qualifying match This feature can be used similarly to the ASID qualification that is available on cores with TLBs If an RTOS loads a process ID for the current process that load can be used as the qualifying breakpoint When a matching process ID is loaded entering the desired RTOS process qualified instruction breakpoints will be enabled When a different pro cess ID is loaded leaving the desire
91. eire ka eee E ex sicut aa ser dic pud usto yas 112 Figure 5 20 TraceControl2 Register Format cocido ter ec tr tac ac RE x dp ADI ED acit E pr Una Mi EQ D DedL ires 114 Figure 5 21 User Trace Data Register FO BE Vossio ed sacet cites eae Eee da et ase a tede e atenta teadceed a 116 Figure 5 22 Trace BPC Register Foral tee rreces a R E haero Seresse cuta etie saetd p udi ua ebede tuia 117 Figure 5 23 Debio2 Reglster ROMMEL eoa teed cipes oett pareve riai rE edet e peer tesa ka sept rx posce EEN 118 Figure 5 24 DEPC Register FORMAL sunsrsargia du dete ai te lass thud aa erae D races e budRc dU ipN TIE pP IEN 119 Figure 25 Errore PG Register FOETIal gerningen d petat teu iet ua tte Reo a d Le T Pope INE 120 Figure 5 26 DeSave Register FOIImagt iss deo capte E sup E Ceta E osi DvaS ir to sede occu plu Cssedua cadet 120 Figure 8 T TAP Controller State DIaOEalt exa occi pascebat ner haa SE xx Exiha nace Ex paie ita trae uad do ea ACEN ORE 153 Figure 8 2 Concatenation of the EJTAG Address Data and Control Registers 0 cccceeeeeeeeeeeceeeeeeesteeeeeeees 157 Figure 8 3 TDI to TDO Path When in Shift DR State and FASTDATA Instruction is Selected 158 Figure 8 4 Endian Formats for the PAD Register s1iccccccccssscsssccenscasetenedenesscenaustzazaccneceeisensaceteescndestnenncsaacensccemneatens 166 Figure 8 52 Trace EOgiGOVOTVIGW ro ccc etos xad Peter cec tia REE KEERT ENNER EEN NONE 171 Figure 8 6 EJTAG
92. eret Return to interrupted code NestedException F X MIPS328 MAKTM Nested exceptions typically require saving the EPC and Status registers any GPRs that may be modified by the nested exception routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processing and is intended only to demonstrate the concepts Save GPRs here and setup software context mfcO k0 CO EPC Get restart address sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value sw k0 StatusSave Save in memory li k1 IMbitsToClear Get Im bits to clear for this interrupt E this must include at least the IM bit 7 for the current interrupt and may include Es others and k0 kO k1 Clear bits in copy of Status ins k0 zero S_StatusEXL W_StatusKSU W_StatusERL W_StatusEXL Clear KSU ERL EXL bits in k0 Processor Core Software User s Manual Revision 02 03 59 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core mtcO k0 CO Status Modify mask switch to kernel mode re enable interrupts Process interrupt here including clearing device interrupt In some environments this may be done with a thread running in kernel or user m
93. executed starting with the LL and ending with the SC do not lie in a 2048 byte contiguous region of virtual memory The region does not have to be aligned other than the alignment required for instruc tion words The following conditions must be true or the result of the SC is UNPREDICTABLE Execution of SC must have been preceded by execution of an LL instruction e An RMW sequence executed without intervening events that would cause the SC to fail must use the same address in the LL and SC The address is the same if the virtual address physical address and cache coherence algorithm are identical Restrictions The effective address must be naturally aligned If either of the 2 least significant bits of the address is non zero an Address Error exception occurs MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Store Conditional Word SC Operation vAddr sign extend offset GPR base if vAddr o 0 then SignalException AddressError endif pAddr CCA AddressTranslation vAddr DATA STORE dataword GPR rt if LLbit then StoreMemory CCA WORD dataword pAddr vAddr DATA endif GPR rt 0 LLbit Exceptions TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes LL and SC are used to atomically update memory locations as shown below Ll LL T1 TO load
94. field defines the value on the PD TraceOn signal 8 11 2 TCBCONTROLB Register The TCB includes a second control register TCBCONTROLB 0x11 This register generally controls what to do with the trace information received The format of the TCBCONTROLB register is shown below and the fields are described in Table 8 40 TCBCONTROLB Register Format 31 30 26 25 21 20 19 17 16 15 14 13 12 11 10 8 7 6 3 2 1 0 we 0 REG wr 0 RM TR BF TM o CR Cal 0 ca orc EN Table 8 40 TCBCONTROLB Register Field Descriptions Fields Read Wr Name Bits Description ite Reset State WE 31 Write Enable R 0 Only when set to 1 will the other bits be written in TCBCONTROLB This bit will always read 0 0 30 26 Reserved Must be written as zero returns zero on read R 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 183 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 40 TCBCONTROLB Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State REG 25 21 Register select This field select the registers accessible through R W 0 the TCBDATA register Legal values are shown in Table 8 38 WR 20 Write Registers When set the register selected by REG field is R W 0 read and written when TCBDATA is accessed Otherwise the selected register is only read
95. function field is exe cuted This includes Coprocessor 2 instructions which are decoded reserved in the Coprocessor 2 Cause Register ExcCode Value RI Additional State Saved None Entry Vector Used General exception vector offset 0x 180 4 8 13 Execution Exception Coprocessor Unusable The coprocessor unusable exception is one of the nine execution exceptions All of these exceptions have the same priority A coprocessor unusable exception occurs when an attempt is made to execute a coprocessor instruction for one of the following e a corresponding coprocessor unit that has not been marked usable by setting its CU bit in the Status register e CPO instructions when the unit has not been marked usable and the processor is executing in user mode Cause Register ExcCode Value CpU MIPS32 M4K Processor Core Software User s Manual Revision 02 03 77 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 78 Additional State Saved Table 4 12 Register States on a Coprocessor Unusable Exception Causecg unit number of the coprocessor being referenced Entry Vector Used General exception vector offset 0x180 4 8 14 Execution Exception CorExtend Unusable The CorExtend unusable exception is one of the nine execution exceptions All of these exceptions have the same pri ority A CorExtend Unusable exception occurs when an attempt is made to ex
96. instruction register and the processor starts executing 9 The processor increments the program counter and outputs an instruction read request for the next instruction This starts the whole sequence again Using the same protocol the processor can also execute a load instruction to access the EJTAG Probe s memory For this to happen the processor must execute a load instruction e g a LW LH LB with the target address in the appro priate range Almost the same protocol is used to execute a store instruction to the EJTAG Probe s memory through dmseg The store address must be in the range OXFF20 0000 to OxFF2F FFFF the ProbEn bit must be set and the processor has to be in debug mode DM 1 The sequence of actions is found below 1 The internal hardware latches the requested address into the PA Address register 2 The internal hardware latches the data to be written into the PA Data register 168 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 7 Trace Mechanisms 3 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PRnW 1 selects processor write operation Psz 1 0 value depending on the transfer size 4 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit
97. is found 1 it means that the requested address is available and can be shifted out 5 The EJTAG Probe checks the PRnW bit to determine the required access 6 The EJTAG Probe selects the PA Address register and shifts out the requested address 7 The EJTAG Probe selects the PA Data register and shifts out the data to be written 8 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the write access is finished 9 The EJTAG Probe writes the data to the requested address in its memory 10 The processor detects that PrAcc bit 0 which means that it is ready to handle a new access The above examples imply that no reset occurs during the operations and that Rocc is cleared Note probe accesses and external bus accesses are serialized by the core A probe access will not begin until all exter nal bus requests have completed Similarly a new probe or external bus access will not begin until a pending probe access has completed 8 7 Trace Mechanisms There are two optional trace mechanisms that are available to extract additional information about program execution EJTAG Trace is a powerful mechanism that allows for the tracing of the program flow as well as load and store addresses and data values EJTAG Trace can be configured to only trace in specific modes and can produce cycle accurate trace information Tracing can be controlled by either a hardware probe
98. is not considered in these match equations for value as the compare uses the data bus value directly thus debug software is responsible for setup of the breakpoint corresponding with endianess DB value match DBCnjyM s DATA 7 0 DBVnpgy 9 BYTELANE O DBCngpy oj DBCngai oj amp amp DATA 15 8 DBVnpgg 15 8j BYTELANE 1 DBCngyyi DBCngaij amp amp DATA 23 16 DBVfnpgsyi53 16 BYTELANE 2 DBCngyyi2 DBCngai amp amp DATA 31 24 DBVnpgsy a1 534 BYTELANE 3 DBCngyya3 DBCngai 3 The match for a data breakpoint is always precise since the match expression is fully evaluated at the time the load store instruction is executed A true DB match can thereby be indicated on the very same instruction causing the DB match to be true 8 2 5 Debug Exceptions from Breakpoints Instruction and data breakpoints may be set up to generate a debug exception when the match condition is true as described below 8 2 5 1 Debug Exception by Instruction Breakpoint If the breakpoint is enabled by BE bit in the BCn register then a debug instruction break exception occurs if the IB match equation is true The corresponding BS n bit in the BS register is set when the breakpoint generates the debug exception The debug instruction break exception is always precise so the DEPC register and DBD bit in the Debug register point to the instruc
99. n bit set prior to the match and debug exception are kept set since BS n bits are only cleared by debug software The debug handler usually returns to the instruction causing the debug data break exception whereby the instruction is re executed This re execution may result in a repeated load from system memory since the load may have occurred previously in order to evaluate the breakpoint as described above I O devices with side effects on loads may not be reaccessible without changing the system behavior The Load Data Value register was introduced to capture the value that was read and allow debug software to synthesize the load instruction without reaccessing memory Debug software is responsible for disabling breakpoints when returning to the instruction otherwise the debug data break exception will reoccur 8 2 6 Breakpoint Used as TriggerPoint Both instruction and data hardware breakpoints can be setup by software so a matching breakpoint does not generate a debug exception but only an indication through the BS n bit The TE bit in the BCn or DBCn register controls if an instruction or data breakpoint is used as a so called triggerpoint The triggerpoints are like breakpoints only com pared for instructions executed in non debug mode The BS n bit in the BS or DBS register is set when the respective IB match or DB match bit is true The triggerpoint feature can be used to start and stop tracing See 8 12 EJTAG Trace Enablin
100. not updated on any exception which sets Statusppy to 1 i e Reset Soft Reset NMI cache error an entry into EJTAG Debug mode or any excep tion or interrupt that occurs with Statusgy 1 or Sta tuspry 1 This field is not updated on an exception that occurs while Statuspgg 1 The operation of the processor is UNDEFINED if soft ware writes a value into this field that is greater than the value in the HSS field Must be written as zeros returns zero on read 0 Current Shadow Set If GPR shadow registers are imple 0 mented this field is the number of the current GPR set With the exclusions noted in the next paragraph this field is updated with a new value on any interrupt or exception and restored from the PSS field on an ERET Table 5 10 describes the various sources from which the CSS field is updated on an exception or interrupt This field is not updated on any exception which sets Statusppy to 1 i e Reset Soft Reset NMI cache error an entry into EJTAG Debug mode or any excep tion or interrupt that occurs with Statusgx 1 or Sta tusggy 1 Neither is it updated on an ERET with Statusgry 1 or Statuspggy 1 This field is not updated on an exception that occurs while Statusgg 1 The value of CSS can be changed directly by software only by writing the PSS field and executing an ERET instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 97 Copyright 2002 2008
101. or DEPC for debug exceptions is sufficient to restart execution It also ensures that exceptions are taken in the order of execution an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle 4 2 Exception Priority 56 Table 4 1 lists all possible exceptions and the relative priority of each highest to lowest Several of these exceptions can happen simultaneously in that event the exception with the highest priority is the one taken Table 4 1 Priority of Exceptions Exception Description Reset Assertion of SI ColdReset signal Soft Reset Assertion of SI Reset signal EJTAG Debug Single Step DINT EJTAG Debug Interrupt Caused by the assertion of the external EJ DINT input or by setting the EjtagBrk bit in the ECF register INM 0 0 Asserting edge of SI NMI signal Interrupt Assertion of unmasked hardware or software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error User mode fetch reference to kernel address Instruction fetch bus error EJTAG Breakpoint execution of SDBBP instruction Execution of SYSCALL instruction Execution of BREAK instruction Execution of a coprocessor instruction for a coprocessor that is not enabled Execution of a CorExtend instruction with CorExtend disabled Execution of a Reserved Instruction Execution of coprocess
102. or software interface In contrast the iFlowtrace mechanism is much lighter weight It only can only be controlled by debug software executing on the core and it only provides the ability to trace the program flow The reduced capabilities also reduce the silicon area required to implement it and reduces the costs associated with tracing while still providing valuable information for software debugging These two trace mechanisms are described in further detail in the rest of the chapter 8 8 iFlowtrace Mechanism The iFlowtrace mechanism provides a means to reconstruct a simple instruction trace from an execution stream This light weight instruction only tracing scheme is sufficient to reconstruct the execution flow in an M4K core under con ditions that are classified as appropriate The presence of the iFlowtrace mechanism is indicated by the CPO Config3 rrr register bit MIPS32 M4K Processor Core Software User s Manual Revision 02 03 169 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 170 8 8 1 A Simple Instruction Only Tracing Scheme A trace methodology can often be mostly defined by its inputs and outputs Hence this basic scheme is described by the inputs to the core tracing logic and by the trace output format from the core We assume here that the execution flow of the program is traced at the end of the execution path in the core similar to PDtrace 8 8 1 1 T
103. register No other CPO registers or fields are changed due to the debug exception thus no additional state is saved Operation if InstructionInBranchDelaySlot then DEPC PC 4 Debugpgp 1 else DEPC PC Debugppp amp 0 endif Debugp pits DebugExceptionType Debugyait HaltStatusAtDebugException Debugpoze DozeStatusAtDebugException Debugpy lt 1 if EJTAGControlRegisterproprrap 1 then PC OxFF20 0200 else PC OxBFCO 0480 endif The same debug exception vector location is used for all debug exceptions The location is determined by the Prob Trap bit in the EJTAG Control register ECR as shown in Table 4 9 Table 4 9 Debug Exception Vector Addresses ProbTrap bit in ECR Register Debug Exception Vector Address 0 OxBFCO 0480 1 OxFF20_0200 in dmseg MIPS32 M4K Processor Core Software User s Manual Revision 02 03 71 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 4 8 Exceptions 72 The following subsections describe each of the exceptions listed in the same sequence as shown in Table 4 1 4 8 1 Reset SoftReset Exception A reset exception occurs when the S ColdHeset signal is asserted to the processor A soft reset occurs when the SI Reset signals is asserted These exception is not maskable When one of these exceptions occurs the processor performs a full reset initiali
104. reserved Memory Management of the M4K Core 44 e User mode e Kernel mode e Debug mode User mode is most often used for application programs Kernel mode is typically used for handling exceptions and privileged operating system functions including CPO management and I O device accesses Debug mode is used for software debugging and most likely occurs within a software development tool The address translation performed by the MMU depends on the mode in which the processor is operating 3 2 1 Virtual Memory Segments The Virtual memory segments are different depending on the mode of operation Figure 3 2 shows the segmentation for the 4 GByte 23 bytes virtual memory space addressed by a 32 bit virtual address for the three modes of opera tion The core enters Kernel mode both at reset and when an exception is recognized While in Kernel mode software has access to the entire address space as well as all CPO registers User mode accesses are limited to a subset of the vir tual address space 0x0000_0000 to 0x7FFF_FFFF and can be inhibited from accessing CPO functions In User mode virtual addresses 0x8000_0000 to OXFFFF_FFFF are invalid and cause an exception if accessed Debug mode is entered on a debug exception While in Debug mode the debug software has access to the same address space and CPO registers as for Kernel mode In addition while in Debug mode the core has access to the debug segment dseg This area over
105. reserved 0 DM Debug Mode 0 This bit indicates the debug or non debug mode 0 Processor is in non debug mode 1 Processor is in debug mode The bit is sampled in the Capture DR state of the TAP controller Res reserved 0 8 5 3 Processor Access Address Register The Processor Access Address PAA register is used to provide the address of the processor access in the dmseg and the register is only valid when a processor access is pending The length of the Address register is 32 bits and this register is selected by shifting in the ADDRESS instruction 8 5 3 1 Processor Access Data Register The Processor Access Data PAD register is used to provide data value to and from a processor access The length of the Data register is 32 bits and this register is selected by shifting in the DATA instruction The register has the written value for a processor access write due to a CPU store to the dmseg and the output from this register is only valid when a processor access write is pending The register is used to provide the data value fora processor access read due to a CPU load or fetch from the dmseg and the register should only be updated with a new value when a processor access write is pending The PAD register is 32 bits wide Data alignment is not used for this register so the value in the PAD register matches data on the internal bus The undefined bytes for a PA write are undefined and for a PAD read then 0 zer
106. s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 3 3 Fixed Mapping MMU unpredictable and writes are ignored to any unimplemented register in the drseg Refer to Chapter 8 EJTAG Debug Support in the M4K Core on page 127 for more information on the DCR The allowed access size is limited for the drseg Only word size transactions are allowed Operation of the processor is undefined for other transaction sizes 3 2 4 2 Conditions and Behavior for Access to dmseg EJTAG Memory The behavior of CPU access to the dmseg address range at OXFF20 0000 to OxFF2F_FFFF is determined by the table shown in Table 3 5 Table 3 5 CPU Access to dmseg Address Range ProbEn bit in LSNM bit in Transaction DCR register Debug register Access Load Store Don t care 1 Kernel mode address space kseg3 Fetch 1 Don t care dmseg Load Store 1 0 Fetch 0 Don t care See comments below Load Store 0 0 The case with access to the dmseg when the ProbEn bit in the DCR register is 0 is not expected to happen Debug software is expected to check the state of the ProbEn bit in DCR register before attempting to reference dmseg If such a reference does happen the reference hangs until it is satisfied by the probe The probe can not assume that there will never be a reference to dmseg if the ProbEn bit in the DCR register is 0 because there is an inherent race between the debug software samp
107. s Manual Revision 02 03 35 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core Figure 2 17 IU Pipeline Slip after a MFHI One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle MFHI to R3 M A W Data bypass from A to E ADD R4 R34R5 o E slip E M A W 2 7 Coprocessor 2 Instructions If a coprocessor 2 is attached to the M4K core a number of transactions has to take place on the CP2 Interface for each coprocessor 2 instruction First of all if the CU 2 bit in the CPO Status register is not set then no coprocessor 2 related instruction will start a transaction on the CP2 Interface Rather a Coprocessor Unusable exception will sig naled If the CU 2 bit is set and a coprocessor 2 instruction is fetched the following transactions will occur on the CP2 Interface 1 The Instruction is presented on the instructions bus in E stage The coprocessor 2 can do a decode in the same cycle 2 The Instruction is validated from the core in M stage From this point the core will accept control and data sig nals back from coprocessor 2 All control and data signals from the coprocessor 2 is captured on input latches to the core 3 Ifall the expected control and data signals was presented to the core in the previous M stage the core will pro ceed executing the A stage If some return information is missing the A stage will not advance and cause a slip
108. sent is defined as shown in the table below when the trace buffer is either on chip or off chip as determined by the TCBCONTROLBojc bit SyP On chip Off chip 000 27 001 28 010 29 011 100 101 110 111 This field defines the value on the PD SyncPeriod signal Trace All Branches When set to one this field indicates that the core must trace either full or incremental PC values for all branches When set to zero only the unpredictable branches are traced This field defines the value on the PD TraceAllBranch sig nal Undefined Inhibit Overflow This bit is used to indicate to the core trace logic that slow but complete tracing is desired Hence the core tracing logic must not allow a FIFO overflow and discard trace data This is achieved by stalling the pipeline when the FIFO is nearly full so that no trace records are ever lost This field defines the value on the PDI InhibitOverflow sig nal MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Undefined Copyright 2002 2008 MIPS Technologies Inc All rights reserved 181 EJTAG Debug Support in the M4K Core Table 8 39 TCBCONTROLA Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State When set to one this enables tracing in Debug mode i e R W when the DM bit is one in the Debug register For trace to be en
109. signals from data breakpoints 1 enables trigger signals from data breakpoints DBPOn 17 16 Each of the 2 bits corresponds to the 2 possible EITAG R W hardware data breakpoints that may be implemented For example bit 16 corresponds to the first data break point If 2 data breakpoints are present in the EJTAG implementation then they correspond to bits 16 and 17 The rest are always ignored by the tracing logic since they will never be triggered A value of one for each bit implies that a trigger from the corresponding data breakpoint should start tracing And a value of zero implies that tracing should be turned off with the trigger signal IE 15 Used to specify whether the trigger signal from EJTAG instruction breakpoint should trigger tracing functions or not 0 disables trigger signals from instruction breakpoints 1 enables trigger signals from instruction breakpoints 0 14 6 Reserved Each of the 6 bits corresponds to the 6 possible EITAG hardware instruction breakpoints that may be imple mented Bit 0 corresponds to the first instruction breakpoint and so on If only 2 instruction breakpoints are present in the EJTAG implementation then only bits 0 and 1 are used The rest are always ignored by the tracing logic since they will never be triggered A value of one for each bit implies that a trigger from the corresponding instruction breakpoint should start tracing And a value of zero implies that tracing shou
110. significant three bits of the 32 bit virtual address are 1105 32 bit kseg2 virtual address space is selected In the M4K core this 22 byte 512 MByte kernel virtual space is located at physical addresses OxCO000 0000 OxDFFF FFFF 3 2 3 5 Kernel Mode Kernel Space 3 kseg3 In Kernel mode when the most significant three bits of the 32 bit virtual address are 111 the kseg3 virtual address space is selected In the M4K core this 22 byte 512 MByte kernel virtual space is located at physical addresses OxE000 0000 OxFFFF_FFFF 3 2 4 Debug Mode Debug mode address space is identical to Kernel mode address space with respect to mapped and unmapped areas except for kseg3 In kseg3 a debug segment dseg co exists in the virtual address range OXFF20 0000 to OxFF3F FFFF The layout is shown in Figure 3 5 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 49 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Memory Management of the M4K Core Figure 3 5 Debug Mode Virtual Address Space OxFFFF FFFF OxFFA40 0000 ksegl kseg0 Unmapped Mapped if mapped in Kernel Mode 0x0000 0000 The dseg is sub divided into the dmseg segment at OXFF20 0000 to OXFF2F FFFF which is used when the probe ser vices the memory segment and the drseg segment at OxXFF30 0000 to OxFF3F_FFFF which is used when mem ory mapped debug registers are accessed The subdivision and attributes for the segments
111. the SRSMap register Table 5 11 describes the SRSMap register fields Figure 5 8 SRSMap Register Format 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSVO Table 5 11 SRSMap Register Field Descriptions Fields Read Wr Name Bits Description ite Reset State SSV7 31 28 Shadow register set number for Vector Number 7 RW 9 SSV6 27 24 Shadow register set number for Vector Number 6 RW 0 SSV5 23 20 Shadow register set number for Vector Number 5 R W SSV4 19 16 Shadow register set number for Vector Number 4 R W SSV3 15 12 Shadow register set number for Vector Number 3 RW 0 SSV2 11 8 Shadow register set number for Vector Number 2 R W SSVI 7 4 Shadow register set number for Vector Number 1 R W 98 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 11 SRSMap Register Field Descriptions Continued Fields Read Wr Description ite Name Bits Reset State SSVO Shadow register set number for Vector Number 0 Rw o 5 2 9 Cause Register CPO Register 13 Select 0 The Cause register primarily describes the cause of the most recent exception In addition fields also control soft ware interrupt requests and the vector through which interrupts are dispatched With the exception of the P 9
112. the exception and whether the BEV bit is set in the Status register Table 4 6 gives the offsets from the vector base address as a function of the exception Note that the IV bit in the Cause register causes Interrupts to use a dedicated exception vector offset rather than the general exception vector For implementations of Release 2 of the Architecture Table 4 4 gives the offset from the base address in the case where StatuSgey 0 and Causejy 1 For implementations of Release 1 of the architecture in which Causejy 1 the vector offset is as if IntCtlys were 0 Table 4 7 combines these two tables into one that contains all possible vector addresses as a function of the state that can affect the vector selection To avoid complexity in the table the vector address value assumes that the EBase register as implemented in Release 2 devices is not changed from its reset state and that IntCtlys is O Table 4 5 Exception Vector Base Addresses Statuspey Exception 0 1 Reset Soft Reset NMI 16 BFCO 0000 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 67 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core Table 4 5 Exception Vector Base Addresses Statuspey Exception EJTAG Debug with ProbEn 0 in the 16 BFCO 0480 EJTAG_Control_register EJTAG Debug with ProbEn 1 in the 16 FF20 0200 EJTAG_Control_register For Release 1 of
113. the system to make a distinction between the two MIPS32 M4K Processor Core Software User s Manual Revision 02 03 45 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Memory Management of the M4K Core 3 2 1 2 Mapped Segments A mapped segment does use the FM to translate from virtual to physical addresses For the M4K core the mapped segments have a fixed translation from virtual to physical address The cacheability of the segment is defined in the CPO register Config fields K23 and KU see 5 2 13 Config Register CPO Register 16 Select 0 Write protection of segments is not possible during FM translation 3 2 2 User Mode In user mode a single 2 GByte 23 bytes uniform virtual address space called the user segment useg is available Figure 3 3 shows the location of user mode virtual address space Figure 3 3 User Mode Virtual Address Space 32 bit OxFFFF_FFFF Address Error 0x8000_0000 Ox7FFF FFFF 2GB Mapped useg 0x0000 0000 The user segment starts at address 0x0000 0000 and ends at address 0x7FFF_FFFF Accesses to all other addresses cause an address error exception The processor operates in User mode when the Status register contains the following bit values e UM 1 e EXL 0 e ERL 0 In addition to the above values the DM bit in the Debug register must be 0 Table 3 1 lists the characteristics of the useg User mode segments Table 3 1 User Mode Segments
114. tuia cct eto sede iua d toa edt EQ fun Oa cad i End R Mn nud 41 Table 3 12 User Mode Segmen meningi ra NE E NRR 46 Table 3 2 Kernel Mode Segments siucair ETE 48 Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces 50 Table 3 4 CPU Access to drseg Address Hafige s ciei gor dissix te cntnetichencendasiuvalaniadey ndi uisa siti d RaMDE d Aa 50 Table 3 5 CPU Access to dinseg Address Rahge uui ei testet aie tes eei iier ease N NE 51 Table 3 6 Cache Colierency ATIIBUIS tette tet pPER a Dum c tid su Sas N Reise ute Ea MP EUER E URS 51 Table 3 7 Cacheability of Segments with Block Address Translation ssssssssseeeeeenene 52 Table 1 Prionty Of EXCOpIORS oc dsciecm scietis vitir sedi durata te sucosutdpeisdseidu Fu dietam teres EDU ERA 56 Table 4 2 Interrpt MOGGS eite th ree are a rire prr ee Ea DRE e esu bon cec i itera nb ce tr tocca lui ve RAE 58 Table 4 3 Relative Interrupt Priority for Vectored Interrupt Mode ssssssseeseeeeereenemeennn nnns 61 Table 4 4 Exception Vector Offsets for Vectored Interrupts ssessssssssssseeeee eene nennen 65 Table 4 5 Exception Vector Base Addresses x oer pere RE ER BERI aaa C EAR QE RNUS INASRE USER Re EA 67 Table 4 6 Exception Vector OffSelsuoiisieccii iac orti aet aee teli eter eet Dese vul desea rio sedi NRA RRRE E ANERER RANNA 68 Table4 7 Exception Vectors iei EDU ee esie tos WEAR
115. various processor modes This section precisely describes these modes The terminology is then used elsewhere in the document DebugMode lt Debugpy 1 ExceptionMode lt not DebugMode and Statusgy 1 or StatuSpp 1 KernelMode lt not DebugMode or ExceptionMode and Statusyy 0 UserMode lt not DebugMode or ExceptionMode and Statusyy 1 8 9 2 Software Versus Hardware Control In some of the specifications and in this text the terms software control and hardware control are used to refer to the method for how trace is controlled Software control is when the CPO register TraceControl is used to select the modes to trace etc Hardware control is when the EJTAG register TCBCONTROLA in the TCB via the PDtrace interface is used to select the trace modes The 7raceControl TS bit determines whether software or hardware con trol is active 8 9 3 Trace Information The main object of trace is to show the exact program flow from a specific program execution or just a small window of the execution In EJTAG Trace this is done by providing the minimal cycle by cycle information necessary on the PDtrace interface for trace regeneration software to reproduce the trace The following is a summary of the type of information traced MIPS32 M4K Processor Core Software User s Manual Revision 02 03 175 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in t
116. written in consecutive cycles The trace output data is UNPREDICTABLE if this register is written in consecutive cycles This register is only implemented if the EJTAG Trace capability is present Figure 5 21 User Trace Data Register Format 31 0 Data Table 5 24 UserTraceData Register Field Descriptions Fields Read Description Write Reset State Data 31 0 Software readable writable data When written this R W 0 triggers a user format trace record out of the PDtrace interface that transmits the Data field to trace memory 116 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 21 TraceBPC Register CPO Register 23 Select 4 This register is used to control start and stop of tracing using an EJTAG Hardware breakpoint The Hardware break point would then be set as a trigger source and optionally also as a Debug exception breakpoint This register is only implemented if both Hardware breakpoints and the EJTAG Trace capability are present Figure 5 22 Trace BPC Register Format 31 30 18 17 16 15 14 6 5 0 DE 0 DBPOn IE 0 IBPOn Table 5 25 TraceBPC Register Field Descriptions Name Bits Description i Reset State DE 31 Used to specify whether the trigger signal from 0 EJTAG data breakpoint should trigger tracing func tions or not 0 disables trigger
117. 001 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 105 CPO Registers of the M4K Core Figure 5 14 Config Register Field Descriptions Continued Fields Read Writ Name i Description e Reset State MT MMU Type R 3 3 Fixed Mapping 0 2 4 7 Reserved 0 Must be written as zeros returns zeros on reads 0 0 KO Kseg0 coherency algorithm Refer to Table 5 17 for the R W 010 field encoding Table 5 17 Cache Coherency Attributes C 2 0 Value Cache Coherency Attribute 2 Uncached 3 Cached Core treats as uncached but passes attribute to the system for use with any external caching mechanisms 5 2 14 Config1 Register CPO Register 16 Select 1 The Config register is an adjunct to the Config register and encodes additional information about capabilities present on the core All fields in the Config register are read only Figure 5 15 Config1 Register Format Select 1 31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0 M MMU Size IS IL IA DS DL DA C2 MD PC WR CA EP FP Table 5 18 Config Register Field Descriptions Select 1 Fields oe Name Bit s Description Reset State This bit is hardwired to 1 to indicate the presence of the Config register MMU Size This field contains the number of entries in the TLB minus one The field is read as 0 d
118. 161 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 30 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State Psz 1 0 Processor Access Transfer Size R Undefined These bits are used in combination with the lower two address bits of the Address register to determine the size of a processor access transaction The bits are only valid when processor access is pending PAA 1 0 Psz 1 0 Transfer Size 00 00 Byte LE byte 0 BE byte 3 01 00 Byte LE byte 1 BE byte 2 10 00 Byte LE byte 2 BE byte 1 11 00 Byte LE byte 3 BE byte 0 00 01 Halfword LE bytes 1 0 BE bytes 3 2 10 01 Halfword LE bytes 3 2 BE bytes 1 0 00 10 Word LE BE bytes 3 2 1 0 00 11 Triple LE bytes 2 1 0 BE bytes 3 2 1 01 11 Triple LE bytes 3 2 1 BE bytes 2 1 0 All others Reserved Note LE little endian BE big endian the byte refers to the byte number in a 32 bit register where byte 3 bits 31 24 byte 2 bits 23 16 byte 1 bits 15 8 byte O bits 7 0 independently of the endianess Res reserved R 0 Doze Doze state R 0 The Doze bit indicates any kind of low power mode The value is sampled in the Capture DR state of the TAP con troller 0 CPU not in low power mode 1 CPU is in low power mode Doze includes the Reduced
119. 16e Multiply and Divide Instr ctiofis s eeu rotate ttr tenni terae aaa 233 Table 11 18 MIPS16e Jump and Branch Instructions ssssssssssssseseee ener 234 Table 11219 MIPS16e Shift INSWUGCHONS sacos tiae rina euet seco N Eacdx eR RAUM dre RA UNES 234 12 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 M4K Processor Core The MIPS32 M4K core from MIPS Technologies is a high performance low power 32 bit MIPS RISC proces sor core intended for custom system on silicon applications The core is designed for semiconductor manufacturing companies ASIC developers and system OEMs who want to rapidly integrate their own custom logic and peripher als with a high performance RISC processor A M4K core is fully synthesizable to allow maximum flexibility it is highly portable across processes and can easily be integrated into full system on silicon designs This allows develop ers to focus their attention on end user specific characteristics of their product The MAK core is ideally positioned to support new products for emerging segments of the routing network access network storage residential gateway and smart mobile device markets It is especially well suited for applications where high performance density is critical especially those requiring multiple processor cores on a single chip The M
120. 2008 MIPS Technologies Inc All rights reserved 4 8 Exceptions Additional State Saved Table 4 10 Register States an Interrupt Exception Cause p indicates the interrupts that are pending Entry Vector Used See 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts on page 65 for the entry vector used depending on the interrupt mode the processor is operating in 4 8 6 Debug Instruction Break Exception A debug instruction break exception occurs when an instruction hardware breakpoint matches an executed instruc tion The DEPC register and DBD bit in the Debug register indicate the instruction that caused the instruction hard ware breakpoint to match This exception can only occur if instruction hardware breakpoints are implemented Debug Register Debug Status Bit Set DIB Additional State Saved None Entry Vector Used Debug exception vector 4 8 7 Address Error Exception Instruction Fetch Data Access An address error exception occurs on an instruction or data access when an attempt is made to execute one of the fol lowing e Fetch an instruction load a word or store a word that is not aligned on a word boundary Load or store a halfword that is not aligned on a halfword boundary e Reference the kernel address space from user mode Note that in the case of an instruction fetch that is not aligned on a word boundary PC is updated before the condition is detected Therefore both EPC and Bad
121. 8320 Inst2 Bypass Data0 InstO Instl 0x1110 2000 0x8340 Inst3 Bypass Datal Inst4 Inst5 0x1514 2100 0x8360 Inst4 Bypass Datal Inst3 Inst5 0x1513 2100 0x8380 Inst5 Bypass Datal Inst3 Inst4 0x1413 2100 0x83a0 Data0 Bypass InstO Insti Inst2 0x1211_1000 0x84e0 Datal Bypass Inst3 Inst4 Inst5 0x1514 1300 0x8500 8 2 9 3 Stopwatch Timer Control STCi Register 0x8900 Compliance Level Implemented if stopwatch timer is implemented The Stopwatch Timer Control STCtl register gives configuration information about how the stopwatch timer regis ter is controlled On a M4K core the break channels that control the stopwatch timer are fixed and this register is read only Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS32 M4K Processor Core Software User s Manual Revision 02 03 31 Res StopChanl StartChanl Fields Name Bit s STCtI Register Format 18 17 14 13 10 Table 8 24 STCi Register Field Descriptions Description Read Wr ite 8 2 Hardware Breakpoints 9 8 5 4 1 0 StopChanO StartChanO Reset State Res 31 18 Must be written as zero returns zero on read R StopChanl StartChanl Enl StopChan0 17 14 13 10 8 5 Indicates the instruction breakpoint channel that will stop the counter if the timer is under pairl breakpoint control Indicates the instruction breakpoint channel that will start the counter if the timer is under pairl b
122. AK family has two members distinguished by the range of build time options available e MIPS32 M4K Core Fully configurable cacheless core e MIPS32 M4K Lite Core A subset of the full M4K core with a reduced set of build time configuration choices The term M4K core used throughout this document generally refers to all members of the M4K family Since the MAK Lite core has fewer configuration options than the M4K core certain features described in this document may not be available on the M4K Lite version The core implements the MIPS32 Release 2 Instruction Set Architecture ISA and may optionally support the MIPS16e Application Specific Extension ASE for code compression The MMU consists of a simple Fixed Map ping Translation FMT mechanism for applications that do not require the full capabilities of a Translation Looka side Buffer TLB based MMU available on other MIPS cores The M4K core is cacheless in lieu of caches it includes a simple interface to SRAM style devices This interface may be configured for independent instruction and data devices or combined into a unified interface The SRAM interface allows deterministic latency to memory while still maintaining high performance The core includes one of two different Multiply Divide Unit MDU implementations selectable at build time allow ing the user to trade off performance and area for integer multiply and divide operations The high performance MDU option i
123. ANDs each of the Causeyp bits with the corresponding Status bits If any of these values is 1 and if interrupts are enabled Statusjg 1 Statu 60 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 3 Interrupts SEXL 0 and Statuspg 0 an interrupt is signaled and a priority encoder scans the values in the order shown in Table 4 3 Table 4 3 Relative Interrupt Priority for Vectored Interrupt Mode Interrupt Vector Number Relative Interrupt Interrupt Request Generated by Priority Type Source Calculated From Priority Encoder IP7 and IM7 IP6 and IM6 IP5 and IM5 IP4 and IM4 IP3 and IM3 IP2 and IM2 Highest Priority Hardware IP1 and IM1 IPO and IMO Software Lowest Priority The priority order places a relative priority on each hardware interrupt and places the software interrupts at a priority lower than all hardware interrupts When the priority encoder finds the highest priority pending interrupt it outputs an encoded vector number that is used in the calculation of the handler for that interrupt as described below This is shown pictorially in Figure 4 1 Figure 4 1 Interrupt Generation for Vectored Interrupt Mode Latch Mask Encode Generate gt IntCtlpry a
124. All bits of the EPC register are significant and must be writable For synchronous precise exceptions the EPC contains one of the following e The virtual address of the instruction that was the direct cause of the exception e The virtual address of the immediately preceding branch or jump instruction when the exception causing instruction is in a branch delay slot and the Branch Delay bit in the Cause register is set On new exceptions the processor does not write to the EPC register when the EXL bit in the Status register is set however the register can still be written via the MTCO instruction In processors that implement the MIPS16e ASE a read of the EPC register via MFCO returns the following value in the destination GPR GPR rt ExceptionPC3 ISAModeg That is the upper 31 bits of the exception PC are combined with the lower bit of the SAMode field and written to the GPR Similarly a write to the EPC register via MTCO takes the value from the GPR and distributes that value to the exception PC and the SAMode field as follows ExceptionPC lt GPR rt 344 0 ISAMode lt 2 0 GPRIrt g 102 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions That is the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC and the lower bit of the exception PC is cleared
125. CBTRIGx Register Field Descriptions Fields Read W Reset Names Bits Description rite State TCBinfo 31 24 TCBinfo to be used in a possible TF6 trace format when this trigger R W 0 fires Trace 23 When set generate TF6 trace information when this trigger fires R W 0 Use TCBinfo field for the TCBinfo of TF6 and use Type field for the two MSB of the TCBtype of TF6 The two LSB of TCBtype are 00 The write value of this bit always controls the behavior of this trig ger When this trigger fires the read value will change to indicate if the TF6 format was ever suppressed by a simultaneous trigger If so the read value will be 0 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx reg ister is written 22 16 Reserved Must be written as zero returns zero on read R 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 191 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 48 TCBTRIGx Register Field Descriptions Continued Fields Read W Reset Names Bits Description rite State CHTro 15 When set generate a single cycle strobe on TC ChipTrigOut when R W 0 this trigger fires PDTro 14 When set generate a single cycle strobe on TC ProbeTrigOut R W 0 when this trigger fires 0 13 7 Reserved Must be written as zero returns zero on read R 0 DM 6
126. DIV Operation Clock 1 2 3 4 26 27 28 29 Estage PE Mupu Stage A Mupu Stage P Mapu Stage Muu Stage P Ampu Stage P Wunu Stage P LI LJ LI LI LI LI LJ RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 9 High Performance MDU Pipeline Flow During a 32 bit Divide DIV Operation Clock 1 2 3 4 34 35 36 37 Estage P E Munu Stage P Mupu Stage P Mapu Stage P Mupu Stage Je Ampu Stage P Wunu Stage P LI LI LI LI LI LI LJ RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Early In MDU Res Rdy 2 4 MDU Pipeline Area Efficient MDU The area efficient multiply divide unit MDU is a separate autonomous block for multiply and divide operations The MDU is not pipelined but rather performs the computations iteratively in parallel with the integer unit IU pipe line It does not stall when the IU pipeline stalls This allows the long running MDU operations to be partially masked by system stalls and or other integer unit instructions The MDU consists of one 32 bit adder result accumulate registers HI and LO a combined multiply divide state machine and all multiplexers and control logic A simple 1 bit per clock recursive algorithm is used for both multiply and divide operations Using booth s algorithm all multiply operations complete in 32 clocks Two extra clocks are needed for multiply acc
127. Description ite Read Wr Reset State Indicates whether the last debug exception or exception in debug mode occurred in a branch delay slot 0 Not in delay slot 1 In delay slot Undefined Indicates that the processor is operating in debug mode 0 Processor is operating in non debug mode 1 Processor is operating in debug mode LSNM Indicates whether the dseg memory segment is present and the Debug Control Register is accessible 0 dseg is present 1 No dseg present Controls access of load store between dseg and main memory 0 Load stores in dseg address range goes to dseg 1 Load stores in dseg address range goes to main mem ory Undefined Doze Halt IBusEP Indicates the Count register behavior in debug mode 0 Count register stopped in debug mode 1 Count register is running in debug mode Instruction fetch Bus Error exception Pending Set when an instruction fetch bus error event occurs or if a 1 is written to the bit by software Cleared when a Bus Error exception on instruction fetch is taken by the processor and by reset If IBusEP is set when IEXI is cleared a Bus Error exception on instruction fetch is taken by the processor and IBusEP is cleared 27 Indicates that the processor was in any kind of low power mode when a debug exception occurred 0 Processor not in low power mode when debug excep tion occurred 1 Processor in low power mode when debug exception occurred 26
128. Divide High Performance MDU ssssssssssssseseseseee eene nnne eene ntn nennen nnns 30 2 4 MDU Pipeline Area Etficient MDU 3 ctore i ese taeda eic etd anid ela Rc i dE idus 31 2 41 Multiply Area Eticiont MIU idco tos atin tacto den giae tcd daa tec vga ter dv ep aE ac 32 2 4 2 Multiply Accumulate Area Efficient MIDI tiet cacao berita citato bak Ra br detnr ga bnc demere 32 2 4 3 Divide Area Efficient MDU useisiin ninini iaaiiai aa 33 2S Brame Delay I EU 33 PS BITE EY as SIMON esa Sa REED Em 34 26 MINUIT EE 35 2 6 2 Move from HI LO and CPO Delay sess eene nennen snnt nen nennen nnns 35 27 Goprocessor2 InstD Cl9l s ssc eens tidied eode boe proci sre tici sep o ti a Rcg RGR eidcm AE DeL dus 36 exsilio suene eese career totes EE 37 219 Slip COMCIMOMS e ee RE A E 38 2 10 Instiucton Interot KS esse toecaateca taces ct dedu Eteue Sa ppUmR a Un EUE UA dU pna RU estu aa A aaia 38 2A ncVacjorqe t case a a a a dagen N a ictaclenre ad eiaaeiels 39 2 1 bewkd EEO ElaZ elio terii idco rte ee ee er meer ttn A unc taken onec cere err erent eer eec ur Db 40 211 2 Instr ctiomn Lisin Gerk E A N benceeracgeaactasety 41 2 11 3 Eliminatng Hazar dS iseanan anaana aaa ai a a aai aa iaaa iaDia 41 Chapter 3 Memory Management of the M4K Core nsaanassnunnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn mnnn 43 Sle MOUCHO eresas E E E A HM 43 3 2 Modes OF Ope IUO Minsan E A EA R A a ties beveta
129. Figure 3 7 FM Memory Map ERL 1 in the M4K Processor Core c ccccceeeeeeceeeeeeeeeeeeeeeeeaeeeseneeesaeeeeeaeeesaas 53 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Interrupt Generation for Vectored Interrupt Mode ssssssesssssssseseeeenne entente 61 Interrupt Generation for External Interrupt Controller Interrupt Mode sseeeese 64 General Exception Handler HW Lusso rent tre etn iana naaa 81 General Exception Servicing Guidelines SW sienne entente 82 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines ssssss 83 FIV AE Ma RSSISIBE FOI 11 2 pot cot enr ctc deuxpa EeceE ako SURE exRko e pIDEXKE A e euin ex boa eebisk ke dt dioe Ieee 87 BaaVAdat Register FOMA dies tues cota onia cds pen eniin oliv teo aea fed er aedes p eva sto ns diga aesex d Ya cx nine uade 88 Counthegister Format o octo sesedumreeluiedarstenv pb E dipradtedRu seed Unix d i E RUU P rRMdE 88 Compare Register Fone senises etes ieu dte rtat tec iesu e Deae aU o cec ce ea eR RU LU deca ceanie e tec cube pend e IEEE 89 Status Register FORMAL escena EI nesio ethos PE Nee SU Ot UN to cede och qubr ufzdses un cepe US DER Dos 90 Iit REJIS ter SORTI ccrto dcos pacer tu pex eee ect resa esae Pr RN Papae PR EES 94 SRSCII Register ROMMEL coole trate N deese ut esa duc
130. G Debug Support in the M4K Core 1 TAP controller enters is in Test Logic Reset state 2 EJ TRST N input is asserted low 8 12 EJTAG Trace Enabling 194 As there are several ways to enable tracing it can be quite confusing to figure out how to turn tracing on and off This section should help clarify the enabling of trace 8 12 1 Trace Trigger from EJTAG Hardware Instruction Data Breakpoints If hardware instruction data simple breakpoints are implemented in the M4K core then these breakpoint can be used as triggers to start stop trace When used for this the breakpoints need not also generate a debug exception but are capable of only generating an internal trigger to the trace logic This is done by only setting the TE bit and not the BE bit in the Breakpoint Control register Please see 8 2 7 5 Instruction Breakpoint Control n IBCn Register 0x1118 n 0x100 on page 136 and 8 2 8 5 Data Breakpoint Control n DBCn Register 0x2118 0x100 n on page 140 for details on breakpoint control In connection with the breakpoints the Trace BreakPoint Control 7raceBPC register is used to define the trace action when a trigger happens When a breakpoint is enabled as a trigger TE 1 it can be selected to be either a start or a stop trigger to the trace logic Please see 5 2 21 TraceBPC Register CPO Register 23 Select 4 on page 117 for detail in how to define a start stop trigger 8 12 2 Turning On PDtrace Trace
131. ID M ASID G Mode Table 5 22 TraceControl Register Field Descriptions Description Reset State The trace select bit is used to select between the hard 0 ware and the software trace control bits A value of zero selects the external hardware trace block signals and a value of one selects the trace control bits in this software control register 112 MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 22 TraceControl Register Field Descriptions Continued Fields Description This bit is used to indicate the type of user triggered trace record A value of zero implies a user type 1 and a value of one implies a user type 2 The actual triggering of a user trace record happens on a write to the UserTraceData register Trace All Branch When set to one this tells the pro Undefined cessor to trace the PC value for all taken branches not just the ones whose branch target address is statically unpredictable Inhibit Overflow This signal is used to indicate to the Undefined core trace logic that slow but complete tracing is desired When set to one the core tracing logic does not allow a FIFO overflow or discard trace data This is achieved by stalling the pipeline when the FIFO is nearly full so that no trace records are ever lost When set to one this enables tracing in De
132. IFlowTrace data output Records are concatenated into a continuous stream starting at the LSB When a trace word is filled it is written to memory along with some tag bits Each record consists of a 64 bit word which comprises 58 message bits and 6 tag bits or header bits that clarify information about the message in that word The ITCB includes a 58 bit shift register to accumulate trace messages Once 58 or more bits are accumulated the 58 bits and 6 tag bits are sent to the memory write interface Messages may span a trace word boundary In this case the 6 tag bits indicate the bit number of the first full trace message in the 58 bit data field The tag bits are not strictly binary because they serve a secondary purpose of indicating to off chip trace hardware when a valid trace word transmission begins At least one of the 4 LSB s of the tag is always a 1 The longest trace message is 36 bits so the starting position indicated by the tag bits is always between 0 and 35 When trace stops ON set to zero any partially filled trace words are written to memory Any unused space above the final message is filled with 1 s The decoder distinguishes 1111 patterns used for fill in this position from an 1111 overflow message by recognizing that it is the last trace word These trace formats are written to a trace memory that is off chip No particular size of SRAM is specified the size is user selectable based on the application needs and area tra
133. IPS Technologies Inc All rights reserved 9 3 Computational Instructions The access type together with the three low order bits of the address define the bytes accessed within the addressed word as shown in Table 9 1 Only the combinations shown in Table 9 1 are permissible other combinations cause address error exceptions Table 9 1 Byte Access Within a Word Bytes Accessed Low Order Big Endian Little Endian Address Bits 31 0 31 0 Access Type Word Triplebyte Halfword 9 3 Computational Instructions Computational instructions can be either in register R type format in which both operands are registers or in imme diate I type format in which one operand is a 16 bit immediate Computational instructions perform the following operations on register values e Arithmetic e Logical e Shift e Multiply e Divide These operations fit in the following four categories of computational instructions e ALU Immediate instructions e Three operand Register type Instructions e Shift Instructions e Multiply And Divide Instructions MIPS32 M4K Processor Core Software User s Manual Revision 02 03 205 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Instruction Set Overview 9 3 1 Cycle Timing for Multiply and Divide Instructions Any multiply instruction in the integer pipeline is transferred to the multiplie
134. Indicates that the internal system bus clock was stopped when the debug exception occurred 0 Internal system bus clock stopped 1 Internal system bus clock running MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Undefined 5 2 CPO Register Descriptions Table 5 21 Debug Register Field Descriptions Continued Fields Name Read Wr Description ite Reset State MCheckP CacheEP Indicates that an imprecise Machine Check exception is pending All Machine Check exceptions are precise on the M4K processor so this bit will always read as 0 Indicates that an imprecise Cache Error is pending Cache Errors cannot be taken by the M4K core so this bit will always read as 0 Data access Bus Error exception Pending Covers imprecise bus errors on data access similar to behavior of IBusEP for imprecise bus errors on an instruction fetch DDBSImpr Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications Set when the processor takes a debug exception or exception in debug mode Cleared by execution of the DERET instruction otherwise modifiable by debug mode software When IEXI is set the imprecise error exception from a bus error on an instruction fetch or data access cache error or machine check is inhibited and deferred until the bit is cleared Indicates that an imprecise Debug Data
135. Instruction Description Function BC2FL Branch On COP2 Condition False Likely if COP2Condition cc PC int offset else Ignore Next Instruction BC2T Branch On COP2 Condition True if COP2Condition cc 1 PC int offset BC2TL Branch On COP2 Condition True Likely if COP2Condition cc PC int offset else Ignore Next Instruction BEQ Branch On Equal if Rs Rt PC int offset BEQL Branch On Equal Likely if Rs Rt PC int offset else Ignore Next Instruction BGEZ Branch on Greater Than or Equal To Zero if Rs 31 PC int offset BGEZAL Branch on Greater Than or Equal To Zero And GPR 31 PC 8 Link if Rs 31 PC int offset BGEZALL Branch on Greater Than or Equal To Zero And GPR 31 PC 8 Link Likely if Rs 31 PC int offset else Ignore Next Instruction BGEZL Branch on Greater Than or Equal To Zero if Rs 31 Likely PC int offset else Ignore Next Instruction BGTZ Branch on Greater Than Zero if Rs 31 amp amp Rs 0 PC int offset BGTZL Branch on Greater Than Zero Likely if Rs 31 amp amp Rs 0 PC int offset else Ignore Next Instruction BLEZ Branch on Less Than or Equal to Zero if Rs 31 ll Rs PC int offset BLEZL Branch on Less Than or Equal to Zero Likely if Rs 31 ll Rs 0 PC int offset else Ignore Next Instruction BLTZ Branch on Less Than Zero if Rs 31 PC int offset BLTZAL Branch on Less Than Zero And Link GPR 31 PC 8 if
136. K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers The value used for reset indicated in the table below takes effect on both hard and soft CPU resets but not on TAP controller resets by e g TRST_N TCK clock is not required when the hard or soft CPU reset occurs but the bits are still updated to the reset value when the TCK applies The first 5 TCK clocks after hard or soft CPU resets may result in reset of the bits due to synchronization between clock domains EJTAG Control Register Format 31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 4 3 20 Rocc Psz Res se pu PerRst PRnW PrAcc Res PrRst ProbEn ProbTrap Res ped Res DM Table 8 30 EJTAG Control Register Descriptions Fields Read Name Bit s Description Write Reset State Rocce 31 Reset Occurred R W 1 The bit indicates if a hard or soft reset has occurred 0 No reset occurred since bit last cleared 1 Reset occurred since bit last cleared The Rocc bit will keep the 1 value as long as a hard or soft reset is applied This bit must be cleared by the probe to acknowledge that the incident was detected The EJTAG Control register is not updated in the Update DR state unless Rocc is 0 or written to 0 This is in order to ensure proper handling of processor access MIPS32 M4K Processor Core Software User s Manual Revision 02 03
137. MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 11 Trace Control Block TCB Registers Hardware Control Table 8 40 TCBCONTROLB Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State TM 13 12 Trace Mode This field determines how the trace memory is R W 0 filled when using the simple break control in the PDtrace interface to start or stop trace TM Trace Mode 00 Trace To 01 Trace From 10 Reserved 11 Reserved In Trace To mode the on chip trace memory is filled continu ously wrapping around and overwriting older Trace Words as long as there is trace data coming from the core In Trace From mode the on chip trace memory is filled from the point that PDO_lamTracing is asserted and until the on chip trace memory is full In both cases de asserting the EN bit in this register will also stop fill to the trace memory If a TCBTRIGx trigger control register is used to start stop tracing then this field should be set to Trace To mode This bit is reserved if on chip memory is not implemented 0 11 Reserved Must be written as zero returns zero on read R 0 CR 10 8 Off chip Clock Ratio Writing this field sets the ratio of the R W 100 core clock to the off chip trace memory interface clock The clock ratio encoding is shown in Table 8 41 Remark As the
138. Mis TECHNOLOGI MIPS32 M4K Processor Core Software User s Manual Document Number MD00249 Revision 02 03 August 29 2008 MIPS Technologies Inc 955 East Arques Avenue Sunnyvale CA 94085 4521 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS 7 Verified Copyright 2002 2008 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve fu
139. PC SWSP SW RRR 6 RRO EXTEND 6 1 The ADDIUSP opcode is used by the ADDIU rx sp immediate instruction 2 The ADDIUPC opcode is used by the ADDIU rx pc immediate instruction 3 The ADDIU8 opcode is used by the ADDIU rx immediate instruction 4 The LWSP opcode is used by the LW rx offset sp instruction 5 The LWPC opcode is used by the LW rx offset pc instruction 6 The SWSP opcode is used by the SW rx offset sp instruction T TD Dl Dej N Table 11 3 MIPS16e JAL X Encoding of the x Field JAL JALX Table 11 4 MIPS16e SHIFT Encoding of the f Field f bits 1 0 1 The ADDIU function is used by the ADDIU ry rx immediate instruction Table 11 6 MIPS16e I8 Encoding of the funct Field BTEQZ BTNEZ SWRASP ADJSP SVRS MOV32R T MOVR32 1 The SWRASP function is used by the SW ra offset sp instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 11 1 Instruction Bit Encoding 2 The ADJSP function is used by the ADDIU sp immediate instruction 3 The MOV32R function is used by the MOVE 132 rz instruction 4 The MOVR32 function is used by the MOVE ry r32 instruction Table 11 7 MIPS16e RRR Encoding of the f Field f bits 1 0 Table 11 8 MIPS16e RR Encoding of the Funct Field funct bits 2 0
140. PS32 M4K Processor Core Software User s Manual Revision 02 03 47 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Memory Management of the M4K Core Figure 3 4 Kernel Mode Virtual Address Space OxFFFF_FFFF Kernel virtual address space kseg3 OxEO00 0000 Fixed Mapped 512MB OxDFFF FFFF Kernel virtual address space Fixed Mapped 512MB kseg2 0xC000 0000 OxBFFF FFFF Kernel virtual address space ksegl 0xA000 0000 Unmapped Uncached 512MB Ox9FFF FFFF Kernel virtual address space kseg0 Unmapped 512MB seg 0x8000_0000 Ox7FFF FFFF Fixed Mapped 2048MB kuseg 0x0000 0000 Table 3 2 Kernel Mode Segments Status Register Is One of These Values Address Bit Segment Segment Values UM EXL ERL Name Address Range Size A 31 20 UM 0 0x0000 0000 2 GBytes 23 Or through bytes EXL 1 Ox7FFF FFFF A 31 29 1005 re 0x8000_0000 512 MBytes ERL 1 a through 27 bytes DM 0 Ox9FFF FFFF A 31 29 1015 O0xA000 0000 512 MBytes through 2 bytes OxBFFF FFFF A 31 29 1105 0xCO000 0000 512 MBytes through 2 bytes OxDFFF FFFF A 31 29 1115 kseg3 OxEO00 0000 512 MBytes through 2 bytes OxFFFF FFFF 48 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation 3 2 3 1 Kernel Mode User Space kuseg In Kernel mode when the most significant bit of the
141. Power RP and WAIT power reduction modes Halt 21 Halt state R 0 The Halt bit indicates if the internal system bus clock is running or stopped The value is sampled in the Cap ture DR state of the TAP controller 0 Internal system clock is running 1 Internal system clock is stopped 162 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers Table 8 30 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State PerRst Peripheral Reset 0 When the bit is set to 1 it is only guaranteed that the peripheral reset has occurred in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EJ_PerRst signal on the core PRnW Processor Access Read and Write Undefined This bit indicates if the pending processor access is for a read or write transaction and the bit is only valid while PrAcc is set 0 Read transaction 1 Write transaction PrAcc Processor Access PA 0 Read value of this bit indicates if a Processor Access PA to the EJTAG memory is pending 0 No pe
142. Put a programmable byte into the trace stream from the TCB 4 Start End or About delayed end control of the TCBCONTROLBgy bit The basic function of the trigger actions is explained in 8 11 9 TCBTRIGx Register Reg 16 23 on page 191 Please also read the next 8 13 5 Simultaneous Triggers 8 13 5 Simultaneous Triggers Two or more triggers can fire simultaneously The resulting behavior depends on trigger action set for each of them and whether they should produce a TF6 trace information output or not There are two groups of trigger actions Pri oritized and OR ed 8 13 5 1 Prioritized Trigger Actions For prioritized simultaneous trigger actions the trigger control unit which has the lowest number takes precedence over the higher numbered units The x in TCBTHIGx registers defines the number The oldest trigger takes prece dence over everything The following trigger actions are prioritized when two or more units fire simultaneously Trigger Start End and About type triggers TCB TRHIGXyse field set to 00 01 or 10 which will assert de assert the TCBCONTROLBgy bit The About trigger is delayed and will always change 7CBCONTROLBgy because MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 14 EJTAG Trace Cycle by Cycle Behavior it is the oldest trigger when it de asserts TC BCONTROLBgy An About trigger will not start the countdo
143. R desee Qu S dekalM E pt a amM D auIR d EF anauniaress 180 Table 8 98 Registers selected by TCBCONTROLEB iire pit rtp ret bte ese Rx ani ase duos ATE na SORS ERX PA argus 180 Table 8 39 TCBCONTROLA Register Field Descriptions eseesssssssssssseseseneneee nennen 180 Table 8 40 TCBCONTROLB Register Field Descriptions 183 Table 8 41 Clock Ratio encoding of the CR fleldl ssuuia iecit putre atee dix untras ases asbl d PM SS DEO 187 Table 8 43 TCBCONFIG Register Field Descriptions cea iri eee eoe eset tote re tasca ee an aaki 188 Table 8 42 TCBDATA Register Field Descriptions sessies innean sete k anima enu SRR Ran RNE 188 Table 8 44 TCBTW Register Field Descriptions ssssissssssssssseseseenee nennen nnne nnns nnns nnne 189 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 11 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Table 3 45 TCBRDP Register Field DESCHPIONS waiiccisseceeccesstvcecedsasnesvavsteenccectunssenecectyaavaredvatenoecttavanceedetsh ine 190 Table 8 46 TCBWAP Register Field Descriptions nennen nne E 190 Table 8 47 TCBSTP Register Field Description sessionen aoc risen etr inne et etas e EE eee eade DH MER 191 Table 8 48 TCBTRIGx Register Field Descriptions itr terre ette a ARES 191 Table 9 1 Byte Access Within a WO raten ak nera b toa a e b ate aed a 205 Table 10 1 Encoding of the Opcode Fleld retis tenerte apes e ipe
144. Register Format 31 0 DBV Table 8 16 DBVn Register Field Descriptions Read Wr N Bit s Description ite Reset State ame DBV 31 0 Data breakpoint value for condition R W Undefined 8 2 8 7 Data Breakpoint Complex Control n DBCCn Register 0x2128 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented data breakpoints The Data Breakpoint Complex Control n DBCCn register controls the complex break conditions for data break point n DBCCn Register Format 31 20 14 13 10 8 543210 19 16 15 9 m mies rur fe mes cue mmus o ne Table 8 17 DBCCn Register Field Descriptions Fields Name Bits Description Read Write Reset State Res 31 14 9 Must be written as zero returns zero on read 3 0 TIBrkNum 19 16 Tuple Instruction Break Number Indicates which DBCCO 0 instruction breakpoint will be paired with this data break DBCCI 3 point to form a tuple breakpoint TUP 15 Tuple Enable qualify this data breakpoint with a match on the TIBrkNum instruction breakpoint on the same instruction PrCnd 13 12 Upper bits of priming condition for D breakpoint n M4K only supports 4 priming conditions so the upper 2 bits are read only as 0 PrCnd 11 10 Priming condition for D Breakpoint n 00 Bypass no priming needed Other vary depending on the break number refer to Table 8 20 for mapping CBE 9 Complex Break Enable ena
145. Reset State of this field is Undefined If the Reset State of this field is Undefined software reads of this field result in an UNPRE hardware updates this field only under those DICTABLE value except after a hardware conditions specified in the description of the update done under the conditions specified in field the description of the field W A field that can be written by software but which can not be read by software Software reads of this field will return an UNDEFINED value 0 A field that hardware does not update and for A field to which the value written by software which hardware can assume a zero value must be zero Software writes of non zero val ues to this field may result in UNDEFINED behavior of the hardware Software reads of this field return zero as long as all previous software writes are zero If the Reset State of this field is Undefined software must write this field with zero before it is guaranteed to read as zero 5 2 1 HWREna Register CPO Register 7 Select 0 The HWRHREna register contains a bit mask that determines which hardware registers are accessible via the RDHWR instruction Figure 5 1 shows the format of the HWREna Register Table 5 3 describes the HWHEna register fields Figure 5 1 HWREna Register Format 31 4 3 0 0 0000 0000 0000 0000 0000 0000 0000 cs Table 5 3 HWREna Register Field Descriptions Fields Read Name Bits Description Write
146. SRSCtl Register Format 31 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 0 0 0 0 0 0 00 HSS 00 00 EICSS 00 ESS 00 PSS 00 CSS Table 5 9 SRSCtl Register Field Descriptions Reds iid Reset Description State 31 30 30 Must be written as zeros returns zero on read MIPS32 M4K Processor Core Software User s Manual Revision 02 03 95 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 96 Table 5 9 SRSCtl Register Field Descriptions Continued Fields Name Read Wr Bits Description ite Highest Shadow Set This field contains the highest shadow set number that is implemented by this proces sor A value of zero in this field indicates that only the normal GPRs are implemented Possible values of this field for the M4K processor are Encoding Meaning One shadow set normal GPR set is present Two shadow sets are present Four shadow sets are present Eight shadow sets are present 2 4 6 9 15 Reserved The value in this field also represents the highest value that can be written to the ESS EICSS PSS and CSS fields of this register or to any of the fields of the SRSMap register The operation of the processor is UNDEFINED if a value larger than the one in this field is written to any of these other fields Must be written as zeros returns zero on rea
147. T instruction designed to signal the rest of the device that execution and clocking should be halted reducing system power con sumption during idle periods The core provides two mechanisms for system level low power support discussed in the following sections e Section 7 1 Register Controlled Power Management e Section 7 2 Instruction Controlled Power Management 7 1 Register Controlled Power Management The RP bit in the CPO Status register enables a standard software mechanism for placing the system into a low power state The state of the RP bit is available externally via the S HP output signal Three additional pins S _EXL SI EHRL and EJ DebugM support the power management function by allowing the user to change the power state if an exception or error occurs while the core is in a low power state Setting the RP bit of the CPO Status register causes the core to assert the S FP signal The external agent can then decide whether to reduce the clock frequency and place the core into power down mode If an interrupt is taken while the device is in power down mode that interrupt may need to be serviced depending on the needs of the application The interrupt causes an exception which in turn causes the EXL bit to be set The setting of the EXL bit causes the assertion of the S EXL signal on the external bus indicating to the external agent that an interrupt has occurred At this time the external agent can choose to either speed up
148. The TCBCONTROLA register is written by an EJTAG TAP controller instruction TC BCONTROLA 0x10 The format of the TCBCONTROLA register is shown below and the fields are described in Table 8 39 TCBCONTROLA Register Format 31 26 25 24 23 22 20 19 18 17 16 15 14 13 12 5 4 3 1 0 0 VModes ADW SyP 73 o pe 0 K u ASID G Mode On Table 8 39 TCBCONTROLA Register Field Descriptions Fields Read Wr Name Bits Description ite Reset State EN 31 26 Reserved Must be written as zero returns zero on read OR 9 180 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 11 Trace Control Block TCB Registers Hardware Control Table 8 39 TCBCONTROLA Register Field Descriptions Continued Fields Name Bits Description Read Wr ite Reset State VModes This field specifies the type of tracing that is supported by the processor as follows Encodin g Meaning 00 PC tracing only 01 PC and Load and store address tracing only 10 PC load and store address and load and store data This field is preset to the value of PDO ValidModes PDO AD bus width 0 The PDO AD bus is 16 bits wide 1 The PDO AD bus is 32 bits wide Used to indicate the synchronization period The period in cycles between which the periodic synchroni zation information is to be
149. This chapter provides a general overview on the three CPU instruction set formats of the MIPS architecture Immedi ate Jump and Register Refer to Chapter 10 M4K Processor Core Instructions on page 207 for a complete list ing and description of instructions This chapter discusses the following topics e Section 9 1 CPU Instruction Formats e Section 9 2 Load and Store Instructions e Section 9 3 Computational Instructions e Section 9 4 Jump and Branch Instructions e Section 9 5 Control Instructions e Section 9 6 Coprocessor Instructions 9 1 CPU Instruction Formats Each CPU instruction consists of a single 32 bit word aligned on a word boundary There are three instruction for mats immediate I type jump J type and register R type as shown in Figure 9 1 The use of a small number of instruction formats simplifies instruction decoding allowing the compiler to synthesize more complicated and less frequently used operations and addressing modes from these three formats as needed MIPS32 M4K Processor Core Software User s Manual Revision 02 03 203 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Instruction Set Overview Figure 9 1 Instruction Formats I Type Immediate 31 26 25 2120 16 15 0 Co os eO mmo Type J ump 31 2625 0 op target R Type PERREN 2625 2120 1615 1110 A a E ad op 6 bit operation code TS 5 bit source register specifier
150. UB MSUBU 1 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation 2 4 1 Multiply Area Efficient MDU Multiply operations are executed using a simple iterative multiply algorithm Using Booth s approach this algorithm works for both positive and negative operands The operation uses 32 cycles in Mypy stage to complete a multiplica tion The register writeback to HI and LO are done in the A stage For MUL operations the register file writeback is done in the Wypyg stage Figure 2 10 shows the latency for a multiply operation The repeat rate is 33 cycles as a second multiply can be in the first Mypu stage when the first multiply is in Aygpy stage Figure 2 10 M4K Area Efficient MDU Pipeline Flow During a Multiply Operation Clock 1 2 33 34 35 EStage Pl Mypu Stage P Aupu Stage P Wupu Stage JE ee Ry T Add sub shift HI LO Write neo wa 2 4 2 Multiply Accumulate Area Efficient MDU Multiply accumulate operations use the same multiply machine as used for multiply only Two extra stages are needed to perform the addition subtraction The operations uses 34 cycles in Mypy stage to complete the multi ply accumulate The register writeback to HI and LO are done in the A stage Figure 2 11 shows the latency for a multiply accumulate operation The repeat rate is 35 cycles as a second multi ply accumulate can be in the E stage when the first multiply is i
151. VAddr point to the unaligned instruction address In the case of a data access the exception is taken if either an unaligned address or an address that was inaccessible in the current proces sor mode was referenced by a load or store instruction Cause Register ExcCode Value ADEL Reference was a load or an instruction fetch ADES Reference was a store MIPS32 M4K Processor Core Software User s Manual Revision 02 03 75 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 76 Additional State Saved Table 4 11 CPO Register States on an Address Exception Error BadVAddr failing address Entry Vector Used General exception vector offset 0x180 4 8 8 Bus Error Exception Instruction Fetch or Data Access A bus error exception occurs when an instruction or data access makes a bus request and that request terminates in an error The bus error exception can occur on either an instruction fetch or a data access Bus error exceptions that occur on an instruction fetch have a higher priority than bus error exceptions that occur on a data access Bus errors taken on any external access on the M4K core are always precise Cause Register ExcCode Value IBE Error on an instruction reference DBE Error on a data reference Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 9 Debug Software Breakpoint Exception
152. When set this Trigger will fire when a rising edge on the Debug R W 0 mode indication from the core is detected The write value of this bit always controls the behavior of this trig ger When this trigger fires the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written CHTri 5 When set this Trigger will fire when a rising edge on R W 0 TC_ChipTrigin is detected The write value of this bit always controls the behavior of this trig ger When this trigger fires the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written PDTri 4 When set this Trigger will fire when a rising edge on R W 0 TC ProbeTrigln is detected The write value of this bit always controls the behavior of this trig ger When this trigger fires the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx regis
153. When the value of the Count register equals the value of the Compare register the S Timerlnt pin is asserted This pin will remain asserted until the Compare register is written The S Timerlnt pin can be fed back into the core on one of the interrupt pins to generate an interrupt Traditionally this has been done by multiplexing it with hardware interrupt 5 to set interrupt bit P 7 in the Cause register For diagnostic purposes the Compare register is a read write register In normal use however the Compare register is write only Writing a value to the Compare register as a side effect clears the timer interrupt Figure 5 4 Compare Register Format 31 0 Compare Table 5 6 Compare Register Field Description Fields Read Wr Name Bit s Description ite Reset State Compare 31 0 Interval count compare value R W Undefined 5 2 5 Status Register CPO Register 12 Select 0 The Status register is a read write register that contains the operating mode interrupt enabling and the diagnostic states of the processor Fields of this register combine to create operating modes for the processor Refer to 3 2 Modes of Operation on page 43 for a discussion of operating modes and 4 3 Interrupts on page 57 for a dis cussion of interrupt modes Interrupt Enable Interrupts are enabled when all of the following conditions are true E 1 e EXL 0 e ERL 0 e DM 0 If these conditions are met then the
154. a en eme ete anc b ti ECs sine e Rras CM Rep M RAS UdyEO 208 Table 10 2 Special Opcode encoding of Function Field sssssssssssesee eene enne 208 Table 10 3 Special2 Opcode Encoding of Function Field sss nnns 208 Table 10 4 Special Opcode Encoding of Function Field sse enne 209 Table 10 5 Heglmm Encoding oft rt Field rite proci ttt a a cimup E wanadserslansyivece 209 Table 10 6 COP2 Encoding or TS Fleld erosion edite teta ioc ectetur aida t ocu Meteo on EAS 209 Table 10 7 COP2 Encoding of rt Field When resBG2 o tte ree ip e aree ena rege dokn 209 Table 10 8 COPO Encoding of rs fields sueco retra aaa t ramcn ta rex ka genre i naina 210 Table 10 9 COPO Encoding of Function Field When rS CO ccccccsssscssessesseeeeessseeeeeeesssnaeesesesensecesssenseseeessenees 210 Table 10 10 InsmlgllOn9 BE cisci tree erence ee rarer ette don thon vencer faced tr rerr en aS 210 Table 10 1 Usage of Effective Address usines cob reset Eb Pak nane naa Py base x XE ANGEN S Na EXER ee REE Ges u XAR EAS 217 Table 10 2 Encoding of Bits 17 16 of CACHE Instruction eerte erret rrr irren 218 Table 10 3 Encoding of Bits 20 18 of the CACHE Instruction nennen 218 Table 10 1 Values of hint Field tor PREF InstEltioli sss occa o oor eee poete esee tete eo rene taste eee aia 222 Table 11 1 Symbols Used in the Instruction Encoding Tables 229 Table 11 2 MIPS166 Encoding of t
155. a pre determined memory area such as in the EJTAG Probe This register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed Figure 5 26 DeSave Register Format 31 0 DESAVE Table 5 29 DeSave Register Field Description Read Wr ETE Bit s Description ite Reset State DESAVE 31 0 Debug exception save contents Undefined 120 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization of the M4K Core A MAK processor core contains only a minimal amount of hardware initialization and relies on software to fully ini tialize the device This chapter contains the following sections e Section 6 1 Hardware Initialized Processor State e Section 6 2 Software Initialized Processor State 6 1 Hardware Initialized Processor State A MAK processor core like most other MIPS processors is not fully initialized by hardware reset Only a minimal subset of the processor state is cleared This is enough to bring the core up while running in unmapped and uncached code space All other processor state can then be initialized by software S _Co dReset is asserted after power up to bring the device into a known state Soft reset can be forced by asserting the S _Reset pin This distinction is made for compatibility
156. abled in Debug mode the On bit must be one When set to zero trace is disabled in Debug mode irrespective of other bits This field defines the value on the PD DM signal u R W Undefined This controls when tracing is enabled When set tracing is Undefined enabled when either of the EXL or ERL bits in the Status reg ister is one provided that the On bit bit 0 is also se This field defines the value on the PD E signal Reserved Must be written as zero returns zero on read R 0 R W Undefined This field defines the value on the PD K signal When set this enables tracing when the core is in User mode Undefined as defined in the MIPS32 or MIPS64 architecture specifica tion This is provided the On bit bit 0 is also set This field defines the value on the PD U signal The ASID field to match when the G bit is zero When the G R W Undefined bit is one this field is ignored ASID This field defines the value on the PD ASID signal When set this implies that tracing is to be enabled for all pro R W Undefined cesses provided that other enabling functions like U S etc are also true This field is ignored on the M4K core because there is no ASID This field defines the value on the PD G signal When set this enables tracing when the On bit is set and the core is in Kernel mode Unlike the usual definition of Kernel Mode this bit enables tracing only when the ERL and EXL bits in the Status register
157. abling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processing and is intended only to demonstrate the concepts Use the current GPR shadow set and setup software context mfcO k0 CO EPC Get restart address sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value Sw k0 StatusSave Save in memory mfcO k0 CO SRSCtl1 Save SRSCtl if changing shadow sets Sw k0 SRSCtlSave li k1 IMbitsToClear Get Im bits to clear for this interrupt 7 this must include at least the IM bit for the current interrupt and may include Pd others and k0 kO k1 Clear bits in copy of Status If switching shadow sets write new value to SRSCtlpgg here ins k0 zero S_StatusEXL W_StatusKSU W_StatusERL W_StatusEXL Clear KSU ERL EXL bits in k0 mtcO k0 CO Status Modify mask switch to kernel mode re enable interrupts Tf switching shadow sets clear only KSU above write target address to EPC and do execute an eret to clear EXL switch shadow sets and jump to routine XY Process interrupt here including clearing device interrupt To complete interrupt processing the saved values must be restored and the original interrupted code restarted di Disable interrupts may
158. ace Mechanism but nevertheless the full PC value needs to be reconstructed This is used for synchronization purposes sim ilar to the Sync in PDtrace A preset sync period of 256 instructions is counted down and when an internal counter runs through all the values this format is used The bit assignments of this format on the bus between the core tracing logic and the ITCB is 3 0 4 b0111 34 4 PC 31 1 35 2 NCC 11 11 Used to indicate trace resumption after a discontinuity occurred The next format is a 1110 that sends a full PC value A discontinuity might happen due to various reasons for example an internal buffer over flow and at trace on trace off trigger action 8 8 2 ITCB Overview The IFlowTrace Control Block ITCB is responsible for accepting trace signals from the CPU core formatting them and storing them into an on chip FIFO The figure also shows the Probe Interface Block PIB which reads the FIFO and outputs the memory contents through a narrow off chip trace port Figure 8 5 Trace Logic Overview Logic Pipeline Out Valid IFlowTrace In TraceOn In Stall Trigger ITCB write port FIFO FIFO Control read port PIB 8 8 3 ITCB IFlowTrace Interface Off chip fe trace port The IFlowTrace interface consists of 36 data signals plus a valid signal The 36 data signals encode information about what the CPU is doing in ea
159. akpoint must be qualified to be taken 8 2 7 7 Instruction Breakpoint Pass Counter n BPCn Register 0x1128 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented instruction breakpoints The Instruction Breakpoint Pass Counter n BPCn register controls the pass counter associated with instruction breakpoint n If complex breakpoints are implemented there will be an 8b pass counter for each of the instruction breakpoints on the M4K core IBPCn Register Format 81 8 7 0 pu e Toren MIPS32 M4K Processor Core Software User s Manual Revision 02 03 137 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 9 BPCn Register Field Descriptions Fields Name Bits Description Read Write Reset State 0 31 8 Ignored on write returns zero on read R 009 PassCnt 7 0 Prevents a break trigger action until the matching condi R W 0 tions on breakpoint n have been seen this number of times Each time the matching condition is seen this value will be decremented by 1 Once the value reaches 0 subse quent matches will cause a break or trigger as requested and the counter will stay at 0 The break or trigger action is imprecise if the PassCnt register was last written to a non zero value It will remain imprecise until this register is written to 0 by soft ware The instruction pass counter shou
160. al move instructions MOVZ MOVN Prefetch instruction PREF e MIPS32 Enhanced Architecture Release 2 Features Vectored interrupts and support for an external interrupt controller Programmable exception vector base Atomic interrupt enable disable GPR shadow sets Bit field manipulation instructions e MIPS16e Application Specific Extension 16 bit encodings of 32 bit instructions to improve code density Special PC relative instructions for efficient loading of addresses and constants Data type conversion instructions ZEB SEB ZEH SEH Compact jumps JRC JALRC Stack frame set up and tear down macro instructions SAVE and RESTORE e Programmable Memory Management Unit MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 1 1 Features e Simple Fixed Mapping Translation FMT e Address spaces mapped using register bits e Simple SRAM Style Interface e Cacheless operation enables deterministic response and reduces size e 32 bit address and data input byte enables enable simple connection to narrower devices e Single or multi cycle latencies Configuration option for dual or unified instruction data interfaces e Redirection mechanism on dual I D interfaces permits D side references to be handled by I side e Transactions can be aborted to improve interrupt latency e Multi Core Support e External lock indication enables multi process
161. ansaction 1 Condition is never fulfilled on store transaction NoLB 12 Controls if condition for data breakpoint is not fulfilled R W Undefined on a load transaction 0 Condition may be fulfilled on load transaction 1 Condition is never fulfilled on load transaction Res 11 8 Must be written as zero returns zero on reads R 0 BLM 7 4 Byte lane mask for value compare on data breakpoint R W Undefined BLM 0 masks byte at bits 7 0 of the data bus BLM 1 masks byte at bits 15 8 etc 0 Compare corresponding byte lane 1 Mask corresponding byte lane Res 3 Must be written as zero returns zero on reads R 0 TE 2 Use data breakpoint n as triggerpoint R W 0 0 Don t use it as triggerpoint 1 Use it as triggerpoint IVM 1 Invert Value Match When set the data value compare R W 0 will be inverted a break or trigger will be taken if the value does not match the specified value BE 0 Use data breakpoint n as breakpoint R W 0 0 Don t use it as breakpoint 1 Use it as breakpoint 8 2 8 6 Data Breakpoint Value n DBVn Register 0x2120 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Value n DBVn register has the value used in the condition for data breakpoint n MIPS32 M4K Processor Core Software User s Manual Revision 02 03 141 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core DBVn
162. ardware breakpoint in the EJTAG block has a control bit associated with it that enables a trigger signal to be generated on a break match condition This trigger signal can be used to turn trace on or off thus allowing a user to control the trace on off functionality using breakpoints For the simple hardware breakpoints there are already defined registers TraceIBPC TraceDBPC etc in PDtrace that are used to control tracing functionality Similar regis ters need to be defined to control the start and stop of IFlowTrace And in addition the new complex Tuple break points need to be added to the list of breakpoints that can trigger trace The details on the actual register names and drseg addresses are shown in Table 8 35 Table 8 35 Registers that Enable Disable Trace from Complex Triggers and their drseg Addresses Register Name drseg Address Reset value Description ITrigiFlowTrcEn Ox3FDO Instruction break Trigger iFlowtrace Enable register DTrigiFlowTrcEn Ox3FD8 Data break Trigger iFlowtrace Enable reg ister The bits in each register are defined as follows e Bit 28 IE DB Used to specify whether the trigger signal from EJTAG simple or complex instruction or data break should trigger iFlowtrace tracing functions or not Value of 0 disables trigger signals from EJTAG instruc tion breaks and 1 enables triggers for the same e Bits 14 0 IBrkK DBrk Used to explicitly specify which instruction or data breaks enable or disa
163. are not implemented 1 Vectored interrupts are implemented On the M4K core this bit is always a 1 since vectored interrupts are implemented 108 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Table 5 20 Config3 Register Field Descriptions 5 2 CPO Register Descriptions Fields Description Read Wr ite Reset State Small 1KByte page support is implemented and the PageGrain register exists This bit will always read as 0 on the M4K core since no TLB is present Encoding Meaning 0 Small page support is not implemented 1 Small page support is implemented SmartMIPS ASE implemented This bit indicates whether the SmartMIPS ASE is implemented Since SmartMIPS is not present on the M4K core this bit will always be 0 Encoding Meaning 0 SmartMIPS ASE is not implemented 1 SmartMIPS ASE is implemented TL 0 Trace Logic implemented This bit indicates whether PC or data trace is implemented Encoding Meaning 0 Trace logic is not implemented 1 Trace logic is implemented R Preset 5 2 17 Debug Register CPO Register 23 Select 0 The Debug register is used to control the debug exception and provide information about the cause of the debug exception and when re entering at the debug exception vector due t
164. are shown in Table 3 3 Accesses to memory that would normally cause an exception if tried from kernel mode cause the core to re enter debug mode via a debug mode exception The unmapped kseg0 and kseg1 segments from kernel mode address space are available from debug mode which allows the debug handler to be executed from uncached and unmapped memory Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces Segment Sub Segment Cache Name Name Virtual Address Generates Physical Address Attribute OxFF20 0000 dmseg maps to addresses Uncached through 0x0 0000 OxF_FFFF in EJTAG OxFF2F FFFF probe memory space OxFF30 0000 through OxFF3F FFFF drseg maps to the breakpoint reg isters OxO 0000 OxF_FFFF 3 2 4 1 Conditions and Behavior for Access to drseg EJTAG Registers The behavior of CPU access to the drseg address range at OxXFF30 0000 to OXFF3F FFFF is determined as shown in Table 3 4 Table 3 4 CPU Access to drseg Address Range LSNM bit in Debug Transaction register Access Load Store 1 Kernel mode address space kseg3 Fetch Don t care drseg see comments below Load Store 0 Debug software is expected to read the debug control register DCR to determine which other memory mapped reg isters exist in drseg The value returned in response to a read of any unimplemented memory mapped register is 50 MIPS32 M4K Processor Core Software User
165. ate 72 48 2 Debug Single Step EXCOPUON sace cette ERI b Se SPD Ici ode ASE 72 48 3 Debug Interrupt EXCODLOFI occae tree rere than reat erede exa dor aei pae aae 73 4 8 4 Non Maskable Interrupt NMI Exception cccccceccceeeeseeeeeeeeeeeaaeeeeneeeeeaaeseeaeeeeeaaeeeeeeeeessaeeteeaeeneaas 74 48 5 lMtenUpt EXCODUOM aieiaa E A E 74 4 8 6 Debug Instruction Break EXCODLUIODIL 6 te cispecceietadstes teteioyanteceiabcute tera gated x Rene obo om E QUA Ra REO MR rR 75 4 8 7 Address Error Exception Instruction Fetch Data Access ssssssssseeeeeeenees 75 4 8 8 Bus Error Exception Instruction Fetch or Data ACCeSS cceeeeeecceeeeeeeeeeeeeeeeeeeeeeesneceeeneneees 76 48 9 Debug Software Breakpoint EXeOODIOD eai roce rate coca sone sta esee tet i rer epo I ERR Naa 76 2 8 10 Execution Exception System Gall cip estoit pu Sete dx e S EDuEERRUXEUN E nS eR PERSE RENE AS 76 4 8 11 Execution Exception Breakpollt 5 arret treo creep berk ea er Ek oor pae 77 4 8 12 Execution Exception Reserved InstrlletloDussecoocosedee conia et adag dp anced egeta Durte hl Ud a MA RR cd 77 4 8 13 Execution Exception Coprocessor Unusable ccecccceceeeeeeeeeeeeeseeeeeeeeeeeaaeseseneeeeaeeeeeeaeeeaas 77 4 8 14 Execution Exception CorExtend Unusable sssesssssssseeesseeeetne ener tnn 78 4 8 15 Execution Exception Coprocessor 2 Exception esssssssssssseeeeeenn
166. ated as matches are detected The current count value can be read from the regis ter while operating in debug mode Note that this behavior is architecturally recommended but not required MIPS32 M4K Processor Core Software User s Manual Revision 02 03 149 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 150 8 3 4 Usage of Tuple Breakpoints A tuple breakpoint is the logical AND of a data breakpoint and an instruction breakpoint Tuple breakpoints are spec ified as a condition on a data breakpoint If the DBCOCn p bit is set the data breakpoint will not match unless there the corresponding instruction breakpoint conditions are also met e Uses the data breakpoint resources to specify the break action break status pass counters and priming condi tions e The instruction breakpoint involved in the tuple should be configured as follows bd IBCCncpr 1 IBCCnpc IBCCnpo IBCnyg IBCngg IBPCn 0 8 3 5 Usage of Priming Conditions Priming conditions provide a way to have one breakpoint enabled by another one Prior to the priming condition being satisfied any breakpoint matches are ignored e Priming condition resets to bypass which specifies that no priming is required e 3 other priming conditions are available for each breakpoint These condition vary from breakpoint to breakpoint since it makes no sense for a breakpoint to prime itself The conditions for
167. below These registers have implementation information and are used the setup the data breakpoints All registers are in drseg and the addresses are shown in Table 8 20 Table 8 20 Addresses for Complex Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1120 0x100 n IBCCn Instruction Breakpoint Complex Control n described above with instruction breakpoint registers 0x1128 0x100 n IBPCn Instruction Breakpoint Pass Counter n described above with instruction breakpoint registers 0x2128 0x100 n DBCCn Data Breakpoint Complex Control n described above with data breakpoint registers 0x2130 0x100 n DBPCn Data Breakpoint Pass Counter n described above with data breakpoint registers 0x8000 0x8300 0x20 n CBTControl Complex Break and Triggerpoint Control indicates which of the complex breakpoint features are implemented PrCndAln Prime Condition Register A for Instruction breakpoint n 0x84e0 0x20 n PrCndADn Prime Condition Register A for Data breakpoint n 0x8900 STCtl Stopwatch Timer Control 0x8908 STCnt Stopwatch Timer Count 144 nis breakpoint number from 0 to 5 range dependent on implemented hardware 8 2 9 1 Complex Break and Trigger Control CBTC Register 0x8000 Compliance Level Implemented only if complex breakpoints are implemented MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyr
168. ber of data registers all accessible through the TAP 8 5 1 Instruction Register The Instruction register is accessed when the TAP receives an Instruction register scan protocol During an Instruction register scan operation the TAP controller selects the output of the Instruction register to drive the T DO pin The shift register consists of a series of bits arranged to form a single scan path between TD and TDO During an Instruction register scan operations the TAP controls the register to capture status information and shift data from TDI to TDO Both the capture and shift operations occur on the rising edge of TCK However the data shifted out from the TDO occurs on the falling edge of TCK In the Test Logic Reset and Capture IR state the instruction shift register is set to 00001 as for the IDCODE instruction This forces the device into the functional mode and selects the Device ID register The Instruction register is 5 bits wide The instruction shifted in takes effect for the following data register scan operation A list of the implemented instructions are listed in Table 8 27 8 5 2 Data Registers Overview The EJTAG uses several data registers which are arranged in parallel from the primary 7Dl input to the primary TDO output The Instruction register supplies the address that allows one of the data registers to be accessed during a data register scan operation During a data register scan operation the addressed scan register recei
169. ble iFlowtrace A value of 0 implies that trace is turned off unconditional trace stop and a value of 1 specifies that the trigger enables trace unconditional trace start If both trace on and trace off events happen on the same instruction tracing will be enabled 8 9 EJTAG Trace 174 EJTAG Trace enables the ability to trace program flow load store addresses and load store data Several run time options exist for the level of information which is traced including tracing only when in specific processor modes i e UserMode or KernelMode EJTAG Trace is an optional block in the M4K core If EJTAG Trace is not imple mented the rest of this chapter is irrelevant If EJTAG Trace is implemented the CPO Config3 bit is set The pipeline specific part of EJTAG Trace is architecturally specified in the PDtrace Interface Specification The PDtrace module extracts the trace information from the processor pipeline and presents it to a pipeline independent module called the Trace Control Block TCB The TCB is specified in the EJTAG Trace Control Block Specification The collective implementation of the two is called EJTAG Trace When EJTAG Trace is implemented the M4K core includes both the PDtrace and the Trace Control Block TCB modules The two modules talk to each other on the generic pin interface called the PDtrace Interface This inter face is embedded inside the M4K core and will not be discussed in detail here read the PD
170. bles this breakpoint for use as a priming or qualifying condition for another break point 142 MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 17 DBCCn Register Field Descriptions Fields Name Bits Description Read Write Reset State DQBrkNum 8 5 Indicates which data breakpoint channel is used to qual R 0 ify this data breakpoint Data qualification of data breakpoints is not supported on a M4K core and this field will read as 0 and cannot be written DQ 4 Qualify this breakpoint based on the data breakpoint indi R 0 cated in DBrkNum Data qualification of data breakpoints is not supported on a M4K core and this field will read as 0 and cannot be written 8 2 8 8 Data Breakpoint Pass Counter n DBPCn Register 0x2130 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented data breakpoints The Data Breakpoint Pass Counter n DBPCn register controls the pass counter associated with data breakpoint n If complex breakpoints are implemented there will be an 16b pass counter for each of the data breakpoints on the MAK core DBPCn Register Format 31 16 15 0 0 PassCnt Table 8 18 DBPCn Register Field Descriptions Fields Name Bits Description Read Write Reset State 0 31 16 Ignored on write re
171. bug Mode Undefined see 8 9 1 Processor Modes on page 175 For trace to be enabled in Debug mode the On bit must be one When set to zero trace is disabled in Debug Mode irrespective of other bits When set to one this enables tracing in Exception Undefined Mode see 8 9 1 Processor Modes on page 175 For trace to be enabled in Exception mode the On bit must be one When set to zero trace is disabled in Exception Mode irrespective of other bits When set to one this enables tracing in Kernel Mode Undefined see 8 9 1 Processor Modes on page 175 For trace to be enabled in Kernel mode the On bit must be one When set to zero trace is disabled in Kernel Mode irrespective of other bits U 21 When set to one this enables tracing in User Mode Undefined see 8 9 1 Processor Modes on page 175 For trace to be enabled in User mode the On bit must be one When set to zero trace is disabled in User Mode irre spective of other bits ASID M 20 13 R 0 In the M4K core where ASID is not supported this field is ignored on write and returns zero on read MIPS32 M4K Processor Core Software User s Manual Revision 02 03 113 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Table 5 22 TraceControl Register Field Descriptions Continued Description Reset State In the M4K core where ASID is not supported this field is ignored on wr
172. c All rights reserved Chapter 3 Memory Management of the M4K Core The M4K processor core includes a Memory Management Unit MMU that interfaces between the execution unit and the cache controller The core implements a simple Fixed Mapping FM style MMU This chapter contains the following sections e Section 3 1 Introduction e Section 3 2 Modes of Operation e Section 3 3 Fixed Mapping MMU e Section 3 4 System Control Coprocessor 3 1 Introduction The MMU will translate any virtual address to a physical address before a request is sent to the SRAM interface for an external memory reference In the M4K processor core the MMU is based on a simple algorithm to translate virtual addresses into physical addresses via a Fixed Mapping FM mechanism These translations are different for various regions of the virtual address space useg kuseg kseg0 kseg1 kseg2 3 Figure 3 1 shows how the memory management unit interacts with the SRAM access in the M4K core Figure 3 1 Address Translation During SRAM Access Virtual Physical Instruction Address Address Address aS inst Calculator SRAM FMT Data Data SRAM PONES ig Physical Calculator Virtual Address Address 3 2 Modes of Operation A MAK processor core supports three modes of operation MIPS32 M4K Processor Core Software User s Manual Revision 02 03 43 Copyright 2002 2008 MIPS Technologies Inc All rights
173. cacueeiaad 43 3 21 Vitual Memory Segrmielils 3 e eria citis N B tud URINE ER REEF Ee RA COE de adds 44 Deere WSC hr NOU ME pM 46 32S Kemell Mod seid T UN 47 3 24 DEBUG MOUS irc EE TEE DLL LUE 49 3 3 Fixed Mapping ue steadnce sateen Retloana ieses eee Rea in TTR ond deek Hotes tetas 51 ou System Conttol COmrOCeSS Ol sx derer aE A ee iA eee cA n 53 Chapter 4 Exceptions and Interrupts in the M4K Core eeeeeeeeeeee eee ee rennen 55 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 3 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 EXceptonm Conditio NS eraann e aaan n ao En EOR EEEE 55 4 2 EX CE PUOM FIO onesna a a aa b ccs i rcf e bed ode da dos can 56 2 3 Interr pte poit itx enac T dp rit eut Eae aio Husa T i E Rasse deti E veu dad ra T rius 57 da nieder ET 57 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts sssseeee 65 44 GPR Shadow RSgIsIGlS uiid reine sdinrerutes trcsstedu a Eaa EA 66 4 5 Exception d erdum eT 67 46 General Exception Processing iocis Stud pentes a ipea cR UU bie edi PURA EE rubo Dn p DU Sue epu eee 68 4 7 Debug Exception PTOCOSSIFIg 2 orienter tt deese dus tere det Ha x eet epa a pd S ka epe see a E XA td eR raa d 70 4 8 EXCBDUO S potuere et iare cox toraiuc ve iUa R a etas utut Sdn eboer irons 72 493 BHesevsofteseb EXCODLIIOT s t eth coti ute tu tero testi aute n loei Met scum Er ac PM SENE s
174. can be configured to be free running or controlled by instruction breakpoints This could be used to measure the amount of time that is spent in a particular function by starting the counter upon function entry and stopping it upon exit e Count value is reset to 0 e Reset state has counter stopped and under breakpoint control so that the counter is not running when the core is not being debugged e Bit in CBTControl register controls whether the counter is free running or breakpoint controlled e Counter does not count in debug mode e When breakpoint controlled the involved instruction breakpoints must have BCnrg or IBCCngpg set in order to start or stop the timer 8 4 Test Access Port TAP The following main features are supported by the TAP module e pin industry standard JTAG Test Access Port TCK TMS TDI TDO TRST_N interface which is compati ble with IEEE Std 1149 1 e Target chip and EJTAG feature identification available through the Test Access Port TAP controller e The processor can access external memory on the EJTAG Probe serially through the EJTAG pins This is achieved through Processor Access PA and is used to eliminate the use of the system memory for debug rou tines e Support for both ROM based debugger and debugging both through TAP MIPS32 M4K Processor Core Software User s Manual Revision 02 03 151 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in
175. ception it loads RIPL into Causegjp which overlays Causejpz jp and signals the external interrupt controller to notify it that the request is being serviced Because CauSe pip is only loaded by the processor when an interrupt exception is signaled it is available to software during interrupt processing The vector number that the EIC passes to the core is combined with the ntCtlys to determine where the interrupt service routine is located The vector number is not stored in any software visible registers In EIC interrupt mode the external interrupt controller is also responsible for supplying the GPR shadow set number to use when servicing the interrupt As such the SRSMap register is not used in this mode and the mapping of the vectored interrupt to a GPR shadow set is done by programming or designing the interrupt controller to provide the correct GPR shadow set number when an interrupt is requested When the processor loads an interrupt request into Causengip it also loads the GPR shadow set number into SRSCtlejcgg which is copied to SRSCt cgg when the interrupt is serviced The operation of EIC interrupt mode is shown pictorially in Figure 4 2 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 63 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 64 Figure 4 2 Interrupt Generation for External Interrupt Controller Interrupt Mode
176. ch clock cycle Valid indicates that the CPU is executing an instruction in this cycle and MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 171 EJTAG Debug Support in the M4K Core therefore the 36 data signals carry valid execution information The IFlowTrace data bus is encoded as shown in Table 8 33 Note that all the non defined upper bits of the bus are zeroes Table 8 33 Data Bus Encoding Valid Data LSBs Description 0 X No instructions executed in this cycle 1 0 Sequential instruction executed 1 01 Branch executed destination predictable from code 1 lt 8 gt 0011 Discontinuous instruction executed PC offset is 8 bit signed offset 1 lt 16 gt 1011 Discontinuous instruction executed PC offset is 16 bit signed offset 1 NCC 3150111 Discontinuous instruction or synchronization record No Code Com pression NCC bit included as well as 31 MSBs of the PC value 1 1111 Internal overflow The ITCB controls trace using the In_TraceOn signal When 0 all data appearing on the IFlowTrace outputs is con sidered invalid To turn on trace the ITCB switches In TraceOn from 0 to 1 A 1011 record represents the first instruction executed thereafter with a full PC indicating the current execution point 8 8 4 ITCB IFlowTrace Storage Representation Records from IFlowTrace are inserted into a memory stream exactly as they appear on the
177. ch to perform the operation as follows Table 10 2 Encoding of Bits 17 16 of CACHE Instruction Code Name Cache 0b00 Primary Instruction 0b01 D Primary Data Bits 20 18 of the instruction specify the operation to perform Table 10 3 Encoding of Bits 20 18 of the CACHE Instruction Effective Address Operand Code Caches Type Operation 0b000 Index Invalidate Index Set the state of the cache block at the specified index to invalid This encoding may be used by software to inval idate the entire instruction cache by stepping through all valid indices D Index This encoding may be used by software to inval Index f idate the entire data cache by stepping through all valid indices Note that Index Store Tag should be used to initialize the cache at pow erup we J 0b010 Index Store Tag Index This encoding may be used by software to ini tialize the entire instruction or data caches by stepping through all valid indices Doing so requires that the TagLo and TagHi registers associated with the cache be initialized first set the state of the cache block to invalid This encoding may be used by software to inval idate a range of addresses from the instruction cache by stepping through the address range by the line size of the cache I S T All Unspecified I D Hit Invalidate Address If the cache block contains the specified address S T Address 218 MIPS32 M4K Processor Cor
178. ck cycles in worst case to complete Early in to the algorithm detects sign extension of the dividend if it is actual size is 24 16 or 8 bit the divider will skip 7 15 or 23 of the 32 iterations An attempt to issue a subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide operation is completed The area efficient non pipelined MDU consists of a 32 bit full adder result accumulation registers HI and LO a combined multiply divide state machine and all multiplexers and control logic required to perform these functions It performs any multiply using 32 cycles in an iterative 1 bit per clock algorithm Divide operations are also imple mented with a simple 1 bit per clock iterative algorithm no early in and require 35 clock cycles to complete An attempt to issue a subsequent MDU instruction while a multiply divide is still active causes a pipeline stall until the operation is completed The M4K implements an additional multiply instruction MUL which specifies that lower 32 bits of the multiply result be placed in the register file instead of the HI LO register pair By avoiding the explicit move from LO MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Two instructions multiply add MADD MADDU and multiply subtract MSUB MSUBU are used to perform the multiply add and multiply sub
179. ck to 1 4 of the core clock the trace probe clock always runs at a double data rate multiple to the core clock See 8 14 3 1 Probe Width and Clock Ratio Settings for a description of probe width and clock ratio options The com bination between the probe width 4 8 or 16 and the data speed allows for data rates through the trace probe from 256 bits per core clock cycle down to only 1 bit per core clock cycle The high extreme is not likely to be supported in any implementation but the low one might be The data rate is an important figure when the likelihood of a TCB fifo overflow is considered The TCB will at maxi mum produce one full 64 bit TW per core clock cycle This is true for any selection of trace mode in TraceControlyopg or TCBCONTROLAyopg The PDtrace module will guarantee the limited amount of data If the TCB data rate cannot be matched by the off chip probe width and data speed then the TCB fifo can possibly over flow There is only one way to handle this 1 Prevent the overflow by asserting a stall signal back to the core PD StallSending This will in turn stall the core pipeline There is no way to guarantee that this back stall from the TCB is never asserted unless the effective data rate of the Trace Probe interface is at least 64 bits per core clock cycle MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 15 TCB On Chip Trac
180. code sequence performs a data cache Index Store Tag operation using the index passed in GPR a0 Li al 0x80000000 Base of kseg0 segment or a0 a0 al Convert index to kseg0 address cache DCIndexStTag 0 a1 Perform the index store tag operation MIPS32 M4K Processor Core Software User s Manual Revision 02 03 219 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Load Linked Word LL 220 31 26 25 21 20 16 15 0 LL 110000 base rt offset 6 5 5 16 Format LL rt offset base MIPS32 Purpose Load Linked Word To load a word from memory for an atomic read modify write Description GPR rt memory GPR base offset The LL and SC instructions provide the primitives to implement atomic read modify write RMW operations for synchronizable memory locations The contents of the 32 bit word at the memory location specified by the aligned effective address are fetched and written into GPR rt The 16 bit signed offset is added to the contents of GPR base to form an effective address This begins a RMW sequence on the current processor There can be only one active RMW sequence per processor When an LL is executed it starts an active RMW sequence replacing any other sequence that was active The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomically and suc ceeds or does not and fails Executing LL on one processor does not cau
181. ction breakpoints IBS Register Format 31 30 29 28 27 24 23 6 5 0 Res ASIDsup Res BCN Res BS Table 8 3 BS Register Field Descriptions Fields je Read Wr Name Bit s Description ite Reset State Res 31 Must be written as zero returns zero on read R 0 ASIDsup 30 Indicates that ASID compare is supported in instruction R 0 breakpoints 0 No ASID compare 1 ASID compare IBASIDn register implemented Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of instruction breakpoints implemented R 2 4 or 6 Res 23 6 Must be written as zero returns zero on read R 0 134 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 3 BS Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State BS 5 0 Break status for breakpoint n is at BS n with n from 0 R W Undefined to 5 The bit is set to 1 when the condition for the corre sponding breakpoint has matched and BCnrg or IBCngg are set a Based on actual hardware implemented b In case of fewer than 6 Instruction breakpoints the upper bits become reserved 8 2 7 2 Instruction Breakpoint Address n BAn Register 0x1100 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Addres
182. ction Field function bits 2 0 bits 5 3 0 000 1 001 2 010 3 5011 4 100 5 6 7 101 110 111 Table 10 3 Special2 Opcode Encoding of Function Field function bits 2 0 000 1 CorExtend instructions are a build time option of the M4K Pro core if not implemented this instructions space will cause a reserved instruction exception If assembler support exists the mnemonics for CorExtend instructions are most likely UDIO UDI UDI15 208 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 10 2 M4K Opcode Map Table 10 4 Special3 Opcode Encoding of Function Field function bits 2 0 RIRIRIRIRjRIj Ry Ryel r BLITZ BGEZ TGEI TGEIU BLTZAL BGEZAL Q Q 1 The core will treat the entire row as a BC2 instruction However compiler and assembler support only exists for the first one Some compiler and assembler products may allow the user to add new instructions Table 10 7 COP2 Encoding of rt Field When rs BC2 BC2T BC2TL MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 209 M4K Processor Core Instructions bits 23 21 Table
183. ction not seeing a Timer Interrupt Compare 4 update that clears Timer Interrupt MTCO gt Instruction affected by change Any other CPO 2 register 1 This is the minimum value Actual value is system dependent since it is a function of the sequential logic between the S Timerlnt output and the external logic which feeds S _ Timerlnt back into one of the S Int inputs or a function of the method for handling SI Timerlntin an external interrupt controller 2 11 1 2 Instruction Hazards Instruction hazards are those created by the execution of one instruction and seen by the instruction fetch of another instruction Table 2 7 lists instruction hazards Table 2 7 Instruction Hazards Spacing Producer Consumer Hazard On Instructions MTCO gt Instruction fetch seeing the new value including a change to ERL fol Status lowed by an instruction fetch from the useg segment 40 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 11 Hazards Table 2 7 Instruction Hazards Continued Spacing Producer gt Consumer Hazard On Instructions Instruction stream gt Instruction fetch seeing the new instruction stream Cache entries 3 write via redi rected store 2 11 2 Instruction Listing Table 2 8 lists the instructions designed to eliminate hazards See the document titled MIPS32 Architecture for Pro grammers Vol
184. d EIC interrupt mode shadow set If Config3ypyc is 1 EIC interrupt mode is enabled this field is loaded from the external interrupt controller for each interrupt request and is used in place of the SRSMap register to select the current shadow set for the interrupt See 4 3 1 3 External Interrupt Controller Mode on page 63 for a discussion of EIC interrupt mode If Config3ygic is 0 this field must be written as zero and returns zero on read Must be written as zeros returns zero on read Exception Shadow Set This field specifies the shadow set to use on entry to Kernel Mode caused by any excep tion other than a vectored interrupt The operation of the processor is UNDEFINED if soft ware writes a value into this field that is greater than the value in the HSS field 11 10 Must be written as zeros returns zero on read 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 9 SRSCtl Register Field Descriptions Continued Fields Read Wr Reset Name Bits Description ite State Previous Shadow Set If GPR shadow registers are 0 implemented and with the exclusions noted in the next paragraph this field is copied from the CSS field when an exception or interrupt occurs An ERET instruction copies this value back into the CSS field if Statusggy 0 This field is
185. d RTOS process the qualified instruction breakpoints are disabled Alternatively with the Invert ValueMatch feature of the data breakpoint the instruction breakpoints could be enabled on any process ID other than the specified one MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 4 Test Access Port TAP e The qualifying data break must have DBCnrg or DBC Crncpe set e The qualifying data break should have data comparison enabled via settings of DBCnp m and DBCngy e The qualifying data break should not have pass counters priming conditions or tuples enabled The qualifying data access can be either a load or store depending on the settings of DBCNyosg and DBCnyo p e The Qualified Unqualified state is stored with the instruction breakpoint that is being qualified Writing it s IBCCn register will unqualify that breakpoint e Qualified instruction breakpoint can also have priming conditions and or pass counters enabled The pass counter will only decrement when the priming and qualifying conditions have been met The instruction breakpoint action break trigger or complex enable will only occur when all priming qualifying and pass counter condi tions have been met e Qualified instruction breakpoint can be used to prime another breakpoint 8 3 7 Usage of Stopwatch Timers The stopwatch timer is a drseg memory mapped count register It
186. d to herein are the property of their respective owners Template nB1 01 Built with tags 2B MIPS32 PROC MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Table of Contents Chapter 1 Introduction to the MIPS32 amp M4K Processor Core csssssseeceeeeessseeeeeneeeeseeeeeneeseeneees 13 Tel RCAC Emm 14 t2 MAK Gore BIOCK DIAG lat ossia eet tote aee Fossa o sert ttu tei asm duse PIU DIDI IE 16 Te i Required Logie BIGGKS e UU 17 12 2 Optional Logie BIOGKS xoi port eie pannosdend eb hanteeaneare e epp eser E a o 21 Ghapter2 Pipeline or the MIK M Ci cae reo eben tutta pecho cuo rrui uta Ru naaa araoa ruentes oar cha te onines 23 ZIS Pipeliie Stag S Aae E EEE E ect crrern nr rece errr ten mre re emer errr tree 23 Ze ltl Stage Instrictioni FOtClas toiles etes puni E A A bendeecdiadvagedtasede 24 2 2 E Staget EXoCUBOTTS nic cn a aaa AE AAGO Gia EAT 25 v poules sien aa a R N 25 2 12 t3ge AM erae E E E E a teta ord a dE 25 zx Moms Stage Wite DAK esris E R EE 26 2 2 M ltiply Divide Opeta t N S scic22cetatstsasieesdccedpcaataceimacstpcucnestace QR o eR Ua Ep UE Est TEE siangueaaceeneuersdanianeneslennieada 26 2 9 MDU Pipeline High Performance MIU iioi na a a 26 2 940 92 16 Multiply High Periormance MDU sso duceno dedu anea a Sp ete rui echec 29 2 3 2 92x32 Multiply Migh Perormance MDU srianan aenea E baredianguraaetieacy 29 2 3 3
187. de field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 24 DEPC Register Format 31 0 DEPC Table 5 27 DEPC Register Formats Fields Read Wr Name Bit s Description ite Reset The DEPC register is updated with the virtual address of Undefined the instruction that caused the debug exception If the instruction is in the branch delay slot then the virtual address of the immediately preceding branch or jump instruction is placed in this register Execution of the DERET instruction causes a jump to the address in the DEPC 5 2 24 ErrorEPC CPO Register 30 Select 0 The ErrorEPC register is a read write register similar to the EPC register except that ErrorEPC is used on error exceptions All bits of the ErrorEPC register are significant and must be writable It is also used to store the program counter on Reset Soft Reset and nonmaskable interrupt NMI exceptions The ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error This address can be e The virtual address of the instruction that caused the exception e The virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot Unlike the EPC register there is no corresponding branch delay slot indication for the ErrorEPC register In processors that implement the MIPS16e ASE a read of t
188. de offs Each trace word can typically store about 20 to 30 instructions so a 1 KWord trace memory could store the history of 20K to 30K executed instructions 8 8 5 ITCB IFlowTrace Interface The ITCB includes a drseg memory interface to allow the MIPS CPU to set up tracing and read current status There are two drseg register locations in the ITCB as shown in Table 8 34 172 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 8 iFlowtrace Mechanism Table 8 34 Registers in the ITCB drseg Location Defined Offset Register Bits Code Description Ox3FCO Control Status 0 ON Software control of trace collection 0 disables all collection and flushes out any partially filled trace words 1 EN Trace enable This bit may be set by software or by Trace on Trace off action bits caused by EJTAG hardware breaks Software writes EN with the desired initial state of tracing when the ITCB is first turned on and EN is controlled by hardware thereafter EN turning on and off does not flush partly filled trace words 2 IO Inhibit overflow If set the CPU is stalled whenever the trace memory is full Ignored unless OfC is also set 3 OfC Offchip 1 enables the PIB if present to unload the trace memory 0 disables the PIB and would be used when on chip storage is desired or if a PIB is not present The M4K core only supports off chip storage so this b
189. dify write Description if atomic update then memory GPR base offset GPR rt GPR rt 1 else GPR rt lt 0 The LL and SC instructions provide primitives to implement atomic read modify write RMW operations for syn chronizable memory locations The 32 bit word in GPR rt is conditionally stored in memory at the location specified by the aligned effective address The 16 bit signed offset is added to the contents of GPR base to form an effective address The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor To complete the RMW sequence atomically the following occur e The 32 bit word of GPR rt is stored into memory at the location specified by the aligned effective address e A 1 indicating success is written into GPR rt Otherwise memory is not modified and a 0 indicating failure is written into GPR rt On the M4K core the SRAM interface supports a lock protocol and the success or failure can be indicated by external hardware If the following event occurs between the execution of LL and SC the SC fails e An ERET instruction is executed If either of the following events occurs between the execution of LL and SC the SC may succeed or it may fail the success or failure is not predictable Portable programs should not cause one of these events e A memory access instruction load store or prefetch is executed on the processor executing the LL SC e The instructions
190. dresses for Data Breakpoint Registers ecceecesencceeeeeeeneeeeeeeeeeeeseeeaaeeeeeeeaaaeeeseeeaeneeeneeseenenees 138 Table 89 9 JBPCn Register Field Descriptions s istos Ee esa tiit a ER en etri reet n ce RI Le n E 138 Table 8 11 DBS Register Field Descriptions coco ooi E tie TO Saee UE ER Posh Pea tes SP asi dEROs 139 Table 8 12 DBAn Register Field DeScrpUOnssa eno ppp repente erts o aia aa narea raa 139 Table 8 13 DBMn Register Field Descriptions sessist E E nennen tent nnns ntn 140 Table 8 34 DBASIDn Register Field Descriptions uo icit ree eere hoo rea et Este tepal eese Pese c a E a a e dE 140 Table 8 15 DBCn Register Field Desetpliofnsiss ie soesqoni vicina ede or tos Eos s RE SUI URNA icc de eR O RE 141 Table 8 16 DBVn Register Field Descriptions rep pid eene trt pote Ct rx pera ba E Rte ka ER E KENNARANN 142 Table 8 17 DBCCr Register Field Descriptions itr idit een atri tede netos ier edin Rin tenb dne EEA 142 Table 8 18 DBPCn Register Field DesctiptiOris sacco inerneta 143 Table 819 DVM Register Field DescriptiORis merrnin aAA cathe Eo ERR SER a SepPa Sun DESEE EROS 144 Table 8 20 Addresses for Complex Breakpoint Registers sesssssssssssseeeeeenn nennen 144 Table 8 21 CBTC Register Field DescripllOris sao uio iret aa nens Mr t En dM e E dacP SEM RM URS 145 Table 8 23 Priming Conditions and Register ValuBs rese troupe posten Er aean AaS 146 Table 8 22 PrCndA Register Field Desc
191. e However if an About trigger has started the count down from n 2 but not yet reached zero then a new About trigger will NOT be executed Only one About trigger can have the cycle counter This second About trigger will store 11 in the TCBTRIGXy field But if the TCBTRIGXTrace bit is set a TF6 trace information will still go in the trace 8 13 5 2 OR ed Trigger Actions The simple trigger actions CHTro and PDTro from each trigger unit are effectively OR ed together to produce the final trigger One or more expected trigger strobes on i e TC_ChipTrigOut can thus disappear External logic should not rely on counting of strobes to predict a specific event unless simultaneous triggers are known not to occur 8 14 EJTAG Trace Cycle by Cycle Behavior A key reason for using trace and not single stepping to debug a software problem is often to get a picture of the real time behavior However the trace logic itself can when enabled affect the exact cycle by cycle behavior 8 14 1 Fifo Logic in PDtrace and TCB Modules Both the PDtrace module and the TCB module contain a fifo This might seem like extra overhead but there are good reasons for this The vast majority of the information compression happens in the PDtrace module Any data informa tion like PC and load store address values delta or full load store data and processor mode changes are all sent on the same 16 data bus to the TCB on the PDtrace interface When an instructio
192. e Trace is turned off when the following expression evaluates true MIPS32 M4K Processor Core Software User s Manual Revision 02 03 195 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core TraceControlpg and not TraceControlo or not TraceControlpg and not TCBCONTROLAg or not MatchEnable and not TriggerEnable and TriggerDisable where TriggerDisable c DBCicg and DBS 14 and TraceBPCpg and TraceBPCpgpon i 0 or IBCigg and IBSgs i and TraceBPCig and TraceBPCrpponji 0 Tracing can be unconditionally turned off by de asserting the TraceControlo bit or the TCBCONTROLAo signal When either of these are asserted tracing can be turned off if all of the enables are de asserted EJTAG hardware breakpoints can be used to trigger trace off as well Note that if simultaneous triggers are generated and even one of them turns on tracing then even if all of the others attempt to trigger trace off then tracing will still be turned on This condition is reflected in presence of the not TriggerEnable term in the expression above 8 12 4 TCB Trace Enabling The TCB must be enabled in order to produce a trace on the probe or to on chip memory when trace information is sent on the PDtrace interface The main switch for this is the TCBCONTROLBEgy bit When set the TCB will send trace information to either on chip t
193. e CE field is loaded but not defined for any exception type other than a coprocessor unusable exception e The EXL bit is set in the Status register e The processor is started at the exception vector The value loaded into EPC represents the restart address for the exception and need not be modified by exception handler software in the normal case Software need not look at the BD bit in the Cause register unless it wishes to identify the address of the instruction that actually caused the exception Note that individual exception types may load additional information into other registers This is noted in the descrip tion of each exception type below Operation If Statusgy is 1 all exceptions go through the general exception vector and neither EPC nor Causegy nor SRSCtl are modified if Statusgyy 1 then vectorOffset c 1614180 else if InstructionInBranchDelaySlot then else EPC restartPC PC of branch jump Causegp amp 1 EPC lt restartPC PC of instruction Causegp 0 endif Compute vector offsets as a function of the type of exception NewShadowSet lt SRSCtlgss Assume exception Release 2 only if ExceptionType TLBRefill then MIPS32 M4K Processor Core Software User s Manual Revision 02 03 69 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core vectorOffset c 16 000 elsei
194. e Memory As a practical matter the amount of data to the TCB can be minimized by only tracing PC information and excluding any cycle accurate information This is explained in 8 14 2 Handling of Fifo Overflow in the PDtrace Module and below in 8 14 4 Adding Cycle Accurate Information to the Trace With this setting a data rate of 8 bits per core clock cycle is usually sufficient No guarantees can be given here however as heavy interrupt activity can increase the number of unpredictable jumps considerably 8 14 3 1 Probe Width and Clock Ratio Settings The actual number of data pins 4 8 or 16 is defined by the TCBCONFIGpw field Furthermore the frequency of the Trace Probe can be different from the core clock frequency The trace clock TR_CLK is a double data rate clock This means that the data pins TR_DATA change their value on both edges of the trace clock When the trace clock is running at clock ratio of 1 2 one half of core clock the data output registers are running a core clock fre quency The clock ratio is set in the TCBCONTROLBcp field The legal range for the clock ratio is defined in TCBCONFIGermax and TCBCONFIG cgyji both values inclusive If TCBCONTROLBc is set to an unsup ported value the result is UNPREDICABLE The maximum possible value for TCBCONFIGcrmax is 8 1 TH CLK is running 8 times faster than core clock The minimum possible value for TCBCONFIGecpgmin is 1 8 TR CLKis running at one eighth
195. e Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Perform Cache Operation CACHE Table 10 3 Encoding of Bits 20 18 of the CACHE Instruction Continued Effective Address Operand Code Caches Type Operation D Address This encoding may be used by software to inval S T Address idate a range of addresses from the data cache by stepping through the address range by the line size of the cache 0b110 D Address S T Address Restrictions The operation of this instruction is UNDEFINED for any operation cache combination that is not implemented The operation of this instruction is UNDEFINED if the operation requires an address and that address is uncache able If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled Operation vAddr lt GPR base sign extend offset pAddr uncached AddressTranslation vAddr DataReadReference CacheOp op vAddr pAddr Exceptions TLB Refill Exception TLB Invalid Exception Coprocessor Unusable Exception Programming Notes For cache operations that require an index it is implementation dependent whether the effective address or the trans lated physical address is used as the cache index Therefore the index value should always be converted to a ksegO address by ORing the index with 0x80000000 before being used by the cache instruction For example the following
196. e Value IS1 Additional State Saved Depending on the coprocessor 2 implementation additional state information of the exception can be saved in a coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 17 Execution Exception Integer Overflow The integer overflow exception is one of the nine execution exceptions All of these exceptions have the same priority An integer overflow exception occurs when selected integer instructions result in a 2 s complement overflow Cause Register ExcCode Value Ov Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 18 Execution Exception Trap The trap exception is one of the nine execution exceptions All of these exceptions have the same priority A trap exception occurs when a trap instruction results in a TRUE value Cause Register ExcCode Value Tr Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 19 Debug Data Break Exception A debug data break exception occurs when a data hardware breakpoint matches the load store transaction of an exe cuted load store instruction The DEPC register and DBD bit in the Debug register will indicate the load store instruction that caused the data hardware breakpoint to match The load store instruction that caused the debug excep tion has not completed e g not updated the register file and the instruction can
197. e by cycle change whether trace is turned on or not This is achieved at the cost of potentially losing trace information After an overflow the fifo is completely emptied and the next instruction is traced as if it was the start of the trace processor mode and full PC are traced This guarantees that only the un traced fifo information is lost The second option guarantees that all the trace information is traced to the TCB In some cases this is then achieved by back stalling the core pipeline giving the PDtrace fifo time to empty enough room in the fifo to accept new trace information from a new instruction This option can obviously change the real time behavior of the core when tracing is turned on If PC trace information is the only thing enabled in TraceControlyopg or TCBCONTROLAyopg depending on the setting of TraceControlgs and Trace of all branches is turned off via TraceControlyg or TCBCONTROLA gp depending on the setting of TraceControl s then the fifo is unlikely to overflow very often if at all This is of course very dependent on the code executed and the frequency of exception handler jumps but with this setting there is very little information overhead 8 14 3 Handling of Fifo Overflow in the TCB The TCB also holds a fifo used to buffer the TW s which are sent off chip through the Trace Probe The data width of the probe can be either 4 8 or 16 pins and the speed of these data pins can be from 16 times the core clo
198. e that this cycle is spent even if the remainder was positive A sign adjust is performed on the quotient and or remainder if necessary The sign adjust stage is skipped if both operands are positive In this case the Rem Adjust is moved to the Aypy stage Figure 2 6 Figure 2 7 Figure 2 8 and Figure 2 9 show the latency for 8 16 24 and 32 bit divide operations respec tively The repeat rate is either 11 19 27 or 35 cycles one less if the sign adjust stage is skipped as a second divide can be in the RS Adjust stage when the first divide is in the Reg WR stage Figure 2 6 High Performance MDU Pipeline Flow During a 8 bit Divide DIV Operation Clock 1 2 3 4 10 11 12 13 E Stage Mypy Stage Mypy Stage Mmpu Stage gt Mmpu Stage Ampu Stage Wmpu Stage gt RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 7 High Performance MDU Pipeline Flow During a 16 bit Divide DIV Operation Clock 1 2 3 4 18 19 20 21 Estage P4 Munu Stage P Mupu Stage P Mupu Stage 4 Mupu Stage 4 Ampu Stage P Wunu Stage gt RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In 30 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 4 MDU Pipeline Area Efficient MDU Figure 2 8 High Performance MDU Pipeline Flow During a 24 bit Divide
199. e the exception base register to 16488000 0000 providing backward compatibility with Release 1 implementations Bits 31 30 of the EBase Register are fixed with the value 2410 to force the exception base address to be in the kseg0 or ksegl unmapped virtual address segments If the value of the exception base register is to be changed this must be done with Statusggy equal 1 The operation of the processor is UNDEFINED if the Exception Base field is written with a different value when Statusppy is 0 Combining bits 31 20 with the Exception Base field allows the base address of the exception vectors to be placed at any 4KByte page boundary If vectored interrupts are used a vector offset greater than 4KBytes can be generated In this case bit 12 of the Exception Base field must be zero The operation of the processor is UNDEFINED if soft ware writes bit 12 of the Exception Base field with a 1 and enables the use of a vectored interrupt whose offset is greater than 4KBytes from the exception base address Figure 5 12 shows the format of the EBase Register Table 5 16 describes the EBase register fields Figure 5 12 EBase Register Format 31 30 29 12 11 10 9 0 1 0 Exception Base 00 CPUNum Table 5 16 EBase Register Field Descriptions Fields Read Name Bits Description Write Reset State This bit is ignored on write and returns zero on read Exception In conjunction with bits 31 30 this field s
200. echnologies Inc All rights reserved 221 Prefetch PREF 222 31 26 25 21 20 16 15 0 PREF 110011 base hint offset 6 5 5 16 Format PREF hint offset base MIPS32 Purpose Prefetch To move data between memory and cache Description prefetch_memory GPR base offset PREF adds the 16 bit signed offset to the contents of GPR base to form an effective byte address The hint field sup plies information about the way that the data is expected to be used PREF does not cause addressing related exceptions including TLB exceptions If the address specified would cause an addressing exception the exception condition is ignored and no data movement occurs However even if no data is moved some action that is not architecturally visible such as writeback of a dirty cache line can take place It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct of the action taken by the PREF instruction PREF neither generates a memory operation nor modifies the state of a cache line for a location with an uncached memory access type whether this type is specified by the address segment e g kseg1 the programmed coherency attribute of a segment e g the use of the KO KU or K23 fields in the Config register or the per page coherency attribute provided by the TLB If PREF results in a memory operation the memory access type and coherency at
201. ecimal in the M4K cores since no TLB is present This field contains the number of instruction cache sets per way Since the M4K core does not include caches this field is always read as 0 This field contains the instruction cache line size Since the MAK core does not include caches this field is always read as 0 18 16 This field contains the level of instruction cache associativ R 0 ity Since the M4K core does not include caches this field is always read as 0 106 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 18 Config1 Register Field Descriptions Select 1 Continued Fields Read Wri Name i Description te Reset State This field contains the number of data cache sets per way Since the M4K core does not include caches this field is always read as 0 This field contains the data cache line size Since the M4K core does not include caches this field is always read as 0 This field contains the type of set associativity for the data cache Since the M4K core does not include caches this field is always read as 0 Coprocessor 2 present Preset 0 No coprocessor is attached to the COP2 interface 1 A coprocessor is attached to the COP2 interface If the Cop2 interface logic is not implemented this bit will read 0 MDMxX implemented This bi
202. ection 10 3 MIPS32 Instruction Set for the M4K core The M4K processor core also supports the MIPS16 ASE to the MIPS32 architecture The MIPS16 ASE instruction set is described in Chapter 11 MIPS16e Application Specific Extension to the MIPS32 Instruction Set on page 229 10 1 Understanding the Instruction Descriptions Refer to Volume II of the MIPS32 Architecture Reference Manual for more information about the instruction descrip tions There is a description of the instruction fields definition of terms and a description function notation available in that document 10 2 M4K Opcode Map Key e CAPITALIZED text indicates an opcode mnemonic e Italicized text indicates to look at the specified opcode submap for further instruction bit decode e Entries containing the symbol indicate that a reserved instruction fault occurs if the core executes this instruc tion e Entries containing the B symbol indicate that a coprocessor unusable exception occurs if the core executes this instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 207 Copyright 2002 2008 MIPS Technologies Inc All rights reserved M4K Processor Core Instructions Table 10 1 Encoding of the Opcode Field opcode bits 28 26 110 Special BLEZ ADDI XORI P p BEQL BNEL BLEZL a o o o Sw aan o LBU LWR SWR a a Table 10 2 Special Opcode encoding of Fun
203. ecturally optional On the MAK core the VEIC bit is set externally by the static input S _E CPresent to allow system logic to indicate the presence of an external interrupt controller The reset state of the processor is to interrupt compatibility mode such that a processor supporting Release 2 of the Architecture like the M4K core is fully compatible with implementations of Release 1 of the Architecture MIPS32 M4K Processor Core Software User s Manual Revision 02 03 57 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 58 Table 4 2 shows the current interrupt mode of the processor as a function of the coprocessor 0 register fields that can affect the mode Table 4 2 Interrupt Modes elo l gt o 2 u 2g PES o o0 2 2 92 2 2 S S 15 5 o 616 Interrupt Mode 1 x x x x Compatibly x JO x x x Compatibility x 0 x x Compatibility z0 x 1 ojojoj x denotes don t care Vectored Interrupt External Interrupt Controller Can t happen IntCtlys can not be non zero if neither Vectored Interrupt nor External Interrupt Controller mode is implemented 4 3 1 1 Interrupt Compatibility Mode This is the default interrupt mode for the processor and is entered when a Reset exception occurs In this mode inter rupts are non vectored and dispatched though exception vector offset 1648180 if Cau
204. ecute a CorExtend instruction when Sta tuscpg is cleared It is implementation dependent whether this functionality is supported Generally the functionality will only be supported if a CorExtend block contains local destination registers Cause Register ExcCode Value CEU Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 15 Execution Exception Coprocessor 2 Exception The Coprocessor 2 exception is one of the nine execution exceptions All of these exceptions have the same priority A Coprocessor 2 exception occurs when a valid Coprocessor 2 instruction cause a general exception in the Coproces sor 2 Cause Register ExcCode Value C2E Additional State Saved Depending on the Coprocessor 2 implementation additional state information of the exception can be saved in a Coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 16 Execution Exception Implementation Specific 1 Exception The Implementation Specific 1 exception is one of the nine execution exceptions All of these exceptions have the same priority An implementation specific 1 exception occurs when a valid coprocessor 2 instruction cause an imple mentation specific 1 exception in the Coprocessor 2 MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 8 Exceptions Cause Register ExcCod
205. ed
206. ed from the Trace Control Block TCB see 8 11 Trace Control Block TCB Registers Hardware Control on page 180 As such these fields in the TraceControl2 register will not have valid values until the TCB asserts these Valid TB 9 Modes TBI U SyP 114 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 23 TraceControl2 Register Field Descriptions Fields Read Name Bits Description Write Reset State 0 31 5 Reserved for future use Must be written as zero 0 0 returns zero on read ValidModes 6 5 This field specifies the type of tracing that is supported R 10 by the processor as follows Encoding Meaning 00 PC tracing only 01 PC and load and store address tracing only 10 PC load and store address and load and store data 11 Reserved TBI 4 This bit indicates how many trace buffers are imple R Per imple mented by the TCB as follows mentation Encoding Meaning 0 Only one trace buffer is implemented and the TBU bit of this register indicates which trace buffer is implemented 1 Both on chip and off chip trace buffers are implemented by the TCB and the TBU bit of this register indicates to which trace buffer the trace is currently written TBU 3 This bit denotes to which trace buffer the trace is cur R Undefined
207. ed to hold their present state during the Capture and Shift operations The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update DR or Update IR state The Update state causes the shadow latches to update or parallel load with the new data that has been shifted into the selected scan path Figure 8 1 TAP Controller State Diagram PLZ 0 0 GA RunTestide E Select DR Scan H 1 0 0 ap 1 Exitl IR Exitl DR 0 CDI 1 o Exi DR Exit2 IR Update DR Update IR 1 0 m mum eo 8 4 2 1 Test Logic Reset State In the Test Logic Reset state the boundary scan test logic is disabled The test logic enters the Test Logic Reset state when the 7MS input is held HIGH for at least five rising edges of TCK The BYPASS instruction is forced into the instruction register output latches during this state The controller remains in the 7est Logic Reset state as long as TMS is HIGH MIPS32 M4K Processor Core Software User s Manual Revision 02 03 153 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 154 8 4 2 2 Run Test Idle State The controller enters the Run Test Idle state between scan operations The controller remains in this state as long as TMS is held LOW The instruction register and all test data registers retain their previous state The instruction cannot change w
208. eeeeeeneeeeeeeeeeeeeeseeeeeeeeaeseseeeeseaeeneeeeeess 177 8 9 6 Programmable Trace Information Options sseessesssssseesesee eene tn nnne oia 177 8 9 7 Enable Trace to Probe On Chip Memory eessssssssssseseeesees essen nennen snnt nnn tent nsns snnt n nn 178 8 99 TCB THOG melt iiec tuere a ree Proce eto Ds ad tue reenter rere ter ree rer 178 9 9 9 Oycle by Cycle IMi ormat Oi x cota siete dE MEE ue tue coe rp Den Dem ocio d E ist rete mE REUS aiaieeinte 179 8 940 Trace Message FORMAL soe For erepto rho obe iet exe Eb eao edan aaie ai 179 Bod Tace WOO FOUNIGU c n eiqp avt treno QUY MESE Qa DEuan UD acd Mu ME UD D dtes dri Mc M I Bes ed 179 8 10 PDirace Registers Sottwate CODIFOD s uie ioo te a betae ond aptata eat text ecue tiu etanciu RL 179 8 11 Trace Control Block TCB Registers Hardware Control 180 Pm TCBCONTAOLA ioci CES 180 811 2 TCBCONTROLB Register E 183 mpECHNIGIBA NPIM Isi 187 Bart TCBGONEIG Register Reg O s osapece cin eremo ete xU SERES Des Ur telo ite Reap aden Ded UE EERES 188 8 15 TER TW Registen Reg 4 T aa an iaaa naa 189 811 6 TCBRDP Register Rag D isori a a RE 190 eik TCBWRP Register Reg 6 i siete ctiani usas tust et at etesc et ebueo grt A certubta duaceeaaneneneenies 190 Bag TCBSTPRegisterdRet oce esit a Dena tetesauk etae n ie NNA d v epic cddsa aui De uU ies 190 8 T5 9 TOCBTRHIGX Begister Reg 16 23 rsrs tereti ed eR Rpaaeeu er tures rur Epo pc aaran 191 8 11
209. egisters selected with the FASTDATA instruction allow efficient completion of pending Fastdata area accesses During Fastdata uploads and downloads the processor will stall on accesses to the Fastdata area The PrAcc proces sor access pending bit will be 1 indicating the probe is required to complete the access Both upload and download accesses are attempted by shifting in a zero SPrAcc value to request access completion and shifting out SPrAcc to see if the attempt will be successful i e there was an access pending and a legal Fastdata area address was used Downloads will also shift in the data to be used to satisfy the load from dmseg s Fastdata area while uploads will shift out the data being stored to dmseg s Fastdata area As noted above two conditions must be true for the Fastdata access to succeed These are e PrAcc must be 1 i e there must be a pending processor access e The Fastdata operation must use a valid Fastdata area address in dmseg 0xFF20 0000 to OxFF20 000F Table 8 32 shows the values of the PrAcc and SPrAcc bits and the results of a Fastdata access Table 8 32 Operation of the FASTDATA access PrAcc in Address the LSB PrAcc LSB Probe Match Control SPrAcc Action in the changes shifted Data shifted Operation check Register shifted in Data Register to out out Download Fails X X none unchanged 0 invalid using FASTDATA Passes 1 1 none unchanged 1 invalid 1 0 write data 0 SPrAcc 1 va
210. ent stores a dynamically determined delta to the previous store address is traced l A SC Store Conditional instruction is not flagged as a store instruction if the load locked bit prevented the actual store 176 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 9 EJTAG Trace e When load data tracing is on the full load data read by each load instruction is traced indicated by the load flag Only actual read bytes are traced e When store data tracing is on the full store data written by each store instruction is traced indicated by the store flag Only written bytes are traced After each synchronization instruction the first load address and the first store address following this are both traced with the full address if load store address tracing is enabled 8 9 5 Programmable Processor Trace Mode Options To enable tracing a global Trace On signal must be set When trace is on it is possible to enable tracing in any com bination of the processor modes described in 8 9 1 Processor Modes on page 175 Additionally an EJTAG Simple Break trigger point can override the processor mode and turn them all on Another trigger point can disable this override again 8 9 6 Programmable Trace Information Options The processor mode changes are always traced e On the first instruction e On any synchronization instruction e When the mode cha
211. entically so the hardware reset value of these fields need not be modified MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 6 2 Software Initialized Processor State e Count Should be set to a known value if Timer Interrupts are used e Compare Should be set to a known value if Timer Interrupts are used The write to compare will also clear any pending Timer Interrupts Thus Count should be set before Compare to avoid any unexpected interrupts e Status Desired state of the device should be set e Other COPO state Other registers should be written before they are read Some registers are not explicitly write able and are only updated as a by product of instruction execution or a taken exception Uninitialized bits should be masked off after reading these registers MIPS32 M4K Processor Core Software User s Manual Revision 02 03 123 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Hardware and Software Initialization of the M4K Core 124 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 7 Power Management of the M4K Core A MAK processor coreoffers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAI
212. eption e A store transaction is not allowed to complete the store to the memory system e A load transaction with no data value compare i e where the DB no value compare is true for the match is not allowed to complete the load e A load transaction for a breakpoint with data value compare must occur from the memory system since the value is required in order to evaluate the breakpoint The result of this is that the load or store instruction causing the debug data break exception appears as not executed with the exception that a load from the memory system does occur for a breakpoint with data value compare but the register file is not updated by the load If both data breakpoints without and with data value compare would match the same transaction and generate a debug exception then the following rules apply with respect to updating the BS n bits e On both a load and store the BS n bits are required to be set for all matching breakpoints without a data value compare e Onastore the BS n bits are allowed but not required to be set for all matching breakpoints with a data value compare but either all or none of the BS n bits must be set for these breakpoints Onaload then none of the BS n bits for breakpoints with data value compare are allowed to be set since the load is not allowed to occur due to the debug exception from a breakpoint without a data value compare and a valid data value is therefore not returned Any BS
213. ertion of TRST_N The core signal for this is called EJ TRST N This signal is optional but power on reset must apply a low pulse on this signal at power on and then leave it high in case the signal is not available as a pin on the chip If available on the chip then it must be low on the board when the EJTAG debug features are unused by the probe 8 4 2 Test Access Port Operation The TAP controller is controlled by the Test Clock TCK and Test Mode Select TMS inputs These two inputs determine whether an the Instruction register scan or data register scan is performed The TAP consists of a small controller driven by the TCK input which responds to the TMS input as shown in the state diagram in Figure 8 1 The TAP uses both clock edges of TCK TMS and TDI are sampled on the rising edge of TCK while TDO changes on the falling edge of TCK At power up the TAP is forced into the Test Logic Reset by low value on TRST_N The TAP instruction register is thereby reset to IDCODE No other parts of the EJTAG hardware are reset through the Test Logic Reset state When test access is required a protocol is applied via the TMS and TCK inputs causing the TAP to exit the Test Logic Reset state and move through the appropriate states From the Run Test Idle state an Instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown in Figure 8 1 MIPS32 M4K Processor Core Software
214. es code density through the use of 16 bit encodings of MIPS32 instructions plus some MIPS 16e specific instructions PC relative loads allow quick access to constants Save Restore macro instructions provide for single instruction stack frame setup teardown for efficient subroutine entry exit Sign and zero extend instructions improve handling of 8bit and 16bit datatypes A decompressor converts the MIPS16e 16 bit instructions fetched from the external interface back into 32 bit instruc tions for execution by the core 1 2 2 2 EJTAG Controller All cores provide basic EJTAG support with debug mode run control single step and software breakpoint instruction SDBBP as part of the core These features allow for the basic software debug of user and kernel code Optional EJTAG features include hardware breakpoints A M4K core may have up to six instruction breakpoints and two data breakpoints and potentially support for complex breakpoints The hardware instruction breakpoints can be configured to generate a debug exception when an instruction is executed anywhere in the virtual address space Bit mask values may apply in the address compare These breakpoints are not limited to code in RAM like the software instruction breakpoint SDBBP The data breakpoints can be configured to generate a debug exception on a data transaction The data transaction may be qualified with both virtual address data value size and load store transac tion type Bit mask
215. esence of the Config3 register 0 30 0 These bits are reserved R 0 5 2 16 Config3 Register CPO Register 16 Select 3 The Config3 register encodes additional capabilities All fields in the Config3 register are read only Figure 5 17 shows the format of the Config3 register Table 5 20 describes the Config3 register fields Figure 5 17 Config3 Register Format 31 30 9 8 7 6 5 4 3 2 1 0 0 M 000 0000 0000 0000 0000 0000 0 MT 0 VEIG a WE MIL Table 5 20 Config3 Register Field Descriptions NE NN ReadiWr Name Bits Description ite Reset State M This bit is reserved to indicate that a Config4 register is present With the current architectural definition this bit should always read as a 0 0 Must be written as zeros returns zeros on read Indicates that IFlowTrace hardware is present R Preset VEIC 6 Support for an external interrupt controller is imple R Externally Set mented Encoding Meaning 0 Support for EIC interrupt mode is not implemented 1 Support for EIC interrupt mode is implemented The value of this bit is set by the static input SLEICPresent This allows external logic to communi cate whether an external interrupt controller is attached to the processor or not Vint 5 Vectored interrupts implemented This bit indicates R 1 whether vectored interrupts are implemented Encoding Meaning 0 Vector interrupts
216. eserved Table 2 1 lists the latencies number of cycles until a result is available for multiply and divide instructions The 2 3 MDU Pipeline High Performance MDU latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the first instruction to produce the result needed by the second instruction Table 2 1 MDU Instruction Latencies High Performance MDU Size of Operand Instruction Sequence Latency 1st Instruction 1st Instruction 2nd Instruction Clocks 16 bit MULT MULTU MADD MADDU 1 MADD MADDU MSUB MSUBU or MSUB MSUBU MFHI MFLO 32 bit MULT MULTU MADD MADDU 2 MADD MADDU or MSUB MSUBU or MSUB MSUBU MFHI MFLO 16 bit MUL Integer operation 2831 32 bit MUL Integer operation 2B 8 bit DIVU MFHI MFLO 9 16 bit DIVU MFHI MFLO 17 24 bit DIVU MFHI MFLO 25 32 bit DIVU MFHI MFLO 33 8 bit DIV MFHI MFLO 10 41 16 bit DIV MFHI MFLO 18 4 24 bit DIV MFHI MFLO 26 41 32 bit DIV MFHI MFLO 34 4 any MFHI MFLO Integer operation 2 any MTHI MTLO MADD MADDU or 1 MSUB MSUBU 1 For multiply operations this is the rt operand For divide operations this is the rs operand 2 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation 3 This does not include the 1 or 2 IU pipeline stalls 16 bit or 32 bit that the MUL operation causes irre spective of the following instruction These s
217. ess Translation Virtual Address Range Cacheability Ox9FFF_FFFF 0xA000 0000 OxBFFF FFFF useg kuseg 0x0000 0000 Controlled by the KU field bits 27 25 of the Config register Refer to Ox7FFF FFFF Table 3 6 for the encoding kseg0 0x8000_0000 Controlled by the KO field bits 2 0 of the Config register See Table 3 6 for the encoding Always uncacheable kseg2 0xC000_0000 OxDFFF FFFF OxE000 0000 OxFFFF FFFF Controlled by the K23 field bits 30 28 of the Config register Refer to Table 3 6 for the encoding Controlled by K23 field bits 30 28 of the Config register Refer to Table 3 6 for the encoding The FM performs a simple translation to map from virtual addresses to physical addresses This mapping is shown in Figure 3 6 When ERL 1 useg and kuseg become unmapped and uncached The ERL behavior is the same as if there was a TLB The ERL mapping is shown in Figure 3 7 The ERL bit is usually never asserted by software It is asserted by hardware after a Reset SoftReset or NMI See 4 8 Exceptions on page 72 for further information on exceptions Figure 3 6 FM Memory Map ERL 0 in the M4K Processor Core Virtual Address kseg3 OxEOO0 0000 kseg2 OxC000_0000 ksegl 0xAO000 0000 kseg0 0x8000 0000 useg kuseg 0x0000 0000 52 Physical Address kseg3 OxE000_0000 kseg2 OxC000_0000 useg kuseg 0x4000_0000 re
218. est data register connected between TD and T DO as a result of the current instruction shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW on the rising edge of TCK the con troller remains in the Shift DR state A HIGH on TMS causes the controller to transition to the Exit DR state The instruction cannot change while the TAP controller is in this state 8 4 2 7 Exit1 DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Pause DR state A HIGH on TMS causes the controller to transition to the Update DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 8 4 2 8 Pause DR State The Pause DR state allows the controller to temporarily halt the shifting of data through the test data register in the serial path between TD and TDO All test data registers selected by the current instruction retain their previous state If TMS is sampled LOW on the rising edge of TCK the controller remains in the Pause DR state A HIGH on TMS causes the controller to transition to the Exit2 DR state The instruction cannot change while the TAP controller is in this state MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc A
219. et This chapter describes the MIPS16e TM ASE as implemented in the M4K core Refer to lume IV a of the MIPS32 Architecture Reference Manual for a general description of the MIPS16e ASE as well as instruction descriptions This chapter covers the following topics e Section 11 1 Instruction Bit Encoding e Section 11 2 Instruction Listing 11 1 Instruction Bit Encoding Table 11 2 through Table 11 9 describe the encoding used for the MIPS16e ASE Table 11 1 describes the meaning of the symbols used in the tables Table 11 1 Symbols Used in the Instruction Encoding Tables Symbol Meaning Operation or field codes marked with this symbol are reserved for future use Executing such an instruction cause a Reserved Instruction Exception Also italic field name Operation or field codes marked with this symbol denotes a field class The instruction word must be further decoded by examining additional tables that show values for another instruction field B Operation or field codes marked with this symbol represent a valid encoding for a higher order MIPS ISA level Executing such an instruction cause a Reserved Instruction Exception 0 Operation or field codes marked with this symbol are available to licensed MIPS partners To avoid multiple conflicting instruction definitions the partner must notify MIPS Technologies Inc when one of these encodings is used If no instruction is encoded with this value executing such
220. et pAddr CCA AddressTranslation vAddr DATA LOAD Prefetch CCA pAddr vAddr DATA hint Exceptions Bus Error Cache Error Prefetch does not take any TLB related or address related exceptions under any circumstances Programming Notes Prefetch cannot move data to or from a mapped location unless the translation for that location is present in the TLB Locations in memory pages that have not been accessed recently may not have translations in the TLB so prefetch may not be effective for such locations Prefetch does not cause addressing exceptions A prefetch may be used using an address pointer before the validity of the pointer is determined without worrying about an addressing exception It is implementation dependent whether a Bus Error or Cache Error exception is reported if such an error is detected as a byproduct of the action taken by the PREF instruction Typically this only occurs in systems which have high reliability requirements Prefetch operations have no effect on cache lines that were previously locked with the CACHE instruction MIPS32 M4K Processor Core Software User s Manual Revision 02 03 223 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Store Conditional Word SC 224 31 26 25 21 20 16 15 0 SC 111000 base rt offset 6 5 5 16 Format SC rt offset base MIPS32 Purpose Store Conditional Word To store a word to memory to complete an atomic read mo
221. exception is taken This field is loaded by hardware on every exception but is UNPREDICT ABLE for all exceptions except for Coprocessor Unus able MIPS32 M4K Processor Core Software User s Manual Revision 02 03 R Undefined Undefined Undefined 99 CPO Registers of the M4K Core Table 5 12 Cause Register Field Descriptions Continued Fields Read Wri Name Bits Description te Reset State DC 27 Disable Count register In some power sensitive appli R W 0 cations the Count register is not used and is the source of meaningful power dissipation This bit allows the Count register to be stopped in such situations Encoding Meaning 0 Enable counting of Count register 1 Disable counting of Count register PCI 26 Performance Counter Interrupt In an implementation of R 0 Release 2 of the Architecture this bit denotes whether a performance counter interrupt is pending analogous to the IP bits for other interrupt types Encoding Meaning 0 No timer interrupt is pending 1 Timer interrupt is pending Since performance counters are not implemented Configlpe 0 this bit must be written as zero and returns zero on read IV 23 Indicates whether an interrupt exception uses the gen R W Undefined eral exception vector or a special interrupt vector Encoding Meaning 0 Use the general exception vector 165180 1 Use the
222. f ExceptionType Interrupt then if Causey 0 then vectorOffset c 1614180 else if Statusggy 1 or IntCtlyg 0 then vectorOffset c 1613200 else if Config3yg o 1 then VecNum lt Causemgripr NewShadowSet lt SRSCtlgicss else VecNum c VIntPriorityEncoder NewShadowSet lt SRSMapripiX4 3 rprX4 endif vectorOffset 164200 VecNum x IntCtlyg 2400000 endif if Statusggy 1 or IntCtlyg 0 then endif if Cause 0 then endif elseif ExceptionType Interrupt then Update the shadow set information for an implementation of Release 2 of the architecture if ArchitectureRevision 2 2 and SRSCtlygg gt 0 and Statusggy 0 and Statusggy 0 then SRSCtlpgg SRSCtlogg SRSCtlogg NewShadowSet endif endif if Statusgyg 1 then Causecp lt FaultingCoprocessorNumber CauSepyccode ExceptionType Statuspy amp 1 Calculate the vector base address if StatusSggy 1 then vectorBase 164BFC0 0200 else if ArchitectureRevision 2 2 then The fixed value of EBases4 39 forces the base to be in kseg0 or ksegl vectorBase lt EBases4 4 164000 else vectorBase 16 8000 0000 endif endif Exception PC is the sum of vectorBase and vectorOffset PC vectorBases4 39 vectorBases5s 9 vectorOffsetz9 9 No carry between bits 29 and 30 4 7 Debug Exception Processing All debug except
223. first clock cycle the pipeline is full and the cache miss is detected Instruction IO is in the A stage instruction I1 is in the M stage instruction I2 is in the E stage and instruc tion I3 is in the I stage The cache miss occurs in clock 2 when the I4 instruction fetch is attempted I4 advances to the E stage and waits for the instruction to be fetched from main memory In this example it takes two clocks 3 and 4 to fetch the I4 instruction from memory Once the cache miss is resolved in clock 4 and the instruction is bypassed to the E stage the pipeline is restarted causing the I4 instruction to finally execute it s E stage operations 2 10 Instruction Interlocks 38 Most instructions can be issued at a rate of one per clock cycle In order to adhere to the sequential programming model the issue of an instruction must sometimes be delayed This to ensure that the result of a prior instruction is MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 11 Hazards available Table 2 5 details the instruction interactions that prevent an instruction from advancing in the processor pipeline Table 2 5 Instruction Interlocks Instruction Interlocks Issue Delay in First Instruction Second Instruction Clock Cycles Slip Stage LB LBU LH LHU LL LW LWL LWR Consumer of load data 1 E stage MFCO Consumer of destination re
224. four times that of core clock 010 2 1 Trace clock is double that of core clock O11 1 1 Trace clock is same as core clock 100 1 2 Trace clock is one half of core clock 101 1 4 Trace clock is one fourth of core clock 110 1 6 Trace clock is one sixth of core clock 111 1 8 Trace clock is one eighth of core clock 8 11 3 TCBDATA Register The TCBDATA register 0x12 is used to access the registers defined by the TCBCONTROLBpgg field see Table 8 38 Regardless of which register or data entry is accessed through TCBDATA the register is only written if the TCBCONTHROLBNw g bit is set For read only registers the TCBCONTROLBNwg is a don t care The format of the TCBDATA register is shown below and the field is described in Table 8 42 The width of TCBDATA is 64 bits when on chip trace words TWs are accessed TCBTW access TCBDATA Register Format 31 63 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 187 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Table 8 42 TCBDATA Register Field Descriptions Fields Reset Names Bits Description Read Write State Data 31 0 Register fields or data as defined by the Only writable if 0 63 0 TCBCONTROLBggg field TCBCONTROLBwg is set 8 11 4 TCBCONFIG Register Reg 0 The TCBCONFIG register holds information about the hardware configuration of the TCB The f
225. g for details MIPS32 M4K Processor Core Software User s Manual Revision 02 03 133 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 8 2 7 Instruction Breakpoint Registers The registers for instruction breakpoints are described below These registers have implementation information and are used to set up the instruction breakpoints All registers are in drseg and the addresses are shown in Table 8 2 Table 8 2 Addresses for Instruction Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1000 IBS Instruction Breakpoint Status 0x1100 n 0x100 IBAn Instruction Breakpoint Address n 0x1108 n 0x100 IBMn Instruction Breakpoint Address Mask n Ox1110 4 n 0x100 IBASIDn Instruction Breakpoint ASID n Ox1118 n 0x100 IBCn Instruction Breakpoint Control n 0x1120 n 0x100 IBCCn Instruction Breakpoint Complex Control n 0x1128 n 0x100 IBPCn Instruction Breakpoint Pass Counter n n is breakpoint number in range 0 to 5 or 3 or 1 depending on the implemented hardware An example of some of the registers BAO is at offset 0x1100 and BC2 is at offset 0x1318 8 2 7 1 Instruction Breakpoint Status BS Register 0x1000 Compliance Level Implemented only if instruction breakpoints are implemented The Instruction Breakpoint Status BS register holds implementation and status information about the instru
226. g The first way the MatchEnable expression uses the input enable signals from the TCB or the bits in the 7raceContro register This tracing is done over general program areas For example all of the user level code and so on The second way to turn on tracing the TriggerEnable expression is from the processor side using the EJTAG hard ware breakpoint triggers If EJTAG is implemented and hardware breakpoints can be set then using this method enables finer grain tracing control It is possible to send a trigger signal that turns on tracing at a particular instruction For example it would be possible to trace a single procedure in a program by triggering on trace at the first instruc tion and triggering off trace at the last instruction The easiest way to unconditionally turn on trace is to assert either hardware or software tracing and the corresponding trace on signal with other enables For example with TraceControlrzs 0 i e hardware controlled tracing assert TCBCONTROLAo and all the other signals in the second part of expression MatchEnable When using the EJTAG hardware triggers to turn trace on and off it is best if TCBCONTROLAg is asserted and all the other processor mode selection bits in TCBCONTROLA are turned off This would be the least confusing way to control tracing with the trigger signals Tracing can be controlled via software with the Trace Control register in a similar manner 8 12 3 Turning Off PDtrace Trac
227. g mode exceptions the DEPC contains either e The virtual address of the instruction that was the direct cause of the debug exception or e The virtual address of the immediately preceding branch or jump instruction when the debug exception causing instruction is in a branch delay slot and the Debug Branch Delay DBD bit in the Debug register is set For asynchronous debug exceptions debug interrupt complex break the DEPC contains the virtual address of the instruction where execution should resume after the debug handler code is executed In processors that implement the MIPS 16e ASE a read of the DEPC register via MFCO returns the following value in the destination GPR GPR rt DebugExceptionPC3 4 ISAModeg 118 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions That is the upper 31 bits of the debug exception PC are combined with the lower bit of the SAMode field and writ ten to the GPR Similarly a write to the DEPC register via MTCO takes the value from the GPR and distributes that value to the debug exception PC and the SAMode field as follows DebugExceptionPC GPR rt 3 0 ISAMode lt 2 0 GPRIrt g That is the upper 31 bits of the GPR are written to the upper 31 bits of the debug exception PC and the lower bit of the debug exception PC is cleared The upper bit of the SAMo
228. ght 2002 2008 MIPS Technologies Inc All rights reserved 8 11 Trace Control Block TCB Registers Hardware Control This register is reserved if on chip trace memory is not implemented The format of the TCBSTP register is shown below and the fields are described in Table 8 47 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always Zero TCBSTP Register Format 31 n 1 n 0 Table 8 47 TCBSTP Register Field Descriptions Data 31 n 1 Reserved Must be written zero reads back zero Address n 0 Byte address of on chip trace memory word 8 11 9 TCBTRIGx Register Reg 16 23 Up to eight Trigger Control registers are possible Each register is named TCBTRIGx where xis a single digit num ber from 0 to 7 TCBTRIGO is Reg 16 The actual number of trigger registers implemented is defined in the TCBCONFIGqg g field An unimplemented register will read all zeros and writes are ignored Each Trigger Control register controls when an associated trigger is fired and the action to be taken when the trigger occurs Please also read Chapter 8 TCB Trigger logic on page 197 for detailed description of trigger logic issues The format of the TCBTRIGx register is shown below and the fields are described in Table 8 48 TCBTRIGx Register Format 31 24 23 22 16 15 14 13 7 6 5 4 3 2 1 0 TCBinfo Trace 0 CHTro PDTro 0 7 ua uix Type FO TR Table 8 48 T
229. gis 1 E stage ter MULTx MADDx MSUBx 16bx32b MFLO MFHI 0 high performance MDU 32bx32b 1 M stage MUL 16bx32b Consumer of target data 2 E stage high performance MDU 32bx32b 3 E stage MUL 16bx32b Non Consumer of target data 1 E stage high performance MDU 32bx32b 2 E stage MFHI MFLO Consumer of target data 1 E stage MULTx MADDx MSUBx 16bx32b MULT MUL MADD MSUB oll E stage high performance MDU MTHI MTLO DIV 32bx32b yl E stage DIV MUL MULTx MADDx Until DIV completes E stage MSUBx MTHI MTLO MFHI MFLO DIV MULT MUL MADD MSUB MTHI MTLO MF MULT MUL MADD MSUB Until 1st MDU op E stage HI MFLO DIV MTHI MTLO MFHI MFLO completes area efficient MDU DIV MUL Any Instruction Until MUL completes E stage area efficient MDU MFCO MFC2 CFC2 Consumer of target data 1 E stage 2 11 Hazards In general the M4K core ensures that instructions are executed following a fully sequential program model Each instruction in the program sees the results of the previous instruction There are some deviations to this model These deviations are referred to as hazards Prior to Release 2 of the MIPS32 Architecture hazards primarily CPO hazards were relegated to implementa tion dependent cycle based solutions primarily based on the SSNOP instruction This has been an insufficient and error prone practice that must be addressed with a firm compact between hardware and software As such new instructions have been added to Release 2 of the arch
230. he full speed ITCB outputs data at the CPU core clock rate but the trace clock is half that hence the 1 2 OfClk value is the full speed and the 1 4 OfCIk ratio is half speed When a 64 bit trace word is ready to transmit the PIB reads it from the FIFO and begins sending it out on TR DATA It is sent in 4 bit increments starting at the LSB s In a valid trace word the 4 LSB s are never all zero so a probe lis tening on the TR DATA port can easily determine when the transmission begins and then count 15 additional cycles to collect the whole 64 bit word Between valid transmissions TR DATA Is held at zero and TR CLK continues to run TR CLK runs continuously whenever a probe is connected An optional signal TR PROBE N may be pulled high when a probe is not connected and could be used to disable the off chip trace port If not present this signal must be tied low at the PIB input MIPS32 M4K Processor Core Software User s Manual Revision 02 03 173 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core The following encoding is used for the 6 tag bits to tell the PIB receiver that a valid transmission is starting if srcount 0 EncodedSrCount 111000 56 else if srcount 16 EncodedSrCount 111001 57 else if srcount 32 EncodedSrCount 111010 58 else EncodedSrCount srcount 8 8 7 Breakpoint Based Enabling of Tracing Each h
231. he ErrorEPC register via MFCO returns the following value in the destination GPR GPR rt lt ErrorExceptionPC3 ISAModeg MIPS32 M4K Processor Core Software User s Manual Revision 02 03 119 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core That is the upper 31 bits of the error exception PC are combined with the lower bit of the ISAMode field and written to the GPR Similarly a write to the ErrorEPC register via MTCO takes the value from the GPR and distributes that value to the error exception PC and the SAMode field as follows ErrprExceptionPC GPR rt 3 4 0 ISAMode lt 2 0 GPR rtlo That is the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC and the lower bit of the error exception PC is cleared The upper bit of the SAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 25 ErrorEPC Register Format 31 0 ErrorEPC Table 5 28 ErrorEPC Register Field Description dir a Bit s Description Reset State ErrorEPC Error Exception Program Counter Undefined 5 2 25 DeSave Register CPO Register 31 Select 0 The Debug Exception Save DeSave register is a read write register that functions as a simple memory location This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to
232. he M4K Core eeeeeeeeeeeeeeee eee nennen e dv Debug Control EegiSIBl det irrito re ed Ses tice auc den deser bate ana tuetur Tenere flc equ a RE eta eterna 9 2 Hardware Breakpolnts 2 dais e Deere E A i oix beds edu D nave evant 8 2 1 Features of Instruction Breakpoint sssssssssssssssssseeeee enne ennemis 9 2 2 Features or Data BreakpOlb a ce aiii cisci taies a eim Ib De FUNT eee Lc ERU DE 8 2 3 Features or Complex BIeakDOINTIS ia c cust neretriecacn ceters e ede qe hb eerte raa e gau bedefiQa tet ideae 9 2 4 Conditions for Matching BIeakpollite ss a uci iia ctae aaa Goes pbx E EN 8 2 5 Debug Exceptions from Breakpoints ssssssssssssssseeseeen eene entren nennen nennen 9 2 6 Breakpoint Used as Tigger Oit scires icio an ee Phe eec E PX e DU Pb aie dis 9 2 Inst cton Breakpoint PIeBISLBES erret crea der acm recht deas ere Ratt eto tecto tue nea T 8 2 8 Data Breakpoint BBOISIBIS acere etri Secrets obese deae ote a tb s x E a ei nde needs 8 2 9 Complex Breakpoint Registers sssssssssssssssssseeeene nennen nennen nnne nennen sinn nennen 8 3 Complex Breakpoint BSag8 cucio ido repe P dere eb ioco e PRI Ld veau N ees 8 3 1 Checking for Presence of Complex Break Support 9 9 2 G neral Complex Break BEN AVION iius eti orta itte RR UBL edi eb to use eria pbc stia iu ades NA 9 3 9 Usage of Pass COUFels uiiioe cette rhet cr Eb tud ui ise DUE a E E
233. he M4K Core e Only instructions which complete at the end of the pipeline are traced and indicated with a completion flag The PC is implicitly pointing to the next instruction e Load instructions are indicated with a load flag e Store instructions are indicated with a store flag e Taken branches are indicated with a branch taken flag on the target instruction e New PC information for a branch is only traced if the branch target is unpredictable from the static program image e When branch targets are unpredictable only the delta value from current PC is traced if it is dynamically deter mined to reduce the number of bits necessary to indicate the new PC Otherwise the full PC value is traced e When a completing instruction is executed in a different processor mode from the previous one the new proces sor mode is traced e The first instruction is always traced as a branch target with processor mode and full PC Periodic synchronization instructions are identified with a sync flag and traced with the processor mode and full PC All the instruction flags above are combined into one 3 bit value to minimize the bit information to trace The possi ble processor modes are explained in 8 9 1 Processor Modes on page 175 The target address is statically predictable for all branch and all jump immediate instructions If the branch is taken then the branch taken flag will indicate this All jump register instructions and ERET
234. he Opcode Field corretto tp rie Sera aan 230 Table 11 3 MIPS16e JAL X Encoding or the x Field idiot iecore a teda ape scende enadusedbrdncd eq dex unus Mies 230 Table dT MIPSTeS SHIET Encoding of the t Field cti os coetui oh eoe pere eet Este tite tasti i iussu Sa 230 Table 11 5 MIPS16e RRI A Encoding of the f Field nein tete nete neni EA 230 Table 11 6 MIPS166 I8 Encoding of the f nct Fleldl niii rtt tr eorr tte eterna br tnra 230 Table 11 7 MIPS16e RRR Encoding of thet Fleld uiuitori ote putre de der utate edin ur tes dne aE 231 Table 11 8 MIPSTe6S RR Encoding of the Funct Field sirsa anaia eant Sue adain 231 Table 11 9 MIPS16e I8 Encoding of the s Field when funct SVRS ssssssssssseeeeeenneeen nennen 231 Table 11 10 MIPS16e RR Encoding of the ry Field when funct J AL R C sssssseeeennne 231 Table 11 11 MIPS16e RR Encoding of the ry Field when funct CNVT ssssssssssseeeeennemene nennen 231 Table 11 12 MIPST6e Eoad and Store InstTA tls sacos te coats eoru ioca eua East a ascetur E Aaaa 232 Table 11 13 MIPS16e Save and Restore lnstr ctions sinesine a R 232 Table 11 14 MIPST6e ALU Immediate INSU CONS occuao crit retreat rtr rrr etr ka eate trenta 232 Table 11 15 MIPS16e Arithmetic Two or Three Operand Register Instructions sese 232 Table 11 16 MIPST6e Special InStmbOlS cce tore oreste Coda e oce Re Rte S NEEE ONES 233 Table 11 17 MIPS
235. held in ErrorEPC instead of EPC The lower 27 bytes of kuseg are treated as an unmapped and uncached region See Chapter 3 Modes of Operation on page 43 This allows main memory to be accessed in the presence of cache errors The operation of the processor is UNDEFINED if the ERL bit is set while the processor is executing instructions from kuseg Exception Level Set by the processor when any exception other than Reset Soft Reset or NMI exceptions is taken Encoding Meaning 0 Normal level Undefined 1 Exception level When EXL is set The processor is running in Kernel Mode nterrupts are disabled EPC Causegp and SRSCt implementations of Release 2 of the Architecture only will not be updated if another exception is taken IE 0 Interrupt Enable Acts as the master enable for software Undefined and hardware interrupts Encoding Meaning 0 Interrupts are disabled 1 Interrupts are enabled In Release 2 of the Architecture this bit may be modified separately via the DI and EI instructions 5 2 6 IntCtl Register CPO Register 12 Select 1 The ntCtl register controls the expanded interrupt capability added in Release 2 of the Architecture including vec tored interrupts and support for an external interrupt controller This register does not exist in implementations of Release 1 of the Architecture MIPS32 M4K Processor C
236. hen the TAP controller is in this state When 7MS is sampled HIGH on the rising edge of TCK the controller transitions to the Select_DR state 8 4 2 3 Select DR Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Capture DR state A HIGH on 7MS causes the controller to transition to the Select IR state The instruction cannot change while the TAP controller is in this state 8 4 2 4 Select IR Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW on the rising edge of TCK the controller transitions to the Capture IR state A HIGH on TMS causes the controller to transition to the Test Reset Logic state The instruction cannot change while the TAP controller is in this state 8 4 2 5 Capture DR State In this state the boundary scan register captures the value of the register addressed by the Instruction register and the value is then shifted out in the Shift DR If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift DR state A HIGH on TMS causes the controller to transition to the Exit _DR state The instruction can not change while the TAP controller is in this state 8 4 2 6 Shift DR State In this state the t
237. ht Variable Rd Rtp 1 9 Il Rts p SB Store Byte byte Mem Rs offset Rt SC Store Conditional Word if LL 1 mem Rxoffs Rt Rt LL SDBBP Software Debug Breakpoint Trap to SW Debug Handler SEB Sign Extend Byte Rd SignExtend Rt7_ 0 SEH Sign Extend Half Rd SignExtend Rt 5 9 SH Store Halfword halfy Mem Rs offset Rt SLL Shift Left Logical Rd Rt lt lt sa SLLV Shift Left Logical Variable Rd Rt lt lt Rs 4 0 SLT Set on Less Than if int Rs lt int Rt Rd 1 else Rd 0 SLTI Set on Less Than Immediate if int Rs lt int Immed Rt 1 else Rt 0 SLTIU Set on Less Than Immediate Unsigned if uns Rs lt uns Immed Rt 1 else Rt 0 SLTU Set on Less Than Unsigned if uns Rs uns Immed Rd 1 else Rd 0 SRA Shift Right Arithmetic Rd int Rt gt gt sa 214 MIPS328 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 10 3 MIPS32 Instruction Set for the M4K core Table 10 10 Instruction Set Continued Instruction Description Function SRAV Shift Right Arithmetic Variable Rd int Rt gt gt Rs 4 0 SRL Shift Right Logical Rd uns Rt gt gt sa SRLV Shift Right Logical Variable Rd uns Rt gt gt Rs 4 0 SSNOP Superscalar Inhibit No Operation Nop SUB Integer Subtract Rt int Rs int Rd SUBU Unsigned Subtract Rt uns Rs uns Rd SW Store Word Mem Rs offset Rt SWC2 Store Word From Cop
238. ight 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints The CBTC register contains configuration bits that indicate which features of complex break are implemented as well as a control bit for the stopwatch timer On a M4K core if complex break is implemented all of the separate features will be present CBTC Register Format 31 9 8 7 5 4 3 2 1 0 E swap we ew oar er Table 8 21 CBTC Register Field Descriptions Description Read Write Reset State 31 9 7 5 Reserved 0 STMode Stopwatch Timer Mode controls whether the stopwatch timer is free running or controlled by triggerpoints 0 free running 1 started and stopped by instruction triggers Stopwatch Timer Present indicates whether stopwatch timer is implemented Priming Present indicates whether primed breakpoints are supported Data Qualifiy Present indicates whether data qualified breakpoints are supported Tuple Present indicates whether any tuple breakpoints are implemented Pass Counters Present indicates whether any break points have pass counters associated with them 8 2 9 2 Priming Condition A PrCndAl Dn Registers 1 1 1 1 1 1 Compliance Level Implemented if complex breakpoints are implemented The Prime Condition registers hold implementation specific information about which triggerpoints are used for the priming conditions for each breakpoint register On a M4K core these con
239. in the SRAM interface unit are reset when a Reset or SoftReset exception is taken 6 1 3 Static Configuration Inputs All static configuration inputs should only be changed during Reset 6 1 4 Fetch Address Upon Reset SoftReset unless the EJTAGBOOT option is used the fetch is directed to VA 0xBFC00000 PA Ox1FC00000 This address is in KSeg1 which is unmapped and uncached 6 2 Software Initialized Processor State 122 Software is required to initialize the following parts of the device 6 2 1 Register File The register file powers up in an unknown state with the exception of r0 which is always 0 Initializing the rest of the register file is not required for proper operation in hardware However when simulating the operation of the core unknown values can cause problems Thus initializing the register file in the boot code may avoid simulation prob lems 6 2 2 Coprocessor 0 State Miscellaneous COPO states need to be initialized prior to leaving the boot code There are various exceptions which are blocked by ERL 1 or EXL 1 and which are not cleared by Reset These can be cleared to avoid taking spurious exceptions when leaving the boot code e Cause WP Watch Pending SW0 1 Software Interrupts should be cleared e Config Typically the KO KU and K23 fields should be set to the desired Cache Coherency Algorithm CCA value prior to accessing the corresponding memory regions But in the M4K core all CCA values are treated id
240. ions have the same basic processing flow The DEPC register is loaded with the program counter PC value at which execution will be restarted and the DBD bit is set appropriately in the Debug register The value loaded into the DEPC register is the current PC if 70 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS32 M4K Processor Core Software User s Manual Revision 02 03 4 7 Debug Exception Processing the instruction is not in the delay slot of a branch or the PC 4 of the branch if the instruction is in the delay slot of a branch The DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr and DDBSImpr bits in the Debug register are updated appropriately depending on the debug exception type The Debug2 register is updated with additional information for complex breakpoints e Halt and Doze bits in the Debug register are updated appropriately e DM bit in the Debug register is set to 1 e The processor is started at the debug exception vector The value loaded into DEPC represents the restart address for the debug exception and need not be modified by the debug exception handler software in the usual case Debug software need not look at the DBD bit in the Debug reg ister unless it wishes to identify the address of the instruction that actually caused the debug exception A unique debug exception is indicated through the DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr and DDBSImpr bits in the Debug
241. it will be a read only 1 4 OfClk Controls the Off chip clock ratio When the bit is set this implies 1 2 that is the trace clock is running at 1 2 the core clock and when the bit is clear implies 1 4 ratio that is the trace clock is at 1 4 the core clock Ox3FC8 Trace write address N 0 WAddr This register is used only if the SRAM is supported in on chip mode pointer The current write pointer for trace memory Each completed trace word is written to memory then WAddr increments When trace con cludes WAddr contains the first address in trace memory not yet writ4 ten 31 Wrap Trace wrapped This bit indicates that the entire trace depth has been written at least once After trace concludes this bit along with WAddr is used by software to determine the oldest and youngest words in the buffer 8 8 6 ITCB IFlowTrace Off Chip Interface The off chip interface consists of a 4 bit data port TR DATA and a trace clock TR CLK TR CLK can bea DDR clock that is both edges are significant TR DATA and TR CLK follow the same timing and have the same output structure as the PDtrace TCB described in MIPS specifications The trace clock is the same as the system clock or related to the system clock as either divided or multiplied The OfCIk bit in the Control Status register is of the form X Y where X is the trace clock and Y is the core clock The Trace clock is always 1 2 of the trace port data rate hence t
242. ite and returns zero on read In the M4K core where ASID is not supported this field is ignored on write and returns 1 on read This causes all match equations to work correctly in the absence of an ASID These three bits control the trace mode function Undefined Mode Trace Mode 000 Trace PC 001 Trace PC and load address 010 Trace PC and store address 011 Trace PC and both load store addresses 100 Trace PC and load data 101 Trace PC and load address and data 110 Trace PC and store address and data 111 Trace PC and both load store address and data The TraceControl2yajiaModes field determines which of these encodings are supported by the processor The operation of the processor is UNPREDICTABLE if this field is set to a value which is not supported by the processor This is the master trace enable switch in software con trol When zero tracing is always disabled When set to one tracing is enabled whenever the other enabling functions are also true 5 2 19 Trace Control2 Register CPO Register 23 Select 2 31 This register is only implemented if the EJTAG Trace capability is present Figure 5 20 TraceControl2 Register Format The TraceControl2 register provides additional control and status information Note that some fields in the TraceControl2 register are read only but have a reset state of Undefined This is because these values are load
243. itecture which act as explicit barriers that eliminate hazards To the extent that it was possible to do so the new instructions have been added in such a way that they are back ward compatible with existing MIPS processors MIPS32 M4K Processor Core Software User s Manual Revision 02 03 39 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core 2 11 1 Types of Hazards With one exception all hazards were eliminated in Release of the Architecture for unprivileged software The exception occurs when unprivileged software writes a new instruction sequence and then wishes to jump to it Such an operation remained a hazard and is addressed by the capabilities of Release 2 In privileged software there are two different types of hazards execution hazards and instruction hazards Both are defined below 2 11 1 1 Execution Hazards Execution hazards are those created by the execution of one instruction and seen by the execution of another instruc tion Table 2 6 lists execution hazards Table 2 6 Execution Hazards Spacing Producer gt Consumer Hazard On Instructions MTCO gt Coprocessor instruction execution depends on the new value of Sta Statuscy 1 tuscy MTCO gt ERET EPC 1 DEPC ErrorEPC MTCO gt ERET Status 0 MTCO EI DI gt Interrupted Instruction Statusyp 1 MTCO gt Interrupted Instruction Causerp 3 MTCO gt RDPGPR SRSCtlpss 1 WRPGPR MTCO gt Instru
244. ited States government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPS 3D MIPS16 MIPS 16e MIPS32 MIPS64 MIPS Based MIPSsim MIPSpro MIPS Technologies logo MIPS VERIFIED MIPS VERIFIED logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd M4K 5K 5Kc 5Kf 24K 24Kc 24Kf 24KE 24KEc 24KEf 34K 34Kc 34Kf 74K 74Kc 74Kf 1004K 1004Kc 1004Kf R3000 R4000 R5000 ASMACRO Atlas At the core of the user experience BusBridge Bus Navigator CLAM CorExtend CoreFPGA CoreLV EC FPGA View FS2 FS2 FIRST SILICON SOLUTIONS logo FS2 NAVIGATOR HyperDebug HyperJTAG JALGO Logic Navigator Malta MDMX MED MGB OCI PDtrace the Pipeline Pro Series SEAD SEAD 2 SmartMIPS SOC it System Navigator and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries All other trademarks referre
245. iterative area efficient array The MDU choice has a MIPS32 M4K Processor Core Software User s Manual Revision 02 03 23 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core significant effect on the MDU pipeline and the latency of multiply divide instructions executed on the core Software can query the type of MDU present on a specific implementation of the core by querying the MDU bit in the Config register CPO register 16 select 0 see 5 2 13 Config Register CPO Register 16 Select 0 for more details Figure 2 1 shows the operations performed in each pipeline stage of the M4K processor core when the high perfor mance multiplier is present Figure 2 1 M4K Core Pipeline Stages with high performance MDU L Gr Ue ees d i l Lo 0 ooe owo a w __ Fram I SRAM read 1 Instruction Decode i l A gt E Bypass i IDec i i i M gt E Bypass i Regra Register file read o ac AC2 Instruction Address Calculation stage 1 and 2 sna Rega auon Ee ALU Op Arithmetic Logic and Shift operations Regt g Dac Data Address Calculation F D SRAM read 8 osuw l u Align Load data aligner i vA Bypass i 2 Regw Register file write l MUL MDU Res Rdy RegW MUL MUL instruction i l i i g TPA Carry Propagate Adder CPA 7 Mult Macc Multiply
246. its previous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Shift IR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update IR state which terminates the scanning pro cess The instruction cannot change while the TAP controller is in this state MIPS32 M4K Processor Core Software User s Manual Revision 02 03 155 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 156 8 4 2 16 Update_IR State The instruction shifted into the instruction register takes effect on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select_DR_Scan state 8 4 3 Test Access Port TAP Instructions The TAP Instruction register allows instructions to be serially input into the device when TAP controller is in the Shift IR state Instructions are decoded and define the serial test data register path that is used to shift data between TDI and TDO during data register scanning The Instruction register is a 5 bit register In the current EJTAG implementation only some instructions have been decoded the unused instructions default to the BYPASS instruction Table 8 27 Implemented EJTAG Instructions Value Instruction Function 0x01 IDCODE
247. lays part of the kernel segment kseg3 dseg access in Debug mode can be turned on or off allowing full access to the entire kseg3 in Debug mode if so desired MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation Figure 3 2 M4K processor core Virtual Memory Map Virtual Address User Mode Kernel Mode Debug Mode OXPFFFLPRRR TTT TCTs ees OxFF3F_FFFF it kseg3 OxFF20_0000 ae nd OxFF1F FFFF OxEOO00 0000 OxDFFF FFFF kseg2 0xC000 0000 ong ksegl Ox9FFF FFFF kseg0 0x8000 0000 Ox7FFF FFFF useg kuseg 0x0000 0000 Each of the segments shown in Figure 3 2 are either mapped or unmapped The following two sub sections explain the distinction Then sections 3 2 2 User Mode 3 2 3 Kernel Mode and 3 2 4 Debug Mode specify which segments are actually mapped and unmapped 3 2 1 1 Unmapped Segments An unmapped segment does not use the FM to translate from virtual to physical addresses Unmapped segments have a fixed simple translation from virtual to physical address This is much like the transla tions the FM provides for the M4K core but we will still make the distinction All segments are treated as uncached within the M4K core Cache coherency attributes of cached or uncached can be specified and this information will be sent with the request to allow
248. ld be turned off with the trigger signal MIPS32 M4K Processor Core Software User s Manual Revision 02 03 117 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 5 2 22 Debug2 Register CPO Register 23 Select 6 This register holds additional information about Complex Breakpoint exceptions This register is only implemented if complex hardware breakpoints are present Figure 5 23 Debug2 Register Format 31 4 3 2 1 0 0 Prm DQ Tup PaCo Table 5 26 Debug2 Register Field Descriptions Fields Description Reset State Reserved 0 Primed indicates whether a complex breakpoint with Undefined an active priming condition was seen on the last debug exception Data Qualified indicates whether a complex break Undefined point with an active data qualfier was seen on the last debug exception Tuple indicates whether a tuple breakpoint was seen Undefined on the last debug exception Pass Counter indicates whether a complex breakpoint Undefined with an active pass counter was seen on the last debug exception 5 2 23 Debug Exception Program Counter Register CPO Register 24 Select 0 The Debug Exception Program Counter DEPC register is a read write register that contains the address at which processing resumes after a debug exception or debug mode exception has been serviced For synchronous precise debug and debu
249. ld not be set on instruc tion breakpoints that are being used as part of a tuple breakpoint 8 2 8 Data Breakpoint Registers The registers for data breakpoints are described below These registers have implementation information and are used the setup the data breakpoints All registers are in drseg and the addresses are shown in Table 8 10 Table 8 10 Addresses for Data Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x2000 DBS Data Breakpoint Status 0x2100 0x100 n DBAn Data Breakpoint Address n 0x2108 0x100 n DBMn Data Breakpoint Address Mask n 0x2110 0x100 n DBASIDn Data Breakpoint ASID n 0x2118 0x100 n DBCn Data Breakpoint Control n 0x2120 0x100 n DBVn Data Breakpoint Value n 0x2128 0x100 n DBCCn Data Breakpoint Complex Control n 0x2130 0x100 n DBPCn Data Breakpoint Pass Counter n Ox2ff0 DVM Data Value Match Register nis breakpoint number as 0 or 1 or just 0 depending on the implemented hardware An example of some of the registers DBMO is at offset 0x2108 and DBV is at offset 0x2220 138 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints 8 2 8 1 Data Breakpoint Status DBS Register 0x2000 Compliance Level Implemented if data breakpoints are implemented The Data Breakpoint Status DBS regis
250. ld time option on the M4K core Although Release 2 of the Architecture defines a maximum of 16 shadow sets the core allows one the normal GPRs two four or eight shadow sets The highest number actually implemented is indicated by the SRSCtlyss field If this field is zero only the normal GPRs are implemented Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to kernel mode via an interrupt or exception Once a shadow set is bound to a kernel mode entry condition reference to GPRs work exactly as one would expect but they are redirected to registers that are dedicated to that condition Privileged software may need to reference all GPRs in the register file even specific shadow registers that are not visible in the current mode The RDPGPR and WRPGPR instructions are used for this purpose The CSS field of the SRSCtl register provides the number of the current shadow register set and the PSS field of the SRSCtl register provides the number of the previous shadow register set that which was current before the last exception or interrupt occurred If the processor is operating in VI interrupt mode binding of a vectored interrupt to a shadow set is done by writing to the SRSMap register If the processor is operating in EIC interrupt mode the binding of the interrupt to a specific shadow set is provided by the external interrupt controller and is configured in an implementation dependent way Binding of
251. lds Name Bits Description Read Write Reset State IM7 IM2 15 10 Interrupt Mask Controls the enabling of each of the hard ware interrupts Refer to 4 3 Interrupts on page 57 for a complete discussion of enabled interrupts An interrupt is taken if interrupts are enabled and the corre sponding bits are set in both the Interrupt Mask field of the Status register and the Interrupt Pending field of the Cause register and the IE bit is set in the Status register Encoding Meaning 0 Interrupt request disabled 1 Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled these bits take on a different meaning and are interpreted as the IPL field described below R W Undefined IPL 15 10 Interrupt Priority Level In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled this field is the encoded 0 63 value of the current IPL An interrupt will be signaled only if the requested IPL is higher than this value If EIC interrupt mode is not enabled these bits take on a different meaning and are interpreted as the IM7 IM2 bits described above Undefined IM1 IM0O 9 8 Interrupt Mask Controls the enabling of each of the soft ware interrupts Refer to Section 4 3 Interrupts for a complete discussion of enabled interrupts Encoding Meaning 0 Interrupt
252. lid previ ous data 0 x none unchanged 0 invalid Upload Fails x X none unchanged 0 invalid using FASTDATA Passes 1 1 none unchanged 1 invalid 1 0 read data 0 SPrAcc 1 valid data 0 X none unchanged 0 invalid There is no restriction on the contents of the Data register It is expected that the transfer size is negotiated between the download upload transfer code and the probe software Note that the most efficient transfer size is a 32 bit word The Rocc bit of the Control register is not used for the FASTDATA operation 8 6 TAP Processor Accesses The TAP modules support handling of fetches loads and stores from the CPU through the dmseg segment whereby the TAP module can operate like a s ave unit connected to the on chip bus The core can then execute code taken from the EJTAG Probe and it can access data via a load or store which is located on the EJTAG Probe This occurs in a MIPS32 M4K Processor Core Software User s Manual Revision 02 03 167 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core serial way through the EJTAG interface the core can thus execute instructions e g debug monitor code without occupying the memory Accessing the dmseg segment EJTAG memory can only occur when the processor accesses an address in the range from OxFF20 0000 to OxFF2F FFFF the ProbEn bit is set and the processor is in debug mode DM 1 In addition
253. ling the ProbEn bit as 1 and the probe clearing it to 0 3 3 Fixed Mapping MMU The MAK core implements a simple Fixed Mapping FM memory management unit that is smaller than the a full translation lookaside buffer TLB and more easily synthesized Like a TLB the FM performs virtual to physical address translation and provides attributes for the different memory segments Those memory segments which are unmapped in a TLB implementation ksegO and kseg1 are translated identically by the FM in the M4K MMU The FM also determines the cacheability of each segment These attributes are controlled via bits in the Config regis ter Table 3 6 shows the encoding for the K23 bits 30 28 KU bits 27 25 and KO bits 2 0 of the Config register The M4K core does not contain caches and will treat all references as uncached but these Config fields will be sent out to the system with the request and it can choose to use them to control any external caching that may be present Table 3 6 Cache Coherency Attributes Config Register Fields K23 KU and KO Cache Coherency Attribute 2 Uncached 3 Cacheable MIPS32 M4K Processor Core Software User s Manual Revision 02 03 51 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Memory Management of the M4K Core In the M4K core no translation exceptions can be taken although address errors are still possible Table 3 7 Cacheability of Segments with Block Addr
254. ll rights reserved 8 4 Test Access Port TAP 8 4 2 9 Exit2_DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previ ous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift_DR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update_DR state which termi nates the scanning process The instruction cannot change while the TAP controller is in this state 8 4 2 10 Update_DR State When the TAP controller is in this state the value shifted in during the Shift_DR state takes effect on the rising edge of the TCK for the register indicated by the Instruction register If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select_DR_Scan state The instruction cannot change while the TAP controller is in this state and all shift register stages in the test data registers selected by the current instruction retain their previous state 8 4 2 11 Capture IR State In this state the shift register contained in the Instruction register loads a fixed pattern 000015 on the rising edge of TCK The data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift IR state A HIGH
255. llowed in the branch delay slot of another ump Instruction Processor does notexecute the instruction which is in the ERET s branch delay slot PC EPGEXL 0 LLbit 0 ERET 82 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts Figure 4 5 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines Reset Exception Config lt Reset state Soft Reset or NMI Exception Status RP 0 BEV 1 BEV 1 TS lt 0 TS 0 SR 1 0 SR 0 NMI 0 1 NMI 0 ERL 1 ERL 1 Reset Soft Reset amp NMI Exception Handling HVV PC lt OxBFCO 0000 Status NVI E U 5 E 23 Q8 4 1 Pa x E i NMI Service Code l StatusSR U l MEHREREN j S c l MM Soft Reset Service Code a m Reset Service Code v 3 Eie lecce M uc eu Ci Optional MIPS32 M4K Processor Core Software User s Manual Revision 02 03 83 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 84 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers of the M4K Core The System Control Coprocessor CPO provides the register interface to the M4K processor core and s
256. lly and hence the new PC does not need to be traced out Note that if this branch was not taken it would have been indicated by a 0 bit that is sequential flow A 11 instruction implies a taken branch for an indirect jump like instruction whose branch target could not be computed statically and hence the taken branch address is now given in the trace This includes for example instructions like jr jalr and interrupts e 1100 followed by 8 bits of 1 bit shifted offset from the last PC The bit assignments of this format on the bus between the core tracing logic and the ITCB is 3 0 4 b0011 11 4 PCdelta 8 1 35 12 24 b0 e 1101 followed by 16 bits of 1 bit shifted offset from the last PC The bit assignments of this format on the bus between the core tracing logic and the ITCB is 3 0 4 b1011 19 4 PCdelta 16 1 35 20 16 b0 e 11 10 followed by 31 of the most significant bits of the PC value followed by a bit NCC that indicates no code compression Note that for a MIPS32 or MIPS64 instruction NCC 1 and for MIPS 16e instruction NCC 0 This trace record will appear at all transition points between MIPS32 MIPS64 and MIPS 16e instruction execution This form is also a special case of the 11 format and it is used when the instruction is not a branch or jump MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 8 iFlowtr
257. logies Inc All rights reserved 8 3 Complex Breakpoint Usage 8 If support for qualified breakpoints is indicated it may only be supported for some of the breakpoints Addition ally the data breakpoint used for the qualification may be configurable Software can check this by writing to the xBCCnpg and xBCCnpgerkNum fields If a M4K core support qualified breakpoints it will only support it on instruction breakpoints and the data break used for qualification will be fixed for each instruction breakpoint 9 If the stopwatch timer is implemented either one or two pairs of instruction breakpoints may be available for controlling it and it may be possible to dynamically select which instruction breakpoints are used This can be tested by writing to the STCtl register 8 3 2 General Complex Break Behavior There is some general complex break behavior that is common to all of the features This behavior is described below e Resets to a disabled state when the core is reset the complex break functionality will be disabled and debug software that is not aware of complex break should continue to function normally e Complex break state is not updated on exceptional instructions Complex breakpoints are evaluated at the end of the pipeline and complex breakpoint exceptions are taken imprecisely on the following instruction e There is no hazard between enabling and enabled events When an instruction causes an enabling event the fol
258. lows implementation dependent masking of none some or all sources for soft reset The soft reset masking may only be applied to a soft reset source if that source can be efficiently masked in the system thus result ing in no reset at all If that is not possible then that soft reset source should not be masked since a partial soft reset may cause the system to fail or hang There is no automatic indication of whether the SRE is effective so the user must consult system documentation The PE bit reflects the ProbEn bit from the EJTAG Control register ECR whereby the probe can indicate to the debug software running on the CPU if the probe expects to service dmseg accesses The reset value in the table below takes effect on both hard and soft resets Debug Control Register 29 28 18 17 16 15 14 13 11 10 9 8 6 5 4 3 2 1 0 Res INTE NMIE NMIP SRE PE ENM Res ps IB IVM ovv Res chn PCS cn pcse 128 Table 8 1 Debug Control Register Field Descriptions Fields Read Wri Name Bit s Description te Reset State ENM Endianess in Kernel and Debug mode 0 Little Endian 1 Big Endian 17 DB Data Break Implemented 0 No Data Break feature implemented 1 Data Break feature is implemented 16 Instruction Break Implemented Preset 0 No Instruction Break feature implemented 1 Instruction Break feature is implemented 15 Inverted Value Match Indicates that the data hardware 1 breakpoints if i
259. ltiplexers A W to E bypass is not needed as the register file is capable of making an internal bypass of Rd write data directly to the Rs and Rt read ports Figure 2 14 IU Pipeline Data bypass I stage E stage M stage i A stage i W stage A to E bypass M to E bypass Instruction Bypass Load data HI LO Data or multiplexers CPO data Figure 2 15 shows the data bypass for an Add instruction followed by a Sub and another Add instruction The Sub instruction uses the output from the Add instruction as one of the operands and thus the M to E bypass is used The following Add uses the result from both the first Add instruction and the Sub instruction Since the Add data is 34 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 6 Data Bypassing now in A stage the A to E bypass is used and the M to E bypass is used to bypass the Sub data to the Add instruc tion Figure 2 15 IU Pipeline M to E bypass One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle ADD E M A W BUENO A to E bypass SUB R4 R3 R7 M to E bypas ADD p R5 R3 R4 2 6 1 Load Delay Load delay refers to the fact that data fetched by a load instruction is not available in the integer pipeline until after the load aligner in A stage All instructions need the source operands available in the E stage
260. mplemented support an inverted value match a Preset IB IVM DVM Data Value Match Register Indicates that a DRSEG mapped register is present that will capture the load data value on precise data value breakpoints CBrk Indicates that Complex Breakpoint logic is implemented R Preset MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints Table 8 1 Debug Control Register Field Descriptions Continued Fields Description Read Wri te Reset State PC Sampling Rate Controls how often the program counter is sampled if PC Sampling is implemented PC Sampling Enable Enables sampling of PC if imple mented Interrupt Enable in Normal Mode This bit provides the hardware and software interrupt enable for non debug mode in addition to other masking mechanisms 0 Interrupts disabled 1 Interrupts enabled depending on other enabling mecha nisms NMIE NMIP 2 Non Maskable Interrupt Enable for non debug mode 0 NMI disabled 1 NMI enabled NMI Pending Indication 0 No NMI pending 1 NMI pending SRE 1 Soft Reset Enable This bit allows the system to mask soft resets The core does not internally mask soft resets Rather the state of this bit appears on the EJ_SAstE external output signal allow ing the system to mask soft resets if desired PE 0
261. mplements single cycle multiply and multiply accumulate MAC instructions which enable DSP algorithms to be performed efficiently It allows 32 bit x 16 bit MAC instructions to be issued every cycle while a 32 bit x 32 bit MAC instruction can be issued every other cycle The area efficient MDU option handles multiplies with a one bit per clock iterative algorithm The basic Enhanced JTAG EJTAG features provide CPU run control with stop single stepping and re start and with software breakpoints through the SDBBP instruction Additional EJTAG features instruction and data virtual address hardware breakpoints complex hardware breakpoints connection to an external EJTAG probe through the Test Access Port TAP and PC Data tracing may optionally be included MIPS32 M4K Processor Core Software User s Manual Revision 02 03 13 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 M4K Processor Core The rest of this chapter provides an overview of the MIPS32 M4K processor core and consists of the following sec tions e Section 1 1 Features e Section 1 2 M4K Core Block Diagram 1 1 Features e 5 stage pipeline e 32 bit Address and Data Paths e MIPS32 Compatible Instruction Set Multiply add and multiply subtract instructions MADD MADDU MSUB MSUBU Targeted multiply instruction MUL Zero and one detect instructions CLZ CLO Wait instruction WAIT Condition
262. multi cycle latency is desired however the interface can be stalled to allow connection to slower devices Redirection When the dual I D interface is present a mechanism exists to divert D side references to the I side if desired The redirection is employed automatically in the case of PC relative loads in MIPS16e mode The mechanism can be MIPS32 M4K Processor Core Software User s Manual Revision 02 03 19 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 M4K Processor Core 20 explicitly invoked for any other D side references as well When the DS Fiedir signal is asserted a D side request is diverted to the I side interface in the following cycle and the D side will be stalled until the transaction is completed Transaction Abort Because the core does not know whether loads or stores are re startable it cannot arbitrarily interrupt a request which has been initiated on the SRAM interface However cycles spent waiting for a multi cycle transaction to complete can directly impact interrupt latency In order to minimize this effect the interface supports an abort mechanism The core requests an abort whenever an interrupt is detected and a transaction is pending The external system logic can choose to acknowledge the abort if it wants to reduce interrupt latency MIPS16e Execution When the core is operating in MIPS16e mode instruction fetches only require 16 bits of data to
263. n Table 8 41 This bit is reserved if off chip trace option is not implemented 188 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 11 Trace Control Block TCB Registers Hardware Control Table 8 43 TCBCONFIG Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State PW 10 9 Probe Width Number of bits available on the off chip trace R Preset interface TR_DATA pins The number of TR_DATA pins is encoded as shown in the table PW Number of bits used on TR_DATA 00 4 bits 01 8 bits 10 16 bits 11 reserved This field is preset based on input signals to the TCB and the actual capability of the TCB This bit is reserved if off chip trace option is not implemented PiN 8 6 Pipe number R 0 Indicates the number of execution pipelines OnT 5 When set this bit indicates that on chip trace memory is R Preset present This bit is preset based on the selected option when the TCB is implemented OfT 4 When set this bit indicates that off chip trace interface is R Preset present This bit is preset based on the selected option when the TCB is implemented and on the existence of a PIB module TC_PibPresent asserted REV 3 0 Revision of TCB An implementation that conforms to the R 0 described architecture in this document must have revision 0
264. n requires more than 16 bits of infor mation to be traced properly the PDtrace fifo will buffer the information and send it on subsequent clock cycles In the TCB the on chip trace memory is defined as a 64 bit wide synchronous memory running at core clock speed In this case the fifo is not needed For off chip trace through the Trace Probe the fifo comes into play because only a limited number of pins 4 8 or 16 exist Also the speed of the Trace Probe interface can be different either faster or slower from that of the M4K core So for off chip tracing a specific TCB TW fifo is needed MIPS32 M4K Processor Core Software User s Manual Revision 02 03 199 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 200 8 14 2 Handling of Fifo Overflow in the PDtrace Module Depending on the amount of trace information selected for trace and the frequency with which the 16 bit data inter face is needed it is possible for the PDtrace fifo overflow from time to time There are two ways to handle this case 1 Allow the overflow to happen and thereby lose some information from the trace data 2 Prevent the overflow by back stalling the core until the fifo has enough empty slots to accept new trace data The PDtrace fifo option is controlled by either the TraceControljg or the TCBCONTROLA jo bit depending on the setting of TraceCon trolrs bit The first option is free of any cycl
265. n the last Mypy stage Figure 2 11 M4KC Area Efficient MDU Pipeline Flow During a Multiply Accumulate Operation Clock 1 2 33 34 35 36 37 e EStage M Munu Stage lt Munu Stage lt Munu Stage gt Ampu Stage Wau Stage gt LILI LI LI LI Ly Add Subtract Shift Accumulate LO Accumulate HI HI LO Write 32 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 5 Branch Delay 2 4 3 Divide Area Efficient MDU Divide operations also implement a simple non restoring algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note that this cycle is executed even if negation is not needed The next 32 cycle 3 34 executes an interactive add subtract shift function Two sign adjust Sign Adjust 1 2 cycles are used to change the sign of one or both the quotient and the remainder Note that one or both of these cycles are skipped if they are not needed The rule is if both operands were positive or if this is an unsigned division both of the sign adjust cycles are skipped If the rs operand was negative one of the sign adjust cycles is skipped If only the rs operand was negative none of the sign adjust cycles are skipped Register writeback to HI and LO are done in the A stage Figure 2 12 shows the pipeline flow for a divide
266. nction design or otherwise MIPS Technologies does not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be the governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the Un
267. nd Servicing Flowcharts Figure 4 3 General Exception Handler HW Exceptions other than Reset Soft Reset NMI or first level TLB missNote Interrupts can be masked by IE or IMs and Watch is masked if EXL 1 Comments BadVA is set only for AdEL S exceptions Note Set CauseEXCCode CE not set if itis a Bus Error BadVA VA Check if exception within another exception Yes Instr in Br Dly Slot EPC lt PC 4 EPCe PC Cause BD 1 Cause BD 0 Processor forced to Kernel Mode amp interrupt disabled 0 normal 1 bootstrap PC lt 0x8000_0000 180 PC lt OxBFCO 0200 180 unmapped cached unmapped uncached To General Exception Servicing Guidelines MIPS32 M4K Processor Core Software User s Manual Revision 02 03 81 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core Figure 4 4 General Exception Servicing Guidelines SW Comments EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions MFCO Only Reset Soft Reset NMI exceptions possible EPG Status Cause AMA MTCO Set Status bits UM lt 0 EXL lt 0 IE1 Optional only to enable Interrupts while keeping Kernel Mode d boe amp J ump to appropriate After EXL 0 all exceptions allowed except lid interrupt if masked by IE NERONE RU C Oe ED Service Code ERET is not a
268. nding processor access 1 Pending processor access The probe s software must clear this bit to 0 to indicate the end of the PA Write of 1 is ignored A pending Processor Access is cleared when Rocc is set but another PA may occur just after the reset if a debug exception occurs Finishing a Processor Access is not accepted while the Rocc bit is set This is to avoid that a Processor Access occurring after the reset is finished due to indication of a Processor Access that occurred before the reset The FASTDATA access can clear this bit Res reserved 0 PrRst Processor Reset Implementation dependent behavior 0 When the bit is set to 1 then it is only guaranteed that this setting has taken effect in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EJ PrHst signal If the signal is used in the system then it must be ensured that both the processor and all devices required for a reset are properly reset Otherwise the system may fail or hang The bit resets itself since the EJTAG Control register is reset by hard or soft reset MIPS32 M4K Processor Core Software User s Manual Revision 02 03 163 Copyright 2002 2008
269. nections are predetermined and these regis ters are read only The architecture allows for up to 16 priming conditions to be specified and there can be up to 4 priming condition reg isters per breakpoint A B C D A M4K core only allows for 4 priming conditions and thus only implements the PrCndA registers The general description is shown in Table 8 22 The actual priming conditions for each of the breakpoints are shown in Table 8 23 PrCndA Register Format 31 24 23 16 15 8 7 0 Cond3 Cond2 Condl CondO MIPS32 M4K Processor Core Software User s Manual Revision 02 03 145 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 146 Table 8 22 PrCndA Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State CondN 31 24 Specifies which triggerpoint is connected to priming R Preset 23 16 condition 3 2 1 or 0 for the current breakpoint 15 8 7 0 31 30 Reserved R 0 23 22 15 14 7 6 29 28 Trigger type R Preset 21 20 00 Special Bypass 13 12 01 Instruction 5 4 10 Data 11 Reserved 27 24 Break Number 0 14 R Preset 19 16 11 8 3 0 a Condition 0 is always Bypass and will read as 8 bO Table 8 23 Priming Conditions and Register Values drseg Break Condo Cond1 Cond2 Cond3 PrCndA Value offset InstO Bypass Data Insti Inst2 Ox1211 2000 0x8300 Insti Bypass Data InstO Inst2 0x1210 2000 0x
270. nens 78 4 8 16 Execution Exception Implementation Specific 1 Exception esssseeesss 78 4 8 17 Execution Exception Integer Overflow essisssssssssissssseeee nennen tnnt nnns 79 2 918 EXSCUTON EXGOpHOI TIO suctaciisddo ute ed HFERE RI du SHE N 79 48 19 Debug Data Break EXCODllOn us oco tr irr terree toro eer onec dex dence opaca mas 79 4 9 20 Complex Break EXCSLUOG s votes tocar ito udea secteur RAE 80 4 9 Exception Handling and Servicing FIoWCHarts 5 ie cceece snes sar anena aaa aaa 80 Chapter 5 CPO Registers of the M4K Core leeseeeeeeeeeeeeeeeeeee eene eene nannte nannten nnn 85 5 15 CPO Register SUITIial ced catecesudetep c toco a a e ERU A ETE a BERI LER Qo coU esl o aaa 85 5 2 CPO Register DescripU ONS ete M Em 86 5 2 M HWREna Register CPO Register 7 Selebt OJren anann ata 87 5 2 2 Bad VAdar Register CPO Register 8 Select 0 iiio mere a aana ni 88 5 2 3 Count Register CPO Register 9 Select 0 sssssssssssssssseseeeeene entrent nnns 88 5 2 4 Compare Register CPO Register 11 Sel ct 0 2 i nerit a ei cR px ican eset ien aa 89 5 2 5 Status Register GPO Register 72 Select 0 irae tenere siet eiua Speer tct 89 5 2 6 4ntCt Register CPO Register 12 Select T uiui eiecti iate oda ed A esed ed itcr audiui 93 5 2 7 SRSCtI Register CPO Register 12 Select 2 ssssssssssssssssseeenee entere 95 5 2 8
271. ng arithmetic overflows I O inter rupts and system calls When the CPU detects one of these exceptions the normal sequence of instruction execution is suspended and the processor enters kernel mode In kernel mode the core disables interrupts and forces execution of a software exception processor called a handler located at a specific address The handler saves the context of the processor including the contents of the program counter the current operating mode and the status of the interrupts enabled or disabled This context is saved so it can be restored when the exception has been serviced When an exception occurs the core loads the Exception Program Counter EPC register with a location where execution can restart after the exception has been serviced Most exceptions are precise which mean that EPC can be used to identify the instruction that caused the exception For precise exceptions the restart location in the EPC regis ter is the address of the instruction that caused the exception or if the instruction was executing in a branch delay slot the address of the branch instruction immediately preceding the delay slot To distinguish between the two software must read the BD bit in the CPO Cause register Bus error exceptions and CP2 exceptions may be imprecise For imprecise exceptions the instruction that caused the exception can not be identified This chapter contains the following sections e Section 4 1 Exception Conditions
272. nges and either the previous or the current processor mode is selected for trace The amount of extra information traced is programmable to include e PC information only e PC and load address e PC and store address e PC and load and store address e PC and load address and load data e PC and store address and store data e PC and load and store address and load and store data e PC and load data only The last option is helpful when used together with instruction accurate simulators If the full internal state of the pro cessor is known prior to trace start PC and load data are the only information needed to recreate all register values on an instruction by instruction basis MIPS32 M4K Processor Core Software User s Manual Revision 02 03 177 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 178 8 9 6 1 User Data Trace In addition to the above a special CPO register UserTraceData can generate a data trace When this register is writ ten and the global Trace On is set then the 32 bit data written is put in the trace as special User Data information Remark The User Data is sent even if the processor is operating in an un traced processor mode 8 9 7 Enable Trace to Probe On Chip Memory When trace is On based on the options listed in 8 9 5 Programmable Processor Trace Mode Options the trace information is continuously sent on the PDtrace M interface
273. not be required lw k0 StatusSave Get saved Status including EXL set lw k1 EPCSave and EPC mtcO k0 CO Status Restore the original value lw k0 SRSCtlSave Get saved SRSCtl mtcO k1 CO EPC and EPC mtcO k0 CO_SRSCt1 Restore shadow sets ehb Clear hazard eret Dismiss the interrupt MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 3 Interrupts 4 3 1 3 External Interrupt Controller Mode External Internal Interrupt Controller Mode redefines the way that the processor interrupt logic is configured to pro vide support for an external interrupt controller The interrupt controller is responsible for prioritizing all interrupts including hardware software timer and performance counter interrupts and directly supplying to the processor the priority level and vector number of the highest priority interrupt EIC interrupt mode is in effect if all of the following conditions are true Config3yeic 1 e IniCtlys 0 e Causejy 1 e Statlusggy 0 In EIC interrupt mode the processor sends the state of the software interrupt requests Causejp jpg and the timer interrupt request Causery to the external interrupt controller where it prioritizes these interrupts in a system depen dent way with other hardware interrupts The interrupt controller can be a hard wired logic block or it can be config
274. nterrupt vector 16 200 based on the value of Causeyy Software was required to prioritize interrupts as a function of the Causejp bits in the interrupt handler prologue Release 2 of the Architecture implemented by the M4K core adds an upward compatible extension to the Release 1 interrupt architecture that supports vectored interrupts In addition Release 2 adds a new interrupt mode that supports the use of an external interrupt controller by changing the interrupt architecture 4 3 1 Interrupt Modes The M4K core includes support for three interrupt modes as defined by Release 2 of the Architecture Interrupt compatibility mode which acts identically to that in an implementation of Release 1 of the Architec ture e Vectored Interrupt VI mode which adds the ability to prioritize and vector interrupts to a handler dedicated to that interrupt and to assign a GPR shadow set for use during interrupt processing The presence of this mode is denoted by the VInt bit in the Config3 register This mode is architecturally optional but it is always present on the M4K core so the VInt bit will always read as a 1 for the M4K core e External Interrupt Controller EIC mode which redefines the way in which interrupts are handled to provide full support for an external interrupt controller handling prioritization and vectoring of interrupts This presence of this mode denoted by the VEIC bit in the Config3 register Again this mode is archit
275. o must be shifted in for the unused bytes The organization of bytes in the PAD register depends on the endianess of the core as shown in Figure 8 4 The endian mode for debug kernel mode is determined by the state of the S _Endian input at power up MIPS32 M4K Processor Core Software User s Manual Revision 02 03 165 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core Figure 8 4 Endian Formats for the PAD Register bit 31 ve 24 23 16 15 87 as 0 BERN A n 0 4 5 6 7 Aln 2 1 Aino 0_ 2 3 anzi Most significant byte is at lowest address Word is addressed by byte address of most significant byte MSB LSB bit 31 24 23 16 15 87 0 Vien A n 0 27 6 5 4 Aln 2 1 Aln 0 3 2 1 0 Aln 2 0 Least significant byte is at lowest address Word is addressed by byte address of least significant byte The size of the transaction and thus the number of bytes available required for the PAD register is determined by the Psz field in the ECR 8 5 4 Fastdata Register TAP Instruction FASTDATA The width of the Fastdata register is 1 bit During a Fastdata access the Fastdata register is written and read i e a bit is shifted in and a bit is shifted out During a Fastdata access the Fastdata register value shifted in specifies whether the Fastdata access should be completed or not The value shifted out is a flag that indicates whether the Fa
276. o a normal exception in debug mode The read only information bits are updated every time the debug exception is taken or when a normal exception is taken when already in debug mode Only the DM bit and the EJTAGver field are valid when read from non debug mode the values of all other bits and fields are UNPREDICTABLE Operation of the processor is UNDEFINED if the Debug register is written from non debug mode Some of the bits and fields are only updated on debug exceptions and or exceptions in debug mode as shown below e DSS DBp DDBL DDBS DIB DINT DIBImpr DDBLImpr DDBSImpr are updated on both debug excep tions and on exceptions in debug modes e DExcCode is updated on exceptions in debug mode and is undefined after a debug exception Haltand Doze are updated on a debug exception and are undefined after an exception in debug mode e DBD is updated on both debug and on exceptions in debug modes All bits and fields are undefined when read from normal mode except those explicitly described to be defined e g EJTAGver and DM MIPS32 M4K Processor Core Software User s Manual Revision 02 03 109 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 110 Figure 5 18 Debug Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 lm Pal ep ee 18 17 15 14 10 9 8 7 6 5 4 3 2 1 0 el oe SPER eer Table 5 21 Debug Register Field Descriptions Bit s
277. ode Such an environment is well beyond the scope of this example 4 To complete interrupt processing the saved values must be restored and the original interrupted code restarted EJ di Disable interrupts may not be required lw k0 StatusSave Get saved Status including EXL set lw k1 EPCSave IR and EPC mtcO k0 CO Status Restore the original value mtcO k1 CO EPC and EPC Restore GPRs and software state eret Dismiss the interrupt 4 3 1 2 Vectored Interrupt Mode Vectored Interrupt mode builds on the interrupt compatibility mode by adding a priority encoder to prioritize pending interrupts and to generate a vector with which each interrupt can be directed to a dedicated handler routine This mode also allows each interrupt to be mapped to a GPR shadow set for use by the interrupt handler Vectored Inter rupt mode is in effect if all of the following conditions are true Config3 yi 1 Config3 veic 0 Li IntCtl vst 0 e Causey l Stat uSpey 0 In VI interrupt mode the six hardware interrupts are interpreted as individual hardware interrupt requests The timer interrupt is combined in a system dependent way external to the core with the hardware interrupts the interrupt with which they are combined is indicated by the ntCtl p7 field to provide the appropriate relative priority of the timer interrupt with that of the hardware interrupts The processor interrupt logic
278. of the core clock See Table 8 41 for a description of the encoding of the clock ratio fields 8 14 4 Adding Cycle Accurate Information to the Trace Depending on the trace regeneration software it is possible to obtain the exact cycle time relationship between each instruction in the trace This information is added to the trace when the TCBCONTROLB a bit is set The overhead on the trace information is a little more than one extra bit per core clock cycle This setting only affects the TCB module and not the PDtrace module The extra bit therefore only affects the likeli hood of the TCB fifo overflowing 8 15 TCB On Chip Trace Memory When on chip trace memory is available TCBCONFIGonr is set the memory is typically of smaller size than if it were external in a trace probe The assumption is that it is of some value to trace a smaller piece of the program With on chip trace memory the TCB can work in three possible modes 1 Trace From mode 2 Trace To mode 3 Under Trigger unit control Software can select this mode using the TCBCONTROLBpy field If one or more trigger control registers TCBTRIGX are implemented and they are using Start End or About triggers then the trace mode in TCBCONTROLB yy should be set to Trace To mode 8 15 1 On Chip Trace Memory Size The supported On chip trace memory size can range from 256 byte to 8Mbytes in powers of 2 The actual size is shown in the TCBCONFI Gs field MIPS32 M4K
279. on PC which can be masked at bit level The registers for each instruction breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation IB_match all 1 s IBMnyzpy PC lBAngga The match indication for instruction breakpoints is always precise i e indicated on the instruction causing the IB match to be true 8 2 4 2 Conditions for Matching Data Breakpoints When a data breakpoint is enabled that breakpoint is evaluated for every data transaction due to a load store instruc tion executed in non debug mode including load store for coprocessor and transactions causing an address error on data access The breakpoint is not evaluated due to a PREF instruction or other transactions which are not part of explicit load store transactions in the execution flow nor for addresses which are not the explicit load store source or destination address A breakpoint match depends on the transaction type TYPE as load or store the address and optionally the data value of a transaction The registers for each data breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation The overall match equation is the DB match DB match TYPE load amp amp DBCnygpp TYPE store amp amp DB Cnwsgg amp amp DB addr match amp amp DB no value compare
280. on TMS causes the controller to transition to the Exit IR state The instruction cannot change while the TAP controller is in this state 8 4 2 12 Shift IR State In this state the instruction register is connected between TDI and TDO and shifts data one stage toward its serial out put on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller remains in the Shift IR state A HIGH on TMS causes the controller to transition to the Exit IR state 8 4 2 13 Exit1 IR State This is a temporary controller state in which all registers retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Pause IR state A HIGH on TMS causes the controller to transi tion to the Update IR state which terminates the scanning process The instruction cannot change while the TAP con troller is in this state and the instruction register retains its previous state 8 4 2 14 Pause IR State The Pause IR state allows the controller to temporarily halt the shifting of data through the instruction register in the serial path between TD and TDO If TMS is sampled LOW at the rising edge of TCK the controller remains in the Pause IR state A HIGH on TMS causes the controller to transition to the Exif2 IR state The instruction cannot change while the TAP controller is in this state 8 4 2 15 Exit2 IR State This is a temporary controller state in which the instruction register retains
281. on all I E and M stage see 2 9 Slip Conditions on page 38 If this instruction involved sending data from the core to the coprocessor 2 then this data is send in A stage 4 The instruction completion is signaled to the coprocessor 2 in the W stage Potential data from the coprocessor is written in the register file Figure 2 18 Show the timing relationship between the M4K core and the coprocessor 2 for all coprocessor 2 instruc tion 36 MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 8 Interlock Handling Figure 2 18 Coprocessor 2 Interface Transactions One Cycle One Cycle One Cycle One Cycle One Cycle COP2 inst Capture Control amp Get ToData from FromData memory Core internal Fetch instrucion operations Decode and setup valid Core to CP2 info Validate inst Instrucion ToData Complete Control amp FromData CP2 to Core info Capture ToData Complete instruction CP2 internal operations As can be seen all control and data from the coprocessor must occur in the M stage If this is not the case the A stage will start slipping in the following cycle and thus stall the I E M and A pipeline stages but if all expected control and data is available in the M stage a Coprocessor 2 instructions can execute with no stalls on the pipeline
282. operation The repeat rate is either 34 35 or 36 cycles depending on how many sign adjust cycles are skipped as a second divide can be in the E stage when the first divide is in the last Mypyu Stage Figure 2 12 M4K Area Efficient MDU Pipeline Flow During a Divide DIV Operation Clock 1 2 3 34 35 36 37 38 E Stage P E Mypy Stage P My py Stage P My py Stage P Mupu Stage 4 Aupy Stage P Wypy Stage gt RS Adjust Add Subtract Shift Sign Adjust 1 Sign Adjust 2 HI LO Write 2 5 Branch Delay The pipeline has a branch delay of one cycle The one cycle branch delay is a result of the branch decision logic oper ating during the E pipeline stage This allows the branch target address to be used in the I stage of the instruction fol lowing 2 cycles after the branch instruction By executing the 1st instruction following the branch instruction sequentially before switching to the branch target the intervening branch delay slot is utilized This avoids bubbles being injected into the pipeline on branch instructions Both the address calculation and the branch condition check are performed in the E stage The pipeline begins the fetch of either the branch path or the fall through path in the cycle following the delay slot After the branch decision is made the processor continues with the fetch of either the branch path for a taken branch or the fall through path for the non taken branch The branch delay means that the in
283. or 2 instruction which caused a general exception in the coprocessor Execution of coprocessor 2 instruction which caused an Implementation Spe cific exception 1 in the coprocessor Execution of an arithmetic instruction that overflowed Execution of a trap when trap condition is true DDBL DDBS EJTAG Data Address Break address only or EJTAG Data Value Break on Store address and value AdEL Load address alignment error User mode load reference to kernel address MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 3 Interrupts Table 4 1 Priority of Exceptions Continued Exception Description AdES Store address alignment error User mode store to kernel address DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare 4 3 Interrupts Older 32 bit cores available from MIPS that implemented Release 1 of the Architecture included support for two soft ware interrupts six hardware interrupts and a special purpose timer interrupt Note that the Architecture also defines a performance counter interrupt but this is not implemented on the M4K core The timer interrupt was provided external to the core and typically combined with hardware interrupt 5 in an system dependent manner Interrupts were handled either through the general exception vector offset 16 180 or the special i
284. or Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 6 1 Fetch Load and Store from to the EJTAG Probe through dmseg sse 168 8 7 TASS WECIAMISING uices duisecstu dest dasttincaalE tir umsaso dics xtd dSs dcc lacgases a 169 8 8 IFlowtrace MecHhariStfi ass saccis oid oisi dri se Eee ot RE eec ascen EEA TER AAE EAR SS eO Pa Pedo tein 169 8 8 1 A Simple Instruction Only Tracing Scheme 22 toin Leto trois a 170 Eye rua nu n i 171 8 8 3 PCB FIOW I FACE nterface usce reed ier uite uqur sect lad a d MF UEas SS 171 8 8 4 ITGB IFlowTrace Storage Representations 2 2 tut ote ut penna ota ttai te resti duse sexi rr ted epus 172 8 6 5 MCB AROW eic EE 172 8 5 0 TCB IFlow Trace Off Ghip Interface uoo iet te feretro t Rte denkt eros ert oec reris 173 8 8 7 Breakpoint Based Enabling Of TTAGCIFIQ iieri oe trece raa a SF Dese pud 174 BO EJT AG Ta Einna tisse E Dc HS teu D cL Ded EIE 174 B O c TProcessor IMIOG ES i coro iim o IE ROSA uIecu RM nx AERE HR De Uetbo Loss obese nolan 175 8 9 2 Software Versus Hardware GOntnol ioci oet tret portatori es Stk te gerere Ren peres aka 175 8 93 Tace larormiatiglls sueco ome sr en Det O eo SViD ants Dot daabdon uadite n ases ton td fed od Uu MP D a pes DUR 175 8 9 4 Load Store Address and Data Trace Information 176 8 9 5 Programmable Processor Trace Mode Options cccccceec
285. or semaphores based on LL SC instructions e External sync indication allows memory ordering e Debug support includes cross core triggers e CorExtend User Defined Instruction capability access to this feature is available in the M4K Pro cores and requires a separate license e Optional support for the CorExtend feature allows users to define and add instructions to the core as a build time option e Single or multi cycle instructions e Source operations from register immediate field or local state e Destination to a register or local state e Full featured Coprocessor 2 Interface e Almost all I Os registered e Separate unidirectional 32 bit instruction and data buses e Support for branch on Coprocessor condition e Processor to from Coprocessor register data transfers e Direct memory to from Coprocessor register data transfers e Multiply Divide Unit High performance build time option e Maximum issue rate of one 32x16 multiply per clock MIPS32 M4K Processor Core Software User s Manual Revision 02 03 15 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 M4K Processor Core e Maximum issue rate of one 32x32 multiply every other clock e HBarly in divide control Minimum 11 maximum 34 clock latency on divide e Multiply Divide Unit Area efficient build time option e Iterative multiply and divide 32 or more cycles for each instruction e Power Control e No minimum frequency
286. ore Software User s Manual Revision 02 03 93 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 94 Figure 5 6 shows the format of the ntCt register Table 5 8 describes the ntCt register fields Figure 5 6 IntCtl Register Format 31 29 28 26 25 10 9 5 4 0 IPTI IPPCI 0 VS 0 Table 5 8 IntCtl Register Field Descriptions Fields Read Wr Reset Name Bits Description ite State IPTI 31 29 For Interrupt Compatibility and Vectored Interrupt R Externally modes this field specifies the IP number to which the Set IPPCI Timer Interrupt request is merged and allows software to determine whether to consider Causey for a potential interrupt Hardware Interrupt Encoding IP bit Source 2 2 HWO 3 3 HWI 4 4 HW2 5 5 HW3 6 6 HW4 7 7 HW5 The value of this bit is set by the static input SI IPTI 2 0 This allows external logic to communi cate the specific S _ nt hardware interrupt pin to which the S Timerlnt signal is attached The value of this field is not meaningful if External Interrupt Controller Mode is enabled The external inter rupt controller is expected to provide this information for that interrupt mode For Interrupt Compatibility and Vectored Interrupt 0 modes this field specifies the IP number to which the Performance Counter Interrupt request is merged and allows software to determine whe
287. ore determine the value of these bits These bits can be scanned out of the D register after being selected The register is selected when the Instruction register is loaded with the IDCODE instruction Device Identification Register Format 31 28 27 12 11 1 0 Version PartNumber ManufID R Table 8 28 Device Identification Register Fields Read Name Description Write Reset State Version Version 4 bits R EJ Version 3 0 This field identifies the version number of the proces sor derivative PartNumber Part Number 16 bits R EJ PartNumber 15 0 This field identifies the part number of the processor derivative ManufID Manufacturer Identity 11 bits R EJ ManufID 10 0 Accordingly to IEEE 1149 1 1990 the manufacturer identity code shall be a compressed form of the JEDEC Publications 106 A MIPS32 M4K Processor Core Software User s Manual Revision 02 03 159 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 160 Table 8 28 Device Identification Register Fields Read Name Bit s Description Write Reset State 8 5 2 3 Implementation Register This 32 bit read only register is used to identify the features of the EJTAG implementation Some of the reset values are set by inputs to the core The register is selected when the Instruction register is loaded with the IMPCODE instruction Implementation Regis
288. ormat of the TCBCONFIG register is shown below and the field is described in Table 8 43 TCBCONFIG Register Format 31 30 25 24 21 20 17 16 14 13 11 10 9 8 6 5 4 3 0 CF1 0 TRIG SZ cRMax CRMin PW PiN OnT OfT REV Table 8 43 TCBCONFIG Register Field Descriptions Fields Read Wr Name Bits Description ite Reset State CFI 31 This bit is set if a TCBCONFIG7 register exists In this revi R 0 sion TCBCONFIG 1 does not exist and this bit always reads Zero 0 30 25 Reserved Must be written as zero returns zero on read R 0 TRIG 24 201 Number of triggers implemented This also indicates the num R Preset ber of TCBTRIGx registers that exist Legal values are0 8 SZ 20 17 On chip trace memory size This field holds the encoded size of R Preset the on chip trace memory The size in bytes is given by 28248 implying that the mini mum size is 256 bytes and the largest is 8Mb This bit is reserved if on chip memory is not implemented CRMax 16 14 Off chip Maximum Clock Ratio R Preset This field indicates the maximum ratio of the core clock to the off chip trace memory interface clock The clock ratio encod ing is shown in Table 8 41 This bit is reserved if off chip trace option is not implemented CRMin 13 11 Off chip Minimum Clock Ratio R Preset This field indicates the minimum ratio of the core clock to the off chip trace memory interface clock The clock ratio encoding is shown i
289. peat Instruction 1st Instruction 2nd Instruction Rate 16 bit MULT MULTU MADD MADDU 1 MADD MADDU MSUB MSUBU MSUB MSUBU 32 bit MULT MULTU MADD MADDU MSUB MSUBU 2 MADD MADDU MSUB MSUBU Figure 2 3 below shows the pipeline flow for the following sequence 1 32x16 multiply Mult 2 Add 3 32x32 multiply Mult 4 Subtract Sub The 32x16 multiply operation requires one clock of each pipeline stage to complete The 32x32 multiply operation requires two clocks in the Mypy pipe stage The MDU pipeline is shown as the shaded areas of Figure 2 3 and always starts a computation in the final phase of the E stage As shown in the figure the Mypy pipe stage of the MDU pipeline occurs in parallel with the M stage of the IU pipeline the Ay stage occurs in parallel with the A stage and the Wypy stage occurs in parallel with the W stage In general this need not be the case Following the 1st cycle of the M stages the two pipelines need not be synchronized This does not present a problem because results in the MDU pipeline are written to the HI and LO registers while the integer pipeline results are written to the register file Figure 2 3 MDU Pipeline Behavior During Multiply Operations cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 E E qu x pr Tm ee l l i f l l l Mult I E Mwpu Em WMDU l l Add j I E M A Ww l Mult I E Nem EE NES Waipu S
290. pecifies the Base base address of the exception vectors when Status BEV S Zero Must be written as zero returns zero on read CPUNum 9 0 This field specifies the number of the CPU in a R Externally Set multi processor system and can be used by software to distinguish a particular processor from the others The value in this field is set by the SI CPUNum 9 0 static input pins to the core In a single processor sys tem this value should be set to zero 104 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 13 Config Register CPO Register 16 Select 0 5 2 CPO Register Descriptions The Config register specifies various configuration and capabilities information Most of the fields in the Config reg ister are initialized by hardware during the Reset exception process or are constant 31 30 28 27 25 24 23 Figure 5 13 Config Register Format Select 0 22 21 20 19 17 16 15 14 13 12 10 9 7 6 M K23 Ku 0 BE AT upiss wv 0 DS ar wr Figure 5 14 Config Register Field Descriptions Fields Name Bit s Description Read Writ e Reset State M K23 KU 31 30 28 This bit is hardwired to 1 to indicate the presence of the R Config register This field controls the cacheability of the kseg2 and kseg3 address segments in FM implementations
291. previ ously missing Changed KO KU and K23 fields in Config register to be read only with a static value of 2 01 01 August 29 2002 Removed EIC field from ntCtl register per change in MIPS32 Release 2 Architecture External interrupt controller mode is specified by Config3ygjc 01 02 December 15 2003 CPO Config register Added CA field description corrected typo in IS IL IA DS DL DA field description Trademark updates Replaced reference to obsolete MD00232 with MD00086 Updated crossrefs in Status register description 01 03 October 29 2004 Added CorExtend Unusable exception Added note that EJTAG accesses and external memory accesses are serialized by the core 02 00 02 01 June 22 2006 Corrected minor errors related to EJTAG trace Clarified read only nature of several CPO register fields and removed several references to ASID since the M4K core does not contain a TLB Clarified description of mapped and unmapped segments with FM based memory management unit Added description on possible uses for trace triggers September 28 2006 Minor changes for addition of M4K Lite core to the M4K family 02 02 02 03 March 21 2008 Fixed select number for Debug register August 29 2008 Fixed address for Data Value Match Register MIPS32 M4K Processor Core Software User s Manual Revision 02 03 235 Copyright 2002 2008 MIPS Technologies Inc All rights reserv
292. qpy stage 6 Since a 32x32 multiply requires two passes through the multiplier with each pass requiring one clock the 32x32 Mult remains in the Myqpy stage in cycle 6 The Sub instruction enters M stage in the integer pipeline The Add operation completes and is written to the register file in the W stage of the integer pipeline 7 The Mult multiply operation progresses to the Ayr stage and the Sub instruction progress to the A stage 8 The Mult operation completes and is written to the HI LO registers pair the Wy py stage while the Sub instruc tion write to the register file in the W stage 2 3 1 32x16 Multiply High Performance MDU The 32x16 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires one clock and occurs in the Mypy stage In the Aypy stage the carry propagate add CPA function occurs and the operation is completed The result is ready to be read from the HI LO registers in the Wy stage Figure 2 4 shows a diagram of a 32x16 multiply operation Figure 2 4 MDU Pipeline Flow During a 32x16 Multiply Operation Clock 1 2 3 4 Booth Array CPA Res Rdy 2 3 2 32x32 Multiply High Performance MDU The 32x32 multiply operation begins in the last phase of the E stage which is shared be
293. r Field Descriptions Continued Fields Read Wr Name Bit s Description ite Reset State Undefined Indicates that a debug instruction break exception occurred Cleared on exception in debug mode 0 No debug instruction exception 1 Debug instruction exception Indicates that a debug data break exception occurred on Undefined a store Cleared on exception in debug mode R 0 No debug data exception on a store 1 Debug instruction exception on a store DDBL 2 Indicates that a debug data break exception occurred on Undefined a load Cleared on exception in debug mode 0 No debug data exception on a load 1 Debug instruction exception on a load DBp 1 Indicates that a debug software breakpoint exception R Undefined occurred Cleared on exception in debug mode 0 No debug software breakpoint exception 1 Debug software breakpoint exception DSS 0 Indicates that a debug single step exception occurred R Undefined Cleared on exception in debug mode 0 No debug single step exception 1 Debug single step exception 5 2 18 Trace Control Register CPO Register 23 Select 1 The TraceContro register configuration is shown below Note the special behavior of the ASID M ASID and G fields for the M4K processor This register is only implemented if the EJTAG Trace capability is present Figure 5 19 TraceContro Register Format 31 30 29 28 27 26 25 24 23 22 21 20 13 12 5 4 3 1 0 U T TS T 0 B IO D E K S U AS
294. r as remaining instructions continue through the pipeline the product of the multiply instruction is saved in the HI and LO registers If the multiply instruction is followed by an MFHI or MFLO before the product is available the pipeline interlocks until this product does become available Refer to Chapter 2 Pipeline of the M4K Core on page 23 for more information on instruction latency and repeat rates 9 4 Jump and Branch Instructions Jump and branch instructions change the control flow of a program All jump and branch instructions occur with a delay of one instruction that is the instruction immediately following the jump or branch this is known as the instruction in the delay slot always executes while the target instruction is being fetched from storage 9 4 1 Overview of Jump Instructions Subroutine calls in high level languages are usually implemented with Jump or Jump and Link instructions both of which are J type instructions In J type format the 26 bit target address shifts left 2 bits and combines with the high order 4 bits of the current program counter to form an absolute address Returns dispatches and large cross page jumps are usually implemented with the Jump Register or Jump and Link Register instructions Both are R type instructions that take the 32 bit byte address contained in one of the general purpose registers For more information about jump instructions refer to the individual instructions in 10 3
295. race Inputs 1 In_TraceOn when on legal trace words are coming from the core and at the point when it is turned on that is for the first traced instruction a full PC value is output When off it cannot be assumed that legal trace words are available at the core interface In_Stall This says stall the processor to avoid buffer overflow that can lose trace information When off a buffer overflow will simply throw away trace data and start over again When on the processor is signalled from the tracing logic to stall until the buffer is sufficiently drained and then the pipeline is restarted 8 8 1 2 Trace Outputs l Stall cycles in the pipe are ignored by the tracing logic and are not traced This is indicated by a valid signal Out Valid that is turned off when no valid instruction is being traced When the valid signal is on instructions are traced out as described in the rest of this section The traced instruction PC is a virtual address In the output format every sequentially executed instruction is traced as bit 0 Every instruction that is not sequential to the previous one is traced as either a 10 or an 11 This implies that the target instruction of a branch or jump is traced this way not the actual branch or jump instruction this is similar to PDtrace A 10 instruction implies a taken branch for a conditional branch instruction whose condition is unpredictable statically but whose branch target can be computed statica
296. race memory or to the Trace Probe controlled by the setting of the The TCB can optionally include trigger logic which can control the TCBCONTROLBgy bit Please see 8 13 TCB Trigger logic for details 8 12 5 Tracing a Reset Exception Tracing a reset exception is possible However the TraceControlrs bit is reset to 0 at core reset so all the trace con trol must be from the TCB using TCBCONTROLA and TCBCONTROLB The PDtrace fifo and the entire TCB are reset based on an EJTAG reset It is thus possible to set up the trace modes etc using the TAP controller and then reset the processor core 196 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 13 TCB Trigger logic 8 13 TCB Trigger logic The TCB is optionally implemented with trigger unit If this is the case then the TCBCONFIGrgg field is non zero This section will explain some of the issues around triggers in the TCB 8 13 1 Trigger Units Overview TCB trigger logic features three main parts 1 Acommon Trigger Source detection unit 2 ltoS8 separate Trigger Control units 3 Acommon Trigger Action unit Figure 8 7 show the functional overview of the trigger flow in the TCB Figure 8 7 TCB Trigger Processing Overview Trigger sources Trigger Source Unit Trigger strobes Trigger control Unit 1 to 7 are optional when trigger logic is implemented Trigger
297. ranch just before the SDBBP instruction causes a debug single step exception with the DEPC pointing to the SDBBP instruction To ensure proper functionality of single step the debug single step exception has priority over all other exceptions except reset and soft reset Debug Register Debug Status Bit Set DSS Additional State Saved None Entry Vector Used Debug exception vector 4 8 3 Debug Interrupt Exception A debug interrupt exception is either caused by the EjtagBrk bit in the EJTAG Control register controlled through the TAP or caused by the debug interrupt request signal to the CPU The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible but with no specific relation to the executed instructions The DEPC register is set to the instruction where execution should con tinue after the debug handler is through The DBD bit is set based on whether the interrupted instruction was execut ing in the delay slot of a branch Debug Register Debug Status Bit Set DINT Additional State Saved None Entry Vector Used Debug exception vector MIPS32 M4K Processor Core Software User s Manual Revision 02 03 738 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Exceptions and Interrupts in the M4K Core 74 4 8 4 Non Maskable Interrupt NMI Exception A non maskable interrupt exception occurs when the S _NMI signal is asserted to the processor S _NMI i
298. re saving the EPC Status and SRSCtl registers t t F HF 0X setting up the appropriate GPR shadow set for the routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode below can not cover all nuances of this processing and is intended only to demonstrate the concepts and re enabling interrupts The sample code Use the current GPR shadow set and setup software context mfcO mfcO srl sw mfcO sw ins k1 CO Cause s k0 CO EPC JE k1 k1 S CauseRIPL k0 EPCSave AA k0 CO Status e k0 StatusSave 7d k0 k1 S StatusIPL 6 Read Cause to get RIPL value Get restart address Right justify RIPL field Save in memory Get Status value Save in memory Set IPL to RIPL in copy of Status MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 3 Interrupts mfcO kl CO SRSCtl Save SRSCtl if changing shadow sets sw k1 SRSCtlSave If switching shadow sets write new value to SRSCtlpgg here ins k0 zero S StatusEXL W StatusKSU W StatusERL W StatusEXL Clear KSU ERL EXL bits in k0 mtcO k0 CO Status Modify IPL switch to kernel mode re enable interrupts Tf switching shadow sets clear only KSU above write target address to EPC and do execute an eret to clear EXL switch shadow se
299. reakpoint control Enables the second pair pair1 of breakpoint registers to control the timer when under breakpoint control If the stopwatch timer is configured to be under breakpoint control by setting CBTControlsrm and this bit is set the breakpoints indicated in the StartChanl and StopChan1 fields will control the timer The M4K core only supports 1 pair of stopwatch control breakpoints so this field is not writeable and will read as 0 Indicates the instruction breakpoint channel that will stop the counter if the timer is under pairO breakpoint control R 0x4 StartChanO EnO 4 1 Indicates the instruction breakpoint channel that will start the counter if the timer is under pairO breakpoint control Enables the first pair pairO of breakpoint registers to control the timer when under breakpoint control If the stopwatch timer is configured to be under breakpoint control by setting CBTControlsrm and this bit is set the breakpoints indicated in the StartChanO and StopChan0 fields will control the timer The M4K core only supports 1 pair of stopwatch control breakpoints so this field is not writeable and will read as 1 8 2 9 4 Stopwatch Timer Count S7TCni Register 0x8908 Compliance Level Implemented if stopwatch timer is implemented The Stopwatch Timer Count STCnt register is the count value for the stopwatch timer MIPS32 M4K Processor Core Software User s Manual Revision 02 03
300. reamed to either on chip trace memory or to the trace probe Each of the major Trace Formats are of different size This complicates how to store this information into an on chip memory of fixed width without too much wasted space It also compli cates how to transmit data through a fixed width trace probe interface to off chip memory To minimize memory overhead and or bandwidth loss the Trace Formats are collected into Trace Words of fixed width A Trace Word TW is defined to be 64 bits wide An empty invalid TW is built of all zeros A TW which contains one or more valid TF s is guaranteed to have a non zero value on one of the four least significant bits 3 0 During operation of the TCB each TW is built from the TF s generated each clock cycle When all 64 bits are used the TW is full and can be sent to either on chip trace memory or to the trace probe 8 10 PDtrace Registers Software Control The CPO registers associated with PDtrace are listed in Table 8 36 and described in Chapter 5 CPO Registers of the M4K Core on page 85 Table 8 36 A List of Coprocessor 0 Trace Registers Register Se Register Number I Name Reference 23 1 TraceControl 5 2 18 Trace Control Register CPO Register 23 Select 1 on page 112 23 2 TraceControl2 5 2 19 Trace Control2 Register CPO Register 23 Select 2 on page 114 23 3 UserTraceData 5 2 20 User Trace Data Register CPO Register 23 Select 3
301. request disabled 1 Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled these bits are writ able but have no effect on the interrupt system Undefined UM 7 5 Reserved This field is ignored on write and read as 0 This bit denotes the base operating mode of the processor See 3 2 Modes of Operation on page 43 for a full dis cussion of operating modes The encoding of this bit is Encoding Meaning 0 Base mode is Kernel Mode 1 Base mode is User Mode 0 Undefined Note that the processor can also be in kernel mode if ERL or EXL is set regardless of the state of the UM bit This bit is reserved This bit is ignored on write and read as R 0 Zero 92 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 7 Status Register Field Descriptions Continued Fields Read Write Name Bits Description Reset State ERL 2 Error Level Set by the processor when a Reset Soft Reset R W 1 NMI or Cache Error exception are taken EXL Encoding 0 Normal level Meaning 1 Error level When ERL is set The processor is running in kernel mode nterrupts are disabled The ERET instruction will use the return address
302. reserved EJTAG Debug Support in the M4K Core The Bypass register is selected when the NORMALBOOT instruction is given 8 4 3 10 FASTDATA Instruction This selects the Data and the Fastdata registers at once as shown in Figure 8 3 Figure 8 3 TDI to TDO Path When in Shift DR State and FASTDATA Instruction is Selected TDI Data d Fastdata 7D0 8 4 3 11 TCBCONTROLA Instruction This instruction is used to select the TCBCONTROLA register to be connected between T Dl and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register 8 4 3 12 TCBCONTROLB Instruction This instruction is used to select the TCBCONTROL B register to be connected between TDI and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register 8 4 3 13 TCBDATA Instruction This instruction is used to select the TCBDATA register to be connected between 7D and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register It should be noted that the TCBDATA register is only an access register to other TCB registers The width of the TCBDATA register is dependent on the specific TCB register 8 5 EJTAG TAP Registers 158 The EJTAG TAP Module has one Instruction register and a num
303. riptions cue och cce aer ceto A ES 146 Table 8 24 STC Register Field DescriptiOlls irre cesses od Petit rore tir secet barra dE prec uina esatta neca AEE 147 Table 8 25 STCI Register Fleld DescrlpliOlls asd aidter idest are tcveada suits a Ru Eras dr es dsMdeda i pd cR QUAE 148 tableg 26 EJ TAG Interface PINS sonos inet aso tete ette Asics o desee a Lc EP PIT S META 152 Table 8 27 Implemented EJTAG Instr ctlOns nio iod e eite tete Pene tL nda het ENR 156 Table 8 28 Device Identification Beglster rri ettet reru t bb i aene a re Eia RNK RENANE ARNES 159 Table 8 29 Implementation Register Descriptions ssisssssssssseseseseenee ennt nnne nne 160 Table 8 90 EJTAG Control Register Descriptlons ucc tus c Ru toina ar eheu ste taie past nuire seen Daaa 161 Table 8 31 Fastdata Register Field DeSCTIDEHOIn iioc eei Ee Fen dae E er iex ele xus petu dus aan du pE CLEAR lade RT 166 Table 8 92 Operation of the FASTDA TA ACCESS i erint rtis testi eet a rra dae n Pes xa Paare ak a aec RE xd REESE 167 Table 8 33 erigere 172 Table 8 94 Registers Ir he HT OB eiiis e ed ett ma e se UE osse t ace Debt et LI M E spaces ahegtehes 173 Table 8 35 Registers that Enable Disable Trace from Complex Triggers and their drseg Addresses 174 Table 8 96 A List of Coprocessor O Trace Registers coiere trt rri erc pese pares cas le kd eg E kan 179 Table 8 97 GB EJTAG IGgiSterssioapeocite eco ecce u che ier ur tetti secu E
304. rocessor 2 Mem Rs offset CPR 2 n 0 SWL Store Word Left See SWL instruction description SWR Store Word Right See SWR instruction description SYNC Synchronize See SYNC instruction below SYNCI Synchronize Caches to Make Instruction Writes Nop Effective SYSCALL System Call SystemCallException TEQ Trap if Equal if Rs Rt TrapException TEQI Trap if Equal Immediate if Rs int Immed TrapException TGE Trap if Greater Than or Equal if int Rs gt int Rt TrapException TGEI Trap if Greater Than or Equal Immediate if int Rs gt int Immed TrapException TGEIU Trap if Greater Than or Equal Immediate if uns Rs gt uns Immed Unsigned TrapException TGEU Trap if Greater Than or Equal Unsigned if uns Rs gt uns Rt TrapException TLT Trap if Less Than if int Rs lt int Rt TrapException TLTI Trap if Less Than Immediate if int Rs lt int Immed TrapException TLTIU Trap if Less Than Immediate Unsigned if uns Rs lt uns Immed TrapException TLTU Trap if Less Than Unsigned if uns Rs lt uns Rt TrapException TNE Trap if Not Equal if Rs Rt TrapException TNEI Trap if Not Equal Immediate if Rs int Immed TrapException WAIT Wait for Interrupts Stall until interrupt occurs WRPGPR Write to GPR in Previous Shadow Set SGPR SRSCtlpss Rd Rt WSBH Word Swap Bytes within Halfwords RdzSwapBytesWithinHalfs Rt MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc
305. rved in the M4K core Compare Timer interrupt control Status Processor status and control interrupt control and shadow set IntCtl control SRSCtl SRSMapl Cause of last exception Program counter at last exception MIPS32 M4K Processor Core Software User s Manual Revision 02 03 85 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 5 2 CPO Register Descriptions 86 Table 5 1 CPO Registers Continued Register Number Register Name Function PRId EBase Processor identification and revision exception base address Config Config1 Config2 Config3 Reserved Configuration registers Reserved in the M4K core Debug Debug2 TraceControl TraceControl2 UserTraceData TraceBPC Debug control exception status and EJTAG trace control DEPC Reserved Program counter at last debug exception Reserved in the M4K core ErrorEPC Program counter at last error 1 Registers used in exception processing DeSAVE2 2 Registers used in debug Debug handler scratchpad register The CPO registers provide the interface between the ISA and the architecture Each register is discussed below with the registers presented in numerical order first by register number then by select field number For each register described below field descriptions include the read write properties of the field
306. s the throughput of multiply intensive operations is increased Four instructions multiply add MADD multiply add unsigned MADDU multiply subtract MSUB and multi ply subtract unsigned MSUBU are used to perform the multiply accumulate and multiply subtract operations The MADD MADDU instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB MSUBU instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in DSP algo rithms All multiply operations except the MUL instruction write to the HI LO register pair All integer operations write to the general purpose registers GPR Because MDU operations write to different registers than integer operations fol lowing integer instructions can execute before the MDU operation has completed The MFLO and MFHI instructions are used to move data from the HI LO register pair to the GPR file If a MFLO or MFHI instruction is issued before the MDU operation completes it will stall to wait for the data 2 3 MDU Pipeline High Performance MDU 26 The M4Kprocessor core contains an autonomous multiply divide unit MDU with a separate pipeline for multiply and divide operations This pipeline operates in parallel with the integer unit IU pipeline and does not stall when the IU pipeline stalls This allows multi cycle MDU operations
307. s Mask n DBMn Register 0x2108 0x100 n Compliance Level Implemented only for implemented data breakpoints MIPS32 M4K Processor Core Software User s Manual Revision 02 03 139 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core The Data Breakpoint Address Mask n DBMn register has the mask for the address compare used in the condition for data breakpoint n A 1 indicates that the corresponding address bit will not be considered in the match A mask value of all 0 s would require an exact address match while a mask value of all 1 s would match on any address DBMn Register Format 31 0 DBM Table 8 13 DBMn Register Field Descriptions Fields Read W Name Bit s Description rite DBM Data breakpoint address mask for condition Undefined 0 Corresponding address bit not masked Reset State 1 Corresponding address bit masked 8 2 8 4 Data Breakpoint ASID n DBASIDn Register 0x2110 0x100 n Compliance Level Implemented only for implemented data breakpoints For processors with a TLB based MMU this register is used to define an ASID value to be used in the match expres sion On the M4K processor this register is reserved and reads as 0 DBASIDn Register Format 31 8 7 0 Res ASID Table 8 14 DBASIDn Register Field Descriptions Fields Read Wr Name Bit s Description ite Reset State Res 31 8
308. s a return from the subroutine 1 2 1 6 Power Management The core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted hence reducing system power consumption during idle periods The core provides two mechanisms for system level low power support Register controlled power management e nstruction controlled power management MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 1 2 M4K Core Block Diagram In register controlled power management mode the core provides three bits in the CPO Status register for software control of the power management function and allows interrupts to be serviced even when the core is in power down mode In instruction controlled power down mode execution of the WAIT instruction is used to invoke low power mode Refer to Chapter 7 Power Management of the M4K Core on page 125 for more information on power manage ment 1 2 2 Optional Logic Blocks The core consists of the following optional logic blocks as shown in the block diagram in Figure 1 1 2 2 1 MIPS16e Application Specific Extension The M4K core includes optional support for the MIPS16e ASE This ASE improv
309. s an edge sensitive signal only one NMI exception will be taken each time it is asserted An NMI exception occurs only at instruction boundaries so it does not cause any reset or other hardware initialization The state of the cache memory and other processor states are consistent and all registers are preserved with the following exceptions The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruc tion in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC e PCisloaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OxBFCO_0000 Operation Statusggy amp 1 Statusgs 0 Statusgg amp 0 StatuSymr 1 StatuSga amp 1 if InstructionInBranchDelaySlot then ErrorEPC lt PC 4 else ErrorEPC lt PC endif PC OxBFCO 0000 4 8 5 Interrupt Exception The interrupt exception occurs when one or more of the six hardware two software or timer interrupt requests is enabled by the Status register and the interrupt input is asserted See 4 3 Interrupts on page 57 for more details about the processing of interrupts Register ExcCode Value Int MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002
310. s counters it will implement an 8b counter for each instruction breakpoint and a 16b counter for each data breakpoint If tuples are implemented they may only be supported on a subset of the data breakpoint channels This can be checked by seeing if the DBBCn7yp bit can be set to 1 Additionally some cores may support dynamically changing which instruction breakpoint is associated with a given data breakpoint This can be checked by attempting to write the DBCCn prium field If a M4K core implements tuple support it will support it for all data breakpoint channels and the instruction breakpoint association will be fixed If Priming Conditions are supported a core may only support a subset of the possible priming condition values This can be checked by 4 hf to the xXBCCNp cpq field If only 1 or 2 bits can be written the available priming conditions will be described in the PrCndA registers If 3 bits are writeable PrCndA and PrCndB will describe the conditions and if all 4 bits are writeable the PrCndA PrCndB PrCndC and PrCnaD registers will all exist Some cores may also support changing the priming conditions and this can be checked by attempting to write to the PrCnd registers If a M4K core supports priming conditions it will support 4 statically mapped priming conditions per breakpoint which will be described in the PrCndA registers MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Techno
311. s n BAn register has the address used in the condition for instruction breakpoint n IBAn Register Format 31 0 IBA Table 8 4 BAn Register Field Descriptions Description Reset State Instruction breakpoint address for condition Undefined 8 2 7 3 Instruction Breakpoint Address Mask n BMn Register 0x1108 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address Mask n BMn register has the mask for the address compare used in the condi tion for instruction breakpoint n A 1 indicates that the corresponding address bit will not be considered in the match A mask value of all 0 s would require an exact address match while a mask value of all 1 s would match on any address IBMn Register Format 31 0 IBM Table 8 5 BMn Register Field Descriptions Fields Read W Name Bit s Description rite Reset State IBM 31 0 Instruction breakpoint address mask for condition R W Undefined 0 Corresponding address bit not masked 1 Corresponding address bit masked MIPS32 M4K Processor Core Software User s Manual Revision 02 03 135 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core 8 2 7 4 Instruction Breakpoint ASID n BAS Dn Register 0x1110 n 0x100 Compliance Level Implemented only for implemented instruction breakpoints For processors with
312. s that don t implement Release 2 can emulate the function using the CACHE instruction 2 11 3 Eliminating Hazards The Spacing column shown in Table 2 6 and Table 2 7 indicates the number of unrelated instructions such as NOPs or SSNOPs that prior to the capabilities of Release 2 would need to be placed between the producer and consumer of the hazard in order to ensure that the effects of the first instruction are seen by the second instruction Entries in the table that are listed as 0 are traditional MIPS hazards which are not hazards on the M4K core With the hazard elimination instructions available in Release 2 the preferred method to eliminate hazards is to place one of the instructions listed in Table 2 8 between the producer and consumer of the hazard Execution hazards can be removed by using the EHB JALR HB or JR HB instructions Instruction hazards can be removed by using the JALR HB or JR HB instructions in conjunction with the SYNCI instruction Since the M4K core does not contain caches the SYNCI instruction is not strictly necessary but is still recommended to create portable code that can be run on other MIPS processors that may contain caches MIPS32 M4K Processor Core Software User s Manual Revision 02 03 41 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core 42 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies In
313. se an action that by itself causes an SC for the same block to fail on another processor An execution of LL does not have to be followed by execution of SC a program is free to abandon the RMW sequence without attempting a write Restrictions The addressed location must be synchronizable by all processors and I O devices sharing the location if it is not the result in UNPREDICTABLE Which storage is synchronizable is a function of both CPU and system implementa tions See the documentation of the SC instruction for the formal definition The addressed location may be uncached for the M4K core The effective address must be naturally aligned If either of the 2 least significant bits of the effective address is non zero an Address Error exception occurs Operation vAddr sign extend offset GPR base if vAddr 9 0 then SignalException AddressError endif pAddr CCA lt AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr DATA GPR rt lt memword LLbit 1 Exceptions TLB Refill TLB Invalid Address Error Reserved Instruction Watch Programming Notes There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS T
314. sejy 0 or vector offset 1642200 if Cause y 1 This mode is in effect if any of the following conditions are true e Causeyz0 e Statlusggy 1 e IniCtlys 0 which would be the case if vectored interrupts are not implemented or have been disabled A typical software handler for interrupt compatibility mode might look as follows Cause 1 if it were zero the interrupt exception would have to be isolated from the general exception vector before getting GPRs k0 and k1 are available no shadow register switches invoked in compatibility mode The software priority is IP7 IPO HW5 HWO SW1 SWO Assumptions here Location Offset 0x200 from exception base u IVexception mfcO k0 CO Cause mfcO k1 CO Status Read Cause register for IP bits and Status register for IM bits andi k0 k0 M_CauseIM Keep only IP bits from Cause and k0 k0 k1 and mask with IM bits beq k0 zero Dismiss no bits set spurious interrupt MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved F ORO F F FF F F F F X FF RS Xo RS X X X P9 4 3 Interrupts clz k0 KO Find first bit set IP7 IP0 k0 16 23 xori k0 k0 0x17 FR MOS e235 gt 3 0 sll k0 k0 VS Shift to emulate software IntCtly g la k1 VectorBase Get base of 8 interrupt vectors
315. served 0x2000 0000 ksegQ ksegl 0x0000 0000 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 3 4 System Control Coprocessor Figure 3 7 FM Memory Map ERL 1 in the M4K Processor Core Virtual Address kseg3 OxE000_0000 kseg2 OxC000_0000 ksegl 0xAO000 0000 kseg0 0x8000 0000 useg kuseg 0x 0000 0000 Physical Address kseg3 OxEO000 0000 kseg2 OxC000_0000 reserved 0x8000_0000 useg kuseg 0x2000_0000 ksegQ ksegl 0x0000 0000 3 4 System Control Coprocessor The System Control Coprocessor CPO is implemented as an integral part of M4K processor core and supports mem ory management address translation exception handling and other privileged operations Certain CPO registers are used to support memory management Refer to Chapter 5 CPO Registers of the M4K Core on page 85 for more information on the CPO register set MIPS32 M4K Processor Core Software User s Manual Revision 02 03 53 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Memory Management of the M4K Core 54 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts in the M4K Core The M4K processor core receives exceptions from a number of sources includi
316. settings of the M and E bits enable the interrupts Operating Modes If the DM bit in the Debug register is 1 then the processor is in debug mode otherwise the pro cessor is in either kernel or user mode The following CPU Status register bit settings determine user or kernel mode e User mode UM 1 EXL 0 and ERL 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 89 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core e Kernel mode UM 0 or EXL 1 or ERL 1 Coprocessor Accessibility The Status register CU bits control coprocessor accessibility If any coprocessor is unus able then an instruction that accesses it generates an exception Figure 5 5 shows the format of the Status register Table 5 7 describes the Status register fields Figure 5 5 Status Register Format 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0 CU3 CUO RP FR RE R BEV TS SR NMI R CEE R IM7 IM2 IM1 IMO R UM R ERL EXL IE IPL Table 5 7 Status Register Field Descriptions Fields Read Name Bits Description Write Reset State CU3 31 Controls access to coprocessor 3 COP3 is not supported R 0 This bit cannot be written and will read as 0 CU2 30 Controls access to coprocessor 2 This bit can only be writ R W 0 ten if coprocessor is attached to the COP2 interface C2 bit in
317. special interrupt vector 16 200 In implementations of Release 2 of the architecture if the Causejy is 1 and Statuspgy is 0 the special interrupt vector represents the base of the vectored interrupt table WP 22 Indicates that a watch exception was deferred because R 0 Statusgx or Statusppy were a one at the time the watch exception was detected This bit both indicates that the watch exception was deferred and causes the exception to be initiated once Statusgyx and Statusgpy are both Zero As such software must clear this bit as part of the watch exception handler to prevent a watch exception loop Software should not write a 1 to this bit when its value is a 0 thereby causing a 0 to 1 transition If such a transi tion is caused by software itis UNPREDICTABLE whether hardware ignores the write accepts the write with no side effects or accepts the write and initiates a watch exception once Statusgx and Statuspg are both Zero Since watch registers are not implemented on the M4K core this bit is ignored on write and read as zero 100 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 12 Cause Register Field Descriptions Continued Fields i Read Wri Name Bits Description te Reset State
318. stdata access was successful or not if completion was requested Fastdata Register Format 0 Table 8 31 Fastdata Register Field Description Power up Description State SPrAcc Shifting in a zero value requests completion of the Fast Undefined data access The PrAcc bit in the EJTAG Control register is overwritten with zero when the access succeeds The access succeeds if PrAcc is one and the operation address is in the legal dmseg Fastdata area When successful a one is shifted out Shifting out a zero indicates a Fastdata access failure Shifting in a one does not complete the Fastdata access and the PrAcc bit is unchanged Shifting out a one indi cates that the access would have been successful if allowed to complete and a zero indicates the access would not have successfully completed 166 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 6 TAP Processor Accesses The FASTDATA access is used for efficient block transfers between dmseg on the probe and target memory on the processor An upload is defined as a sequence of processor loads from target memory and stores to dmseg A download is a sequence of processor loads from dmseg and stores to target memory The Fastdata area specifies the legal range of dmseg addresses OxFF20 0000 OxFF20 000F that can be used for uploads and downloads The Data Fastdata r
319. ster Format 31 n 1 n 0 Address Table 8 45 TCBRDP Register Field Descriptions Description rite NEL NE Read W eesti Be 31 n 1 Reserved Must be written zero reads back zero 0 oa Address n 0 Byte address of on chip trace memory word R W 0 8 11 7 TCBWHRP Register Reg 6 The TCBWRHP register is the address pointer to on chip trace memory It points to the location where the next new IW for on chip trace will be written This register is reserved if on chip trace memory is not implemented The format of the 7CBWHP register is shown below and the fields are described in Table 8 46 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW the lower three bits are always Zero TCBWRP Register Format n 0 31 n 1 Table 8 46 TCBWHRP Register Field Descriptions Read W Data 31 n 1 Reserved Must be written zero reads back zero Address n 0 Byte address of on chip trace memory word 8 11 8 TCBSTP Register Reg 7 The TCBSTP register is the start pointer register This register points to the on chip trace memory address at which the oldest TW is located This pointer is reset to zero when the TCBCONTROLByz bit is written to 1 If a continu ous trace to on chip memory wraps around the on chip memory 7 SBSTP will have the same value as TCBWAP 190 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyri
320. struction immediately following a branch is always executed regardless of the branch direction If no useful instruction can be placed after the branch then the compiler or assembler must insert a NOP instruction in the delay slot Figure 2 13 illustrates the branch delay MIPS32 M4K Processor Core Software User s Manual Revision 02 03 33 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core Figure 2 13 IU Pipeline Branch Delay One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle J ump or Branch Delay Slot Instruction J ump Target Instruction One Clock Branch Delay 2 6 Data Bypassing Most MIPS32 instructions use one or two register values as source operands These operands are fetched from the register file in the first part of E stage The ALU straddles the E to M boundary and can present the result early in M stage The result is not written to the register file before the W stage however If no precautions were made it would take 3 cycles before the result was available for the following instructions To avoid this data bypassing is imple mented Between the register file and the ALU a data bypass multiplexer is placed on both operands see Figure 2 14 This enables the M4K core to forward data from a preceding instruction whose target is a source register of a following instruction An M to E bypass and an A to E bypass feed the bypass mu
321. t always reads as 0 because MDMX is not supported Performance Counter registers implemented Always a 0 since the M4K core does not contain Performance Counters Watch registers implemented 0 No Watch registers are present 1 One or more Watch registers are present This bit is always read as 0 since the M4K core does not contain Watch registers Code compression MIPS 16e implemented 0 No MIPS16e present 1 MIPS 16e is implemented EJTAG present This bit is always set to indicate that the core implements EJTAG FPU implemented This bit is always zero since the core does not contain a floating point unit 5 2 15 Config2 Register CPO Register 16 Select 2 The Config2 register is an adjunct to the Config register and is reserved to encode additional capabilities informa tion Config2 is allocated for showing the configuration of level 2 3 caches These fields are reset to 0 because L2 L3 caches are not supported by the M4K core All fields in the Config2 register are read only Figure 5 16 Config2 Register Format Select 2 31 30 0 M 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 107 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core Table 5 19 Config Register Field Descriptions Select 1 Fields Read Wri Name Bit s Description te Reset State This bit is hardwired to 1 to indicate the pr
322. talls do not add to the latency of 2 4 If both operands are positive then the Sign Adjust stage is bypassed Latency is then the same as for DIVU In Table 2 1 a latency of one means that the first and second instructions can be issued back to back in the code with out the MDU causing any stalls in the IU pipeline A latency of two means that if issued back to back the IU pipeline will be stalled for one cycle MUL operations are special because it needs to stall the IU pipeline in order to maintain its register file write slot Consequently the MUL 16x16 or 32x16 operation will always force a one cycle stall of the IU pipeline and the MUL 32x32 will force a two cycle stall If the integer instruction immediately following the MUL operation uses its result an additional stall is forced on the IU pipeline MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 27 Pipeline of the M4K Core Table 2 2 lists the repeat rates peak issue rate of cycles until the operation can be reissued for multiply accumu late subtract instructions The repeat rates are listed in terms of pipeline clocks In this table repeat rate refers to the case where the first MDU instruction in the table below if back to back with the second instruction Table 2 2 MDU Instruction Repeat Rates High Performance MDU i Instruction Sequence Operand Size of 1st Re
323. tecture or EHB in Release 2 of the Architecture to guarantee that memory reference results are visible across operating mode changes For example a SYNC is required on entry to and exit from Debug Mode to guarantee that memory affects are han dled correctly Detailed Description SYNC does not guarantee the order in which instruction fetches are performed The stype values 1 31 are reserved for future extensions to the architecture A value of zero will always be defined such that it performs all defined synchronization operations Non zero values may be defined to remove some synchronization opera tions As such software should never use a non zero value of the stype field as this may inadvertently cause future failures if non zero values remove synchronization operations The SYNC instruction is externalized on the SRAM interface of the M4K core External logic can use this infor mation in a system dependent manner to enforce memory ordering between various memory elements in the sys tem Restrictions The effect of SYNC on the global order of loads and stores for memory access types other than uncached and cached coherent is UNPREDICTABLE Operation SyncOperation stype Exceptions None 226 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Enter Standby Mode WAIT 31 26 25 24 6 5 0 COPO CO WAIT 010000
324. ter Format 31 29 28 25 24 23 21 20 17 16 15 14 13 0 DINT EJTAGver reserved T ASIDsize reserved MIPS16 0 NoDMA reserved Table 8 29 mplementation Register Descriptions Read Wr Description i Reset State EJTAGver EJTAG Version 2 Version 2 6 reserved reserved 0 DINTsup DINT Signal Supported from Probe EJ_DINTsup This bit indicates if the DINT signal from the probe is supported 0 DINT signal from the probe is not supported 1 Probe can use DINT signal to make debug interrupt ASIDsize Size of ASID field in implementation 0 No ASID in implementation 1 6 bit ASID 2 8 bit ASID 3 Reserved reserved reserved MIPS 16 Indicates whether MIPS 16 is implemented 0 No MIPS16 support 1 MIPS16 implemented NoDMA No EJTAG DMA Support reserved reserved reserved 13 0 reserved R 0 8 5 2 4 EJTAG Control Register This 32 bit register controls the various operations of the TAP modules This register is selected by shifting in the CONTROL instruction Bits in the EJTAG Control register can be set cleared by shifting in data status is read by shifting out the contents of this register This EJTAG Control register can only be accessed by the TAP interface The EJTAG Control register is not updated in the Update DR state unless the Reset occurred Rocc bit 31 is either 0 or written to 0 This is in order to ensure prober handling of processor accesses MIPS32 M4
325. ter holds implementation and status information about the data breakpoints DBS Register Format 29 28 27 24 23 210 fesse PO g Table 8 11 DBS Register Field Descriptions Fields Po Read Wr Name Bit s Description ite Reset State Res 31 Must be written as zero returns zero on read R 0 ASID 30 Indicates that ASID compares are supported in data R 0 breakpoints 0 Not supported 1 Supported Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of data breakpoints implemented R 2 or 12 Res 23 2 Must be written as zero returns zero on read R 0 BS 1 0 Break status for breakpoint n is at BS n with n from 0 R WO Undefined to 1 The bit is set to 1 when the condition for the corre sponding breakpoint has matched a Based on actual hardware implemented b In case of only 1 data breakpoint bit 1 become reserved 8 2 8 2 Data Breakpoint Address n DBAn Register 0x2100 0x100 n Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address n DBAn register has the address used in the condition for data breakpoint n DBAn Register Format 31 0 DBA Table 8 12 DBAn Register Field Descriptions Fields Read W De ma Bit s Description rite Reset State 30 0 Data Data breakpoint address for condition Data breakpoint address for condition for condition Undefined 8 2 8 3 Data Breakpoint Addres
326. ter in any other case This is the condition for a non interrupt exception or a non vectored interrupt Similarly the rules for updating the fields in the SRSCtl register at the end of an exception or interrupt are as follows 1 No field in the SRSCi register is updated if any of the following conditions is true In this case step 2 is skipped A DERET is executed e An ERET is executed with Statusep 1 2 SHSCtlpssis copied to SHSCtloss These rules have the effect of preserving the SHSCII register in any case of a nested exception or one which occurs before the processor has been fully initialize StatuSgry 1 Privileged software may switch the current shadow set by writing a new value into SRSCtlpss loading EPC with a target address and doing an ERET 4 5 Exception Vector Locations The Reset Soft Reset and NMI exceptions are always vectored to location 164 BFCO0 0000 EJTAG Debug excep tions are vectored to location 16 BFCO 0480 or to location 16 FF20 0200 if the ProbTrap bit is zero or one respectively in the EJTAG Control register Addresses for all other exceptions are a combination of a vector offset and a vector base address In Release 1 of the architecture the vector base address was fixed In Release 2 of the architecture software is allowed to specify the vector base address via the EBase register for exceptions that occur when StatuSggy equals 0 Table 4 5 gives the vector base address as a function of
327. ter is written 192 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Table 8 48 TCBTRIGx Register Field Descriptions Continued 8 11 Trace Control Block TCB Registers Hardware Control Fields Names Bits Description Read W rite Reset State Type FO 3 2 Trigger Type The Type indicates the action to take when this trig ger fires The table below show the Type values and the Trigger action Type Trigger action 00 Trigger Start Trigger start point of trace 01 Trigger End Trigger end point of trace 10 Trigger About Trigger center point of trace 11 Trigger Info No action trigger only for trace info The actual action is to set or clear the TCBCONTROLBgy bit A Start trigger will set TCBCONTROLBgy a End trigger will clear TCBCONTROLBgy The About trigger will clear TCBCONTHROLBgy half way through the trace memory from the trigger The size determined by the TCBCONF Gs field for on chip memory Or from the TCBCONTROLAgyp field for off chip trace If Trace is set then a TF6 format is added to the trace words For Start and Info triggers this is done before any other TF s in that same cycle For End and About triggers the TF6 format is added after any other TF s in that same cycle If the TCBCONTROLB py field is implemented it must be set to Trace
328. ter is zero the EPC register is loaded with the PC at which execution will be restarted and the BD bit is set appropriately in the Cause register see Table 5 12 The value loaded into the EPC register is dependent on whether the processor implements the MIPS16e ASE and whether the instruction is in the delay slot of a branch or jump which has delay slots Table 4 8 shows the value stored in each of the CPO PC registers including EPC For implementations of Release 2 of the Architecture if Statusgry 0 the CSS field in the SHSCII register is copied to the PSS field and the CSS value is loaded from the appropriate source If the EXL bit in the Status register is set the EPC register is not loaded and the BD bit is not changed in the Cause register For implementations of Release 2 of the Architecture the SHSCII register is not changed Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception MIPS16e In Branch Jump Implemented Delay Slot Value stored in EPC ErrorEPC DEPC No No Address of the instruction No Yes Address of the branch or jump instruction PC 4 Yes No Upper 31 bits of the address of the instruction combined with the SA Mode bit Yes Yes Upper 31 bits of the branch or jump instruction PC 2 in the MIPS16e ISA Mode and PC 4 in the 32 bit ISA Mode combined with the SA Mode bit e The CE and ExcCode fields of the Cause registers are loaded with the values appropriate to the exception Th
329. the LSNM bit in the CPO Debug register controls transactions to from the dmseg When a debug exception is taken while the ProbTrap bit is set the processor will start fetching instructions from address 0xFF20 0200 A pending processor access can only finish if the probe writes 0 to PrAcc or by a soft or hard reset 8 6 1 Fetch Load and Store from to the EJTAG Probe through dmseg 1 The internal hardware latches the requested address into the PA Address register in case of the Debug exception OxFF20 0200 2 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PRnW 0 selects processor read operation Psz 1 0 value depending on the transfer size 3 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out 4 The EJTAG Probe checks the PRnW bit to determine the required access 5 The EJTAG Probe selects the PA Address register and shifts out the requested address 6 The EJTAG Probe selects the PA Data register and shifts in the instruction corresponding to this address 7 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the instruction is available 8 The instruction becomes available in the
330. the M4K Core 152 8 4 1 EJTAG Internal and External Interfaces The external interface of the EJTAG module consists of the 5 signals defined by the IEEE standard Table 8 26 EJTAG Interface Pins Pin Type Description TCK Test Clock Input Input clock used to shift data into or out of the Instruction or data regis ters The TCK clock is independent of the processor clock so the EJTAG probe can drive TCK independently of the processor clock frequency The core signal for this is called EJ_TCK TMS Test Mode Select Input The TMS input signal is decoded by the TAP controller to control test operation TMS is sampled on the rising edge of TCK The core signal for this is called EJ_TMS TDI Test Data Input Serial input data TDI is shifted into the Instruction register or data regis ters on the rising edge of the TCK clock depending on the TAP controller state The core signal for this is called EJ TDI TDO Test Data Output Serial output data is shifted from the Instruction or data register to the TDO pin on the falling edge of the TCK clock When no data is shifted out the TDO is 3 stated The core signal for this is called EJ_TDO with output enable controlled by EJ TDOzstate TRST_N Test Reset Input Optional pin The TRST_N pin is an active low signal for asynchronous reset of the TAP controller and instruction in the TAP module independent of the pro cessor logic The processor is not reset by the ass
331. the architecture 16 BFCO 0200 16 8000 0000 For Release 2 of the architecture EBase3 12 16 000 Note that EBase3 39 have the fixed value 2410 Table 4 6 Exception Vector Offsets Exception Vector Offset General Exception 164180 Interrupt Causery 1 164200 In Release 2 implementa tions this is the base of the vectored interrupt table when Statuspggy 0 Reset Soft Reset NMI None Uses Reset Base Address Table 4 7 Exception Vectors Vector EN For Release 2 Implementations assumes EJTAG that EBase retains its reset Exception Statuspey Statusey Causey ProbEn state and that IntCtlys 0 Reset Soft Reset NMI X x X X 16 BFCO 0000 EJTAG Debug X X X 0 16 BFCO 0480 EJTAG Debug X x x 1 164FF20 0200 Interrupt 0 0 0 X 16 8000 0180 Interrupt 0 0 1 X 16 8000 0200 Interrupt 1 0 0 X 16 BFCO 0380 Interrupt 1 0 1 X 16 BFCO 0400 All others 0 X X X 16 8000 0180 All others 1 x X X 16 BFCO 0380 x denotes don t care 4 6 General Exception Processing With the exception of Reset Soft Reset NMI cache error and EJTAG Debug exceptions which have their own spe cial processing as described below exceptions have the same basic processing flow 68 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 6 General Exception Processing If the EXL bit in the Status regis
332. the clocks and service the inter rupt or let it be serviced at the lower clock speed The setting of the ERL bit causes the assertion of the S _EAL signal on the external bus indicating to the external agent that an error has occurred At this time the external agent can choose to either speed up the clocks and service the error or let it be serviced at the lower clock speed Similarly the EJ DebugM signal indicates that the processor is in debug mode Debug mode is entered when the processor takes a debug exception If fast handling of this is desired the external agent can speed up the clocks The core provides four power down signals that are part of the system interface Three of the pins change state as the corresponding bits in the CPO Status register are set or cleared The fourth pin indicates that the processor is in debug mode The S HP signal represents the state of the RP bit 27 in the CPO Status register e The S EXL signal represents the state of the EXL bit 1 in the CPO Status register e The S EHL signal represents the state of the ERL bit 2 in the CPO Status register MIPS32 M4K Processor Core Software User s Manual Revision 02 03 125 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Power Management of the M4K Core The EJ DebugM signal indicates that the processor has entered debug mode 7 2 Instruction Controlled Power Management 126 The second mechanism for invoking power
333. ther to consider Causepcy for a potential interrupt Since performance counters are not implemented on the MAK core Configlpc 0 this field is ignored on write and returns zero on read Must be written as zero returns zero on read 0 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 8 IntCtl Register Field Descriptions Continued Fields Read Wr Reset Name Bits Description ite State Vector Spacing If vectored interrupts are implemented 0 as denoted by Config3yy _ or Config3ypyc this field specifies the spacing between vectored interrupts Spacing Spacing Between Between Vectors Encoding Vectors hex decimal 16 00 16 000 0 16 01 16 020 32 16 02 16 040 64 16 04 16 080 128 16 08 16 100 256 16 10 16 200 512 All other values are reserved The operation of the pro cessor is UNDEFINED if a reserved value is written to this field 0 4 0 Must be written as zero returns zero on read 0 0 5 2 7 SRSCtI Register CPO Register 12 Select 2 The SRSCtl register controls the operation of GPR shadow sets in the processor This register does not exist in imple mentations of the architecture prior to Release 2 Figure 5 7 shows the format of the SRSCt register Table 5 9 describes the SRSCtlI register fields Figure 5 7
334. ting for COP2 Condition Check D side SRAM Stall SRAM Access not complete Coprocessor 2 completion slip Coprocessor 2 control and or data delay from coprocessor MIPS32 M4K Processor Core Software User s Manual Revision 02 03 37 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core In general MIPS processors support two types of hardware interlocks e Stalls which are resolved by halting the pipeline e Slips which allow one part of the pipeline to advance while another part of the pipeline is held static In the M4K processor core all interlocks are handled as slips 2 9 Slip Conditions On every clock internal logic determines whether each pipe stage is allowed to advance These slip conditions propa gate backwards down the pipe For example if the M stage does not advance neither does the E or I stage Slipped instructions are retried on subsequent cycles until they issue The back end of the pipeline advances normally during slips This resolves the conflict when the slip was caused by a missing result NOPs are inserted into the bub ble in the pipeline Figure 2 19 shows an instruction cache miss Figure 2 19 Instruction Cache Miss Slip Clock 1 2 3 4 5 6 Stage lu 4 e iso E I hil ly l4 I M ILI mul A i35 a ae lofo qd Cache miss detected Q Critical word received Q Execute E stage Figure 2 19 shows a diagram of a two cycle slip In the
335. tion that caused the IB match equation to be true The instruction receiving the debug exception does not update any registers due to the instruction nor does any load or store by that instruction occur Thus a debug exception from a data breakpoint can not occur for instructions receiv ing a debug instruction break exception The debug handler usually returns to the instruction causing the debug instruction break exception whereby the instruction is executed Debug software is responsible for disabling the breakpoint when returning to the instruction otherwise the debug instruction break exception reoccurs 8 2 5 2 Debug Exception by Data Breakpoint If the breakpoint is enabled by BE bit in the DBCn register then a debug exception occurs when the DB match con dition is true The corresponding BS n bit in the DBS register is set when the breakpoint generates the debug excep tion A debug data break exception occurs when a data breakpoint indicates a match In this case the DEPC register and DBD bit in the Debug register points to the instruction that caused the DB match equation to be true MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints The instruction causing the debug data break exception does not update any registers due to the instruction and the following applies to the load or store transaction causing the debug exc
336. to the TCB The TCB must however be enabled to trans mit the trace information to the Trace probe or to on chip trace memory by having the 7 CBCONTROLBgy bit set It is possible to enable and disable the TCB in two ways Set clear the TCBCONTROLBgy bit via an EITAG TAP operation e Initialize a TCB trigger to set clear the TCBCONTROLBgn bit 8 9 8 TCB Trigger The TCB can optionally include 0 to 8 triggers A TCB trigger can be programmed to fire from any combination of Probe Trigger Input to the TCB e Chip level Trigger Input to the TCB e Processor entry into DebugMode When a trigger fires it can be programmed to have any combination of actions e Create Probe Trigger Output from TCB e Create Chip level Trigger Output from TCB e Set clear or start countdown to clear the TCBCONTROLBgy bit start end about trigger e Putan information byte into the trace stream Trace triggers may prove useful for various types of system debug If the system has a reasonable capability to pro gram the external triggers a wide variety of system information can be included in the trace e nsert system events into a trace e Using a timer event as a trigger that inserted a trace record would allow for performance analysis at a coarser granularity than cycle accurate mode but with better compression e The trace could be annotated with interesting system events like each time a packet is received or transmitted Trigger traces
337. trace Interface Specifi MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 9 EJTAG Trace cation for a detailed description While working closely together the two parts of EJTAG Trace are controlled separately by software Figure 8 6 shows an overview of the EJTAG Trace modules within the core Figure 8 6 EJTAG Trace Modules in the M4K Core CPO control bus EJ TAG TAP access l TAP Probe Control path Pipeline specific P Dtrace Pipeline independant module g Trace Contol Block TCB module Trace Probe Back stall to pipeline Extracted Pipeline Trace compression and Bemor optional information extraction alignment iik boundary m4k_top mm mm mm Trace 40 chip Trace e I To some extent the two modules both provide similar trace control features but the access to these features is quite different The PDtrace controls can only be reached through access to CPO registers The TCB controls can only be reached through EJTAG TAP access The TCB can then control what is traced through the PDtrace Interface Before describing the EJTAG Trace implemented in the M4K core some common terminology and basic features are explained The remaining sections of this chapter will then provide a more thorough explanation 8 9 1 Processor Modes Tracing can be enabled or disabled based on
338. tract operations The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in Digital Signal Processor DSP algorithms 2 1 3 System Control Coprocessor CPO In the MIPS architecture CPO is responsible for the virtual to physical address translation cache protocols the exception control system the processor s diagnostics capability operating mode selection kernel vs user mode and the enabling disabling of interrupts Configuration information such as presence of build time options are available by accessing the CPO registers Refer to Chapter 5 CPO Registers of the M4K Core on page 85 for more infor MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 1 2 M4K Core Block Diagram mation on the CPO registers Refer to Chapter 8 EJTAG Debug Support in the M4K Core on page 127 for more information on EJTAG debug registers 1 2 1 4 Memory Management Unit MMU The M4K core contains an MMU that interfaces between the execution unit and the SRAM controller shown in Figure 1 2 The M4K implement a FMT based MMU The FMT performs a simple translation to get the physical address from the virtual address
339. tribute used for the operation are determined by the memory access type and coherency attribute of the effective address just as it would be if the memory operation had been caused by a load or store to the effective address Table 10 1 Values of hint Field for PREF Instruction Value Name Data Use and Desired Prefetch Action 0 load Use Prefetched data is expected to be read not modified Action Fetch data as if for a load Use Prefetched data is expected to be stored or modified Action Fetch data as if for a store Reserved load_streamed Use Prefetched data is expected to be read not modified but not reused extensively it streams through cache store streamed Use Prefetched data is expected to be stored or modified but not reused exten sively it streams through cache load retained Use Prefetched data is expected to be read not modified and reused exten sively it should be retained in the cache MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Prefetch PREF Table 10 1 Values of hint Field for PREF Instruction store_retained Use Prefetched data is expected to be stored or modified and reused exten sively it should be retained in the cache writeback_invalidate also known as nudge 30 31 Restrictions None Operation vAddr GPR base sign extend offs
340. ts and jump to routine a Process interrupt here including clearing device interrupt The interrupt completion code is identical to that shown for VI mode above 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts For vectored interrupts in either VI or EIC interrupt mode a vector number is produced by the interrupt control logic This number is combined with ntCtlys to create the interrupt offset which is added to 1642200 to create the exception vector offset For VI interrupt mode the vector number is in the range 0 7 inclusive For EIC interrupt mode the vector number is in the range 0 63 inclusive The ntCtlys field specifies the spacing between vector loca tions If this value is zero the default reset state the vector spacing is zero and the processor reverts to Interrupt Compatibility Mode A non zero value enables vectored interrupts and Table 4 4 shows the exception vector offset for a representative subset of the vector numbers and values of the ntCtlys field Table 4 4 Exception Vector Offsets for Vectored Interrupts Value of IntCtlys Field Vector Number 2400001 2400010 2400100 25401000 2210000 0 1630200 1630200 1630200 1630200 1630200 1 16 0220 16 0240 16 0280 16 0300 16 0400 2 16 0240 16 0280 16 0300 16 0400 16 0600 3 16 0260 16 02CO 16 0380 16 0500 16 0800 4 16 0280 16 0300 16 0400 16 0600 16 0A00 5 16 02A0 16 0340 16 0480 16 0700 16 0C00 6 16 02C0
341. tted TF s The stall information included excluded is TF6 formats with TCBcode 0001 and 0101 All TFI formats If set to 1 trace is sent to off chip memory using 7H DATA pins If set to 0 trace info is sent to on chip memory This bit is read only if a single memory option exists either off chip or on chip only MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Preset 8 11 Trace Control Block TCB Registers Hardware Control Table 8 40 TCBCONTROLB Register Field Descriptions Continued Fields Read Wr Name Bits Description ite Reset State EN 0 Enable trace R W 0 This is the master enable for trace to be generated from the TCB This bit can be set or cleared either by writing this regis ter or from a start stop about trigger When set to 1 trace information is sampled on the PDO_ pins Trace Words are generated and sent to either on chip memory or to the Trace Probe The target of the trace is selected by the OfC bit When set to 0 trace information on the PDO_ pins is ignored A potential TF6 stop from a stop trigger is generated as the last information the TCB pipe line is flushed and trace output is stopped Table 8 41 Clock Ratio encoding of the CR field CR CRMin CRMax Clock Ratio 000 8 1 Trace clock is eight times that of core clock 001 4 1 Trace clock is
342. turns zero on read R a PassCnt 15 0 Prevents a break trigger action until the matching condi tions on data breakpoint n have been seen this number of times Each time the matching condition is seen this value will be decremented by 1 Once the value reaches 0 subse quent matches will cause a break or trigger as requested and the counter will stay at 0 The break or trigger action is imprecise if the PassCnt register was last written to a non zero value It will remain imprecise until this register is written to 0 by soft ware 8 2 8 9 Data Value Match DVM Register Ox2ffo Compliance Level Implemented only if data breakpoints are implemented MIPS32 M4K Processor Core Software User s Manual Revision 02 03 143 Copyright 2002 2008 MIPS Technologies Inc All rights reserved EJTAG Debug Support in the M4K Core The Data Value Match DVM register captures the data value of a load that takes a precise data value breakpoint This allows debug software to synthesize the load instruction without reexecuting it in case it is to a system register that has destructive reads 31 DVM Register Format LDV Table 8 19 DVM Register Field Descriptions Name Read W rite Reset State Description Load data value for the last precise load data value breakpoint taken Undefined 8 2 9 Complex Breakpoint Registers The registers for complex breakpoints are described
343. tware User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 2 Hardware Breakpoints 8 2 7 6 Instruction Breakpoint Complex Control n BCCn Register 0x1120 n 0x100 Compliance Level Implemented only if complex breakpoints are implemented and only for implemented instruction breakpoints The Instruction Breakpoint Complex Control n BCCn register controls the complex break conditions for instruc tion breakpoint n IBCCn Register Format 31 14 13 10 8 5 4 3 2 1 0 9 g mcs oe pen o e Table 8 8 BCCn Register Field Descriptions Fields Description Read Write Reset State Must be written as zero returns zero on read R 0 Upper bits of priming condition for I breakpoint n M4K R 0 only supports 4 priming conditions so the upper 2 bits are read only as 0 Priming condition for I Breakpoint n R W 0 00 Bypass no priming needed Other vary depending on the break number refer to Table 8 10 for mapping Complex Break Enable enables this breakpoint for use R W 0 in a complex sequence as a priming condition for another breakpoint to start or stop the stopwatch timer or as part of a tuple breakpoint DBrkNum 8 5 Indicates which data breakpoint channel is used to qual R IBCCO 2 0 ify this instruction breakpoint IBCC3 6 1 Q 4 Qualify this breakpoint based on the data breakpoint indi R W 0 cated in DBrkNum 0 Not dependent on qualification 1 Bre
344. tween the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires two clocks and occurs in the Mypv stage In the Aypy stage the CPA func tion occurs and the operation is completed MIPS32 M4K Processor Core Software User s Manual Revision 02 03 29 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core Figure 2 5 shows a diagram of a 32x32 multiply operation Figure 2 5 MDU Pipeline Flow During a 32x32 Multiply Operation Clock 1 2 3 4 5 Ie E DPE Muy Muu Auu Wu gt Gk Rena 2 3 3 Divide High Performance MDU Divide operations are implemented using a simple non restoring division algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note that this cycle is spent even if the adjustment is not necessary During the next maximum 32 cycles 3 34 an iterative add subtract loop is executed In cycle 3 an early in detection is performed in parallel with the add subtract The adjusted rs operand is detected to be zero extended on the upper most 8 16 or 24 bits If this is the case the following 7 15 or 23 cycles of the add subtract iterations are skipped The remainder adjust Rem Adjust cycle is required if the remainder was negative Not
345. two instructions are allowed to execute since the jump branch and the instruction MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 4 8 Exceptions in the delay slot are executed as one step Debug single step exceptions are enabled by the SSt bit in the Debug regis ter and are always disabled for the first one two instructions after a DERET The DEPC register points to the instruction on which the debug single step exception occurred which is also the next instruction to single step or execute when returning from debug mode So the DEPC will not point to the instruction which has just been single stepped but rather the following instruction The DBD bit in the Debug register is never set for a debug single step exception since the jump branch and the instruction in the delay slot is executed in one step Exceptions occurring on the instruction s executed with debug single step exception enabled are taken even though debug single step was enabled For a normal exception other than reset a debug single step exception is then taken on the first instruction in the normal exception handler Debug exceptions are unaffected by single step mode e g returning to a SDBBP instruction with debug single step exceptions enabled causes a debug software breakpoint exception and the DEPC will point to the SDBBP instruction However returning to an instruction not jump b
346. u soem Lo Ux Ck oS RUM GR eu MP aiai 9 9 4 DUsage or Tuple Breakpolhis iori tec He Ee Hide kiss aee hi Hesse EL eei cu CUL aie edaduetie 9 3 5 Usagenr PRIMING COMMONS so ict creer ete tenet he at esed den eee htc settee Dbssee dere doux 9 9 0 Usage of Data Qualified Breakpolrits sictiscicedactraieteaesoecctisaaderd soraniciicassedacccniat heeded 8 3 7 Usage of Stopwatch Timers ccccccceceeeeeeeeeeeeeeeeeeeeaaeeceaeeeeeaaeeeeeeeeesaaeeeeceeeeseaeesseaaeesseeeessnaeessenees 6 4 Test Access Om TAP isis iriver tie erica naa deciding anata 9 434 EJTAG Internal and Exteral Merac ES isco cioe rerit a te te ves ied etes deett E 8 4 2 TeSt Access POM ODBIGUOIs 5 pisi diee cis iiie coi ERE sd ei tubes ei ba bd ea ud hc ade es reco E ra 8 4 3 Test Access Port TAP Instructions sseesssssssssssseeeeee eene nnns nnne nennen nennen enis 8 5 EJIAG TAP ROGISICNS 3 iiri nta ttc bet a bos a a IPAE i CHR eee EE 9E IMS EMI CHOU FABOISIOE oec ecce ttt ede E uds Sacs b user ue setae itas tope cd hue 8 5 2 Data Registers OVGIVIOW aee gaettice ur sesso msstase bravta RU cedes vd edsU d uo Dx Resa da uir Deed eai E Dp DxLRDE 8 5 3 Processor Access Address Register sse eene 8 5 4 Fastdata Register TAP Instruction FAS TDA TA eiae the deberet tristes tota to vocc iua sleek eaa anne s OG TAP Processor ACCESSES eiit eiecit tcdtasetitcset nte tecta tas ota United ended ots sien eae maet dofus MIPS32 M4K Process
347. ub l l I E M A WwW l i The following is a cycle by cycle analysis of Figure 2 3 1 The first 32x16 multiply operation Mult is fetched from the instruction cache and enters the I stage 28 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 2 3 MDU Pipeline High Performance MDU 2 An Add operation enters the I stage The Mult operation enters the E stage The integer and MDU pipelines share the I and E pipeline stages At the end of the E stage in cycle 2 the MDU pipeline starts processing the multiply operation Mult 3 In cycle 3 a 32x32 multiply operation Mult enters the I stage and is fetched from the instruction cache Since the Add operation has not yet reached the M stage by cycle 3 there is no activity in the M stage of the integer pipeline at this time 4 Incycle4 the Subtract instruction enters I stage The second multiply operation Mult enters the E stage And the Add operation enters M stage of the integer pipe Since the Mult multiply is a 32x16 operation only one clock is required for the Mypy stage hence the Mult operation passes to the Apy stage of the MDU pipeline 5 Incycle 5 the Subtract instruction enters E stage The Mult multiply enters the Myyny stage The Add operation enters the A stage of the integer pipeline The Mult operation completes and is written back in to the HI LO reg ister pair in the Wy
348. ubfields Major Revi 7 5 This number is increased on major revisions of the proces R Preset sion sor core Minor Revi 4 2 This number is increased on each incremental revision of R Preset sion the processor and reset on each new major revision Patch Level 1 0 If a patch is made to modify an older revision of the pro R Preset cessor this field will be incremented MIPS32 M4K Processor Core Software User s Manual Revision 02 03 103 Copyright 2002 2008 MIPS Technologies Inc All rights reserved CPO Registers of the M4K Core 5 2 12 EBase Register CPO Register 15 Select 1 The EBase register is a read write register containing the base address of the exception vectors used when Statuspry equals 0 and a read only CPU number value that may be used by software to distinguish different processors in a multi processor system The EBase register provides the ability for software to identify the specific processor within a multi processor sys tem and allows the exception vectors for each processor to be different especially in systems composed of heteroge neous processors Bits 31 12 of the EBase register are concatenated with zeros to form the base of the exception vectors when Statuspggy is 0 The exception vector base address comes from the fixed defaults see 4 5 Exception Vector Locations on page 67 when Statuspgy is 1 or for any EJTAG Debug exception The reset state of bits 31 12 of the EBase register initializ
349. ume IT The MIPS32 Instruction Set MD00086 for a more detailed description of these instructions Table 2 8 Hazard Instruction Listing Mnemonic Function EHB Clear execution hazard JALR HB Clear both execution and instruction hazards JR HB Clear both execution and instruction hazards SYNCI Synchronize caches after instruction stream write 2 11 2 1 Instruction Encoding The EHB instruction is encoded using a variant of the NOP SSNOP encoding This encoding was chosen for compat ibility with the Release 1 SSNOP instruction such that existing software may be modified to be compatible with both Release 1 and Release 2 implementations See the EHB instruction description for additional information The JALR HB and JR HB instructions are encoding using bit 10 of the hint field of the JALR and JR instructions These encodings were chosen for compatibility with existing MIPS implementations including many which pre date the MIPS32 architecture Because a pipeline flush clears hazards on most early implementations the JALR HB or JR HB instructions can be included in existing software for backward and forward compatibility See the JALR HB and JR HB instructions for additional information The SYNCI instruction is encoded using a new encoding of the REGIMM opcode This encoding was chosen because it causes a Reserved Instruction exception on all Release 1 implementations As such kernel software run ning on processor
350. umulate The non restoring algorithm used for divide operations will not work with negative numbers Adjustment before and after are thus required depending on the sign of the operands All divide operations complete in 33 to 35 clocks Table 2 3 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the second instruction to use the results of the first Table 2 3 M4K Core Instruction Latencies Area Efficient MDU Operand Signs of Instruction Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd Instruction Clocks any any MULT MULTU MADD MADDU 32 MSUB MSUBU or MFHI MFLO any any MADD MADDU MADD MADDU 34 MSUB MSUBU MSUB MSUBU or MFHI MFLO any any MUL Integer operation 32 any any DIVU MFHI MFLO 33 MIPS32 M4K Processor Core Software User s Manual Revision 02 03 31 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Pipeline of the M4K Core Table 2 3 M4K Core Instruction Latencies Area Efficient MDU Operand Signs of Instruction Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd Instruction Clocks pos pos MFHI MFLO 33 any neg MFHI MFLO 34 neg pos MFHI MFLO 35 any any MFHI MFLO Integer operation 2 any any MTHI MTLO MADD MADDU 1 MS
351. upports mem ory management address translation exception handling and other privileged operations Each CPO register has a unique number that identifies it this number is referred to as the register number For instance the PageMask regis ter is register number 5 For more information on the EJTAG registers refer to Chapter 8 EJTAG Debug Support in the M4K Core on page 127 After updating a CPO register there is a hazard period of zero or more instructions from the update instruction MTCO and until the effect of the update has taken place in the core Refer to Chapter 10 M4K Processor Core Instructions on page 207 for further details on CPO hazards The current chapter contains the following sections e Section 5 1 CPO Register Summary e Section 5 2 CPO Register Descriptions 5 1 CPO Register Summary Table 5 1 lists the CPO registers in numerical order The individual registers are described throughout this chapter Where more than one registers shares the same register number at different values of the sel field of the instruction their names are listed using a slash as separator Table 5 1 CPO Registers Register Number Register Name Function 0 6 Reserved Reserved in the M4K core HWREna Enables access via the RDHWR instruction to selected hardware registers in non privileged mode BadVAddr Reports the address for the most recent address related excep tion Reserved Rese
352. values may apply in the address compare and byte mask may apply in the value compare Complex breakpoints can be configured to match on more intricate scenarios Complex break features include pass counters to enable the breakpoint after N matching occurrences requiring matching of both data and instruction breaks on one instruction priming to enable after another breakpoint condition has been met and qualifying to enable instruction breaks when certain data conditions have been met An optional TAP enabling communication between an EJTAG probe and the CPU through a dedicated port may also be applied to the core This provides the possibility for debugging without debug code in the application and for download of application code to the system Another optional block is EJTAG Trace which enables real time tracing capability The trace information can be stored to either an on chip trace memory or to an off chip trace probe The trace of program flow is highly flexible and can include instruction program counter as well as data addresses and data values The trace features provides a powerful software debugging mechanism Refer to Chapter 8 EJTAG Debug Support in the M4K Core on page 127 for more information on the EJTAG features MIPS32 M4K Processor Core Software User s Manual Revision 02 03 21 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Introduction to the MIPS32 amp M4K Processor Core 22 1
353. ves TAP control signals to capture the register and shift data from TDI to TDO During a data register scan operation the TAP selects the out MIPS32 MAKTM Processor Core Software User s Manual Revision 02 03 Copyright 2002 2008 MIPS Technologies Inc All rights reserved 8 5 EJTAG TAP Registers put of the data register to drive the TDO pin The register is updated in the Update DR state with respect to the write bits This description applies in general to the following data registers e Bypass Register e Device Identification Register e Implementation Register EJTAG Control Register ECR e Processor Access Address Register e Processor Access Data Register e FastData Register 8 5 2 1 Bypass Register The Bypass register consists of a single scan register bit When selected the Bypass register provides a single bit scan path between TD and TDO The Bypass register allows abbreviating the scan path through devices that are not involved in the test The Bypass register is selected when the Instruction register is loaded with a pattern of all ones to satisfy the IEEE 1149 1 Bypass instruction requirement 8 5 2 2 Device Identification D Register The Device Identification register is defined by IEEE 1149 1 to identify the device s manufacturer part number revision and other device specific information Table 8 28 shows the bit assignments defined for the read only Device Identification Register and inputs to the c
354. virtual address A31 is cleared the 32 bit kuseg virtual address space is selected and covers the full g bytes 2 GBytes of the current user address space mapped to addresses 0x0000 0000 Ox7FFF FFFF When ERL 1 in the Status register the user address region becomes a 23 _byte unmapped and uncached address space While in this setting the kuseg virtual address maps directly to the same physical address 3 2 3 2 Kernel Mode Kernel Space 0 kseg0 In Kernel mode when the most significant three bits of the virtual address are 1005 32 bit ksegO virtual address space is selected it is the 27 byte 512 MByte kernel virtual space located at addresses 0x8000_0000 Ox9FFF_FFFF References to ksegO are unmapped the physical address selected is defined by subtracting 0x8000_0000 from the virtual address The KO field of the Config register controls cacheability 3 2 3 3 Kernel Mode Kernel Space 1 kseg1 In Kernel mode when the most significant three bits of the 32 bit virtual address are 1015 32 bit ksegl virtual address space is selected ksegl is the 22 byte 512 MByte kernel virtual space located at addresses 0xA000 0000 OxBFFF FFFF References to kseg1 are unmapped the physical address selected is defined by subtracting 0xA000 0000 from the virtual address 3 2 3 4 Kernel Mode Kernel Space 2 kseg2 In Kernel mode when UM 0 ERL 1 or EXL 1 in the Status register and DM 0 in the Debug register and the most
355. with other MIPS processors In practice both resets are handled identically with the exception of the setting of Statussg 6 1 1 Coprocessor 0 State Much of the hardware initialization occurs in Coprocessor 0 e Statusggy cleared to 1 on Reset SoftReset e StatuSrg cleared to 0 on Reset SoftReset e StatuSgp cleared to 0 on Reset set to 1 on SoftReset e StatUSym cleared to 0 on Reset SoftReset e SGt atusgg set to 1 on Reset SoftReset e Statusgp cleared to 0 on Reset SoftReset e Config fields related to static inputs set to input value by Reset SoftReset e Configyg set to 010 uncached on Reset SoftReset e Configxyy set to 010 uncached on Reset SoftReset e Configyos set to 010 uncached on Reset SoftReset MIPS32 M4K Processor Core Software User s Manual Revision 02 03 121 Copyright 2002 2008 MIPS Technologies Inc All rights reserved Hardware and Software Initialization of the M4K Core e DebugDM cleared to 0 on Reset SoftReset unless EJTAGBOOT option is used to boot into DebugMode see Chapter 8 EJTAG Debug Support in the M4K Core on page 127 for details e Debug sym cleared to 0 on Reset SoftReset e DebugijgysEp cleared to 0 on Reset SoftReset e DebugpgusEp cleared to 0 on Reset SoftReset e Debugygy cleared to 0 on Reset SoftReset e Debuggg cleared to 0 on Reset SoftReset 6 1 2 Bus State Machines All pending bus transactions are aborted and the state machines
356. with support for complex breaks 8 2 1 Features of Instruction Breakpoint 130 Instruction breaks occur on instruction fetch operations and the break is set on the virtual address on the bus between the CPU and the instruction cache Finally a mask can be applied to the virtual address to set breakpoints on a range of instructions Instruction breakpoints compare the virtual address of the executed instructions PC with the registers for each instruction breakpoint including masking of address When an instruction breakpoint matches a debug exception and or a trigger is generated An internal bit in the instruction breakpoint registers is set to indicate that the match occurred 8 2 2 Features of Data Breakpoint Data breakpoints occur on load store transactions Breakpoints are set on virtual address values similar to the Instruc tion breakpoint Data breakpoints can be set on a load a store or both Data breakpoints can also be set based on the value of the load store operation Finally masks can be applied to both the virtual address and the load store value Data breakpoints compare the transaction type TYPE which may be load or store the virtual address of the transac tion ADDR accessed bytes BYTELANE and data value DATA with the registers for each data breakpoint including masking or qualification on the transaction properties When a data breakpoint matches a debug exception and or a trigger is generated and an internal
357. wn if an even older About trigger is using the Trace Word counter e Triggers which produce TF6 trace information in the trace flow Trace bit is set Regardless of priority the TCBTR Gxzp bit is set when the trigger fires This is so even if a trigger action is sup pressed by a higher priority trigger action If the trigger is set to only fire once the TCBTRIGXpo bit is set then the suppressed trigger action will not happen until after TCBTR IGXzp is written 0 If a Trigger action is suppressed by a higher priority trigger then the read value when the T CBTHIGxXq bit is set for the TCBTRIGXq ac field will be 0 for suppressed TF6 trace information actions The read value in the TCB TRIGXqype field for suppressed Start End About triggers will be 11 This indication of a suppressed action is sticky If any of the two actions Trace and Type are ever suppressed for a multi fire trigger the TCBTRIGXpo bit is Zero then the read values in Trace and or Type are set to indicate any suppressed action About Trigger The About triggers delayed de assertion of the TCBCONTROLBgy bit is always executed regardless of priority from another Start trigger at the time of the TCBCONTROLBgw change This means that if a simultaneous About trigger action on the TCBCONTROLBgy bit n 2 Trace Words after the trigger and a Start trigger hit the same cycle then the About trigger wins regardless of which trigger number it is The oldest trigger takes precedenc
358. zation including aborting state machines establishing critical state and generally placing the processor in a state in which it can execute instructions from uncached unmapped address space On a Reset Soft Reset exception the state of the processor is not defined with the following exceptions The Config register is initialized with its boot state The RP BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state e The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruc tion in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that this value may or may not be predictable PC is loaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 Operation Config ConfigurationState StatuSpp amp 0 StatuSpry amp 1 Statusgs 0 Statusgg lt 0 1 depending on Reset or SoftReset Statusyyr 0 StatuSga amp 1 if InstructionInBranchDelaySlot then ErrorEPC lt PC 4 else ErrorEPC PC endif PC OxBFCO 0000 4 8 2 Debug Single Step Exception A debug single step exception occurs after the CPU has executed one two instructions in non debug mode when returning to non debug mode after debug mode One instruction is allowed to execute when returning to a non jump branch instruction otherwise

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MIPS32® M4K™ Processor Core Software User`s Manual