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MC68PM302 Integrated Multiprotocol Processor with PCMCIA

1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 R X w l ERR 0 OFFSET 2 DATALENGTH OFFSET 4 TXDATABUFFER POINTER OFFSET 6 R Ready 0 The data buffer associated with this BD is not currently ready for transmission The user is free to manipulate this BD or its associated data buffer The CP clears this bit after the buffer has been transmitted or after an error condition is encountered 1 The data buffer which has been prepared for transmission by the user has not been transmitted or is currently being transmitted No fields of this BD may be writ ten by the user once this bit is set X External Buffer 0 The buffer associated with this BD is in internal dual port RAM 1 The buffer associated with this BD is in external memory W Wrap Final BD in Table 0 This is not the last buffer descriptor in the Tx BD table 1 This is the last buffer descriptor in the Tx BD table After this buffer has been used the CP will transmit data from the first BD in the table allowing the user to use few er than eight BDs to conserve internal RAM NOTE The user is required to set the wrap bit in one of the first eight BDs otherwise erratic behavior may occur I Interrupt 0 No interrupt is generated after this buffer has been serviced 1 The TX bit in the 16550 event register will be set when this buffer has been ser viced by the CP which can cause an i
2. FIFO Interrupt Mode fae od P Interrupt Set and Reset Functions Identification Reg Only Priority Interrupt Reset Bit 3 Bit 2 Bit 1 Bit 0 Level Interrupt Type Interrupt Source Control 0 0 0 1 None None Rx line Overrun or parity error or Reading the line status 0 1 1 0 Highest spats ie error or break in register Rx Dat ilabl tri E rine tino x Data available or trig register or the 0 1 0 0 Second Rx data available qe evel reached g drops below the trigger evel Ne ieee have re Character een removed or input to the Rx FIFO during the Reading the receiver i 1 0 0 Second timeout last 4 character times and buffer registar indication there was at least 1 char acter in it during this time Tx holdi j tenure mein aer x holding regis if source of interrupt or 0 0 1 0 Third ter empty gls Tx Holding register emptylwriting into the Ra ter holding register CTS DSR ring indica Reading the MODEM 0 0 0 0 Fourth MODEM status ign or GD g status register 4 4 4 1 5 Interrupt Enable Register IER PC Access Only 7 6 5 4 3 2 1 0 0 0 0 0 EDSSI ELSI ETBEI ERBFI RESET 0 O 0 0 0 0 0 0 Read Write PC ERBFl Enable Received Data Available Interrupt This bit enables the received data available interrupt to the PC and timeout interrupts in the FIFO mode when set to one ETBEI Enable Transmitter Holding Register Empty Interrupt This bit enables the transmitter holding register empty inte
3. IWUCR OF7 7 6 5 4 3 2 1 0 0 PIE PB10E PB9Ev 0 Pien PBI0En PB9En coe 0 0 0 0 0 0 0 Read Write PB9Ev PB9 Event This bit will be set to one when there is a high to low transition on the PB9 pin When PB9En is set and PB9Ev is set the IMP will wake up from the selected power down state and a PB9 Interrupt will be generated The IMP cannot enter the power down mode if MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc PB9Ev and PB9En are both set to one PB9Ev is cleared by writing a one writing a zero has no effect In modem applications RI should be connected to the PB9 pin PB10Ev PB10 Event This bit will be set to one when there is a high to low transition on the PB10 pin When PB10En is set and PB10Ev is set the IMP will wake up from the selected power down state and the PB10 Interrupt will be generated The IMP cannot enter the power down mode when PB10Ev and PB10En are both set to one PB10Ev is cleared by writing a one writing a zero has no effect In modem applications the DTE TxD line may be connected to the PB10 pin PITEv PIT Event This bit will be set to one when there is a time out on the periodic interrupt timer PIT When PITEn bit is set and a time out occurs PITEv is set the IMP will wake up from the selected power down and a PIT Interrupt will be generated The IMP cannot ent
4. dINI 0 VIOWNOd Wo 4 40 9 LOHI eus9 U YSOO u 4q UMGAMd oO J7190 dil 5 E L_ MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller 5 1 10 4 The Ready Busy Signal Rdy Bsy The ready busy signal can be passed to the host through the Rdy Bsy IREQ in I O mode pin in memory only mode and the Rdy Bsy bit in the pin replacement register PRR in I O mode The RDY BSY pin can be controlled by the 68000 by writing to the Rdy Bsy bit in the PRR The state of the Rdy Bsy pin can be monitored in the PRR even though the PCMCIA interface is configured as a memory only interface The RdyBsy bit is also controlled during the transitions to and from the three low power STOP modes See 5 1 10 2 Power Down and Wake Up Using the PwrDwn Bit for more de tails 5 2 PCMCIA PINS 5 2 1 PCMCIA Pins Supported by the MC68PM302 The pin descriptions for the MC68PM302 PCMCIA pins are given in Section 6 Signal De scription The MC68PM302 will read the PC_EN pin at IMP reset and if this pin is strapped to Vcc it will configure the pins with PCMCIA functionality as PCMCIA pins If it is strapped to ground the pins will revert to their non PCMCIA functions Most PCMCIA pins have internal pullup or pulldown resistors see 5 2 3 Pullup Control Reg ister PUCR NOTE The PCMCIA pins are denoted in the signal description Section 2 as PC_S
5. cceceeeeeeeeeeeeeeeeteeeeeeeeeeeees 2 6 2 4 2 1 Default System Clock Generation cceeeeeeeeeeeeeeneeeeeeeeeeeeneeeeeeeeeeees 2 7 2 4 3 IMP System Clock Generation eccecccceeeeeeeeeeeeeeeeeeeeseaeeeeeeeeeneeaaees 2 8 2 4 3 1 System Clock COntaUrana Ms vessc ivocdey te Geeectaedensrstedecttasinectidivvexedetecdextes 2 8 2 4 3 2 On Chip Oscillatoria taster aae te asset aN 2 8 2 4 3 3 Phase Locked Loop PLL cccseeeeeeeseeceeeeeeeeeeeeeeeeeeeeesnsaeeeeeeeeeeneeas 2 8 2 4 3 4 Frequency Multiplication 2i4 sects al ahh cee heed ate lu at ale 2 8 2 4 3 4 1 Low Power PLL Clock Dividel ccccceeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeeeeeeeee 2 9 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR seeeeeeeeeeeeeteees 2 10 2 4 3 5 IMP Internal Clock Signals cscs ecciececvchereis tet seires ecueneuee cwweteeuierineeeeadeavetend 2 11 2 4 3 5 1 IMP System GGIOCK sy a reaa aea alaan puacaxgesteessacaatoeel eter qeereesseetess 2 11 2 4 3 5 2 BIG Glockiin aa aE G 2 11 2 4 3 5 3 AAO E A E AE E N AAA EN 2 12 2 4 3 6 W EA E vce E T A E E E E 2 12 2 4 3 6 1 LESA AN CE E EE E E eedes 2 12 2 4 3 6 2 GNDS N ser rs cele a ws oh eee enn Senet a dace ecb pdose 2 12 2 4 3 6 3 IEG ood E es en cea havin E re een tenets 2 12 2 4 3 6 4 MODGEK maere e a a a a ven aa 2 12 2 4 4 IMP Power Managemen cccceeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeneeeeeeeeeeesnaaees 2 12 2 4 4 1 IMP Low Power Modes
6. D15 D0 INPUT w E lt PC_D15 PC_DO OUTPUT NOTES 1 PC_A11 is input if ABUF PC_A11 bit in PCMR 0 2 Asynchronous input if set up is met AS is asserted as shown 3 If ABUF A11 1 in PCMR A23 A12 are input to chip Figure 7 25 PCMCIA to 68K Fast Burst Read MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics CLKO OUTPUT PC_A11 PC_A0 INP T NOTE 1 PC CE2 PC_CE1 INPUT A23 A12 OUTPUT A11 A0 OUTPUT NOTE 3 a Dra 65 ee AS OUTPUT LDS UDS OUTPUT WEH WEL OUTPUT D15 D0 OUTPUT PC_D15 PC_DO INPUT NOTES 1 PC_A11 is input if ABUF PC_A11 bit in PCMR 0 2 Asynchronous input if set up is met AS is asserted as shown 3 If ABUF A11 1 in PCMR A23 A12 are input to chip Figure 7 26 PCMCIA to 68K Fast Burst Write MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc PC_A11 PC_A0 REG_ INPUT PC_CE2 PC_CEl INPUT PC_OE INPUT WAIT OUTPUT PC_D15 PC_DO OUTPUT Figure 7 27 PCMCIA Register Read PC_Al1 PC_AO REG_ INPUT PC_CE2 PC_CE1 INPUT PC_WE INPUT WAIT PC_D15 PC_DO INPUT Figure 7 28 PCMCIA Register Write MC68PM302 REFERENC
7. cccceeeeeeseeeeeeeeeeeeeeeeeeeeeeneesenaeeeeees 4 27 4 4 4 1 2 Line Status Register LSR Read Only cccececeeeeeeeeeeeeeeeeeeeeeeees 4 28 4 4 4 1 3 FIFO Control Register FCR Write Only ceeeeeeeeeeeeeeeeeseeeeeees 4 29 4 4 4 1 4 Interrupt Identification Register IIR Read Only eeeeeeeeeee 4 30 4 4 4 1 5 Interrupt Enable Register IER ccccsccceeeeeessseeeeeeeeeeeneeeeeeeeeeeeeee 4 31 4 4 4 1 6 MODEM Control Register MCR cccccccseceeeeeeeeeeseeeneeeeeeeeeeeeenneeeees 4 31 4 4 4 1 7 MODEM Status Register MSR ccccecceeeeeeeeeeeeeeeeeeeeeeeeeeeeneneaeeeees 4 33 4 4 4 1 8 Divisor Latch LS DEL wa vrsetctait ta ueads ail cia etna etaed ced uen i Ac caed 4 34 4 4 4 1 9 Divisor Latch LM DEM cin ies ea aoe ae oe capes 4 34 4 4 4 1 10 Receive Buffer Register RBR ccccsccceeeeeeeeeeeeeeeeeeeeenaeeeeeeeeeees 4 34 4 4 4 1 11 Transmit Holding Register THR cceeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeeees 4 35 4 4 4 1 12 Scratchpad Register SCR cccccesssseeccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 4 35 4 4 5 68000 Programming Model ix s ccivs ceed eceniins eects 4 35 4 4 5 1 16550 Memory Map 5 5 cevscccntee taecgace tl eceeetansccennteveresiederosepeitedbetteeeceaentes 4 35 4 4 5 2 16550 Emulation Mode Register EMR cccccceceeeeeeeeeeseeeeeeeeeeeeee 4 36 4 4 5 3 16550 Command Sel cinch eae wed sbi ctedhecig niae ev
8. 16 67 MHz 20 MHzat 25 MHzat Num Characteristic Symbol at 5 0 V 30V 5 0V Unit Min Max Min Max Min Max 100 R W Valid to DS Low trwvps_ 0 0 0 ns 101 DS Low to Data In Valid tosLoiv 30 25 20 ns 102 DTACK Low to Data In Hold Time DKLDH 0 0 0 ns 103 AS Valid to DS Low tasvos 0 0 0 ns 104 DTACK Low to AS DS High tpKLDSH 0 0 lt 0 ns 105 DS High to DTACK High tosoku 45 40 30 ns 106 DS Inactive to AS Inactive tDSIASI 0 0 0 ns 107 DS High to R W High tpSHRWH 0 0 0 ns 108 DS High to Data High Impedance tpsHpz 45 40 30 ns 108A DS High to Data Out Hold Time see Note tpsHpH 0 0 0 ns 109A Data Out Valid to DTACK Low tpovpkL 15 15 10 ns NOTE If AS is negated before DS the data bus could be three stated spec 126 before DS is negated MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics so gt lt S7 S6 gt S5 Sw Sw Sw Sw Sw Sw S3 S4 gt 29 E S2 gt gt SI CLKO OUTPUT UDS LDS INPUT RAV INPUT DTACK OUTPUT D15 DO OUTPUT Figure 7 8 External
9. 50 42 33 ns 8 seek High to Address FC Invalid Mini Tae 0 0 0 ns 9 Clock High to AS DS Asserted see Note 1 tcHsL 3 30 3 25 3 20 ns Address FC Valid to AS DS Asserted ma So 11 Read AS Asserted Write see Note 2 tarcvsL 15 12 10 ns 12 Clock Low to AS DS Negated see Note 1 tcLsH 30 235 20 ns 13 AS DS Negated to Address FC Invalid see fete i 12 10 os Note 2 14 AS and DS Read Width Asserted see tsL 120 10 s Ins Note 2 14A DS Width Asserted Write see Note 2 tpsL 60 50 40 ns 15 AS DS Width Negated see Note 2 tsH 60 50 40 ns 16 Clock High to Control Bus High Impedance tcHcz 50 42 33 ns 17 AS DS Negated to R W Invalid see Note 2 tsHRH 15 12 10 ns 18 Clock High to R W High see Note 1 CHRH 30 25 20 ns 20 Clock High to RW Low see Note 1 tCHRL gt 30 25 20 ns 20A AS Asserted to RW Low Write see Notes tasky 101 Fe has 7 nS 2 and 6 21 Address FC Valid to R W Low Write see teenie 45 12 10 ns Note 2 22 aw Low to DS Asserted Write see Note lute 30 NP 25 20 ns 23 Clock Low to Data Out Valid teLDo 30 25 20 ns AS DS Negated to Data Out Invalid Write _ _ C 25 SENG taper 15 12 10 ns 26 Data Out Valid to DS Asserted Write see facet 15 12 10 ats ns Note 2 Data In Valid to Cl
10. cards This pin is used as RDY BSY while an I O capable card is configured for the mem ory only interface In Non PCMCIA Mode this pin functions as R W see section 6 1 6 Bus Control Pins PC_REG UDS AO PCMCIA Attribute Memory Select or Upper Data Strobe Address In PCMCIA Mode this input is kept inactive high for all common memory accesses When this signal is active access is limited to attribute memory OE or WE active and to the I O space IORD or IOWR active In Non PCMCIA Mode this pin functions as UDS A0 see section 6 1 6 Bus Control Pins PC_CE1 LDS PCMCIA Card Enable or Lower Data Strobe The PC_CE2 pin interfaces to the PCMCIA Connector and is asserted by the PC Host when it selects the Card In Non PCMCIA Mode this pin functions as LDS see section 6 1 6 Bus Control Pins PC_A5 FRZ PCMCIA Address or Freeze Activity The PC_AS input is driven by the PCMCIA card interface See Section 5 PCMCIA Con troller The FRZ pin is used to freeze the activity of selected peripherals This is useful for sys tems debugging purposes FRZ should be continuously negated during total system reset See section 3 6 6 for more information about this function PC_A4 AVEC PCMCIA Address or Autovector The PC_A 4 input is driven by the PCMCIA card interface See Section 5 PCMCIA Con troller AVEC when asserted during an interrupt acknowledge cycle indicates that the M68000 core should use automatic vectoring f
11. 7 4 POWER DISSIPATION SEE NOTE Characteristic Power Dissipation Symbol ae Unit Typ Max Normal Mode at 20 MHz PD 70 TBD mA Normal Mode at 16 MHz Ppi 60 TBD mA Low Power Standby Mode Ppsg 7 TBD mA Low Power Doze Mode Pppz 1 500 TBD uA Low Power Stop Mode PpsP 1 100 TBD uA Note These values are preliminary estimates Test values are TBD MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 4 1 Layout Practices Each Vcc pin on the MC68PM302 should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vcc power supply should be bypassed to ground using at least four 0 1 uF by pass capacitors located as close as possible to the four sides of the package The capacitor leads and associated printed cir cuit traces connecting to chip Vcc and GND should be kept to less than 1 2 per capacitor lead A four layer board is recommended employing two inner layers as Vcc and GND planes All output pins on the MC68PM302 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and re flections caused by these fast output switching times Maximum PC trace lengths on the or der of 6 are
12. CD1 SYNC INPUT Freescale Semiconductor Inc clectrical Characteristics 7 6 19 AC Electrical Specifications PCMCIA Interface Characteristic PC Address Setup before PC_OE or PC_WE Low PC_CE Setup before PC_OE or PC_WE Low PC_CE Hold from PC_WE or PC_OE High See Note 1 PC_Address Hold from PC_OE or PC_WE High See Note 1 PC_WE or PC_OE Low to AS Low only for FAST Burst Mode Asynchronous Input Setup Now 2 PC_OE or PC_WE Width only for FAST Burst Mode See ote AS LDS UDS Hold from PC_OE or PC_WE High only for FAST Burst Mode PC_OE High to OE High only for FAST Burst Mods or PC_WE High to WEH WEL High only for FAST Burst Mode 68k Data Bus Valid to PC_Data Bus Valid See Note 3 PC_OE or PC_WE High to 68k Address Bus Invalid only for FAST Burst Mode PC_Address Hold from PC_OE or PC_WE High See Note 4 PC_CE Hold from PC_OE or PC_WE High See Note 4 Clock High to PC_ABUF Low Clock High to PC_ABUF High PC_OE or PC_WE Low to 68k Address Bus Valid only for FAST Burst Mode AS Low to 68k Data Out only for FAST Burst Mode PC_Data Valid to 68k Data Valid WEL WEH High to 68k Data Invalid only for FAST Burst Mode PC_Data Setup before PC_WE High PC_Data Bus Hold Time from PC_OE High PC_OE or PC_WE or PC_IORD or PC_IOWR Low to PC_WATT Low PC_OE or PC_WE or PC_IORD or PC_IOWR High from PC_WAIT High See Note 5 Clock High to PC_WAIT High PC_OE Low to PC_ D
13. Clock High to IAC High Clock Low to IAC Low tCHIAH tCLIAL Clock Low to DTACK High Clock High to Data Out Valid AS High to Data Out Hold Time tCLDTH tcHDoVv taSHDOH CLKO OUTPUT A23 Al OUTPUT AS OUTPUT IAC OUTPUT OUTPUT RW OUTPUT D15 D0 OUTPUT DTACK OUTPUT Figure 7 13 Internal Master Internal Read Cycle Timing Diagram 7 6 9 IMP AC Electrical Specifications Chip Select Timing Internal Master see Figure 7 14 NOTE 1 This specification is valid only when the ADCE or WPVE bits in the SCR are set 2 For loading capacitance less than or equal to 50 pF subtract 4 ns from the maximum value given 3 Since AS and CS are asserted negated on the same CLKO edges no AS to CS relative timings can be MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 16 67MHzat 20 MHz 25 MHz Num Characteristic Symbol 5 0 V at 5 0 V at5 0V Unit Min Max Min Max Min Max Clock High to CS IACK OE WEL WEH 150 Pow aoe Note 2 tcHcsiakL 0 40 0 35 0 27 ns Clock Low to CS TACK OE WEL WEH 151 High see Note 2 CLCSIAKH 0 40 0 35 0 27 ns 152 CS Width Negated tcsH 60 50 40 ns 153 Clock High to DTACK Low 0 Wait
14. DCD Data Carrier Detect This bit emulates the complement of the DCD input The 68000 core writes this bit If bit 4 loop of the MCR is set to 1 this bit is equivalent to OUT 2 in the MCR 4 4 4 1 8 Divisor Latch LS DLL This register contains the low byte of the baud rate generator divisor latch When the PC writes this register the DLL interrupt if enabled will be generated to the 68000 core See 4 4 5 12 16550 Event Register for more details The 68000 core can read this register value and program SCC2 BRG according to this value NOTE The 16550 requires a baud rate multiplied by one clock instead of the baud rate multiplied by sixteen clock used in the standard 68302 SCC in UART mode i e to generate a 16550 9600 baud clock at 16 67MHZ the clock divider bits in the SCON register should be programmed to 1735 instead of 108 The 4 bit divid ers for the TX and RX FIFOs should also be programmed to match the number of bits per character being transferred to slow down the PC interrupt rate to a level to emulate a serialized UART 4 4 4 1 9 Divisor Latch LM DLM This register contains the high byte of the baud rate generator divisor latch When the PC writes this register the DLM interrupt if enabled will be generated to the 68000 core See 4 4 5 12 16550 Event Register for more details The 68000 core can read the register value at program SCC2 BRG 4 4 4 1 10 Receive Buffer Register RBR When the 68000 core has data
15. c cee 7 6 2 AC Electrical Characteristics IMP Phased Lock Loop PLL CATACISNIS CS tesa eo och eee aaar env aa ens ale e Na a aeaa 7 6 3 IMP DC Electrical Characteristics NMSI1 in IDL Mode 7 6 4 AC Electrical Specifications IMP Bus Master Cycles 7 6 5 IMP AC Electrical Specifications DMA ccceceeeeeeeeeeeeeeeeeees 7 6 6 IMP AC Electrical Specifications External Master Internal Asynchronous Read Write Cycles ccseeeeeeeeeeeeeteeeees 7 6 7 IMP AC Electrical Specifications External Master Internal Synchronous Read Write Cycles cceceeeeeeeeeeeeteeeees 7 6 8 IMP AC Electrical Specifications Internal Master Internal Read Write Cycles ccccccceeeeeseeseeeeeeeeeeeeaeeeeeeeeeeneaaaees 7 6 9 IMP AC Electrical Specifications Chip Select Timing Int rnal Master carne criterias a tact cies acu es 7 6 10 IMP AC Electrical Specifications Chip Select Timing External WASTOM fos ctl settp eves tees cued a dca vente AAA EEO EAA EEEE 7 6 11 IMP AC Electrical Specifications Parallel I O cceeeeeeeeeeees 7 6 12 IMP AC Electrical Specifications Interrupts ccceeeeeeeeeees 7 6 13 IMP AC Electrical SpecificationS Timers eeeeseeeeeeeeeeeeeeeeeees 7 6 14 IMP AC Electrical Specifications Serial Communications Port 7 6 15 IMP AC Electrical Specifications IDL Timing ccceeeeee 7 6 16 IMP AC Electrical Specificat
16. 5 3 10 2 Card Configuration and Status Register CCSR CCSR PCMCIA Address A25 1 2 68000 Address BAR 871 7 6 5 4 3 2 1 0 Changed SigChg lOis8 RingEn Audio PwrDwn Intr Res 0 Read Write The 68000 core will receive an interrupt when this register is written by the PC See 5 3 5 PCMCIA Access Wake Up Event Register PCAWER Changed This bit indicates that one or more of the pin replacement register bits CBVD1 CBVD2 CRdyBSY CWProt is set to one or when one or more of the I O event indication register event bits are set and its corresponding enable bit is also set When this bit is set the STSCHG BVD1 pin is held low if the SigChg bit is 1 and the card is configured as I O SigChg 1 When the card is configured for I O interface the changed bit controls the STSCHG signal and is called the changed status signal 0 The BVD1 STSCHG line will be held high while the card is configured as I O RingEn 0 The state of the STSCHG is controlled by the SigChg bit as described above 1 The STSCHG signal is used to indicate the state of the ring indicate signal STSCHG is asserted low whenever ringing is present on the RI PB9 pin STSCHG is negated high when there is no ringing lOis8 1 The host can provide I O cycles only with 8 bit DO D7 data path Accesses to 16 bit registers will occur as two byte accesses 0 The host can provide I O cycles with 16 bit data path Audio This bi
17. Base Address Registers Are Programmable by either the PC or 68000 Core Base Register Can Be Used as Transmit and Receive Buffer Pointers for Ultra Fast Communication Data Transfers Supports Cycle Steal Transfers and Burst Transfers Arbitration Scheme for Common Memory Accesses Supports Full 64 Megabytes of Attribute Memory Space Addressing Card Information Structure Mapped into 68000 Space with Special Base Address Register UART 16550 Registers and FIFO Mapped into I O Space for x86 PC Compatibility 1 O Pin Definitions Supported Supports Pull Up Pull Down Resistors on PCMCIA Pins PUCR Register Supports Two Ring Indication Handling Methods l O Event Indication Register RI Enable and Event Bits Direct Connection to STSCHG Signal Supports PC power management of the card Internal Register and Chip Select Lockout of PCMCIA Accesses Supports PCMCIA DMA Cycles According to DMA Change Pages Document 0035 re lease 004 ExCA Compatible 5 1 PCMCIA CONTROLLER FUNCTIONAL OVERVIEW The PCMCIA controller fully supports PCMCIA standard 2 1 The block diagram of the MC68PM302 PCMCIA controller is shown in Figure 5 2 The PCMCIA controller interfaces between the PCMCIA bus and both the 68000 bus and the UART 16550 registers Depend ing on the memory access mode the controller will handle the transfer of data from or to the appropriate source or destination Attribute memory accesses are supported for both the MC
18. Divisor Latch This bit is set when the PC writes to the 16550 divisor latch either DLL or DLM emulation registers Loop Loopback Mode This bit is set when the PC changes the loop signal level by writing to the 16550 MODEM control emulation register The status register may be read to determine loop current sta tus Out2 Out2 Status Changed This bit is set when the PC changes the Out2 signal level by writing to the 16550 MODEM control emulation register The status register may be read to determine Out2 current sta tus Outi Out1 Status Changed This bit is set when the PC changes the Out1 signal level by writing to the 16550 MODEM control emulation register The status register may be read to determine Out1 current sta tus RTS RTS Status Changed This bit is set when the PC changes the RTS signal level by writing to the 16550 MODEM control emulation register The status register may be read to determine RTS current sta tus DTR DTR Status Changed This bit is set when the PC changes the DTR signal level by writing to the 16550 MODEM control emulation register The status register may be read to determine DTR current sta tus 4 4 5 13 16550 MASK REGISTER The 16550 mask register is a 16 bit read write register with the same bit formats as the 16550 event register If a bit in the 16550 mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interr
19. MRBLR ord Maximum Rx Buffer Length SCC Base 84 Word Rx Internal State SCC Base 86 Byte Reserved SCC Base 87 RBD Byte Rx Internal Buffer Number SCC Base 88 2 Words Rx Internal Data Pointer SCC Base 8C Word Rx Internal Byte Count SCC Base 8E Word Rx Temp SCC Base 90 Word Tx Internal State SCC Base 92 Byte Reserved SCC Base 93 TBD Byte Tx Internal Buffer Number SCC Base 94 2 Words Tx Internal Data Pointer SCC Base 98 Word Tx Internal Byte Count SCC Base 9A Word Tx Temp SCC Base 9C First Word of Protocol Specific Area SCC Base BF Last Word of Protocol Specific Area Should be Initialized by the user M68000 core Modified by the CP following a CP or system reset 4 3 7 Interrupt Mechanism The interrupt mechanism for each SCC is the same as the MC68302 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 3 8 UART Controller The functionality of the UART controller has not changed The new Autobaud feature is dis cussed in 4 3 9 Autobaud Controller New For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 8 1 UART MEMORY MAP When configured to operate in UART mode the IMP over lays the structure see Table 4 2 onto the protocol specific area of that SCC s parameter RAM Refer to 2 3 System Con
20. Section 2 Configuration Clocking Low Power Modes and Internal Memory Map Section 3 System Integration Block SIB Section 4 Communications Processor CP Section 5 PCMCIA Controller Section 6 Signal Description Section 7 Electrical Characteristics Section 8 Mechanical Data And Ordering Information ELECTRONIC SUPPORT The Technical Support BBS known as AESOP Application Engineering Support Through On Line Productivity can be reach by modem or the internet AESOP provides commonly asked application questons latest device errata device specs software code and many other useful support functions Modem Call 1 800 843 3451 outside US or Canada 512 891 3650 on a modem that runs at 14 400 bps or slower Set your software to N 8 1 F emulating a vt100 Internet This access is provided by telneting to pirs aus sps mot com 129 38 233 1 or through the World Wide Web at http pirs aus sps mot com Sales Offices For questions or comments pertaining to technical information questions and applications please contact one of the following sales offices nearest you MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ALABAMA Huntsville ARIZONA Tempe CALIFORNIA Agoura Hills CALIFORNIA Wee Angeles CALIFORNIA Irvine CALIFORNIA Roseville CALIFORNIA San Diego CALIFORNIA Sunnyvale Cononabo Golorado Springs COLORADO D CONNECTICUT Wallin
21. Each one of these inputs except for level 7 can be programmed to be either level sensitive or edge sensitive The M68000 always treats a level 7 interrupt as edge sensitive NOTE These pins function as bus arbitration pins only in Slave Mode and PCMCIA DISCPU 1 and PC_EN 1 Table 6 13 specifies in what mode each function is available MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description IPL1 IRQ6 BG Bus Grant The Bus Grant pin is an input to the IDMA SDMA and PCMCIA Controller when the inter nal M68000 core is disabled During total system reset BG BR For Interrupt functionality see the description under Bus Request IPL2 IRQ7BGACK Bus Grant Acknowledge BGACK bidirectional signal indicates that some Master has taken ownership of the bus This signal is an input when an external device owns the bus This signal is an output when the IDMA SDMA or PCMCIA Controller has become the master of the bus If the SDMA steals a cycle from the IDMA the BGACK pin will remain asserted continuously NOTE BGACK should always be used in the external bus arbitration process See 3 8 3 Bus Arbitration Logic for more details For Interrupt functionality see description under Bus Request 6 1 8 Chip Select Pins The chip select pins are shown in Figure 6 8 a CS0 IOUT2 CS3 CS1 Figure 6 8 Chip Select Pins CS0 IOUT2 Chip
22. Function Code The function code field should contain the function code of the common memory address on the 68000 bus 5 3 10 Card Configuration Registers 5 3 10 1 Configuration Option Register COR COR PCMCIA Address A25 1 0 68000 Address BAR 870 7 6 5 4 3 2 1 0 SRESET LevIREQ Configuration Index 0 0 0 0 0 0 0 0 Read Write The 68000 core will receive an interrupt when this register is written by the PC See 5 3 5 PCMCIA Access Wake Up Event Register PCAWER SRESET Reset Card When this bit is set to one the 68PM302 enters a hardware reset state The RESET pin is asserted and the CPU is reset The 68PM302 stays in the reset state until the PCMCIA resets the bit This bit is also cleared by asserting RESET and HALT simultaneously MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc LevIREQ Level Mode Interrupts The MC68356 PCMCIA controller supports the interrupt level mode only Regardless of this bit value NOTE The pulse mode may be supported by the 68000 software Configuration Index This field is written with the index number of the entry in the card s configuration table which corresponds to the configuration which the system chooses for the card When the configuration index is 0 the card s I O is disabled and will not respond to any I O cycles and will use the memory only interface
23. Go to www freescale com Freescale Semiconductor Gem Integration Block SIB At the end of the Boot from SCC function the following registers contain values that differ from their default reset values ICR 0xc000 BAR 0x0000 SCON1 depends on mode The SCM1 register is reprogrammed to its reset value of 0x0 NOTE During the boot from SCC procedure no external master should acquire the bus 3 4 DMA CONTROL The IMP includes seven on chip DMA channels six serial DMA SDMA channels for the three serial communications controllers SCCs and one IDMA 3 4 1 68PM302 Differences The DREQ DACK and DONE pins have been removed unless the PCMCIA interface is dis abled The user should not program the IDMA should for external request generation If the PCMCIA interface is disabled then the DREQ pin is available on PA13 If the PCMCIA Interface is enabled then the DREQ pin is available on PB8 see 6 2 Summary of Pin Mul tiplexing for more details on pin muxing The external bus exceptions BERR and retry have been removed unless the PCMCIA interface is disabled Only HALT or an internal BERR generated by the hardware watchdog timer or CS logic is supported The rest of the functionality remains the same as for the MC68302 For details on the bus operation please refer to the MC68302 User s Manual 3 4 1 1 Channel Mode Register CMR The CMR a 16 bit register is reset to 0000 15 14 13 12 11 10 9 8 7 6
24. Manual 4 3 SERIAL COMMUNICATION CONTROLLERS SCCS The IMP contains three independent SCCs each of which can implement different proto cols This configuration provides the user with options for controlling up to three independent full duplex lines implementing bridges or gateway functions or multiplexing up to three SCCs onto the same physical layer interface to implement a 2B D ISDN basic rate channel or three channels of a PCM highway Each protocol type implementation uses identical buffer structures to simplify programming 4 3 1 SCC Configuration Register SCON Each SCC controller has a configuration register that controls its operation and selects its clock source and baud rate This register has not been changed from the MC68302 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 woms EXTC TCS RCS CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CDO DIV4 4 3 1 1 DIVIDE BY 2 INPUT BLOCKS NEW FEATURE The SCC Baud Rate Generators have 2 divide by 2 blocks added to them With the divide by 2 blocks enabled the VCO Out put from the PLL and the TIN1 input clock can be divided by 2 before they are used by the BRG to generate the serial clocks The divide by two blocks can be enabled by setting the BCD bit in the IOMCR register if the BRG clock source is derived from the IMP system clock or by setting the BRGDIV bit in the DISC register if the BRG clock source is derived
25. Register SCC1 Event Register Reserved SCC1 Mask Register Reserved SCC1 Status Register SCC2 Configuration Register SCC2 Mode Register SCC2 Data Sync Register SCC2 16550 Emulation Event Registe Reserved SCC2 16550 Emulation Mask Register Reserved AN Emulation Status Regis er SCC3 Configuration Register Base 8A4 SCC3 Mode Register Base 8A6 SCC3 Data Sync Register Base 8A8 SCC3 Event Register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freasgate senicenducter wid amp G lt and Internal Memory Map Table 2 6 Internal Registers Map Address Description Reset Value Reserved SCC3 Mask Register Base 8AD RES Base 8AE RES SPMODE SIMASK SCP SMC Mode and Clock Control Register Serial Interface Mask Register SIMODE Serial Interface Mode Register Reserved PCMR PCMCIA PCMCIA Mode Register PCRWER PCMCIA PCMCIA Configuration Registers Write 00 Event Register PCAWER PCMCIA E McA Access Wake up Event Reg 00 ister PCRWMR PCMCIA PCMCIA Configuration Registers Write 00 Mask Register PCAWMR PCMCIA rowel Access Wake up Mask Regis er PCHER PCMCIA PCMCIA Host PC Event Register CISBAR CMBAR1 PCMCIA PCMCIA CIS Base Address Register Common Me
26. Since a length for this external buffer is not given the user must provide enough space in memory for characters to be assem bled and written until the autobaud process is to avoid overwrit ing other data in memory This location is not used as the CHARACTER7 value in the control character table until the channel operates in normal UART mode After reception begins in normal UART mode i e the a or A is found this entry is available again as a control character table entry The TxBD entry is used as the transmit character descriptor for smart echo or software transmit This location is not used as the CHARACTER8 value in the control character table until the channel operates in normal UART mode After reception begins in normal UART mode i e the a or A is found this entry is available again as a control character table entry 4 3 9 4 AUTOBAUD PROGRAMMING MODEL The following sections describe the details of initializing the autobaud microcode preparing for the autobaud process and the memory structures used 4 3 9 4 1 Preparing for the Autobaud Process The host begins preparation for the auto baud process with the following steps Steps 1 and 2 are required if the SCC has been used after reset or after UART mode in order to re enable the process 1 Disable the SCC by clearing the ENR and ENT bits The host may wish to precede this action with the STOP_TRANSMIT commands to abort transmission in an orderly
27. System Clock or TIN1 Clock Divider bits in SCON 1 EQ 1 assuming that the DIV bit in SCON is set to 0 otherwise an additional divide by 4 must be included Sampling Rate BRG Clk Rate where BRG Clk rate gt Max Desired UART Baud Rate x 16 EQ 2 For instance if a 115 2K baud rate is desired with a 16 67 MHz system clock the minimum sampling rate possible is 1 843 MHz 115 2K x 16 This exact frequency can be input to RCLK1 or TIN1 as the sample clock If the system clock is to be used a 16 67 MHz system clock cannot produce an exact baud rate clock of 1 843 MHz The lowest one that can be used is Baud Rate 16 67 MHz 7 1 2 083 MHz Thus 2 083 MHz is the sampling rate and the SCON should be set to 000E to produce this Once the sampling rate is known the other two equations follow easily The maximum START bit length is calculated by the following equation Maximum start length Sampling Rate Recognized baud rate x 1 05 EQ 3 Thus for the first entry in the table the maximum start length is 1 8432 Mhz 115200 x 1 05 17 for an external sample clock The value 1 05 is a suggested margin that allows char acters 5 larger than the nominal character rate to be accepted In effect the margin deter mines the split point between what is considered to be a 56 7K character rate and what is a 38 4K character rate The margin should not normally be less than 1 03 due to clocking differences between UAR
28. TPM1 TPMO RPM PEN UM1 UMO FRZ CL RTISM SL COMMON SCC MODE BITS 4 3 8 3 UART RECEIVE BUFFER DESCRIPTOR RX BD The CP reports information about each buffer of received data by its BDs The Rx BD is shown in Figure 4 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 E xX W l C A M ID BR FR PR OV CD OFFSET 2 DATA LENGTH OFFSET 4 RX BUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 2 UART Receive Buffer Descriptor MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP 4 3 8 4 UART TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the channel s Tx BD table The Tx BD shown in Figure 4 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vemo SR kW on Ae Pp oe el er OFFSET 2 OFFSET 4 OFFSET 6 TX BUFFER POINTER 24 bits used upper 8 bits must be 0 Figure 4 3 UART Transmit Buffer Descriptor 4 3 8 5 UART EVENT REGISTER The SCC event register SCCE is called the UART event register when the SCC is operating as a UART 7 6 5 4 3 2 1 0 4 3 8 6 UART MASK REGISTER The SCC mask register SCCM is referred to as the UART mask register when the SCC is operating as a UART If a bit in the UAR
29. echoing characters or transmitting characters The two methods are automatic echo and smart echo 4 3 9 8 1 Automatic Echo This method uses the SCC hardware to automatically echo the characters back on the TxD pin The automatic echo is enabled by setting the DIAG bits in the SCM to 10 The transmitter should not be enabled The hardware echo is done auto matically The CD pin needs to be asserted in order for the characters to be transmitted back On SCC1 the external CD pin must be tied low On SCC2 and SCC3 either the exter nal CD pin must be tied low or the CD pins should be left configured as general purpose input pins the CD signal to the SCC is then connected to ground internally Using the automatic echo the receiver still autobauds correctly and performance is not affected The SCC echoes the received data with a few nanoseconds delay 4 3 9 8 2 Smart Echo This method requires addition hardware and software to implement The user must provide two clock sources One clock source is the sample clock which is input on RCLK and cannot be divided down The BRG is used to divide the second clock down to provide the clock used for transmit The second clock can be either the system clock or a clock connected to TIN1 The TIN1 and RCLK pins can be connected to each other externally After the first character is received the user must take the following steps 1 Determine the baud rate from the returned NOM_START value and progra
30. if expired the PCMCIA cycle will be terminated and the PTIE interrupt to the PC will be generated if enabled ABUF Address Buffer Control This bit when set enables the address buffer control output function The PCMCIA con troller will not drive the high address lines A12 A23 as programmed in the base registers but instead will drive an address buffer control line with the appropriate timing This mech anism is useful when the paging is not sufficient for the system design requirements Ex ternal address buffers must be implemented on the card 16Bit PCMCIA Interface is 16 Bit 0 The PCMCIA interface is 8 data bits wide The D8 D15 and CE2 pins can be muxed for their alternative functions 1 The PCMCIA interface is 16 data bits wide AINC1 2 Auto Increment When set the corresponding common memory base address register will auto increment when the last entry in the page is accessed The last entry differs depending on the PC MCIA bus width programmed in bit 16 in the PCMCR register For PCMCIA 8 bit mode 16bit 0 in PCMR the last entry is PC_A11 PC_A0 fff for PCMCIA 16 bit mode 16bit 1 in PCMR the last entry in the page is PC_A11 PC_A1 7ff and CE2_ 0 word access or PC_A0 1 byte access This mechanism is useful during burst mode access es because it eliminates the need to reprogram the base address register when crossing a page boundary RISWDIS Ring Indicate Software Disable 0 The RIEvt bit in the IO
31. ister The chip then asserts PC_DREQ_ to the PC Host which in turn it executes a PC DMA Write cycle to the card The block transfer is terminated in two ways If the PC turns on during a transfer PC_DREQ_ or IDMA DREQ _ are not asserted any more and an interrupt is issued to the 68k if enabled event is in PCAWER Register If the IDMA Transfer Count is exhausted it internally asserts DONE_ and no more PC_DREQ_ or IDMA DREQ_ will be issued until the IDMA and the PC DMA registers are reprogrammed PCSTR is automatically reset upon ter mination In addition to those hardware events the CPU can reset the PCSTR bit and ter minate the transfer NOTE After software reset of the PCSTR the PC DMA hardware com pletes the transfer 5 3 11 2 Data Path and Swapping Issues The PC DMA specification does not define a byte transfer on PCD15 8 Byte transfers occur only on PCD7 0 With this constrain we assume that the specification is tailored only for Intel type masters Furthermore we assume that a PC Host with 16 bit data bus does not initiate a DMA block transfer at an odd address by doing so the Host would have to implement byte swapping from its high byte to its low byte MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc The following combinations of data bus width are supported 1 68k 8bit PC 8bit 2 68k 16bit PC 16bit 3 68k 16bit PC 8
32. memory or I O transfers depending on the value written in the configuration index of the con figuration option register COR If the configuration index is non zero the card will respond to I O cycles and the I O pin functionality replaces the memory card only pin configuration I O data transfers are used to read and write the 16550 registers 5 1 8 PCMCIA to 68000 Bus Access and Monitoring Options The PCMCIA controller can be programmed to allow the SDMA the core interrupt acknowl edge routine and external peripherals to use the 68000 bus between PCMCIA transfers by setting the BCLR bit in the PCMR register The PCMCIA controller can also be programmed to generate a bus clear signal and gain mastership of the bus when it is not immediately granted upon request This feature is enabled by setting the BCLROE bit in the PCMR If a PCMCIA to 68000 bus cycle is terminated with BERR the PCMCIA controller can be programmed to assert an interrupt to the PC through the INTRL bit in the PCMR The BERR status bit can be read by the PC through the BERR bit in the PCHER register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc There is also a PCMCIA bus watchdog timer which can issue an interrupt to the PC as well as the 68000 core The counter will count the WAIT length and if expired the PCMCIA cycle will be terminated and the PTIE interrupt to the PC
33. 18 ISR 3 17 IWUCR 2 6 LCR 4 27 LM 4 34 Load Boot Code from an SCC 3 8 Loopback Mode 4 3 Low Power 2 5 2 12 68000 bus 2 12 Low Power Drive Control Register _PDCR 2 12 2 14 Low Power Modes IMP 2 12 Low Power Stop STOP DOZE STAND_BY Mode 2 15 Low Power Support IWUCR 2 17 Low Power Clock Divider 2 9 LPDCR 2 14 LPM1 0 2 14 LS 4 34 LSR 4 28 M MC68000 MC68008 Modes 2 1 MC68PM302 Dual Port RAM 2 20 MCR 4 31 MF 11 0 2 10 MODCLK 2 7 2 12 MODCLK1 0 2 7 Mode Pin Functions 6 19 Mode Pins 6 6 MSR 4 33 Multiplication Factor 2 10 N NC1 6 16 NC1 See Signals NMSI 4 2 6 18 CD1 6 20 CTS1 6 21 NMSI1 6 19 NMSI2 6 21 NMSI3 6 23 RTS1 6 21 NMSI1 or ISDN Interface Pins 6 19 NMSI2 Port or Port A Pins or PCMCIA Data Bus 6 21 NMSI3 Port or Port A Pins or SCP Pins 6 23 No Connect Pins 6 16 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Index O OR3 OR0 3 26 Oscillator 2 8 PACNT 3 19 PADAT 3 20 PADDR 3 19 Parallel I O Pins with Interrupt Capability 6 27 Parallel I O Port PB11 3 18 3 19 PB8 3 19 3 30 Port A 3 17 6 21 6 23 6 24 Control Register 3 17 Port B 3 17 6 25 6 27 Control Register 3 18 Data Direction Register PBDDR 3 18 Parallel I O Ports 3 17 Parameter RAM 2 21 PB10 6 28 PB11 3 18 3 19 6 27 PB11 See DRAM Refresh PB11 See Parallel I O Port PB8 3 19 3 30 6 27 PBCNT 3 20 PBDAT 3 20 PBDDR 3 20 PC Progr
34. 2 mA A1 A23 PBO PB11 FC0 FC2 CS0 CS3 ee IACK BG RCLK1 RCL RCLK3 ____ 0 5 TCLK1 TCLK2 TCLK3 RTS1 KiS RTS3 SDS2 PA12 RXD2 RXD3 CTS2 CD2 CD3 DREQ BRG1 Ilo 5 3mA AS UDS LDS R W BERR _ 05 BGACK DIACK DACK y D0 D15 RESET lo 7 0 mA TXD1 TXD2 TXD3 0 5 lo 8 9mA DONE HALT BR as output 0 5 Io 3 2mA CLKO ae lo 3 2 mA All other pins E Output Drive CLKO OcLk 50 pF Output Drive Except CLKO Oat 100 pF Output Drive Derating Factor for CLKO of 0 030 ns pF OkF 20 50 pF Output Drive Derating Factor for CLKO of 0 025 ns pF OkF 50 130 pF Output Drive Derating Factor for All Other Pins 0 025 ns pF OkF 20 100 pF Output Drive Derating Factor for All Other Pins 0 05 ns p OkF 100 200 pF Power 5 0 Volt Pat y 4 5 5 5 y 3 3 Volt Part D9 3 0 3 6 Common Vss 0 0 V NOTE The maximum lop for a given pin is one half the l rating for that pin For an lop between 400 uA and lo1 2 mA the minimum Voy is calculated as Vpp 1 05 VimA lou 400 mA MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 5 DC ELECTRICAL CHARACTERISTICS NMSI1 IN IDL MODE Characteristic Symbol Min Max Unit Condition Input Pin Characteristics L1CLK L1SY1 L1RXD L1GR Input Low Level Voltage Vit 10 20 V of Vpp Input
35. 30 a mae tS 86 Clock High to BGACK Low tCHBKL 30 25 20 ns AS and BGACK High the Latest One to 2 5 2 5 2 5 clks 87 BGACK Low when B Is Asserted tABHBKL 1 5 30 1 5 25 1 5 20 ns BG Low to BGACK Low No Other Bus 2 5 2 5 2 5 clks 88 Master see Notes 3 be 4 taqLBKL 1 5 30 1 5 125 1 5 20 ns 89 IRN Impedance to BG High see Notes tBRHBGH 0 0 0 ns Clock_on which BGACK Low to Clock on 90 which AS Low tCLBKLAL 2 2 2 2 2 2 clks 91 Clock High to BGACK High tCHBKH 30 25 20 ns 92 Clock Low to BGACK High Impedance CLBKZ sae 15 15 10 ns 93 Clock High to DACK Low tCHACKL 30 25 20 ns 94 Clock Low to DACK High tCLACKH 30 25 20 ns 95 Clock High to DONE Low Output tCHDNL 30 25 20 ns 96 Clock Low to DONE High Impedance tcLDNz 30 25 20 ns DONE Input Low to Clock High lt 97 Asynchronous Setup DNLTCH 15 15 10 ns NOTES 1 DREQ is sampled on the falling edge of CLK in cycle steal and burst modes 2 If 80 is satisfied for DREQ 81 may be ignored 3 BR will not be asserted while AS HALT or BERR is asserted 4 Specifications are for DISABLE CPU mode only 5 DREQ DACK and DONE do not apply to the SDMA channels 6 DMA and SDMA read and write cycle timing is the same as that for the M68000 core MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor
36. BSW bit in the PCMCIA Protection Register See Section Section 3 System Integration Block SIB and toggling the BSWEN bit in the PPR 3 2 2 Basic Procedure The MC68PM302 is booted in its 8 bit mode by externally connecting the BUSW pin to GND It is expected that the MC68PM302 will be executing out of EPROM or Flash at this time and that no external data memory is available in 8 bit mode The MC68PM302 initializes the BAR register to place the 4K block of dual port RAM and peripherals in an area that does not overlap the EPROM region Note that this is part of a normal 302 initialization sequence Also note that the CFC bit of the BAR register should NOT be set it must be cleared At this time other desired initialization should be completed on the MC68PM302 No bus masters IDMA SDMA or external should be enabled While in 8 bit mode the MC68PM302 should initialize the external memory registers that control the16 bit external memory space External memory refresh is not enabled at this time but all other desired external memory control features should be enabled Note that the MC68PM302 does not access the external memory itself yet only the external memory control registers The MC68PM302 now copies a special boot code to the user area of the internal dual port RAM and then jumps to the start of that code This code is copied as data to the dual port RAM To summarize the procedure is then e Boot up MC68PM302 e P
37. Controller Freescale Semiconductor Inc Table 5 8 Common Memory Read Function Mode PC_REG PC_CE2 PC_CE1 Pc_Ao Pc_oE pc_we S a pc_p7 pc_po Standby Mode x H H x x x High Z High Z H H L L L H High Z Even Byte Byles necess H H L H L H High z Odd Byte Word Access H L L x L H Odd Byte Even Byte Odd Byte Only Access H L H x L H Odd Byte High Z Table 5 9 Common Memory Write i PC_D15 Function Mode PC_REG PC_CE2 PC_CE1 PC_A0 PC_OE PC_WE PC D8 PC_D7 PC_DO Standby Mode x H H x x x XXX XXX H H L L H L XXX Even Byte Byte Access H H L H H L xxx Odd Byte Word Access H L L x H L Odd Byte Even Byte Odd Byte Only Access H L H x H L Odd Byte XXX Table 5 10 Card Common Memory Space Address Map PCMCIA 68000 Selected Register PC_REG PC_CE1 PC_CE2 PC_OE PC_WE a lt z a Offset Address Base Address or Space Common memory Common memory H L H L L H A25 1 base reg1 read accesses FC A23 11 into 68000 bus W L Common memory Common memory H L H L A25 1 base reg1 write accesses FC A23 11 into 68000 bus W L Common memory Common memory H L L H A25 0 base reg2 read accesses FC A23 11 into 68000 bus W L Common memory Common memory H L H L A25 0 base reg2 write accesses FC A23 11 into 68000 bus PC_CE2 will remain unasserted during byte accesses 5 1 6 Protecting Memory and Internal Space from PCMCIA Accesses
38. Controller Accesses eo ccce 1 sce tesco oe heeeiehi dete me retieeeiys 5 22 PCMCIA Mode Register PCMR ccceceeeeeeeeeeeeeeeeeeeneeeeeeeeeseeeeeeeees 5 22 PCMCIA Configuration Registers Write Event Register PCRWER 5 26 PCMCIA Configuration Registers Write Mask Register PCRWMR 5 27 PCMCIA Access Wake Up Event Register PCAWER cee 5 27 PCMCIA Access Wake up Mask Register PCAWMR ceeee 5 28 PCMCIA Host PC Event Register PCHER eeeeeeeeeeeeeeeeeeees 5 29 CIS Base Address Register CISBAR 22 c cceeeeeeeeeeeeeeeeeeeeseeeeees 5 29 Common Memory Space Base Address Register CMBAR1 2 5 30 Card Configuration ReQisters ceccsccceceeeeseeeeeceeeeeeeeeenaeeeeeeeeeeaeees 5 31 Configuration Option Register COR cccccceseeceeeeeeeeeeereeeeeeeeeneaaees 5 31 Card Configuration and Status Register CCSR eceeeeeeeeeeeesetees 5 32 Pin Replacement Register Organization PRR cceeeeeeeeeereeeeees 5 33 Socket and Copy Register SCR cccccesseeeecceeeeeeeeeeeeeeeeeeeenaeees 5 34 I O Event Indication Register IOEIR ccccccccseeeeeeeeeeeeetteeeeeeeeeee 5 35 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Paragraph Title Page Number Number 5 3 10 6 Reserved RegiSters sain sietien Aisi ee Ba A
39. DB DB DB DB 0 Input 1 Output Port B Data Register PBDAT 15 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PB PB PB PB PB PB PB PB PB PB PB PB Port D Data Register PDDAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 PD PD PD PD PD PD PD 0 0 0 0 0 0 0 0 Figure 3 2 Parallel I O Port Registers 3 7 TIMERS The MC68PM302 includes four timer units two identical general purpose timers a software watchdog timer and a periodic interrupt timer PIT Each general purpose timer consists of a timer mode register TMR a timer capture regis ter TCR a timer counter TCN a timer reference register TRR and a timer event register TER The TMR contains the prescaler value programmed by the user The software watch dog timer which has a watchdog reference register WRR and a watchdog counter WCN uses a fixed prescaler value 3 7 1 General Purpose Timers Programming Model 3 7 1 1 Timer Mode Register TMR1 TMR2 TMR1 and TMR2 are identical 16 bit regis ters TMR1 and TMR2 which are memory mapped read write registers to the user are cleared by reset 15 8 7 6 oa A wo N Oo PRESCALER VALUE PS CE OM ORI FRR CLK RST MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB RST Reset Timer 0 Reset timer software reset includes clearing the T
40. External Master can acquire the bus by asserting HALT rather than using the normal arbitration mechanism In the disable CPU mode the PM302 makes requests for the bus rather than granting the bus In such a system the IMP functions as an external master and the external processor MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc e g an MC68030 does not assert BGACK as it accesses the IMP s on chip RAM and reg isters 3 8 3 2 External Bus Arbitration Using HALT When the CPU is enabled and the PCMCIA interface is enabled an external bus master may gain ownership of the M68000 bus by asserting the HALT signal In order to enable external bus arbitration in this mode the EMEN bit in the SCR should be set Assertion of the HALT signal will cause the PM302 bus master M68000 core SDMA IDMA or PCMCIA to stop at the completion of the current bus cycle the external bus master must wait until AS is negated plus 2 additional system clocks before accessing the bus to allow the PM302 to threestate all of the bus signals After gaining ownership the external master can not access the internal IMP registers or RAM Chip select logic and system control functions such as the hardware watchdog continue to operate When an external master desires to gain ownership the following bus arbitration protocol should be used 1 Assert
41. Fall Times PLL Disabled textre 5 5 5 ns Note The minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency lt ac gt EXTAL INPUT VOLTAGE MIDPOINT lt O gt CLKO OUTPUT Figure 7 1 Clock Timing MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 2 AC Electrical Characteristics IMP Phased Lock Loop PLL Characteristics Characteristics Expression Min Max Unit VCO frequency when PLL enabled MF Ef 10 f Note 1 MHz PLL external capacitor XFC pin to VCCSYN MF Cyec Note 1 MF lt 5 MF 340 MF 480 pF MF gt 5 MF 380 MF 970 1 fis the maximum operating frequency Ef is EXTAL frequency CXFC is the value of the PLL capacitor connected between XFC pin and VCCSYN for MF 1 The recommended value for Cygc is 400pF for MF lt 5 and 540pF for MF gt 5 The maximum VCO frequency is limited to the internal operation frequency as defined above Examples 1 vccsYN MODCK 1 2 Crystal is 32 768 KHz or 4 192 MHz initial MF 401 initial frequency 13 14 MHz lat er MF is changed to 762 to support a frequency of 25 MHz Minimum Cyegc is 762 x 380 289 nF maximum Cygc is 401 x 970 390 nF The recommended CxFo for 25 MHz is 762 x 540 414 nF 289 nF lt cxpc lt 390 nF and closer
42. High Level Voltage Vin Vpp 20 Vpp 10 V Input Low Level Current IlL 10 uA Vin Vss Input High Level Current My 10 uA Vin Vpp Output Pin Characteristics L1TXD SDS1 SDS2 L1RQ Output Low Level Voltage VoL 0 1 0 V lo 5 0 mA Output High Level Voltage VoH Vpp 1 0 Vpp V lon 400 uA MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 6 IMP CHARACTERISTICS 7 6 1 IMP AC ELECTRICAL SPECIFICATIONS CONTROL TIMING GND 0 Vdc TA 0 to 70 C The electrical specifications in this document are preliminary See Figure 7 1 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Min Max Min Max Min Max Unit System Frequency fsys dc1 16 67 dci 20 00 dc 25 00 MHz Crystal Frequency fXTAL 25 6000 25 6000 25 6000 kHz On Chip VCO System Frequency fsys 10 16 67 10 20 10 25 MHz mo o o et beam With external crystal oscillator enabled osc j i CLKO stability ACLK TBD TBD TBD TBD TBD TBD 1 CLKO Period toye 60 50 40 ns 1A EXTAL Duty Cycle tdcye 40 60 40 60 40 60 1C External Clock Input Period tEXxTcyc 60 50 40 ns 2 3 CLKO Pulse Width measured at 1 5v tow1 TBD TBD TBD ns 4 5 CLKO Rise and Fall Times full drive tor 5 4 4 ns 5B EXTAL to CLKO skew PLL Disabled texTP1 2 11 2 9 2 7 ns 5C 5D EXTAL Rise and
43. IMP PLL input CLKIN when the IMP PLL is disabled or from the IMP PLL VCO output when the PLL is enabled The BRG prescaler input clock may be optionally programmed to be divided by 2 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senvueandaeten Inc to allow very low baud rates to be generated from the system clock by setting the BCD bit in the IOMCR 2 4 3 5 3 PIT Clock CLKIN is supplied to the periodic interrupt timer PIT submodule which allows the PIT clock to run independently of the system clock refer to Figure 2 2 and Section 3 System Integration Block SIB 2 4 3 6 IMP PLL PINS The following pins are dedicated to the IMP PLL operation 2 4 3 6 1 VCCSYN This pin is the Vcc dedicated to the analog IMP PLL circuits The volt age should be well regulated and the pin should be provided with an extremely low imped ance path to the Vcc power rail if the PLL is to be enabled VCCSYN should be bypassed to GNDSYN by a 0 1 uF capacitor located as close as possible to the chip package VCCSYN should be tied to ground if the PLL is to be disabled 2 4 3 6 2 GNDSYN This pin is the GND dedicated to the analog IMP PLL circuits The pin should be provided with an extremely low impedance path to ground GDNSYN should be bypassed to VCCSYN by a 0 1 uF capacitor located as close as possible to the chip pack age The user should also bypass GNDSYN to VCC
44. L1SY0 SDS1 CDTIL1SY1 OTSTILIGR RTST L1RQ GCIDCL NMSI2 PAIO PCMCIA DATA RXD2 PA0 PC_D8 TXD2 PA1 PC_D9 RCLK2 PA2 PC_D10 TCLK2 PA3 PC_D11 CTS2 PA4 PC_D12 RTS2 PA5 PC_D13 CD2 PA6 PC_D14 BOOT BRG2 SDS2 PA7 PC_15 NMSI3 PAIO SCP RXD3 PA8 TXD3 PA9 RCLK3 PA10 TCLK3 PA11 CTS3 SPRXD RTS3 SPTXD CD3 SPCLK MODCK0 BRG3 PA12 TIMER PBIO TIN1 PB3 TRIS TIN2 PB5 PC_EN TOUT2 PB6 WDOG PB7 DREQ PC_DREQ PB8 RI PB9 PB10 PB11 PCMCIA PortD pcjoRD DREGIPAI3 PC_IOWR DACK PA14 PC_WE DONE PA15 PC_REG UDS AO PC_OE BGACK PC_CE1 LDS DS PC_CE2 IACK1 PB2 PC_A25 IACK6 PB1 PC_A11 IACK7 PBO PC _A10 TOUT1 PB4 PC_A9 PC_A6 PDI14 PDI11 PC_AS FRZ PC_A4 AVEC PC_A3 BERR PC_A2 PC_A0 PDI10 PDI8 Pins available in PGA Package In PGA package these signals are only available on the new pins and are not driven on any of the muxed pins lt lt _ _ lt _ lt _J Freescale Semiconductor Inc Address Bus A1 A19 Chip Select CSO MOUT2 CS3 CST DO D15 Data Bus IS Bus Control WEH AO UDS AO WEL WE LDS DS OE RW DTACK System Control BUSW PC_ABUF DISCPU Interrupt Control IPLO RQT BR IPLT IRQ6 BGACK IPL2 IRQ7 BG CLKO EXTAL XTAL XFC VCCSYN CLOCK PCMCIA PC_DO PC_D3 1 FC2 0 PC_D7 4 A23 A20 PC_WAIT BG PC_STSCHG BR PC_RDY PC_IREG RW NC1 NC2 Note Signals in parenthesis are only valid in a system where DISCPU PC_EN 1 P
45. MC68PM302 has power supply pins throughout the outer four rows columns and Voc pins on the Vcc ring located on the perimeter of the inner ground pins Special attention should be paid to connecting the IMP PLL power pins designated by VCCSYN and GNDSYN respectively see 2 4 3 6 IMP PLL Pins Careful attention has been paid to reduc ing IMP noise potential cross talk and RF radiation from the output drivers Inputs may be 5 V when Vec is 0 V without damaging the device 6 4 WHEN TO USE PULLUP RESISTORS Pins that are input only or output only do not require external pullups The bidirectional bus control signals require pullups since they are three stated by the processor when they are not being driven Open drain signals always require pullups Unused inputs should not be left floating If they are input only they may be tied directly to Voc or ground or a pullup or pulldown resistor may be used Unused outputs may be left unconnected Unused I O pins may be configured as outputs after reset and left unconnect ed If the IMP is to be held in reset for extended periods of time in an application other than what occurs in normal power on reset or board test sequences due to a special application re quirement such as Vcc dropping below required specifications etc then three stated sig nals and inputs should be pulled up or down This decreases stress on the device transistors and saves power See the RESET pin description for the cond
46. Master Internal Asynchronous Read Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 113 Ha s S5 Sw Sw Sw Sw Sw s4 gt S3 119 S2 2 1 i y y i A A CG k A 3 NY ek OS ge 88 26 yee Be Be iE 3 di po Hg fo R Figure 7 9 External Master Internal Asynchronous Write Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 7 IMP AC Electrical Specifications External Master Internal Synchronous Read Write Cycles see Figure 7 10 Figure 7 11 and Figure 7 12 16 67 MHzat 20 MHz at 25 MHz at Num Characteristic Symbol 5 0 V 5 0 V 5 0 V Unit Min Max Min Max Min Max 110 Address Valid to AS Low tavASL 15 12 10 ns 111 AS Low to Clock High tASLCH 30 25 20 ns 112 Clock Low to AS High CLASH 45 40 30 ns 113 AS High to Address Hold Time on Write tasHAH 0 0 0 ns 114 AS Inactive Time tasH 1 1 1 clk 115 UDS LDS Low to Clock High see Note 2 tsLcH 40 3
47. NE PE OEE ENAA TEA EEEE REENA 4 38 4 4 5 4 16550 Transmit CommandS sssessssseseeerrrrerternrrrrerrrrnnnnnnetrnnnnnnreennn 4 38 4 4 5 4 1 STOP TRANSMIT GOMMANGicctescccitecctteetet otis tittecisehadiacai ed eteeaacaeatelats 4 38 4 4 5 4 2 RESTART TRANSMIT Command 4vcishia nwa ahaa 4 39 4 4 5 5 16550 Receive COMMANAS cccceeeeeseceeeeeeeeseneeeeeeeeeenaeeeeeeeeeeeee 4 39 4 4 5 5 1 ENTER HUNT MODE Comma ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeee 4 39 4 4 5 6 16550 Control Characters ReCeiVEl ccceeeeeseeeeeeeeeeeeeteeeeeeeeeeee 4 39 4 4 5 6 1 Transmission of Out of Sequence Characters Transmitter 4 40 4 4 5 7 BREAK Support Receiver eeecceccceeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeeenneeeeeees 4 41 4 4 5 8 Send Break Transmitter cccceceeeseccceeeeeeeseaeeeeeeeeeseeeeaeeeeeeeeeeseaees 4 41 4 4 5 9 16550 Error Handlinga eee aril en a a ea 4 41 4 4 5 9 1 IDLE Sequence Receive eeeeeccceeeeeeeeeeeeceeeeeeeeeeeeaeeeeeeeeeeaaeeeeeeetenee 4 41 4 4 5 9 2 BREAK SGQUONCC sena e tae adie cutee da teteets 4 42 4 4 5 10 16550 Rx Buffer Descriptor Rx BD ccccceeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeeee 4 42 4 4 5 11 16550 Tx Buffer Descriptor Tx BD x ccdectissecacess ectvavees Gicesiwcoeruteceeseewedite 4 43 4 4 5 12 TESSO0 EVEMEREOISIC Re ceraale ore rdhe ca bes eed Absa lene dela 4 45 4 4 5 13 16550 Mask Register cccceeeesccceeeeeeeseeeeeceeeees
48. Product Go to www freescale com Freescale Semiconductor Inc SECTION 4 COMMUNICATIONS PROCESSOR CP The CP includes the following modules 4 oh Main Controller RISC Processor Six Serial Direct Memory Access SDMA Channels A Command Set Register Serial Channels Physical Interface Including Motorola Interchip Digital Link IDL General Circuit Interface GCI Also Known as IOM 2 Pulse Code Modulation PCM Highway Interface Nonmultiplexed Serial Interface NMSI Implementing Standard Modem Signals Three Independent Full Duplex Serial Communication Controllers GCCs Supporting the Following Protocols High Level Synchronous Data Link Control HDLC SDLC Universal Asynchronous Receiver Transmitter UART Binary Synchronous Communication BISYNC Transparent Modes Uart 16550 Hardware and Software Emulation Serial Communication Port SCP for Synchronous Communication Two Serial Management Controllers SMCs to Support the IDL and GCI Management Channels MC68PM302 KEY DIFFERENCES FROM THE MC68302 SCC2 Is Only Available when the PCMCIA Is Used in 8 Bit Data Operation and the 16550 Channel Is Disabled The DDCMP and V 110 Protocols Were Removed The Autobaud Function Was Added for Detecting the Baud Rate of the Incoming Asyn chronous Bit Stream This section only presents a description of features and registers that have changed or been added Features that have not changed s
49. ResEnab3 ResEnab2 PlEnab RlEnab Read Write The 68000 core will receive an interrupt when this register is written by the PC See 5 3 5 PCMCIA Access Wake Up Event Register PCAWER This is an optional register that contains information about the changes in the card status Its bit assignments are defined below This register may be read or written The upper four bits are latched to a one when the corresponding IO event occurs on the PC card When one of these upper four bits is latched and the corresponding enable bit in the lower nibble has also previously been set the changed bit in the card configuration and status register CCSR is set to a one and the STSCHG pin will be driven low if enabled by the SigChg bit in the CCSR The host can clear any one of the upper four bits by writing a one to that bit Writing a zero to these bits will have no effect All bits of this register are cleared by an IMP reset ResEvt3 Reserved for future expansion definition Set to zero ResEvt3 Reserved for future expansion definition Set to zero PIEvt This bit is latched to a one by the card the 68000 core can set this bit after the receipt of a valid incoming packet over a modem channel When this bit is set to a one and the PI Enab bit is set to a one the changed bit in the card configuration and status register will also be set to a one If the SigChg bit in the card configuration and status register has also been set by the host then th
50. SCCS1 register CD1 may also be used as an external sync in NMSI mode CD71 will be grounded internally when this pin is used for an alternate function CTS1 L1GR Clear to Send Layer 1 Grant This input is the NMSI1 CTS signal in the NMSI mode or the grant signal in the IDL GCI mode If this pin is not used as a grant signal in GCI mode it should be connected to Vcc If the CTS1 pin has changed for more than one transmit clock cycle the IMP asserts the appropriate bit in the SCC1 event register and optionally aborts the transmission of that frame If SCC1 is programmed not to support CTS1 in the SCC1 mode register then this pin may be used as an external interrupt source The current value of the CTS1 pin may be read in the SCCS1 register RTS1 L1RQ GCIDCL Request to Send Layer 1 Request GCl Clock Out This output is the NMSI1 RTS signal in NMSI mode or PCM Highway mode the IDL re quest signal in IDL mode or the GCI data clock output in GCI mode In PCM Highway mode RTS1 is asserted high RTS1 is asserted when SCC1 in NMSI mode has data or pad flags or syncs to transmit In GCI mode this pin is used to output the GCI data clock 6 1 15 NMSI2 Port or Port A Pins or PCMCIA Data Bus The NMSI2 port or port A pins are shown in Figure 6 11 The PCMCIA function of these pins is shown in italics NOTE Those pins function as PAIO NMSI2 when PCMCIA is disabled PC_EN 0 or when PCMCIA is configured to 8 bit memory 16b
51. SPCLK Clock Output Rise Fall Time 0 15 0 10 0 8 ns 252 Delay from SPCLK to Transmit see Note 1 0 40 0 30 0 24 ns 253 SCP Receive Setup Time see Note 1 40 30 24 ns 254 SCP Receive Hold Time see Note 1 10 8 7 ns NOTES 1 This also applies when SPCLK is inverted by CI in the SPMODE register 2 The enable signals for the slaves may be implemented by the parallel I O pins SPCLK OUTPUT SPTXD OUTPUT SPRXD INPUT Figure 7 19 Serial Communication Port Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 15 IMP AC Electrical Specifications IDL Timing Ali timing measurements unless otherwise specified are referenced to the L1CLK at 50 point of VDp see Figure 7 20 16 67 MHz 20 MHz 25 MHz Num Characteristic at 5 0 V at 5 0 V at 5 0 V Unit Min Max Min Max Min Max 260 L1CLK IDL Clock Frequency see Note 1 6 66 8 10 MHz 261 L1CLK Width Low 55 45 37 ns 262 L1CLK Width High see Note 3 P 10 P 10 P 10 ns 263 Tee L1RQ SDS1 SDS82 Rising Falling __ 20 17 14 ng 264 Ea sync Setup Time to L1CLK Falling 39 _ 25 _ 20 _ S L1SY1 sync Hold Time from L1CLK Fall 265 Ing AARS 50 40 34 ns 266 L1SY
52. Select 0 Interrupt Output 2 In normal operation this pin functions as CSO CSO is one of the four active low output pins that function as chip selects for external devices or memory It does not activate on accesses to the internal RAM or registers including the BAR SCR or CKCR registers When the M68000 core is disabled this pin operates as IOUT2 When the M68000 core is disabled IOUT2 provides the interrupt request output signal from the IMP interrupt con troller to an external CPU This signal is asserted if an internal Interrupt of level 4 6 7 is generated CS3 CS1 Chip Selects 3 1 These three active low output pins function as chip selects for external devices or mem ory CS8 CS0 do not activate on accesses to the internal RAM or registers including the BAR SCR or CKCR registers MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 6 1 9 No Connect Pins NC1 NC2 are reserved for future use and should not be connected 6 1 10 PGA Package Pins Figure 6 9 PGA Package Pins FRZ Freeze Activity The FRZ pin is used to freeze the activity of selected peripherals This is useful for sys tems debugging purposes See section 3 1 5 Freeze Control for more details FRZ should be continuously negated during total system reset 1AC Internal Access The IAC signal is only available in the PGA package This output ind
53. Semiconductor Inc PCMCIA Controller PUCR 68000 Address BAR 8E0 7 6 5 4 3 2 1 0 3 3VM PUC6 PUC5 PUC4 PUC3 PUC2 PUC1 Reserved ee 0 0 0 0 0 0 0 Read Write 3 3VM 3 3V Mode This bit should be set when the operating the MC68PM302 at 3 3V to ensure proper pullup resistance values 0 5V Mode 1 3 V Mode PUC6 This bit when cleared will enable a 100K ohm pulldown resistor for each of these PCM CIA address pins Setting this bit will disable the pulldowns 0 PC_AO 1 2 6 7 8 9 are pulled down PC_A3 4 5 10 11 25 are pulled down only if PC_EN 1 1 All pulldowns are disabled PUC5 This bit when cleared will enable a 10K ohm pullup resistor for each of the PCMCIA con trol pins Setting this bit will disable the pullups 0 PC_CE1 PC_CE2 PC_REG PC_IORD are pulled up 1 All pullups are disabled PUC4 This bit when cleared will enable a 10K ohm pullup resistor for these pins when PCMCIA is disabled Setting this bit will disable the pullups 0 PC_RDY RW PC_STSCHG BR PC_WAIT BG are pulled up only if PC_EN 0 1 All pullups are disabled PUC3 This bit when cleared will enable a 10K ohm pullup resistor for each of the PCMCIA con trol pins Setting this bit will disable the pullups 0 PC_WE PC_IOWR PC_OE are pulled up 1 All pullups are disabled PUC2 This bit when cleared will enable a 100K ohm pulldown resistor for each of the PCMCIA data pins Setting this bit
54. Signal Description DONE PA15 PC_WE DONE or Parallel IO or PCMCIA Write Enable Program DONE is a bidirectional open drain signal asserted by the IDMA or by a peripheral device during any IDMA bus cycle to indicate that the data being transferred is the last item ina block The IDMA asserts this signal as an output during a bus cycle when the byte count register is decremented to zero Otherwise this pin is an input to the IDMA to terminate IDMA operation PCMCIA Write Enable Program the WE PGM input is used for strobing memory write data into the memory card 6 1 18 IACK or PIO Port B Pins or PCMCIA The IACK or PIO port B pins are shown in Figure 6 14 4 gt IACK7 PB0 PC_A11 a IACK6 PB1 PC_A25 gt IACK1 PB2 PC_CE2 Figure 6 14 IACK or PIO Port B Pins In non PCMCIA Mode each one of these three pins can be used either as an interrupt ac knowledge signal or as a general purpose parallel I O port NOTE These pins function as PCMCIA if PC_EN 1 NOTE The IMP interrupt controller does not require the use of the IACK pins when it supplies the interrupt vector for the external source IACK7 PB0 PC_A11 Interrupt Acknowledge or Port B I O or PCMCIA Address IACK7 is an active low output signal that indicates to the external device that the IMP is executing an interrupt acknowledge cycle The external device must then place its vector number on the lower byte of the data bus or use AVEC for autovectoring unless internal v
55. TB B BR TD TR UN CT OFFSET 2 DATA LENGTH OFFSET 4 TXBUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 7 BISYNC Transmit Buffer Descriptor 4 3 11 5 BISYNC EVENT REGISTER The SCC event register SCCE is referred to as the BISYNC event register when the SCC is programmed as a BISYNC controller It is an 8 bit register used to report events recognized by the BISYNC channel and to generate inter rupts On recognition of an event the BISYNC controller sets the corresponding bit in the BISYNC event register Interrupts generated by this register may be masked in the BISYNC mask register This register is cleared at reset 7 6 5 4 3 2 1 0 ets cD Txe RCH Bsy Tx RX 4 3 11 6 BISYNC MASK REGISTER The SCC mask register SCCM is referred to as the BISYNC mask register when the SCC is operating as a BISYNC controller It is an 8 bit read write register that has the same bit format as the BISYNC event register If a bit in the BISYNC mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt in the event register will be masked This register is cleared upon reset 4 3 12 Transparent Controller The functionality of the transparent controller has not changed For any additional informa tion on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 12 1 TRANSPARENT MEMORY MAP W
56. TOUT2 PB6 BOOT BRG2 SDS2 PA7 Table 6 1 Table 6 2 and Table 6 3 show the MC68PM302 signals in their functional groups Each table includes a note describing in which modes PCMCIA enable or Disable CPU specific signals are available Table 6 13 defines the actual function of the pins as a function of the mode of opera tion The following paragraphs describe all the IMP signals and their functionality The PC MCIA signals are described following those paragraphs Please refer to Table 6 1 Ta ble 6 2 and Table 6 3 for when a signal is available The PCMCIA interface is enabled by connecting the PC_EN pin high during reset After re set the PC_EN pin becomes TOUT2 PB6 The CPU is disabled by connecting the DISCPU pin to VCC The IMP uses a M68000 like bus for communication between both on chip and external pe ripherals This bus is a single continuous bus existing both on chip and off chip Any access made internal to the device is visible externally Any access made external is visible inter nally Thus when the M68000 core accesses the dual port RAM the bus signals are driven externally Likewise when an external device accesses an area of external system memory the chip select logic can be used to generate the chip select signal and DTACK MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description NMSI1 ISDN I F RXD1 L1RXD TXD1 L1TXD RCLK1 L1CLK TCLK1
57. TQFP it was not possible to make the PM302 exactly pin compatible with the original 68302 Thus the PM302 should not be used as a drop in replacement for the 68302 in a 144 TQFP MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Introduction Freescale Semiconductor Inc MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 2 CONFIGURATION CLOCKING LOW POWER MODES AND INTERNAL MEMORY MAP The MC68PM302 integrates a high speed M68000 processor with multiple communications peripherals The provision of direct memory access DMA control and link layer manage ment with the serial ports allows high throughput of data for communications intensive appli cations such as basic rate Integrated Services Digital Network ISDN The MC68PM302 can operate either in the full MC68000 mode with a 16 bit data bus or in the MC68008 mode with an 8 bit data bus by connecting the BUSW PC_ABUF pin low dur ing reset NOTE The BUSW pin is static and is not intended to be used for dy namic bus sizing Instead the BSW and BSWEN bits in the PPR register should be used to switch the bus width after reset Refer to the MC68000UM AD M68000 8 16 32 Bit Microprocessors User s Manual and the MC68302UM AD MC68302 Integrated Multiprotocol Processor User s Manual for com plete details of the on chip microprocessor including t
58. The interrupt level generated as a result of one of the accesses can be programmed to the following 68000 interrupt levels 00 No interrupt is generated 01 The interrupt is generated on level 1 10 The interrupt is generated on level 6 11 The interrupt is generated on level 7 NOTE The interrupt will be generated as level triggered The user should program the GIMR register to generate the interrupt vec tor BCLROE Bus Clear Output Enable When this bit is set the PCMCIA controller will assert the BCLR signal when requesting the bus and it is not granted The IDMA when programed to work under software control will release the bus at the end of its current transfer BCLRIE Bus Clear Input Enable When this bit is set the PCMCIA controller will release the 68000 bus when BCLR is as serted and the current cycle is terminated regardless of the ArbIDL value BCLR can be asserted for the following reasons 1 The SDMA requests the 68000 bus 2 An external master requests the 68000 bus 3 A 68000 interrupt is pending and the BCLM bit is set in the SCR BERRIE Bus Error Interrupt Enable When this bit is set the PCMCIA control logic will generate an interrupt to the PC when a PCMCIA bus cycle results in a 68000 bus error SWAP Swapper Enable This bit when set enables the swapping function for direct read and write PCMCIA ac cesses The PCMCIA logic swaps the high and low bytes of 16 bit words when doing di
59. This Product Go to www freescale com Freescale Semiconductor Inc Index 4 22 TRIS 6 11 TRR1 TRR2 3 21 U UART Controller 4 6 Memory Map 4 6 Rx BD 4 6 SCCE 4 7 SCCM 4 7 Tx BD 4 7 UART Event Register 4 7 UART Mask Register 4 7 UART Mode Register 4 6 V Value 3 21 VCCSYN 2 7 2 12 VCO 2 9 2 10 Vector Generation Enable 3 6 3 29 W Wake_Up Clock Cycles IMP 2 13 Wake up PB10 2 18 PIT 2 18 PIT Event 2 18 Watchdog WDOG 3 18 6 27 Hardware 3 6 Timer 3 22 Watchdog WDOG See Signals Watchdog WDOG See Timers WCN 3 22 Write Protect Violation 3 4 X XFC 2 12 XTAL 6 9 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Index Freescale Semiconductor Inc Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080
60. This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller asynchronous accesses to the card configuration registers and MC68PM302 PCMCIA con troller registers Attribute accesses can only be byte wide and memory locations and ac cesses must be at even addresses only See Table 5 1 Table 5 2 and Table 5 3 for signal states and bus validity for the attribute memory read and write function 5 1 2 Configuration Registers The card configuration registers are built into the PCMCIA controller hardware These reg isters along with additional PCMCIA controller specific registers are visible to the PCMCIA bus and have PCMCIA addresses in the attribute space as shown in Table 5 4 Accesses to these registers are asynchronous with respect to the system clock Table 5 1 Attribute Memory Read Function Mode PC_REG PC_CE2 PC_CE1 Pc_Ao Pc_oE Pc_we S S pc_p7 pc_po Standby Mode x H H x x x High Z High Z L H L L L H High Z Even Byte Byte Access L H L H L H High z Not Valid Word Access L L L x L H Not Valid Even Byte Odd Byte Only Access L L H Xx L H Not Valid High Z Table 5 2 Attribute Memory Write PC_D15 Function Mode PC_REG PC_CE2 PC_CE1 PC_AO PC_OE PC_WE PC D8 PC_D7 PC_DO Standby Mode x H H x x x XXX High Z L H L L H L XXX Even Byte Byte Access L H L H H L XXX XXX Word Access L L L x H L XXX Even Byte Odd Byte Only Access L L H xX H L XX
61. Word Max_Length Counter SCC Base B6 HMASK Word User Defined Frame Address Mask SCC Base B8 HADDR1 Word User Defined Frame Address SCC Base BA HADDR2 Word User Defined Frame Address SCC Base BC HADDR3 Word User Defined Frame Address SCC Base BE HADDR4 Word User Defined Frame Address Should be initialized by the user M68000 core 4 3 10 2 HDLC MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The term HDLC mode register refers to the protocol specific bits 15 6 of the SCC mode register when that SCC is configured for HDLC The read write HDLC mode register is cleared by reset 15 14 13 12 11 10 9 8 7 6 5 0 NOF3 NOF2 NOF1 NOFO C32 FSE RTE FLG ENC COMMON SCC MODE BITS 4 3 10 3 HDLC RECEIVE BUFFER DESCRIPTOR RX BD The HDLC controller uses the Rx BD to report information about the received data for each buffer The Rx BD is shown in Figure 4 4 15 144 13 142 110 10 9 8 7 6 5 4 3 2 i 0 OFFSET 0 E xil wih i 1 Fe LG NO AB CR OV cD OFFSET 2 DATA LENGTH or RXBUFFER POINTER 24 bits used upper 8 bits must be 0 Figure 4 4 HDLC Receive Buffer Descriptor 4 3 10 4 HDLC TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the HDLC controller for transmission on an SCC channel by arranging it in buffers referenced by the channel s Tx BD
62. a flow control transmission character To use this entry instead as a receive control characters entry this E bit and all other E bits in the table should be zero R Reject Must be zero to use this entry as flow control transmission character For receive control characters entry it maintains its functionality as previously defined REA Ready This bit is set by the 68000 core when the character is ready for transmission and will re main one while the character is being transmitted The CP clears this bit after transmis sion I Interrupt If set the core will be interrupted when this character has been transmitted The TX bit will be set in the 16550 event register CHARACTER8 Flow Control Character Value This value contains the character to be transmitted This value may be modified only while the REA bit is cleared 4 4 5 7 BREAK SUPPORT RECEIVER The 16550 controller offers very flexible BREAK emulation support for the receiver See 4 4 5 9 2 BREAK Sequence for more details 4 4 5 8 SEND BREAK TRANSMITTER A break is an all zeros character without a stop bit s A break emulation is transferred to the PC by issuing the STOP TRANSMIT com mand The 16550 controller sends a programmable number of break characters according to the break count register BRKCR and then reverts to idle or sends data if the RESTART TRANSMIT command was given before completion The break characters do not pre empt characters already
63. and PCDRDY are described in Section 5 3 11 5 3 7 PCMCIA Host PC Event Register PCHER PCHER PMCIA Address A25 1 2A 68000 Address BAR 8C8 7 6 5 4 3 2 1 0 en A e Os RESET 0 O 0 0 0 0 0 0 Read Write BERR Bus Error This bit is set when a cycle is terminated by bus error An interrupt to the PC will be gen erated if the BERRIE bit is set This bit is cleared by writing one PTIE PCMCIA Timer Expired This bit is set when a cycle is terminated by a PCMCIA watchdog timer expiration An in terrupt to the PC will be generated if the TIEn bit is set This bit is cleared by writing a one SW 68000 Software Interrupt The 68000 S W may set this bit to generate an interrupt to the PC This bit is cleared by the PC writing a one 5 3 8 CIS Base Address Register CISBAR CISBAR PCMCIA Address A25 1 30 68000 Address BAR 8CC 15 14 13 12 11 10 9 8 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 RESET 0 0 0 0 0 0 0 0 PMCIA Address A25 1 32 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 FC2 FC1 FCO V RESET 0 0 0 0 0 0 0 0 Read Write This register is used to locate PCMCIA CIS accesses to the 68000 bus The CIS must be located in memories RAM EEPROM etc on the 68000 bus The 68000 core should pro gram the starting address of the CIS memory structure into this register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to w
64. and parity The host then uses the returned nominal start value from the lookup table modifies the SCC configuration register SCON to generate the correct baud rate and reprograms the SCC to UART mode Many rates are supported including 150 300 600 1200 2400 4800 9600 14 4K 19 2K 38 4K 57 6K 64K 96K and 115 2K To estimate the performance of the autobaud mode the performance table in Appendix A can be used The maximum full duplex rate for a MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc BISYNC channel is one tenth of the system clock rate So a 20 MHz IMP can support 115 2K autobaud rate with 2 low speed channels The performance can vary depending on system loading configuration and echoing mode It is important that the highest priority SCC be used for the autobaud function since it is run ning at avery high rate Any SCC that is guaranteed to be idle during the search operation of the autobaud process will not impact the performance of autobaud in an application Idle is defined as not having any transmit or receive requests to from the SCC FIFOs 4 3 9 1 AUTOBAUD CHANNEL RECEPTION PROCESS The interface between the auto baud controller and the host processor is implemented with shared data structures in the SCC parameter RAM and in external memory and through the use of a special command to the SCC The autobaud
65. be configured as an open drain output in NMSI mode L1TXD in IDL and PCM mode is a three state output In GCI mode it is an open drain output MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc RCLK1 L1CLK Receive Clock Layer 1 Clock This pin is used as an NMSI1 bidirectional receive clock in NMSI mode or as an input clock in IDL GCI and PCM modes In NMSI mode this signal is an input when SCC1 is working with an external clock and is an output when SCC1 is working with its baud rate generator The RCLK1 output can be three stated by setting bit 14 in the DISC register TCLK1 L1SY0 SDS1 Transmit Clock PCM Sync Serial Data Strobe 1 This pin is used as an NMSI1 bidirectional transmit clock in NMSI mode as a sync signal in PCM mode or as the SDS1 output in IDL GCI modes In NMSI mode this signal is an input when SCC1 is working with an external clock and is an output when SCC1 is working with its baud rate generator The TCLK1 output can be three stated by setting bit 15 in the DISC register NOTE When using SCC1 in the NMSI mode with the internal baud rate generator operating the TCLK1 and RCLK1 pins will always out put the baud rate generator clock unless disabled in the CKCR register Thus if a dynamic selection between an internal and external clock source is required in an application the clock pins should be disabled first in
66. bit in the BR is masked 1 The RW bit in the BR is not masked CFC Compare Function Code Should be disabled in PCMCIA mode if an external master uses the CS logic for its memory space 0 The FC bits in the BR are ignored 1 The FC bits on the BR are compared 3 8 1 3 PCMCIA Protection Register PPR This register controls the PCMCIA protection mechanism that blocks the chip select mechanism for external PCMCIA accesses made to the block of memory covered by the protected chip select It also includes the Protect Inter nal Registers PIR bit that controls the protection mechanism to block PCMCIA accesses to the internal registers and dual port RAM This register is located at BAR 82C This reg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BSW BSWEN PIR PCS3 PCS2 PCS1 PCSO ister is cleared at reset PCS 3 0 Protect Chip Select Each of these bits when set will disable the corresponding chip select for PCMCIA access es When a PCMCIA controller access is made to a protected memory space the chip select line will not assert and the DTACK line will also not be asserted This will result in MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc a 68000 bus error and an Interrupt to the PCMCIA if the BERRIE bit is set in the PCMR register PiIR Protec
67. bit is zero the corresponding interrupt in the event register will be masked This register is cleared upon reset 4 3 11 BISYNC Controller The functionality of the BISYNC controller has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 11 1 BISYNC MEMORY MAP When configured to operate in BISYNC mode the IMP overlays the structure listed in Table 4 10 onto the protocol specific area of that SCC param eter RAM Refer to System Configuration Registers on page 4 for the placement of the three SCC parameter RAM areas and Table 4 1 for the other parameter RAM values Table 4 10 BISYNC Specific Parameter RAM Address Name Width Description SCC Base 9C RCRC Word Temp Receive CRC SCC Base 9E CRCC Word CRC Constant SCC Base AO PRCRC Word Preset Receiver CRC 16 LRC SCC Base A2 TCRC Word Temp Transmit CRC SCC Base A4 PTCRC Word Preset Transmitter CRC 16 LRC SCC Base A6 RES Word Reserved SCC Base A8 RES Word Reserved SCC Base AA PAREC Word Receive Parity Error Counter SCC Base AC BSYNC Word BISYNC SYNC Character SCC Base AE BDLE Word BISYNC DLE Character SCC Base BO CHARACTER1 Word CONTROL Character 1 SCC Base B2 CHARACTER2 Word CONTROL Character 2 SCC Base B4 CHARACTER3 Word CONTROL Character 3 SCC Base B6 CHARACTER4 Word CONTROL Character 4 SCC Base B8 CHARACTER5 Word CONTROL Character 5 SCC Bas
68. bit when it is set OV Overrun bit 1 If this bit is set a receiver overrun occurred during autobaud reception NOTE The user must clear this bit when it is set CD Carrier Detect Lost bit 0 If this bit is set the carrier detect signal was negated during autobaud reception NOTE The user must clear this bit when it is set MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Lookup Table Size Lookup table size is the number of baud rate entries in the external lookup table Lookup Table Pointer The lookup table pointer is the address in the external RAM where the lookup table begins NOTE The lookup table cannot cross a 64k memory block boundary 4 3 9 4 4 Autobaud Lookup Table The autobaud controller uses an external lookup table to determine the baud rate while in the process of receiving a character The lookup table contains two entries for each supported baud rate The first entry is the maximum start length for the particular baud rate and the second entry is the nominal length for a 1 2 START bit To determine the two values for each table entry first calculate the autobaud sampling rate EQ 2 To do this EQ 1 must be used until EQ 2 is satisfied The sampling rate is the lowest speed baud rate that can be generated by the SCC baud rate generator that is over a thresh old defined in EQ 2 BRG Clk Rate
69. bits in the Chip Select registers to zero or mask them off Also FC2 0 are driven to 5 so we suggest that the function code comparison be turned off MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc 3 8 1 Chip Select Registers Each of the four chip select units has two registers that define its specific operation These registers are a 16 bit base register BR and a 16 bit option register OR e g BRO and ORO The BR should normally be programmed after the OR since the BR contains the chip select enable bit 3 8 1 1 Base Register BR3 BRO These 16 bit registers consist of a base address field a read write bit and a function code field 15 13 12 2 1 0 FC2 FCO BASEADDRESS A23 A13 RW EN FC2 FC0O Function Code Field This field is contained in bits 15 13 of each BR These bits are used to set the address space function code Because of the priority mechanism and the EN bit only the CSO line is active after a system reset Bits 12 2 Base Address These bits are used to set the starting address of a particular address space RW Read Write 0 The chip select line is asserted for read operations only 1 The chip select line is asserted for write operations only EN Enable 0 The chip select line is disabled 1 The chip select line is enabled After system reset only CSO is enabled CS3 CS1 are
70. by the chip selects for address comparison MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc 3 4 1 4 Function Code Register FCR The FCR is an 8 bit register 7 6 4 3 2 0 1 DFC 1 SFC The function codes must e initialized by the user The function code value programmed into the FCR is placed on pins FC2 FCO during a bus cycle to further qualify the address bus value NOTE This register is undefined following power on reset The user should always initialize it and should not use the function code value 111 in this register 3 4 1 5 Byte Count Register BCR This 16 bit register specifies the amount of data to be transferred by the IDMA up to 64K bytes BCR 0 is permitted 3 4 1 6 Channel Status Register CSR The CSR is an 8 bit register used to report events recognized by the IDMA controller On recognition of an event the IDMA sets its corre sponding bit in the CSR regardless of the INTE and INTN bits in the CMR 7 4 3 2 1 0 RESERVED DNS BES BED DONE Bits 7 4 These bits are reserved for future use DNS Done Not Synchronized Only Valid if the PCMCIA is disabled This bit is set if operand packing is performed between 16 bit memory and an 8 bit periph eral and the DONE signal is asserted as an input to the IDMA i e by the peripheral dur ing the first access of the 8 bit
71. controller uses receive buffer descriptor number 7 Rx BD7 for the autobaud command descriptor This Rx BD is initialized by the host to contain a pointer to a lookup table residing in the external RAM contains the maximum and nominal START bit length for each baud rate The host also prepares two characters against which the autobaud control ler will compare the received character usually these characters are a and A and the host initializes a pointer to a buffer in external memory where the assembled characters will be stored until the host stops the autobaud process Finally the host initializes the SCC data synchronization register DSR to 7FFF in order to synchronize on the falling edge of the START bit Once the data structures are initialized the host programs the SCON register to provide a sampling clock that is 16X the maximum supported baud rate The host then issues the Enter_Baud_Hunt command and enables the SCC in the BISYNC mode The autobaud controller reception process begins when the START bit arrives The auto baud controller then begins to measure the START bit length With each byte received from the SCC that belongs to the START bit the autobaud controller increments the start length counter and compares it to the current lookup table entry If the start length counter passed the maximum bit length defined by the current table entry the autobaud controller switches to the next lookup table entry the ne
72. dimes end etagh coun cidietias da ENERE EAA AAE RETENER ted 2 18 2 4 4 3 5 Ring Oscillator Control Register RINGOCR ceceeeeeeeeeeeeeeeeteee 2 19 2 4 4 3 6 Ring Oscillator Event Register RINGOEVR cccceeeeeeeteeeeeeeeeee 2 20 2 5 MC68PM302 Dual Port RAMs 5c6cit cn adeene hha 2 20 2 6 Internal Registers RAP 45 fice cence 5 a ccieecancceincchacng adus Seeneensaeeeces ne menace 2 23 Section 3 System Integration Block SIB 3 1 System Control oniar aean oa eaaet aa AE a AEE E 3 1 3 1 1 System Control Register SCR ssssssssseeesessnnnrrresrrrnnnrensrennnnnrnsrerennen 3 2 3 1 2 System Stat s Bilsa e in neeeerncoe ron nib EA SIEA EAE Ni 3 3 3 1 3 System Control Bits eth iA Si ial a Sa ANE a ke EAE Rei ee a 3 4 3 1 4 Hardware Watchdog ccccceeeeeeeeceeeeeeeeeeeeeeeeeeeeeeeeaaaaeeeeeeeeeesceeeeeees 3 6 3 1 5 Freeze COMMON icici ace attest aad hi tei ea tad 3 6 3 2 Programmable Data Bus Size Switch 0 eeececceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 3 7 3 2 1 Enabling the Dynamic Bus Switch eeeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeees 3 7 3 2 2 Basic PlOCCOUIG rei exe iee a a abe bete teats a aa 3 7 3 3 Load Boot Code from an SCC 2 02 00 As Giese 3 8 3 4 DIP ONO ieee aes aie e aa TE att hehe t ees Shh et A uke aes 3 11 3 4 1 68PM302 Different S inin E Tae ete aces 3 11 3 4 1 1 Channel Mode Register CMR eceeceeeeeeeeeeeeeeeeeeeeceeeeeeeeeeesnaaees 3 11 3 4 1 2 Sour
73. except that PB7 PBO is controlled by the port B control register PBCNT the port B data direction reg ister PBDDR and the port B data register PBDAT and PB7 is configured as an open drain output WDOG upon total system reset Table 3 3 shows the dedicated function of each pin The third column shows the input to the peripheral when the pin is used as a general purpose I O pin MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB Table 3 3 Port B Pin Functions PBCNTBit 1 PBCNTBit 0 Inputtolnterrupt Pin Function Pin Function Control and Timers IACK7 PBO IACK6 PB1 IACK1 PB2 TIN1 PB3 GND TOUT1 PB4 TIN2 PB5 GND TOUT2 PB6 WDOG PB7 3 6 2 2 PB11 PB8 PB11 PB8 are four general purpose I O pins continuously available as general purpose I O pins and therefore are not referenced in the PBCNT PB8 operates like PB11 PB9 except that it can also be used as the DRAM refresh controller request pin as selected in the system control register SCR NOTE If the PIT is enabled then the PB8 pin will not generate an inter rupt since the PIT uses the PB8 interrupt in the IPR IMR and ISR 3 6 3 Port D When the PCMCIA interface is disabled PC_EN tied to GND 7 general purpose INPUT ONLY pins are available as port D These pins also have optional internal pull
74. follows CLKO Drive Options CLKOMOD1 2 These bits are now in the IMP clock control register IPLCR on the MC68PM302 see 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaetesn Inc Three State TCLK1 TSTCLK1 This bit is now in the BRGP register on the MC68PM302 see section 4 3 2 Baud Rate Gen erator Pins Register BRGP Three State RCLK1 TSRCLK1 This bit is now in the BRGP register on the MC68PM302 see section 4 3 2 Baud Rate Gen erator Pins Register BRGP Disable BRG1 DISBRG1 This bit has been removed since the BRG1 pin was removed 2 4 2 MC68PM302 System Clock Generation Figure 2 3 the MC68PM302 system clock schematic shows the IMP clock synthesizer The block includes an on chip oscillator a clock synthesizer and a low power divider which allows a comprehensive set of options for generating the system clock The choices offer many opportunities to save power and system cost without sacrificing flexibility and control In addition to performing frequency multiplication the PLL block can also provide EXTAL to CLKO skew elimination and dynamic low power divides of the output PLL system clock Clock source and default settings are determined during the reset of the IMP The MC68PM302 decodes the MODCLK and VCCSYN pins and the value of these pins deter mines the initi
75. force the TXD line high idle Data already in the trans mit shift register will not be transmitted ENT may be set or cleared regardless of whether serial clocks are present MODE1 MODE0 Channel Mode 00 HDLC 01 Asynchronous UART 10 UART 16550 only on SCC2 when the PCMCIA is enabled 11 BISYNC Promiscuous Transparent and Autobaud 4 3 4 SCC Data Synchronization Register DSR Each DSR is a 16 bit memory mapped read write register DSR specifies the pattern used in the frame synchronization procedure of the SCC in the synchronous protocols In the UART protocol it is used to configure fractional stop bit transmission After reset the DSR defaults to 7E7E two FLAGs thus no additional programming is necessary for the HDLC protocol For BISYNC the contents of the DSR should be written before the channel is enabled 15 8 7 0 SYN2 SYN1 4 3 5 Buffer Descriptors Table Data associated with each SCC channel is stored in buffers Each buffer is referenced by a buffer descriptor BD BDs are located in each channel s BD table located in dual port RAM There are two such tables for each SCC channel one is used for data received from the serial line the other is used to transmit data The format of the BDs is the same for each SCC mode of operation HDLC UART UART 16550 BISYNC and transparent and for MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fre
76. freescale com Freescale Semiconductor cJm unications Processor CP The structure of the autobaud command descriptor for the autobaud process is shown in Table 4 4 The first word of the descriptor or the status word is updated after every character is received Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FE M2 M1 EOT OV CD 2 LOOKUP TABLE SIZE 4 FUNCTION CODE 8 LOOKUP TABLE POINTER Table 4 4 Autobaud Command Descriptor FE Framing Error Bit 10 If this bit is set a character with a framing error was received A framing error is detected by the autobaud controller when no STOP bit is detected in the received data FE will be set for a 9 bit character 8 bits parity if the parity bit is 0 NOTE The user must clear this bit when it is set M2 Match Character2 Bit 9 When this bit is set the character received matched the User Defined Character 2 The received character is written into the receive control character register RCCR M1 Match Character1 Bit 8 When this bit is set the character received matched the User Defined Character 1 The received character is written into the receive control character register RCCR EOT End Of Table bit 3 When this bit is set the autobaud controller measured start length exceeded the maxi mum start length of the last entry in the lookup table lowest baud rate NOTE The user must clear this
77. from the TIN pin 4 3 2 Baud Rate Generator Pins Register BRGP This 8 bit register controls 1 enabling the divide by 2 prescaler for the baud rate generator from the TIN1 pin and 2 options for three stating the BRG1 TCLK1 and RCLK1 pins MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP BRGP Base 8EE 15 14 13 12 11 10 9 8 TSTOLKI TSROLK1 TSTBRGI BRGDIV RES RES RES RES Sea 0 0 0 0 0 0 0 TSTBRG1 Disable BRG1 0 When the PCMCIA interface is not enabled the BRG1 clock is driven on the BRG1 pin 1 When the PCMCIA interface is not enabled the BRG1 output is three stated In order to allow the baud rate generator output clocks which will be driven on TCLK1 and RCLK1 when an internal baud rate generator is used for SCC1 to be disabled the following bits are provided TSRCLK1 0 RCLK1 is driven on its pin when SCC1 RCLK is the baud rate generator output 1 RCLK1 is three state TSTCLK1 0 TCLK1 is driven on its pin when SCC1 RCLK is the baud rate generator output 1 TCLK1 is three state BRGDIV Enables and disables the divide by two block between the TIN1 pin and the BRG1 pres caler input 0 The divide by two block is disabled 1 The divide by two block is enabled 4 3 3 SCC Mode Register SCM Each SCC has a mode register The functions of bits 5 0 are common to each protocol The function
78. indicate to external devices that the processor has stopped An example of a double fault condition is the occurrence of a bus error followed by a second bus error during the bus error ex ception stacking process This signal is asserted with the RESET signal to cause a total IMP system reset If BERR is asserted with the HALT signal a retry cycle is performed PC_A3 BERR PCMCIA Address 3 Bus Error When PC_EN 0 PCMCIA is disabled this pin functions as the input signal BERR which informs the bus master that there is a problem with the cycle currently being executed MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description This signal is generated externally however an internal BERR signal can be asserted by the on chip hardware watchdog bus timeout because of no DTACK by the chip select logic address conflict or write protect violation or by external circuitry If BERR is assert ed with the HALT signal a retry cycle is performed 6 1 4 IMP Address Bus Pins A23 A1 The address bus pins are shown in Figure 6 4 lt q 023 A1 Figure 6 4 Address Bus Pins A23 A1 form a 24 bit address bus when combined with WEH UDS A0 The address bus is a bidirectional three state bus capable of addressing 16M bytes of data including the IMP internal address space It provides the address for bus operation during all cycles excep
79. is sampled as MODCLK at reset After reset MODCLK PA12 is a general purpose O pin Table 6 4 Default Operation Mode of the PLL PLL Multi factor EXTAL freq CLKIN to the PM302 System VCCSYN MODCLK MF 1 examples PLL Clock 0 X Disabled x EXTAL EXTAL 1 0 Enabled 4 4 192MHz 4 192MHz 16 768 MHz 1 1 Enabled 401 32 768KHz 32 768KHz 13 14 MHz VCCSYN Analog PLL Circuit Power This pin is dedicated to the PM302 analog PLL circuits and determines whether the PLL is enabled or not When this pin is connected to Vcc the PLL is enabled and when this pin is connected to ground the PLL is disabled The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the Vcc power rail Vocsyn Should be bypassed to GND by a 0 1uF capacitor located as close as possible to the chip package 6 1 2 Clock Pins The clock pins are shown in Figure 6 2 EXTAL XTAL CLKO XFC MODCLK VCCSYN GNDSYN Figure 6 2 Clock Pins EXTAL External Clock Crystal Input This input provides two clock generation options crystal and external clock EXTAL may be used with XTAL to connect an external crystal to the on chip oscillator and clock gen erator If an external clock is used the clock source should be connected to EXTAL and MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Descript
80. memory accesses into the 68000 bus This mechanism will enable the card designer to use memories SRAM DRAM etc or peripher als on the 68000 bus and access them by the host The 68000 core or the PC should pro gram the starting 68000 address of the memory or peripheral into these registers A25 will distinguish between the two base registers When A25 1 CMBAR1 will be selected and when A25 0 CMBAR2 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller NOTE Since the PCMCIA attribute space accesses are only 8 bits this 16 bit register address will be 2 bytes on even addresses only V Valid Bit This bit indicates that the contents of the base register is valid The PCMCIA common memory space cycle will not be transferred into the 68000 bus until the V bit is set 0 This register base address is invalid 1 This register base address is valid BA12 23 Base Address The base address field should contain the upper address bits of the I O memory address on the 68000 bus The lower address bits will be taken from the PCMCIA address lines NOTE The 2Kbyte block defined by this base address should not con tain any internal addresses internal dual port RAM internal reg isters etc if it is desired to use the fast mode accesses Fast mode accesses Fast Mode 1 to internal memory locations will result in erratic operation FC0O 2
81. mode 4 3 10 HDLC Controller The functionality of the HDLC controller has not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual 4 3 10 1 HDLC MEMORY MAP When configured to operate in HDLC mode the IMP over lays the structure shown in Table 4 9 onto the protocol specific area of that SCC parameter RAM Refer to System Configuration Registers on page 4 for the placement of the three SCC parameter RAM areas and to Table 4 1 for the other parameter RAM values MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP Table 4 9 HDLC Specific Parameter RAM Address Name Width Description SCC Base 9C RCRC_L Word Temp Receive CRC Low SCC Base 9E RCRC H Word Temp Receive CRC High i SCC Base AO C_MASK_L Word Constant F0B8 16 Bit CRC DEBB 32 Bit CRC SCC Base A2 C_MASK_H Word Constant XXXX _16 Bit CRC 20E3 32 Bit CRC SCC Base A4 TCRC_L Word Temp Transmit CRC Low SCC Base A6 TCRC_H Word Temp Transmit CRC High SCC Base A8 DISFC Word Discard Frame Counter SCC Base AA CRCEG Word CRC Error Counter SCC Base AC ABTSC Word Abort Sequence Counter __ SCC Base AE NMARG Word Nonmatching Address Received Counter SCC Base BO RETRC Word Frame Retransmission Counter SCC Base B2 MFLR Word Max Frame Length Register SCC Base B4 MAX_cnt
82. occurs on the respective TIN1 or TIN2 pin TCR1 and TCR2 appear as memory mapped read only regis ters to the user 3 7 1 4 Timer Counter TCN1 TCN2 TCN1 and TCN2 are 16 bit up counters Each is memory mapped and can be read and written by the user A read cycle to TCN1 and TCN2 yields the current value of the timer and does not affect the counting operation 3 7 1 5 Timer Event Registers TER1 TER2 Each TER is an 8 bit register used to report events recognized by any of the timers On recognition of an event the timer will set the MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc appropriate bit in the TER regardless of the corresponding interrupt enable bits ORI and CE in the TMR TER1 and TER2 which appear to the user as memory mapped registers may be read at any time A bit is cleared by writing a one to that bit writing a zero does not affect a bit s value 7 2 1 0 CAP Capture Event The counter value has been latched into the TCR The CE bits in the TMR are used to enable the interrupt request caused by this event REF Output Reference Event The counter has reached the TRR value The ORI bit in the TMR is used to enable the interrupt request caused by this event Bits 7 2 Reserved for future use 3 7 2 Timer 3 Software Watchdog Timer A watchdog timer is used to protect against system failures by provid
83. operating modes is specified in Section 7 Elec trical Characteristics MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgate senicenducter wid amp tG lt and Internal Memory Map Table 2 3 IMP Low Power Modes IMP PLL Enabled Current a Oscillator PLL Clock Wake Up Consumption mare tas st cderane Approximate STOP Not Active Not active Not active Chua ior lt 0 1mA Sop econ No DOZE Active Not active Not active ao pee About 500uA Stee oon No stano 67 nave MAE noraowe SSPE noorena SRE ae ERS SNORMAL Active Acte df Active Low gRPends on Write to DF3 0 Full 2 4 4 1 1 STOP Mode In STOP mode all parts of IMP are inactive and the current con sumption is less than 0 1mA Both the crystal oscillator and the IMP PLL are shut down Because both the oscillator and the PLL must start up the wake up time takes 70000 EXTAL clocks for example 70000 cycles of 32 768 kHz crystal will take about 2 2 seconds The STOP mode is entered by executing the STOP instruction with the LPMO 1 bits in the IOMCR register set to 11 Refer to 2 4 4 2 2 Entering the STOP DOZE STAND_BY Mode for an example instruction sequence for use with the STOP instruction 2 4 4 1 2 DOZE Mode In DOZE mode the oscillator is active in the IMP but the IMP PLL is shut down The current consumption depends on the frequency of the external crystal but is on
84. or PCMCIA Address Interrupt Acknowledge Port B PC_A25 IACK6 PB1 O PORTE PCMCIA Card Enable 2 Interrupt Acknowledge Port B PC_CE2 ACK1 PB2 O PCMCIA Status Change Bus Request PC_STSCHG BR O ROMOIA or PCMCIA Wait Bus Grant PC_WAIT BG VO PCMCIA Output Enable Bus Grant Acknowledge PC_OE BGACk I O PCMCIA Ready PCMICA Interrupt Request Read Write PC_RDY PC_IREQ RW I O PCMCIA REG Upper Data Strobe Address 0 PC_REG UDS AO 1 0 PCMCIA or PCMCIA Card Enable 1 Lower Data Strobe Data Strobe PC_CE1 LDS DS O 68k Bus PCMCIA Address Freeze PC_A5 FRZ I4 PCMCIA Address Autovector PC_A4 AVEC I PCMCIA Address Bus Error PC_A3 BERR I MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc Table 6 3 IMP Peripheral Pins Group Signal Name Mnemonic See Note 1 0 Timer 1 Input Port B TIN1 PB3 O PCMCIA Address Timer 1 Output Port B PC_A10 TOUT1 PB4 I O TIMER pins Threestate Timer 2 Input Port B TRIS TIN2 PB5 V O PCMCIA Enable Timer 2 Output Port B PC_EN TOUT2 PB6 O Watchdog Port B WDOG PB7 O PC_DMA PCMCIA DMA Request IDMA Request Port B DREQ PC_DREQ PB8 l O Port B Ring Indicate PB9 RI O Port B I O Port B PB10 O Port B PB11 O PCMCIA Low Data Bus PC_DO I O IME Sang PCMCIA Low Data Bus Function Codes PC_D3 1 FC2 0 O PCMCIA
85. peripheral BES Bus Error Source This bit indicates that the IDMA channel terminated with an error during the read cycle BED Bus Error Destination This bit indicates that the IDMA channel terminated with an error during the write cycle DONE Normal Channel Transfer Done This bit indicates that the IDMA channel has terminated normally 3 4 2 Interface Signals When the PCMCIA interface is disabled the IDMA channel has three dedicated control sig nals DMA request DREQ DMA acknowledge DACK and end of IDMA transfer DONE The IDMA s use of the bus arbitration signals is described in the MC68302 Users Manual IDMA Operational Description MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB NOTE For details on the IDMA programming and bus operation please refer to Section 3 of the MC68302 Users Manual 3 5 INTERRUPT CONTROLLER The IMP interrupt controller accepts and prioritizes both internal and external interrupt requests and generates a vector number during the CPU interrupt acknowledge cycle 3 5 1 Interrupt Controller Key Differences from the MC68302 Since the function code pins are not connected externally unless the PCMCIA interface is disabled or the PGA Package is used the 68PM302 should be programmed to Dedicated Mode and to internally generate the vectors for Levels 1 6 and 7 An external de
86. reception for use by the close BD mechanism See 16550 Rx Buffer Descrip tor Rx BD on page 42 NOTE In this case the PC is transmitting to the 68000 core Rx Divider This 4 bit value is loaded into a 4 bit countdown counter This counter divides the BRG2 input clock The 16550 emulation receive FIFO requests the RISC controller to poll its Tx BD When the BD is not empty it will transfer data from memory into the FIFO when the counter reaches zero and the FIFO is not full This mechanism slows down the transfer rate and emulates the PC interrupt rate as if the data transfer was done serially This counter is also used for the 16550 Rx FIFO time out interrupt emulation NOTE In this case the 68000 is transmitting to the PC core TSDE Transmitter Slowdown Enable When set this bit enables the transmitter slow down mechanism When cleared the transmit counter is used only for IDLE emulation and the transfer rate is as fast as the RISC controller and the PC can operate NOTE In this case the PC is transmitting to the 68000 core RSDE Receiver Slowdown Enable When set this bit enables the receiver slow down mechanism When cleared the receive counter is used only for FIFO time out interrupt emulation and the transfer rate is as fast as the RISC controller and the PC can transfer In this case transfers will probably be lim ited by PC software rather than the RISC and SDMA channels on the 68K bus The IMP transmitter will p
87. recommended Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces Attention to proper PCB layout and by passing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Voc and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins 7 4 2 Power Dissipation Considerations Power dissipation is a key issue in portable applications Some of the factors which affect current consumption are described in this section Most of the current consumed by CMOS devices is alternating current AC which is charging and discharging the capacitances of the pins and internal nodes Therefore the total current consumption is the sum of these in ternal and external currents This current consumption is described by the formula I CVf whereC node pin capacitance V voltage swing and f frequency of node pin toggle Example For a pin loaded with a 50pF capacitance operating at 5 5V and with a toggling rate of 10MHz the current consumption is T 50 10 7 5 5 10 10 2 75mA The maximum internal current value I c max reflects the maximum possible switching of the internal buses which is not necessarily a real application case The typical internal cur rent value Iccl typ reflects the average switching of t
88. same write cycle First program PC_DREQEN 1 then PC STR 1 Software sequence will be provided If pin PC_EN 0 the DREQ_ to the IDMA is connected to PA13 DREQ _ pin and this pin acts as PB8 parallel IO or Interrupt if PIT is disabled 5 3 11 4 6 PCMCIA DMA Data Register PCDMAD Mapped at Address Base 878 The PCDMAD is a 16 bit register that buffers the data between the PC Host and the PC Card on PC DMA transfers PCMCIA 8 bit transfer PC_CE2 1 pc_CE1 0 writes data to D7 0 of PCDMAD Register If PCDSWP is set the DMA operand address for PCDMAD has to be base 878 if reset the DMA operand address for the PCDMAD has to be base 879 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 6 SIGNAL DESCRIPTION This section defines the MC68PM302 signals Figure 6 1 For more detail on each signal refer to the paragraph named for the signal 6 1 IMP PINS Some of the pins allotted to the IMP portion of the MC68PM302 are multiplexed between the normal IMP signals and the PCMCIA signals The pin multiplexing is organized so the user has all the corresponding IMP pins available when not using PCMCIA In fact when not using the PCMCIA interface additional PIO ports are available The following signals are listed in two functional groups because they are sampled at reset and change function after reset TRIS TIN2 PB5 BUSW PC_ABUF MODCLK BRG3 PA12 PC_EN
89. strength This reg ister is mapped in the 68000 bus space at address 0F8 If the 68000 bus is set to 8 bits BUSW grounded at reset during 8 bit accesses changes to the IPLCR will take effect in the IMP PLL after loading the high byte of IPLCR the low byte is written first The WP bit in IPLCR is used as a protect mechanism to prevent erroneous writing When this bit is set further accesses to the IPLCR will be blocked IMP PLL and Clock Control Register IPLCR 0F8 15 14 13 12 11 10 9 8 IPLWP CLKOMODO 1 PEN MF 11 MF10 MP9 MF8 RESET VOCSYN 0 0 0 VCCSYN 0 0 0 vende 7 6 5 4 3 2 1 0 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MFO RESET VOCSYN VCCSYN Menai 0 0 ODAK 0 0 MODCLK MODCLK Read Write MF 11 0 Multiplication Factor These bits define the multiplication factor that will be applied to the IMP PLL input frequen cy The multiplication factor can be any integer from 1 to 4096 The system frequency is MF bits 1 x EXTAL The multiplication factor must be chosen to ensure that the re sulting VCO output frequency will be in the range from 10 MHz to the maximum allowed clock input frequency e g 20 MHz for a 20 MHz IMP The value 000 results in a multiplier value of 1 The value FFF results in a multiplier value of 4096 Any time a new value is written into the MF11 MFO bits the IMP PLL will lose the lock condition and after a delay of 2500 EXTAL clocks will relock When the IMP PLL loses its lock condition all the c
90. support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters inc
91. that consists of crystal oscillator drive circuit capa ble of driving either an external crystal or accepting an oscillator clock a PLL clock synthe sizer capable of multiplying a low frequency clock or crystal such as a 32 kHz watch crystal up to the maximum clock rate of each processor and a low power divider which allows dynamic gear down and gear up of the system clock for each processor on the fly On Chip Clock Synthesizers with output system clocks Oscillator Drive Circuits and Pins PLL Clock Synthesizer Circuits with Low Power Output Clock Divider Block Low Power Control Of IMP Slow Go Modes using PLL Clock Divider Blocks Varied Low Power STOP Modes for Optimizing Wake Up Time to Low Power Mode Power Consumption Stand By Doze and STOP 2 4 1 PLL and Oscillator Changes to IMP The oscillator that was on the MC68302 has been replaced by the new clock synthesizer described in this section The registers related to the oscillator have been either removed or changed according to the description below Several control bits are still available but have new locations The low power modes on the MC68302 have changed completely and will be discussed later in 2 4 4 1 IMP Low Power Modes 2 4 1 1 CLOCK CONTROL REGISTER The clock control register address FA is not implemented on the MC68PM302 This register location has been reassigned to the IOMCR and ICKCR registers The clock control register bits have been reassigned as
92. the CLKOUT output of the PLL CLKODMO0 1 CLKO Drive Mode 0 1 These bits control the output buffer strength of the CLKO pin Those bits can be dynami cally changed without generating spikes on the CLKO pin Disabling CLKO will save pow er and reduce noise 00 Clock Out Enabled Full Strength Output Buffer 01 Clock Out Enabled 2 3 Strength Output Buffer 10 Clock Out Enabled 1 3 Strength Output Buffer 11 Clock Out Disabled CLKO is driven high by internal pullup NOTE These IMP bits are in a different address location than in the MC68302 where they are located at address FA bits 15 14 IPLWP IMP PLL Control Write Protect Bit This bit prevents accidental writing into the IPLCR After reset this bit defaults to zero to enable writing Setting this bit prevents further writing excluding the first write that sets this bit 2 4 3 5 IMP INTERNAL CLOCK SIGNALS The following paragraphs describe the IMP internal clock signals 2 4 3 5 1 IMP System Clock The IMP system clock is supplied to all modules on the IMP with the exception of the BRG clocks which are connected directly to the VCO output with the PLL enabled The IMP can be programmed to operate with or without IMP PLL If IMP PLL is active the system clock will be driven by PLL clock divider output If IMP PLL is not active the system clock will be driven by the PLL input clock CLKIN 2 4 3 5 2 BRG Clock The clock to the BRGs can be supplied from the
93. the order of 500 ua In DOZE mode the IMP is shut down The wake up time is 2500 cycles of the external crystal for example 2500 cycles of 32 768 kHz crystal will take about 80 milliseconds Doze mode has faster wake up time than the STOP mode at the price of higher current consumption The DOZE mode is entered by executing the STOP instruction with the LPM1 0 bits in the IOMCR register set to 10 Refer to 2 4 4 2 2 Entering the STOP DOZE STAND_BY Mode for an example instruction sequence for use with the STOP instruction 2 4 4 1 3 STAND_BY Mode In STAND_BY mode the oscillator is active and the IMP PLL if enabled is active but the IMP clock is not active and the IMP is shut down Current con sumption in STAND BY mode is less than less than 5mA The wake up time is a few IMP system clock cycles The STAND_BY mode is entered by executing the STOP instruction with the LPM1 0 bits in the IOMCR register set to 01 Refer to 2 4 4 2 2 Entering the STOP DOZE STAND_BY Mode for an example instruction sequence for use with the STOP instruction In STAND BY mode the PCMCIA interface is active and any access on the PCMCIA inter face will cause the IMP to come out of STAND BY mode The STAND_BY mode is useful in applications which have time slots with no activity and require a minimal wake up time before IMP returns to NORMAL or SLOW GO mode 2 4 4 1 4 SLOW_GO Mode In the SLOW GO mode the IMP is fully operational but the IMP PLL divider
94. the source read BES or the destination write BED the channel does not generate an interrupt to the IMP interrupt controller The appropriate bit remains set in the CSR 1 Ifa bus error occurs during an operand transfer either on BES or BED the channel generates an interrupt to the IMP interrupt controller and sets the appropriate bit BES or BED in the CSR NOTE An interrupt will only be generated if the IDMA bit is set in the IMR REQG Request Generation 00 Internal request at limited rate limited burst bandwidth set by burst transfer BT bits 01 Internal request at maximum rate one burst 10 External request burst transfer mode DREQ level sensitive 11 External request cycle steal DREQ edge sensitive NOTE The settings 10 and 11 will not work since the DREQ pin is not present SAPI Source Address Pointer SAP Increment 0 SAP is not incremented after each transfer 1 SAP is incremented by one or two after each transfer according to the source size SSIZE bits and the starting address DAP Destination Address Pointer DAP Increment 0 DAP is not incremented after each transfer 1 DAP is incremented by one or two after each transfer according to the destination size DSIZE bits and the starting address MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB SS IZE Source Size 00 Re
95. to 414 nF The proper available value for Cxpc is 390 nF 3 In order to get higher range higher crystal frequency can be used i e 50 KHz in this case Minimum Cyc is 667 x 380 253 nF Maximum Cy c is 401 x 970 390 nF Therefore 253 nF lt CxFC lt 390 nF 7 6 3 IMP DC Electrical Characteristics NMSI1 in IDL Mode Characteristic Symbol Min Max Unit Condition Input Pin Characteristics L1CLK L1SY1 L1RXD L1iGR Input Low Level Voltage Vit 10 20 V of Vpp Input High Level Voltage Vin Vpp 20 Vpp 10 Input Low Level Current te 10 uA Vin Vss Input High Level Current My 10 uA Vin Vpp Output Pin Characteristics L1TXD SDS1 SDS2 L1RQ Output Low Level Voltage VoL 0 1 0 V lo 5 0 mA Output High Level Voltage VoH Vpp 1 0 Vpp V lon 400 uA MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 6 4 AC Electrical Specifications IMP Bus Master Cycles see Figure 7 2 Figure 7 3 Figure 7 4 and Figure 7 5 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol 5 0V 5 0 V 5 0 V Unit Min Max Min Max Min Max 6 Clock High to FC Address Valid tcuFcapv 0 45 0 40 0 30 ns Clock High to Address Data Bus High Im 7 padance Maximum 3 cHapz
96. to deliver to the PC it prepares a buffer descriptor with associated data buffer The RISC controller will deliver the data buffer characters into the receive buffer register An interrupt will be gener ated to the PC if the receive data available interrupt is enabled and the ready bit is set Also the 68000 core may set the FE and P error bits in the transmit buffer descriptor TxBD and the RISC will transfer them with the data to the FIFO or the line status register To slow down the transfer rate to the PC and emulate the same rate as a serial 16550 the PC interrupt request rate may be slowed by programming the EMR RX divider bits see 4 4 5 2 16550 Emulation Mode Register EMR MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP 4 4 4 1 11 Transmit Holding Register THR When the PC writes to the transmit holding register the RISC controller receives a request from the 16550 emulation logic The RISC controller when servicing the request will read the register and will transfer the data into the Rx data buffer When the RISC reads the register the transmit holding register empty flag is set To slow down the transfer rate and emulate the same rate as the serial 16550 the RISC controller request may be delayed by programming the EMR TX divider bits see 4 4 5 2 16550 Emulation Mode Register EMR 4 4 4 1 12 Scratchpad Register SCR Th
97. to the STSCHG pin This chapter is structured to cover first the three memory space accesses specified by the PCMCIA committee the attribute I O and common memory spaces The low power modes and wake up options are covered next followed by the descriptions of all of the PCMCIA controller registers Finally the PCMCIA card software initialization procedures are covered MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc PCMCIA CIS CSN lt 2 fe CARD CONFIGURATION MEMORY REGISTERS PC DMA DATA REGISTER Beles MODE STATUS AND MASK 68000 BUS SPACEBASE ADDRESS 1 COMMON MEMORY SPACEBASE ADDRESS2 ADDRESS COMMON CSN MEMORY BERR PC DREQ PC STSCHG BCLR DTACK eee BGACK PC RDYIREQ BG PC REG BR PC CET 2 PC WE AIA PC OE AS UDS LDS A0 PC IOWR DACK DONE PC_IORD pees es PC A35 DREQ PC_A11 0 DOS PC D045 PERIPHERAL PC_D0 7 BUS Figure 5 2 PCMCIA Controller Block Diagram 5 1 1 Attribute Memory Accesses Attribute memory space accesses are used to access the configuration registers and the card information structure CIS Attribute memory accesses are generated when the PC as serts the PC_REG pin as shown in Table 5 1 and Table 5 2 As shown in Table 5 3 A25 selects between accessing the CIS with the CIS base address register CISBAR and direct MC68PM302 REFERENCE MANUAL For More Information On
98. up resistors see Pullup Control Register PUCR on page 20 Port D may be accessed through the Port D data register PDDAT When PDDAT is read the state of the input pins is read 3 6 4 Port Registers The I O port consists of three memory mapped read write 16 bit registers for port A and three memory mapped read write 16 bit registers for port B Refer to Figure 3 2 for the I O port registers The reserved bits are read as zeros Port A Control Register PACNT 15 14 13 12 11 10 9 8 7 6 CA CA CA CA CA CA CA CA CA CA CA CA CA CA CA CA 0 1 0 1 Peripheral oa A wo N Oo Port A Data Direction Register PADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA 0 Input 1 Output MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc Port A Data Register PADAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PA PA PA PA PA PA PA PA PA PA PA PA PA PA PA PA a oO Port B Control Register PBCNT 15 8 7 6 5 4 3 2 1 0 RESERVED CB CB CB CB CB CB CB CB 0 l 0 1 Peripheral Port B Data Direction Register PBDDR 15 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DB DB DB DB DB DB DB DB
99. uses only the most sig nificant bits to cause an address match within its block size Even though A23 20 are sig nals are not available they are driven internally by the core or driven to zeroes in disable CPU mode or when HALT has been asserted by an external master 2 3 SYSTEM CONFIGURATION REGISTERS Four entries in the M68000 exception vectors table located in low RAM are reserved for the addresses of system configuration registers see Table 2 1 These registers have seven addresses within 0FO 0FF The MC68PM302 uses one of the IMP 32 bit reserved spaces for 3 registers added for the MC68PM302 These registers are used to control the MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freagsgale sxenicenducter wid amp G lt and Internal Memory Map PLL clock generation and low power modes See 2 4 Clock Generation and Low Power Control Table 2 1 System Configuration Registers Address Name Width Description Reset Value 0FO PITR 16 Periodic Interrupt Timer Register 0000 0F2 BAR 16 Base Address Register BFFF 0F4 SCR 24 System Control Register 0000 OF 0F7 IWUCR 8 IMP Wake Up Control Register 00 0F8 IPLCR 16 IMP PLL Control Register 0FA IOMCR 8 IMP Operations Mode Control Register 00 0FB IPDR 8 IMP Power Down Register 00 0FC RES 32 Reserved 2 4 CLOCK GENERATION AND LOW POWER CONTROL The MC68PM302 includes a clock circuit
100. volt ages to his high impedance cir cuit Reliability of operation is Che ane Lemperalute Range Ta MC68PM302 0 to 70 C enhanced if unused inputs are tied MC68PM302C 40 to 85 to an appropriate lodie voltage lev el e g either GND or Vpp Storage Temperature Range Tstg 55 to 150 C 7 2 THERMAL CHARACTERISTICS Tj Ta Pp e0ja Pp Voo e Ipp Pro where Pio is the power dissipation on pins MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 3 POWER CONSIDERATIONS The average chip junction temperature Ty in C can be obtained from TJ TA PD qJA 1 where Ta Ambient Temperature oC QJA Package Thermal Resistance Junction to Ambient C W PD PINT PI O PINT IDD x VDD Watts Chip Internal Power P o Power Dissipation on Input and Output Pins User Determined For most applications Pio lt 0 3 e Pint and can be neglected If Pio is neglected an approx imate relationship between Pp and Ty is Pp K I Ty 273C 2 Solving equations 1 and 2 for K gives K Pp TA 273eC qua Pp2 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known TA Using this value of K the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of Ta
101. way 2 Issue the ENTER HUNT MODE command to the SCC This ensures that an open buffer descriptor is closed 3 Setup all the autobaud parameters in the autobaud specific parameter RAM shown in MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Table 4 3 the autobaud command descriptor shown in Table 4 4 and the lookup table shown in Table 4 4 Of these three areas the autobaud controller only modifies the autobaud specific parameter RAM and the first word of the autobaud command de scriptor during its operation 4 Write the SCON to configure the SCC to use the baud rate generator clock of 16x the maximum supported baud rate A typical value is 4000 assuming a 1 8432 MHz clock rate on TIN1 and a maximum baud rate of 115 2K but this can change depending on the maximum baud rate and the EXTAL frequency 5 Write the DSR of the SCC with the value 7FFF in order to detect the START bit 6 The host initiates the autobaud search process by issuing the Enter_Baud_Hunt com mand 7 Write the SCM of the SCC with 1133 to configure it for BISYNC mode with the REVD and RBCS bits set software operation mode and the transmitter disabled After a few characters have been received the transmitter can be enabled and the software echo function may be performed after issuing the RESTART TRANSMIT command In general the autobaud controller u
102. will be generated if enabled The inter rupt will be generated to the PC through the PTIE bit in the PCHER if the TIEn bit is set in the PCMR The five bit counter preset is programmed through the TValue bits in the PCMR The prescaler value is programmed in the TPres bits in the PCMR The PCMCIA bus watch dog timer signal source is the IMP system clock NOTE The features described in the above three paragraphs also apply for CIS accesses in attribute space NOTE All PCMCIA locations registers CIS memory etc that can be accessed by the host may also be accessed by the 68000 core Power Down Options The PC can place the MC68PM302 into low power mode by setting the power down PwrD wn bit in the CCSR When the PC sets the PwrDwn bit the PCMCIA controller will generate an interrupt to the 68000 core if enabled through the INTRL bits in the PCMR The IMP interrupt routine should place the devices on the card in a low power mode and then place itself into one of the low power modes listed in Table 2 3 NOTE The host should not change the PwrDwn bit in the CCSR while the card is busy i e The RDY Bsy bit in the PRR is zero If the 68000 core is in a stand by mode when the PwrDwn bit is set the 68000 core will come out of stand by mode to process the PwrDwn interrupt as above Setting the PwrDwn bit will reset the RDY Bsy bit in the pin replacement register PRR to zero This bit will be set to one RDY when the IMP comp
103. will disable the pulldowns 0 PC_D7 0 are pulled down only if PC_EN 1 1 All pulldowns are disabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc PUC1 This bit when cleared will enable a 100K ohm pulldown resistor for each of the PCMCIA data pins Setting this bit will disable the pulldowns 0 PC_D15 8 are pulled down only if PC_EN 1 1 All pulldowns are disabled PUCO Reserved 5 3 PROGRAMMER S MODEL The PCMCIA controller contains a number of registers described in the following para graphs Those registers can be accessed by the host and the 68000 core 5 3 1 PCMCIA Controller Accesses 5 3 2 PCMCIA Mode Register PCMR PCMR PCMCIA Address A25 1 20 68000 Address BAR 8C0 31 30 29 28 27 26 25 24 RESET 0 0 0 0 0 0 0 0 PCMCIA Address A25 1 22 68000 Address BAR 8C1 23 22 21 20 19 18 17 16 TValue TPres Ten RESET 0 0 0 0 0 0 0 0 PCMCIA Address A25 1 24 68000 Address BAR 8C2 15 14 13 12 11 10 9 8 RISDIS AINC2 AINC1 Res INTRL 16bit ABUF RESET 0 0 0 0 0 0 0 0 PCMCIA Not Accessible 68000 Address BAR 8C3 7 6 5 4 3 2 1 0 Res Res PC_DREQEN PCDSWP PCDDIR IDOI PCSTR RESET 0 0 0 0 0 0 0 0 Read Write Aro IDL Arbitration IDLE Time These bits are used to indicate when to release the 68000 bus after a common memory space transfer has terminated MC68PM302 REFERENCE MAN
104. 0 In Disable CPU mode accesses by an external master to the IMP RAM and registers may be asynchronous or synchronous to the IMP clock See the SAM and EMWS bits in the SCR for details In Disable CPU Mode the PM302 can interrupt an external CPU with the CSO IOUT2 signal only IOUT1 and IOUTO have been deleted IOUT2 is asserted for interrupts of Level 4 6 7 which are generated by internal Blocks VGE Vector Generation Enable This bit should be cleared unless the PCMCIA interface is disabled Otherwise the MC68PM302 cannot decode an interrupt acknowledge cycle without the function code pins 0 In disable CPU mode the IMP will not output interrupt vectors during interrupt ac knowledge cycles 1 Indisable CPU mode the IMP will output interrupt vectors for internal level 4 inter rupts and for levels 1 6 and or 7 as enabled in the interrupt controller during in terrupt acknowledge cycles 3 8 3 Bus Arbitration Logic Both internal and external bus arbitration are discussed in the following paragraphs 3 8 3 1 Internal Bus Arbitration In disable CPU mode or when the PCMCIA interface is disabled the IMP bus arbiter sup ports three bus request sources in the following standard priority 1 External bus master BR pin if the PCMCIA interface is disabled or in Disable CPU mode 2 SDMA for the SCCs six channels 3 IDMA one channel 4 PCMCIA Controller In the enable CPU mode if the PCMCIA Interface is enabled
105. 1 Pc_a11 TACK7 PBo TACK7 PBo TACK7 PBO TACK7 PBO PC_A10 TOUTT PB4 PC_A10 PC_A10 PC_A10 PC_A10 TOUT PB4 TOUTT PB4 TOUTTPB4 TOUTT PB4 PC_A9 PC A6 PDI14 PC A9 PC A9 PC A9 PC_AQ PDI14 PDI14 PDI14 PDI14 PDT 1 PC_A6 PC_A6 PC_AG6 PC_A6 PDI11 PDI11 PDI11 PDI11 PC_A5 FRZ PC_A5 PC_A5 PC_A5 PC_A5 FRZ FRZ PC_A4 AVEC PC_A4 PC_A4 PC_A4 PC_A4 AVEC AVEC PC_A3 BERR PC_A3 PC_A3 PC_A3 PC_A3 BERR BERR BERR BERR PORE ONO POA be PEAS PEM Ppito pois Poito Ppie PDI10 PDI8 PDI10 PDIB PC_DREQ DREG PBS Fe DREQ Fe DRE BE Dre PE DEO ppg PB8 PB8 PB8 PC_IORD DREG PA13 PC_IORD PC_IORD PC_IORD PC_IORD DREQ PA13 DREQ PA13 DREQ PA13 DREG PA13 IPLORQT BR IPLoRa1 IPLOROt BR BR IPLOARGT IPLORQT IPLo IRAT IPLOARGT TPLIIROG BGACK POROS IPL1 IRG6 BGACK BGACK IPL1 IRG6 POMOS POROS POROS TPL2 IRQ7 BG TPL2IRQ7 IPL2 IRQ7 BG BG TPL2IRQ7 IPL2 IRQ7 IPL2ARQ7 IPL2 RQ7 WEH UDS A WEH AO WEH AO UDS AO UDS AO WEF WEF WEF WEH WEL LDS DS WEL WEL DSDS LDS DS WEL WEL WEL WEL OE RW OE OE RW RW OE OE OE OE FC2 FCO PGA FC2 FCO A FC2 FCO FC2 FC0 FC2 FCO FRZ PGA FRZ FRZ FRZ FRZ AVEC PGA z AVEC AVEC AVEC AVEC IAC PGA IAC 7 IAC i IAC IAC This pin is not used in 8 bit mode MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 6 3 POWER AND GROUND PINS The
106. 1 sync Inactive Before 4th L1 CLK 0 0 0 ns 267 Edge Active Delay from L1CLK Rising 0 75 0 65 0 50 ns L1TxD to High Impedance from L1CLK 268 Rising Edge see Note 2 0 50 0 42 0 34 ns 269 L1RxD Setup Time to L1CLK Falling Edge 50 TA 42 E 34 T ns 270 L1RxD Hold Time from L1CLK Falling 50 42 an 34 ns Edge 271 Time Between Successive IDL syncs 20 20 20 LICLK 272 L1RQ Valid before Falling Edge of L1SY1 1 1 1 LICLK 273 L1GR Setup Time to L1SY1 Falling Edge 50 42 34 ns 274 L1GR Hold Time from L1SY1 Falling Edge 50 42 34 ns SDS1 SDS2 Active Delay from L1CLK Ris 275 ing Edge y 10 75 10 65 7 50 ns SDS1 SDS2 Inactive Delay from L1CLK 276 Falling Edge y 10 75 10 65 7 50 ns NOTES 1 The ratio CLKO L1CLK must be greater than 2 5 1 2 High impedance is measured at the 30 and 70 of Vpp points with the line at Vpp 2 through 10K in parallel with 130 pF 3 Where P 1 CLKO Thus for a 25 MHz CLKO rate P 40 ns MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc _ gt kG MBOnoooonmoeEcooooocooen a BOOoooocmoaecCOooocooooong lt gt lt gt Ke lt lt 2 i L1SY1 INPUT LIRQ OUTPUT LIGR INPUT LICLK INPUT LITXD OUTPUT LIRXD INPUT SDS1 SDS
107. 14 IPLO IRQ1 6 16 IRQ1 3 15 6 14 IRQ6 3 15 IRQ7 3 15 NC1 6 16 NMSI2 6 21 NMSI3 6 23 PB11 6 27 PB8 6 27 PC_A25 6 31 PC_CE2 6 31 PC_D15 PC_D0 6 30 PC_IORD 6 24 PC_IOWR 6 24 PC_OE 6 30 PC_RDY IREQ 6 32 PC_STSCHG 6 29 PC_WAIT 6 32 PC_WE 6 25 PCM Highway 6 19 Port A 6 21 6 23 6 24 Port B 6 25 6 27 R W Read Write 6 13 RESET 2 2 6 9 6 10 6 27 RI PB9 6 28 RMC 3 4 RTS1 6 21 SCP 6 23 TIN1 TIN2 6 26 TOUT1 TOUT2 6 26 TRIS 6 11 WDOG 3 18 6 27 XTAL 6 9 SIMASK 4 2 SIMODE 4 2 SLOW_GO 2 9 2 13 2 15 SMC 2 20 Serial Management Controllers 4 49 SMC Memory Structure 4 49 Software Operation 4 3 Software Watchdog Timer 3 22 STAND_ BY 2 13 2 15 STOP 2 13 2 15 Supervisor Data Space 2 2 System Configuration Registers 2 2 Control Registers SCR 2 3 System Clock IMP 2 11 System Control 3 1 System Control Bits 3 4 System Control Pins 6 9 System Control Register SCR 3 2 System Status Bits 3 3 T TCLK1 Disabling 4 3 TCN1 TCN2 3 21 TCR1 TCR2 3 21 TER1 TER2 3 21 THR 4 35 Timer PIT 3 22 Timer 3 3 22 Timer Pins 6 26 Timers 3 20 Prescaler 3 21 TIN1 TIN2 6 26 TOUT 1 TOUT2 6 26 WDOG 3 18 3 22 TIN1 TIN2 6 26 TIN1 TIN2 See SCC TMR1 TMR2 3 20 TOUT 1 TOUT2 6 26 Transparent Controller 4 21 Event Register 4 23 Mask Register 4 23 Transmit Buffer Descriptor 4 23 Transparent Memory Map 4 21 Transparent Mode Register 4 22 Transparent Receive Buffer Descriptor MC68PM302 REFERENCE MANUAL For More Information On
108. 2 OUTPUT Figure 7 20 IDL Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 16 IMP AC Electrical Specifications GClI Timing GCI supports the NORMAL mode and the GCI channel 0 GCNO in MUX mode Normal mode uses 512 kHz clock rate 256K bit rate MUX mode uses 256 x n 3088 kbs clock rate is data rate x 2 The ratio CLKO L1CLK must be greater than 2 5 1 see Figure 7 21 16 67 MHz 20 MHz 25 MHz Num Characteristic at 5 0 V at 5 0 V at5 0V Unit Min Max Min Max Min Max L1CLK GCI Clock Frequency Normal Mode es Note 1 quency 512 5142 512 kHz 280 L1CLK Clock Period Normal Mode see Note 1 1800 2100 1800 2100 1800 2100 ns 281 L1CLK Width Low High Normal Mode 840 1450 840 1450 840 1450 ns 282 L1CLK Rise Fall Time Normal Mode see Note 4 ns 280 L1CLK Clock Period MUX Mode see Note 1 150 150 150 ns 281 L1CLK Width Low MUX Mode 55 55 55 ns 281A L1CLK Width High MUX Mode see Note 5 P 10 P 10 P 10 ns 282 L1CLK Rise Fall Time MUX Mode see Note 4 ns 283 L1SY1 Sync Setup Time to L1CLK Falling Edge 30 25 20 ns 284 L1SY1 Sync Hold Time from L1CLK Falling Edge
109. 2 PA4 PC_D12 RTS2 PA5 PC_D13 CD2 PA6 PC_D14 e BOOT SDS2 PA7 BRG2 PC_D15 Table 6 11 Baud Rate Generator Outputs Source NMSI GCI IDL PCM SCC1 SCC2 BRG2 TCLK2 TCLK2 TCLK2 SCC3 BRG3 TCLK3 TCLK3 TCLK3 NOTE In NMSI mode the baud rate generator outputs can also appear on the RCLK and TCLK pins as programmed in the SCON register PC _D15 PC_D8 PCMCIA Data Bus The bidirectional PCMCIA card interfaces data bus When the MC68PM302 is not en abled for PCMCIA these pins are used for SCC2 signals MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description 6 1 16 NMSI3 Port or Port A Pins or SCP Pins The NMSI3 port or port A pins or SCP pins are shown in Figure 6 12 ma RXDB PA8 a TXD3 PA9 a RCLK3 PA10 a TCLK3 PA11 ma CTS3 SPRXD a RTS3 SPTXD a CD3 SPCLK a MODCLK BRG3 PA12 Figure 6 12 NMSI3 Port or Port A Pins or SCP Pins These eight pins can be used either as the NMSI3 port or as the NMSI3 port less three mo dem lines and the SCP port If the SCP is enabled EN bit in SPMODE register is set then the three lines are connected to the SCP port Otherwise they are connected to the SCC3 port Each of the port A I O pins can be configured individually to be general purpose I O pins or a dedicated function in NMSI3 When they are used as the NMSI3 pins they function exactly as the NMSI1 pins s
110. 3 27 ns 116 Clock Low to UDS LDS High tcCLSH 45 _ 40 E 30 ns 117 R W Valid to Clock High see Note 2 tawvcH 30 25 20 ns 118 Clock High to R W High tcHRWH 45 40 30 ns 119 AS Low to IAC High taSLIAH 40 35 a 27 ns 120 AS High to IAC Low tASHIAL 40 35 27 ns 121 AS Low to DTACK Low 0 Wait State tastotL 45 40 30 ns 122 Clock Low to DTACK Low 1 Wait State tcLDTL 30 25 20 ns 123 AS High to DTACK High tasHDTH 45 40 30 ns 124 DTACK High to DTACK High Impedance totHptz 15 15 10 ns 125 Clock High to Data Out Valid tcHDov 30 25 20 ns 126 AS High to Data High Impedance tASHDZ 45 40 30 ns 127 AS High to Data Out Hold Time tasHDo 0 0 0 ns 128 AS High to Address Hold Time on Read tasHal 0 0 0 ns 129 UDS LDS Inactive Time tsH 1 1 1 clk 130 Data In Valid to Clock Low tcLpIv 30 25 20 ns 131 Clock Low to Data In Hold Time CLDIH 15 12 10 ns NOTES 1 Synchronous specifications above are valid only when SAM 1 in the SCR 2 It is required that this signal not be asserted prior to the previous rising CLKO edge i e in the previous clock cycle It must be recognized by the IMP no sooner than the rising CLKO edge shown in the diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semicond
111. 39 PCRWER 5 26 PCRWMR 5 27 PDDAT 3 20 Periodic Timer Period Calculation 3 23 PGA Package Pins 6 16 Pin Assignments 8 1 Pin Grid Array 8 1 Pin Multiplexing Summary 6 32 Pins IMP System Bus 6 3 6 4 Pins IMP 6 1 Pins IMP Peripheral 6 5 PIT 2 11 2 12 3 22 As a Real Time Clock 3 24 Period Calculation 3 23 PITR 2 6 3 24 PLL 2 9 PLL and Oscillator Changes to IMP and DSP 2 5 CLKO Drive Options 2 5 PLL Clock Divider 2 9 PLL External Components 2 9 PLL Pins IMP 2 12 pgnd 6 9 pinit 2 7 Port A 3 17 Port A Pin Functions 3 18 Port A B Parallel I O 3 17 Port B 3 18 Port B Pin Functions 3 19 Power and Ground Pins 6 34 Power Dissipation 7 2 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Index PPR 3 27 Programmable Data Bus Size Switch 3 7 Enabling the Dynamic Bus Switch 3 7 Protocol Parameters 2 20 PRR 5 33 PUCR 5 20 Pullup Control Register PUCR 5 20 Pullup Resistors 6 34 R RBR 4 34 RCLK1 Disabling 4 3 Read Modify Write Cycle 7 13 7 14 Real Time Clock 3 24 Registers Internal 2 22 Interrupt In Service ISR 3 17 Interrupt Pending IPR 3 16 Port A Control PACNT 3 17 Port B Control PBCNT 3 18 Data Direction Register PBDDR 3 18 System Configuration 2 2 System Control SCR 2 3 Reprogramming to UART Mode or Another Protocol 4 18 RESET 6 9 6 10 6 27 Instruction 2 2 Reset SMC Memory Structure 4 49 Total System 2 2 Re
112. 5 4 3 2 1 0 ECO INTN INTE REQG SAPI DAPI SSIZE DSIZE BT RST STR Bit 15 Reserved for future use ECO External Control Option Only supported if the PCMCIA is disabled 0 If the request generation is programmed to be external in the REQG bits the con trol signals DACK and DONE are used in the source read portion of the transfer since the peripheral is the source 1 Ifthe request generation is programmed to be external in the REQG bits the con trol signals DACK and DONE are used in the destination write portion of the transfer since the peripheral is the destination MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc INTN Interrupt Normal 0 When the channel has completed an operand transfer without error conditions as indicated by DONE the channel does not generate an interrupt request to the IMP interrupt controller The DONE bit remains set in the CSR 1 When the channel has completed an operand transfer without error conditions as indicated by DONE the channel generates an interrupt request to the IMP interrupt controller and sets DONE in the CSR NOTE An interrupt will only be generated if the IDMA bit is set in the in terrupt mask register IMR INTE Interrupt Error 0 Ifa bus error occurs during an operand transfer either on
113. 50 42 e ns L1TxD Active Delay from L1CLK Rising Edge 285 see Note 2 0 100 0 85 0 70 ns L1TxD Active Delay from L1SY1 Rising Edge 286 see Note 2 0 100 0 85 0 70 ns 287 L1RxD Setup Time to L1CLK Rising Edge 20 Tf 14 ns 288 L1RxD Hold Time from L1CLK Rising Edge 50 42 34 ns 2g9 Time Between Successive L1SY1in Normal 64 64 64 LICLK SCIT Mode 192 192 192 LICLK SDS1 SDS2 Active Delay from L1CLK Rising Edge 290 Gee Note 3 y grog 10 90 10 75 7 60 ns SDS1 SDS82 Active Delay from L1SY1 Rising Edge 291 see Note 3 10 90 10 75 7 60 ns 292 Eaa SDS2 Inactive Delay from L1CLK Falling 10 90 10 75 7 60 n 293 GCIDCL GCI Data Clock Active Delay 0 50 0 42 0 34 ns NOTES 1 The ratio CLKO L1CLK must be greater than 2 5 1 2 Condition C 150 pF L1TD becomes valid after the L1CLK rising edge or L1SY1 whichever is later 3 SDS1 SDS2 become valid after the L1CLK rising edge or L1SY1 whichever is later 4 Schmitt trigger used on input buffer 5 Where P 1 CLKO Thus for a 25 MHz CLKO rate P 40 ns MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc GCIDCL OUTPUT SDS1 SDS2 OUTPUT Figure 7 21 GCI Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com F
114. 68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller card configuration registers and the card information structure CIS memory The CIS is lo cated in external 68000 memory space I O accesses are relayed directly to the UART 16550 registers Section 4 Communications Processor CP Common memory accesses are mapped into 68000 memory There is a unique common memory burst access mode which allows a much higher data transfer rate between the PC and the card because it elim inates the WAIT signal handshaking NOTE In this section the PCMCIA master or the computer to which the MC68PM302 slave interface will be plugged into and will com municate with is referred to as the PC The PCMCIA controller also supports low power modes The PC can place the card into one of the three supported STOP modes through the use of the PwrDwn bit in the CCSR The PCMCIA controller is capable of waking up the MC68PM302 from the stand by STOP mode when any access is made on the PCMCIA bus Setting the power down bit can also cause a wake up from any of the three stop modes The PCMCIA controller also supports the ring and packet indication for modem and other I O cards In addition to being able to wake up from low power modes when ring indicate RI is asserted the MC68PM302 can optionally directly notify the PC without waking up through a direct connection of RI
115. 8432 MHz sampling clock on TIN1 or RCLK and a shift factor of 5 Table 4 6 Lookup Table Example Desired Maximum Nominal Baud Rate Start Start 115200 19 8 57600 36 16 38400 54 24 28800 6a 32 19200 10a 48 14400 13a 64 12000 166 77 9600 208 96 7200 270 128 4800 410 192 2400 810 384 1200 1630 768 600 3240 1536 300 6470 3072 110 17600 8378 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 3 9 6 DETERMINING CHARACTER LENGTH AND PARITY Table 4 7 shows the dif ferent possible character lengths and parity that will be discussed The following paragraphs will discuss for each case how to determine the parity Table 4 7 Character Lengths and Parity Cases 4 3 9 7 AUTOBAUD RECEPTION ERROR HANDLING PROCEDURE The Character i Case Length Parity Notes 1 7 bit No parity 1 STOP bit Not Supported Even parity i Odd parity Parity is indicated by the most signif 2 fbit Parity 1 icant bit of the byte Parity 0 3 8 bit No parity Same as 7 bit parity 0 Even parity bn A feoi i Parity is indicated by which charac 4 8 bit Odd parity ters Seneiaie a FE interrupt Parity 0 5 8 bit Parity 1 Not Supported e Case 1 This case cannot be supported because the autobaud can not separate the first character from the second character Case 2 As each cha
116. AANA EELEE AAEE 4 5 VART Controler deea o a y aa Ea eae a anaE 4 6 UART Memory Map ci2 cc ascseceecatacte uve licentameiitth amended eeatn aie Litt cetecs 4 6 UART ModesRegiStetinc 0 oes Ste a eas ca eee eee 4 6 UART Receive Buffer Descriptor RX BD ccceceeeeeeeeeeeeeeeeeteeeeeees 4 6 UART Transmit Buffer Descriptor TX BD ccceesssececeeeeeeeeeeeeeeeees 4 7 UART Event REGIST Mo ected edn caer eaten cnenegsl abe reeset aed dept ee eal etedeng 4 7 WARE MASK Register cca feces ds cai densest a e ee cnc sas EE A 4 7 Autobaud Controller New ecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeaaeeeeeeeeeee 4 7 Autobaud Channel Reception Process cccccccceeeeceeeeeeeeeeeeeneeeeeeeeeees 4 8 Autobaud Channel Transmit Process ccccesesseceeeeeeeeeeeeeeeeeeeeeeeeees 4 9 Autobaud Parameter RAM cccccesseeeeceeeeeeeeeeeneeeeeeeesenaaeeeeeeeeeeees 4 10 Autobaud Programming Model wis cicceccciteiassstecntostapeeeniecaensipldasewetieeielsddicd 4 11 Preparing for the Autobaud Process ccecccceeeeeeeeeeeeeeeeeeeeetesneeeeees 4 11 Enter Baud JURE COMManG i400 te ode cade ou teed ccm due deaton fds 4 12 Autobaud Command DeSCIiptl ceceeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeneees 4 12 Autobaud Lookup Table ccececeecceeeeeeeeeeeeeeeeeeeeeeeeceeeeeeeeeeeenaeeeeeeeeeee 4 14 look p Table Example meee cececd as cette cd esse peace nese caine ea Ea aiia 4 15 Determin
117. Base 560 4 Word SCC2 16550 Tx BD 4 Base 568 4 Word SCC2 16550 Tx B Base 570 4 Word SCC2 16550 Tx BD 6 DRAM Refresh Base 578 4 Word SCC2 16550 Tx BD 7 DRAM Refresh Base 580 SCC2 Specific Protocol Parameters Base 5BF SCC2 Base 5C0 y Reserved 7 Not Implemented Base 5FF Base 600 4 Word SCC3 Rx BD 0 Base 608 4 Word SCC3 Rx BD 1 Base 610 4 Word SCC3 Rx BD 2 Base 618 4 Word SCC3 Rx BD 3 Base 620 4 Word SCC3 Rx BD 4 Base 628 4 Word SCC3 Rx BD 5 Base 630 4 Word SCC3 Rx BD 6 Base 638 4 Word SCC3 Rx BD 7 Base 640 4 Word SCC3 Tx BD 0 Base 648 4 Word SCC3 Tx BD 1 Base 650 4 Word SCC3 Tx BD 2 Base 658 4 Word SCC3 Tx BD 3 Base 660 3 Word SMC Reserved Base 666 Word SMC1 Rx BD Base 668 Word SMC1 Tx BD Base 66A Word SMC2 Rx BD Base 66C Word SMC2 Tx BD Base 66E 6 Word SMC1 SMC2 Internal Use Base 67A Word SCP Rx Tx BD Base 67C Word SCC1 SCC3 BERR Channel Number Base 67E Word CP MC68PM302 Revision Number MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc Table 2 5 Parameter RAM Base 680 SCC3 Specific Protocol Parameters Base 6BF SCC3 Base 6CO gt Reserved Not Implemented Base 7FF Modified by the CP after a CP or system reset Tx BD 4 5 6 and 7 are not initially available to SCC3 4 3 5 Buffer Descriptors Ta
118. Buenos Aires Argonics S A 303 243 9658 316 838 0190 702 746 0642 505 298 7177 801 561 5099 509 924 2322 541 343 1787 HYBRID COMPONENTS RESELLERS Elmo Semiconductor Minco Technology Labs Inc Semi Dice Inc MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com 818 768 7400 512 834 2022 310 594 4631 Freescale Semiconductor Inc TABLE OF CONTENTS Paragraph Title Page Number Number Section 1 Introduction 1 1 Block PIAL noema tduat ecare ated nop E aE aE a E te aAa aE 1 1 1 2 Features cenana E Ceettiatts 1 1 1 3 PM302 Applications sisena aaa a EE te 1 4 1 4 PM302 Differences from Other DeVICES cceeseeeeeeeeteeeeeneeeeeeteeeeees 1 4 Section 2 Configuration Clocking Low Power Modes and Internal Memory Map 2 1 MC68PM302 and MC68302 Signal Differences eeeeeeeeeeeeeees 2 1 2 2 IMP Config ra ton Control sinsnsninira a a aai 2 2 2 2 1 Base Address Register BAR ceeeeeeeeeeeeeeeeeeeeseeeneeeeeeeeeeeee 2 4 2 3 System Configuration ReQiSterS cccccccceeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 2 4 2 4 Clock Generation and Low Power Control c cceeeeeeeeeeeeeeereeeeeeeees 2 5 2 4 1 PLL and Oscillator Changes to IMP eccceeeeeeeeneeeeeeeeeeeeeeeeeeeeeeeeees 2 5 2 4 1 1 Glock Control REGISION a eeraa EEan A aE Ea AEEA AAAA eb Oees demeetenceks 2 5 2 4 2 MC68PM302 System Clock Generation
119. CIA interface is fully functional For more information see 2 4 4 2 Low Power Support 5 1 9 PCMCIA Ring Indication The MC68PM302 PCMCIA interface has several options for handling the ring indicate RI or PB9 signal either by automatically passing the indication to the PC or by first allowing the 68000 core to process it Figure 5 6 shows a diagram of possible routings of the ring indicate signal Note that the IMP can be programmed to wake up from any of the three stop modes upon assertion of the RI signal IMP Interrupt and Wake up Circuitry RingEn From Card To Host RI PB8 _STSCHG RIEvt IOEIR RISWDIS RiEnab IOEIR SigChg CCSR Figure 5 6 Ring Indicate PB9 Connection Options The MC68PM302 can transfer the RI PB9 to the host using either of three programmable methods 1 Pass the RI signal directly to the PC through the RIEvt bit in the I O event indication register IOEIR which also will set the changed bit in the card configuration and status MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc register CCSR and can also optionally assert the STSCHG pin if the SigChg bit is set in the CCSR When the RI PB9 is asserted the RIEvt bit in the I O event indica tion register IOEIR will be set to one If the RlEnab has been set by the PC the changed bit in the CCSR will b
120. CMCIA cards It will perform the controller functions of a V 34 fax data modem in conjunction with a separate data pump With its PCMCIA and ISDN functionality on chip it can be gluelessly connected to an S T or U interface device to perform the functions of a ISDN terminal adaptor It can be used as a MAC controller for IEEE 802 11 wireless LANs It may also be used as a wireless WAN PCMCIA controller for CDPD Ardis Mobitex or dig ital cellular data applications 1 4 PM302 DIFFERENCES FROM OTHER DEVICES The PM302 can be considered as a superset of another derivative called the MC68LC302 The LC302 does not have the PCMCIA and 16550 features and only contains 2 SCCs The PM302 can also be considered to be a subset of the MC68356 The 356 adds a full 56002 DSP with memory and in one of its versions contains a full V 34 fax data data pump running on the DSP When the PM302 is operating in its PCMCIA mode certain functions existing on the original 68302 are no longer available The major differences are listed below External masters are not able to take the bus away from the PM302 except through a simple scheme using the HALT pin This restriction does not apply to using the PM302 is in CPU disabled mode slave mode in which case BR BG and BGACK are all avail able Although the Independent DMA IDMA is still available the external IDMA request pins DACK and DONE have been eliminated The DDCMP and V 110 protocols have been remo
121. CMCIA is enabled and the CPU Figure 6 1 Functional Signal Groups is disabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 6 1 IMP System Bus Pins Signal Description Group Signal Name Mnemonic See Note 0 Threestate TRIS TIN2 PB5 O Bus Width BUSW PC_ABUF O PCMICA Enable PC_EN TOUT2 PB6 O Mode Pins Boot from SCC BOOT BRG2 SDS2 PA7 1 O Disable CPU DISCPU VCCSYN Enable PLL VCCSYN l Clock Mode Select MODCLK BRG3 PA12 O eae Crystal Oscillator Rt he i 5 External Filter Capacitor XFC Clock Out CLKO O System Reset RESET I O Control Halt HALT O Address Address Bus A19 A1 VO Data Data Bus 15 0 D15 D0 VO Address Strobe AS 1 0 Bus Output Enable Read Write OE RW O Control Write Enable High AO Upper Data Strobe Address 0 EH AO UDS AO VO Write Enable Low Lower Data Strobe Data Strobe WEL WE LDS DS O Data Transfer Acknowledge DTACK 0 Interrupt Interrupt Priority Level 0 Int Request 1 Bus Request IPLO IRQT BR I O oer Interrupt Priority Level 1 Int Request 6 Bus Grant IPLT IRQ6 BGACK O Arbitration Interrupt Priority Level 2 Int Request 7 Bus Grant Acknowledge IPL2 IRQ7 BG l l Chip Select 0 Interrupt Output 2 CSOAOUT2 O Chip Select e Chip Select 1 3 1 CS3 O Spare Not Connected NC1 2 Bower Clock S
122. CP Controller NOTE Each one of the parallel I O pins can be configured individually 6 1 13 Typical Serial Interface Pin Configurations Table 6 7 shows typical configurations of the physical layer interface pins for an ISDN envi ronment Table 6 8 shows potential configurations of the physical layer interface pins for a non ISDN environment The IDMA IACK and timer pins can be used in all applications ei ther as dedicated functions or as PIO pins Table 6 7 Typical ISDN Configurations Pins Connected To Used As SCC1 Used as ISDN D ch SCC3 Used as ISDN B2 ch NMSI1 or ISDN I F SCC1 and SCC3 NMSI2 SCC2 SCC2 is Connected to Terminal PA12 PA8 PIO Extra Modem Signals and NMSI3 SCP Select Signals SCP Status Control Exchange NOTES 1 ISDN environment with SCP port for status control exchange and with existing terminal for rate adaption 2 D ch is used for signaling 3 B1 ch is used for voice external CODEC required 4 B2 ch is used for data transfer Table 6 8 Typical Generic Configurations Pins Connected To Used As NMSI1 or ISDN I F SCC1 Terminal with Modem NMSI2 SCC2 Terminal with Modem NMSI3 5 SCC3 Terminal without Modem NMSI3 3 SCP Status Control Exchange NOTE Generic environment with three SCC ports any protocol and the SCP port SCC3 does not use modem control signals MC68PM302 REFERENCE MANUAL For More Information On This Product
123. CR bits If the CPU de termines that the system needs the real clock it programs the RECLMODE bits which en ables the oscillator and PLL and interrupts if necessary if it decides that the system can go back to sleep it executes the normal power down sequence which turns off Ringo Upon switching to the real clock the CPU can be interrupted by programming the RICR bits Note that Ringo is turned off either at the end of a power down sequence or when the PLL has gained lock If the RECLMODE bits are programmed to enable the PLL and the oscillator the user is allowed to enter low power mode after the real clock has resumed The chip will not operate correctly if the CPU enters the low power sequence while the PLL is waking up Resetting of the RINGOEN bit is allowed only if the system is clocked by the real clock The CLKO signal can be disabled by software if the user cannot operate the system at the Ringo frequency 2 4 4 3 5 Ring Oscillator Control Register RINGOCR RINGOCR BAR 81A 7 6 5 4 3 2 1 0 PO RICR RECLMODE _CRINGOEN RESET 0 0 0 0 0 0 0 0 Read Write RINGOEN Ring Oscillator Enable 0 Ring oscillator is not used 1 Ring oscillator is enabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senveandaeten Inc RECLMODE Real Clock Mode 00 Do not enable the real clock 01 Enable the real clock and switch the system cloc
124. DLC Mask Register 4 20 HDLC Mode Register 4 19 HDLC Receive Buffer Descriptor 4 19 HDLC Transmit Buffer Descriptor 4 19 Tx BD 4 19 HDLC Receive Buffer Descriptor 4 19 I IACK or PIO Port B Pins 6 25 IACK7 6 25 6 26 IDL 4 2 6 18 6 19 IDL See Signals IDMA Independent DMA Controller 6 14 6 24 DONE 3 12 3 14 DREQ 3 12 IDMA or Port A Pins or PCMCIA Pins 6 24 IER 4 31 IIR 4 30 IMP Address and Function Codes or PCMCIA Data 6 32 IMP Bus Control Pins 6 30 IMP Data Bus Pins 6 12 IMP Features CP 1 2 1 3 IMP Operation Mode Control Register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Index Freescale Semiconductor Inc IOMCR 2 14 2 15 IMP Peripheral Pins 6 5 IMP Peripheral Pins 6 5 IMP PLL 6 27 IMP PLL and Clock Control Register IPLCR 2 10 IMP System Clocks Schematic PLL Disabled 2 8 IMP Wake Up from Low Power STOP Modes 2 17 IMR 3 17 Internal Bus Arbitration 3 29 Internal Registers 2 22 Internal Registers Map 2 23 Interrupt Acknowledge 2 4 Control Pins 6 14 Controller 3 15 IACK7 6 25 6 26 IPR 3 16 IRQ1 3 15 IRQ6 3 15 IRQ7 3 15 ISR 3 17 Interrupt Control Pins 6 14 Interrupt Controller 3 15 IOEIR 5 35 IOMCR 2 6 2 7 2 8 2 9 2 10 2 15 IPLO IRQ1 6 16 IPL2 IPLO 6 14 IPLCR 2 6 2 7 2 8 2 10 IPR 3 16 IRQ1 3 15 6 14 IRQ1 See Interrupt IRQ1 See Signals IRQ6 3 15 IRQ6 See Interrupt IRQ6 See Signals IRQ7 3 15 IRQ7 See Interrupt IRQ7 See Signals ISDN 6
125. E MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics SO S1 S2 3 S4 S5 S6 S7 S0 S1 2 CLKO OUTPUT PC_A23 A12 INPUT PC_A11 A0 INPUT NOTE 2 PC_CE2 PC_CE1 INPUT PC_OE INPUT WAIT OUTPUT A23 A12 OUTPUT A11 A0 OUTPUT NOTE 2 AS LDS UDS OUTPUT CS OE OUTPUT a i oa cane gt lt lt a ne gt gt lt 6 Figure 7 29 PCMCIA Normal Read DTACK OUTPUT MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc S0 S1 2 3 S4 S5 S6 S7 S0 CLKO OUTPUT PC_A23 PC_A12 INPUT CN PC_A11 PC_AO INPUT NOTE 2 PC_CE2 PC_CEl INPUT PC_WE INPUT WA OUTPU A23 A OUTPU All OUTPUT NOTE gt OUTPU LDS UDS OUTPUT gt lt 22 WEH WEL gt OUTPUT F lt Gi wn OUTPU D15 D0 OUTPU PC_D15 PC_ INPU NOTES 1 PC_A11 is input if ABUF PC_A11 bit in PCMR 0 2 If ABUF A11 1 in pemr A23 A12 are input to chip 3 Asserted if ABUF A11 1 in PCMR Figure 7 30 PCMCIA Normal Write MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristi
126. EH AO UDS A0 lt WEL WE LDS DS lt DTACK Figure 6 6 Bus Control Pins AS Address Strobe This bidirectional signal indicates that there is a valid address on the address bus This line is an output when the IMP M68000 core SDMA or IDMA is the bus master and is an input otherwise MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description OE R W Output Enable Read Write This pin functions as R W in Slave Mode and PCMCIA Enable mode DISCPU 1 and PC_EN 1 In all other cases it functions as OE As OE this output is active during a read cycle and indicates that an external device should place valid data on the bus As RM this bidirectional signal defines the data bus transfer as a read or write cycle It is an output when the PM302 is the bus master and is an input otherwise NOTE This pin is high impedance when External Master acquires the Bus with HALT WEH UDS A0 Write Enable High Upper Data Strobe Address 0 This pin functions as UDS in Slave Mode and PCMCIA Enable DISCPU 1 and PC_EN 1 In all other cases it functions as WEH WEH AO is active during a write cycle to indicate that an external device should expect data on the D15 D8 of the data bus When using an 8 bit data bus this pin acts as AO UDS controls the flow of data on the data bus When using a 16 bit data bus this pin func tions as upper da
127. EIR register will be set when RI is asserted 1 The RIEvt bit in the IOEIR is not set when RI is asserted This mechanism is useful to allow the 68000 core to either integrate or debounce the RI signal by software before updating the RIEvt bit the RI PB9 pin can be read by the 68000 core MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc through the port B data register Refer to Figure 5 6 Ring Indicate PB9 Connec tion Options For bits PCSTR IDOI PCDDIR PCDSWP PC_DREQEN See 5 3 11 PCMCIA DMA Support 5 3 3 PCMCIA Configuration Registers Write Event Register PCRWER PCRWER PCMCIA Address Not accessible 68000 Address BAR 8C4 7 6 5 4 3 2 1 0 RES3 RES2 ES1 IOIEIR SCR PRR CCSR COR RESET 0 O 0 0 0 0 0 0 Read Write The PCMCIA configuration registers write event register is an 8 bit register that reports PC writes to one of the PCMCIA configuration registers The appropriate event bit is set depend ing on the location of host write regardless of the corresponding mask bit in the PCRWMR If the corresponding mask bit is set and the INTRLO 1 bits in the PCMR register are non zero an interrupt will be generated In order to generate an interrupt the INTRLO 1 bits in the PCMR register must be set to a non zero value The PCRWER is a memory mapped register that may be read at any time A bit can be re
128. ETTS Woburn MICHIGAN pene MINNESOTA Minnetonka MISSOURI St Louis NEW JERSEY Fairfield NEW YORK Fairport NEW YORK Haup ppaug NEW YORK Pou keepsie Fishkil NORTH CAROLINA Raleigh OHIO Cleveland OHIO coupe Worthington OHIO Da in Tulsa OREGON Portland PENNSYLVANIA Colmar Philadelphia Horsham TENNESSEE Knoxville TEXAS Austin TEXAS Houston TEXAS Plano VIRGINIA Richmond WASHIN NGTON Bellevue Seattle Acc WISCONSIN Milwaukee Brookfield MALAYSIA Penang MEXICO Mexico City MEXICO Guadalajara Marketing Customer Service NETHERLANDS Best PUERTO RICO San Juan SINGAPORE SPAIN Madrid or SWEDEN Solna SWITZERLAND Geneva SWITZERLAND Zurich TAIWAN Taipei THAILAND Bangkok UNITED KINGDOM Aylesbury 508 481 8100 617 932 9700 201 808 2400 MNAWOONOOJIN aa f a pa e rdar ATNWNOWRMDORMDDA A K Ko N 206 622 9960 414 792 0122 60 4 374514 52 5 282 2864 52 36 21 8977 52 36 21 9023 52 36 669 9160 31 49988 612 11 809 793 2170 65 2945438 34 1 457 8204 34 1 457 8254 46 8 734 8800 41 22 7991111 41 1 730 4074 886 2 717 7089 66 2 254 4910 44 296 395 252 FULL LINE REPRESENTATIVES COLORADO Grand Junction Cheryl Lee Whitely KANSAS Wichita Melinda Shores Kelly Greiving NEVADA Reno Galena Technology Group NEW MEXICO Albuquerque S amp S Technologies Inc UTAH Salt Lake City Utah Component Sales Inc WASHINGTON Spokane Doug Kenley ARGENTINA
129. Each chip select can be set to block PCMCIA accesses to its memory space When the chip select protection bit is set the external PCMCIA host cannot access the memory block The protection for each chip select block can be enabled by setting the PCS 3 0 bits in the PC MCIA protection register PPR In addition internal IMP registers and dual port RAM ac cess from the PCMCIA bus can also be disabled using the PIR bit in the PPR For more information see 3 8 1 3 PCMCIA Protection Register PPR MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller 5 1 7 PCMCIA Controller Initialization After hardware reset the PCMCIA controller assumes the default memory only card con figuration with the RDY BSY signal being low to indicate the busy condition The 68000 core should initialize the CIS base address register with the high address of the external CIS memory address The CIS memory may be located in external IMP RAM ROM which is pointed to by the CIS base address register CISBAR The MC68PM302 has five configu ration registers according to the PCMCIA standard plus the three registers reserved for fu ture use These registers are located on the PCMCIA attribute address space and can be accessed by the PC when A25 is high PCMCIA attribute addresses 2000000 or higher The CIS s configuration tuple TPCC_RADR should have the base address of these reg
130. FB 4K BLOCK BASE 0 SYSTEM RAM DUAL PORT xxx000 BASE 4K BLOCK BASE 400 PARAMETER RAM DUAL PORT BASE 800 INTERNAL REGISTERS BASE FFF F FFFFF Figure 2 1 IMP Configuration Control and HALT The chip select CS lines are not asserted on ac cesses to these locations Thus it is very helpful to use CS lines to select external ROM RAM that overlaps the BAR and SCR register locations since this prevents potential bus contention NOTE In 8 bit system bus operation IMP accesses are not possible un til the low byte of the BAR is written Since the MOVE W instruc tion writes the high byte followed by the low byte this instruction guarantees the entire word is written Do not assign other devices on the system bus an address that falls within the address range of the peripherals defined by the BAR If this happens a BERR is generated to the core if the address decode conflict enable ADCE bit is set and the address decode con flict ADC bit in the SCR is set MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc 2 2 1 Base Address Register BAR The BAR is a 16 bit memory mapped read write register consisting of the high address bits the compare function code bit and the function code bits Upon a total system reset its value may be read as BFFF but its value is not valid until written by
131. Freescale Semiconductor Inc MC68PM302 Integrated Multiprotocol Processor with PCMCIA Reference Manual toy poe freescale For More Information On This Product o to www freescale com Freescale Semiconductor Inc PREFACE The complete documentation package for the MC68PM302 consists of the MC68PM302RM AD MC68PM302 Low Power Integrated Multiprotocol Processor with PC MCIA Interface Reference Manual M68000PM AD MC68000 Family Programmer s Refer ence Manual MC68302UM AD MC68302 Integrated Multiprotocol Processor User s Manual and the MC68PM302 D MC68PM302 Low Power Integrated Multiprotocol Proces sor with PCMCIA Interface Product Brief The MC68PM302 Low Power Integrated Multiprotocol Processor with PCMCIA Interface Reference Manual describes the programming capabilities registers and operation of the MC68PM302 that differ from the original MC68302 the MC68000 Family Programmer s Reference Manual provides instruction details for the MC68PM302 and the MC68PM302 Low Power Integrated Multiprotoco l Processor with PCMCIA Interface Product Brief pro vides a brief description of the MC68PM302 capabilities The MC68302 Integrated Multiprotocol Processor User s Manual User s Manual is required since the MC68PM302 Low Power Integrated Multiprotocol Processor with PCMCIA Inter face Reference Manual only describes the new features of the MC68PM302 This user s manual is organized as follows Section 1 Introduction
132. Go to www freescale com Freescale Semiconductor Inc Signal Description 6 1 14 NMSI1 or ISDN Interface Pins The NMSI1 or ISDN interface pins are shown in Figure 6 10 mt RXD1 L1RXD m TXD1 L1TXD 4 gt RCLK1 L1CLK at TCLK1I L1SYO a CD1 L1SY1 a CTST LIGR RTS1 L1RQ GCIDCL Figure 6 10 NMSI1 or ISDN Interface Pins These seven pins can be used either as NMSI1 in nonmultiplexed serial interface NMSI mode or as an ISDN physical layer interface in IDL GCI and PCM highway modes Table 6 9 shows the functionality of each pin in NMSI GCI IDL and PCM highway modes Table 6 9 Mode Pin Functions Signal Name NMSI1 GCI IDL PCM RXD1 L1RXD L1RXD L1RXD L1RXD TXD1 L1TXD L1TXD L1TXD L1TXD RCLK1 L1CLK L1CLK L1CLK L1CLK TCLK1 L1SY0O SDS1 SDS1 L1SYO CD1 L1SY1 LISYNC LISYNC CTS1 L1GR LiGR L1GR RTS1 L1RQ GCIDCL L1RQ NOTES 1 In IDL and GCI mode SDS2 is output on the PA7 pin 2 CD1 may be used as an external sync in NMSI mode 3 RTS is the RTS1 RTS2 or RTS3 pin according to which SCCs are connected to the PCM highway RXD1 L1RXD Receive Data Layer 1 Receive Data This input is used as the NMSI1 receive data in NMSI mode and as the receive data input in IDL GCI and PCM modes TXD1 L1TXD Transmit Data Layer 1 Transmit Data This output is used as NMSI1 transmit data in NMSI mode and as the transmit data output in IDL GCI and PCM modes TXD1 may
133. HALT If bit FAST 0 in PCMR wait two system clocks If bit FAST 1 in PCMR wait three sys tem clocks N If AS is negated go to step 5 Wait for AS negation Wait two additional system clocks Execute Access now the bus is guaranteed to be threestated When done threestate bus and Negate HALT Ooo KR W NOTE The RMCST bit in the SCR should be zero for this arbitration procedure to work correctly Also the external master cannot access the internal address space of the 68PM302 NOTE WEH WEL and OE are threestated when HALT is asserted by external master 3 9 DYNAMIC RAM REFRESH CONTROLLER The communications processor CP main RISC controller may be configured to handle the dynamic RAM DRAM refresh task without any intervention from the M68000 core Use of this feature requires a timer or SCC baud rate generator either from the IMP or exter nally the I O pin PB8 and two transmit buffer descriptors from SCC2 Tx BD6 and Tx BD7 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB No changes have been made to the DRAM controller For more information please refer to the MC68302 Users Manual MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc MC68PM302 REFERENCE MANUAL For More Information On This
134. I O Ports some with Interrupt Capability On Chip 1152 Byte Dual Port RAM MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Introduction Freescale Semiconductor Inc INTERFACE 3 SERIAL CHANNELS SCCs I I Low 1 GENERAL POWER INTERRUPT PURPOSE 3 TIMERS I l CONTROL CONTROLLER DMA ete RAM ROM l CHANNEL l 68000 68000 SYSTEM BUS CORE 20 ADDRESS l 8 16 DATA l I l 6 SDMA 1152 BYTES l DUAL PORT l CHANNELS F l PCMCIA fI l SLAVE fi INTERFACE l RISC PERIPHERAL BUS amp CONTROLLER UART 11 ADDRESS 16550 8 16 DATA l l l l l 68P M302 Figure 1 1 MC68PM302 Block Diagram Three Timers Including a Watchdog Timer New Periodic Interrupt Timer PIT Four Programmable Chip Select Lines with Wait State Generator Logic Programmable Address Mapping of the Dual Port RAM and IMP Registers On Chip Clock Generator with Output Signal Glueless Interface to EPROM SRAM Flash EPROM and EEPROM Allows Boot in 8 Bit Mode and Running Switch to 16 bit Mode Allows System Clock to be Generated from 32 kHz or 4 MHz Crystals in Addi tion to a Full Speed Clock Oscillator System Control System Status and Control Logic Disable CPU Logic Slave Mode Operation Hardware Watchdog New Low Power Standby Modes in A Range With Wake up From Two Pins or PIT Timer Freeze Control for Debugging DRAM Refresh Controller e CP Including Main Controller RISC Pro
135. IGNALNAME 5 2 2 PCMCIA Pins Not Supported The following pins are not implemented on the MC68PM302 and should be supported with external circuitry Write Protect WP This output signal reflects the status of the card s write protect switch When a card or socket is configured for the I O interface the write protect status may be available in the pin replacement register and the signal is replaced in the interface by the I O Port IS 16 bits IOIS16 signal I O IS 16 Bit Port IOIST6 This output signal is asserted when the address at the socket corresponds to an I O ad dress to which the card responds and the I O port being accessed is capable of 16 bit access When this signal is not asserted during a 16 bit I O access the system will generate 8 bit references to the even and odd bytes of the 16 bit port being accessed MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc NOTE The MC68PM302 PCMCIA controller does not support 16 bit O accesses Therefore this pin should be tied high not asserted on the card Input Acknowledge INPACK I O Operation This output signal is asserted when the card is selected and the card can respond to an I O read cycle at the address on the address bus NOTE If enabled for I O mode accesses the MC68PM302 PCMCIA controller responds to I O read cycles at all addresses All I O accesses
136. In this mode the 68k CPU can either poll PCDRDY bit or enable its interrupt When PCDRDY event occurs the 68K CPU transfers data to from PCDMAD Register The PCDRDY event is reset by writing 1 to the bit NOTE Accessing the PCDMAD Register by the 68k when PCDRDY 0 may result in erroneous behavior 5 3 11 1 2 IDMA Mode Software programs the IDMA in the chip to external request edge sensitive For DMA Read cycles SAPI 0 and the Source Operand Address is the address of PCDMAD PC DMA Data mapped at Base 878 Register for DMA Write cycles DAPI 0 and the Destination Op erand Address is the address of PCDMAD Register The byte count has to be equal or long er to the transfer length Software enables PC_DMA and data flow direction in PCDMA Register When the PCSTR bit is set by software the PC_DMA hardware starts transfers If the data flows from the PC Host to the 68k bus DMA Read cycle the chip asserts PC_DREQ_ to the PC Host The PC Host executes a DMA Read cycle to the card The data is latched in the chip The chip then internally asserts DREQ_ signal to the IDMA The IDMA executes a source operand read from PCDMAD and a Destination operand write to Memory or External IO device on 68k bus If the data flows from the PC Card to the PC Host DMA Write cycle the chip in ternally asserted DREQ_ signal to the IDMA The IDMA executes a source operand read from the 68k bus Memory or IO device and a destination operand write to PCDMAD reg
137. Inc Electrical Characteristics L HIND 3y u HIG OOF seunsse Indu ue s INOA UEYM SLI 9U 104 E L HW 3y Ul q OOF 34 Selunssy g wesbeIp y 0 Ajdde jou op Aau asimiaujo fapow NdI a qGesip ul aL juo aye noqe umoys Dg pue yg SALON ALON OM INOA lt amp AION ONINILL ANY ISIS SNE TWNOLLIGdY SJ101 ALI 0o89 SAS ONINLLGNG STVNOSIS SNE WNOLLIGAY YO SJ 1014 AV JY 00089 SAS Figure 7 6 DMA Timing Diagram IDMA Go to www freescale com MC68PM302 REFERENCE MANUAL For More information On This Product Freescale Semiconductor Inc clectrical Characteristics wesbelp y 0 Adde jou op A y asimuaujo apow Nd aIGesip ul n AjUO sue BADGE UMOYS Dg pue yg zZ ONINLLGNY STVNOIS SNA WNOLLIGOV YO4 SATAD aUwwavY 00089 43S Buruy YWAS 0 jeonuap s Buruy 18 014U09 S3191 WYHA H SALON LNd_ LINO sv 0 1 gt DVDa Z SALON CLAdND 9a Z SALON Figure 7 7 DMA Timing Diagram SDMA MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 6 6 IMP AC Electrical Specifications External Master Internal Asynchronous Read Write Cycles see Figure 7 8 and Figure 7 9
138. Low Data Bus Address bus PC_D7 4 A23 A20 O PCMCIA or PCMCIA Address Port D PC_A9 A6 PDI14 11 lit ort D PCMCIA Address Port D PC_A2 PC_AO PDI10 8 I Note Signals in bold are enabled when the PCMCIA interface is enabled PC_EN 1 If the PCMCIA interface is not enabled then these pin are avaible as their secondary functions Input buffer has a Schmitt Trigger All pins except EXTAL and CLKO support TTL levels EXTAL when used as an input clock requires CMOS levels CLKO supplies a CMOS level output All outputs except CLKO can drive up to 100 pF CLKO is designed to drive up to 50 pF 6 1 1 Mode Pins TRIS Three State This input is sampled during total system reset RESET and HALT asserted When as serted high TRIS three states all of the 68PM302 pins This pin must be valid as long as RESET and HALT are asserted and have a hold time of 5ns after RESET and HALT are negated After reset this pin becomes TIN2 PB5 BUSW Bus Width Select This input defines the M68000 processor mode MC68000 or MC68008 and the data bus width 16 bits or 8 bits respectively This pin must be valid as long as RESET and HALT are asserted and have a hold time of 5ns after RESET and HALT are negated After reset this pin becomes PC_ABUF In 16 bit mode all accesses to internal and external memory by the M68000 core the ID MA the SDMA and any external masters may be 16 bits In 8 bit mode all M68000 core and IDMA acces
139. MC68PM302 SCC2 will be used as the DTE interface and autobauding to the DTE baud rate will often be required If use of the smart echo feature is desired the receive clock can be provided by the baud rate generator 2 BRG2 internally by resetting the RCS bit in the SCON2 register to zero The separate transmit clock can be MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc provided externally to the TCLK2 pin through a hardwire connection to either of the other baud rate generator pin BRG3 The TCS bit in the SCON2 register should be set to one to enable the external clock source After autobauding is complete both the transmit and receive clock sources can be derived internally from BRG2 and the external pin connected to TCLK2 should be three stated to assure that it does not contend with the TCLK2 pin This can be done by programming the BRG3 pin to a general purpose input by resetting bit 12 in the PACNT register to zero and resetting bit 12 in the PADDR register 4 3 9 3 AUTOBAUD PARAMETER RAM When configured to operate in the autobaud mode the IMP overlays some entries of the UART specific parameter RAM as illustrated in Table 4 3 Table 4 3 Autobaud Specific Parameter Address Name Width Description SCC Base 9C MAX_IDL Word Maximum IDLE Characters SCC Base 9E MAX_BIT Word Current Maximum START Bit Lengt
140. MR TRR and TCN 1 Enable timer I LK Input Clock Source for the Timer 00 Stop count 01 Master clock 10 Master clock divided by 16 11 Corresponding TIN pin TIN1 or TIN2 falling edge FRR Free Run Restart 0 Free run timer count continues to increment after the reference value is reached 1 Restart timer count is reset immediately after the reference value is reached ORI I Output Reference Interrupt Enable 0 Disable interrupt for reference reached 1 Enable interrupt upon reaching the reference value OM Output Mode 0 Active low pulse for one CLKO clock cycle 60 ns at 16 67 MHz 1 Toggle output CE Capture Edge and Enable Interrupt 00 Capture function is disabled 01 Capture on rising edge only and enable interrupt on capture event 10 Capture on falling edge only and enable interrupt on capture event 11 Capture on any edge and enable interrupt on capture event PS Prescaler Value The prescaler is programmed to divide the clock input by values from 1 to 256 The value 00000000 divides the clock by 1 the value 11111111 divides the clock by 256 3 7 1 2 Timer Reference Registers TRR1 TRR2 Each TRR is a 16 bit register contain ing the reference value for the timeout TRR1 and TRR2 are memory mapped read write registers 3 7 1 3 Timer Capture Registers TCR1 TCR2 Each TCR is a 16 bit register used to latch the value of the counter during a capture operation when an edge
141. Model 4 11 Reception Error Handling Procedure 4 16 Reprogramming to UART Mode or Another Protocol 4 18 Smart Echo 4 9 4 17 Smart Echo Hardware Setup 4 9 START bit 4 7 Transmit Process 4 9 Automatic Echo 4 3 B Baud Rate Generator 6 22 BCR 3 14 BERR 2 3 3 4 3 5 3 6 BERR See Signals BG 3 28 6 15 BGACK 6 15 BISYNC Controller 4 20 BISYNC Event Register 4 21 BISYNC Mask Register 4 21 BISYNC Memory Map 4 20 BISYNC Mode Register 4 20 BISYNC Receive Buffer Descriptor 4 21 BISYNC Transmit Buffer Descriptor 4 21 MODE Register 4 20 Tx BD 4 21 Bootstrap 3 7 BR 3 28 3 30 6 14 BRG 2 11 BRG Divide by two System Clock 2 14 BRG1 Disabling 4 3 BRGP 4 2 Buffer Buffer Descriptor 4 4 Descriptors 2 20 3 30 Buffer Descriptor 4 4 Buffer Descriptors Table 4 4 Bus Arbitration 6 15 Bandwidth 3 13 Error 2 3 Grant BG 6 15 Grant Acknowledge BGACK 6 15 Master 3 29 Request BR 6 14 Signal Summary 6 17 Bus Arbitration Logic 3 29 Bus Arbitration Pins 6 14 Bus Control Pins 6 12 Bus States during Low Power Modes 68000 2 14 BUSW 2 1 6 6 C CCSR 5 32 Changes to IMP and DSP CLKO Drive Options 2 5 Tri State RCLK1 2 6 Tri State TCLK1 2 6 Chip Select 2 3 AS 3 25 Base Address 3 27 Base Register 3 26 CSO 3 26 3 28 6 15 DTACK 3 26 Option Register 3 26 Chip Select Pins 6 15 Chip Select Registers 3 26 Chip Select Timing 7 25 CIS Base Address Register CISBAR 5 29 CISBAR 5 29 CLKO 6 6 Output Buffer Strengt
142. ND_BY mode is achieved by the 68000 core executing the following code nop move b 6 PC 000000FB scopy STOP operand high byte to addr 000000fb stop XXXX XXXX gt SR nop MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc This code is position independent The core must be in the supervisor state to execute the STOP instruction therefore the write to 000000FB must be done in the supervisor state function code 5 supervisor data The core trace exception should be disabled otherwise the low power control will not enter the STOP mode To guarantee supervisor state and trace exceptions disabled this code should be part of a TRAP routine Upon entering the trap routine examine the stacked status register If it indi cates the supervisor state then execute this code to enter STOP mode If not supervisor do NOT execute this code could perform some application specific error TRAP_x btst b 5 SP supervisor beq s NO_STOP nop flush execution bus pipes move b 6 PC 000000FB scopy STOP operand high byte to addr 0O00000fb stop XXXX XXXX gt SR nop rte NO_STOP a error routine NOTE The RI PB9 DTE PB10 and PIT conditions will generate a level 4 interrupt The PCMCIA will generate a level 1 6 or 7 interrupt The user should set the 68000 interrupt mask register to the ap propriate level before executing this c
143. Once a character of data is received the RISC controller counts any idle characters received If a MAX_IDL number of idle characters are received before the next data character is received and idle timeout occurs the buffer is closed This in turn can produce an interrupt request to the 68000 core to receive the data from the buffer Thus MAX_IDL provides a convenient way to demarcate frames in the 16550 mode NOTE Program MAX_IDL to 0001 for the minimum timeout value pro gram MAX_IDL to 0000 for the maximum timeout value IDLC This value is used by the RISC to store the current idle emulation counter value in the MAX_IDL timeout process IDLC is a down counter It does not need to be initialized or accessed by the user BRKCR The 16550 emulation controller will send an a break character sequence towards the PC whenever a STOP TRANSMIT command is given The Break Interrupt bit in the emulation line status register will be set See Line Status Register LSR Read Only on page 28 for more details The data sent towards the 16550 emulation receiver is the data written in character8 in the control characters table The number of break characters sent by the 16550 emulation controller is determined by the value in BRKCR RCCR CHARACTER8 1 These characters define the receive control characters on which interrupts may be gen erated 4 4 5 2 16550 EMULATION MODE REGISTER EMR This register programmed by the 68000 core is u
144. PC writes to the reserved register This bit can be cleared by writ ing a one to it Res2 Reserved2 Register This bit is set when the PC writes to the reserved2 register This bit can be cleared by writ ing a one to it Res3 Reserved3 Register This bit is set when the PC writes to the reserved3 register This bit can be cleared by writ ing a one to it 5 3 4 PCMCIA Configuration Registers Write Mask Register PCRWMR The PCRWMR is 8 bit memory mapped read write register that has the same bit format as the PCRWER If a bit in the PCRWMR is a one the corresponding interrupt in the PCRWER will be enabled If the bit is zero the corresponding interrupt in the PCRWMR will be dis abled PCRWMR is cleared at reset 5 3 5 PCMCIA Access Wake Up Event Register PCAWER PCAWER PCMCIA Address Not accessible 68000 Address BAR 8C5 7 6 5 4 3 2 1 0 PCDRDY PCTC MRW CMS2 CMS1 ATS IOS RESET 0 O 0 0 0 0 0 0 Read Write The 68000 core may program the IMP into stand by mode when there is no activity on the card for long periods of time PC accesses to the card will wake up the IMP The PCAWER is an 8 bit register used to report which type of PC write access was made to the card to wake the IMP up from STAND BY mode The 68000 core will receive an in terrupt if 1 It is awakened by a PCMCIA access and 2 The INTRL bits in the PCMR are non zero PCMCIA interrupts enabled and 3 The corresponding mask bit for the access type
145. PCAWMR bit 6 PCTC PCMCIA Terminal Count Mask O0 Mask interrupt to CPU 1 Do not mask interrupt bit 7 PCDRDY PCDMAD Register Busy Mask This bit is automatically reset when a block transfer is terminated O0 Mask interrupt to CPU 1 Do not mask interrupt 5 3 11 4 5 PCMCIA Mode Register PCMR Additional Bits bit 0 PCSTR PCMCIA DMA Start Operation 0 Stop PC DMA Controller 1 Start the operation on the PC DMA controller bit 1 IDOI IDMA Mode or Interrupt Mode 0 IDMA mode 1 68k Interrupt mode bit 2 PCDDIR PCMCIA DMA Direction 0 DMA write cycle the data flows from the PC card to the PC host 1 DMA read cycle the data flows from the PC host to the PC card bit 3 PCDSWP PCMCIA Data Swap 0 Do not swap data bytes 1 Swap data bytes bit 4 PC_DREQEN PCMCIA DMA Request Enable 0 PC_DREQ_ IDREQ _ PB8 pin is connected to IDMA PBIO8 and Interrupt Control ler The pin functions as interrupt if unmasked in interrupt controller as IDREQ_ if MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc IDMA is programmed for external request and as Parallel IO Its direction is deter mined by PBIO register programming 1 PC_DREQ _ IDREQ_ PB8 pin is output and functions as PC_DREQ_ The user should connect the pin either to SPKR or INPACK or IOIS16 NOTES Do not program PC_DREQEN 1 and PCSTR 1 during the
146. PCMCIA controller to signal ready high to the host When set to zero the PCMCIA controller will signal busy After reset the PCMCIA controller will set the RRdy Bsy pin low and clear this bit NOTE In O mode the RDY BSY pin becomes the IREQ pin RWProt When read this bit represents the internal state of the corresponding external signal When this bit is written as one the corresponding changed bit is also written Since the MC68PM302 does not support this pin directly external circuitry should be used to mon itor the state of this signal NOTE The 68000 should write the state of this signal into this location The corresponding changed bit will be updated according to the written data 5 3 10 4 Socket and Copy Register SCR SCR PCMCIA Address A25 1 6 68000 Address BAR 873 7 6 5 4 3 2 1 0 Read Write This register can be R W accessed by the PC and the 68000 core The 68000 core will re ceive an interrupt when this register is written by the PC See 5 3 5 PCMCIA Access Wake Up Event Register PCAWER MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller NOTE This is an optional register which the card may use to distinguish between similar cards installed in a system 5 3 10 5 I O Event Indication Register IOEIR IOEIR PCMCIA Address A25 1 8 68000 Address BAR 874 7 6 5 4 3 2 1 0 ResEvt3 ResEvt2 RIEvt
147. PC_EN 1 PC_EN 1 PC_EN 0 PC_EN 0 PC_EN 0 PC_EN 0 Pin Name DISCPU 0 DISCPU 0 DISCPU 1 DISCPU 1 DISCPU 0 DISCPU 0 DISCPU 1 DISCPU 1 TQFP PGA TQFP PGA TQFP PGA TQFP PGA PC_D7 FC DP A23 Pe br Reb Be Br RGD A23 a20 A23 A20 A23 A20 A23 A20 ompa e seer Seb SEB SB reer roro If 16bit 0 in If 16bit 0 in If 16bit 0 in If 16bit 0 in NMS12 PA7 NMSI3 PA7 NMSIO PA7 NMSI2 PAZ PC_D15 PC_D8 PAO PAO PAO PAO _ NMSI2 PA7 NMSI2 PA7 NMSI2 PA7 NMSI2 PA7 NMSI2 PA7 PAO if 16bit 1 in If 16bit 1 in If 16bit 1 in If 16bit 1 in PAO PAO PAO PAO le le ee PC_D8 PC D8 PC D8 PC D8 PC_WAIT BG PC_WAIT PC_WAIT PC_WAIT PC_WAIT BG BG BG BG PC STSCHGBR PC_STSCH PC_STSCH PC_STSCH PC_STSCH BA BA BA BA PC_RDY RW PC_RDY PC_RDY PC_RDY PC_RDY RW RW RW RW PC_IOWR DACK PA14 PC_IOWR PC_IOWR PC_IOWR PC_IOWR DACKI PA14 DACK PA14 DACK PA14 DACK PA14 PC_WE DONE PA15 PC_WE PC_WE PC_WE PC_WE DONE PA15 DONE PA15 DONE PA15 DONE PA15 PC_REG UDS AO PC_REG PC_REG PC_REG PC REG UDS ao UDS ao UDS AO UDS AO PC_OE BGACK PC_OE PC_OE PC_OE PC_OE BGACK BGACK BGACK BGACK PC_CET LDS DS PC_CET PC_CET PC_CET PC_CET LDS DS LDS DS LDS DS LDS DS PC_CEZAACKI PB2 PC_CE2 PC CE2 PC cE2 PC CE2 IACK1 PB2 TACKT PB2 TACKT PB2 TACKT PB2 PC_A25 ACK6 PB1 PC_A25 PC_A25 PC_A25 PC_A25 ACK6PB1 MACK6 PB1 AACK6 PB1 JACK6 PB1 PC_A11 IACK7 PBo PC_A11 PC_At1 Pc_Aa1
148. Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc for the following clock cycle 6 When AS and RAW are equally loaded 20 subtract 5 ns from the values given in these columns 7 The MC68PM302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting BGACK 8 The minimum value must be met to guarantee proper operation If the maximum value is exceeded BG may be reasserted MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics S0 S1 S2 S3 S4 S5 S6 S7 i IVT NAS NP FC2 FCO X O vy to A23 Al DATA IN 2 lt HALT RESET ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Setup time for the asynchronous inputs IPL2 IPLO guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 volt and a high voltage of 2 0 volts unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 volts and 2 0 volts Figure 7 2 Read Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www fre
149. R count value for the periodic timer These bits may be written only when the PIT is disabled PTEN 0 to modify the PIT count value NOTE If the PIT is enabled with the PTP bit is set the first interrupt can be up to 512 clocks early depending on the prescaler counter value when the PIT is enabled 3 8 EXTERNAL CHIP SELECT SIGNALS AND WAIT STATE LOGIC The IMP provides a set of four programmable chip select signals Each chip select signal has an identical internal structure For each memory area the user may also define an inter nally generated cycle termination signal DTACK This feature eliminates board space that would be necessary for cycle termination logic The chip select logic is active for memory cycles generated by internal bus masters M68000 core IDMA SDMA DRAM refresh PCMCIA controller or external bus masters A23 A20 are driven to zero internally and FC2 0 are driven to 5 These signals are driven externally on the falling edge of AS and are valid shortly after AS goes low NOTE For more information on the operation of the Chip Selects please refer to Section 3 of the MC68302 Users Manual Also note that A23 20 and FC2 0 are not driven externally un less the PCMCIA interface is disabled however these signals are still used internally by the chip selects for comparison In Disable CPU mode or for external bus masters A23 A20 are internally driven to zero so the user must program the corre sponding
150. S17 during the read cycle Read modify write cycle is generated only by the TAS instruction ARUN Figure 7 4 Read Modify Write Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc at the next falling edge of the clock CLKO NOTE Setup time to the clock 47 for the asynchronous inputs BERR BGACK BR DTACK AND IPL2 IPLO guarantees their recognition AND RAW BR INPUT STROBES Figure 7 5 Bus Arbitration Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 5 IMP AC Electrical Specifications DMA see Figure 7 6 and Figure 7 7 16 67 MHz 20 MHz at 25 MHz at Num Characteristic Symbol at 5 0 V 5 0 V 5 0 V Unit Min Max Min Max Min Max 80 REQ Asynchronous Setup Time see Note 1 tREQASI 15 15 10 ns 81 REQ Width Low see Note 2 tREAL clks 82 REQ Low to BR Low see Notes 3 and 4 tREQLBRL 2 2 2 clks 83 Clock High to BR Low see Notes 3 and 4 tcHBRL 30 25 20 ns Clock High to BR High Impedance see 84 Notes 3 and 4 agg tcHBRZ 30 25 20 ns BGACK Low to BR High Impedance see 85 Notes 3 and 4 Foote l tekLerz
151. SYN with a 0 01 uF capacitor as close as possible to the chip package 2 4 3 6 3 XFC This pin connects to the off chip capacitor for the PLL filter One terminal of the capacitor is connected to XFC the other terminal is connected to I QVCC 2 4 3 6 4 MODCLK MODCLK specifies what the initial VCO frequency is after a hardware reset if VCCSYN is tied high During the assertion of RESET the value of the VCCSYN and MODCLK input pins causes the PEN bit and the MF1 1 0 bits of the IMP PLL and Clock Con trol Register IPLCR 0F8 to be appropriately written VCCSYN and MODCLK also deter mines if the oscillator s prescaler is used After RESET is negated the MODCLK pins is ignored and becomes PA12 Table 2 2 shows the combinations of VCCSYN and MODCLK pins with the corresponding default settings 2 4 4 IMP Power Management The IMP portion of the MC68PM302 has several low power modes from which to choose 2 4 4 1 IMP LOW POWER MODES The MC68PM302 provides a number of low power modes for the IMP section Each of the operation modes has different current consumption wake up time and functionality characteristics The state of the IMP s 68000 data and address bus lines can be either driven high low or high impedance during low power stop mode by programming the low power drive control register LPDCR NOTE For lowest current consumption the SCCs and BRGs should be disabled before entering the low power modes Current con sumption for all
152. State tcHDTKL 45 40 30 ns 154 Clock Low to DTACK Low 1 6 Wait States teLDTKL 30 25 20 ns 155 Clock Low to DTACK High CLDTKH 40 35 27 ns 156 Clock High to BERR Low see Note 1 tCHBERL 40 35 27 ns 157 A A to BERR High Impedance see isem 40 35 _ 27 ns 158 DTACK High to DTACK High Impedance tptkHptKz 15 15 10 ns 171 Input Data Hold Time from S6 Low tiDHCL 5 5 5 ns 172 CS Negated to Data Out Invalid Write tcsnbol 10 10 7 ns 173 Address FC Valid to CS Asserted taFVCSA 15 15 15 ns 174 CS Negated to Address FC Invalid tosNAFI 15 15 12 ns 175 CS Low Time 0 Wait States tcsLT 120 100 80 ns 176 CS Negated to R W Invalid tcsnRWI 10 10 7 ne ns 177 CS Asserted to R W Low Write tcsaRwL 10 10 8 ns 178 S to Data In Invalid Hold Time i ehioil 0 ae 0 0 al ns Specified However CS timings are given relative to a number of other signals in the same manner as AS See Figure 7 2 and Figure 7 3 for diagrams S0 Sl S2 53 S4 S5 S6 S7 SO Sl S2 3 S4 Sw Sw S5 S6 S7 SO OUTPUT gt lt 50 CS0 CS3 OE 50 G gt pa IACK1 IACK6 IACK7 WEH WEL gt OUTPUT 9 gt Ke OUTPUT BERR OUTPUT Figure 7 14 Internal Master Chip Select Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteris
153. System Configuration Registers The BAR entry contains the BAR described in this section The SCR entry contains the SCR described in Section 3 System Integration Block SIB Figure 2 1 shows all the IMP on chip addressable locations and how they are mapped into system memory The on chip peripherals including those peripherals in both the communications processor CP and system integration block SIB require a 4K byte block of address space This 4K byte block location is determined by writing the intended base address to the BAR in super visor data space FC 5 In slave mode the FC2 0 pins are internally driven by the MC68PM302 to supervisor data space In enable CPU mode the Status Register of the M68000 should be set to supervisor mode in order to access the supervisor data space After a total system reset the on chip peripheral base address is undefined and it is not possible to access the on chip peripherals at any address until BAR is written The BAR and the SCR can always be accessed at their fixed addresses NOTE The BAR and SCR registers are internally reset only when a to tal system reset occurs by the simultaneous assertion of RESET MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freasgate senicenducter wid amp tG lt and Internal Memory Map SYSTEM MEMORY MAP EXCEPTION VECTOR TABLE 0F2 256 VECTOR ENTRIES 0F4 0F0 0F7 0F8 0FA 0
154. T mask reg ister is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt in the event register will be masked This register is cleared upon reset 4 3 9 Autobaud Controller New The autobaud function determines the baud rate and format of an asynchronous data stream starting with a known character This controller may be used to implement the stan dard AT command set or other characters In order to use the autobaud mode the serial communication controller SCC is initially pro grammed to BISYNC mode The SCC receiver then synchronizes on the falling edge of the START bit Once a START bit is detected each bit received is processed by the autobaud controller The autobaud controller measures the length of the START bit to determine the receive baud rate and compares the length to values in a user supplied lookup table After the baud rate is determined the autobaud controller assembles the character and compares it against two user defined characters If a match is detected the autobaud controller inter rupts the host and returns the determined nominal start value from the lookup table The autobaud controller continues to assemble the characters and interrupt the host until the host stops the reception process The incoming message should contain a mixture of even and odd characters so that the user has enough information to decide on the proper char acter format length
155. TSs The nominal START bit length is calculated by Nominal start length Sampling Rate Recognized baud rate 2 EQ 4 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP For the 115 2K example in the first table entry this would be 1 8432 MHz 115 2K 2 8 The structure of the lookup table is shown in Table 4 5 The table starts with the maximum UART baud rate supported and ends with the minimum UART baud rate supported Table 4 5 Autobaud Lookup Table Format OFFSET from Lookup Table Pointer DESCRIPTION 0 Maximum Start Length 2 Nominal Start Length 4 Maximum Start Length 6 Nominal Start Length Maximum Start Length Nominal Start Length Lookup Table Size 1 4 Maximum Start Length Lookup Table Size 1 4 2 Nominal Start Length NOTE If less margin is used in the calculation of the maximum start length above it is possible to distinguish between close UART rates such as 64K and 57 6K However variations in RS232 driv ers of up to 4 plus nominal clocking rate variations of 3 plus the fact that the sampling rate may not perfectly divide into the desired UART rate can make this distinction difficult to achieve in some scenarios 4 3 9 5 LOOKUP TABLE EXAMPLE Table 4 6 is an example autobaud lookup table The maximum start and nominal start val ues are derived assuming a 1
156. UAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller NOTE This mechanism is implemented only for PCMCIA common memory space accesses that are transferred into the 68000 bus Attribute space cycles are always made on a cycle steal basis I O space cycles are mode to the 16550 registers only 00 Cycle steal mode The 68000 bus is released after the cycle has been terminated The arbitration logic will arbitrate for the 68000 bus when next cycle starts CE ac tive 01 Burst mode The arbitration logic waits for 4 idle 68000 bus clocks on the PCMCIA bus before releasing the 68000 bus 10 Burst mode The arbitration logic waits for 8 idle 68000 bus clocks on the PCMCIA bus before releasing the 68000 bus 11 Burst mode The arbitration logic waits for 16 idle 68000 bus clocks on the PCM CIA bus before releasing the 68000 bus FAST Fast Burst Mode Setting this bit enables fast burst mode PCMCIA common memory accesses without the WAIT signal except for the first access When the PCMCIA controller is programmed to burst mode by setting the ArbIDL1 0 bits to non zero the burst can be done in two differ ent modes The first cycle with arbitration is identical in both modes 0 Normal mode When the PCMCIA controller is granted control of the 68000 bus and the PC initiates a common memory space cycle the PCMCIA controller asserts the WAIT signal on the PCMCIA lin
157. X XXX Table 5 3 Attribute Memory Space Map PC_CE1 PC_REG PC_OE PC_WE PC_A25 PC_AO 22090 Selected Register Address or Space CIS Base Reg FC A23 A11 k z k i x L II PCMCIA Address A0 A10 C S Memory Read CIS Base Reg FC A23 A11 L L H L L L PCMCIA Address A0 A10 CIS Memory Write L L L H H L PCMCIA Address A0 A7 ee guration Reais L L H L H L PCMCIA Address A0 A7 configuration Regs MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc 5 1 3 Card Information Structure The card information structure is a data structure at address 0 of attribute space in the card that contains information about the card and its capabilities The CIS will be located in 68000 bus memory space Location 0 of the CIS is pointed to by CISBAR Referring to Table 5 3 accesses to the CIS in attribute space are mapped into the 68000 address space with the concatenation of the CIS base address register CISBAR gt A23 A12 and the low address bits taken from the PCMCIA address lines PC_A11 PC_AO A25 must be equal to zero for CIS accesses to occur When the PC accesses the CIS by performing an attribute space read cycle to address 0 through 1FFFFFF A25 0 the PCMCIA controller detects the cycle asserts the WAIT sig nal on the PCMCIA lines and arbitrates for the 68000 b
158. al clocking for the part Further changes to the clocking scheme can be made by software After reset the 68000 core can control the IMP clocking through the following registers 1 IMP Operation Mode Control Register IOMCR 2 4 4 1 6 IMP Operation Mode Control Register IOMCR 2 IMP PLL and Clock Control Register IPLCR 2 4 3 4 Frequency Multiplication 3 IMP Interrupt Wake Up Control Register IWUCR 2 4 4 2 4 IMP Wake Up Control Register IWUCR 4 Periodic Interrupt Timer Register PITR See Section 3 System Integration Block SIB MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgate sericenducter wid amp G and Internal Memory Map MULTIPLICATION FACTOR DIVIDE FACTOR MF11 MFO DF3 DF0 IMP SYSTEM CLK OUT 0 25MHz IMP PLL VCO OUT En DIVIDE BY 2 Figure 2 2 MC68PM302 PLL Clock Generation Schematic p gt PIT CLOCK 2 4 2 1 DEFAULT SYSTEM CLOCK GENERATION During the assertion of hardware reset the value of the MODCLK and VCCSYN input pins determine the initial PLL settings according to Table 2 2 After the deassertion of reset these pins are ignored The MODCLK and VCCSYN pins control the IMP clock selection at hardware reset The IMP PLL can be enabled or disabled at reset only and the multiplication factor preset to support different industry standard crystals After reset the multiplication
159. al port RAM at the low end of system memory It then samples the PAS pin to determine the clock source for the UART NOTE PA5 is expected to be valid for 100 clocks after the negation of RESET If PA5 is pulled high SCC1 is programmed for external clocks In this mode the user has to connect an external clock 16 the bit rate to TCLK1 and RCLK1 If PA5 is pulled low the SCC is programmed for internal clocks and the TCLK1 and RCLK1 pins are programmed to three state to avoid contention with user clocks The RISC proces sor then programs the SCON register of the SCC based on PA12 The PA12 value sampled during reset MODCLKO is decoded in order to provide 9600 bps with two input frequen cies 4 192 Mhz and 32 768 Khz e If MODCLKO GND SCON1 is programmed to 0x00D8 e If MODCLKO VCC SCON1 is programmed to 0x00A8 The following baud rates are achieved as a function of VCCSYN MODCLK and input clock VCCSYN MODCLK 00 20 Mhz 11467 bps SCON1 0x00D8 10 4 192 Mhz 9614 bps SCON1 0x00D8 10 4 8 Mhz 11009 bps SCON1 0x00D8 11 32 768 Khz 9662 bps SCON1 0x00A8 The following paragraphs explain the boot process for the 32 768 Khz case in detail If the clock provided to the MC68PM302 is 32 768 KHz the system frequency is multiplied by 401 to get 13 139968 MHz The CD10 CD0O bits of the SCON are programmed to 84 decimal giv ing a UART frequency of 9662 In summary 13 139968 MHz 84 1 16 9662 If the starting frequency is
160. ammer Model 4 26 PC_A25 6 31 PC_CE1 6 31 PC_CE2 6 31 PC_D15 PC_DO0 6 30 PC_IORD 6 24 PC_IOWR 6 24 PC_OE 6 30 PC_RDY IREQ 6 32 PC_STSCHG 6 29 PC_WAIT 6 32 PC_WE 6 25 PCAWER 5 27 5 38 PCAWMR 5 28 5 39 PCDMAD 5 40 PCHER 5 29 PCM 4 2 PCM Highway 6 18 6 19 PCMCIA 5 1 Card Configuration and Status Register CCSR 5 32 Card Configuration Registers 5 3 Changed Bit 5 32 Common Memory Space Base Address Register CMBAR1 2 5 30 Configuration Index 5 32 Configuration Option Register COR 5 31 DMA Support 5 36 Enabling on Reset 6 1 6 7 I O Event Indication Register IOEIR 5 35 Internal Bus Arbitration 3 29 Interrupts 3 15 Level Mode Interrupts 5 32 PC_AO PC_A10 6 31 PC_A25 6 31 PC_CE1 6 31 PC_CE2 6 31 PC_D15 PC_D0 6 30 PCMCIA Access Wake Up Event Register PCAWER 5 27 PCMCIA Access Wake up Mask Register PCAWMR 5 28 Pin Replacement Register Organization PRR 5 33 PwrDwn 5 33 Rdy Bsy 5 34 Reserved Registers 5 36 Ring Indicate PB9 Connection Options 5 15 RingEn Bit 5 32 SigChg Bit 5 32 Socket and Copy Register SCR 5 34 SRESET 5 31 STAND BY 2 13 STSCHG pin 5 16 PCMCIA Controller 5 1 68000 Bus Arbitration Options 5 13 ABUF pin 5 10 Attribute 5 2 Attribute Memory Accesses 5 4 Attribute Memory Read 5 5 Attribute Memory Space Map 5 5 Attribute Memory Write 5 5 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Index Freesca
161. an multiply the CLKIN input fre quency by any integer between 1 and 4096 The multiplication factor may be changed to the desired value by writing the MF11 MFO bits in the IPLCR When the IMP PLL multiplier is modified in software the IMP PLL will lose lock and the clocking of the IMP will stop until MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgate senicenducter wid amp G lt and Internal Memory Map VCC 390pf x MF 0 1uF CRYSTAL z alle 20pf B 20pf 0 01 uF f 20 EXTAL XTAL XFC VCCSYN GNDSYN CRYSTAL OSCILLATOR VCC ICLVCG CLOCK GENERATION ICLGND 7 0 1uF j CLKO Figure 2 4 PLL External Components lock is regained worst case is 2500 EXTAL clocks If an alteration in the system clock rate is desired without losing IMP PLL lock the value in the low power clock divider can be to modified to lower the system clock rate dynamically The low power clock divider bits are located in the IOMCR register NOTE If IMP PLL is enabled the multiplication value must be large enough to result in the VCO clock being greater than 10 MHz 2 4 3 4 1 Low Power PLL Clock Divider The output of the IMP VCO is sent to a low power divider block The clock divider can divide the output frequency of the VCO before it generate
162. ansmission Bits 14 6 Reserved for future use should be set to zero by the user C I Command Indication Channel Data Bits 1 O These bits should be written with zeros by the M68000 core MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 5 PCMCIA CONTROLLER The MC68PM302 includes a PCMCIA interface implemented including the registers and signal pins necessary to provide a fully functional PC Card slave interface In addition there is amechanism which allows the PC to directly access resources on the 68000 bus MC68PM302 pm PCMCIA PC DMA DATA REGISTER lt CONFIGURATION REGISTERS 68000BUS DIRECTACCESS LOGIC 16550 REGISTERS FIFO PERIPHERAL BUS g Figure 5 1 PCMCIA Architecture MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc The following are PCMCIA controller key features Fully Supports PCMCIA Standard 2 1 Supports Five Configuration Registers Configuration Option Register Card Configuration and Status Register Pin Replacement Register Socket and Copy Register 1I O Event Indication Register Supports Attribute Common Memory and I O Space Access with Optional WAIT Hand shake Mechanism Common Memory Spaces Are Mapped into 68000 Space Using either of Two Common Memory Base Address Registers
163. are routed to the 16550 registers This signal may thus be asserted whenever the card enable CE1 and CE2 and the REG inputs are true Audio Digital Waveform SPKR replace BVD2 Binary audio output signal Card Reset RESET This signal clears the card configuration option register thus placing the card in an uncon figured memory only interface state A card remains in the unconfigured state until the card configuration register has been written In most cases this signal should trigger a reset sequence in the IMP External circuitry such as a one shot circuit will typically be required to assure that the IMP reset is asserted long enough to meet the 68000 minimum reset specifications see Section 7 Electrical Characteristics when the card is reset The card reset signal should be an input to the ex ternal reset circuitry in order to guarantee that the reset polarity and pulse times meet the requirements of the IMP 5 2 3 Pullup Control Register PUCR The PUCR contains control for the optional pullup resistors on pins with PCMCIA function ality This register can be read and written by the 68000 core A set bit disables the pullup for a particular block of pins A cleared bit enables the pullups in a particular block Some pins have pull ups available for non PCMCIA functionality and some do not as noted in the bit descriptions MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale
164. ata Driven PC_OE High to PC_Data Invalid PC_Data High Z from PC_OE High 49 50 51 52 PC_Address Setup before IOWR or IORD 353 PC_CE and PC_REG Setup before IOWR or IORD PC_OE Low to PC_ Data Valid 55 56 57 58 3 3 3 3 3 Clock Low to PC_ Data Valid 3 Minimum Pulse Width of PC_IOWR 3 3 3 PC_WAIT High to PC_Data Valid See note 6 PC_IORD High to PC_Data Invalid PC_IORD Low to PC_Data Valid MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 360 PC_IORD High to PC_data High Z 30 ns 361 PC_Data Setup before PC_IOWR Low 0 ns 362 PC_Data Hold from PC_IOWR High 0 ns 363 PC_Address PC_CE Hold from PC_IORD or PC_IOWR High 10 ns 364 PC_REG Hold from PC_IORD or PC_IOWR High 0 ns NOTES 1 Hold Time Required for Register Accesses Only 2 If the Asynchronous Input Setup 328 is met this value is 1 5 clks 10ns 3 Delay through chip assuming chip is driving PC_Data Bus 4 Hold Time Required for PCMCIA to 68k Bus Accesses 5 Max is Determined by PC Host Timing 6 PC_IO Cycles with PC_WAIT Enabled CLKO OUTPUT PC_A23 PC_All INPUT NOTE 1 PC_CE2 PC_CE1 INPUT PC_OE INPUT A23 A12 OUTPUT A11 A0 OUTPUT NOTE 3 AS LDS UDS OUTPUT OE OUTPUT
165. ate since the last time it was read by the PC This bit is reset to logic 0 whenever the PC reads the MSR register DDSR Delta Data Set Ready This bit indicates that the DSR bit has changed state since the last time it was read by the PC This bit is reset to logic 0 whenever the PC reads the MSR register TERI Trailing Edge of Ring Indicator This bit indicates that the RI bit has changed from high to low state This bit is reset to logic 0 whenever the PC reads the MSR register DDCD Delta Data Carrier Detect This bit indicates that the DCD bit has changed state This bit is reset to logic 0 whenever the PC reads the MSR register NOTE Whenever bits 0 1 2 or 3 are set to one a MODEM status inter rupt is generated to the PC MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkn escale Semiconductor Inc CTS Clear To Send This bit emulates the complement of the CTS input The 68000 core writes this bit If bit 4 loop of the MCR is set to 1 this bit is equivalent to RTS in the MCR DSR Data Set Ready This bit emulates the complement of the DSR input The 68000 core writes this bit If bit 4 loop of the MCR is set to 1 this bit is equivalent to DTR in the MCR Rl Ring Indicator This bit emulates the complement of the RI input The 68000 core writes this bit If bit 4 loop of the MCR is set to 1 this bit is equivalent to OUT 1 in the MCR
166. ation ssssssssnneseeesnrneeseerrrrnessserrrrreneeee 3 23 3 7 3 3 Using the Periodic Timer As a Real Time Clock cceseeeeeeeeeeeeees 3 24 3 7 3 4 Periodic Interrupt Timer Register PITR ccceecesseeeeeeeeeeeeeeeeeeees 3 24 3 8 External Chip Select Signals and Wait State Logic eeeeeee 3 25 3 8 1 Chip Select REGIStES wx acceccee ig eee fenterecs setter pkandsgecnccerecagyObaseecterecesaNetees 3 26 3 8 1 1 Base Register BRS BRO cccccceeeeeeeseeeeeeeeeeeeeeaeeeeeeeeeeeesnneeeeees 3 26 3 8 1 2 Option Registers ORS ORO scsi dean nGka 3 26 3 8 1 3 PCMCIA Protection Register PPR ccceeeeeeeeeeeeeeneeeeeeeeeeseeneeeeeees 3 27 3 8 2 Disable CPU Kogie MGSQ00 cectccsctccioteci atta ietesiseemhctatatcetarineectniethis 3 28 3 8 3 BUS Arbitration Logic s ccreity cece cette co ebtet decasee nienerre ean serene ee nian 3 29 3 8 3 1 Internal BUS Anan scutes eds aaaea aaaea egies ved EEEE R EEAS 3 29 3 8 3 2 External Bus Arbitration Using HALT 0 eccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 3 30 3 9 Dynamic RAM Refresh Controller cccccccceeeeeeeeeeeeeeeeeeeseeeseeeeeees 3 30 Section 4 Communications Processor CP 4 1 MC68PM302 Key Differences from the MC683802 sseeeeeeeeee 4 1 4 2 Serial Channels Physical Interface cccccsccceeeeeeeseeeceeeeeeeeeeneeeeees 4 2 4 2 1 Serial Interface Registers s oe fc xy Geecee sc dees es edceenc
167. be configured either as an input or an out MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc put When configured as an input this pin can generate a separate maskable interrupt on a high to low transition Refer to section 5 3 11 for further details on this pin muxing NOTE It is possible to enable Wake Up from Low Power when PIT is expired which replaces PB8 interrupt and have DREQ or PC_DREQ at the same system PB9 RI This pin may be configured as a general purpose parallel I O port with interrupt capability and wake up capability This pin can be configured either as an input or an output When configured as an input this pin can generate a separate maskable interrupt on a high to low transition This pin can also wake up the IMP from low power STOP DOZE or STAND BY mode when a high to low transition occurs on this pin when configured as an input See 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes for more information In addition when the MC68PM302 is configured for the PCMCIA interface this pin can be connected internally to the PCMCIA I O Event Indication Register or directly to the PC_STSCHG pin For more details on this feature refer to 5 1 9 PCMCIA Ring Indication PB10 This pin may be configured as a general purpose parallel I O port with interrupt capability and wake up capability This pin can be configured
168. bit In all systems the user programs the DMA Operand Address for the PC to 878 hex 1 In this system BUSW pin 0 and 16BIT 0 in the PCMR register The PCDSWP bit in PCMR is not used don t care The data flows from ID7 0 to PCD7 0 2 In this system BUSW pin 1 and 16BIT 1 in the PCMR register If the data is word oriented there is no need to swap it therefore PCDSWP 0 in PCMR Note that in this case no byte transfers occur If the data transferred is byte oriented the user needs to swap it PCDSWP 1 in PCMR PCDMAD bits 7 0 are transferred into ID bits 15 8 and PCDMAD bits 15 8 are transferred into ID bits 7 0 If an uneven number of bytes is transferred The data on ID7 0 is swapped to PCD15 8 Note that according to our assumption above all accesses in 16 bit systems are aligned to even addresses 3 In this system BUSW pin 1 and 16BIT 0 in the PCMR register The user programs the operand size for the PC and for the 68k to 8 bits SSIZE or DSIZE and PCDSWP 1 in PCMR The data flows from ID15 8 to PCD7 0 In Interrupt Polling mode the CPU has to perform packing and unpacking of the data 5 3 11 3 Description of Pin Reassignment For transfers from the PC Host to the 68K bus DMA support requires replacement of I O interface pins with DMA signals This specification describes the replacements as they apply to the MC68PM302 however it is up to the user to connect the pins of the chip to the correct signals on t
169. bitration or PCMCIA PINS 0 2eeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeee 6 29 6 1 23 IMP Bus Control or PCMCIA PINS ccceeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeee 6 30 6 1 24 IMP Address and Function Codes or PCMCIA Data 6 32 6 2 Summary of Pin Multiplexing sy fp seceececeseevsnc esceeesseeeceosseevivie nv eeesexecestens 6 32 6 3 Power and Ground PIN nersini aa n a eens 6 34 6 4 When to Use Pullup ReSistors ccccccceeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeees 6 34 Section 7 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Table of Contents Freescale Semiconductor Inc Paragraph Title Number Electrical Characteristics 7 1 Ma xin FRAMING S ei a a aaa a a Ea a iA E 7 2 Thermal Characteristics n2 2 c Ge Gaede vyencelewcusbidsa Cortvengaisgcaes 7 3 Power Considerations cccceeseessceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 7 4 Power Dissipation tartar ae eee ans ocean vans aetna 7 4 1 Layo t Practicas eeir Mace fetid ei at Ate heh eels eh add 7 4 2 Power Dissipation Considerations cescccceeeeeeeeeeeeeeeeeeeeeees 7 4 3 DC Electrical Characteristics ccceeeeeeseeceeeeeteeeeeeeeeeeeeeeeeeee 7 5 DC Electrical Characteristics NMSI1 in IDL Mode 0 7 6 IMP Characteristics 25 4 4cibcscd eos htestht oebeiapet i scnatiahiabosrdipebendenleteids 7 6 1 IMP AC Electrical Specifications Control Timing
170. ble for information on how they may be regained In addition to the internal dual port RAM a number of internal registers support the functions of the various M68000 core peripherals The internal registers see Table 2 6 are memory mapped registers offset from the BAR pointer and are located on the internal M68000 bus NOTE All undefined and reserved bits within registers and parameter RAM values written by the user in a given application should be written with zero to allow for future enhancements to the device MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgate senicenducter wid amp tG lt and Internal Memory Map 2 6 INTERNAL REGISTERS MAP Table 2 6 Internal Registers Map Description Reset Value Reserved Channel Mode Register Source Address Pointer Destination Address Pointer Byte Count Register Channel Status Register Reserved IDMA Function Code Register IDMA Reserved Int Cont Global Interrupt Mode Register Int Cont Interrupt Pending Register Int Cont Interrupt Mask Register ISR Int Cont In Service Register RINGOCR Low Power RINGO Control Register RINGOEVR Low Power RINGO Event Register RES Int Cont Reserved PACNT PIO Port A Control Register PADDR PIO Port A Data Direction Register Port A Data Register Port B Control Register Port B Data Direction Register Port B Data Register Low Power Drive Control Register PCMCIA protection regist
171. bled to generate interrupts at a one second rate The interrupt is generated in this case at a precise 1 second rate even if the interrupt is not serviced immediately A true real time clock is obtained if the current interrupt is serviced completely before the next one occurs 3 7 3 4 Periodic Interrupt Timer Register PITR The PITR contains control for prescal ing the periodic timer as well as the count value for the periodic timer This register can be read or written only during normal operational mode Bits 14 13 are not implemented and always return a zero when read A write does not affect these bits PITR 0FO 15 14 13 12 11 10 9 8 PTEN 0 0 PTP PITR10 PITR9 PITR8 PITR7 RESET 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PITR6 PITR5 PITR4 PITR3 PITR2 PITR1 PITRO RESET 0 0 0 0 0 0 0 0 Read Write MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB PTEN Periodic Timer Enable This bit contains the enable control for the periodic timer 0 Periodic timer is disabled 1 Periodic timer is enabled PTP Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer 0 Periodic timer clock is not prescaled 1 Periodic timer clock is prescaled by a value of 512 PITR10 O Periodic Interrupt Timer Register Bits These bits of the PITR contain the remaining bits of the PIT
172. buffer descriptor This bit is reset when the PC reads the LSR register In FIFO mode the framing error bit is set when the character associated with the framing error moves to the top of the FIFO Break Interrupt Bl This bit is set by the 68000 core by issuing the STOP TRANSMIT command This bit is reset when the PC reads the LSR register In FIFO mode this error bit will be set when MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP the character associated with the error moves to the top of the FIFO When break occurs only one character is written into the FIFO NOTE Bits 1 4 are error bits that produce a receiver line status interrupt whenever one of these bits is set and the interrupt is enabled Transmitter Holding Register Empty THRE 0 The transmitter holding register is written by the PC In the FIFO mode at least one byte is written to the FIFO 1 The transmitter is ready to accept a new character A character is transferred from the transmitter holding register to the transmitter shift register emulation In the FIFO mode the Tx FIFO is empty Transmitter Empty TEMT 0 The transmitter holding register contains a character In the FIFO mode at least one byte is written to the FIFO 1 The transmitter holding register and the transmitter shift register emulation are both empty In the FIFO mode the Tx FIFO is empt
173. c ccccceeeeeseceeeeeeeeeeeaeeeeeeeeeseseeeeeeeeeesaaaees 2 12 2 4 4 1 1 STOP MOJE ener ne ree ree eee err eee Ore tee Err ere eee ee 2 13 2 4 4 1 2 DOZE Modeno aa e a E 2 13 2 4 4 1 3 SAPAND EA ASS lee EE ES EEEE ENEE 2 13 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Table of Contents Freescale Semiconductor Inc Paragraph Title Page Number Number 2 4 4 1 4 OW AO MOOS rece sia tears cedeee aera ae Ach cadena aeweh ee aides 2 13 2 4 4 1 5 NORMAL Mod 2 ses iovcterascrardsmianutecra matters int srencianccaine ulescenaneing 2 14 2 4 4 1 6 IMP Operation Mode Control Register IOMCR ceceeeeeeereeeeeee 2 14 2 4 4 1 7 Low Power Drive Control Register LPDCR eeeeeeeeeeeeeeeeeeees 2 14 2 4 4 1 8 IMP Power Down Register IPWRD cceeeeeeeeeeeeeeeeeeeeetneeeeeeeteees 2 15 2 4 4 1 9 Default Operation Modes ccceeeseenennnneeeeeeeeeeeeeeeeeeeeeeseeeeessseee 2 15 2 4 4 2 Low Power SUDDOM sein ncit ee tucor eh cite T a dati ee tet 2 15 2 4 4 2 1 Enter the SLOW GO mode 5 esicieirvcs icyeatdten caret vce vecsase adders wie ob sae etets 2 15 2 4 4 2 2 Entering the STOP DOZE STAND_BY Mode ceeeeseeeeeeeeeees 2 15 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes ccccceeeeeeteeeeeeeeeees 2 17 2 4 4 2 4 IMP Wake Up Control Register IWUCR eee eeeeeeeeeeeeeeeetteeeeeeeeeeee 2 17 2 4 4 3 Fast Wake UD reaa ces
174. ce Address Pointer Register SAPR cceeeeeeeeeeeeeeeeeeeeeeeeees 3 13 3 4 1 3 Destination Address Pointer Register DAPR cceeeeeeeeeeeeeeeees 3 13 3 4 1 4 Function Code Register FOR ccccceeessseceeeeeeeeseeeeeeeeeeeesesseeeeees 3 14 3 4 1 5 Byte Count Register BCR 2 0 casero Aue cae iva e es 3 14 3 4 1 6 Channel Status Register CSR eecccccceceeeseeeeeceeeeeeeeeeeeeeeeeeeeenaaeees 3 14 3 4 2 Interface Signal Sei E E e 3 14 3 5 Interrupt Controller stosccctvnnsecpacecticiewss cmemsicenetecleey ieee olen evedanntdusoe beaters 3 15 3 5 1 Interrupt Controller Key Differences from the MC68302 e 3 15 3 5 1 1 Interrupt Controller Overview ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenees 3 15 3 5 2 Interrupt Controller Programming Model cccccceeeeeeeeeeeeteeeeeeeeeee 3 15 3 5 2 1 Global Interrupt Mode Register GIMR eeeeeeeeeeeeeeeeeeeeeeeeeeeaeees 3 15 3 5 2 2 Interrupt Pending Register IPR cc cceeeeeeeeseeeeeeeeeeseeaeeeeeeeeeeees 3 16 3 5 2 3 Interrupt Mask Register IMR cccsssssseceeeeeeeeeeeeeeeeeeeesaeeeeeeeeeeees 3 17 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Paragraph Title Page Number Number 3 5 2 4 Interrupt In Service Register ISR ccceeeeeeeseeeeeeeeeeeeseaeeeeeeeeeeee
175. cessor MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction Three Independent Full Duplex Serial Communications Controllers SCCs Supporting Various Protocols High Level Synchronous Data Link Control HDLC SDLC Universal Asynchronous Receiver Transmitter UART Binary Synchronous Communication BISYNC Transparent Modes Autobaud Support Instead of DDCMP and V 110 Boot from SCC Capability Six Serial DMA Channels for the Three SCCs Flexible Physical Interface Accessible by SCCs Including ISDN Support Motorola Interchip Digital Link IDL General Circuit Interface GCI Also Known as IOM 2 Pulse Code Modulation PCM Highway Interface Nonmultiplexed Serial Interface NMSI Implementing Standard Modem Signals SCP for Synchronous Communication Two Serial Management Controllers SMCs To Support IDL and GCI Auxiliary Channels e PCMCIA Controller Supports Slave Interface Having 8 or 16 bit Data Pins Compatible with the PC Card Classic Specification Approved in October 1994 Support for Ring Detect and Other Indications Support for Power Down Modes and Automatic Wakeup on Host Access Card Information Structure CIS Size and Location In Memory Programmable Supports DMA Accesses as Defined by PCMCIA Supports Direct Access to Common Memory Space for High Speed Buffer Transfers Security Option to Prevent Host Accesses to Sensitive Address Ran
176. clock recovery from the external crystal or oscillator NOTE If the SCCs use the internal clock or if they use external clock and the Ringo external frequency ratio does not comply with the MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freagsgate senicenducter wid amp G lt and Internal Memory Map 1 2 5 maximum ration specification then they cannot be en abled until the real clock has resumed operation The criteria for enabling Ringo and waking up the CPU by giving it an interrupt are RINGOEN 1 and an unmasked event in the PCMCIA access wake up event register PCAWER occurs RINGOEN 1 and an unmasked PITEv PB10Ev or PB9Ev event occurs please re fer to the IWUCR register The internal ring oscillator is not enabled if the PLL is disabled A system with the PLL dis abled has to have an external oscillator connected in order to shorten the wake up time There are two possible interrupts to the CPU from the Ringo logic Interrupt when Ringo is enabled the CPU is always interrupted when Ringo starts oscillating RINGOEN bit enables both ring oscillator and enables the interrupt to the CPU Event bits for this interrupt are all wake up events Maskable interrupt when the system clock switches to the real clock The event bit for this interrupt is in the ring oscillator event register The Ringo interrupts can be either at level 1 6 or 7 according to RI
177. controller generates the LCR interrupt if enabled This enables the 68000 core to measure the BREAK length DLAB Divisor Latch Access Bit The PC must set this bit to one to access the divisor latches during a read or write oper ation The PC must set this bit to zero to access the receiver buffer the transmitter holding register or the interrupt enable register 4 4 4 1 2 Line Status Register LSR Read Only LSR Base 8F6 7 6 5 4 3 2 1 0 RX FIFO TRANSMITTE EO LANE BREAK FRAMING PARITY OVERRUN DATA READY ERROR R EMPTY INTERRUPT ERROR ERROR ERROR REGISTER RESET 0 o 0 0 0 0 0 0 Read Only by the PC 68000 can set the Overrun bit Data Ready 0 The receiver data register or FIFO is empty 1 A character has been transferred by the RISC controller into the receiver data reg ister or FIFO Overrun This bit is set by the 68000 core when the transmit buffer has not been transmitted for a long period of time It is done to emulate the 16550 Rx FIFO overrun This bit is reset when the PC reads the LSR Parity Error This bit is set by the 68000 core by setting the P bit in the transmit buffer descriptor This bit is reset when the PC reads the LSR In FIFO mode the parity error bit will be set when the character associated with the parity error moves to the top of the FIFO Framing Error This bit is set by the 68000 core indirectly when the 68000 core sets the FR bit in the trans mit
178. cs CLKO OUTPUT PC_A11 PC_ INP PC_CE2 P PC_D15 PC_D0 OUTPUT PC_CE2 P NPU PC_D15 PC_D0 INPUT Figure 7 32 PCMCIA I O 16550 Emulation Write MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc Figure 7 33 PCMCIA to 68K Arbitration MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INDEX Numerics 16550 16550 Command Set 4 38 16550 Specific Parameter RAM 4 35 16550 Transmit Commands 4 38 Memory Map 4 35 16550 Emulation Controller 4 23 16550 Control Characters 4 39 16550 Control Characters Receiver 4 39 16550 Error Handling 4 41 16550 Event Register 4 45 16550 Mask Register 4 47 16550 Receive Commands 4 39 16550 Rx Buffer Descriptor 4 42 16550 Status Register 4 47 16550 Tx Buffer Descriptor 4 43 68000 Programming Model 4 35 Access through the PCMCIA Interface 4 24 Block Diagram 4 25 BREAK Support Receiver 4 41 BRG 4 37 Configuring SCC2 for 16550 Mode 4 35 Divisor Latch LM DLM 4 34 Divisor Latch LS DLL 4 34 Emulation Mode Register EMR 4 36 ENTER HUNT MODE Command 4 39 Features 4 23 FIFO Control Register FCR 4 29 FIFOs 4 24 IDLE Sequence Receive 4 41 I
179. ct is MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB used the D TACK generator will insert wait states on both the read and write portion of the cycles The assertion of the internal RMC by the M68000 core is seen by the arbiter and will pre vent the arbiter from issuing bus grants until the completion of M68000 initiated locked read modify write activity After system reset this bit defaults to zero EMWS External Master Wait State EMWS Valid only in Disable CPU Mode When EMWS is set and an external master is using the chip select logic for DIACK gen eration or is synchronously reading from the internal peripherals SAM 1 one additional wait state will be inserted in every memory cycle to external memory and peripherals and also in every cycle to internal memory and peripherals When EMWS is cleared all syn chronous internal accesses will be with zero wait states and the chip select logic will gen erate DIACK after the exact programmed number of wait states The chip select lines are asserted slightly earlier for internal master memory cycles than for an external master EMWS should be set whenever these timing differences will necessitate an additional wait state for external masters After system reset this bit defaults to zero ADCE Address Decode Conflict Enable 0 BERR is not asserted by a conflict in the chi
180. cycles after the PLL locks if the PLL is enabled by the MODCLK pins WDOG is never asserted by the on chip hardware watchdog see the BERR signal description The WDOG pin function is enabled after a total system re set It may be reassigned as the PB7 I O pin in the PBCNT register 6 1 20 Parallel I O Pins with Interrupt Capability The four parallel I O pins with interrupt are shown in Figure 6 16 IDREQ PC_DREQ PB8 lt a RI PB9 lt PB10 lt PB11 Figure 6 16 Port B Parallel I O Pins with Interrupt PB11 and PB8 Port B Parallel I O Pins These four pins may be configured as a general purpose parallel I O ports with interrupt capability Each of the pins can be configured either as an input or an output When con figured as an input each pin can generate a separate maskable interrupt on a high to low transition PB8 may also be used to request a refresh cycle from the DRAM refresh controller rather than as an I O pin IDREQ PC_DREQ PB8 If the PC_DMA function is enabled this pin is an output and functions as PC_DREQ The user can connect it to SPKR INPACK or IOIS16 pins on the PCMCIA Connector see PC MCIA Draft on DMA If the PC_DMA function is not enabled this pin may be configured as a general purpose parallel I O port with interrupt capability if enabled in the Interrupt Controller or as DREQ input to the IDMA if enabled in the IDMA The user should en able either the Interrupt or IDMA This pin can
181. d for both sync methods 4 Where P 1 CLKO Thus for a 25 MHz CLKO rate P 40 ns MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc LICLK INPUT L1SY0 1 INPUT LITXD OUTPUT LIRXD INPUT LICLK INPUT LISY 0 1 INPUT LITXD OUTPUT LIRXD INPUT NOTE If L1SYn is guaranteed to make a smooth low to high transition no spikes while the clock is high setup time can be defined as shown min 20 ns Figure 7 23 PCM Timing Diagram SYNC Prior to 8 Bit Data MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc c lectrical Characteristics 7 6 18 IMP AC Electrical Specifications NMSI Timing The NMSI mode uses two clocks one for receive and one for transmit Both clocks can be internal or external When the clock is internal it is generated by the internal baud rate gen erator and it is output on TCLK or RCLK All the timing is related to the external clock pin The timing is specified for NMSI1 It is also valid for NMSI2 and NMSI3 see Figure 7 24 16 67 MHz 16 67 MHz 20 MHz 20 MHz 25 MHz 25 MHz Internal External Internal Characteristic Clock Clock Clock External Internal External Clock Clock Clock Min Max Min Max RCLK1 and TCLK1 Fre quency see Not
182. d on the PCMCIA cycle to delay the completion of the cycle This can be done by making sure that the NWAIT bit in the 16550 emulation mode register is reset MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP 68000 BUS PCMCIA Bus LINE STATUS 16550 EMULATION REGISTER MODE REGISTER LINE CONTROL REGISTER DIVISOR LATCH MSB DIVISOR LATCH LSB 16550 EVENT REGISTER INTERRUPT ENABLE INTERRUPT REGISTER CONTROL ae IREQ INTERRUPT ID AND INTR 16550 STATUS REGISTER BIT IN CCSR 16550 MASK REGISTER LOGIC REGISTER RTS DTR OUT1 OUT2 MODEM CONTROL REGISTER CTS DSR DCD RI yp MODEM STATUS REGISTER TRANSMITTER HOLDING REGISTER PERIPHERAL TRANSMITTER BUS Jf FIFO SELECT FIFO CONTROL REGISTER RECEIVER FIFO SELECT RECEIVER HOLDING REGISTER Figure 4 10 16550 Emulation Controller Block Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Peripheral PCMCIA Bus a lt 8 a 16x8 Data Bits wW w RISC Data Bus S HE gt 2 2 Read Write Pointer Pointer FIFO Control RISC Request m 4Bit Counter BRG Fi
183. disabled In disable CPU mode CS3 CS0 are disabled at system reset The chip select does not require disabling before changing its parameters 3 8 1 2 Option Registers OR3 ORO These four 16 bit registers consist of a base address mask field a read write mask bit a compare function code bit and a DIACK gen eration field 15 13 12 2 1 0 DTACK BASEADDRESS MASK M23 M13 MRW CFC Bits 15 12 DTACK Field These bits are used to determine whether DTACK is generated internally with a program mable number of wait states or externally by the peripheral MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB Table 3 4 DTACK Field Encoding Description 0 No Wait State 1 1 Wait State 0 2 Wait States 1 3 Wait States 0 4 Wait States 1 0 1 5 Wait States 6 Wait States External DTACK Bits 12 2 Base Address Mask These bits are used to set the block size of a particular chip select line The address com pare logic uses only the address bits that are not masked i e mask bit set to one to de tect an address match 0 The address bit in the corresponding BR is masked 1 The address bit in the corresponding BR is not masked MRW Mask Read Write Should be disabled in enable CPU enable PCMCIA mode if an external master uses the CS logic for its memory space 0 The RW
184. dition to the IMP PLL BCD BRG Clock Divide Control This bit controls whether the divide by two block shown in Figure 2 2 is enabled 0 The BRG clock is divided by 1 1 The BRG clock is divided by 2 LPM Low Power Modes When the 68000 core executes the STOP instruction the IMP will enter the specified mode LPM1 0 00 Normal the IMP PLL and clock oscillator will continue to operate normally 01 Stand_by Mode 10 DOZE Mode 11 Stop Mode 2 4 4 1 7 Low Power Drive Control Register LPDCR This register controls the state of the IMP s 68000 address and data buses during the Standby Doze and Stop modes By programming this register it is possible to minimize power consumption due to external pul lups or pull downs or floating inputs MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgate senicenducter wid amp G lt and Internal Memory Map LPDCR BAR 82A 7 6 5 4 3 2 1 0 LPAL LPDL LPDEN aa 0 0 0 0 0 0 0 Read Write LPDEN Low Power Drive Enable 0 The IMP 68000 data and address buses will be high impedance 1 The IMP 68000 data and address buses to be driven according to the LPDL bit LPDL Low Power Drive Data Low 0 The data bus will be driven high when the LPDEN bit is set 1 The data bus will be driven low when the LPDEN bit is set LPAL Low Power Drive Address Low 0 The address bus will be drive
185. e BA CHARACTER6 Word CONTROL Character 6 SCC Base BC CHARACTER7 Word CONTROL Character 7 SCC Base BE CHARACTER8 Word CONTROL Character 8 Should be initialized by the user M68000 core 4 3 11 2 BISYNC MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The term BISYNC mode reg ister refers to the protocol specific bits 15 6 of the SCC mode register when that SCC is configured for BISYNC The read write BISYNC mode register is cleared by reset 15 14 13 12 11 10 9 8 7 6 5 0 PM EXSYN NTSYN REVD BCS Z RTR RBCS SYNF ENC COMMON SCC MODE BITS MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP 4 3 11 3 BISYNC RECEIVE BUFFER DESCRIPTOR RX BD The CP reports information about the received data for each buffer using BD The Rx BD is shown in Figure 4 6 DATA LENG RXBUFFER POINTER 24 bits used upper 8 bits must be 0 Figure 4 6 BISYNC Receive Buffer Descriptor 4 3 11 4 BISYNC TRANSMIT BUFFER DESCRIPTOR TX BD Data is presented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the chan nel s Tx BD table The Tx BD is shown in Figure 4 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 R X W l L
186. e It then generates a 68000 cycle When the cycle is terminated with DTACK data is transferred to the PCMCIA data lines and the WAIT signal is negated 1 Fast mode This mode is used to minimize the usage of the WAIT signal on the PCMCIA interface allowing fast direct access transfers to be performed In this mode when the PC MCIA controller is granted control of the 68000 bus and the PC initiates a common memory space cycle the PCMCIA controller will not assert the WAIT signal on the PCMCIA line The cycle on the 68000 bus will use the memory interface signals WE and OE but not the DS The cycle will be terminated when the PCMCIA cycle is terminated The PCMCIA controller timing ignores DIACK and BERR so if 68000 bus cycles are not complete when the PCMCIA bus cycle is terminated gar bage data will result 68000 Bus Errors can be reported to the host by setting the BERRIE bit in the PCMR Fast mode accesses are only allowed for external mem ory space accesses Accesses to internal memory space will result in erratic oper ation INTRL Interrupt Level The PCMCIA control logic will generate an interrupt to the 68000 core when the host writes one of the configuration registers if its interrupt mask bit is set in the PCMCIA Con MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc figuration Registers Write Mask Register PCRWMR
187. e 1 RCLK1 and TCLK1 Low see Note 4 RCLK1 and TCLK1 High RCLK1 and TCLK1 Rise all Time see Note 3 TXD1 Active Delay from TCLK1 Falling Edge RTS1 Active Inactive Delay from TCLK1 Falling Edge CTS1 Setup Time to TCLK1 Rising Edge RXD1 Setup Time to RCLK1 Rising Edge RXD1 Hold Time from RCLK1 Rising Edge see Note 2 CD1 Setup Time to RCLK1 Rising Edge NOTES 1 The ratio CLKO TCLK1 and CLKO RCLK1 must be greater than or equal to 2 5 1 for external clock The input clock to the baud rate generator may be either an internal clock or TIN1 and may be as fast as EXTAL However the output of the baud rate generator must provide a CLKO TCLK1 and CLKO RCLK1 ratio greater than or equal to 3 1 In asynchronous mode UART the bit rate is 1 16 of the TCLK1 RCLK1 clock rate 2 Also applies to CD hold time when CD is used as an external sync in BISYNC or totally transparent mode Oo Schmitt triggers used on input buffers Where P 1 CLKO Thus for a 25 MHz CLKO rate P 40 ns MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc lt gt RTS1 OUTPUT CTs1 INPUT TXD1 OUTPUT Figure 7 24 NMSI Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com CD1 INPUT
188. e 3 17 3 6 Parallel VO POS nenna a aa aa aaa a 3 17 3 6 1 POMA a as ar eed ec a e aAa a a A aAa ETA 3 17 3 6 2 Pork Beeria ee eee A E re ee EE ERS 3 18 3 6 2 1 PB PBO a a T E a EE e a eai 3 18 3 6 2 2 Aea S i DO EEE EEEE EEE E EE ESEE E EEEE 3 19 3 6 3 POM D E AE E E chin suatanse acetieteetineasentts 3 19 3 6 4 Port Registe Sea Ea aa aE aaa aaae ra ealant adai 3 19 3 7 EE T E E E AET 3 20 3 7 1 General Purpose Timers Programming Model cecceeeeeeeeeetees 3 20 3 7 1 1 Timer Mode Register TMR1 TMR2 cccceeeeeeeeeeeeeeeeeeeeneeeeeeeeeees 3 20 3 7 1 2 Timer Reference Registers TRR1 TRR2 ccceeeeeeeseeeeeeeeeeeeees 3 21 3 7 1 3 Timer Capture Registers TCR1 TOR2 cccceecceeeeeeeeeeeeeeeeneeeeeeeeeees 3 21 3 7 1 4 Timer Counter TCN1 TON2 seit cietes tires cgetiene vat cceeecipedenuer en ceweetty 3 21 3 7 1 5 Timer Event Registers TER1 TER2 ccccceeseeeeeeeeeeeeeeeneeeeeeeeeees 3 21 3 7 2 Timer 3 Software Watchdog Timer ccccceeeeeeeeeeeeeeeeeeeneeeeeeeeeeees 3 22 3 7 2 1 Software Watchdog Reference Register WRR eceeeeeeeeeeeees 3 22 3 7 2 2 Software Watchdog Counter WON cccceceeeeeeeeeeeeeeeeeeeeeeeeeeenaaees 3 22 3 7 3 Periodic Interrupt Timer PE iisecccctics te tantets cere teeins tte tent caees urease 3 22 3 7 3 1 COVGI VIO Wi sect hn Shes Wes ods Jak aerate Seay scales enema AEE EE AARAA N 3 23 3 7 3 2 Periodic Timer Period Calcul
189. e PCHER which will cause the IREQ pin to assert 3 When an unmasked 16550 interrupt is issued from the 16550 controller the INTR bit in the CCSR will be set and the IREQ pin will be asserted MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller POW J9MOd MO7 4X3 pue 419 UW 0 Hq UMGIMd y Husn 2 s npl 9UulINOI OUI 34 Seysiul pue 4q Asg Apy S S 00089 UL a O HHd Ou Buum Aq uq pabueyo y S ULI Od OYI MON p uryo 4q AsgApy 9y snes q uiebe jas s jiqpebueyd O AsgApy jo uonebou 10 uow 0 HHd pea ued y Ing Asnq sS yiq AsgApy y snes q yq pebueyD y Jeses JoUULD Od L pebueyd q si S S 1 IeMYOS Dd s s osie yq pebueyo eu ig paBueyg 2d pue 1q Asg Apy 24 Ss s 1 YHS99 ul 4q Asq Apy ye sS gt 19 04 7U00 VIDNOd 94 S S IQ UMQIMd USUM dOLS 1 mod mo 0 UONISULJIL Asnq 0 s 1 S 4q ASgApy yL dnuaju Ue s eiauab pue dWI 24 dn seyem asempsey dI 3UL 55 i p jqeu p Apea 01 188 S Wq ASGAPH SUL WH WIOINOd au q uonisue1 siy HUNG apOW dOLS 19M0 MO 0 dINI 24 SUOIISUeI A noo pardnueiul S 00089 34L OJJUOD JOMOd MOJ y pue 4q UMUMA aU S S 1 Jd UL opene S uogonysu dOLS UL 621 YSOO u 4q UM 1Md S S Od
190. e STSCHG pin will be driven low Writing one to this bit will clear it to zero Writing a zero to this bit has no effect RIEvt This bit is latched to a one by the MC68PM302 on the start of each cycle of the ring fre quency on the phone line When this bit is set to a one and the RIEnab bit will be set to a one the changed bit in the card configuration and status register will also be set to a one If the SigChg bit in the card configuration and status register CCSR has also been set by the PC then the STSCHG pin will be driven low Writing one to this bit will clear it to zero Writing a zero to this bit has no effect MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc NOTE If it is desired to have the 68000 core debounce or otherwise process the RI signal before passing it to the host the RISDIS bit can be set in the PCMR register which will disconnect the di rect connection to the RIEvt bit See Figure 5 6 ResEnab3 Reserved for future expansion definition Set to zero ResEnab2 Reserved for future expansion definition Set to zero PiEnab Setting this bit to a one enables setting the changed bit in the card configuration and sta tus register when the PIEvt bit is set When this bit is cleared to a zero this feature is dis abled The state of PIEvt bit is not affected by this bit RlEnab Setting this bit to a one enables se
191. e configured as dedicated on chip peripheral pins if the corresponding PACNT bit is set When acting as a general purpose I O pin the signal direction for that pin is deter mined by the corresponding control bit in the port A data direction register PADDR Note MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc that these port pins do not have internal pullup resistors for non PCMCIA mode If a port A pin is selected as a general purpose O pin it may be accessed through the port A data register PADAT Table 3 2 Port A Pin Functions PACNT Bit 1 PACNT Bit 0 Input to Pin Function Pin Function SCC2 SCC3 IDMA RXD2 PAO GND TXD2 PA1 RCLK2 GND TCLK2 RCLK2 CTS2 GND RTS2 CD2 SDS2 BRG2 Allows a single external clock source on the RCLK pin to clock both the SCC receiver and transmitter 3 6 2 Port B Port B has 12 pins PB7 PBO may be configured as general purpose I O pins or as dedi cated peripheral interface pins whereas PB11 PB8 are always maintained as four general purpose pins each with interrupt capability NOTE PB2 0 and PB4 are only available when the PCMCIA interface is disabled 3 6 2 1 PB7 PBO Each port B pin may be configured as a general purpose I O pin or as a dedicated peripheral interface pin PB7 PBO functions exactly like PA15 PAO
192. e set If the SigChg bit in the CCSR has been set to one also the STSCHG pin will be driven low In addition the PC may poll the RIEvt bit in the IOEIR register or the changed bit in the CCSR at all times When the host detects the RI it should clear out the RIEvt bit The 68000 may poll or take an interrupt off of the RI in the port B data register PB9 and update the RIEvt bit in the IOEIR This allows the 68000 software to debounce or otherwise process the RI signal to detect a valid ring signal before passing it on to the PC The RISWDIS bit in the PCMR register should be set which will break the direct connection of the RI signal to the RIEvt bit in the IOEIR register see Figure 5 6 Connect the RI directly to the STSCHG pin by setting RingEn bit in the CCSR This mode complies with Intel ExCA specification for host RI using STSCHG When the RingEn bit in the CCSR register is set to one by the PC the STSCHG line reflects the state of the RI PB9 pin all other status change events are disabled When the Rin gEn bit is zero this function is disabled 5 1 9 1 Wake Up Using the PwrDwn Bit The host can wake up the card from any of the three STOP modes by resetting the PwrDwn bit in the CCSR The IMP system clocks will start up and the 68000 core will receive an in terrupt Resetting the PwrDwn bit will set the RDY Bsy bit to zero in the pin replacement reg ister The 68000 core should set the RDY Bsy bit to one upon completing i
193. ector generation is used The PC_A11 input is driven by the PCMCIA card interface See Section 5 PCMCIA Con troller IIACK6 PB1 PC_A25 Interrupt Acknowledge or Port B I O or PCMCIA Address IACKG6 is an active low output signal that indicates to the external device that the IMP is executing an interrupt acknowledge cycle The external device must then place its vector MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc number on the lower byte of the data bus or use AVEC for autovectoring unless internal vector generation is used The PC_A25 PCMCIA card interface input address line is used together with the PC_REG signal to identify different memory regions See Section 5 PCMCIA Controller IACK1 PB2 PC_CE2 Interrupt Acknowledge or Port B I O or PCMCIA Control IACK1 is an active low output signal that indicates to the external device that the IMP is executing an interrupt acknowledge cycle The external device must then place its vector number on the lower byte of the data bus or use AVEC for autovectoring unless internal vector generation is used The PC_CE2 interfaces to the PCMCIA Connector and is asserted by the PC Host when it selects the Card 6 1 19 Timer Pins The timer pins are shown in Figure 6 15 q gt TIN1 PB3 PC_A10 1TOUT1 PB4 lt a TRIS TIN2 PB5 PC_EN TOUT2 PB6 lt a WDOG PB7 Figure 6 15 Timer P
194. ee the previous description TCLK3 acts as the SCC3 baud rate gen erator output if SCC3 is in one of the multiplexed modes e RXD3 PA8 e TXD3 PA9 e RCLK3 PA10 e TCLK3 PA1 1 SPRXD CTS3 SCP Receive Serial Data NMSI3 Clear to Send Pin This signal functions as the SCP receive data input or may be used as the NMSI3 CTS input pin SPTXD RTS3 SCP Transmit Serial Data NMSI3 Request to Send Pin This output is the SCP transmit data output or may be used as the NMSI3 RTS pin SPCLK CD3 SCP Clock NMSI3 CD Pin This bidirectional signal is used as the SCP clock output or the NMSI3 CD3 input pin MODCLK PA12 BRG3 Port A Bit 12 SCC3 Baud Rate Generator This pin functions as bit 12 of port A or may be used as the SCC3 baud rate generator output clock when SCC3 is operating in NMSI mode MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc NOTE This pin is sampled at reset Refer to section 6 1 1 for further de tails 6 1 17 IDMA or Port A Pins or PCMCIA Pins The IDMA or port A pins are shown in Figure 6 13 4 DREQ PA13 PC_IORD DACK PA14 PC_IOWR lt gt DONE PA15 PC_WE Figure 6 13 IDMA or Port A Pins Each of these three pins can be used either as dedicated pins for the IDMA signals or as general purpose parallel I O port A pins Note that even if one or more of the IDMA pins are used as general purpose I O pins the IDMA can st
195. eeeaeeeeeeeeeenaeeeeeeeeeeeed 4 47 4 4 5 14 16550 Status Meuistelincaika pint eae eee ales 4 47 4 5 Serial Communication Port SCP ccccceesssecccceeeeeeeeeeeeeeeeeeeeeaees 4 48 4 5 1 SCP Programming Model nsession aaan a E atts 4 49 4 5 2 SCP Transmit Receive Buffer DeSCriptor ccceeeeeeeeeeeeeeeeeeeteees 4 49 4 6 Serial Management Controllers GMCS 2 ceceeeeeeeeeeeeeeeeeeeeeeaeees 4 49 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Table of Contents Freescale Semiconductor Inc Paragraph Number 4 6 1 4 6 2 4 6 2 1 4 6 2 2 4 6 2 3 4 6 2 4 Title Page Number SMC Programming Modell ccsseesesseeceeesseeeeeeeseeeeesesseeeeeesseeeeeees 4 49 SMC Memory Structure and Buffers DeScriptors cc eeeeeeeeeeeeeeees 4 49 SMC1 Receive Buffer Descriptor ccceeeeeeeeeeeceeeeeeeeeeeeeeeeeeeeesaeees 4 49 SMC1 Transmit Buffer Descriptor cceecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneaaees 4 50 SMC2 Receive Buffer Descriptor cccceeeeeeeeecceeeeeeeeeeeeeeeeeeeeneaeees 4 50 SMC2 Transmit Buffer Descriptor ccceeeeeeeecceeeeeeeeeeeeeeeeeeeenaeees 4 50 Section 5 PCMCIA Controller PCMCIA Controller Functional Overview ccccccceeeeeeeeeeeeeeeeeeeeeeeeees 5 2 Attribute Memory ACCESSES ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseceenaaeeeeeeeneee 5 4 Configuration Register
196. eeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeed 6 12 6 1 6 BUS COMMON RING seesi ft Mattei tees atte ees Dents ates I antes alg 6 12 6 1 7 Interrupt Control or Bus Arbitration Pins 0 cccceeeeeeeeeeeeeeeteeeeeeeeeee 6 14 6 1 8 Gi SClECt PINS iene rrna a une Ceasar alas tenedetusieasecdeecansivanecataeeendessseGes 6 15 6 1 9 NO GOMNGCL PINS sincere n a aa a beater Sascha ceetess 6 16 6 1 10 POA Package PINS ios a aa peasy eo ENa tee eee teen anaiai 6 16 6 1 11 IMP Bus Interface Signal Summary cceeeeeeeeeeeeeeeeeeeeetteeeeeeteeeed 6 17 6 1 12 Physical Layer Serial Interface PinS ccccceceeeeeeeeeeeeeeeeeeeteeeeeeeeeees 6 18 6 1 13 Typical Serial Interface Pin Configurations c cceceeeeeeeeeeeeeeeeeeeees 6 18 6 1 14 NMSI1 or ISDN Interface PINS sissies cesses tes oy iseceeeesoeecinas tees cveeadeaaeteeees 6 19 6 1 15 NMSl2 Port or Port A Pins or PCMCIA Data BUS ceeeeeeeeeeees 6 21 6 1 16 NMSI3 Port or Port A Pins or SCP PINS 5 cssgn cccctsenaccctetzaoibenisieetinteis 6 23 6 1 17 IDMA or Port A Pins or PCMCIA PINS cccceeeeeeceeeeeeeeeeeeeeeteeeeeeeeeeee 6 24 6 1 18 IACK or PIO Port B Pins or PCMCIA cceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 6 25 6 1 19 THIMGIIP UWS a a a ieee te E ta eat sect A TE 6 26 6 1 20 Parallel I O Pins with Interrupt Capability ccceeceeseeeeeeeeeeeeeeteeeees 6 27 6 1 21 PEMGIACORPON D PINS serae ernie a a i dank vase ii add ECEE 6 28 6 1 22 IMP Ar
197. either as an input or an output When configured as an input this pin can generate a separate maskable interrupt on a high to low transition This pin can also wake up the IMP from low power STOP DOZE or STAND BY mode when a high to low transition occurs on this pin when configured as an input See 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes for more information 6 1 21 PCMCIA or Port D Pins The PCMCIA or port D pins are shown in Figure 6 17 When the PCMCIA is disabled 7 of the PCMCIA pins become input only port pins The PCMCIA function of these pins is shown in italics Refer to 6 1 23 IMP Bus Control or PCMCIA Pins for PCMCIA pin description MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description PC_A9 PDI14 PC_A8 PDI13 PC_A7Z PDI12 PC_A6 PDI11 PC_A2 PDI10 PC_A1 PDI9 PC_AO PDI8 Figure 6 17 Port D Pins 6 1 22 IMP Arbitration or PCMCIA Pins NOTE These pins take their PCMCIA function if PC_EN 1 PC_STSCHG BR PC_WATTIBG PC_OE IBGACK Figure 6 18 PCMCIA Signals PC_WAIT BG PCMCIA Extend Bus Cycle or Bus Request The Bus Grant in Enable CPU Mode output indicates to all external bus masters devices that the processor will release the bus control at the end of the current bus cycle In Slave Mode this signal is an input to the IDMA SDMA or PCMCIA Controller During total sys tem reset BR BG PC Wait the WAIT signal i
198. en granted the PCMCIA controller will generate the cycle on the 68000 bus When the cycle is terminated with D TACK the PCMCIA controller may be programmed to maintain the bus ownership for the next cycle or release the bus For burst access cycles FAST 1 in PCMR register bus ownership will be retained Data is transferred to the PCMCIA data lines and the WAIT signal will be negated and the next cycle can take place without WAIT being reasserted Subsequent accesses can occur until the PC has completed the burst and the PCMCIA bus is idle for a programmable number of 68000 bus clocks CLKO as speci fied by the ArbIDL bit in the PCMR The PCMCIA controller may be programmed to automatically increment the CMBAR when the PC reaches the current 4K page boundary defined by CMBAR i e A11 AO FFF This mechanism is useful when the PC is using a DMA cycle to transfer data to or from the card because it eliminates the need to reprogram the base address register each time a page boundary is reached The two common memory base address registers CMBARs can be used to read and write to separate spaces in 68K memory forming pointers to transmit and receive buffers This can be especially useful in high speed communication cards where it is possible to bypass the use of the UART 16550 and simply transfer data directly to and from 68000 memory Figure 5 4 shows how the CMBARs can be used as transmit and receive data buffer point ers Once the data t
199. er Reserved Base Register 0 Option Register 0 Base Register 1 Option Register 1 Base Register 2 Option Register 2 Base Register 3 Option Register 3 Timer Unit 1 Mode Register Timer Unit 1 Reference Register Timer Unit 1 Capture Register Timer Unit 1 Counter Reserved Timer Unit 1 Event Register Watchdog Reference Register Watchdog Counter Reserved Timer Unit 2 Mode Register Timer Unit 2 Reference Register Timer Unit 2 Capture Register Timer Unit 2 Counter Reserved MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senvecandaeten Inc Table 2 6 Internal Registers Map Address Name Width Block Description Reset Value Base 859 TER2 8 Timer Timer Unit 2 Event Register 00 Base 85A RES 16 Timer Reserved Base 85C RES 16 Timer Reserved Reserved Command Register Reserved PC Cont Configuration Option Register PC Cont Card Configuration and Status Registe PC Cont Pin Replacement Register PC Cont Socket and Copy Register PC Cont I O Event Indication register PC Cont PC Cont PC Cont PC DMA PC DMA Data Register Reserved RES1 RES2 RES3 PCDMAD CO CO 4 e gt Reserved SCC1 Configuration Register SCC1 Mode Register SCC1 Data Sync
200. er PCAWER CBVD1 CBVD2 These bits are set to one when the corresponding bits change state These bits may also be written by the host CRdy Bsy This bit is set to one when the corresponding bit changes state These bits may also be written by the host CWProt This bit is set to one when the corresponding bit changes state These bits may also be written by the host RBVD1 RBVD2 When read these bits represent the internal state of the corresponding signals When this bit is written as one the corresponding changed bit is also written Since the MC68PM302 does not support this pin directly external circuitry should be used to implement this pin MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc NOTE The 68000 should write the state of this signal into this location The corresponding changed bit will be updated according to the written data RRdy Bsy When read this bit represents the internal state of the corresponding signal When this bit is written as one the corresponding changed bit is also written See 5 1 10 4 The Ready Busy Signal Rdy Bsy for more information on the functionality of this bit NOTE The 68000 core should write the state of this signal into this lo cation The corresponding changed bit will be updated accord ing to the written data The 68000 core should set this bit to one after initializing the
201. er the power down mode if PITEv and PITEn are both set to one PITEv is cleared by writing a one writing a zero has no effect PB9En PB9 Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PB9 Event bit becomes set PB10En PB10 Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PB10 Event bit becomes set PITEn PIT Enable This bit when set enables the IMP to wake up from power down mode and generate an interrupt when the PIT event bit becomes set see 3 7 3 Periodic Interrupt Timer PIT 2 4 4 3 Fast Wake Up In asystem clocked with a 32 kHz oscillator the wake up recovery time from doze and stop modes may be too long for some applications In order to shorten this time an internal ring oscillator called Ringo can clock the chip the term real clock in the following discussion refers to the clock whose source is the external oscillator or crystal the PLL can be either enabled or disabled Two reasons for using the fast wake up are 1 To allow PC access to the IMP system bus when there is no need to wake up the real clock e g read status of 16550 In this case only the internal oscillator is enabled for the duration of the access The PLL and other clock logic are not awakened 2 To allow PC accesses and other logic to operate in the time frame between the wake up command and the actual real
202. erform required 8 bit operations e Write code to the Dual Port RAM for the bus width change e Jump to code in the dual port RAM MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc When ready to use 16 bit bus width set the BUSW bit to 1 Toggle the BWSEN bit from zero to one Allow time for bus arbitration and the instruction pipeline to clear Initialize external memory Copy boot code from EPROM to external memory space Execute code from external memory space NOTE The stack which is shared by both codes should be placed in the dual ported RAM Copy the stack to dual port RAM after switch ing to the second RAM and change the stack pointer 3 3 LOAD BOOT CODE FROM AN SCC The MC68PM302 provides the capability of downloading program code into SCC1 and beginning program execution in the dual port RAM The boot function has two clocking options external and internal In the first mode the user provides the chip with an external clock 16 the desired baud rate In the second mode the RISC processor programs the SCC into UART mode running at approximately 9600 baud assuming the frequency of the clock to the chip has one of two nominal values 32 768 Khz or 4 192 Mhz The first 576 bytes that are received into SCC1 are stored in the dual port RAM No error checking is performed on the incoming serial bit stream The 68000 processor t
203. es 4 21 BIS YNC Mask Registers c 420s aaa Al eee a A 4 21 Transparent Controller sates eked ee eek ed ele ted ee titel 4 21 Transparent Memory Map 2 26ccncicitecte teen crite ei eiole beim ce 4 21 Transparent Mode Register cccccccseececeeeeeeeeeeeeeeeeeeeeneaeeeeeeeeenees 4 22 Transparent Receive Buffer Descriptor RXBD ceeesseeeeeeeeeeees 4 22 Transparent Transmit Buffer Descriptor TX BD eeeeeeeeeeeeeeeees 4 23 Transparent Event Register cccccsesseecceeeeeeeeeeeeeeeeeeeenaaeeeeeeeeeeees 4 23 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Paragraph Title Page Number Number 4 3 12 6 Transparent Mask Register cccccccsssecccceeeeeeeeeeeeeeeeeeeenaaeeeeeeeeeeees 4 23 4 4 16550 Emulation Controller NEW feature cceeeeeeeeeeeeeeeteeeeeeeeeee 4 23 4 4 1 16550 Emulation Controller Features c ccccccccceeceeeeeeeeeeeeeeeeeeeeeeee 4 23 4 4 2 16550 Emulation Controller Overview ccccccececeeeeeeeeseeenteeeeeeeeeee 4 24 4 4 2 1 16550 Emulation Controller FIFOs Overview cccceeeseeteeeeeeeeeeee 4 24 4 4 3 PE ACCESSOS E AA OANE A 4 24 4 4 4 PC Programmer Model Asyre irisean nne aaea SERERE 4 26 4 4 4 1 16550 Emulation Registers Description cccceeeeeeeeeeeeeetteeeeeeteee 4 27 4 4 4 1 1 Line Control Register LOR
204. es vtawesgeesaeagehaseeciceeeeseeseueuas 4 2 4 3 Serial Communication Controllers SCCS ceeeeeeeeeeeeeeeeeeeeeeeteeees 4 2 4 3 1 SCC Configuration Register SCON cccceeceeeseeeeeeeeeeeeeeeeeeeeeeeeaaees 4 2 4 3 1 1 Divide by 2 Input Blocks New Feature ccceeceeeeeeeeeeeeeeeeteeeeeeeeeees 4 2 4 3 2 Baud Rate Generator Pins Register BRGP ceceeeeeeeeeereeeeeeeees 4 2 4 3 3 SCC Mode Register SCM ccccceeeesccceceeeeeeeeeneeeeeeeeeeseeneeeeeeeeeennaaeaes 4 3 4 3 4 SCC Data Synchronization Register DSR cceeeeeeeeeeeeeeeeeeeeeteees 4 4 4 3 5 Buffer Descriptors Table cecccccceceeeeeseeeeeeeeeeeeeeeeeeeeeeeeesaaeeeeeeeeeeee 4 4 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Table of Contents Freescale Semiconductor Inc Paragraph Number 4 3 6 4 3 7 4 3 8 4 3 8 1 4 3 8 2 4 3 8 3 4 3 8 4 4 3 8 5 4 3 8 6 4 3 9 4 3 9 1 4 3 9 2 4 3 9 3 4 3 9 4 4 3 9 4 1 4 3 9 4 2 4 3 9 4 3 4 3 9 4 4 4 3 9 5 4 3 9 6 4 3 9 7 4 3 9 8 4 3 9 8 1 4 3 9 8 2 4 3 9 9 4 3 10 4 3 10 1 4 3 10 2 4 3 10 3 4 3 10 4 4 3 10 5 4 3 10 6 4 3 11 4 3 11 1 4 3 11 2 4 3 11 3 4 3 11 4 4 3 11 5 4 3 11 6 4 3 12 4 3 12 1 4 3 12 2 4 3 12 3 4 3 12 4 4 3 12 5 Title Page Number SCC Parameter RAM Memory Mab cccceceeeeeeeeeeeeeeeeeneeeeeeeeeeeenaeees 4 5 MTERRUD EM OG MARIS aeaee a aer eaaa EE EAEE
205. escale Semiconductor cdJm unications Processor CP both transmit or receive Only the first field containing status and control bits differs for each protocol The BD format is shown in Figure 4 1 15 p OFFSET 0 STATUS AND CONTROL OFFSET 2 DATA LENGTH OFFSET 4 HIGH ORDER DATABUFFER POINTER only lower 8 bits use upper 8 bits must be 0 OFFSET 6 LOW ORDER DATA BUFFER POINTER Figure 4 1 SCC Buffer Descriptor Format NOTE Even though the address bus is only 20 bits the full 32 bit point er must be Bits 24 32 must be zero and bits 20 23 are used in the Chip Select address comparison so they should be pro grammed to a value which will assert the desired chip select 4 3 6 SCC Parameter RAM Memory Map Each SCC maintains a section in the dual port RAM called the parameter RAM Each SCC parameter RAM area begins at offset 80 from each SCC base area 400 500 or 600 and continues through offset BF Part of each SCC parameter RAM offset 80 9A which is identical for each protocol chosen is shown in Table 4 1 Offsets 9C BF com prise the protocol specific portion of the SCC parameter RAM and are discussed relative to the particular protocol chosen The SCC parameters have not changed functionality from the MC68302 Table 4 1 SCC Parameter RAM Memory Map Address Name Width Description SCC Base 80 RFCR Byte Rx Function Code SCC Base 81 TFCR Byte Tx Function Code SCC Base 82
206. escale com Electrical Characteristics Freescale Semiconductor Inc S0 S1 S2 S3 S4 S5 S6 7 i AKA NANA NS NS FC2 FCO X LDS UDS DATA OUT BERR BR NOTE 2 ASYNCHRONOUS INPUTS NOTE 1 NOTES 1 Timing measurements are referenced to and from a low voltage of 0 8 volt and a high voltage of 2 0 volts unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between between 0 8 volt and 2 0 volts 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 20A 3 Each wait state is a full clock cycle inserted between S4 and S5 Figure 7 3 Write Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 10 S11 12 13 14 15 16 S17 S18 S19 CLKO AS NOTE 2 OUTPUT AS NOTE 3 OUTPUT UDS LDS OUTPUT RW OUTPUT DTACK D15 D0 DATA IN DATA OUT INDIVISIBLE CYCLE NOTES For other timings than indivisible cycles see Figures 7 2 and 7 3 RMCST 0 in the SCR RMCST 1 in the SCR Wait states may be inserted between S4 and S5 during the write cycle and between S16 and
207. eset all external devices During a total system reset the address data and bus control pins are all three stated except for CS3 CS0 WEH WEL and OE which are high and IAC which is low The BG pin output is the same as that on the BR input The general purpose I O pins are config ured as inputs except for WDQG which is an open drain output The NMSI1 pins are all inputs except for RTS1 and TXD1 which output a high value RTS3 is high and CLKO is active NOTE The RESET pin should not be asserted externally without also asserting the HALT pin To reset just the internal IMP peripher als the RESET instruction may be used Besides the total system reset and the RESET instruction some of the IMP peripherals have reset bits in one of their registers that cause that particular peripheral to be reset to the same state as a total system reset or the RESET instruction Reset bits may be found in the CP in the CR the IDMA in the CMR timer 1 in the TMR1 and timer 2 in the TMR2 HALT Halt When this bidirectional open drain signal is driven by an external device it will cause the IMP bus master M68000 core SDMA or IDMA to stop at the completion of the current bus cycle In PC_EN 1 DISCPU 0 mode the external device can take ownership of the bus See section 3 8 3 Bus Arbitration Logic If the processor has stopped executing in structions due to a double fault condition this line is driven by the processor to
208. exactly 32 000 KHz the UART frequency is 9435 NOTE The autobaud function cannot be used in the boot download pro cess Values in bit CD10 0 in SCON are not relevant if PA5 1 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc The RISC processor then programs the SCM register to 013D to program the SCC to UART mode with both the receiver and the transmitter enabled software operation mode CD and CTS are don t cares 8 bit data characters and no parity The RISC processor then begins receiving data into the dual port RAM beginning with location 0 of the dual port RAM Every character that is received is echoed back out of the TXD1 pin The MC68PM302 UART must be sent 576 bytes of data from the external UART since the MC68PM302 will not leave the boot mode until 576 bytes are received If the boot program is less than 576 bytes the user is suggested to write 00 into the remaining locations After 576 bytes are received the RISC programs the SCM register to 0 which clears the ENR and ENT bits to disable the UART returns to its reset value The RISC processor next negates the HALT signal to the core internally The 68000 then reads the reset vector from the first location of the dual port RAM In most cases the code that is downloaded will enable the chip selects of the MC68PM302 initialize the MC68PM302 receive buffer desc
209. factor can be changed in the IPLCR register and the IMP PLL divide factor can be set in the IOMCR register NOTE The IMP input frequency ranges are limited to between 25 kHz and the maximum operating frequency and the PLL output fre quency range before the low power divider is limited to between 10 MHz and the maximum system clock frequency 25 MHz Table 2 2 Default System Clock Generation VCCSYN _ Example IMP IMP CSelect MODCLK EXTAL Freq IMP PLL MF 1 IMP System Clock 0 0X 25 MHz Disabled x IMP EXTAL 0 10 4 192 MHz Enabled 4 IMP EXTALx4 0 11 32 768 kHz Enabled 401 IMP EXTALx401 Note By loading the IPLCR register the user can change the multiplication factor of the PLL after RESET By loading the IOMCR register the user can change the power saving divide factor of the IMP PLL NOTE It is not possible to start the system with PLL disabled and then enable the PLL with software programming MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senvueandaeten Inc 2 4 3 IMP System Clock Generation 2 4 3 1 SYSTEM CLOCK CONFIGURATION The IMP has an on chip oscillator and phased locked loop Figure 2 2 These features provide flexible ways to save power and reduce system cost The operation of the clock generation circuitry is determined by the fol lowing registers The IMP Operation Mode Control Registe
210. fications Timers see Figure 7 18 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol at5 0V at 5 0 V at5 0V Unit Min Max Min Max Min Max 200 Timer Input Capture Pulse Width trpw 50 42 34 ns 201 TIN Clock Low Pulse Width tricLt 50 42 34 ns TIN Clock High Pulse Width and Input a 202 Capture High Pulse Width TICHT 2 E 2 2 clk 203 TIN Clock Cycle Time teyc 3 3 3 clk 204 Clock High to TOUT Valid tcHTov 35 30 24 ns 205 aia put Setup Time to Clock High see feeocti 20 20 14 is 206 FRZ Input Hold Time from Clock High teRZHT 10 10 7 ns NOTES 1 FRZ should be negated during total system reset 2 The TIN specs above do not apply to the use of TIN1 as a baud rate generator input clock In such a case specifications 1 3 may be used CLKO TOUT OUTPUT TIN INPUT FRZ INPUT Figure 7 18 Timers Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics 7 6 14 IMP AC Electrical Specifications Serial Communications Port see Freescale Semiconductor Inc Figure 7 19 16 67 MHz 20 MHz 20 MHz Num Characteristic at 5 0 V at 5 0 V at5 0V Unit Min Max Min Max Min Max 250 SPCLK Clock Output Period 4 64 4 64 4 64 clks 251
211. figuration Registers for the placement of the three SCC parameter RAM areas and to Table 4 1 for the other parameter RAM values Table 4 2 UART Specific Parameter RAM Address Name Width Description SCC Base 9C MAX_IDL Word Maximum IDLE Characters Receive SCC Base 9E IDLC Word Temporary Receive IDLE Counter SCC Base AO BRKCR Word Break Count Register Transmit SCC Base A2 PAREC Word Receive Parity Error Counter SCC Base A4 FRMEC Word Receive Framing Error Counter SCC Base A6 NOSEC Word Receive Noise Counter SCC Base A8 BRKEC Word Receive Break Condition Counter SCC Base AA UADDR1 Word UART ADDRESS Character 1 SCC Base AC UADDR2 Word UART ADDRESS Character 2 SCC Base AE RCCR Word Receive Control Character Register SCC Base BO CHARACTER1 Word CONTROL Character 1 SCC Base B2 CHARACTER2 Word CONTROL Character 2 SCC Base B4 CHARACTER3 Word CONTROL Character 3 SCC Base B6 CHARACTER4 Word CONTROL Character 4 SCC Base B8 CHARACTERS Word CONTROL Character 5 SCC Base BA CHARACTER6 Word CONTROL Character 6 SCC Base BC CHARACTER7 Word CONTROL Character 7 SCC Base BE CHARACTER8 Word CONTROL Character 8 Initialized by the user M68000 core 4 3 8 2 UART MODE REGISTER Each SCC mode register is a 16 bit memory mapped read write register that controls the SCC operation The read write UART mode register is cleared by reset 15 14 13 12 11 10 9 8 7 6 5 0
212. ges e 16550 Emulation Block Complete H W and S W Emulation of the 16550 UART DMA Supported for Transfer of 16550 Data Over 68K bus Speed of Data Transfer Can Be Matched to Traditional 16550 UART High Speed Data Transfer up to 2 Mbps Possible e Initial Offering Features 16 67 and 20 MHz Versions at 5V and 3 3V e 144 Pin Thin Quad Flat Pack TQFP Packaging 1 3 PM302 APPLICATIONS The PM302 excels in several applications areas 1 IOM is a trademark of Siemens AG MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Introduction Freescale Semiconductor Inc First the PM302 excels in low power and portable applications The inclusion of a static 68000 core coupled with the low power modes built into the device make it ideal for hand held or other low power applications The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer s board and allows the PM302 to be an effective de vice in low power systems The PM302 can then optionally generate a full frequency clock for use by the rest of the board During low power modes the new periodic interrupt timer PIT allows the device to be woken up at regular intervals In addition two pins allow the device to be woken up from low power modes These features make the device useful as an upgrade to the existing 68302 Second the performance cost and low power usage of the PM302 is an ideal processor to be used on P
213. gford FLORIDA Maitland FLORIDA t ompano Beach Fort Lauderdal FLORIDA Clearwater GEORGIA cuanta IDAHO Boi ILLINOIS Chica o Hoffman Estates INDIANA Fort Wayne INDIANA Indianapolis INDIANA Kokomo Seis Cedar Rapids NSAS Kansas City Mission MARYLAND Columbia CANADA BRITISH COLUMBIA Vancouver ONTARIO Toronto ONTARIO Ottawa QUEBEC Montreal INTERNATIONAL AUSTRALIA Melbourne AUSTRALIA Sydney BRAZIL Sao Paulo CHINA Beijing FINLAND Helsinki Car Phone FRANCE Paris Vanves GERMANY Langenhagen Hanover GERMANY Munich GERMANY Nuremberg GERMANY Sindelfingen GERMANY Wiesbaden HONG KONG Kwai Fong Tai Po INDIA Bangalore ISRAEL Tel Aviv ITALY Milan JAPAN Aizu JAPAN Atsugi JAPAN Kumagaya JAPAN Kyushu JAPAN Mito JAPAN Nagoya JAPAN Osaka JAPAN Sendai JAPAN Tachikawa JAPAN Tokyo JAPAN Yokohama KOREA Pusan KOREA Seoul UNITED STATES 205 464 6800 602 897 5056 407 628 2636 486 9776 61 3 887 0711 61 2 906 3855 55 11 815 4200 86 505 2180 358 0 35161191 358 49 211501 33 1 40 955 900 49 511 789911 49 89 92103 0 49 911 64 3044 49 7031 69 910 49 611 761921 852 4808333 852 6668333 91 812 627094 972 3 753 8222 39 2 82201 81 241 272231 81 0462 23 0761 1 0485 26 2600 1 092 771 4212 81 0292 26 2340 81 052 232 1621 81 06 305 1801 81 22 268 4333 0425 23 6700 03 3440 331 1 045 472 2751 2051 4635 035 82 2 554 5188 81 81 81 8 MASSACHUSETTS arorangi MASSACHUS
214. gure 4 11 16550 Emulation Controller Transmitter FIFO 4 4 4 PC Programmer Model The PC programmer model is identical to the standard 16550 All software packages that support the 16650 can be executed without any modification MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP Table 4 12 16550 Emulation Registers Addresses REG CE1 IORD IOWR DLAB A25 A2 A1 AO Register L L L H 0 0 0 0 0 Receiver buffer read L L H L 0 0 0 0 0 aie holding register L L L H 0 0 0 0 1 Interrupt enable read L L H L 0 0 0 0 1 Interrupt enable write L L L H x 0 0 1 0 Interrupt identification read L L H L x 0 0 1 0 FIFO control write L L L H x 0 0 1 1 Line control read L L H L x 0 0 1 1 Line control write L L L H x 0 1 0 0 MODEM control read L L H L x 0 1 0 0 MODEM control write L L L H x 0 1 0 1 Line status read L L L H Xx 0 1 1 0 MODEM status read L L L H x 0 1 1 1 Scratch read L L H L x 0 1 1 1 Scratch write L L L H 1 0 0 0 0 Divisor latch LS read L L H L 1 0 0 0 0 Divisor latch LS write L L L H 1 0 0 0 1 Divisor latch MS read L L H L 1 0 0 0 1 Divisor latch MS write 4 4 4 1 16550 EMULATION REGISTERS DESCRIPTION 4 4 4 1 1 Line Control Register LCR This register is used to specify the format of the asynchronous se
215. h 7 in the PC MCIA I O address space therefore PCMCIA address lines 3 to 25 are ignored for I O ac cesses See Table 5 7 Refer to Table 5 5 and Table 5 6 for signal states and bus validity for the I O read and write function MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc Table 5 5 I O Input Accesses Function Mode PC_REG PC_CE2 PC_CE1 PC_A0 PC_IORD PC_IOWR fee PC_D7 PC_DO Standby Mode x H H x x x High Z High Z L H L L L H High Z Even Byte Byte Access L H L H L H High Z Odd Byte Word Access L L L x L H Odd Byte Even Byte 1O inhibit High Z High Z during DMA A X Z L a High Byte Only L L H x L H Odd Byte High Z Table 5 6 I O Output Accesses Function Mode PC_REG PC_CE2 PC_CE1 PC_AO PC_IORD PC_IOWR pos PC_D7 PC_DO Standby Mode x H H xX x x XXX XXX Byte Access L H L L H L XXX Even Byte y L H L H H L XXX Odd Byte Word Access L L L x H L Odd Byte Even Byte I O Inhibit XXX XXX during DMA n A A X M L High Byte Only L L H x H L Odd Byte XXX Table 5 7 Card I O Space Address Map PC_REG PC_CE1 PC_CE2 PC_IORD PC_1owR pc_ao pc_a2 Selected Register or Space L H L H 0 7 16550 8 bytes read L H H L 0 7 16550 8 bytes write See Table 2 6 for specific 16550 register address locatio
216. h SCC Base AO NOM_START Word Current Nom START Bit used to determine baud rate SCC Base A2 PAREC Word Receive Parity Error Counter SCC Base A4 FRMEC Word Receive Framing Error Counter SCC Base A6 NOSEC Word Receive Noise Counter SCC Base A8 BRKEC Word Receive Break Error Counter SCC Base AA ABCHR1 Word User Defined Character1 SCC Base AC ABCHR2 Word User Defined Character2 SCC Base AE RCCR Word Receive Control Character Register SCC Base BO0O CHARACTER1 Word CONTROL Character1 SCC Base B2 CHARACTER2 Word CONTROL Character2 SCC Base B4 CHARACTER3 Word CONTROL Character3 SCC Base B6 CHARACTER4 Word CONTROL Character4 SCC Base B8 CHARACTERS Word CONTROL Character5 SCC Base BA CHR6 RxPTR Word CONTRChar6 MSW of pointer to external Rx Buffer SCC Base BC CHR7RxPTR Word CONTRChar7 LSW of pointer to external Rx Buffer SCC Base BE CHR8 TxBD Word CONTROL Character8 Transmit BD These values should be initialized by the user M68000 core Note the new parameters that have been added to the table They are MAX_BIT NOM_START ABCHR1 ABCHR2 RxPTR 2 words and TxBD These parameters are of special importance to the autobaud controller They must be written prior to issuing the Enter_Baud_Hunt command When the channel is operating in the autobaud hunt mode the MAX_BIT parameter is used to hold the current maximum START bit length The NOM_START location contains
217. h 2 11 Clock CLKO 6 9 Clock Pins 6 8 CMBAR1 2 5 30 CMR 3 11 Communications Processor 4 1 Configuration MC68302 IMP Control 2 3 CQFP 8 2 Crystal Oscillator 2 8 Crystal Oscillator Circuit IMP 2 9 CSO 3 26 3 28 6 15 CS3 CS1 6 15 CSelect 2 7 CSR 3 14 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Index D DACK 6 24 DAPR 3 13 Default System Clock Generation 2 7 DFO 3 2 9 Disable CPU 6 7 BG 3 28 BR 3 28 CSO 3 28 DTACK 3 29 EMWS 3 29 SAM 3 29 Disable CPU Logic 3 28 DISC 4 2 DISCPU 3 28 6 7 Divide by Two Block From Tin1 Pin 4 3 DMA Control 3 11 DONE 6 25 DOZE 2 13 2 15 DRAM Refresh Buffer Descriptors 3 30 PB8 3 19 DREQ 6 24 DSR 4 4 DTACK 3 4 3 5 3 26 3 29 6 17 6 31 Dynamic RAM Refresh Controller 3 30 E EMR 4 36 Emulation Controller 4 23 EMWS External Master Wait State 3 5 3 29 Enable Receive 4 4 Enable Transmitter 4 4 Exception PB8 3 30 EXTAL 6 6 6 8 External Bus Master 3 30 Master Wait State EMWS 3 5 External Bus Arbitration Using HALT 3 30 External Master Wait State 3 5 F FCR 3 14 4 29 Freeze Control 3 6 Function Codes 3 14 6 16 6 32 Comparison 2 4 FC2 FCO 2 4 6 16 Register 3 14 G GCI 4 2 6 18 6 19 GCI See Signals GIMR 3 15 GNDSYN 2 12 H HALT 2 3 6 10 6 27 HALT See Signals Hardware Watchdog 3 6 BERR 3 6 HDLC HDLC Memory Map 4 18 HDLC Controller 4 18 HDLC Event Register 4 20 H
218. has been programmed with a value that is dividing the IMP PLL VCO output to the system clock in order to save power The PLL output divider can only be used with MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc the IMP PLL enabled The divider value is Coe Nota in the DF3 0 bits in the IOMCR The clock may be divided by a power of 2 2 No functionality is lost in SLOW GO mode 2 4 4 1 5 NORMAL Mode In NORMAL mode the IMP part is fully operational and the sys tem clock from the PLL is not being divided down 2 4 4 1 6 IMP Operation Mode Control Register IOMCR IOMCR is a 8 bit read write register used to control the operation modes of the IMP The WP bit in IOMCR is used as a protect mechanism to prevent erroneous writing of IOMCR IOMCR SOFA 7 6 5 4 3 2 1 0 IOMP DF3 DF2 DFI DFO BCD LPM1 LPMO a 0 0 0 0 0 0 0 Read Write IOMWP IMP Operation Mode Control Write Protect Bit This bit prevents accidental writing into the IOMCR After reset this bit defaults to zero to enable writing Setting this bit prevents further writing excluding the first write that sets this bit DF 3 0 Divide Factor The Divide Factor Bits define the divide factor of the low power divider of the PLL These bits specify a divide range between 2 and 2 Changing the value of these bits will not cause a loss of lock con
219. he PCMCIA connector The pins of the MC68PM302 are redefined as follows only redefined pins that affect present specification are mentioned here left most functions are new 1 IDREQ_ PC_DREQ_ PB8 PCMCIA DMA Request in PC DMA mode this pin is an out put the user should connect it either to SPKR or INPACK or IOIS16 signals on the PCMCIA Connector 5 3 11 4 Description of Registers for PC_DMA The following sections describe the registers used for the PC_DMA 5 3 11 4 3 PCMCIA Access Wake Up Event Register PCAWER bit 6 PCTC PCMCIA Terminal Count 0 No event has occurred 1 PCTC PCMCIA Terminal Count This event is asserted if the PC Host asserted TC signal on the PC DMA transfer bit is reset by writing one MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller bit 7 PCDRDY PCDMAD Register Ready 0 PCDMAD register is busy 1 PCDMAD register is ready for 68K bus During DMA Write cycle Bit is set when data is read from PCDMAD by PC Host During DMA Read cycle Bit is set when data is written into PCDMAD by PC Host In both cases bit is reset by writing 1 to it NOTE On DMA Read cycle PC_WE_ active if Terminal Count is ac tive both PCTC and PCDRDY bits are set On DMA Write cycle PC_OE_ active if Terminal Count is ac tive only PCTC bit is set 5 3 11 4 4 PCMCIA Access Wake Up Mask Register
220. he desired events 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes The IMP can wake up from STOP DOZE STAND_BY mode to NORMAL SLOW_GO mode in response to inputs from the following sources 1 Asserting both RESET and HALT hard reset pins 2 Asserting high to low transition either RI PB9 or DTE PB10 pins if these interrupts are enabled 3 A timeout of the periodic interrupt timer if the PIT interrupt is enabled 4 Reset of the PwrDwn bit in the PCMCIA card configuration and status register when the PCMCIA controller is enabled When one of these events occur and the corresponding event bit is set the IMP low power controller will asynchronously restart the IMP clocks Then IMP low power control logic will release the 68000 bus and the IMP will return to normal operation If one of the above wake up events occurs during the execution of the STOP command the low power control logic will abort the power down sequence and return to normal operation NOTE The PB9 PB10 and periodic interrupt timer timeout interrupts conditions will generate level 4 interrupts The user should also set the 68000 interrupt mask in the status register SR to the ap propriate level before executing the STOP command to ensure that the IMP will wake up to the desired events 2 4 4 2 4 IMP Wake Up Control Register IWUCR The IWUCR contains control for the wake up options This register can be read and written by the 68000 core
221. he internal buses For applications which require very low current consumption it is recommended to a minimize external memory accesses and use internal memory accesses instead b minimize the number of pins which are switching c minimize the capacitive load on the pins d connect the unused inputs to pull up or pull down resistors MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 4 3 DC Electrical Characteristics Characteristic Symbol Min Max Unit Input High Voltage Except pins noted below Vie 2 0 Vpp V ape High voltage PC A2 PC_A11 PC_A25 PC_CE2 PC_D7 PC_DO CTS1 CD1 RXD1 TCLK1 BRG1 RCLK1 RTS1 RXD2 TXD2 RCLK2 TCLK2 CTS2 RIS2 CD2 BRG2 RXD3 CD3 RCLK3 y y TCLK3 PA12 RTS3 TXD3 CTS3 TOUT2 TOUT TIN2 TIN1 IH 2 5 DD V WDOG PB8 11 PC_ABUF FRZ_ These pins have schmitt trigger inputs Input Low Voltage ViL Vss 0 3 0 8 V Input Undershoot Voltage VoL 0 8 V Input High Voltage EXTAL 3 3 Volt or 5 Volt Part VciH 8 Vop Vpp V Input High Voltage RESET VIHR 2 5 Vpp V Input Leakage Current liy 20 uA Input Capacitance All Pins Cin 15 pF Three State Leakage Current 2 4 0 5 V Its 20 20 uA Open Drain Leakage Current 2 4 V lop 20 uA Output High Voltage lop 400 A see Note VoH 2 4 V Output Low Voltage V loL 3
222. he programming model and instruction set summary Throughout this manual references may use the notation M68000 meaning all devices belonging to this family of microprocessors or the notation MC68000 MC68008 meaning the specific microprocessor products This section is intended to describe configuration of the MC68PM302 and the differences between thePM302 and the MC68000 and the MC68302 This section also includes tables that show the registers of the IMP portion of the MC68PM302 All of the registers are mem ory mapped into the 68000 space 2 1 MC68PM302 AND MC68302 SIGNAL DIFFERENCES When the PM302 is operating in its PCMCIA mode certain functions existing on the original 68302 are no longer available The major differences are listed below e External masters are not able to take the bus away from the PM302 except through a simple scheme using the HALT pin This restriction does not apply to using the PM302 is in CPU disabled mode slave mode in which case BR BG and BGACK are all avail able e Although the Independent DMA IDMA is still available the external IDMA pins DACK and DONE have been eliminated MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senueandaeten Inc Four address lines have been eliminated giving a total of 20 address lines However the PM302 supports more than a 1 MB addressing range since each of the four chi
223. hen begins executing from the first location of the dual port RAM to complete the boot process This function is not supported for SCC2 or SCC3 Three pins are sampled to determine the mode of operation and clock of the boot function PA7 Sampled during Hard Reset RESET and HALT asserted 0 Boot from SCC is enabled 1 Boot from SCC is disabled PA5 Sampled within 100 clocks from the negation of RESET 0 Internal Clock 1 External Clock 16 the bit rate on TCLK1 and RCLK1 PA12 MODCLKO Sampled during Hard Reset RESET and HALT asserted 0 Nominal input frequency on EXTAL is 4 192 Mhz 1 Nominal input frequency on EXTAL is 32 768 Khz To enable the boot function the PA7 pin must be pulled low during system reset System reset is defined by the RESET and HALT pins being asserted The PA7 pin must be pulled high during system reset if boot mode is not to be enabled Once the MC68PM302 detects that the PA7 pin is asserted it internally keeps the HALT signal to the 68K core asserted MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB after system reset is complete This action prevents the 68000 from fetching the reset vec tor NOTE PA7 needs to be either pulled UP or pulled DOWN Do not leave this pin floating during reset Once system reset is complete the RISC processor programs the BAR register to 0000 to place the du
224. hen configured to operate in transparent mode the IMP overlays the structure illustrated in Table 4 11 onto the protocol specific area of that SCC parameter RAM Refer to System Configuration Registers on page 4 for the MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc placement of the three SCC parameter RAM areas and Table 4 1 for the other parameter RAM values Table 4 11 Transparent Specific Parameter RAM Address Name Width Description SCC BASE 9C RES WORD Reserved SCC BASE 9E RES WORD Reserved SCC BASE AO RES WORD Reserved SCC BASE A2 Reserved SCC BASE A4 Reserved SCC BASE A6 Reserved SCC BASE A8 Reserved SCC BASE AA Reserved SCC BASE AC Reserved SCC BASE AE Reserved SCC BASE BO Reserved SCC BASE B2 Reserved SCC BASE B4 Reserved SCC BASE B6 Reserved SCC BASE B8 Reserved SCC BASE BA RES WORD Reserved SCC BASE BC RES WORD Reserved SCC BASE BE RES WORD Reserved 4 3 12 2 TRANSPARENT MODE REGISTER Each SCC mode register is a 16 bit mem ory mapped read write register that controls the SCC operation The term transparent mode register refers to the protocol specific bits 15 6 of the SCC mode register when that SCC is configured for transparent mode The transparent mode register is cleared by reset All undefined bits should be writ
225. his buffer does not contain a control character 1 This buffer contains a control character The last byte in the buffer is one of the user defined control characters D Buffer Closed on Reception of Idles The buffer was closed due to the reception of the programmable number of consecutive IDLE sequences defined in MAX_IDL BR Break Received A break sequence was received while receiving data into this buffer Data Length Data length is the number of octets written by the CP into this BD s data buffer It is written by the CP once as the BD is closed NOTE The actual amount of memory allocated for this buffer should be greater than or equal to the contents of the maximum receive buffer length register MRBLR Rx Buffer Pointer The receive buffer pointer which always points to the first location of the associated data buffer may be even or odd The buffer may reside in either internal or external memory 4 4 5 11 16550 TX BUFFER DESCRIPTOR TX BD Data is presented to the CP for trans mission on the 16550 channel by arranging it in buffers referenced by the channel s transmit buffer descriptor table The CP confirms transmission via the buffer descriptors to inform the processor that the buffers have been serviced The first word contains status and control bits MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkn escale Semiconductor Inc
226. icates that the current bus cycle accesses an on chip location This includes the on chip 4K byte block of internal RAM and registers both real and reserved locations and the system configuration regis ters S0FO 0FF The above mentioned bus cycle may originate from the M68000 core the IDMA or an external bus master Note that if the SDMA accesses the internal dual port RAM it does so without arbitration on the M68000 bus therefore the IAC pin is not asserted in this case The timing of IAC is identical to that of the CS3 CS0 pins IFC2 FCO0O Function Codes 2 0 These bidirectional signals indicate the state and the cycle type currently being executed The information indicated by the function code outputs is valid whenever AS is active These lines are outputs when the IMP M68000 core SDMA or IDMA is the bus master and are inputs otherwise The function codes output by the M68000 core are predefined whereas those output by the SDMA and IDMA are programmable The function code lines are inputs to the chip select logic and IMP internal register decoding in the BAR AVEC Autovector When asserted during an interrupt acknowledge cycle this pin indicates that the M68000 core should use automatic vectoring for an interrupt This pin operates like VPA on the MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description MC68000 but is used f
227. ide ate aoe eels 5 36 5 3 11 PCMCIA DMA SUDDOM snina aa a redeieey 5 36 5 3 11 1 PC DMA Operation DeSCription c cccceceeeeceeeeeeeeeeeeeeeeeeeeeseeeneeeeees 5 36 5 3 11 1 1 Interrupt Polling Mode eck ita telat sete ah ee led eels 5 37 581112 DIMA Modei neoinein sak Lanta he anina eet Pernt A EESAN 5 37 5 3 11 2 Data Path and Swapping ISSUES cceceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeteaeeeees 5 37 5 3 11 3 Description of Pin ReaSsignment ccccccceeeeeeeeeeeeeeeeeeeeeeeeneeeeeees 5 38 5 3 11 4 Description of Registers for PO_DMA c ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeees 5 38 5 3 11 4 3 PCMCIA Access Wake Up Event Register PCAWER 0 0 5 38 5 3 11 4 4 PCMCIA Access Wake Up Mask Register PCAWMR ee 5 39 5 3 11 4 5 PCMCIA Mode Register PCMR Additional Bits eeeeeee 5 39 5 3 11 4 6 PCMCIA DMA Data Register PCDMAD Mapped at Address EASE DS 1G eae sic witnesses a eae ais pide Sucve 5 40 Section 6 Signal Description 6 1 WIP PIAS eaan el ge Acces cae ee i as cheat ete eae eta alah 6 1 6 1 1 WIETE LEN aa AES Wine Ose RCO REOPEN Reet cae ene REC EPR E OPC SMA a OME OSM THe ERED 6 6 6 1 2 Clock PINS neniiga A A E E E e 6 8 6 1 3 System Control PINS vse tse ccetices doce eet ecege lb Ace denne ee a aiceeed 6 9 6 1 4 IMP Address Bus Pins A23 A1 ecccsseccceeeeeeeeseeeeeeeeeeesaeeeeeeeeneneees 6 11 6 1 5 IMP Data Bus Pins D15 DO cccceceeeee
228. igger level for the receiver FIFO interrupt Table 4 13 Receiver FIFO Trigger Level Bytes RCVR FIFO Trigger Level Bytes 4 4 4 1 4 Interrupt Identification Register IIR Read Only The interrupts are priori tized into four levels and recorded in the interrupt identification register IIR The four levels of interrupt conditions in order of priority are receiver line status received data ready trans mitter holding register empty and MODEM status When the PC accesses the IIR the con tents of the register and all pending interrupts are frozen Any new interrupts will be recorded and updated after the current access is terminated IIR PC Access Only 7 6 5 4 3 2 1 0 INTERRUPT FIFO ENABLES RESERVED RESERVED INTERRUPT ID PENDING RESET 0 O 0 0 0 0 0 0 Read Only PC Interrupt Pending 0 An interruptis pending and the IIR contents may be used as a pointer to the appro priate interrupt routine 1 No interrupt is pending Interrupt ID These bits are used to identify the highest priority interrupt pending as indicated in Table 4 14 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP Bits 4 and 5 These bits are always 0 Bits 6 and 7 These bits are set when FCRO 1 In the 16450 mode they are always 0 Table 4 14 Interrupt Control Functions
229. ill be used For example if DONE is not needed by the IDMA it can be configured as a general purpose 1 O pin If the IDMA is used for memory to memory transfers only then all three pins can be used as general purpose I O pins NOTE These pins function as PCMCIA if PC_EN 1 DREQ PA13 PC_IORD DMA Request or Parallel IO or PCMCIA IO Read DMA Request input is asserted by a peripheral device to request an operand transfer be tween that peripheral device and memory In the cycle steal request generation mode this input is edge sensitive In burst mode it is level sensitive PCMCIA I O Read IORD signal is made active to read data from the card s I O space The REG signal and at least one of CE1 or CE2 must also be active A PC card will not respond to the IORD signal until it has been configured for I O operation by the system DACK PA14 PC_IOWR DMA Acknowledge or Parallel IO or PCMCIA IO Write DMA Acknowledge output asserted by the IDMA signals to the peripheral that an oper and is being transferred in response to a previous transfer request PCMCIA IO Write IOWR signal is made active to write data to the card s I O space The REG signal and at least one of CE1 or CE2 must also be active A PC card will not re spond to the IORD signal until it has been configured for I O operation by the system MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
230. in the 16550 receiver emulation FIFO 4 4 5 9 16550 ERROR HANDLING The 16550 controller reports character reception and transmission error conditions via the channel buffer descriptors the error counters and the 16550 event register The modem interface lines can be monitored by the port C pins 4 4 5 9 1 IDLE Sequence Receive An IDLE is detected when one character consisting of all ones is received The 16550 controller emulates IDLE reception The 16550 emulation TX FIFO is polled by the RISC controller every programmable amount of time When the Tx FIFO is empty the RISC controller assumes reception of an IDLE character When the 16550 is receiving data into a receive buffer and an IDLE is received the channel counts the number of consecutive IDLE characters received If the count reaches the value pro grammed into MAX_IDL the buffer is closed and an RX interrupt is generated If no receive buffer is open this event does not generate an interrupt or any status information The inter nal idle counter IDLC is reset every time a character is received MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 4 5 9 2 BREAK Sequence The 16550 controller offers very flexible BREAK support for the receiver When the PC sets the Set Break bit in the LCR register or a BREAK sequence is received the 16550 controller increments the break error coun
231. in the mode reg ister EMR and after a STOP TRANSMIT command The 16550 controller will resume transmission from the current transmitter buffer in the Tx BD Table 4 4 5 5 16550 RECEIVE COMMANDS 4 4 5 5 1 ENTER HUNT MODE Command After a hardware or software reset and after the channel has been enabled by setting the receive enable bit in the EMR register the channel will be in the transmit enable mode and will use the first buffer in the table The ENTER HUNT MODE command is used to force the 16550 controller to close the current Rx BD if data is being received using it The command generates an RX interrupt if enabled as the buffer is closed The 16550 controller will resume reception using the next BD once a single IDLE character is received 4 4 5 6 16550 CONTROL CHARACTERS RECEIVER The 16550 controller has the capability to recognize special control characters transferred from the PC to the card These characters may be used when the 16550 functions in a message oriented environment Up to eight control characters may be defined by the user in the control characters table Each of these characters may be either written to the receive buffer upon which the buffer is closed and a new receive buffer taken or rejected If rejected the character is written to the received control character register RCCR in internal RAM and a maskable interrupt is gen erated This method is useful for notifying the user of the arrival of control cha
232. ing BAR and SCR must be synchronous to the IMP clock Synchronous read accesses may occur with one wait state if EMWS is also set to one MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc RME RAM Microcode Enable This bit is used to initiate the execution of Communication Processor microcode that has been loaded into the dual port RAM 3 1 4 Hardware Watchdog The hardware watchdog logic is used to assert an internal BERR BERR is driven externally wi the PCMCIA interface is disabled and set HWT when a bus cycle is not terminated by DTACK and after a programmable number of clock cycles has elapsed The hardware watchdog logic uses four bits in the SCR HWDEN Hardware Watchdog Enable 0 The hardware watchdog is disabled 1 The hardware watchdog is enabled After system reset this bit defaults to one to enable the hardware watchdog HWDCN HWDCNO Hardware Watchdog Count 2 0 000 BERR is asserted after 128 clock cycles 8 us 16 MHz clock 001 BERR is asserted after 256 clock cycles 16 us 16 MHz clock 010 BERR is asserted after 512 clock cycles 32 us 16 MHz clock 011 BERR is asserted after 1K clock cycles 64 us 16 MHz clock 100 BERR is asserted after 2K clock cycles 128 us 16 MHz clock 101 BERR is asserted after 4K clock cycles 256 us 16 MHz clock 110 BERR is asserted after 8K clock cyc
233. ing Character Length and Parity ccceccesseeeeeeeeeeeeeeeeees 4 16 Autobaud Reception Error Handling Procedure cccseeeeeereeeeeees 4 16 Autobaud Transmission i c tak sew akin ya es ile ea eee 4 17 PAU TOMAR CE CMO Ga tiated eh Sie heh edt Ne ted waite leche ates 4 17 Sma ECMO sic cecee a ee eases cence ee eee tebe ats 4 17 Reprogramming to UART Mode or Another Protocol eee 4 18 PALS COW ONG EAEE bah ca cites E A one datee enacndeeelyt 4 18 HDLC Memory Wap ds2 ici ects eR echt beads ie hel ak ce ce Sa lee he ads 4 18 HDLC Mode Register ccccceeeseceecceeeeeeeeeeeeeeeeeeeeseaaeaeeeeeeeeeneneeeeees 4 19 HDLC Receive Buffer Descriptor RX BD ceeeeeeeeeeeeeeeeeeeeeeeees 4 19 HDLC Transmit Buffer Descriptor TX BD cccecesseeeeeeeeeeeeeeeeeeeees 4 19 ADEC Event Register siirre a E Aa 4 20 HDLC Mask Register Krataticachi steer neh tes iit Weta 4 20 BISYNC Controller aii crete eee ts A ale ue earch cc cane 4 20 BISYNC Memory Map ccccceeeeeeeeceeeeeeeeeeeeeeeeeeeeseneaaeeeeeeeeeeeeeeaeeeees 4 20 BISYNC Mode Register ccccsssecceeeeeeeeeeeceeeeeeeeeeaeeaeeeeeeesennseeeeeees 4 20 BISYNC Receive Buffer Descriptor RX BD cceeeeeeeeeeeeeeeeeeeeeees 4 21 BISYNC Transmit Buffer Descriptor TX BD eeeceeeeeeeeeeeeeeeeeeeeeees 4 21 BISYNC Event Register ccccccccsecceeeeeeeeseeceeeeeeeeseaaeaeeeeeeesesnneaeeee
234. ing a means to escape from unexpected input conditions external events or programming errors Timer 3 may be used for this purpose Once started the watchdog timer must be cleared by software ona regular basis so that it never reaches its timeout value Upon reaching the timeout value the assumption may be made that a system failure has occurred and steps can be taken to recover or reset the system No changes have been made to the software watchdog timer Please refer to the MC68302 Users Manual for more information 3 7 2 1 Software Watchdog Reference Register WRR WRR is a 16 bit register con taining the reference value for the timeout The EN bit of the register enables the timer WRR appears as a memory mapped read write register to the user 15 1 0 REFERENCE VALUE EN 3 7 2 2 Software Watchdog Counter WCN WCN a 16 bit up counter appears as a memory mapped register and may be read at any time Clearing EN in WRR causes the counter to be reset and disables the count operation A read cycle to WCN causes the cur rent value of the timer to be read A write cycle to WCN causes the counter and prescaler to be reset A write cycle should be executed on a regular basis so that the watchdog timer is never allowed to reach the reference value during normal program operation 3 7 3 Periodic Interrupt Timer PIT The MC68PM302 provides a timer to generate periodic interrupts for use with a real time operating system or the applicat
235. ins Each of these five pins can be used either as a dedicated timer function or as a general purpose port B I O port pin Note that the timers do not require the use of external pins TIN1 PB3 Timer 1 Input or Parallel IO This input is used as a timer clock source for timer 1 or as a trigger for the timer 1 capture register TIN1 may also be used as the external clock source for any or all three SCC baud rate generators TOUT1 PB4 PC_A10 Timer 1 Output or Parallel IO or PCMCIA Address The TOUT1 output is used as an active low pulse timeout or an event overflow output toggle from timer 1 The PC_A10 input is driven by the PCMCIA card interface See Section 5 PCMCIA Con troller MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description TIN2 PB5 Timer 2 Input or Parallel IO This input can be used as a timer clock source for timer 2 or as a trigger for the timer 2 capture register TOUT2 PB6 Timer 2 Output This output is used as an active low pulse timeout or as an event overflow output toggle from timer 2 WDOG PB7 Watchdog Output This active low open drain output indicates expiration of the watchdog timer WOOG may be externally connected to the RESET and HALT pins to reset the IMP When WDOG is asserted it will remain asserted for 16 IMP system clock cycles if the IMP PLL is not en abled by the MODCLK pins or 16 clock
236. iod of the device for which the specs were derived e g 40 ns with a 25 MHz device and Sa is the actual spec in the data sheet Thus for spec 14 at 25 MHz M 5 40 ns 2 80 ns 20 ns Once the margin M is calculated for a given spec a new value of that spec Sn at another clock frequency with period Pa is calculated as Sn N Pa 2 M Thus for spec 14 at 12 5 MHz Sn 5 80 ns 2 20 ns 180 ns These two formulas assume a 50 duty cycle Otherwise if N is odd the previous values N P 2 and N Pa 2 must be reduced by X where X is the difference between the nominal pulse width and the minimum pulse width of the EXTAL input clock for that duty cycle 3 If 47 is satisfied for both DIACK and BERR 48 may be ignored In the absence of DIACK BERR is a synchronous input using the asynchronous input setup time 47 4 For power up the IMP must be held in the reset state for a minimum 100 ms to allow stabilization of on chip circuit This time could be longer to allow the PLL to lock see 7 6 1 IMP AC Electrical Specifications Control Timing After the system is powered up 56 refers to the minimum pulse width required to reset the processor 5 If the asynchronous input setup 47 requirement is satisfied for DIACK the DTACK asserted to data setup time 31 requirement can be ignored The data must only satisfy the data in to clock low setup time 27 MC68PM302 REFERENCE MANUAL For More Information On This
237. ion XTAL should be left unconnected The oscillator uses an internal frequency equal to the external crystal frequency The frequency of EXTAL may range from 0 Mhz to 20 MHz or the maximum rated frequency whichever is higher When an external clock is used it must provide a CMOS level at this input frequency In this manual many references to the frequency 16 67 MHz are made when the maxi mum operating frequency of the MC68PM302 is discussed When using faster versions of the MC68PM302 such as 20 MHz all references to 16 67 MHz may be replaced with 20 MHz Note however that resulting parameters such as baud rates and timer periods change accordingly XTAL Crystal Output This output connects the on chip oscillator output to an external crystal If an external clock is used XTAL should be left unconnected CLKO Clock Out This output clock signal is derived from the on chip clock oscillator This clock signal is internally connected to the clock input of the M68000 core the communication processor and system integration block All M68000 bus timings are referenced to the CLKO signal CLKO supports both CMOS and TTL output levels The output drive capability of the CLKO signal is programmable to one third two thirds or full strength or this output can be disabled XFC IMP External Filter Capacitor This pin is a connection for an external capacitor to filter the PLL GNDSYN Analog PLL Circuits Ground Th
238. ion of an event the transparent controller sets the corre sponding bit in the transparent event register Interrupts generated by this register may be masked in the transparent mask register This register is cleared at reset 7 6 5 4 3 2 1 0 CTs cD TXE RCH BSY TX RX 4 3 12 6 TRANSPARENT MASK REGISTER The SCC mask register SCCM is referred to as the transparent mask register when the SCC is operating as a transparent controller It is an 8 bit read write register that has the same bit format as the transparent event regis ter If a bit in the transparent mask register is a one the corresponding interrupt in the event register will be enabled If the bit is zero the corresponding interrupt in the event register will be masked This register is cleared at reset 4 4 16550 EMULATION CONTROLLER NEW FEATURE 4 4 1 16550 Emulation Controller Features Contains PC port side that implements the full register set external pins external pin timing and interrupt structure of the 16550 The 16550 UART registers are accessible from the PCMCIA port in any page of I O space The emulation controller can optionally scale the transfer rates to and from the PC to match the speeds of a real 16550 The interface to the 68000 core maintains the standard 68302 programming model of a normal SCC in UART mode Data is transferred between the 68000 bus and the 16550 emulation controller using SDMA transfers under RISC con
239. ion software The periodic interrupt time period can vary from 122 us to 128 s assuming a 32 768 kHz crystal is used to generate the general system clock This function can be disabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB 3 7 3 1 Overview The periodic interrupt timer consists of an 11 bit modulus counter that is loaded with the value contained in the PITR The modulus counter is clocked by the CLKIN signal derived from the IMP EXTAL pin See Figure 2 3 The clock source is divided by four before driving the modulus counter PITCLK When the modulus counter value reaches zero an interrupt request signal is generated to the IMP interrupt controller The value of bits 11 1 in the PITR is then loaded again into the modulus counter and the counting process starts over A new value can be written to the PITR only when the PIT is disabled The PIT interrupt replaces the IMP PB8 interrupt and is mapped to the PB8 interrupt priority level 4 The PIT interrupt can be masked using the corresponding bit in the IMR NOTE When the PIT is enabled PB8 can still be used as parallel I O DREQ PC_DREQ pin or as DRAM refresh controller request pin but PB8 will not be capable of generating interrupts 3 7 3 2 Periodic Timer Period Calculation The period of the periodic timer can be calcu lated using the following equation PITR cou
240. ions GCl Timing ceceeeeee 7 6 17 IMP AC Electrical Specifications PCM Timing cceeeee 7 6 18 IMP AC Electrical Specifications NMSI Timing c cee 7 6 19 AC Electrical Specifications PCMCIA Interface ceee Section 8 Mechanical Data and Ordering Information 8 1 PIN ASSIQMMEGING enee et Acre eter a aeaa EEEa BAe ed eeo arse 8 1 1 Pin Grid Array POA ea a i tiie canted tel a EEEE 8 1 2 Surface Mount TOFP viteceiscasdccsbeccdadusketasertdatevvnetdandatyeransedieiiels 8 2 Package Dimensions ccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneaeeeeeeeeeeee 8 2 1 Pin Grid Array P GAM dren ed o a A oaa nase Acre 8 2 2 Surface Mount TOF P artna eare aaa E r Eaa Eai 8 3 Ordering InformatO Mirisni aaa MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Page Number imiia 7 3 Freescale Semiconductor Inc SECTION 1 INTRODUCTION Motorola has developed a derivative version of the well known MC68302 integrated multi protocol processor IMP called the MC68PM302 The PM302 has two modes of operation In the first mode it functions as an enhanced MC68302 with a new static 68000 core a new timer and low power modes and additional parallel I O pins In the second mode it functions as the same enhanced MC68302 but with PCMCIA and 16550 UART functionality instead of the additional parallel I O pins The PM302 is packaged in a low pr
241. is 8 bit read write register does not control the 16550 in any way It is intended as a scratchpad register to be used by the PC to hold data temporarily 4 4 5 68000 Programming Model SCC2 can be configured as a 16550 emulation controller by programming its mode register SCM into UART16550 mode MODE1 MODEO 11 BRG2 should be programmed to the appropriate rate after reading the 16550 emulation divisor latch It uses the same data struc ture as the SCCs in the other modes The 16550 data structure supports multi buffer oper ation The user can program the 16550 emulation controller to accept or reject control characters If a control character is rejected an interrupt may be generated The 16550 emulation controller enables the user to transfer break sequences parity and framing errors to the PC via the buffer descriptor table An indication of the status of the 16550 emulation transmit FIFO IDLE is reported through the status register and a maskable interrupt is generated upon a status change In its simplest form the 16550 can function in a character oriented environment Each character is transmitted with accompanied stop bits and parity as configured by the user and received into separate one byte buffers Reception of each buffer may generate a maskable interrupt 4 4 5 1 16550 MEMORY MAP When the 16550 emulation controller is enabled the 68PM302 overlays the structure illustrated in Table 4 2 with the 16550 emulation controlle
242. is active These lines are outputs when the IMP M68000 core SDMA IDMA or PCMCIA Controller is the bus master and are inputs otherwise The function codes output by the M68000 core are predefined whereas those output by the SDMA and IDMA are programmable The function code lines are inputs to the chip select logic and IMP internal register decoding in the BAR The bidirectional PCMCIA card interfaces to the data bus When the MC68PM302 is not enabled for PCMCIA these pins are used for SCC2 signals function codes and additional address lines A23 A20 6 2 SUMMARY OF PIN MULTIPLEXING The following table defines the actual function of the pins as a function of the mode of oper ation On the left column the pin is identified with all its possible functions In the table cells the actual function of the pin is specified according to the mode defined in the column head er This table specifies pin muxing determined by mode pins PC_EN and DISCPU and by the Package type TQFP or PGA it does not specify muxing determined by software pro gramming of registers MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description Table 6 12 Pin Muxing PC_EN 1 PC_EN 1
243. is bit is set when a control character was received with reject character bit in the control character table R bit 1 and stored in the receive control character register RCCR BSY Busy Condition This bit is set when a character was received and discarded due to lack of buffers Recep tion continues as soon as an empty buffer is provided TX Tx Buffer This bit is set when a buffer has been transmitted over the 16550 channel If CR 1 in the Tx BD this bit is set no sooner than when the last stop bit of the last character in the buffer begins to be transmitted If CR 0 this bit is set after the last character was written to the transmit FIFO RX Rx Buffer This bit is set when a buffer has been received over the 16550 channel This event occurs no sooner than the middle of the first stop bit of the character that causes the buffer to be closed IDL IDLE Sequence Status Changed This bit is set when a change in the status of the serial line is detected on the 16550 chan nel The real time status of the line may be read in SCCS Idle is entered when 16550 em ulation FIFO has been empty for at least one full character time It is exited when a character is received LCR Line Control Register Write This bit is set when the PC writes to the 16550 LCR emulation register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP DL
244. is pin is dedicated to the IMP analog PLL circuits The pin should be provided with an extremely low impedance path to ground GNDSYN should be bypassed to VCCSYN by a 0 1uF capacitor located as close as possible to the chip package 6 1 3 System Control Pins The system control pins are shown in Figure 6 3 RESET lt HALT lt a PC_A3 BERR Figure 6 3 System Control Pins RESET Reset This bidirectional open drain signal acting as an input and asserted along with the HALT pin starts an initialization sequence called a total system reset that resets the entire IMP MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc RESET and HALT should remain asserted for at least 100 ms at power on reset and at least 10 clocks otherwise The on chip system RAM is not initialized during reset except for several locations initialized by the CP NOTE With a 32 768KHz external crystal the minimum RESET length is 2 3 seconds An internally generated reset from the M68000 RESET instruction causes the RESET line to become an output for 124 clocks In this case the M68000 core is not reset how ever the communication processor is fully reset and the system integration block is al most fully reset refer to 2 6 Internal Registers Map for a list of the unaffected registers The user may also use the RESET output signal in this case to r
245. is set in the PCAWMR NOTE Read accesses by the PC to one of the PCMCIA configuration registers will not wake up the IMP MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc The appropriate event bit will be set regardless of the corresponding mask bit in the PCR WMR If the corresponding mask bit is set an interrupt will be generated The PCAWER is a memory mapped register that may be read at any time A bit is reset by writing a one and is left unchanged by writing a zero More than one bit may be reset at a time and the register is cleared by reset IOS IO Space Access This bit is set when the PC accesses the 16550 emulation module an I O space access is made When the IMP is in stand by mode the IMP will resume its operation An inter rupt may be generated if the corresponding mask bit is set This bit is cleared by writing one ATS Attribute Space Access This bit is set when the PC accesses the CIS memory When the IMP is in stand by mode the IMP will resume its operation An interrupt may be generated if the corresponding mask bit is set This bit is cleared by writing one NOTE PC writes to one of the PCMCIA configuration registers while the IMP is in stand by mode will also resume operation The 68000 will be able to detect it by the 5 3 5 PCMCIA Access Wake Up Event Register PCAWER CMSIi1 Common Memory Space Acce
246. isters PCMCIA attribute addresses 2000000 or higher The 68000 core software may then signal that the card is ready by setting the RDY BSY line in the pin replacement register PRR The host reads the CIS from attribute memory This is done by the host performing an at tribute space read cycle to address 0 The PCMCIA controller detects the cycle asserts the WAIT signal on the PCMCIA lines and arbitrates for the 68000 bus When granted the con troller generates the cycle on the 68000 bus The high address bits and FC are taken from the CIS base address register the low address bits are taken from the PCMCIA address lines When the cycle is terminated with DTACK the 68000 bus will be released data will be transferred to the PCMCIA data lines and the WAIT signal will be negated The host reads the CIS by this mechanism The host can then initialize the configuration registers The host can access these registers directly without using the 68000 bus When A25 is high on an attribute space cycle the PC MCIA controller can asynchronously access the configuration registers Those registers can also be accessed by the 68000 core The 68000 core can read and write these registers like any other register in the 68000 address space The PCMCIA controller may also generate an interrupt to the 68000 core when one of the registers is written by the PC After the initialization is completed the MC68356 is configured for either PCMCIA common
247. it 0 in PCMR In non PCMCIA mode these eight pins can be used either as the NMSI2 port or as a general purpose parallel I O port Each one of these pins can be configured individually to be gen eral purpose I O pins or a dedicated function in NMSI2 When they are used as NMSI2 pins they function exactly as the NMSI1 pins in NMSI mode MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc wt RXD2 PA0 PC_D8 q gt TXD2 PA1 PC_D9 H RCLK2 PA2 PC_D10 lt gt TCLK2 PA3 PC_D11 a gt CTS2 PA4 PC_D12 gt RTS2 PA5 PC_D13 ap CD2 PAG PC_D14 p gt BOOT BRG2 SDG2 PA7 PC_D15 Figure 6 11 NMSI2 Port or Port A Pins The PA7 signal in dedicated mode becomes serial data strobe 2 SDS2 in IDL and GCI modes In IDL GCI modes the SDS2 SDS1 outputs may be used to route the B1 and or B2 channels to devices that do not support the IDL or GCI buses This is configured in the Sl MODE and SIMASK registers If SCC2 is in NMSI mode this pin operates as BRG2 the out put of the SCC2 baud rate generator unless SDS2 is enabled to be asserted during the B1 or B2 channels of ISDN bits SDC2 SDC1 of SIMODE SDS2 BRG2 may be temporarily disabled by configuring it as a general purpose output pin TCLK2 acts as the SCC2 baud rate generator output if SCC2 is in one of the multiplexed modes e RXD2 PA0 PC_D8 TXD2 PA1 PC_D9 RCLK2 PA2 PC_D10 TCLK2 PA3 PC_D11 CTS
248. it data TXD1 L1TXD O Receive Clock Layer 1 clock RCLK1 L1CLK O ISON E e 1 TCLKI LISYO SDS1 vo Carrier Detect Layer 1 Sync CDT L1SY1 l Clear To Send Layer 1 Grant CTST L1GR 1 Request To Send Layer 1 Request GCI Clock Out RTS1 L1RQ GCIDCL O Receive Data Port A PCMCIA Data RXD2 PA0 PC_D8 O Transmit Data Port A PCMCIA Data TXD2 PA1 PC_D9 O NMSI2 or Receive Clock Port A PCMCIA Data RCLK2 PA2 PC_D10 O PORT A Transmit Clock Port A PCMCIA Data TCLK2 PA3 PC_D11 O PON an Clear To Send Port A PCMCIA Data CTS2 PA4 PC_D12_ I O Data Request To Send Port A PCMCIA Data RTS2 PA5 PC_D13 O Carrier Detect Port A PCMCIA Data CD2 PA6 PC_D14 O Baud Rate Generator 2 Output Port A PCMCIA Data BOOT BOET PRET I O Receive Data Port A RXD3 PA8 O Transmit Data Port A TXD3 PAQ9 O Receive Clock Port A RCLK3 PA10 O NMSI3 or PORT A Transmit Clock Port A TCLK3 PA11 O eee Pins SCP Receive Serial Data Clear To Send SPRXD CTS3 l SCP Transmit Serial Data Request To Send SPTXD RTS3 O SCP Clock Carrier Detect SPCLK CD3 O Mode Clock Select Baud Rate Generator 3 Output Port A MODCLK BRG3 PA12 I O PCMCIA or PCMCIA IO Read DMA Request Port A PC_IORD DREQ PA13 I O IDMA Pins or PCMCIA IO Write DMA Acknowledge Port A PC_IOWR DACK PA14 VO FORTA PCMCIA IO Write Enable DMA Done Port A PC_WE DONE PA15 O PCMCIA or PCMCIA Address Interrupt Acknowledge Port B PC_A11 IACK7 PBO O IACK
249. ition of all pins during reset MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 7 ELECTRICAL CHARACTERISTICS The AC specifications presented consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of the clock CLKO pin and possibly to one or more other signals VERY IMPORTANT NOTE REGARDING SIGNALS A few signals have been added to and removed from the 68PM302 or their functionality has changed Several signals are only available when 68302 is in CPU disable mode or when the PCMCIA interface is disabled The IAC signal is only available on the PGA package The RMC and BCLR signals have been removed please ignore any reference to these two signals The following diagrams and tables show the timing for all available signals For complete information on which signals are available in which modes CPU disable and or PCMCIA disable please refer to Section 6 Signal Description 7 1 MAXIMUM RATINGS Rating Symbol Value Unit gl ae gece contains rake to protect the inputs against damage Supply Voltage Vpop 0 3 to 7 0 V due to high s atie voltages or elec ric fields however it is advise Input Voltage Vin Cee y that normal precautions be taken Current Drain per Pin excluding Veg and Vsg ma to avoid application of any voltage higher than maximum rated
250. k from Ringo to the real clock once it is stable 10 Enable the real clock and generate an interrupt to the CPU after the switch occurs 11 Reserved RICR Ring Oscillator Interrupt Control 00 Connect Ringo Interrupts to 68k interrupt request level 1 01 Connect Ringo Interrupts to 68k Interrupt request level 6 10 Connect Ringo Interrupts to 68k interrupt request level 7 11 Reserved 2 4 4 3 6 Ring Oscillator Event Register RINGOEVR RINGOEVR BAR 81B 7 6 5 4 3 2 1 0 RESERVED RECLSEV RESET 0 0 0 0 0 0 0 0 Read Write RECLSEV Real Clock Switch Event 0 Event has not occurred 1 Real clock is now the system clock This bit is reset by writing 1 Bits 7 1 Reserved 2 5 MC68PM302 DUAL PORT RAM The internal 1152 byte dual port RAM has 576 bytes of system RAM see Table 2 4 and 576 bytes of parameter RAM see Table 2 5 Table 2 4 System RAM Address Width Block Description Base 000 576 Bytes RAM User Data Memory Base 23F Base 240 X Reserved Not Implemented Base 3FF The parameter RAM contains the buffer descriptors for each of the three SCC channels the 16550 channel or SCC2 the SCP and the two SMC channels The memory structures of the three SCC channels are identical When any SCC SCP or SMC channel buffer descrip tors or parameters are not used their parameter RAM area can be used for additional mem ory For detailed information about the u
251. l memory 4 4 5 12 16550 EVENT REGISTER The 16550 event register SCCE is called the 16550 event register when the 16550 is enabled It is a 16 bit register used to report events to the 68000 core recognized by the 16550 emulation controller and is also used generate inter rupts On recognition of an event the 16550 controller will set the corresponding bit in the 16550 event register Interrupts to the 68000 core generated by this register may be masked in the 16550 mask register The 16550 event register is a memory mapped register that may be read by the 68000 at any time A bit is cleared by writing a one writing a zero does not affect a bit s value More than one bit may be cleared at a time All unmasked bits must be cleared before the CP will clear the internal interrupt request This register is cleared at reset MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc E550 Base 898 15 14 13 12 11 10 9 8 RES RES RES BRK CCR BSY TX RX RESET 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 IDL LCR LOOP DL OUT2 OUT1 RTS DTR RESET 0 0 0 0 0 0 0 0 Read Write Bits 15 13 Reserved Should be written with zeros BRK Break This bit is set when a break character is received This is the first break of a break se quence Multiple break events will not be generated if a long break sequence is received CCR Control Character Received Th
252. lation time out and the 302 idle emulation 4 4 2 1 16550 EMULATION CONTROLLER FIFOS OVERVIEW The 16550 controller has separate transmit and receive FIFO s for implementing 16550 mode which is enabled by set ting the FIFO enable bit in the FIFO control register Figure 4 11 shows the receiver FIFO which transfers data from the CP 16550 transmit buffer descriptors via the communication processor s peripheral bus to the PC via the PCMCIA bus The FIFO is 16 bytes deep and includes three error bits that are attached to each byte and are decoded in the line status register as each byte reaches the top of the FIFO The data is never serialized in the pro cess The baud rate clock is provided by BRG2 and can be divided down further by a 4 bit counter The 4 bit counter is useful to slow the baud rate clock down to a rate that emulates the serial transfer rates of a true 16550 while allowing the baud rate generator itself to be programmed with traditional values used for serial UART rates This will keep the receive interrupt rate to the PC at the level it is used to handling and prevent the PC from being inun dated with bursts of fast interrupts 4 4 3 PC Accesses The PC accesses the 16550 emulation registers through the PCMCIA interface using I O space accesses These read and write cycles are synchronized with the IMP clock The IMP clock rate affects the synchronization time and the cycle length When using low rate clocks WAIT should be asserte
253. le Semiconductor Inc Auto Increment 5 25 BERR 5 13 Block Diagram 5 1 Burst Access Cycles 5 9 Bus Watchdog Timer 5 14 Card Common Memory Space Address Map 5 12 Card Configuration Registers 5 5 5 31 Card Information Structure 5 6 CIS 5 3 Common Memory Accesses 5 8 5 11 Common Memory Burst Access Mode 5 3 Common Memory Read 5 12 Common Memory Write 5 12 Configuration Registers 5 5 Configuration Registers Write Event Register PCRWER 5 26 Configuring for I O Mode 5 13 Controller Block Diagram 5 4 Direct Access Mode Accesses 5 8 Direct Addressing Using ABUF 5 11 Functional Overview 5 2 Host Interrupts 5 17 I O Space Accesses 5 7 IORD 5 7 IOWR 5 7 IREQ Pin 5 17 Key Features 5 1 Memory Space Protection 5 12 PCMCIA Controller Accesses 5 22 PCMCIA Controller Initialization 5 13 PCMCIA Host PC Event Register PCHER 5 29 PCMCIA Host Interrupts 5 17 PCMCIA Pins 5 19 PCMCIA Ring Indication 5 15 PCMCIA to 68000 Bus Access and Monitoring Options 5 13 PCMR 5 22 Pins 5 19 Pins Not Supported 5 19 Power Down Options 5 14 PwrDwn 5 3 5 17 PwrDwn Bit 5 14 Rdy Bsy Signal 5 19 Registers Access Map 5 7 Reset 5 20 STAND _BY 5 14 STOP 5 14 Tuple TPCC_RADR 5 13 UART 16550 Registers 5 3 WAIT Signal 5 9 Wake Up from STAND BY Mode 5 17 Wake Up Options 5 16 Wake Up using the PwrDwn Bit 5 16 PCMCIA or Port D Pins 6 28 PCMCIA Pins 6 29 6 30 PCMCIA Protection Register PPR 3 27 PCMR 5 22 5
254. les 512 us 16 MHz clock 111 BERR is asserted after 16K clock cycles 1 ms 16 MHz clock After system reset these bits default to all ones thus BERR will be asserted after 1 ms for a 16 MHz system clock 3 1 5 Freeze Control Used to freeze the activity of selected peripherals FRZ is useful for system debugging pur poses When FRZ is asserted For more information on these bits please refer to the MC68302 Users Manual FRZ1 Freeze Timer 1 Enable 0 Freeze Timer 1 Logic is disabled 1 Freeze Timer 1 Logic is enabled After system reset this bit defaults to zero FRZ2 Freeze Timer 2 Enable 0 Freeze Timer 2Logic is disabled 1 Freeze Timer 2Logic is enabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB After system reset this bit defaults to zero FRZW Freeze Watchdog Timer Enable 0 Freeze Watchdog Timer Logic is disabled 1 Freeze Watchdog Timer Logic is enabled After system reset this bit defaults to zero 3 2 PROGRAMMABLE DATA BUS SIZE SWITCH The following procedure allows MC68PM302 to be booted in an 8 or 16 bit bus width and then switched to 16 or 8 bit bus width for future accesses It does not implement true dynamic bus sizing but allows a software reconfiguration of the BUSW pin 3 2 1 Enabling the Dynamic Bus Switch In order to enable the dynamic bus switch the user must write the
255. letes its transition to the power down STOP mode Of the three different power down modes the STAND_BY mode is the only one in which a normal host PCMCIA interface access will cause the IMP to resume operation see 5 1 10 1 Wake Up on PCMCIA Access in STAND BY mode The 68000 core can also place the card into one of four different low power modes when the card is idle for long periods of time and it is desired to conserve power Table 2 3 even if the PC does not initiate the power down transition The PC can access the configuration registers while in power down MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller Table 5 11 IMP Low Power Modes Low Power Mode Method of Entry Comments Slow Go Write to DF3 DFO in PCMCIA I F functional no wake up time higher IOMCR power consumption than other STOP mode 7 7 The imp can detect any PCMCIA access and wake Stand by STOP LPM 01 Uy 2 5 cycle wake up time gt The IMP wakes up on setting of PwrDwn bit in Doze STOP LPM 10 GCSR 2500 cycle wake up time Stop STOP LPM 11 The IMP wakes up on setting of PwrDwn bit in CCSR 70000 max cycle wake up time In addition to placing itself ina STOP mode the 68000 core can also lower the system clock frequency to save power by writing a higher value divide factor to the PLL clock divider In this mode the IMP and PCM
256. locks that are generated by the IMP PLL are disabled After hardware reset the MF11 MFO bits default to either 0 3 or 400 190 hex depending on the MODCLK and VCCSYN pins giving a multiplication factor of 1 4 or 401 If the mul tiplication factor is 401 then a standard 32 768 kHz crystal generates an initial general system clock of 13 14 MHz If the multiplication factor is 4 then a standard 4 192 MHz MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freasgate senicenducter wid amp G lt and Internal Memory Map crystal generates an initial general system clock of 16 768 MHz The user would then write the MF bits or adjust the output frequency to the desired frequency NOTE Since the clock source for the periodic interrupt timer is CLKIN see Figure 2 2 the PIT timer is not disturbed when the IMP PLL is in the process of acquiring lock PEN PLL Enable Bit The PEN bit indicates whether the IMP PLL is operating This bit is written by the MC68PM302 based on the value of VCCSYN during reset When the IMP PLL is disabled the VCO is not operating in order to minimize power consumption During hardware reset this bit is set if the VCCSYN pin specifies that the IMP PLL is enabled The only way to clear PEN is to hold the VCCSYN pin low during a hardware reset 0 The IMP PLL is disabled Clocks are derived directly from the EXTAL pin 1 The IMP PLL is enabled Clocks are derived from
257. luding Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part gt 2 freescale MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com
258. m SCON to input frequency baud rate 1 where the input frequency is either the system clock or the clock on TIN1 2 Program the DSR to FFFF The DSR will need to be programmed back to 7FFF be fore the Enter_Baud_Hunt command is issued again 3 Set the ENT bit in the mode register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 Program the transmit character BD as show in Table 4 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PET PM CHAR Table 4 8 Transmit Character BD R Ready Bit 0 Character is not ready 1 Character is ready to transmit CL Character Len 0 7 bits parity or 8 bits with no parity 1 8 bits parity PE Parity Enable 0 No parity 1 Parity PM Parity Mode 0 Even parity 1 Odd parity The autobaud controller issues a Tx interrupt after each character is transmitted 4 3 9 9 REPROGRAMMING TO UART MODE OR ANOTHER PROTOCOL The following steps should be followed in order to switch the SCC from autobaud to UART mode or to another protocol Disable the SCC by clearing ENR and ENT Issue the Enter_Hunt_Mode command Initialize the SCC parameter RAM specifically the Rx and Tx internal states and the words containing the Rx and Tx BD s to the state immediately after reset and initialize the protocol specific parameter area for the new protocol Re enable the SCC with the new
259. mory Space Base Ad dress Register1 CMBAR2 PCMCIA Reserved Common Memory Space Base Ad dress Register2 Pull Up Control Register Reserved Reserved Port D Data Register Reserved Baud Rate Generator Pins Register Base 8EF Reserve d Base 8F0 EMR 16 16550 16550 Emulation Mode Register Base 8F2 LCR 8 16550 16550 Emulation Line Control Register 00 Base 8F3 MSR 8 16550 eak Emulation Modem Status Regis Base 8F4 DLM 8 16550 16550 Emulation Divisor Latch MSB Base 8F5 DLL 8 16550 16550 Emulation Divisor Latch LSB Base 8F6 LSR 8 16550 16550 Emulation Line Status Register 00 Base 8F7 Base FFF Reserved Not implemented Reset only upon total system reset RESET and HALT assert together but not on the execution of an M68000 RESET instruction See the RESET pin description for details The output latches are undefined at total system reset Event register with special properties MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senvueandaetesn Inc MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 3 SYSTEM INTEGRATION BLOCK SIB The MC68PM302 contains an extensive SIB that simplifies the job of both the hardware and software designer Most
260. mory structures and memory mapped registers to communicate with the M68000 core All the structures detailed in the following paragraphs reside in the dual port RAM of the IMP The SMC buffer descriptors allow the user to define one data byte at a time for each transmit channel and receive one data byte at a time for each receive channel 4 6 2 1 SMC1 RECEIVE BUFFER DESCRIPTOR The CP reports information about the received byte using this BD 1 7 0 5 14 13 12 11 10 9 8 eej om MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 6 2 2 SMC1 TRANSMIT BUFFER DESCRIPTOR The CP reports information about this transmit byte through the BD R L AR AB EB DATA 4 6 2 3 SMC2 RECEIVE BUFFER DESCRIPTOR In the IDL mode this BD is identical to the SMC1 receive BD In the GCI mode SMC2 is used to control the C I channel 15 14 6 5 2 1 0 RESERVED C I 0 0 4 6 2 4 SMC2 TRANSMIT BUFFER DESCRIPTOR In the IDL mode this BD is identical to the SMC1 transmit BD In the GCI mode SMC2 is used to control the C I channel 15 14 6 5 2 1 0 RESERVED C I 0 0 R Ready 0 This bit is cleared by the CP after transmission to indicate that the BD is now avail able to the M68000 core 1 This bit is set by the M68000 core to indicate that the data associated with this BD is ready for tr
261. n high when the LPDEN bit is set 1 The address bus will be driven low when the LPDEN bit is set NOTE In 8 bit non PCMCIA mode AO is also driven during low power With the PGA package in non PCMCIA mode the FC2 FCO pins are also driven during low power With the TQFP package in non PCMCIA mode the PC_D1 PC_D7 pins are also driven during low power 2 4 4 1 8 IMP Power Down Register IPWRD The IPWRD is a 8 bit read write register located at 0FB that is used to control the low power operation of the IMP This register must be written with the same operand as the STOP instruction that follows This tells the hard ware what level of interrupt and above will stop the MC68PM302 from entering low power if it occurs while the clocks are being stopped 2 4 4 1 9 Default Operation Modes See 2 4 2 1 Default System Clock Generation 2 4 4 2 LOW POWER SUPPORT The following sections describe how to enter the various low power modes 2 4 4 2 1 Enter the SLOW_GO mode When the required IMP performance can be achieved with a lower clock rate the user can reduce power consumption by dividing IMP PLL output clock that provides the IMP system clock Switching between the NORMAL and SLOW_GO modes is achieved by changing the DF3 0 field in the IOMCR register to a non zero value The IMP PLL will not lose lock when the DF3 0 field in the IOMCR register is changed 2 4 4 2 2 Entering the STOP DOZE STAND_BY Mode Entering the STOP DOZE STA
262. n this is the same as Case 5 Case 5 This case is not supported because it can not be differentiated from 7 bit force 0 parity and 8 bit no parity If the 9th bit is a 1 then it will be interpreted as a STOP bit autobaud controller reports reception error conditions using the autobaud command descriptor Three types of errors are supported e Carrier Detect Lost during reception MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP When this error occurs and the channel is not programmed to control this line with software the channel terminates reception sets the carrier detect lost CD bit in the command descriptor and generates the CCR interrupt if enabled CCR is bit 3 of the SCCE register e Overrun Error When this error occurs the channel terminates reception sets the overrun OV bit in the command descriptor and generates the CCR interrupt if enabled End Of Table Error When this error occurs the channel terminates reception sets the end of table EOT bit in the command descriptor and generates the CCR interrupt if enabled Any of these errors will cause the channel to abort reception In order to resume autobaud operation after an error condition the M68000 should clear the status bits and issue the Enter_Baud_Hunt command again 4 3 9 8 AUTOBAUD TRANSMISSION The autobaud package supports two methods for
263. not changed For any additional information on parameters registers and functionality please refer to the MC68302 Users Manual MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP 4 5 1 SCP Programming Model The SCP mode register consists of the upper eight bits of SPMODE The SCP mode regis ter an internal read write register that controls both the SCP operation mode and clock source is cleared by reset 15 14 13 12 11 10 9 8 STR LOOP Cl PM3 PM2 PM1 PMO EN 4 5 2 SCP Transmit Receive Buffer Descriptor The transmit receive BD contains the data to be transmitted written by the M68000 core and the received data written by the SCP The done D bit indicates that the received data is valid and is cleared by the SCP 15 14 8 7 0 HS E 4 6 SERIAL MANAGEMENT CONTROLLERS SMCS The functionality of the SMCs has not changed For any additional information on parame ters registers and functionality please refer to the MC68302 Users Manual 4 6 1 SMC Programming Model The operating mode of both SMC ports is defined by SMC mode which consists of the lower eight bits of SPMODE As previously mentioned the upper eight bits program the SCP 7 6 5 4 3 2 1 0 E SMD3 SMD2 SMD1 SMDO LOOP EN2 ENI 4 6 2 SMC Memory Structure and Buffers Descriptors The CP uses several me
264. not sampled at initialization See 3 3 Load Boot Code from an SCC DISCPU Disable CPU M68000 Core The 68PM302 can be configured to work solely with an external CPU In this mode the on chip M68000 core CPU should be disabled by asserting the DISCPU pin high during a total system reset RESET and HALT asserted DISCPU may only be changed on a total system reset The DISCPU pin for instance allows use of several IMP family devices to provide more than three SCC channels without the need for bus isolation techniques Only one of the IMP M68000 cores is active and services the other IMPs as peripherals with their respec tive cores disabled Refer to 3 8 2 Disable CPU Logic M68000 for more details MODCLK BRG3 PA12 Clock Mode Select During reset if VCCSYN is connected to VCC the state of this input signal determines the frequency of the external clock that is to be used by the phase locked loop PLL in the clock synthesizer to generate the system clocks This pin must be valid as long as RE MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc SET and HALT are asserted and have a hold time of 5ns after RESET and HALT are ne gated After reset this pin becomes BRG3 PA12 Table 6 4 shows the default values of the PLL When the PLL is disabled VCCSYN 0 this pin functions as PA12 When the PLL is enabled VCCSYN1 this pin
265. nous During synchronous reads one wait state may be used if required EMWS bit set The following pins change their func tionality in this mode 1 THE IPLO pin becomes BR and is an output from the IDMA and SDMA to the external M68000 bus 2 The IPL2 pin becomes BG and is an input to the IDMA and SDMA from the external M68000 bus When BG is sampled as low by the IMP it waits for AS HALT and BGACK to be negated and then asserts BGACK and performs one or more bus cy cles 3 The IPL1 pin becomes BGACK and is an output from the IDMA and SDMA to indicate bus ownership 4 The IPL2 0 lines are no longer encoded interrupt lines The interrupt controller will out put the 68PM302 s interrupt request on IOUT2 CSO which is multiplexed with IOUT2 is not available in this mode 5 The WEH and WEL signals become UDS and LDS respectively 6 The OE becomes R W MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB NOTE If the PCMCIA interface is disabled then the IPL2 0 WE WEL and OE signals are available along with BR BG BGAC UDS LDS and R W I J NI J DISCPU should remain continuously high during disable CPU mode operation Although the CS0 pin is not available as an output from the device in disable CPU mode it may be enabled to provide DTACK generation In disable CPU mode BRO is initially C00
266. ns 5 1 5 Common Memory and Direct Access Mode Accesses Common memory reads and writes are initiated by the PC when it does a normal access by not asserting the PC_IORD PC_IOWR or the PC_REG pins See Table 5 8 and Table 5 9 for signal states for reads and writes Common memory reads and writes are mapped directly onto the 68000 bus using a concat enation of the lower 12 address lines from the PCMCIA address bus and upper address lines from either of the two common memory base address registers CMBAR1 2 The base address register to be used is selected by A25 CMBAR1 is used when A25 1 and CMBAR2 is used when A25 0 Both the PC and the 68000 can program the CMBARs See Table 5 10 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller In addition to the being able to perform single common memory accesses between the PC MCIA bus and the 68000 bus there is also a feature that allows the PCMCIA controller to hold onto the 68000 bus and perform multiple reads or writes without having to rearbitrate for the 68000 bus This allows the PCMCIA side access cycles to be carried out without hav ing to assert the WAIT signal for each access This mechanism works as follows When the PC initiates a common memory space cycle on the PCMCIA interface the PCM CIA controller will assert the WAIT signal on the PCMCIA lines and arbitrate for the 68000 bus Wh
267. nt Register for more details Out 2 When this bit is set the Out 2 status bit in the 16550 status register is forced to 1 When this bit is reset the Out 2 status bit in the 16550 status register is forced to 0 Out 2 status change interrupt may be generated See 4 4 5 12 16550 Event Register for more details Loop Loopback Mode When this pin is set to one the 16550 emulation controller is forced into the local loopback diagnostic feature The following occurs The four MODEM control outputs DTR RTS OUT 1 OUT 2 are internally connected to the four MODEM control inputs DSR CTS RI and DCD The 68000 core will receive the loop interrupt See Loop Loopback Mode on page 47 and will have to transfer data between the TxBDs and the RxBD to emulate the loopback feature The buffer length should only be one byte NOTE To emulate the local loopback diagnostic the slowdown mech anism should be enabled It should be enabled by the user oth erwise the loopback will be done too quickly MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP Bits 5 7 Always 0 4 4 4 1 7 MODEM Status Register MSR MSR Base 8F3 7 6 5 4 3 2 1 0 DCD RI DSR CTS DDCD TERI DDSR DCTS RESET 0 O 0 0 0 0 0 0 Read Only PC Write 68000 DCTS Delta Clear to Send This bit indicates that the CTS bit has changed st
268. nt value 1 EXTAL 10r512 4 periodic interrupt timer period Solving the equation using a crystal frequency of 32 768 kHz with the prescaler disabled gives PITR count value 1 32768 1 92 periodic interrupt timer period periodic interrupt timer period EET County ale 8192 This gives a range from 122 us with a PITR value of 0 to 250 ms with a PITR value of 7FF assuming a 32 768Khz at the EXTAL pin MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc Solving the equation with the prescaler enabled PTP 1 gives the following values PITR count value 32768 512 22 periodic interrupt timer period PITR count value 16 periodic interrupt timer period This gives a range from 62 5 ms with a PITR value of 0 to 128 s with a PITR value of 7FF For a fast calculation of periodic timer period using a 32 768 kHz crystal the following equa tions can be used With prescaler disabled programmable interrupt timer period PITR 122 us With prescaler enabled programmable interrupt timer period PITR 62 5 ms 3 7 3 3 Using the Periodic Timer As a Real Time Clock The periodic interrupt timer can be used as a real time clock interrupt by setting it up to generate an interrupt with a one second period When using a 32 768 kHz crystal the PITR should be loaded with a value of 0F with the prescaler ena
269. nterrupt Err Parity and Framing Error 00 No error is written into the 16550 emulation FIFO for the PC 01 Framing error is associated with the buffer s characters The framing error will be set in the 16550 emulation line status register when the PC reads this character 10 When the transmit Slow Down is disabled See TSDE Transmitter Slowdown Enable on page 38 the next buffer transmission will be delayed by the counter time out 11 A parity error is associated with the buffer s character The parity error will be set in the 16550 emulation line status register when the PC reads this character NOTE When parity error is transmitted to the PC the buffer will only contain a single character MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP NOTE When error is transmitted to the PC and the transmit Slow Down is disabled See TSDE Transmitter Slowdown Enable on page 38 the next buffer transmission will be delayed by the counter time out Data Length The data length is the number of octets that the CP should transmit from this BD s data buffer It is never modified by the CP This value should be normally greater than zero Tx Buffer Pointer The Tx Buffer Pointer which always points to the first location of the associated data buff er may be even or odd The buffer may reside in either internal or externa
270. nterrupt Control Functions 4 31 Interrupt Enable Register IER 4 31 Interrupt Identification Register IIR 4 30 Line Control Register LCR 4 27 Line Status Register LSR 4 28 Minimizing Host Interrupt Rate 4 24 MODEM Control Register MCR 4 31 MODEM Status Register 4 33 Overview 4 24 PC Accesses 4 24 PC Programmer Model 4 26 Receive Buffer Register RBR 4 34 RESTART TRANSMIT Command 4 39 Scratchpad Register SCR 4 35 STOP TRANSMIT Command 4 38 Transmission of Out of Sequence Characters Transmitter 4 40 Transmit Holding Register THR 4 35 Transmitter FIFO 4 26 Use of SCC2 Resources 4 24 Using Low Rate Clocks 4 24 68000 Bus 6 1 A Address AS 3 25 Decode Conflict 2 3 3 4 3 5 AS 3 4 3 25 7 27 AT Command Set 4 7 Autobaud Controller 4 7 Autobaud Command Descriptor 4 12 Autobaud Lookup Table Format 4 15 Autobaud Sampling Rate 4 14 Autobaud Transmission 4 17 Automatic Echo 4 17 Carrier Detect Lost 4 16 Channel Reception Process 4 8 Determining Character Length and Parity 4 16 End of Table Error 4 17 Enter_Baud_Hunt Command 4 12 Lookup Table 4 14 Lookup Table Example 4 15 Lookup Table Pointer 4 14 Lookup Table Size 4 14 Maximum START bit length 4 14 Overrun Error 4 17 Parameter RAM 4 10 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Index Freescale Semiconductor Inc Performance 4 7 Preparing for the Autobaud Process 4 11 Programming
271. ock Low Setup Time on 27 Read see Note 5 eee Dict Bo Seu Oe i Sel Ce eee MS AS DS Negated to DTACK Negated Asyn 28 chronous Hold see Note 2 3 Asyn tsoan 0 110 o 9 o 75 ns AS DS Negated to Data In Invalid Hold 29 Time on Head sHDI 0 i 0 LAES Se Bec 30 AS DS Negated to BERR Negated tSHBEH 0 0 0 ns DTACK Asserted to Data In Valid Setu 31 Time see Notes 2 and 5 l p DALDI 50 42 33 j ns 32 HALT and RESET Input Transition Time tRHr RH 150 150 150 ns 33 Clock High to BG Asserted tCHGL 30 25 20 ns 34 Clock High to BG Negated tcHGH 30 25 20 ns 35 BR Asserted to BG Asserted see Note 11 tgrre 2 5 4 5 2 5 4 5 2 5 4 5 clks 36 BR Negated to BG Negated see Note 7 tereh 1 5 2 5 1 5 2 5 1 5 2 5 clks MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol Unit Min Max Min Max Min Max 37 BGACK Asserted to BG Negated teaccH 2 5 45 25 45 25 4 5 ciks 37A ae Asserted to BR Negated see Note teater 10 15 10 15 10 15 Mie BG Asserted to Control Address Data Bus w pa 38 High Impedance AS Negated telz 50 42 33 ns 39 BG Wid
272. ode IMP s low power control logic will 1 Detect the write cycle 2 Check if bit 5 1 supervisor space if it is 0 the low power request will be ignored 3 Sample the interrupt mask bits bits 0 2 If during this process of stopping the clocks an interrupt of higher level than the mask is asserted to the core this process will abort 4 Wait for 16 clocks to guarantee the execution of the STOP command by the core BG and BGACK will reset the 16 clock counter and it will restart its count 5 Assert bus request signal to the core 6 Wait for Bus Grant from the core 7 Force the IMP to the selected power down mode as defined in Table 2 3 If the IMP is in STAND _BY mode any PCMCIA access will initiate a wake up from STAND_BY mode See All PCMCIA locations registers CIS memory etc that can be accessed by the host may also be accessed by the 68000 core Power Down Options NOTE The RI PB9 DTE PB10 and periodic interrupt timer timeout interrupts conditions will generate level 4 interrupts The PCM MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Fregsgatle senicenducter wid amp G and Internal Memory Map CIA controller can be programmed to generate either level 1 6 or 7 interrupts The user should also set the 68000 interrupt mask in the status register SR to the appropriate level before executing the STOP command to ensure that the IMP will wake up to t
273. oduct Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc 7 6 11 IMP AC Electrical Specifications Parallel 1 O see Figure 7 16 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol at5 0V at 5 0 V at5 0V Unit Min Max Min Max Min Max 180 Input Data Setup Time to Clock Low tosu 20 20 14 ns 181 Input Data Hold Time from Clock Low DH 10 10 19 ns Clock High to Data Out Valid 182 CPU Waites Data Control or Direction cHpov 35 30 24 ns DATA IN DATA OUT gt CPU WRITE S6 OF PORT DATA CONTROL OR DIRECTION REGISTER Figure 7 16 Parallel I O Data In Data Out Timing Diagram 7 6 12 IMP AC Electrical Specifications Interrupts see Figure 7 17 16 67 MHz 20 MHz 25 MHz Num Characteristic Symbol at5 0 V at 5 0 V at5 0V Unit Interrupt Pulse Width Low TRQ Edge Trig 180 Garod Modes Edge Trig ty 50 42 Minimum Time Between Active Edges 191 tAEMT 3 3 3 NOTE Setup time for the asynchronous inputs IPL2 IPL0 and AVEC guarantees their recognition at the next falling edge of the clock IRQ INPUT 491 Figure 7 17 Interrupts Timing Diagram MC68PM302 REFERENCE MANUAL For More information On This Product o to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 13 IMP AC Electrical Speci
274. of the features are taken from the MC68302 without change fea tures that have been added or changed are highlighted in bold text NOTE This section will only present the register descriptions for each block For more information on the operation of each block please refer to the MC68302 Users Manual Items that are new or have changed will be described in detail The SIB includes the following functions IDMA Controller with Three Handshake Signals DREQ DACK and DONE Interrupt Controller with Two Modes of Operation More Parallel Input Output I O Ports Some with Interrupt Capability Pullup Resistors on Parallel Input and PCMCIA Input Pins On Chip 1152 Byte Dual Port RAM Four Timers Including a Watchdog Timer and Periodic Interrupt Timer Four Programmable Chip Select Lines with Wait State Generator Logic Glueless Interface to SRAM EPROM Flash EPROM and EEPROM System Control System Status and Control Logic Disable CPU Logic M68000 Bus Arbitration Logic with Low Interrupt Latency Support Hardware Watchdog for Monitoring Bus Activity DRAM Refresh Controller Programmable Bus Width Boot from SCC 3 1 SYSTEM CONTROL The IMP system control consists of a System Control Register SCR that configures the fol lowing functions System Status and Control Logic MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconducto
275. of the specific mode bits varies according to the protocol selected by the MODE 1 MODEO bits They are described in the relevant sections for each protocol type Each SCM is a 16 bit memory mapped read write register The SCMs are cleared by reset Only the Mode bits have changed functionality For more information on the other bits please refer to the MC68302 Users Manual 15 6 5 4 3 2 1 0 SPECIFIC MODE BITS DIAG1 DIAGO ENR ENT MODE1 MODEO DIAG1 DIAGO Diagnostic Mode 00 Normal operation CTS CD lines under automatic control 01 Loopback mode 10 Automatic echo 11 Software operation CTS CD lines under software control MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc ENR Enable Receiver When ENR is set the receiver is enabled When it is cleared the receiver is disabled and any data in the receive FIFO is lost If ENR is cleared during data reception the receiver aborts the current character ENR may be set or cleared regardless of whether serial clocks are present To restart reception the ENTER HUNT MODE command should be issued before ENR is set again ENT Enable Transmitter When ENT is set the transmitter is enabled when ENT is cleared the transmitter is dis abled If ENT is cleared the transmitter will abort any data transmission clear the transmit data FIFO and shift register and
276. ofile 144 TQFP that is suitable for use in Type II PCMCIA cards The Personal Computer Memory Card International Association PCMCIA has implement ed a set of specifications for small form factor cards These cards were previously specified by a version number of the spec to which they complied After the specification 2 1 these cards were named PC Cards The PCMCIA functionality on the PM302 is compliant with the specification approved in October 1994 In addition the PM302 contains a parallel interface and register set identical to the 16550 UART used in IBM compatible PCs This functionality is available when the PCMCIA mode is enabled and shares pins with the PCMCIA interface The document fully describes all the differences between the PM302 and the regular 68302 Any feature not described in this document will operate as described in the MC68302 User s Manual In addition this document contains the full set of electrical descriptions for the PM302 1 1 BLOCK DIAGRAM The block diagram is shown in Figure 1 1 1 2 FEATURES The features of the PM302 are as follows The items in bold face type show major differ ences from the MC68302 although a complete list of differences is given in section 1 4 on page 4 e On Chip Static 68000 Core Supporting a 16 or 8 Bit M68000 Family System e SIB Including Independent Direct Memory Access IDMA Controller Interrupt Controller with Two Modes of Operation Parallel Input Output
277. oll the transmit BD ready bit every Tx counter time out When the buffer is ready data will be transferred at the maximal rate NOTE In this case the 68000 is transmitting to the PC core 4 4 5 3 16550 COMMAND SET The following commands can be issued to the command register CR 4 4 5 4 16550 TRANSMIT COMMANDS 4 4 5 4 1 STOP TRANSMIT Command After a hardware or software reset and after the channel has been enabled by setting the transmit enable bit in the EMR register the channel will be in the transmit enable mode and will start polling the first buffer in the table every pro grammable number of clocks as programmed by the Tx Divider bits in the EMR The channel STOP TRANSMIT command disables the transmission of characters to the 16550 emulation receive FIFO MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP The 16550 transmitter will transmit a programmable number of break sequences to the 16550 emulation receive FIFO and then stop transmission The number of break sequences which may be zero should be written to the break count register BRKCR before this com mand is issued to the 16550 Controller 4 4 5 4 2 RESTART TRANSMIT Command The channel RESTART TRANSMIT com mand enables the transmission of characters on the 16550 emulation receive FIFO This command is expected by the 16550 controller after disabling the channel
278. ond method is a smart echo or software transmit which is supported with an additional clock and software Automatic echo is enabled by setting the DIAG bits in the SCC mode register SCM to 10 and asserting the CD pin externally on SCC1 and on SCC2 and SCC3 either externally or by leaving the pin as a general purpose input The ENT bit of the SCC should remain cleared The transmitter is not used so this echoing method does not impact performance The smart echo or software transmit requires use of an additional clock and the transmitter so the overall performance could be affected if other SCCs are running This method requires an additional clock for sampling the incoming bit stream since the baud rate gener ator BRG must be used to provide the correct frequency for transmission The user needs to provide the sampling clock that will be used for the autobaud function on the RCLK pin for example a 1 8432 MHz clock for 115 2K The clock that will be used for the SCC trans mission can be provided to the BRG from the system clock or on TIN1 The TIN1 and RCLK1 pins can be tied together externally After the first two characters have been received and character length and parity determined the host programs the DSR to FFFF enables the transmitter by setting ENT and programs the transmit character descriptor overlays CON TROL Character 8 The host is interrupted after each character is transmitted For modem applications with the
279. onflict Enable Bus Clear Mask Freeze Watch Dog Timer Enable Freeze Timer 1 Enable Freeze Timer 2 Enable SAM Synchronous Access Mode HWDEN Hardware Watchdog Enable HWDCN Hardware Watchdog Count 3 1 2 System Status Bits Bits 27 24 of the SCR are used to report events recognized by the system control logic On recognition of an event this logic sets the corresponding bit in the SCR The bits may be read at any time A bit is reset by one and is left unchanged by zero More than one bit may be reset at a time For more information on these bits please refer to the MC68302 Users Manual MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc PA Interrupt Priority Active This bit is set when the M68000 core has an unmasked interrupt request NOTE If BCLM is set an interrupt handler will normally clear IPA at the end of the interrupt routine to allow an alternate bus master to regain the bus however if BCLM is cleared no additional action need be taken in the interrupt handler HWT Hardware Watchdog Timeout This bit is set when the hardware watchdog see 3 8 3 Bus Arbitration Logic reaches the end of its time interval BERR is generated following the watchdog timeout even if this bit is already set WPV Write Protect Violation This bit is set when a bus master attempts to write to a location
280. or an interrupt This pin operates like VPA on the MC68000 but is used for automatic vectoring only AVEC instead of DIACK should be asserted during autovectoring and should be high otherwise PC_A3 BERR PCMCIA Address or Bus Error The PC_A 4 input is driven by the PCMCIA card interface See Section 5 PCMCIA Con troller The Bus Error input signal informs the bus master M68000 core SDMA IDMA or exter nal bus master that there is a problem with the cycle currently being executed The on chip hardware watchdog bus timeout because of no DIACK and the chip select logic address conflict or write protect violation can assert the internal bus error signal to the current bus master If BERR is asserted with the HALT signal a retry cycle is performed MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 6 1 24 IMP Address and Function Codes or PCMCIA Data NOTE These pins take their PCMCIA function if PC_EN 1 PC_D3 PC_D1 C2 FCO0 PC_D7 PC_D4 FC2 FC0 PC_DO Figure 6 20 PCMCIA Data Bus or IMP Address FC PC_D15 PC_D0 FC2 FCO PCMCIA Data Bus or Function Codes In PCMCIA mode this bidirectional Data Bus interfaces to the Card Connector As FC2 FCO these bidirectional signals indicate the state and the cycle type currently be ing executed The information indicated by the function code outputs is valid whenever AS
281. or automatic vectoring only AVEC instead of DIACK should be asserted during autovectoring and should be high otherwise 6 1 11 IMP Bus Interface Signal Summary Table 6 5 and Table 6 5 summarize all bus signals discussed in the previous paragraphs They show the direction of each pin for the following bus masters M68000 core IDMA SDMA includes DRAM refresh PCMCIA Controller and External Each bus master can ac cess either internal dual port RAM and registers or an external device or memory When an external bus master accesses the internal dual port RAM or registers the access may be synchronous or asynchronous When the M68000 core is disabled BR and BG change their direction Table 6 5 Bus Signal Summary Core and External Master M68000 Core Master External Master Access To Access To Internal External Internal External Signal Name Pin Type Memory Memory Memory Memory Space Space Space Space Pe ine Was Ae V0 o o WEH WEL OE O O O O O IAC available only in PGA O O O O O D15 D0 Read 1 0 O I O D15 D0 Write 0 O O l DTACK 1 0 O O ii BR I O Open Drain BG 1 0 O O O O BGACK 1 0 l l HALT I O Open Drain O V O l RESET I O Open Drain VO VO l BERR je p p p TPL2 IPLO l l l l AVEC l TOUT2 O O O O O WEH WEL OE are high impedance when External Master Acquires the Bus with HALT If DTACK is generated automatically internall
282. ost is responsible for determining the end of the incoming message for example a carriage return stopping the autobaud process and reprogramming the SCC to UART mode The autobaud controller returns the nominal START bit length value for the detected baud rate from the lookup table and a pointer to the last character received that was written to the external data buffer The host must be able to handle each character inter rupt in order to determine parity and character length this information may be overwritten when the next character interrupt is presented to the host The host uses the two received characters to determine 1 whether a properly formed at or AT was received and 2 the proper character format character length parity Once this is decided three possible actions can result First the host may decide that the data received was not a proper at or AT and issue the Enter_Baud_Hunt command to cause the autobaud controller to resume the search process Second the host may decide the at or AT is proper and simply continue to receive characters in BISYNC mode Third the M68000 core may decide that the at or AT is proper but a change in character length or parity is required 4 3 9 2 AUTOBAUD CHANNEL TRANSMIT PROCESS The autobaud microcode pack age supports two methods for transmission The first method is automatic echo which is sup ported directly in the SCC hardware and the sec
283. p selects still decodes a 24 bit address This allows a total of 4 MB to be addressed The FC2 0 pins have been eliminated In CPU disabled mode slave mode these sig nals are internally driven to a value of 5 Supervisor Data function code The UDS LDS and R W pins are not available except in slave mode where they re place the WEH WEL and OE pins The new pins WEH WEL and OE are available in enable CPU mode Their functionalities have been defined for glueless interfacing to memory PA12 is now muxed with the MODCLK pin which is associated with the 32 kHz or 4 MHz PLL The MODCLK pin is sampled at reset and then becomes the PA12 pin New VCCsyn GNDsyn and XFC pins have been added in support of the on chip PLL For purposes of emulation support only a special 180 PGA version is supported This version adds back the FC2 0 IAC FRZ and AVEC pins PA7 is sampled during reset to enable Boot from SCC When the PM302 is not used in its PCMCIA mode most of the original 68302 pins are returned to the device However even though the 68302 is also offered in a 144 TQFP it was not possible to make the PM302 exactly pin compatible with the original 68302 Thus the PM302 should not be used as a drop in replacement for the 68302 in a 144 TQFP 2 2 IMP CONFIGURATION CONTROL A number of reserved entries in the external M68000 exception vector table are used as addresses for internal system configuration registers See Table 2 1
284. p select logic when two or more chip select lines are programmed to overlap the same area 1 BERRis asserted by a conflict in the chip select logic when two or more chip select lines are programmed to overlap the same area BCLM Bus Clear Mask 0 The arbiter does not use the M68000 core internal IPEND signal to assert the in ternal and external bus clear signals The arbiter uses the M68000 core internal IPEND signal to assert the internal and external bus clear signals 1 SAM Synchronous Access Mode Valid only in Disable CPU Mode This bit controls how external masters may access the IMP peripheral area This bit is not relevant for applications that do not have external bus masters that access the IMP In ap plications such as disable CPU mode in which the M68000 core is not operating the user should note that SAM may be changed by an external master on the first access of the IMP but that first write access must be asynchronous with three wait states If DIACK is used to terminate bus cycles this change need not influence hardware 0 Asynchronous accesses All accesses to the IMP internal RAM and registers in cluding BAR and SCR by an external master are asynchronous to the IMP clock Read and write accesses are with three wait states and DTACK is asserted by the IMP assuming three wait state accesses This is the default value 1 Synchronous accesses All accesses to the IMP internal RAM and registers in clud
285. r IOMCR in 2 4 4 1 6 IMP Operation Mode Con trol Register IOMCR The IMP PLL and Clock Control Register IPLCR in 2 4 3 3 Phase Locked Loop PLL PIT CLOCK p IMP SYSTEM CLOCK CLKIN 0 25 MHZ Figure 2 3 IMP System Clocks Schematic PLL disabled Figure 2 2 shows the IMP system clocks schematic with the IMP PLL enabled Figure 2 3 shows the IMP system clocks schematic with the IMP PLL disabled The clock generation features of the IMP are discussed in the following paragraphs 2 4 3 2 ON CHIP OSCILLATOR A 32 768 kHz watch crystal provides an inexpensive ref erence but the EXTAL reference crystal frequency can be any frequency from 25 kHz to 6 0 MHz Additionally the system clock frequency can be driven directly into the EXTAL pin In this case the EXTAL frequency should be the exact system frequency desired 0 to Maxi mum operating frequency and the XTAL pin should be left floating Figure 2 4 shows all the external connections required for the on chip oscillator as well as the PLL VCC and GND connections 2 4 3 3 PHASE LOCKED LOOP PLL The IMP PLL s main function is frequency multipli cation The phase locked loop takes the CLKIN frequency and outputs a high frequency source used to derive the general system frequency of the IMP The IMP PLL is comprised of a phase detector loop filter voltage controlled oscillator VCO and multiplication block 2 4 3 4 FREQUENCY MULTIPLICATION The IMP PLL c
286. r Inc AS Control During Read Modify Write Cycles Disable CPU M68000 Logic Bus Arbitration Logic with Low Interrupt Latency Support Hardware Watchdog e Low Power Standby Modes e Freeze Control 3 1 1 System Control Register SCR The SCR is a 32 bit register that consists of system status and control bits a bus arbiter con trol bit and hardware watchdog control bits Refer to Figure 3 1 and to the following para graphs for a description of each bit in this register The SCR is a memory mapped read write register The address of this register is fixed at 0F4 in supervisor data space FC 5 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB F4 31 30 2 28 27 5 24 EMEN 0 0 0 PA HWT w ADC F5 2 2 21 20 19 18 17 16 RME ERRE VGE WPVE RMCST EMWS ADCE BCLM F6 15 14 13 12 11 10 9 8 FRZW FRZ2 FRZ1 SAM HWDEN HWDCN2 HWDCNO Figure 3 1 System Control Register Table 3 1 SCR Register Bits Bit Name EMEN External Master Cycle Disabled IPA Interrupt Priority Active HWT Hardware Watchdog Timeout WPV Write Protect Violation Address Decode Conflict Ram Microcode Enable External RISC Request Enable Vector Generation Enable Write Protect Violation Enable Read Modify Write Cycle Special Treatment External Master Wait State Address Decode C
287. r specific parameters described in Table 4 15 Table 4 15 16550 Specific Parameter RAM Address Name Width Description SCC2 Base 9C MAX_IDL Word Maximum IDLE characters SCC2 Base 9E IDLC Word Temporary IDLE counter SCC2 Base A0 BRKCR Word Break count register transmit SCC2 Base A2 res Word SCC2 Base A4 res Word SCC2 Base A6 res Word SCC2 Base A8 BRKEC Word Receive break condition counter SCC2 Base AA res Word SCC2 Base AC res Word SCC2 Base AE RCCR Word Receive control character register SCC2 Base B0 CHARCTER1 Word CONTROL character 1 SCC2 Base B2 CHARCTER2 Word CONTROL character 2 SCC2 Base B4 CHARCTER3 Word CONTROL character 3 SCC2 Base B6 CHARCTER4 Word CONTROL character 4 SCC2 Base B8 CHARCTERS5 Word CONTROL character 5 SCC2 Base BA CHARCTER6 Word CONTROL character 6 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Table 4 15 16550 Specific Parameter RAM Address Name Width Description SCC2 Base BC CHARCTER7 Word CONTROL character 7 SCC2 Base BE CHARCTER8 Word CONTROL character 8 The items above in bold face should be initialized by the user MAX_IDL The 16550 emulation TX FIFO is polled by the RISC controller every programmable amount of time When the Tx FIFO is empty the RISC controller assumes reception of an IDLE character
288. r has become master of the bus If the SDMA steals a cycle from the IDMA the BGACK pin will remain asserted continuously PC Output Enable PC_OE line is an active low input signal used to gate memory read data from the memory card 6 1 23 IMP Bus Control or PCMCIA Pins These pins are muxed and therefore replace other pins described in the previous para graphs The replaced signal is indicated in each description NOTE These pins take their PCMCIA function if PC_EN 1 PC_RDY PC_IREQ RW PC_REG UDS AO PC_CE7 LDS DS PC_AS5 FRZ PC_A4 AVEG PC_A3 BERR tht yyy Figure 6 19 PCMCIA Signals or IMP Bus Control PC_RDY PC_IREQ RW PCMCIA Ready Busy PCMCIA Interrupt Request or 68K Read Write In PCMCIA Mode the Ready Busy RDY BSY function is provided by this signal only when the card and the host are configured for the memory only interface When a host socket and the card inserted into it are both configured for the I O interface this function is provided by the RDY BSY status bit in the card s pin replacement register This signal is available as PCMCIA Interrupt Request PC_IREQ only when the card and the interface are configured for the I O and memory interface The interrupt request is lev el only This pin serves as RDY BSY in memory only cards and as PC_IREQ for I O MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description
289. racter is assembled it is stored into a complete byte Assuming that the characters are ASCII characters with 7 bit codes the 8th bit of the byte will con tain the parity bit If the parity is either even or odd then after receiving an odd character and an even character the 8th bit should be different for the odd and even characters The parity can be determined by the setting of the parity bit for one of the two charac ters If the 8th bit is always a 1 this is the same as a 7 bit character no parity and at least 2 STOP bits or a 7 bit character with force 1 parity If the 8th bit is always a zero then either the character is a 7 bit character with force 0 parity or the character is a 8 bit character with no parity Case 3 This case is the same as 7 bit character with force 0 parity The 8th bit of the byte will always be zero Case 4 This case assumes a 8 bit character with the 8th bit of the character equal toa 0 ASCII character codes define the 8th bit as zero If the parity is either even or odd then after receiving an odd and an even character a framing error FE interrupt should have been generated for one of them the interrupt is generated when the parity bit is zero The user can determine the parity by which character generated a FE interrupt if the odd character did then the parity is odd If a framing error occurs on every char acter then the character is 8 bits with force 0 parity If no framing error occurs tha
290. racters e g XOFF that are not part of the received messages The 16550 uses a table of 16 bit entries to support control character recognition Each entry consists of the control character a valid bit and a reject character bit The control characters table is described in Table 4 16 Table 4 16 16550 Control Character Table 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 RCCR OFFSET 2 E R CHARACTER1 OFFSET 4 E R CHARACTER2 OFFSET 6 OFFSET 10 E R REA CT 0 0 0 CHARACTER8 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc RCCR Received Control Character Register Upon a control character match for which the Reject bit is set the 16550 controller will write the control character into the RCCR and generate a maskable interrupt The core must process the interrupt and read the RCCR before a second control character arrives Failure to do so will result in the 16550 controller overwriting the first control character CHARACTER8 1 T Control Character Values These fields define control characters that should be compared to the incoming character E End of table 0 This entry is valid The lower 8 bits will be checked against the incoming character 1 The entry is not valid This must be the last entry in the control characters table NOTE In tables with 8 control characters this bi
291. ransfer begins the PC can burst transfer data into 68K memory incre menting the lower addresses for each transfer and using the A25 line to select between transmit and receive buffers The CMBAR auto increment feature is also useful in this case if the buffer size needs to be larger than 4 Kbytes By using this method data transfer rates are limited only by the 68000 bus cycle rate or the PC bus transfer rate MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA Controller Freescale Semiconductor Inc 68K Memory Map 2K Window ransmit Data DMA Bloc Common Memory Base Address Register 1 Transmit Data Common Memory Base Address Register 2 Receive Data 2K Window Receive Data DMA Block Figure 5 4 Use of the CMBARs for Fast Mode Transmit and Receive Data Transfers To eliminate paging entirely the PCMCIA controller may be programmed not to drive the high address lines from the base register but rather drive the ABUF pin which has the ap propriate timing to control external address buffers This address buffer control line is con nected to external address buffer circuitry that interfaces the upper PCMCIA address bus lines to the 68000 bus This feature is enabled by setting the ABUF bit in the PCMR register See Figure 5 5 MC68PM302 REFERENCE MANUAL For More Information On This Produc
292. rect read or write accesses Both the PCMCIA interface and the 68000 bus must be set to 16 bit wide for the swapper to be enabled TEn Timer Enable The PCMCIA direct access mechanism has a bus monitor hardware watchdog timer to prevent excessively long cycles or hung state conditions on the PCMCIA interface The timer is activated when a PCMCIA interface cycle begins The WAIT signal is negated and a maskable interrupt is generated when the timer expires before the cycle is terminated 0 The PCMCIA interface bus monitor timer is disabled 1 The PCMCIA interface bus monitor timer is enabled MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller TIEn PCMCIA Watchdog Timer Interrupt Enable This bit when set enables interrupt generation to the PC from the PCMCIA bus monitor timer A PTIE interrupt is generated to the PC when this bit is set and the PCMCIA bus monitor timer expires TPres PCMCIA Watchdog Timer Prescaler The PCMCIA watchdog timer uses this prescaler value The PCMCIA watchdog timer uses the prescaler output clock as an input to its 5 bit down counter 00 Divide by 1 01 Divide by 4 10 Divide by 8 11 Divide by 16 TValue Timer Value The PCMCIA watchdog timer is a 5 bit down counter with the programmable T Value pre set The counter has a programmable prescaler The counter will count the WAIT length and
293. reescale Semiconductor Inc clectrical Characteristics 7 6 17 IMP AC Electrical Specifications PCM Timing There are two sync types Short Frame Sync signals are one clock cycle prior to the data Long Frame Sync signals are N bits that envelope the data N gt 0 see Figure 7 22 and Figure 7 23 16 67 MHz 20 MHz 25 MHz Num Characteristic at 5 0 V at 5 0 V at 5 0 V Unit Min Max Min Max Min Max 300 L1CLK PCM Clock Frequency see Note 1 666 8 0 10 0 MHz 301 L1CLK Width Low 55 45 37 ns 301A L1CLK Width High see Note 4 P 10 P 10 P 10 ns 302 L1SY0 L1SY1 Setup Time to L1CLK Rising Edge 0 0 0 ns 303 L1SY0 L1SY1 Hold Time from L1CLK Falling Edge 40 33 27 ns 304 L1SY0 L1SY1 Width Low 1 1 1 LICLK Time Between Successive Sync Signals Short 305 trae ync Signals 8 8 8 SEK 306 Nee oy Valid after L1CLK Rising Edge see 0 70 0 60 0 47 ae 307 L1TxD to High Impedance from L1CLK Rising Edge 0 50 0 42 0 34 ns 308 L1RxD Setup Time to L1CLK Falling Edge see 20 17 14 ns Note 3 309 Naag S Time from L1CLK Falling Edge see 50 42 34 _ ns NOTES 1 The ratio CLK L1CLK must be greater than 2 5 1 2 L1TxD becomes valid after the L1CLK rising edge or the sync enable whichever is later if long frames are used 3 Specification vali
294. registers write access when one of the PCMCIA registers accessible by the PC is written to 5 1 10 2 Power Down and Wake Up Using the PwrDwn Bit The Rdy Bsy bit is reset to zero busy by the PCMCIA logic if the host writes a one to the PwrDwn bit in the CCSR and will stay in the busy state until the IMP has completed its tran sition to one of the low power STOP modes or can be set back to one by software if it is not desired by the card to enter STOP mode Once the IMP has entered low power mode the Rdy Bsy bit will be set to ready When the host writes a zero to the PwrDwn bit while the IMP is in low power mode the Rdy Bsy bit will again be reset to busy while the IMP wakes up IMP software should set the Rdy Bsy bit to one when it has finished recovering from low power mode Refer to Figure 5 7 for a more detailed description of the transition to and wake up from low power stop mode using the PwrDwn bit 5 1 10 3 PCMCIA Host Interrupts The host can be interrupted by the PCMCIA controller in I O mode through the IREQ pin which is the Rdy Bsy pin in memory only mode The IREQ pin s status is always reflected by the INTR bit in the CCSR for PCMCIA interrupts 1 The PCMCIA controller will set the INTR bit and the IREQ pin in I O mode if the PTIE or BERR bit in the PCHER register is set AND the PTIEn and BERRIE bits in the PCMR register are set respectively 2 The 68000 core can set the INTR bit in the CCSR by setting the SW bit in th
295. rial data The 68000 core receives an interrupt when the PC writes to this register See 16550 Event Register on page 45 for more details The 68000 may read the register bits and emulate the UART functions The PC can write and read the contents of this register The 68000 can only read this reg ister LCR Base 8F2 7 6 5 4 3 2 1 0 DLAB SET BREAK STICK PARITY EVEN PARITY PARITYENABLE ely CHARACTER LENGTH RESET 0 O 0 0 0 0 0 0 Read Write PC Read Only 68000 Bits 0 5 These bits do not affect the 16550 emulation controller The 68000 core may read them and use them in the emulation process The 16550 emulation controller generates the LCR interrupt if enabled when the PC writes these bits NOTE The 16550 emulation logic will write a zero to the bit 8 location when the character length is programmed to 7 bits MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Set Break Break Control Bit When the PC sets this bit to one the 16550 emulation controller will transfer the receive break indication to the 68000 core It is done by incrementing the BRKEC counter closing the receive buffer setting the BR bit if a buffer is currently open and generating the BRK interrupt if enabled In addition the 16550 emulation controller generates the LCR inter rupt if enabled When the PC clears this bit the 16550 emulation
296. riptors of SCC1 to continue receiving additional boot code into external system RAM and re initialize the UART receiver NOTE The first 576 bytes also overlays the exception vector table meaning that exception vectors will not work unless the user carefully maps the code around certain desired vectors and points those vectors into the 576 byte code space In addition the stack pointer must point into the 576 bytes if any exceptions are to be taken within the boot code All 68000 accesses to the dual port RAM are visible externally on the address and data pins so program execution in the 576 byte code space can be monitored After the boot process is completed by the user it is suggested that the user issue the CP Reset command to the CP command register CR before reinitializing the SCCs This will return the CP to its original state and eliminate any possible inconsistencies in the initializa tion process The RISC cannot return to boot mode unless a system reset is executed with the PA7 pin asserted low Toggling of the PA7 pin when the device is not in system reset is allowed and in this mode the PA7 pin can be used in its alternate functions NOTE The user may wish to disable the software watchdog timer Tim er 3 in the initial boot code if a long delay i e more than 10 sec onds can occur between the initial boot download and the rest of the download process MC68PM302 REFERENCE MANUAL For More Information On This Product
297. rrupt to the PC when set to one ELSI Enable Receiver Line Status Interrupt This bit enables the receiver line status interrupt to the PC when set to one EDSSI Enable MODEM Status Interrupt This bit enables the MODEM status interrupt to the PC when set to one Bits 4 to 7 These bits are always 0 4 4 4 1 6 MODEM Control Register MCR MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc MCR PC Access Only 7 6 5 4 3 2 1 0 0 0 0 Loop Out2 Outi RTS DTR RESET 0 O 0 0 0 0 0 0 Read Write PC DTR Data Terminal Ready When this bit is set the DTR status bit in the 16550 status register is forced to 1 When this bit is reset the DTR status bit in the 16550 status register is forced to 0 DTR status change interrupt may be generated See 4 4 5 12 16550 Event Register for more details RTS Request To Send When this bit is set the RTS status bit in the 16550 status register is forced to 1 When this bit is reset the RTS status bit in the 16550 status registers forced to 0 RTS status change interrupt may be generated See 4 4 5 12 16550 Event Register for more details Out 1 When this bit is set the Out 1 status bit in the 16550 status register is forced to 1 When this bit is reset the Out 1 status bit in the 16550 status register is forced to 0 An Out 1 status change interrupt may be generated See 4 4 5 12 16550 Eve
298. rted 1 WAIT will not be asserted The 302 clock rate should be equal or higher than 25 Mhz otherwise the data will not be read or written correctly FRZ Freeze Transmission This bit allows the user to halt the 68000 data transfer into the 16550 emulation receive FIFO Data transfer will continue from the next character in the buffer when this bit is reset to zero 0 Normal operation or resume transmission after FRZ is set 1 The RISC controller completes the current transfer into the 16550 emulation re ceive FIFO and then stops transferring data ENT Enable Transmitter 0 The RISC controller transmission process is disabled 1 The RISC controller transmission process is enabled ENR Enable Receiver 0 The RISC controller reception process is disabled 1 The RISC controller reception process is enabled Tx Divider This 4 bit value is loaded into a 4 bit countdown counter This counter divides BRG2 input clock The 16550 emulation transmit FIFO will request the RISC controller to transfer data into memory when the counter reaches zero and the FIFO is not empty This mechanism will slow down the transfer rate and emulate the PC interrupts rate as if the data transfer MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc was done serially When the FIFO is empty the RISC controller will identify the request as an IDLE
299. rupt pending register IPR indicates which INRQ interrupt sources require interrupt service The interrupt mask register IMR allows the user to prevent any of the INRQ interrupt sources from generating an interrupt request The interrupt in service register ISR provides a capa bility for nesting INRQ interrupt requests 3 5 2 1 Global Interrupt Mode Register GIMR The user normally writes the GIMR soon after a total system reset The GIMR is initially 0000 and is reset only upon a total system reset MOD M7 M6 M ET7 ET6 ETI V75 RESERVED MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com System Integration Block seyeescale Semiconductor Inc MOD Mode 0 Normal operational mode Interrupt request lines are configured as IPL2 IPLO 1 Dedicated operational mode Interrupt request lines are configured as IRQ7 IRQ6 and IRQ1 I V7 Level 7 Interrupt Vector 0 Internal vector 1 External vector IV6 Level 6 Interrupt Vector 0 Internal vector 1 External vector I1Vi Level 1 Interrupt Vector 0 Internal vector 1 External vector ET7 IRQ7 Edge Level Triggered 0 Level triggered An interrupt is made pending when IRQ7 is low 1 Edge triggered An interrupt is made pending when IRQ7 changes from one to zero falling edge ET6 IRQ6 Edge Level Triggered 0 Level triggered An interrupt is made pending
300. s asserted by the MC68PM302 to delay the memory space accesses or I O space accesses PC_STSCHG BR PCMCIA Status Changed replace BVD1 or Bus Grant The Bus Request in Enable CPU Mode input indicates to the on chip bus arbiter that an external device desires to become Bus Master In Slave Mode this signal is an open drain output request from the IDMA SDMA or PCMCIA Controller STSCHG is an optional signal used to alert the system to changes in the ready busy RDY BSY write protect WP or battery voltage BV conditions of the card while the 1 O interface is configured This signal is inactive high when this function is not supported by the card or when the SigChg bit in the card status register is false logic 0 When the SigChg bit is true logic MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 1 this signal is active when the changed bit in the card status register is true logic 1 The changed bit is logical OR of the individual changed bits CBVD1 CBVD2 CWP and CRDBSY in the pin replacement register PC_OE BGACK PCMCIA Output Enable or Bus Grant Acknowledge The BGACK bidirectional signal indicates that some other device besides the M68000 core has become the bus master This signal is an input when an external device or the M68000 core owns the bus This signal is an output when the IDMA SDMA or the PCM CIA Controlle
301. s sn cuaitin terearieinenstia vei asiwitd Siastenmuiaaeaaeds 5 5 Card Information Sur Une eae te nee dhe leh ia celle ee Seale a 5 6 V O DPACC ACCOSSES isnan cid oi ice ee etiam oats 5 7 Common Memory and Direct Access Mode Accesses ccceeeeeeeees 5 8 Protecting Memory and Internal Space from PCMCIA Accesses 5 12 PCMCIA Controller InitialiZation ccccceceeeeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 5 13 PCMCIA to 68000 Bus Access and Monitoring Options 5 13 PEMGIA Ring IMOICAR OM ier niensis Ye ods De dae nace Suswed aa aA 5 15 Wake Up Using the PwrDwn Bit cccccceeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeees 5 16 Wake UP ODNONS santisima aa a A tati lori teabae 5 16 Wake Up on PCMCIA Access in STAND BY Mod ssseeeeeeees 5 17 Power Down and Wake Up Using the PwrDwn Bit eeeeeees 5 17 PCMCIA Host Interrupts 0 cccccceeeceeeeeeeeeeeeeeeeeeeeseneaeeeeeeseeeeeeaeeeees 5 17 The Ready Busy Signal Rdy Bsy ceeeeeeeeeeeeeeeeeeeeseeneeeeeeeeeeees 5 19 NEE IS S E ty ictus cas aden E A E aren eesreranentan 5 19 PCMCIA Pins Supported by the MC68PM302 cceeeeeeeeeeeeeeeees 5 19 PCMCIA Pins Not Supported cccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeees 5 19 Pullup Control Register PUCR ccceeceseecceeeeeeeeeeeeeeeeeeeeeeeensaeeeeees 5 20 Programmer sWViOde lesis s chee int oc i ehh ies Se ha a ulna 5 22 PCMCIA
302. s the system clock The clock for the baud rate generators BRGs bypasses this clock divider The purpose of the clock divider is to allow the user to reduce and restore the operating fre quency of the IMP without losing the IMP s PLL lock Using the clock divider the user can still obtain full IMP operation but at a slower frequency The BRG is not affected by the low power divider circuitry so previous BRG divider settings will not have to be changed when the divide factors are changed When the PLL low power divider bits DFO 3 are programmed to a non zero value the IMP is in SLOW_GO mode The selection and speed of the SLOW_GO mode may be changed at any time with changes occurring immediately MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Configuration Clocking Loy Peesmale Senvueandaeten Inc NOTE The IMP low power clock divider is active only if the IMP PLL is active The low power divider block is controlled in the IOMCR The default state of the low power divider is to divide all clocks by 1 If the low power divider block is not used and the user is concerned that errant software could accidentally write the IOMCR the user may set a write protection bit in IOMCR to pre vent further writes to the register 2 4 3 4 2 IMP PLL and Clock Control Register IPLCR IPLCR is a 16 bit read write reg ister used to control the IMP s PLL multiplication factor and CLKO drive
303. se of the buffer descriptors and protocol parameters in a specific protocol see Section 4 CP Base 67E contains the MC68PM302 revision number MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freasgate senicenducter wid amp tG lt and Internal Memory Map Table 2 5 Parameter RAM Address Width Block Description Base 400 4 Word SCC1 Rx BD 0 Base 408 4 Word SCC1 Rx BD 1 Base 410 4 Word SCC1 Rx BD 2 Base 418 4 Word SCC1 Rx BD 3 Base 420 4 Word SCC1 Rx BD 4 Base 428 4 Word SCC1 Rx BD 5 Base 430 4 Word SCC1 Rx BD 6 Base 438 4 Word SCC1 Rx BD 7 Base 440 4 Word SCC1 Tx BD 0 Base 448 4 Word SCC1 Tx BD 1 Base 450 4 Word SCC1 Tx BD 2 Base 458 4 Word SCC1 Tx BD 3 Base 460 4 Word SCC1 Tx BD 4 Base 468 4 Word SCC1 Tx BD 5 Base 470 4 Word SCC1 Tx BD 6 Base 478 4 Word SCC1 Tx BD 7 Base 480 SCC1 Specific Protocol Parameters Base 4BF SCC1 Base 4C0 Reserved x Not Implemented Base 4FF Base 500 4 Word SCC2 16550 Rx BD 0 Base 508 4 Word SCC2 16550 Rx BD 1 Base 510 4 Word SCC2 16550 Rx BD 2 Base 518 4 Word SCC2 16550 Rx BD 3 Base 520 4 Word SCC2 16550 Rx BD 4 Base 528 4 Word SCC2 16550 Rx BD 5 Base 530 4 Word SCC2 16550 Rx BD 6 Base 538 4 Word SCC2 16550 Rx BD 7 Base 540 4 Word SCC2 16550 Tx BDO Base 548 4 Word SCC2 16550 Tx BD 1 Base 550 4 Word SCC2 16550 Tx BD 2 Base 558 4 Word SCC2 16550 Tx BD3
304. sed to enable the RISC controller reception and transmission processes In addition this register is used to program the counters used for reception to slow down trans missions for timeout in the 16550 emulation Rx FIFO and the Rx buffer descriptor IDLE count EMR Base 8F0 15 14 13 12 11 10 9 8 RES RES NWAIT FRZ ENT ENR TX DIVIDER RESET 0 0 0 0 0 0 0 0 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP 0 7 6 5 4 3 2 1 0 TX DIVIDER RX DIVIDER TSDE RSDE RESET 0 0 0 0 0 0 0 0 Read Write 68000 The 16550 controller uses the SCC2 interrupt event and mask registers and the SCC2 parameter RAM The 16550 controller BRG uses the SCC2 SCON register to set the BRG clock frequency which can be further divided by the two 4 bit counters A divide by two block can be enabled from either the system clock source or the TIN pin depending on where the baud rate clock is supplied NOTE IMP clock to 16550 BRG rate should not exceed a ratio of 3 1 NWAIT PCMCIA No WAIT Cycle The PC accesses the 16550 emulation registers through the PCMCIA interface on I O space These read and write cycles are synchronized with the IMP clock The IMP clock rate affects the synchronization time and the cycle length When using lower rate IMP clocks WAIT should be asserted on the PCMCIA cycle to delay the completion of the cy cle 0 WAIT will be asse
305. served 01 Byte Word 11 Reserved _ oO Il DSIZE Destination Size 00 Reserved 01 Byte 10 Word 11 Reserved BT Burst Transfer 00 IDMA gets up to 75 of the bus bandwidth 01 IDMA gets up to 50 of the bus bandwidth 10 IDMA gets up to 25 of the bus bandwidth 11 IDMA gets up to 12 5 of the bus bandwidth RST Software Reset 0 Normal operation 1 The channel aborts any external pending or running bus cycles and terminates channel operation Setting RST clears all bits in the CSR and CMR STR Start Operation 0 Stop channel clearing this bit will cause the IDMA to stop transferring data at the end of the current operand transfer The IDMA internal state is not altered 1 Start channel setting this bit will allow the IDMA to start or continue if previously stopped transferring data NOTE STR is cleared automatically when the transfer is complete 3 4 1 2 Source Address Pointer Register SAPR 31 a B 0 RESERVED SOURCE ADDRESS POINTER The SAPR is a 32 bit register Note that A23 A20 must be initialized by the user They are driven internally by the IDMA and can be used by the chip selects for address comparison 3 4 1 3 Destination Address Pointer Register DAPR The DAPR is a 32 bit register 31 a B 0 RESERVED DESTINATIONADDRESS POINTER Note that A23 A20 must be initialized by the user They are driven internally by the IDMA and can be used
306. ses the same data structure as that of the UART con troller The first character if matched is stored in the receiver control character register and the external data buffer and the status of that character is reported in the autobaud com mand descriptor After the first character each incoming character is then stored in the buffer pointed to by RxPTR and the status is updated in the autobaud command autobaud descriptor The Tx internal data pointer at offset SCC Base 94 is updated to point to the last character stored in the external data buffer 4 3 9 4 2 Enter_Baud_Hunt Command This command instructs the autobaud controller to begin searching for the baud rate of a user predefined character Prior to issuing the com mand the M68000 prepares the autobaud command descriptor to contain the lookup table size and pointer The Enter_Baud_Hunt uses the GCI command with opcode 10 and the channel number set for the corresponding SCC For example with SCC1 the value written to the command register would be 61 4 3 9 4 3 Autobaud Command Descriptor The autobaud controller uses the receive buffer descriptor number 7 Rx BD7 as an autobaud command descriptor The autobaud command descriptor is used by the M68000 core to transfer command parameters to the autobaud controller and by the autobaud controller to report information concerning the received character MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www
307. ses to internal and external memory are limited to 8 bits Also in 8 bit mode SDMA accesses to external memory are limited to 8 bits but CP accesses to the CP side of the dual port RAM continue to be 16 bits In 8 bit mode external accesses to internal memory are also limited to 8 bits at a time MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description Low 8 bit data bus MC68008 core processor High 16 bit data bus MC68000 core processor NOTE The system bus can be changed dynamically by changing the BSW and BSWEN bits in the PPR register See 3 2 Programma ble Data Bus Size Switch PC_EN TOUT2 PB6 The PCMCIA interface is enabled by connecting the PC_EN pin high during reset with 5ns hold time after negation of RESET and HALT After reset the PC_EN pin becomes TOU T2 PB6 If PC_EN is low during reset the PM302 regains most of the functions of the MC68302 BOOT SDS2 PA7 BRG2 Boot From SCC PA7 and PAS pins are sampled at initialization to determine the boot mode To enable Boot from SCC2 mode PA7 has to be pulled LOW during Reset with 5ns hold time after negation of RESET and HALT If Boot mode is enabled PA5 determines the Clock source to SCC2 This pin has to be valid for 100 clocks after the negation of RESET and HALT The user can pull it HIGH or LOW with an external resistor If Boot mode is not enabled then PA5 is
308. set by writing a one and is left un changed by writing a zero More than one bit may be reset at a time All bits are cleared by reset CCR Card Configuration Register This bit is set when the PC writes to the card configuration option register The 68000 core may monitor writes to this register to detect SRESET and changes to the configuration index field to determine if the host has enabled or disable the I O card This bit can be cleared by writing a one to it CCSR Card Configuration and Status Register This bit is set when the PC writes to the card configuration and status register The 68000 core may monitor writes to this register to detect if the PC has requested to place the card in the power down state by setting the PwrDwn bit This bit can be cleared by writing a one to it PRR Pin Replacement Register This bit is set when the PC writes to the pin replacement register This bit can be cleared by writing a one to it SCR Socket and Copy Register This bit is set when the PC writes to the socket and copy register This bit can be cleared by writing a one to it MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller IOEIR IO Event Indication Register This bit is set when the PC writes to the IO event indication register This bit can be cleared by writing a one to it Resi Reserved1 Register This bit is set when the
309. ss This bit is set when the PC accessing common memory space with A25 1 CMBAR1 is selected When the IMP is in stand by mode the IMP will resume its operation An inter rupt may be generated if the corresponding mask bit is set This bit is cleared by writing one CMSI2 Common Memory Space Access This bit is set when the PC accessing common memory space with A25 0 CMBARZ2 is selected When the IMP is in stand by mode the IMP will resume its operation and an interrupt may be generated if the corresponding mask bit is set This bit is cleared by writ ing one MRW Mode Registers Write This bit is set when the PC writes to one of the PCMCIA mode or base registers in the attribute space When the IMP is in stand by mode the IMP will resume its operation An interrupt may be generated if the corresponding mask bit is set This bit is cleared by writ ing one Bits PCTC and PCDRDY are described in 5 3 11 PCMCIA DMA Support 5 3 6 PCMCIA Access Wake up Mask Register PCAWMR The PCAWMR is an 8 bit memory mapped read write register that has the same bit format as the PCAWER If a bit in the PCAWMR is a one the corresponding interrupt in the PCAW MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller ER will be enabled If the bit is zero the corresponding interrupt in the PCRWMR will be dis abled PCAWMAR is cleared at reset Bits PCTC
310. t Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller MC68PM302 ABUF PC_A25 aye PCA23 PC_A0O PC_A11 PC_AO PC_A25 Figure 5 5 PCMCIA Direct Addressing Using ABUF To summarize common memory accesses can occur using two different modes Normal mode FAST 0 The PCMCIA controller will assert the WAIT signal on the PC MCIA lines and generate a 68000 cycle When the cycle is terminated with DTACK data will be transferred to the PCMCIA data lines and the WAIT signal will be negated The next normal mode cycle can then be initiated Fast mode FAST 1 This mode is used to eliminate the WAIT on the PCMCIA inter face and perform fast direct access transfers The first cycle with arbitration is as de scribed above From the second cycle until the burst is terminated the PCMCIA controller will not assert the WAIT signal on the PCMCIA line The cycle on the 68000 bus will use the memory interface signals WE and OE but not DS The cycle will be ter minated when the PCMCIA cycle is terminated DTACK and BERR are ignored in this mode The PCMCIA controller will release the 68000 bus when the PC does not ac cess the card for a programmable number of clocks NOTE FAST mode accesses are not allowed for PC accesses to the IMP internal space Erratic operation will result MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com PCMCIA
311. t CPU space cycles In CPU space cycles the CPU reads a peripheral device vector number These lines are outputs when the IMP M68000 core SDMA or IDMA is the bus master and are inputs otherwise NOTE When PCMCIA mode is enabled pin PC_EN 1 A23 A20 sig nals are not available to the user Internally they are driven by the current bus master and the CS logic compares those sig nals In this way the address space is comprised of 4 banks of 1Mbyte When an External master has ownership of the bus A23 A20 are internally driven LOW NOTE When PCMCIA mode is disabled PC_D7 PC_D4 become A23 A20 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 6 1 5 IMP Data Bus Pins D15 D0O lt q 115 DO Figure 6 5 Data Bus Pins This 16 bit bidirectional three state bus is the general purpose data path It can transmit and accept data in either word or byte lengths For all 16 bit IMP accesses byte 0 the high order byte of a word is available on D15 D8 conforming to the standard M68000 format When working with an 8 bit bus BUSW is low the data is transferred through the low order byte D7 D0O The high order byte D15 D8 is not used for data transfer but D8 D15 are outputs during write cycles and are not three stated 6 1 6 Bus Control Pins The bus control pins are shown in Figure 6 6 AS lt gt OF RW W
312. t Internal Registers This bit when set will block PCMCIA accesses to internal registers and the internal dual port ram When a PCMCIA access is made to an internal register or memory location while the PIR bit is set the register will not be addressed and the DTACK line will not be asserted This will result in a 68000 bus error and an Interrupt to the PCMCIA if the BER RIE bit is set in the PCMR register BSWEN Bus Width Switch Enable When this bit is toggled from a zero to a one the bus width switch mechanism is enabled From the point this bit is toggled the bus width is determined by the BSW bit of this reg ister If another bus width switch is necessary this bit must be toggled back to zero and then one again This bit is zero following a power up reset Setting this bit enables a hardware state machine that arbitrates the internal bus away from the 302 core changes the BUSW pin internally and then gives the bus back to the 302 core BSW Bus Width This bit determines the bus width after the bus width switch is performed 0 Data Bus width is 8 bits 1 Data Bus width is 16 bits 3 8 2 Disable CPU Logic M68000 The IMP can be configured to operate solely as a peripheral to an external processor In this mode the on chip M68000 CPU should be disabled by strapping DISCPU high during sys tem reset RESET and HALT asserted simultaneously The internal accesses to the IMP peripherals and memory may be asynchronous or synchro
313. t is always 0 R Reject character 0 The character is not rejected but written into the receive buffer The buffer is then closed and a new receive buffer is used if there is more data in the message A maskable I bit in the receive BD interrupt is generated 1 If this character is recognized it will not be written to the receive buffer Instead it is written to the received control characters register RCCR and a maskable inter rupt is generated The current buffer is not closed when a control character is re ceived with R set 4 4 5 6 1 Transmission of Out of Sequence Characters Transmitter Transmission of out of sequence characters to the PC is also supported by the 16550 controller and is nor mally used for the transmission of flow control characters such as XON or XOFF This is per formed using the last eight entry in the control characters table The 16550 controller will poll this character whenever the transmitter is enabled for 16550 controller operation This includes during buffer transmission and when no buffer is ready for transmission The char acter is transmitted at a higher priority than the other characters in the transmit buffer if any but does not preempt characters already in the 16550 receiver emulation FIFO MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP E Empty Must be one to use this entry as
314. t is set to one to enable audio information on BVD2 pin while the card is configured MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller PwrDwn This bit is set to one to request the card enter a powerdown state The 68000 core will receive an interrupt if enabled when this register is written see 5 3 4 PCMCIA Configu ration Registers Write Mask Register PCRWMR and should check the state of this bit to determine if the PC has placed the card into power down mode If it has the 68000 should place the card into power down mode When this bit is reset while the IMP is in any of the three STOP modes the 68000 core will be waked up the PC can access the con figuration registers while in powerdown mode Intr This bit represents the state of the interrupt request This value is available whether or not interrupts have been configured This signal should remain true until the condition which caused the interrupt request has been serviced See 5 1 10 8 PCMCIA Host Interrupts for more information on the functionality of this bit 5 3 10 3 Pin Replacement Register Organization PRR PRR PCMCIA Address A25 1 4 68000 Address BAR 872 7 6 5 4 3 2 1 0 CBVD1 CBVD2 CRdy Bsy CWProt RBVD1 RBVD2 RRdy Bsy RWProt Read Write The 68000 core will receive an interrupt when this register is written by the PC See 5 3 5 PCMCIA Access Wake Up Event Regist
315. ta strobe UDS When using an 8 bit data bus this pin functions as AO When used as AO i e the BUSW pin is low the pin takes on the timing of the other ad dress pins as opposed to the strobe timing This line is an output when the PM302 is the bus master and is an input otherwise NOTE This pin is high impedance when External Master acquires the Bus with HALT WEL LDS DS Write Enable Low Lower Data Strobe Data Strobe This pin functions as LDS in Slave Mode and PCMCIA Enable DISCPU 1 and PC_EN 1 In all other cases it functions as WEL WEL is active during a write cycle to indicate that an external device should expect data on the D7 D0O of the data bus LDS controls the flow of data on the data bus When using a 16 bit data bus this pin func tions as lower data strobe LDS When using an 8 bit data bus this pin functions as DS This line is an output when the PM302 M68000 core SDMA or IDMA is the bus master and is an input otherwise NOTE This pin is high impedance when External Master acquires the Bus with HALT MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc DTACK Data Transfer Acknowledge This bidirectional signal indicates that the data transfer has been completed DIACK can be generated internally in the chip select logic either for an IMP bus master or for an ex ternal bus master access to an e
316. table The HDLC controller confirms transmission or indicates error conditions using the BDs to inform the M68000 core that the buffers have been serviced The Tx BD is shown in Figure 4 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 R xX Ww L TC UN CT OFFSET 2 DATA LENGTH OFFSET 4 TXBUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 5 HDLC Transmit Buffer Descriptor MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 3 10 5 HDLC EVENT REGISTER The SCC event register SCCE is called the HDLC event register when the SCC is operating as an HDLC controller It is an 8 bit register used to report events recognized by the HDLC channel and to generate interrupts Upon recog nition of an event the HDLC controller sets its corresponding bit in the HDLC event register Interrupts generated by this register may be masked in the HDLC mask register This register is cleared at reset 7 6 5 4 3 2 1 0 4 3 10 6 HDLC MASK REGISTER The SCC mask register SCCM is referred to as the HDLC mask register when the SCC is operating as an HDLC controller It is an 8 bit read write register that has the same bit formats as the HDLC event register If a bit in the HDLC mask register is a one the corresponding interrupt in the event register will be enabled If the
317. ten with zero 15 14 13 12 11 10 9 8 7 6 5 0 _ EXSYN NTSYN REVD COMMON SCC MODE BITS 4 3 12 3 TRANSPARENT RECEIVE BUFFER DESCRIPTOR RXBD The CP reports information about the received data for each buffer using BD The RxBD is shown in Figure 4 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 E X Ww ov cD OFFSET 2 DATA LENGTH OFFSET 4 RXBUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 8 Transparent Receive Buffer Descriptor MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP 4 3 12 4 TRANSPARENT TRANSMIT BUFFER DESCRIPTOR TX BD Data is pre sented to the CP for transmission on an SCC channel by arranging it in buffers referenced by the channel s Tx BD table The Tx BD is shown in Figure 4 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wema HE a TL OFFSET 2 OFFSET 4 TXBUFFER POINTER 24 bits used upper 8 bits must be 0 OFFSET 6 Figure 4 9 Transparent Transmit Buffer Descriptor 4 3 12 5 TRANSPARENT EVENT REGISTER The SCC event register SCCE is referred to as the transparent event register when the SCC is programmed as a transparent control ler Itis an 8 bit register used to report events recognized by the transparent channel and to generate interrupts On recognit
318. ter BRKEC and issues the break BRK event in the 16550 event register which can generate an interrupt if enabled If the 16550 controller was currently in the process of receiving characters when the BREAK was received it will also close the receive buffer and set the BR bit in the Rx BD and write the RX bit in the event register which can generate an interrupt if enabled A long break sequence only increments the counter once Error Counter BRKEC Break Error Counter 4 4 5 10 16550 RX BUFFER DESCRIPTOR RX BD The CP reports information con cerning the received data on a per buffer basis via buffer descriptors The CP closes the cur rent buffer generates a maskable interrupt and starts to receive data to the next buffer due to these events 1 Reception of a user defined control character when the Reject bit 0 in the control character table entry 2 Detection of the receive buffer being full 3 Reception of a MAX_IDL number of consecutive IDLE characters 4 Issuing the ENTER HUNT MODE command The first word of the Rx BD contains control and status bits Its format is detailed below 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 OFFSET 0 E X w l C KeS D BR OFFSET 2 DATA LENGTH OFFSET 4 RXDATABUFFER POINTER OFFSET 6 E Empty 0 The data buffer associated with this BD has been filled with received data or data reception has been aborted due
319. th Negated teu 15 1 5 15 ciks 40 BGACK Asserted to Address Valid tGaLav 15 15 15 ns 41 BGACK Asserted to AS Asserted teatasa 30 30 20 ns 44 AS DS Negated to AVEC Negated tsHvPH 0 50 0 42 0 33 ns 46 BGACK Width Low tea 1 5 1 5 1 5 clks 47 TOE Input Setup Time see Note tas 10 10 as 7 ns BERR Asserted to DTACK Asserted see 48 Notes 2 and 3 teeLoaL 10 10 7 aa ie 53 Data Out Hold from Clock High tcHDoI 0 0 0 ns 55 Eaa ce to Data Bus Impedance tainan 0 0 0 ns 56 HALT RESET Pulse Width see Note 4 tHRPW 10 10 10 clks 57 BGACK Negated to AS DS RW Driven teasp 1 5 1 5 1 5 cks 57A BGACK Negated to FC tGaAFD 1 1 1 clks 58 BR Negated to AS DS R W Driven see thus 15 15 sl aks Note 7 58A BR Negated to FC see Note 7 tRHFD 1 1 1 cls NOTES 1 For loading capacitance of less than or equal to 50 pF subtract 4 ns from the value given in the maximum columns 2 Actual value depends on clock period since signals are driven latched on different CLKO edges To calculate the actual spec for other clock frequencies the user may derive the formula for each specification First derive the margin factor as M N P 2 Sa where N is the number of one half CLKO periods between the two events as derived from the timing diagram P is the rated clock per
320. that has RW set to zero read only in its associated base register BR3 BRO ADC Address Decode Conflict This bit is set when a conflict has occurred in the chip select logic because two or more chip select lines attempt assertion in the same bus cycle 3 1 3 System Control Bits The system control logic uses seven control bits in the SCR EMEN External Master Cycle Using Halt Enable 0 External master cycles using the HALT Arbitration are disabled 1 External master cycles using the HALT Arbitration are enabled After system reset this bit defaults to zero This bit is used to enable the bus arbitration using HALT when the CPU is enabled and the PCMCIA interface is enabled WPVE Write Protect Violation Enable 0 BERR is not asserted when a write protect violation occurs 1 BERR is asserted when a write protect violation occurs RMCST RMC Cycle Special Treatment 0 The locked read modify write cycles of the TAS instruction will be identical to the M68000 AS and CS will be asserted during the entire cycle The arbiter will issue BG regardless of the internal M68000 core RMC If an IMP chip select is used the DTACK generator will insert wait states on the read cycle only 1 The IMP uses the internal RMC to negate AS and CS at the end of the read portion of the RMC cycle and reasserts AS and CS at the beginning of the write portion BG will not be asserted until the end of the write portion If an IMP chip sele
321. the CKCR register before switching the TCLK1 and RCLK1 lines On SCC2 and SCC3 contention may be avoided by disabling the clock line outputs in the PACNT register In PCM mode L1SY1 L1SY0 are encoded signals used to create channels that can be in dependently routed to the SCCs Table 6 10 PCM Mode Signals L1SY1 L1SY0 Data L1RXD L1TXD is Routed to SCC 0 0 L1TXD is Three Stated L1RXD is Ignored 0 1 CH 1 1 0 CH 2 1 1 CH 3 NOTE CH 1 2 and 3 are connected to the SCCs as determined in the SIMODE register In IDL GCI modes the SDS2 SDS1 outputs may be used to route the B1 and or B2 chan nels to devices that do not support the IDL or GCI buses This is configured in the serial in terface mode SIMODE and serial interface mask SIMASK registers CD1 L1SY1 Carrier Detect Layer 1 Sync This input is used as the NMSI1 carrier detect CD pin in NMSI mode as a PCM sync signal in PCM mode and as an L1SYNC signal in IDL GCI modes If the CD1 pin has changed for more than one receive clock cycle the IMP asserts the appropriate bit in the SCC1 event register If the SCC1 channel is programmed not to sup MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description port CD71 automatically in the SCC1 mode register then this pin may be used as an ex ternal interrupt source The current value of CD71 may be read in the
322. the corresponding bit in the IMR 15 14 13 12 11 10 8 PB11 PB10 SCC1 SDMA IDMA scc2 TIMER1 SCC3 7 PB9 6 TIMER2 5 SCP 4 TIMERS 3 SMC1 2 SMC2 1 PB8 0 3 5 2 4 Interrupt In Service Register ISR Each bit in the 16 bit ISR corresponds to an INRQ interrupt source In a vectored interrupt environment the interrupt controller sets the ISR bit when the vector number corresponding to the INRQ interrupt source is passed to the core during an interrupt acknowledge cycle The user s interrupt service routine should clear this bit during the servicing of the interrupt 15 14 13 PB11 PB10 SCC1 IDMA TIMER1 TIMER2 SMC1 3 6 PARALLEL I O PORTS The IMP supports three general purpose I O ports port A port B and port D whose pins can be general purpose I O pins or dedicated peripheral interface pins Some port B pins are always maintained as four general purpose I O pins each with interrupt capability 3 6 1 Port A Each of the 16 port A pins are independently configured as a general purpose I O pin if the corresponding port A control register PACNT bit is cleared NOTE PA7 0 are only available if the PCMCIA interface is disabled or the PCMCIA data bus is only 8 bits wide PA15 13 are only avail able when the PCMCIA interface is disabled Port A pins ar
323. the cur rent nominal start from the lookup table After the autobaud is successful and the first char acter is matched the user should use the NOM_START value from the autobaud specific parameter RAM to determine which baud rate from the lookup table was detected Also the Tx internal data pointer at offset SCC Base 94 will point to the last character received into external data buffer MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cdJm unications Processor CP NOTE When the channel is operating in the UART mode the NOM_START_ BRKCR is used as the break count register and must be initialized before a STOP_TRANSMIT command is is sued The characters ABCHR1 and ABCHR2 are the autobaud characters that should be searched for by the autobaud controller Typically these are a and A i e 0061 and 0041 if using the Hayes command set These characters must be odd in order for the auto baud controller to correctly determine the length of the START bit Characters are transmit ted and received least significant bit first so the autobaud controller detects the end of the START bit by the least significant bit of the character being a 1 The RxPTR is a 2 word location that contains a 32 bit pointer to a buffer in external memory used for assembling the received characters and must be initialized before the Enter_Baud_Hunt command is issued NOTE
324. the user The address of this register is fixed at 0F2 in supervisor data space BAR cannot be accessed in user data space 15 13 12 11 0 BASEADDRESS 3B 2 aoa 19 18 17 16 15 14 13 12 Bits 15 13 FC2 FC0 The FC2 FC0 field is contained in bits 15 13 of the BAR These bits are used to set the address space of 4K byte block of on chip peripherals The address compare logic uses these bits dependent upon the CFC bit to cause an address match within its address space When the core is enabled the function code bits will be driven by the core to indi cate the type of cycle in process In disable CPU mode the FC pins are not present unless the PCMCIA is disabled they are internally driven to 5 In this situation the user does not have any control over how the FC signals are driven and it is recommended that the user write these bits to zero and write the CFC bit to zero to disable the FC comparison NOTE Do not assign this field to the M68000 core interrupt acknowledge space FC2 FCO 7 CFC Compare Function Code 0 The FC bits in the BAR are ignored Accesses to the IMP 4K byte block occur with out comparing the FC bits 1 The FC bits in the BAR are compared The address space compare logic uses the FC bits to detect address matches Bits 11 O Base Address The high address field is contained in bit 11 0 of the BAR These bits are used to set the starting address of the dual port RAM The address compare logic
325. tics 7 6 10 IMP AC Electrical Specifications Chip Select Timing External Master see Figure 7 15 16 67 MHz at 20 MHz 25 MHz Num Characteristic Symbol 5 0V at 5 0 V at5 0V Unit Min Max Min Max Min Max 154 Clock Low to DTACK Low 1 6 Wait States tctptk 30 25 20 ns 160 AS Low to CS Low tastcsL 30 25 20 ns 161 AS High to CS High tasucsh 30 25 20 ns 162 Address Valid to AS Low tavasL 15 12 10 ns 163 R W Valid to AS Low see Note 1 tawvasL 15 12 10 ns 164 AS Negated to Address Hold Time tasHal 0 0 0 ns 165 AS Low to DTACK Low 0 Wait State tastoTKL 45 40 30 ns 167 AS High to DTACK High tasHotkH 30 25 20 ns 168 AS Low to BERR Low see Note 2 tasLBERL 30 25 20 ns 169 a to BERR High Impedance see isee 30 25 20 na NOTES 1 The minimum value must be met to guarantee write protection operation 2 This specification is not applicable to the 68PM302 BERR_ is only an input pin The BERR_ signal is internally asserted to the CPU if ADCE or WPVE bits in the SCR are set WEH WEL gt lt Gi OUTPUT RAW INPUT DTACK OUTPUT BERR OUTPUT Figure 7 15 External Master Chip Select Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Pr
326. to an error condition The core is free to examine or write to any fields of this Rx BD The CP will not use this BD again while the emp ty bit remains zero 1 The data buffer associated with this BD is empty or reception is currently in progress This Rx BD and its associated receive buffer are owned by the CP Once the E bit is set the 68000 core should not write any fields of this Rx BD X External Buffer 0 The buffer associated with this BD is in internal dual port RAM 1 The buffer associated with this BD is in external memory MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP W Wrap Final BD in Table 0 This is not the last buffer descriptor in the Rx BD table 1 This is the last buffer descriptor in the Rx BD table After this buffer has been used the CP will receive incoming data into the first BD in the table allowing the user to use fewer than eight BDs to conserve internal RAM NOTE The user is required to set the wrap bit in one of the first eight BDs otherwise erratic behavior may occur I Interrupt 0 No interrupt is generated after this buffer has been filled 1 The RX bit in the 16550 event register will be set when this buffer has been com pletely filled by the CP indicating the need for the 68000 core to process the buffer The RX bit can cause an interrupt C Control Character 0 T
327. trol Data transfers are never serialized in the emulation controller MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 4 2 16550 Emulation Controller Overview The 16550 emulation controller has the complete register set of the 16550 with the same FIFO and interrupt structure The data transfer between the PC and the 68000 core consists of parallel transfers of data There is no parallel to serial shift register transformation of the data The 16550 emulation controller transfers modem status written by the PC via hardware reg isters visible to the 68000 core The 68000 core transfers data and modem status bits to the 16550 emulation controller though register visible to both the 68000 core and the PC Data transfers to and from the 16550 FIFO or holding registers are routed to IMP memory using the RISC controller and the SDMA channels Data transfers to and from the PC take place through the PCMCIA interface The 16550 emulation controller uses SCC2 parameter RAM space and its baud rate generator BRG when enable and therefore the SCC2 serial chan nel cannot be used simultaneously with the 16550 emulation The 16550 controller uses the same data structures as a typical IMP SCC in UART mode and supports multi buffer oper ation Two 4 bit counters and a BRG control the data transfer rate of the 16550 emulation control ler the FIFO emu
328. ts wake up routine NOTE The user should reset enable and event bits in the IMP wake up control register IWUCR after it has recovered from STOP mode See 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes 5 1 10 Wake Up Options There are several methods that allow the PC to wake up the IMP The IMP will wake up when 1 2 3 The PC accesses the card and the IMP is in STAND by mode The PwrDwn bit is reset The modem RI PB9 or the PB10 signal is asserted if enabled See 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes The PIT timer is enabled and expires if enabled See 2 4 4 2 3 IMP Wake Up from Low Power STOP Modes The IMP RESET and HALT is asserted MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller 5 1 10 1 Wake Up on PCMCIA Access in STAND BY mode The IMP will wake up on any of five different types of accesses to the PCMCIA interface if it is in the STAND BY low power mode The PCMCIA write event register PCAWER indi cates the type of access that has taken place to wake up the IMP The PCMCIA write event mask registers PCAWMR is used to enable the wake up mechanism for a particular type of PCMCIA access The following accesses can be programmed as described above to wake up the IMP from the STANDY BY mode e I O space access e Attribute space Access e Common memory space access 1 or 2 e Mode
329. tting the changed bit in the card configuration and sta tus register when the RIEvt bit is set When this bit is cleared to a zero this feature is dis abled The state of RIEvt bit is not affected by this bit 5 3 10 6 Reserved Registers The MC68PM302 implements additional 3 card configuration registers Those 8 bits regis ters can be read written by both the 68000 core and the PC They are reserved for future use 5 3 11 PCMCIA DMA Support The PCMCIA Controller supports DMA transfers between the PC Host and PCMCIA Card Compliant with DMA Change Pages PCMCIA document 0035 Release 004 5 3 11 1 PC DMA Operation Description As a preface it useful to clear right away that in the PCMCIA specification on a DMA Read cycle the data flows from the PC Host to the PC Card PC_IOWR_ is asserted on a DMA Write cycle the data flows from the PC Card to the PC Host PC_IORD_ is asserted On the DMA transfers the data between the PC Host and the Card is latched internally in the chip in the 16 bit PCDMAD PC DMA Data Register The Data transfer to the 68k bus can be performed by the 68k CPU Interrupt driven or by the on chip IDMA according to IDOI bit in PCMR register NOTE The PC DMA Logic is not affected by the contents of the COR register MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller 5 3 11 1 1 Interrupt Polling Mode
330. uch as UART HDLC BISYNC Transparent the SMCs and the SCP will not be discussed For more information on any function not dis cussed in this section please refer to the MC68302 User s Manual This section assumes that the user is familiar with the different protocols For more informa tion on a specific protocol implementation please refer to the MC68302 User s Manual MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc 4 2 SERIAL CHANNELS PHYSICAL INTERFACE The serial channels physical interface joins the physical layer serial lines to the three SCCs and the two SMCs The separate three wire SCP interface is described in Serial Commu nication Port SCP on page 48 The IMP supports five different external physical interfaces from the SCCs 1 NMSI Nonmultiplexed Serial Interface 2 PCM Pulse Code Modulation Highway 3 IDL Interchip Digital Link 4 GCl General Circuit Interface 5 UART 16550 physical register set through the PCMCIA interface 4 2 1 Serial Interface Registers There are two serial interface registers SIMODE and SIMASK The SIMODE register is a 16 bit register used to define the serial interface operation modes The SIMASK register is a 16 bit register used to determine which bits are active in the B1 and B2 channels of ISDN For more information on these two registers please refer to the MC68302 Users
331. uctor Inc om 7 NN A NF NS NS A23 Al INPUT AS INPUT IAC OUTPUT wn LDS INPUT RW INPUT 26 Q D15 D0 OUTPUT DTACK OUTPUT e Re Figure 7 10 External Master Internal Synchronous Read Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics CLKO OUTPUT A23 Al INPUT AS INPUT IAC OUTPUT INPU D15 D0 OUTPU DTACK OUTPUT Figure 7 11 External Master Internal Synchronous Read Cycle Timing Diagram One Wait State MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Electrical Characteristics Freescale Semiconductor Inc A23 Al INPUT AS INPUT RW INPUT D0 D15 INPUT DTACK OUTPUT Figure 7 12 External Master Internal Synchronous Write Cycle Timing Diagram MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc clectrical Characteristics 7 6 8 IMP AC Electrical Specifications Iinternal Master Internal Read Write Cycles see Figure 7 13 16 67 MHzat 5 0 V 20 MHz at 5 0 V 25 MHz at 5 0 V Characteristic Symbol
332. upt in the event register will be masked This register is cleared upon reset 4 4 5 14 16550 STATUS REGISTER The 16550 status register is a 16 bit read only regis ter which allows the user to monitor real time status conditions set by the PC MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkn escale Semiconductor Inc 550 Base 8AC 15 14 13 12 11 10 9 8 RES RES RES RES RES RES RES RES RESET 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 RES RES Loop ID OUT2 OUT1 RTS DTR RESET 0 0 0 0 0 0 0 0 Read Write Out2 Out1 Status This bit reflects the current status of the Out2 bit in the 16550 MODEM control emulation register Out1 Out1 Status This bit reflects the current status of the Out1 bit in the 16550 MODEM control emulation register RTS RTS Status This bit reflects the current status of the RTS bit in the 16550 MODEM control emulation register DTR DTR Status This bit reflects the current status of the DTR bit in the 16550 MODEM control emulation register ID Idle Status The ID bit is set when the 16550 emulation FIFO has been empty for at least one full char acter time 0 The line is not currently idle 1 The line is currently idle Loop Loopback Mode This bit reflects the current status of the Loop bit in the 16550 MODEM control emulation register 4 5 SERIAL COMMUNICATION PORT SCP The functionality of the SCP has
333. us When granted the controller gen erates the cycle on the 68000 bus The high address bits and FC are taken from the CIS base address register the low address bits are taken from the PCMCIA address lines When the cycle is terminated with DTACK the 68000 bus will be released data will be transferred to the PCMCIA data lines and the WAIT signal will be negated NOTE The PCMCIA attribute space accesses are only 8 bit The exter nal CIS memory must be at 68000 even addresses only 68000 memory PCMCIA PCMCIA Connector TO 68K PC_A25 0 BUS I F t CISBAR A23 A12 eer hes cis 0 l REG L CISBAR DO D7 PC_DO PC_D7 PC_A11 0 PI PC_A11 PC_AO CISBAR PC_A11 A0 This maps to location zero in attribute space Figure 5 3 CIS Mapped into 68000 Space MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PCMCIA Controller Table 5 4 PCMCIA Controller Registers Access Map PC_CE1 PC_REG PC_OE PC_WE PC_A25 Offset PC_A7 PC_A0 Selected Register or Space L L L H H 00 Configuration Option Register L L H L H 00 Configuration Option Register L L L H H 02 Card Configuration and Status Register L L H L H 02 Card Configuration and Status Register L L L H H 04 Pin Replacement Register L L H L H 04 Pin Replacement Register L L L H H 06 Socket and Cop
334. ved Four address lines have been eliminated giving a total of 20 address lines However the PM302 supports more than a 1 MB addressing range since each of the four chip selects still decodes a 24 bit address This allows a total of 4 MB to be addressed The UDS LDS and R W pins are not available except in slave mode where they re place the WEH WEL and OE pins Instead the new pins WEH WEL and OE have been defined for glueless interfacing to memory PA12 is now muxed with the MODCLK pin which is associated with the 32 kHz or 4 MHz PLL The MODCLK pin is sampled at reset and then becomes the PA12 pin BCLR RMC and BRG1 pins have been eliminated New VCCsyn GNDsyn and XFC pins have been added in support of the on chip PLL MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction e For purposes of emulation support only a special 180 PGA version is supported This version adds back the FC2 0 IAC FRZ and AVEC pins The FC2 0 pins allow bus cy cles to be distinguished between program and data accesses interrupt cycles etc The IAC FRZ and AVEC pins are provided so that emulation vendors can quickly retrofit their existing 68302 emulator designs to support the PM302 When the PM302 is not used in its PCMCIA mode most of the original 68302 pins are re turned to the device However even though the 68302 is also offered in a 144
335. vice will not easily be able to decode an IACK cycle and provide an vector back to the 68PM302 In Disable CPU mode with the PCMCIA interface enabled the IRQ1 IRQ6 and IRQ7 become the BR BGACK and BG signals With the core disabled the MC68PM302 will not be able to decode an external CPU s interrupt acknowledge cycle The user must poll the Interrupt Pending Register IPR during interrupt handling to determine which peripheral caused the interrupt If the PCMCIA interface is disabled then the MC68PM302 can use the function codes to decode the interrupt acknowledge cycle and provide a vector back to the host CPU 3 5 1 1 Interrupt Controller Overview In addition to the MC68302 internal sources the interrupt controller receives interrupts from the PCMCIA Controller and from the Fast Wake Up Ring Oscillator see 2 4 4 3 Fast Wake Up These interrupts are additional sources to IRQ7 IRQ6 and IRQ1 programmable in PCMR DCOR and RINGOCR registers With PCMCIA Interrupts it is possible to work in Normal or Dedicated mode for the three external interrupt requests pins The chip ORs all sources at the same level and asserts the interrupt to the 68000 core Interrupts at the same level 1 6 or 7 are not prioritized 3 5 2 Interrupt Controller Programming Model The user communicates with the interrupt controller using four registers The global interrupt mode register GIMR defines the interrupt controller s operational mode The inter
336. vision Number 2 20 RI ExCA complient 5 16 RI PB9 6 28 Ring Indication 5 3 RINGOCR 2 19 RINGOEVR 2 20 RMC 3 4 Rx BD 4 21 SAM 3 5 3 29 SAPR 3 13 SCC 2 20 Buffer Descriptor 4 4 DSR 4 4 Normal Operation 4 3 SCON 4 2 Software Operation 4 3 TIN1 TIN2 6 26 SCC Mode Register 4 3 SCC Parameter RAM 4 5 SCC Parameter RAM Memory Map 4 5 SCCs 4 2 SCM 4 3 SCON 4 2 SCP 2 20 Serial Communication Port 4 48 SCP Port 6 23 SCR 3 2 4 35 5 34 SCR System Control Register 2 3 SCR Register Bits 3 3 SDMA Serial DMA Controller 6 14 Serial Channels Physical Interface 4 2 Serial Communication 4 48 SMC1 Receive Buffer Descriptor 4 49 SMC1 Transmit Buffer Descriptor 4 50 SMC2 Receive Buffer Descriptor 4 50 SMC2 Transmit Buffer Descriptor 4 50 Serial Communication Controllers 4 2 Serial Communication Port 4 48 7 30 Serial Management Controllers 4 49 Signals AS 3 4 3 25 AS Address Strobe 6 12 BERR 2 3 3 4 3 5 3 6 BG 3 28 6 15 BGACK 6 15 BR 3 28 3 30 6 14 BUSW 2 1 6 6 CD1 6 20 CLKO 6 9 CS 2 3 3 4 CSO 3 26 3 28 6 15 CS3 CS1 6 15 CTS1 6 21 DACK 6 24 DISCPU 3 28 6 7 DONE 3 12 3 14 6 25 DREQ 3 12 6 24 MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Index Freescale Semiconductor Inc DTACK 3 4 3 5 3 26 3 29 6 14 6 17 6 31 EXTAL 6 8 FC2 FCO 6 16 GCI 6 19 HALT 2 3 6 10 IAC 6 16 IACK7 6 25 6 26 IDL 6 19 6 22 IDMA 6 24 ILPO 6
337. when IRQ6 is low 1 Edge triggered An interrupt is made pending when IRQ6 changes from one to zero falling edge ET1 IRQ1 Edge Level Triggered 0 Level triggered An interrupt is made pending when IRQ1 is low 1 Edge triggered An interrupt is made pending when IRQ1 changes from one to zero falling edge V7 V5 Interrupt Vector Bits 7 5 These three bits are concatenated with five bits provided by the interrupt controller which indicate the specific interrupt source to form an 8 bit interrupt vector number If these bits are not written the vector 0F is provided NOTE These three bits should be greater than or equal to 010 in order to put the interrupt vector in the area of the exception vector ta ble for user vectors Bits 11 and 4 0O Reserved for future use 3 5 2 2 Interrupt Pending Register IPR Each bit in the 16 bit IPR corresponds to an INRQ interrupt source When an INRQ interrupt is received the interrupt controller sets the corresponding bit in the IPR MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Gem Integration Block SIB 15 14 13 12 11 10 9 8 PB11 PB10 Scci SDMA IDMA Scc2 TIMER1 SCc3 7 6 5 4 3 2 1 0 TIMER mR ma m Pe ER 3 5 2 3 Interrupt Mask Register IMR Each bit in the 16 bit IMR corresponds to an INRQ interrupt source The user masks an interrupt source by clearing
338. ww freescale com PCMCIA Controller Freescale Semiconductor Inc NOTE Since the PCMCIA attribute space accesses are only 8 bits and AO should be always 0 the CIS memory should be on the 68000 even addresses only NOTE This register is in the PCMCIA attribute space and this 24 bit register address will be 3 bytes on even addresses only V Valid Bit This bit indicates that the contents of the base register is valid The PCMCIA attribute space cycle REG is asserted and A25 0 will not be transferred to the 68000 bus until the V bit is set 0 This CIS base address register is invalid 1 This CIS base address register is valid BA12 23 Base address The base address field should contain the upper address bits of the CIS data structure address on the 68000 bus The lower address bits will be taken from the PCMCIA address lines FC0O 2 Function Code The function code field should contain the function code of the CIS data structure address on the 68000 bus 5 3 9 Common Memory Space Base Address Register CMBAR1 2 CMBAR1 CIMBAR2 PCMCIA Address A25 1 38 40 15 14 68000 Address BAR 8D0 8D4 8 10 9 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 RESET 0 0 0 0 0 0 0 0 PCMCIA Address A25 1 3A 42 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 FC2 FC1 FCO V RESET 0 0 0 0 0 0 0 0 Read Write There are two identical registers to map common
339. xt slower baud rate This process goes on until the autobaud controller recognizes the end of the START bit Then the autobaud controller starts the character assembly process The character assembly process uses the nominal bit length taken from the current lookup table entry to sample each incoming bit in it s center Each bit received is stored to form an 8 bit character When the assembly process is completed a STOP bit is received the char acter is compared against two user defined characters If the received character does not match any of the two user defined characters the auto baud controller re enters the Enter_Baud_Hunt process The host is not notified until a match is encountered If a match is found the character is written to the received control character register RCCR with the corresponding status bit set in Rx BD7 The channel will generate the control char acter received CCR interrupt bit 3 in the SCCE if enabled If the character matched but MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor cJm unications Processor CP a framing error was detected on the STOP bit the autobaud controller will also set the fram ing error status bit in Rx BD7 The autobaud controller then continues to assemble the incoming characters and to store them in the external data buffer The host receives a CCR interrupt after each character is received The h
340. xternal address within the chip select ranges It will also be generated internally during any access to the on chip dual port RAM or internal regis ters If DIACK is generated internally then it is an output It is an input when the IMP ac cesses an external device not within the range of the chip select logic or when programmed to be generated externally 6 1 7 Interrupt Control or Bus Arbitration Pins lt q IPLOIROT BR q IPLTIRO6 BG tp IPL2 IROQ7 BGACK Figure 6 7 Interrupt Control and Bus Arbitration Pins NOTE These pins function as Arbitration only in Slave Mode and PCM CIA DISCPU 1 and PC_EN 1 IPLO IRQ1 BR Bus Request The Bus Request pin is an open drain output request signal from the IDMA and SDMA when the internal M68000 core is disabled As IPL2 IPLO normal mode these input pins indicate the encoded priority level of the external device requesting an interrupt Level 7 is the highest nonmaskable priority while level O indicates that no interrupt is requested The least significant bit is IPLO and the most significant bit is IPL2 These lines must remain stable until the M68000 core sig nals an interrupt acknowledged through FC2 FCO and A19 A16 to ensure that the inter rupt is properly recognized The IRQ1 IRQ6 and IRQ7 dedicated mode inputs indicate to the IMP that an external device is requesting an interrupt Level 7 is the highest level and cannot be masked Level 1 is the lowest level
341. y LSR7 In the NS16450 mode this bit is 0 In the FIFO mode this bit is set when there is at least one parity error framing error or break indication in the FIFO It is cleared when the PC reads the LSR if there are no subsequent errors in the FIFO 4 4 4 1 3 FIFO Control Register FCR Write Only FCR PC Access Only 7 6 5 4 3 2 1 0 RX FIFO TRIGGER RESERVED RESERVED DMA MODE XMITFIFORST RCVRFIFORST FIFO ENABLE RESET 0 O 0 0 0 0 0 0 Write Only PC FIFO Enable 0 Clear all bytes in XMIT and RCVR FIFOs 1 Enables both FIFOs NOTE When changing from FIFO mode to NS16450 mode and vice versa data is automatically cleared from the FIFOs This bit must be one when other FCR bits are written MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Communications Processorkne escale Semiconductor Inc Receiver FIFO Reset When the PC writes a one to this bit all bytes are cleared in the RCVR FIFO and the RCVR FIFO counter is reset The one that is written to this bit is cleared immediately i e it is not latched Transmitter FIFO Reset When the PC writes a one to this bit all bytes in the XMIT FIFO are cleared and the XMIT FIFO counter is reset The one that is written to this bit is cleared immediately i e it is not latched DMA Mode Select This bit is not implemented because the DMA mode is not supported Receiver FIFO trigger These bits are used to set the tr
342. y by the chip select logic then it is an output Otherwise it is an input BERR is input only in 68PM302 an internal BERR may be asserted by the IMP when the hardware watchdog is used or when the chip select logic detects address conflict or write protect violation BERR may be asserted by external logic in all cases MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc 6 1 12 Physical Layer Serial Interface Pins The physical layer serial interface has 23 pins and all of them have multiple functionality The pins can be used in a variety of configurations in ISDN or non ISDN environments Ta ble 6 6 shows the functionality of each group of pins and their internal connection to the three SCC and one SCP controller The physical layer serial interface can be configured for non multiplexed operation NMSI or multiplexed operation that includes IDL GCI and PCM highway modes IDL and GCI are ISDN interfaces When working in one of the multiplexed modes the NMSI1 ISDN physical interface can be connected to all three SCC controllers Table 6 6 Serial Interface Pin Functions First Function Connected To Second Function Connected To NMSI1 8 SCC1 Controller ISDN Interface CC1 SCC2 SCC3 NMSI2 8 SCC2 Controller PlO Port A Parallel I O NMSI3 5 SCC3 Controller PlO Port A Parallel I O NMSI3 3 SCC3 Controller SCP S
343. y Register L L H L H 06 Socket and Copy Register L L L H H 08 Reserved1 for future PCMCIA Definition L L H L H 08 Reserved1 for future PCMCIA Definition L L L H H OA Reserved2 for future PCMCIA Definition L L H L H OA Reserved2 for future PCMCIA Definition L L L H H oC Reserved3 for future PCMCIA Definition L L H L H 0C Reserved for future PCMCIA Definition L L L H H 0E Reserved4 for future PCMCIA Definition L L H L H 0E Reserved4 for future PCMCIA Definition L L L H H 20 PCMCIA Mode Register Read L L H L H 20 PCMCIA Mode Register Write L L L H H 2A PCMCIA Event Register Read L L H L H 2A PCMCIA Event Register Write L L L H H 30 CIS Base Address Register Read L L H L H 30 CIS Base Address Register Write L L L H H 38 Common Mamor Space Base Address Reg L L H L H 38 Common Memory Space Base Address Reg L L L H H 40 Common Merny Space Base Address Reg L L H L H 40 Re on Mamoy Space Base Address Reg 5 1 4 I O Space Accesses The MC68PM302 fully emulates the 16550 UART Section 4 Communications Processor CP The host can transfer data to the card by writing or reading the 16550 FIFO which is mapped into the PCMCIA address space I O accesses are initiated by the assertion of ei ther the PC_IORD or the PC_IOWR signal and the PC_REG signal All I O accesses are connected directly to the 16550 emulation logic registers without using the 68000 bus The 16550 emulation registers addresses are located at addresses 0 throug
344. ynthesizer Ground GNDSYN System Power Supply and Return VCC GND Note Signal Names in Parentheses are only valid when the CPU is Disabled and the PCMCIA is enabled DISCPU PC_EN 1 When the PCMCIA is disabled these signals are available on the PCMCIA pins and these pins retain their primary functionality When the CPU is enabled and the PCMCIA interface is enabled these signals are not available Input buffer has a Schmitt Trigger Pins sampled during RESET and change function after RESET MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Signal Description Freescale Semiconductor Inc Table 6 2 Additional Pins in PGA Package Group Signal Name see Note Mnemonic Internal Access IAC Autovector AVEC Function Codes FC2 0 Freeze Pin for Timers FRZ Note In the PGA package these signals are only available on these additional pins They will not be driven onto any other pins that they are muxed with Input buffer has a Schmitt Trigger MC68PM302 REFERENCE MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Description Table 6 3 IMP Peripheral Pins Group Signal Name Mnemonic See Note 1 0 Receive Data Layer 1 Receive data RXD1 L1RXD l Transmit Data Layer 1 Transm

MC68PM302 Integrated Multiprotocol Processor with PCMCIA

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