AX2010 User Manual
Contents
1. 12 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 6 Universal Asynchronous Receiver Transmitter UART 6 1 Overview UART is a serial port capable of asynchronous transmission The UART can function in full duplex mode Receive data is buffered in a holding register This allows the UART to start reception of a second incoming data byte before software has finished reading the previous data byte When U1SRC 0 Receive pin U1RX P0 6 Transmit pin U1TX P1 6 When U1SRC 1 Receive pin U1RX P3 7 e Transmit pin U1TX P3 5 6 2 Special Function Registers Register 6 1 UARTCON UART Configure Register UARTCON Address 7 6 5 4 3 2 1 0 Default Value UART Configure Register OxFD UTSB UTTX NBIT UTE UTTXI UTRX RXIE 0100 0000 S NB EN N NV INV BANK 0 RW RW RW RAW RAW RW RW RAW UTSBS Stop Bit Select 0 1 bit as Stop Bit 1 2 bits as Stop Bit UTTXNB The ninth bit data of transmitter buffer Write the ninth bit into this location that you want to transmit NBITEN Nine BIT mode Enable Bit 0 Eight bit mode 1 Nine bit mode UTEN UART Enable Bit 0 Disable UART module 1 Enable UART module UTTXINV Transmit Invert Selection Bit 0 Transmitter output without inverted 1 Transmitter output inverted UTRXINV Receive Invert Selection Bit 0 Receiver input without inverted 1 Receiver input inverted2. There is 1 digital input enable register PIE There are several I O MUXed with analog module I O digital input and output must be disabled when Analog Module is enabled Register 4 1 PIE Port Digital Input Enable PIE Address 7 6 5 4 3 2 1 0 Default Value Port Input Enable 9 PIE7 PIE6 PIE3 PIE2 PIE1 PIEO 11 1111 BANK 0 RW RAW RW RW RW RW PIE7 P35 and P37 Digital Input Enable Bit For AMUX 0 P35 and P37 Input Disabled 1 P35 and P37 Input Enabled PIE6 P34 and P36 Digital Input Enable Bit For AMUX 0 P34 and P36 Input Disabled 1 P34 and P36 Input Enabled PIE3 Digital Input Enable Bit For ADC3 0 Input Disabled 1 Input Enabled PIE2 P02 Digital Input Enable Bit For ADC2 0 P02 Input Disabled 1 P02 Input Enabled PIE1 P01 Digital Input Enable Bit For ADC1 0 P01 Input Disabled 1 Input Enabled PIEO POO Digital Input Enable Bit For ADCO or LVD external input 0 POO Input Disabled 1 POO Input Enabled 4 6 Wakeup 4 6 1 Wakeup through External Port0 Wakeup is one way of causing the device to exit the power down mode AX2010 supports Port Wakeup The PWKEN registers Wakeup Enable Register allow P0 4 P0 5 6 and 7 to cause wakeup Clearing bit0 3 the PWKEN register enables wakeup on corresponding pin of P0 4 P0 5 P0 6 and PO 7 The trigger condition on the selected pin can be either risin
3. AX2010 User Manual AX2010 UM 102 EN Rev 1 0 2 January 2012 AppoTech Limited Add Unit 705 707 7 F IC Development Ctr No 6 Science Park West Ave Hong Kong Science Park Shatin N T HK Tel 852 2607 4090 Fax 852 2607 4096 www appotech com High Performance 8 bit MCU DC 48MHz operation Compatible with 8051 104ns internal interrupt response at 48 MIPS All instructions are single cycled except branching instructions Two data pointers for indirect addressing Program Memory and Data Memory 60K Bytes Mask ROM program memory 32K Bytes OTP program memory 34K Bytes internal SRAM used for program and or data memory Flexible I O 28 GPIO pins All GPIO pins are internally pull up selectable CMOS TTL level Schmitt triggered inputs Digital Peripheral Features Two multi function 8 bit timers support Capture and PWM mode Two multi function 16 bit timers support Capture and PWM mode Watchdog Timer with on chip RC oscillator One high speed full duplex UART MP3 decoder WMA decoder SPI AX2010 8 bit CMOS Micro Controller N BEEN AppoTech One EMI controller use for external memory access Full speed USB 2 0 OTG controller Analog Peripheral Features e One 4 24MHz Crystal Oscillator Full speed USB 2 0 OTG PHY PLL DAC ADC Power on reset Two Low Drop Out regulators 5V to 1 8V 5V to 3 3V RC Oscillator Programming and Deb
4. 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 4 FLEXIBLE INPUTS OUTPUTS I O AX2010 provides four ports Port 0 1 2 3 for user to develop applications Inputs are all Schmitt triggered with about 400 500mvV hysteresis level to filter input voltage fluctuations Each port pin can be independently set as input or output Most of the port pins are built in slew rate controlled to reduce output bouncing noise There is also an internally 10KQ pull up resistor selectable for each input port pin 4 1 Data Direction Configuration There are four port data direction registers PODIR P1DIR P2DIR P3DIR All port pins are defined as output when it is set as O and as input when it is set as 1 Table 4 1 illustrates the configuration Table 4 1 PxDIR registers setting Register Address Set bit x of PxDIR as 1 Clear bit x of PxDIR as 0 Initial value PODIR BAh Inputs Outputs FFh P1DIR BBh Inputs Outputs FFh P2DIR BCh Inputs Outputs FFh P3DIR BDh Inputs Outputs FFh 4 2 Port Data Configuration There are four port data registers PO P1 P2 P3 The port data value is stored as 0 when Px register is set to 0 and as 1 when Px register is set to 1 Table 4 2 illustrates the configuration Table 4 2 Px registers setting Register Address Set bit x of Px as 1 Clear bit x of Px as 0 Initial v
5. Registers SFR used by the CPU and Peripheral Modules for controlling the desired operation The Special Function Registers can be classified into two sets core and peripheral Core SFR will be described in this section Peripheral SFR will be described in related peripherals Register 2 1 PSW Processor Status Word PSW Address 7 6 5 4 3 2 1 0 Default Value Processor Status Word OxDO AC F1 RS1 RSO0 OV SBS 0000 0000 BANK 0 RW RAW RAW RAW RW RW RAW RW CY Carry Flag AC Auxiliary carry flag F1 General purpose flag available for user RS1 RSO Register bank select 00 bankO 01 bank1 10 bank2 11 bank3 OV Overflow flag SBS SFR bank select 0 Select SFR bankO 1 Select SFR bank1 P Odd parity check of ACC 0 There are even number of 1 bits in ACC 1 There are odd number of 1 bits in ACC 2011 AppoTech Ltd 5 AX2010 8 bit Microcontroller USER MANUAL 3 INTERRUPT 3 1 Interrupt Sources and Vectors All interrupts with the exception of the ISD are controlled by a series combination of individual enable bits and a global enable EA in the interrupt enable register IENO 7 Setting EA to logic 1 allows individual interrupts to be enabled Setting EA to logic 0 disables all interrupts regardless of the individual interrupt enable settings The interrupt enables and priorities are functionally identical to those of the 80C52 except that the AX2010 sup
6. TXIE Transmit Interrupt Enable 0 Transmit interrupt disable 1 Transmit interrupt enable RXIE Receive Interrupt Enable 0 Receiver interrupt disable 1 Receiver interrupt enable Register 6 2 UARTSTA UART Status Register 2011 AppoTech Ltd 13 AX2010 8 bit Microcontroller USER MANUAL Rev 1 0 2 UARTSTA UART Status Register Address OxFC 7 6 5 4 3 UTRX NB FEF U1R XIF U1TX IF U1SR BANK 0 RW RW RW RW UTRXNB The ninth bit data of receiver buffer FEF Frame Error Flag 0 the stop bit is 1 in the last received frame 1 the stop bit is 0 in the last received frame U1RXIF UART RX Interrupt Flag 0 UART receive not done 1 UART receive done U1TXIF UART TX Interrupt Flag 0 UART transmit not done 1 UART transmit done Writing a data to UTBUF or 0 to U1TXIF to clear this flag U1SRC UART Source Select 0 UART select P0 6 as receive pin P1 6 as transmit pin 1 UART select P3 7 as receive pin P3 5 as transmit pin Default Value xx01 0 Register 6 3 UTBAUD UART Baud Rate Register Register of UART baud rate generator Baud rate formula Baud Rate fsystem clock 8 1 n is 8 bit Register range 0 256 UARTBAUD Address 7 6 5 4 3 2 1 0 UART Baud Rate Register OxFE UARTBAUD BANK 0 RW RAW RAW RAW RAN RAW RW RW Default Value XXXX XXXX Regist
7. 4 15 WDTCON 7 IE1 7 IP1 7 RTCC 0x0073 0x4073 14 15 RTCON 7 IE1 7 IP1 7 UART 0x0073 0x4073 14 15 UTSTA 5 IE1 7 IP1 7 UTSTA 4 IRTCC 0x0073 0x4073 14 15 IRTCON 3 IE1 7 IP1 7 IRTCON 5 Register 3 1 IENO Interrupt Enable 0 Register IENO Address 7 6 4 3 2 1 Default Value Interrupt Enable 0 Register OxA8 EA T2IE TOIE 0000 0000 BANK 0 EA Global Interrupt Enable Bit 0 Disable 1 Enable Timer3 Interrupt Enable Bit 0 Disable RW RW RW RW RW RW RW RW 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 1 Enable T2IE Timer2 Interrupt Enable Bit 0 Disable 1 Enable Timer1 Interrupt Enable Bit 0 Disable 1 Enable TOIE TimerO Interrupt Enable Bit 0 Disable 1 Enable Register 3 2 IEN1 Interrupt Enable 1 Register Address OxA9 IEN1 Interrupt Enable 1 Register BANK 0 UIE LVD UART WDT Interrupt Enable Bit 0 Disable 1 Enable PORTIE Port Wakeup Interrupt Enable Bit 0 Disable 1 Enable 7 6 5 4 3 2 1 0 Default Value UIE PORT 0000 0000 IE R W RW RW RW RW RW RW Register 3 3 IPO Interrupt Priority 0 Register Address OxB8 IPO Interrupt Priority O Register BANK 0 T3IP Timer3 Interrupt Priority Select 0 Low 1 High T2IP Timer2 Interrupt Priority Select 0 Low 1 High T1IP Timer1 Interrupt Priority Select 0 Low 1 H
8. DS 2011 AppoTech Ltd AT AX2010 8 bit Microcontroller USER MANUAL Rev 1 0 2 8 Ordering Code Part No S S S Packing Package H Device Device Option T 7 Tray form DE6 Bare DIE thickness 11mil LQ1 LQFP Lead count 48 QAA OTP Blank AX2010 Ordering Code Brief Description AX2010 QAADE6T Bare Die 11mil AX2010 QAALQ1T LQFP48 Please contact sales office sales appotech com for ordering procedures 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 9 Appendix Revision History Date Version Comment Revised by 2011 08 29 1 0 1 Updated document format Erica Cheong 2012 01 17 1 0 2 Changed new logo Erica Cheong Added ordering code The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice AppoTech assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally AppoTech assumes no responsibility for the functioning of undescribed features or parameters AppoTech reserves the right to make changes without further notice AppoTech makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does AppoTech assume any lia
9. ND1 NDO EN3 EN2 EN1 ENO BANK 0 RW RW RW RW RAN RW RW RW WKPNDx 0 No port0 x wakeup event occurred 1 Port0 x wakeup event occurred PWKENx 0 Enable Port0 x Wakeup 1 Disable Port0 x Wakeup Note 1 Enable Port0 x Wakeup is a condition of Port0 x wakeup events occurred 2 enable WKPNDx set PWKENXx to 0 3 clear WKPNDx write 0 to WKPNDx WKPNDx will be 0 2 clocks later after write 0 to WKPNDx 4 WKPNDx is cleared when PWKENXx is 1 Register 4 3 PWKEDGE Port 0 Wake up Event Select PWKEDGE Address 7 6 5 4 3 2 1 0 Default Value Port 0 Wake up Event Select 0x99 5 WKE WKE WKE WKE XXXX DG2 BANK 0 RW RW RW RW WKEDGx Port Wake up Edge Select 0 select rising edge as wake up event 1 7 select falling edge as wake up event 2011 AppoTech Ltd 11 AX2010 8 bit Microcontroller Rey 1 0 2 USER MANUAL 5 Timers and oscillator 5 1 Watchdog Timer with On chip 32KHz RC oscillator The Watchdog Timer WDT logic consists of a 20bit Watchdog Timer The Watchdog Timer is clocked by internal RC oscillator running at 32KHz When device resets the WDT is disabled and user should enable the WDT if it is needed In the default configuration WDT overflows in 2 ms The application program needs to write a 1 into WDTCON 5 at least once 2 ms to prevent WDT time out The lower 3 bits of the WDTCON register
10. alue PO 80h Stored 1 Stored 0 XX P1 90h Stored 1 Stored 0 XX P2 AOh Stored 1 Stored 0 XX P3 BOh Stored 1 Stored 0 XX 4 3 Pull up Configuration There are four data pull up registers POUP P1UP P2UP P3UP The port pin will be pull up disabled when PxUP register is set to O or the pin is set as output and pull up enabled when it is set to 1 and the pin is set as input Table 4 3 shows the register setting Table 4 3 PxUP register setting Register Address Set as 1 Clear as 0 Initial value POUP BANK 1 BAh Enable pull up Disable pull up 00h P1UP BANK 1 BBh Enable pull up Disable pull up 08h P2UP BANK 1 BCh Enable pull up Disable pull up 00h P3UP BANK 1 BDh Enable pull up Disable pull up 00h 2011 AppoTech Ltd AX2010 8 bit Microcontroller Rey 1 0 2 USER MANUAL 4 4 Pull down Configuration There are 2 data pull down bit SPMODE 0 for P1 7 and SPMODE 1 for pin P3 7 and P0 6 The port pin will be pull down disabled when SPMODE 0 or SPMODE 1 is set to 0 and pull down enabled when it is set to 1 Table 4 4 shows the register setting Table 4 4 SPMODE register setting Bit Address Set as 1 Clear as 0 Initial value SPMODE 0 AEh Enable pull down Disable pull down 1 SPMODE 1 AEh Enable pull down Disable pull down 1 4 5 Digital Input Enable Configuration
11. bility arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages AppoTech products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the AppoTech product could create a situation where personal injury or death may occur Should Buyer purchase or use AppoTech products for any such unintended or unauthorized application Buyer shall indemnify and hold AppoTech harmless against all claims and damages In case of any questions or comments about this documentation please feel free to contact AppoTech at documents appotech com 2011 AppoTech Ltd 19
12. cdssiveeenssctteccssacsnscecedetusansdacceasaaand 9 4 1 Data Direction Configuration sssssssssssssesssssseeeeen 9 42 Pot Data nieto epe e ORELL ERI shea seas bad Eie tesa Ee Rex Pee to aa adt 9 4 3 Mnt rper Pec RR RR PRENDE RT 9 4 4 Pull down 10 4 5 Digital Input Enable Configuration cect ir eee ieee 10 4 6 Wake P deat cates ea tetro e en en Sei oa sl ederet deeds edat pet esa aene eaa deed n 10 4 6 1 Wakeup through External 10 4 6 2 Wakeup R6glstefs cn ee ettet oett e te tuu eter dde tend cd te ite eei as 11 5 Timers and oscillator csestevcicescdexereosedacecdcos sees scans avteveatinceveeceteccsdesesdstdvecvesviexscusvensuseds 12 5 1 Watchdog Timer with On chip 32KHz RC 12 6 Universal Asynchronous Receiver Transmitter UART 13 61 A A 13 6 2 Special Function Registers ettet A wane 13 15 GA WO DG Characteristics e
13. control the selection of overflow time period WDT Registers Register 5 1 WDTCON Watchdog Configure Register WDTCON Address 7 6 5 4 3 2 1 0 Default Value Watchdog Configure Register OxF7 WDTT WDTP CLR WDT RSTE WDTPS 0000 0000 D EN N BANK 0 RW RW WO RW RW RAW RW RAW WDTTO 0 Read 0 after clear Watchdog or Power up 1 Read 1 after Watchdog time out WDTPD 0 read 0 before sleep operation 1 read 1 after sleep operation CLRWDT Write 1 Clear WDT counter Write 0 No action WDTEN 0 Disables the Watchdog timer 1 Enables the Watchdog timer RSTEN 0 Disables the Watchdog reset 1 Enables the Watchdog reset WDTPS WDT time out period setting 000 2ms 001 8ms 010 32ms 011 128ms 100 512ms 101 2048ms 110 8192ms 111 32768ms Watchdog Wake up There are 2 modes for wake up operation wake up without reset and wake up with reset It determines by RSTEN bit WDTCON 3 When RSTEN sets to 0 the watchdog will generate non reset wake up after counter overflows Only in HOLD Mode non reset wake up can wakeup AX2010 and it will continue to execute next instruction AX2010 cannot be waken up by WDT without reset in SLEEP Mode When RSTEN sets to 1 the watchdog will generate a reset wakeup after counter overflows Both in HOLD Mode and SLEEP Mode watchdog reset can wake up the chip and then AX2010 goes back to the initial state
14. er 6 4 UARTDATA UART Data Register UARTDATA Address 7 6 5 4 3 2 1 0 UART Data Register OxFF UARTDATA BANK 0 RAW RAW RAW RAW RAN RAW RW RW Default Value XXXX XXXX Write this location will load the data to transmitter buffer read this location will read the data from the receiver buffer 14 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 7 Characteristics 7 1 DC Characteristics Table 7 1 I O input DC voltage parameters Symbol Descriptions Min Typ Max Units Conditions Vit Low Level Input Voltage 30 VDDIO V VDDIO 3 3V Vin High Level Input Voltage 70 VDDIO V VDDIO 3 3V Low level input voltage V is the threshold voltage read as logic 0 Higher than VIL may not read as 0 For the difference between devices or pins the VIL are different so all the design should refer to the actual criterion High level input voltage Vin is the threshold voltage read as logic 1 Lower than VIH may not read as 1 For the difference between devices or pins the VIH are different so all the design should refer to the actual criterion 2011 AppoTech Ltd AX2010 8 bit Microcontroller USER MANUAL 7 2 MCLR DC Characteristics Table 7 2 MCLR input DC voltage parameters Table 7 2 shows MCLR circuit configuration Capacitance C1 is modified to cha
15. g edge or falling edge The WKED register Wakeup Edge Select selects the desired transition edge Setting a bit in WKED register selects the falling edge of the corresponding P0 4 P0 5 P0 6 and PO 7 pin Resetting the bit selects the rising edge The PWKEN registers are set to OFh upon reset 10 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL Once a valid transition occurs on the selected pin the WKPND PWKEN 7 PWKEN 4 register Wakeup Pending Register latches the transition in the corresponding bit position Logic 1 indicates the occurrence of the selected trigger edge on the corresponding Port pins Upon reset logic O is set to all bits of WKPND Note 1 Port 0 Wakeup initialization To avoid any false signalling to port the followings would be a recommended procedure for Wakeup initialization e Configure the edge select of Port 0 pins on WKEDG register e Clear the corresponding bits WKPND Wakeup Pending Register e Clear the corresponding bits in the PWKEN registers to enable the wakeup on the corresponding port pins 2 Upon exiting the sleep down mode the Multi Input Wakeup logic causes full chip reset 4 6 2 Wakeup Registers Register 4 2 PWKEN Port 0 Wakeup Enable Register PWKEN Address 7 6 5 4 3 2 1 0 Default Value Port 0 Wakeup Enable Register 0x98 WKP WKP WKP WKP PWK PWK PWK PWK 0000 1111 ND3 ND2
16. igh TOIP TimerO Interrupt Priority Select 0 Low 1 High 7 6 5 4 3 2 1 0 Default Value T3IP T2IP T1IP 000 0000 RW RW RW RW RW RW RAW Register 3 4 IP1 Interrupt Priority 1 Register Address 0xB9 IP1 Interrupt Priority 1 Register BANK 0 UIP LVD UART WDT Interrupt Priority Select 0 1 High PORTIP Port Wakeup Interrupt Priority Select 0 1 High 7 6 5 4 3 2 1 0 Default Value UIP POR 0000 0000 TIP RW RW RW RW RW RW RW RAW 2011 AppoTech Ltd AX2010 8 bit Microcontroller Rev 1 0 2 USER MANUAL 3 3 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority decoded each system clock cycle Therefore the fastest possible response time is 4 system clock cycles 1 clock cycle to detect the interrupt and 3 clock cycles to complete the LCALL to the ISR Additional clock cycles will be required if the CPU is executing branch instructions e g ACALL LUMP JZ If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction 8
17. irn t teo METH 15 7 2 MGER DG Characterlstics fedet 16 7 9 DAG CcharacteristiCs itis 16 7 4 Reset 5 e m dotate dtes Mitre 17 8 Ordering Code rere terea ro nere ke Oy crea eS nk ima ona MIR RRAR SER AXE VERE USC 18 Appendix Revision History eo Ene rena aX oy Ra EN RR YR RENE Aaa aU Spa go aa hne 19 2011 AppoTech Ltd 3 AX2010 8 bit Microcontroller Rey 1 0 2 USER MANUAL 1 PIN DEFINITIONS 1 1 Part Numbering AX2010 1 2 Packages LQFP48 1 3 Pin Assignment Figure 1 1 Pin assignment for LQFP48 package VDDCORE VSSCORE 1 36 VDDIO __ 2 35 __ 3 34 vssio Po 4 33 USBDP ___ 5 32 USBDM Pos 6 AX2010 a PH 7 LQFP48 30 __ 12 8 29 ___ P13 DP Po 9 28 4 37 ___ 10 27 MCLR VPP 6 11 26 ___ 16 vssDAC 12 25 __ 17 oo Y DACL DACR VDDDAC VDDIRT IRTOSCI Pa 30 ___ IRTOSCO IRTWKO 4 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 2 MEMORY ORGANIZATION 0x3 fff Ox3 fff CODE XDATA 0x0000 0x0000 2 1 Special Function Registers The Special Function
18. nge circuit s parameter VDDIO 3 3 V MCLR PAD RI 10Kohm ml system 104 Figure 7 1 MCLR circuit configuration Symbol Descriptions Min Typ Max Units Conditions MCLR Low Level Input x _ Voltage 0 2 VDDIO V VDDIO 3 3V MCLR High Level Input _ Voltage 0 8 VDDIO V VDDIO 3 3V Table 7 3 MCLR input AC voltage parameters Symbol Descriptions Min Typ Max Units Conditions TwuciR MCLR Low Level Input width 1 ms VDDIO 3 3V 7 3 DAC characteristics Table 7 4 DAC characteristics Symbol Descriptions Min Typ Max Units Conditions Characteristics SNR 85 db Total Harmonic Distortion Noise 80 db DR Dynamic Range 86 db Power Specifications Analog supply 3 0 3 3 3 6 V Power Supply Current 5 89 mA Sleep Current 51 600 nA 16 2011 AppoTech Ltd Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL 7 4 Reset Characteristics Table 7 5 Reset output AC parameters Symbol Descriptions Min Typ Max Units Conditions Vpor Power On Reset Voltage 1 2 V VDD 3 3V 22 _ V RI 3 3V LVDS 2 05 E V oe 3 3V LVDS _ 1 95 V EX PIN VDDIO 3 3V LVDS 01 18 V iD Lu 3 3V LVDS Vivdr LVD Out Reset Voltage VDDLDO VDDIO 3 3V LVDS 3 3 V 11 VDDLDO VDDIO 3 3V LVDS 3 1 V 10 29 V o ES 3 3V LVDS 27 V 3 3V LV
19. ports 3 levels of interrupt priorities instead of the original 2 3 2 Interrupt Priority Rev 1 0 2 There are 3 levels of interrupt priority Level 2 to 0 The highest interrupt priority is level 2 which is reserved for the ISD interrupts All other interrupts have individual priority bits in the interrupt priority registers to allow each interrupt to be assigned a priority level from 1 to 0 All interrupts also have a natural hierarchy In this manner when a set of interrupts has been assigned the same priority a second hierarchy determines which interrupt is allowed to take precedence The natural hierarchy is determined by analysing potential interrupts in a sequential manner with the order listed in Table 3 1 The processor indicates that an interrupt condition occurred by setting the respective flag bit This bit is set regardless of whether the interrupt is enabled or disabled Table 3 1 Interrupt Summary Interrupt Interrupt Vector Interrupt Natural Order Interrupt Flag Interrupt Enable Bit Priority Sources Number Control Bit Timer 0 0x000B 0x400B 1 2 TMROCON 7 IEO 1 IPO 1 Timer 1 0x0013 0x4013 2 3 TMR1CON 7 IEO 2 2 TMR1CON 6 Timer 2 0x001B 0x401B 3 4 TMR2CON 7 IEO 3 IPO 3 TMR2CON 6 Timer 3 0x0023 0x4023 4 5 TMR3CON 7 IEO 4 4 0 0063 0 4063 12 13 WKPND 1E1 5 IP1 5 LVD 0x0073 0x4073 14 15 LVDCON 7 IE1 7 IP1 7 WDT 0x0073 0x4073 1
20. ugging Support e In System Programming ISP support e In System Debugging ISD support Power Supply LDOVDD is 3 2V to 5 5V VDDIO is 3 0V to 3 6V VDDCORE is 1 6V to 2 0V Packages LQFP48 DIE form Temperature Operating temperature 40 C to 85 C Storage temperature 65 C to 150 C AppoTech Limited Address Unit 705 707 7 F IC Development Centre No 6 Science Park West Ave Hong Kong Science Park Shatin N T Hong Kong Telephone 852 2607 4090 852 2607 4096 www appotech com Rev 1 0 2 AX2010 8 bit Microcontroller USER MANUAL Table of Contents 2 22 4 Ti Part Numberitig siti t ert bee m ben ted ni d eie 4 1 2 4 1 3 Pin ASSIQNMONE D 4 2 MEMORY ORGANIZATION 3 c tinae ek ce onn aa daro cote 5 2 1 Special Function Registers ient tenete AAAA 5 ENE EE EE EE S EE EET T 6 3 1 Interrupt Sources and Vector Sisa aparer 6 3 2 Interrupt Priority cce ttem sette AETH deor s eee ds 6 3 3 Interrupt Latency oers 8 4 FLEXIBLE INPUTS OUTPUTS 1 ccc cisecceiscesteseciccsccsssacuesivetece
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