Home

local copy

1. DH void adjust tare void rts L48 globl _output_data_to_io_buffer data_out gt 0 x output_data_to_io_buffer pshb psha tsx GPIBDEV5 434 adjust_tare is an example of a device specific execute command 94 RV 7 S insert your device specific code here ay GPIB Buffer Routines void output_data_to_io_buffer u_8 data_out GPIBDEV5 448 output_data_to_io_buffer writes data ldab 1 x stab 0 x Because its input is provided by other functions it has no error checking 7 check ranges on variables s assert GPIB state idle state GPIB state reading state GPIB state writing state assert index 0 amp amp index BUFFER SIZE place the data byte on the output buffer x io buffer index data out ldd 4 io buffer pshb psha ldab index clra tsy addd 0 y puly xgdy ldab 0 x stab 0 y GPIBDEV5 449 index index 1 L49 ldab index incb stab index pulx rts 95 to the output buffer globl _parse_input_buffer _parse_input_buffer GPIBDEV5 467 i void parse input buffer parse the message and call the correct routine Also reset the buffer and set the device in idle state If the command just received is invalid send an error messag to the GPIB controller go DH
2. Status Byte management routines x void set status byte bits u 8 srq byte this routine encapsulates writes to the NAT9914 s spmr register It allows the calling routine to set any combination of bits without affecting the others It presents a consistent interface for requesting serial polls Its counterpart is clear status byte bits 4 u 8 srq response byte srq response byte u 8 inp r spsr Srq response byte srq response byte srg byte srg response byte srq response byte amp b_rsv outp r spmr srq response byte use the rsv2 command to request a serial poll instead of the rsv bit The rsv2 command clears itself after the serial poll and mixing rsv2 and rsv can cause undefined behavior zj if srq byte amp b_rsv outp r_auxcr c_rsv2 void clear status byte bits u 8 srq byte this routine encapsulates writes to the NAT9914 s spmr register It allows the calling routine to clear any combination of bits without affecting the others by clearing the bits corresponding to the asserted bits of its input It presents a consistent interface for ceasing to request serial polls Its counterpart is set status byte bits u 8 srq response byte srq response byte u 8 inp r spsr Srq response byte srq response byte amp srg byte 74 srq_response_byte srq_response_byte amp b_rsv outp r spmr srq_respo
3. bsr bits are isr2 define define define define define define define define define define define define define define define define define define bits b_nba b stbo b nl b eos b lloc b atni b cic adr bits define b edpa define b dal define b dat define b rsv define b mav accra bits define b bin define b xeos define b reos accrb bits b iss b inv b lwc b speoi ba accre bi D d D d accrf bi accri bi define b ustd EGE ts hadt hadc tS X hata hala huntl hall ts identical to bcr 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x80 0x40 0x20 spmr spsr bits 0x40 0x10 0x10 0x08 0x04 0x10 0x08 0x04 0x02 0x01 0x08 0x04 0x08 0x04 0x02 0x01 0x08 78 define b_ppl 0x04 define b dmae 0x01 accr icr bits define f_lmhz 0x01 define f 2mhz 0x02 define f 3mhz 0x03 define f 4mhz 0x04 define f 5mhz 0x05 define f 6mhz 0x06 define f 7mhz 0x07 define f 8mhz 0x08 auxcr commands define c nswrst 0x00 define c swrst 0x80 define c nonvalid 0x01 define c valid 0x81 define c rhdf 0x02 define c nhdfa 0x03 define c hdfa 0x83 define c nhdfe 0x04 define c hdfe 0x84 define c nbaf 0x05 define c nfget 0x06 define c fget 0x86 define c nrtl 0x07 define c rtl 0x87 define c feoi 0x08 define c nlon 0x09 define c lon 0x89 define c nto
4. 7 define is file contains tests to determine whether the NAT9914 is connected y It reads and writes to each register except the hidden registers in It is designed to be used unconnected to any other GPIB devices and terfere with them and they may confuse the tests INT_TEST include test h define trigger_logic_analyzer a unsigned char TRIGGER_ADDRESS a define inp io address unsigned char io address define outp io address o data unsigned char io address o data u 8 interrupt pending KS emm KKKKKKKKKK KKK KK KKK TEST TABLES AND SPECIAL TEST ROUTINES KKKKKKKKKKKKKKKK KKK Updated May 28 1997 fully functional KK IK Ck Ck kk kk ek e ke ke ke ke ke e x Simple tests 1 9 CKCKCk kk kk k kk k ke kk ke ke ke e ke x Test 1 check ADSR and ISRO by programming to talk with ton struct WT RD O tst1 ck tauxmr auxcr auxcr auxcr auxcr imr2 imrl imr0 auxcr isr0 isrl adsr auxcr adsr EL 0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 0x8a 0x10 0x00 0x02 0x0a 0x00 return testit tl l j c E r L1 dd t1 sr _testit lra Sx ts area data n reset chip reset chip reset chip page in to imr2 clear GLINT bit and imr2 clear imrl clear imr0 JE ton ET BO bit se
5. ifndef USING INTERRUPTS route nat9914 interrupts endif jwhile 1 Initialization routines x void initialize device void initialization sequences for both the microcontroller and the NAT9914 initialize microcontroller initialize software variables before the device begins accepting GPIB commands be index 0 GPIB state idle state initialize NAT9914 asm cli void initialize_microcontroller initialize the microcontroller these are microcontroller defaults E expanded memory mode set by hardware pins set clock speed A set hardware interrupt to match capabilities of nat9914 bi disable watchdog xy void initialize NAT9914 this routine initializes the NAT9914 and enables the device to receive commands from the GPIB network 66 7 u 8 my gpib address Make sure GPIB chip is in 9914 mode Sch outp r7210 auxmr c7210 sw9914 Reset the NAT9914 Logically remove device from the GPIB ignore GPIB activity until it is initialized ky outp r auxcr Co Ch ns clear the status registers A isr0 byte 0 isrl byte 0 set clock speed ST outp r_accr f icr f 2mhz set T1 delay X outp r auxcr c vstdl enable interrupts x outp r imr0 b bo ie b bi ie outp r imrl b dcas ie b get ie ifndef USING INTERRUPTS outp r auxcr c piimr2 outp r imr2 0x00
6. Dios EOI REN pv 6 18 GND TW PAIR W DAV NRFD 7 19 GND TW PAIR W NRFD NDAC 8 20 GND TW PAIR W NDAC IFC 9 21 GND TW PAIR W IFC SRQ GND TW PAIR W SRQ ATN GND TW PAIR W ATN SHIELD SIGNAL GROUND Figure A 4 GPIB Connector and Pin Assignments 14 Data Lines The eight data lines DIO1 through DIOS carry the command and data messages on the GPIB All commands and most data use the 7 bit ASCII or ISO code set thus the eighth bit DIO8 is not used or is used for parity Interface Management Lines The following lines manage the flow of information across the GPIB e Interface Clear IFC e Attention ATN e Remote Enable REN End or Identify EOI e Service Request SRO Interface Clear IFC Only the System Controller can control the IFC line The System Controller uses IFC to take control of the bus asynchronously This action must initially be done to establish Controller status The IFC line is the master reset of the GPIB When it is asserted all devices return to a known quiescent state Interface Clear IFC a uje Places all devices into quiescent state ws s asserted by System Controller Attention ATN When the ATN line is asserted all devices become Listeners and participate in the communication ATN signifies that a GPIB command message or data message is present on the data lines When ATN is unasserted information on the bus is interpre
7. Figure 4 GPIB FLow Chart NAT9914 Initialization Discussion of Code The microcontroller might need to be configured first The microcontroller locks in many configuration settings after a preset number of cycles The software must initialize the variables and interrupt vectors before the NAT99 14 leaves the pon mode In the pon mode the NAT9914 logically disconnects from the GPIB and will not be affected by any GPIB activity The NAT9914 will become logically connected when the microcontroller sends the pon message to the NAT9914 From this time on the device will handle incoming GPIB signals The initialization of the microcontroller will depend greatly on the microcontroller you use so the rest of this section discusses initialization concerns of the NAT9914 Clock Frequency The NAT9914 uses the clock to generate the required IEEE 488 1 T1 delay between reading bytes A faster clock makes the delays more precise but a 20 MHz clock runs the chip only slightly faster than a 5 MHz clock You should set the clock speed in the ICR register to indicate the external clock speed GPIB Address The microcontroller must send the GPIB address of the device to the NAT9914 during the start up initialization Often the user sets the GPIB address with DIP switches Only 0 through decimal 30 are valid addresses If a user enters 31 a device usually interprets this as address 30 End of Message Condition The four methods
8. gt 298 gt 4 30 HC11 Send Address i Recone bata AAA mes X paa XXX AS gt 153 gt r CE p gt 250 gt gt 220 ODO W 20 NAT9914 lt D 0 7 80 Sen Figure 2 GPIB Read Timing Diagram NAT9914 and M68HC11 CPU Write Timing Diagram lt gt 225 g i E d gt 220 gt M68HC11 i lt 108 gt 33 gt la QU we ess Dat MAA m AS gt 135 gt r i CE lt gt 250 M woe 4 WE WAS AOX Figure 3 GPIB Write Timing Diagram W Parts List Part Description Manufacturer Part Number GPIB interface chip National Instruments NAT9914APD Address decoder Lattice GAL20V8B 15LP GPIB transceivers National Semiconductor DS75160AN DS75162AN GPIB connector AMP 553121 1 2x30 Jumper block Samtec TSW 130 07 S D Microcontroller Motorola M68HC11EVM Designing the Firmware The firmware in the example device uses the following basic flowchart startup output ri output Y i a byte initialize device byte out y S foreground interrupt processing GPIB done clear i interrupt device trigger Vi handler device end of message execute command input a byte last byte of message parse command
9. assert index 0 amp amp index BUFFER SIZE Device Dependent Routines Ki void handle_GET_trigger void This routine performs a device specific trigger action 7 71 regist r stop insert code to implement the device specific trigger action release DAC holdoff to acknowledge to other routines and to the GPIB controller that the device specific trigger action has been completed isrl_byte isrl_byte amp b_get outp r auxcr c nonvalid void read voltage void This routine is an example of a device specific execute query read the device specific data XJ format the device specific data output the data to the output buffer s output data to io buffer 1 output data to io buffer output data to io buffer 2 output data to io buffer V void adjust tare void adjust tare is an example of a device specific execute command Ki X insert your device specific code here Z GPIB Buffer Routines 7 72 void output_data_to_io_buffer u_8 data_out output_data_to_io_buffer writes data to the output buffer Because its input is provided by other functions it has no error checking check ranges on variables eu assert GPIB state idle state GPIB state reading state GPIB state writing state assert index 0 amp amp inde
10. page in to imr2 clear GLINT bit clear imrl clear imr0 page in to bcr register set DAV internal to the NAT9914 read internal DAV signal check ISR1 with ERR flag 0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 t4 switch to 9914 mode reset chip reset chip reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 30 WT auxcr 0x8a set to ton WT cdor 0255 try to output some data RD isrl 0x40 ERRor flag set because no one answered 01 tst4 return testit t4 test 5 check ADR by enabling dat struct ck EST 4 WI tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imrO WT auser 0x8a set to ton WT cdor O55 try to output some data RD cptr 0x55 make sure it is talking correctly WT adr 0x20 disable talk with dat RD cptr 0x00 no talking WT adr 0x00 enable talking for other tests 01 Fett return testit t5 test 6 check SPMR SPSR by writing and checking struct ck t6 WI tauxmr 0x15 switch to 9914 mode WT auxcr
11. 0x80 0x00 Oxle 0x10 0x8a 1 wait for the interrupt asm nop Nn nop Nn nop n nop n trigger_logic_analyzer 0x20 switch to 9 reset chip reset chip reset chip page in to enable BO IE ton 7 check for the interrupt if interrupt_pending 0 interrupt worked trigger_logic_analyzer 0x21 else interrupt failed trigger logic analyzer 0x22 914 mode xy xy IMR2 Ki 34 reset NAT9914 to not interfere with subsequent tests outp imr0 0x00 clear a flag to indicate that the interrupt handler was called successfully xg pragma interrupt handler int handler void int handler signal rest of program that the interrupt has been handled interrupt pending 0 handle the interrupt by writing out some output in this case Oxaa outp cdor 0xaa endif Main program k Set the starting address of the program 4 fpragma abs address 0xF000 void main loop start trigger logic analyzer 0x01 tstl1 tst2 tst tst4 tst5 tst6 tst7 tst8 tst9 tst10 tst11 tst12 trigger logic analyzer 0x10 goto loop start u 8 testit struct ck list of tests u 8 read value 0 u 8 i20 u 8 errorflag 0 while list of tests i gt action 35 if list_of_tests i gt
12. EST 35T714 ESTEC jsr _tst8 EST 3583 A Est90 7 jsr tst9 EST 359451 tst10 jsr _tst10 EST 360 tst11 jsr _tstll EST 361 1 tst12 60 L16 jsr _tst12 362 n trigger logic analyzer 0x10 ldab 16 stab 4369 30352 goto loop start tsx bra 117 globl testit i gt 2 x errorflag gt 3 x read value gt 4 x r list oft tests ae _testit H pshb psha des pshx pshx tsx EST 368 B u 8 testit struct ck list of tests L19 L20 X0 H u 8 read value 0 i 0 errorflag 0 clra clrb stab 4 x clra clro stab 2 x clra clrb stab 3 x BST 3713 while list of tests i gt action ldab 2 x clra lsld lsld addd 5 x xgdy ldab O y clra cpd 40 bne X0 jmp L21 EST 373i if list of tests i gt action RD ldab 2 x 61 clra lsld lsld addd 5 x xgdy ldab O y clra cpd 41 bne 122 EST 23741 read value inp list of tests i gt chip register ldab 2 x clra lsld lsld addd 5 x xgdy ldy 1 y ldab 0 y stab 4 x EST 376 if read value list of tests i gt chip data ldab 2 x clra lsld lsld addd 5 x xgdy ldab 3 y clra pshb psha ldab 4 x clra H H tsy cpd 0 y puly beq 124 ESI 27731 i errorflag 1 ldab 1 stab 3 x L24 L22 EST 383 s if list of tests i gt action WT ldab 2 x
13. Group Execute Trigger and DCAS commands this code initializes the microcontroller and the NAT9914 and then waits state until the NAT9914 sends an interrupt The device interprets th and tares resets executes on the G E T command reads the voltage and into a buffer or outputs the contents of the buffer to the Active GPIB ge handle_GET_trigger and adjust_tare are device specific and as stubs The NAT9914 interrupts the microcontroller for BI BO GET L tatements draw attention to internal errors assert c gt bdevc h rupt handler route nat9914 interrupts define USING INTERRUPTS to input a Sot define inp i define outp nd output on a microcontroller read or write to a memory location o_address unsigned char io_address io_address o_data unsigned char io_address o_data state variable one of the following values idle_state 1 reading_state 2 writing state 3 Zi u 8 GPIB state buffer var index i iables S an offset from the base address of the i o buffer io buffer is both the GPIB input and output buffer 7 u_8 index u_8 io buffer BUFFER SIZE isr0 byte and isrl byte hold data from the NAT9914 status registers which has not yet been proce KY u_8 isr0_byte u_8 isrl_byte ssed 65 void main initialize device do all non GPIB device code goes in this loop
14. clear GLINT bit tendif The device will configure the NEWLINE character to end incoming and outgoing GPIB messages sy outp r auxcr c pieosr r eosr NEWLINE r auxcr c piaccr outp outp outp r accr f accra b xeos b reos set the GPIB address of the device be my gpib address get gpib address outp r adr my gpib address enable the device to receive data and commands from the GPIB network sy outp r auxcr c nswrst 67 u 8 get gpib address void read the GPIB address from DIP switches This device specific function reads the address from a set of DIP switches connected to port D XJ u 8 gpib address gpib address inp PORT D convert the invalid address 31 decimal into 30 if gpib_address 31 gpib_address 30 return gpib_address Handle Interrupt Routines 7 void route nat9914 interrupts void route nat9914 interrupts handles the hardware interrupt from the NAT9914 It determines what caused the interrupt and calls the appropriate function If no interrupts are pending then it does nothing 7 read isr0 and isrl the values must be saved because the act of reading the bits in the registers clears the bits x isr0 byte isr0 byte inp r_isr0 isrl byte isrl byte inp r isrl determine the cause of the interrupt and handle it k if isr
15. clra lsld lsld addd 5 x xgdy 62 H 126 EST L21 EST L28 EST L29 EST ldab 0 y clra cpd 2 bne 126 EST 384 outp list of tests i gt chip register ldab 2 x clra lsld lsld addd 5 x std 0 x xgdy ldy 1 y pshy ldy 0 x ldab 3 y puly stab 0 y 388 list of tests i gt chip data trigger_logic_analyzer 0x02 ldab 2 stab 4369 389 itt ldab 2 x incb stab 2 x jmp L19 392 s end the loop print a message saying it passed the test if lerrorflag trigger logic analyzer 0x04 ldab 3 x clra cpd 0 bne 128 ldab 4 stab 4369 bra 129 393 else trigger logic analyzer 0x08 ldab 8 stab 4369 39551 S return errorflag ldab 3 x clra ins pulx pulx pulx 63 rts L18 area memory abs org 0x0000 globl _interrupt_pending _interrupt_pending blkb 1 org OxFFF2 word int handler org OxFFFE word main 64 Gpibdev5 c gpibdevc c 7 28 97 GPIB DEVIC E implementation for a small microcontroller operating in tandem with a NAT Q t startup nterrupt A in an idle i s tuffs it listener read volta shown here and SDC DC Ef assert s include lt define asser include gpi pragma inter 9914 chip This C code is designed for a microcontroller It implements a PIB voltage query tare
16. i f KK Ek e ke e ke e ke e ke e e e UK IMR tests ck ck ck ck ck ck ck ck Ck ck kk kk ko ko ko ko ko ko kk disable interrupts with GLINT and check them by reading INTO and INT1 IMR2 is implicitly tested since the GLINT d bit is used in both tests test 10 struct ck check IMRO t10 F WT tauxmr 0x15 WT auxcr Oxlc reset chip E WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip E WT auxcr Oxle page in to IMR2 WT imr2 0x00 turn off GLINT WT imrl 0x00 clear imrl WT imrO 0x00 clear imr0 WT imr0 0x10 enable BO IE WT auxcr Ox8a ton RD isr0 0x90 INTO and BO 00 FER KK kk kk kok kk kk kk kk kk kk kk kk AAA kk kk k ck k ck ck ck kk kk kk ke ke e e k switch to 9914 mode imr0 0x00 clear flags for other tests tst10 return testit t10 L10 FEL ldd _t10 jsr _testit clra tsx rts area data globl _t11 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 55 H WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt bl ar rd kb ea 0x1083 128 0x
17. z outp r_imr0 b_bo_ie b_bi_ie ldab 48 stab 4224 GPIBDEV5 137 A outp r_imrl b dcas ie ldab 136 stab 4225 GPIBDEV5 145 ifndef USING INTERRUPTS d outp r auxcr c piimr2 z outp r_imr2 0x00 clear GLINT bit d endif DH configure the NEWLINE i xy outp r auxcr c pieosr ldab 158 stab 4227 GPIBDEV5 146 outp r eosr NEWLINE ldab 10 stab 4226 GPIBDEV5 147 H outp r auxcr c piaccr ldab 159 stab 4227 GPIBDEV5 148 outp r_accr f_accra ldab 140 stab 4226 GPIBDEV5 152 DH 7 get the GPIB address of the device x my gpib address get gpib address 84 b_ character to end incoming and outgoing GPIB messages xeos b reos GP GP jsr get gpib address tsx stab 0 x IBDEV5 153 i outp r adr my gpib address stab 4228 IBDEV5 157 DH enable the device to receive data and commands from the GPIB network Sc outp r auxcr c nswrst clra clrb stab 4227 pulx rts L7 globl get gpib address gpib address gt 0 x get gpib address GP GP L9 GP pshx tsx IBDEV5 170 H u_8 get_gpib_address void read the GPIB address from DIP switches This device specific function reads the address from a set of DIP switches connected to port D y u 8 gpib address gpib address inp PORT D ldab 4104 stab 0 x IBDEV5 174 DH convert the invalid address 31 decimal into 30 S
18. 80 Gpibdev5 s area memory abs org OxFFF2 word route nat9914 interrupts org OxFFFE word main org 0xE000 globl main main GPIBDEV5 56 PA E gpibdevc c 7 28 97 GPIB DEVICE implementation for a small microcontroller operating in tandem with a NAT9914 chip This C code is designed for a microcontroller It implements a GPIB voltage query tare Group Execute Trigger and DCAS commands At startup this code initializes the microcontroller and the NAT9914 and then waits in an idle state until the NAT9914 sends an interrupt The device interprets th interrupt and tares resets xecutes on the G E T command reads the voltage and stuffs it into a buffer or outputs the contents of the buffer to the Active GPIB listener read voltage handle GET trigger and adjust tare are device specific and shown here as stubs The NAT9914 interrupts the microcontroller for BI BO GET and SDC DCL R7 assert statements draw attention to internal errors include lt assert c gt define assert a include gpibdevc h pragma interrupt_handler route_nat9914 interrupts define USING_INTERRUPTS to input and output on a microcontroller read or write to a memory location AY define inp io_address unsigned char io_address define outp io_address o_data unsigned char io_address o_data state variable
19. 94 p H void initialize_microcontroller rts L6 globl initialize NAT9914 my gpib address gt 0 x _initialize NAT9914 pshx tsx GPIBDEV5 114 z initialize the microcontroller S these are microcontroller defaults expanded memory mode set by hardware pins 7 set clock speed set hardware interrupt to match capabilities of nat9914 disable watchdog xy void initialize NAT9914 this routine initializes the NAT9914 and nables th devic to receive commands from the GPIB network p 4 DH S u 8 my gpib address DH Make sure GPIB chip is in 9914 mode i 7 2 outp r7210 auxmr c7210 sw9914 ldab 21 stab 4229 GPIBDEV5 119 i Reset the NAT9914 ignore GPIB activity until it is initialized i 7 s outp r auxcr c ch rst ldab 28 stab 4227 GPIBDEV5 123 83 Logically remove device from the GPIB The device will Ee clear the status registers i S isr0 byte 0 clra clrb stab _isr0O_byte GPIBDEV5 124 isrl byte 0 clra clrb stab isrl byte GPIBDEV5 128 S set clock speed F outp r accr f icr f 2mhz ldab 34 stab 4226 GPIBDEV5 132 P set T1 delay i x 1 outp r auxcr c vstdl ldab 151 stab 4227 GPIBDEV5 136 b get ie E enable interrupts i x
20. When the Controller sends commands it controls DAV and when the Talker sends data messages it controls DAV Figure A 5 illustrates the three wire handshake process The GPIB uses negative logic with standard TTL voltage levels Logic Level Voltage Level 0 false unasserted gt 2 0 V high 1 true asserted 40 8 V low Data 27 X 1 New Data is Valid 3 ne Don t Send More Yet 2 4 Byte 7 Accepted hy F Data Not Valid Anymore 6 Listener Data Transfer Ends Data Transfer Begins Figure A 5 Three Wire Handshake Process Three Wire Handshake Process GPIB devices use the three wire handshake process to transfer information The three wire handshake process is identical for command and data transfers During command transfers the Controller drives the DIO and DAV lines all devices drive the NRFD and NDAC lines During data transfers the Talker drives the DIO and DAV lines all Listeners drive the NRFD and NDAC lines Devices drive the NDAC and NRFD lines with open collector drivers so if any device drives NDAC or NRFD to a low voltage level the signal is logically asserted true If no device drives NDAC or NRFD to a low voltage level the signal floats to a high voltage level thus the signal is logically unasserted false 17 The following actions occur during the three wire handshake process refer to Figure A 5 1 The Talker or Co
21. action RD inp list of tests i gt chip register read value list of tests i gt chip data if read value errorflag 1 if list of tests i gt action WT outp list_of_tests i gt chip_ register list of tests i gt chip data trigger logic analyzer 0x02 itt end the loop print a message saying it passed the test if lerrorflag trigger logic analyzer 0x04 else trigger logic analyzer 0x08 return errorflag 36 Test h d Ad define BASE_ADDRESS 0x1080 define TRIGGER ADDRESS 0x1111 define RD 1 define WT 2 define CLR 0 typedef unsigned char u 8 struct ck u_8 action unsigned chip_register u_8 chip_data u 8 testit struct ck list of tests define i o addresses of the registers on the nat9914 define isr0 BASE ADDRESS define imr0 BASE ADDRESS define isrl BASE ADDRESS 1 define imrl BASE ADDRESS 1 define adsr BASE ADDRESS 2 define imr2 BASE ADDRESS 2 define eosr BASE ADDRESS 2 define bcr BASE ADDRESS 2 define accr BASE ADDRESS 2 define bsr BASE ADDRESS 3 define auxcr BASE ADDRESS 3 define isr2 BASE ADDRESS 4 define adr BASE ADDRESS 4 define spmr BASE ADDRESS 5 define spsr BASE ADDRESS 5 define cptr BASE ADDRESS 6 define ppr BASE ADDRESS 6 define di
22. addressing one Talker automatically unaddresses all others The Unlisten UNL command hex 3F ASCII unaddresses all current Listeners on the bus You cannot unaddress only a single Listener if you have previously addressed several Listeners You must use the UNL command to guarantee that you address only desired Listeners 21 Termination Methods When devices send data over the GPIB they use up to three different methods to signify the end of a data transfer These methods are EOS EOI and the count method Termination methods in GPIB are necessary only for data messages not for command messages EOS Method The EOS method uses an EOS character which signifies the termination of data that devices send on the GPIB This EOS character can be any character However it is commonly a carriage return hex OD or a line feed hex 0A that the Talker places as the last character in a data string The Listener reads individual data bytes from the Talker until the Listener reads the EOS character When the Listener reads the EOS character it knows that there is no more data so it completes the read operation You must configure the Talker and Listener to use the EOS method before the communication takes place Many devices send specific EOS characters and look for specific characters from other devices so it is important for you to read the documentation for all devices to see which termination method the devices use To use the EOS meth
23. an instrument from one vendor with an instrument from another The IEEE 488 1 Specification The GPIB is a digital 8 bit parallel communications interface with maximum data transfer rates over 1 MB s The bus supports one system controller usually a computer and up to 14 additional instruments Because the GPIB is an 8 bit parallel interface with fast data transfer rates it has gained popularity in other applications such as intercomputer communication and peripheral control IEEE 488 2 and SCPI Specifications Although IEEE 488 1 eliminated the need to find the right type of connector and determine which signal line was connected to which pin it did not solve other problems More than 10 years after the release of IEEE 488 1 IEEE 488 2 and SCPI solved these problems Problems with IEEE 488 1 Compatible Devices Users of IEEE 488 1 compatible devices encountered the following problems e No common method for performing operations existed In a system with two different meters one meter could require a command to take a reading while the other could take a reading without a command 11 e Nocommon data format existed among communicating devices Two communicating devices used two different formats to represent the same number e No common command set existed Two devices performed identical functions but used completely different device dependent data messages e Status reporting was unique to each device Each device report
24. any device requests the initiation of a serial poll sequence Overview of Parallel Polls A parallel poll is an exchange of messages between the Controller and other system devices The Controller sends the IDY message true to the other devices each device responds to the IDY message by sending one PPR message PPR1 PPR2 PPR3 PPR4 PPR5 PPR6 PPR7 or PPR8 to the Controller Each device usually sends a different PPR message See the Physical Representation of the PPR Message section in this chapter Each device can send its PPR message either true or false See Figure A 9 PPR1 true Device Controller PPR4 False Device PPR6 true Device Figure A 9 Example Exchange of Messages During a Parallel Poll Determining the Value of the PPR Message Each device examines its local ist message and its Sense bit S to determine whether it will send its PPR message true or false Table A 1 illustrates how the ist message and the Sense bit affect the value of the PPR message Table A 1 PPR Message Value ist Message Sense Bit S PPR Message Sent 0 False 0 True 0 False 1 False 1 True 0 False 1 True 1 True The ist message usually reflects a bit of status information about the device For example when the device has taken a measurement it can assert its local ist message The Sense bit is part of the configuration of a device Each device
25. bit 7 is zero Consider an example in which a Controller at primary GPIB address 0 talks to a device at primary GPIB address 1 To establish the communication link the Controller must send its GPIB talk address and the device s listen address over the GPIB In this example these addresses are as follows Bit Patterns Sent to Set Up Talker Bit pattern 01000000 010 00000 TA ADR Talker s GPIB Address is 0 Hexadecimal value 0100 0000 4 0 Hex 40 ASCII en 20 Refer to the Multiline Interface Command Messages table in Appendix D and find the hex 40 location On the same row under the Msg column you see the message MTAO which means My Talk Address 0 Hex 40 is the command message for setting device 0 to be a Talker Bit Patterns Sent to Set Up Listener Bit pattern 00100001 001 00001 JL ADR Listener s GPIB Address is 1 Hexadecimal value 0010 0001 2 1 Hex 21 ASCII I Refer to the Multiline Interface Command Messages table and find the hex 21 location On the same row under the Msg column you see the message MLAI which means My Listen Address 1 Hex 21 is the command message for setting device to be a Listener Reading the Multiline Interface Command Messages Table By using the Multiline Interface Command Messages table you can understand how the GPIB circuitry interprets the bit patterns to produce the proper message commands The Multiline Interface Command Messages table is organized into four
26. check ranges on variables i 7 assert GPIB state idle state P GPIB_state reading_state A GPIB_state writing_state E assert index gt 0 amp amp index lt BUFFER SIZE DH reset the state variables since the device now has stopped reading GPIB data i 7 F index 0 clra clrb stab _index GPIBDEV5 468 GPIB_state idle_state ldab 1 stab _GPIB state GPIBDEV5 469 isr0 byte isr0 byte amp b end ldab _isr0_ byte andb 247 stab isr0O byte GPIBDEV5 473 H parse the message in the input buffer i 7 E if io buffer 0 V 88 ldab _io buffer clra cpd 86 bne 151 ldab _io buffer i clra cpd 79 bne 151 ldab io buffer 2 clra cpd 76 bne 151 ldab io buffer 3 clra cpd 84 bne 151 ldab _io_buffer 4 clra cpd 63 bne 151 96 GPIBDEV5 478 E io buffer 1 O 88 z io buffer 2 L 88 S io buffer 3 T amp amp io_buffer 4 P read_voltage jsr read voltage GPIBDEV5 483 H RS terminate the data string and request service now that the data is in the buffer i xj A output data to io buffer NEWLINE ldd 10 jsr output data to io buffer GPIBDEV5 484 i set status byte bits b mav b rsv ldd 80 jsr set status byte bits tsx bra 152 L51 GPIBDEV5 487 DH S else if io_buffer 0 T amp amp ldab _io_buffer clra cpd 84 bne 157 ldab _io_buffer l clra cpd 65 bne 1
27. might be willing to sacrifice performance because making measurements may not be a time critical task e Frequency of device access even a moderate GPIB speed will cost the user time in a test operating continually A GPIB device that rarely transmits data can send data slower than one that constantly sends data Choosing a GPIB Interface Chip NAT9914 The NAT9914 can transmit or receive data at several kbytes s to several hundred kbytes s depending on the microcontroller The NAT9914 is relatively easy to program inexpensive and versatile The NAT9914 does need external GPIB transceivers NAT9914 with Supplementary Hardware Read Software Considerations in the NAT9914 Reference Manual for more detailed information on both DMA and FIFOs The NAT9914 can also use Direct Memory Access DMA A DMA controller transfers data directly between the NAT9914 and the memory without intervention by the microcontroller Product and company names are trademarks or trade names of their respective companies 341398A 01 Copyright 1998 National Instruments Corporation All rights reserved January 1998 FIFOs are simpler to interface to the NAT9914 but still increase GPIB transfer speed significantly Using external FIFOs the NAT9914 can transfer more than Mbytes s Both a FIFO and a DMA controller working together with a NAT9914 transfer data even faster However for high performance applications you should choose the TNT4882 which tra
28. needs VR O uest Alerts Controller that service is needed s asserted by Non Controller Handshake Lines Three lines asynchronously control the transfer of message bytes among devices e Not Ready For Data NRFD e Not Data Accepted NDAC e Data Valid DAV 16 The GPIB uses a three wire interlocking handshake scheme This handshake scheme guarantees that message bytes on the data lines are sent and received without transmission error Not Ready For Data NRFD The NRFD line indicates whether a device is ready to receive a data byte When a Controller is sending commands all devices drive NRFD When a Talker is sending data messages only Listeners drive NRFD Not Data Accepted NDAC The NDAC line indicates whether a device has accepted a data byte When a Controller is sending commands all devices drive NRFD When a Talker is sending data messages only Listeners drive NRFD Note This handshake scheme limits the transfer rate on the GPIB to that of the slowest active Listener The transfer rate is limited because a Talker waits until all Listeners are ready that is NRFD is false before sending data and waits for all Listeners to accept data that is NDAC is false before transferring more data Therefore the slowest device dictates the maximum GPIB transfer rate Data Valid DAV The DAV line indicates whether signals on the data lines are stable valid and whether devices can safely accept the signals
29. of terminating a message are e The listener stops listening after a certain number of bytes e The talker asserts the GPIB EOI signal e The talker sends an EOS byte usually a newline character hex OA e The talker sends the EOS with the EOI signal asserted On the NAT9914 the XEOS bit in the ACCRA register configures the NAT9914 to assert EOI whenever the device sends the character in EOSR to another GPIB device The REOS bit of the same register sets the END bit of ISRO if the GPIB device receives an EOS character T1 Delay The T1 delay is the time allowed for GPIB lines to settle before DAV asserts and gives the listening GPIB device enough setup time to ensure reliable data transfer The length of the delay depends on the capabilities of the transceivers GPIB cable length and the number of powered on GPIB devices The stdl stdl vstdl and vstdl commands to the AUXCR register and the USTD bit in the ACCRI register set the IEEE 488 1 T1 delay The NAT9914 automatically shortens the delay after the first byte it sends Internally the NAT9914 uses the clock setting to count out the T1 delay so set the ICR register to indicate the clock speed Holdoff Condition When Listening A GPIB device can refuse to accept a data byte or command byte until the device has processed the previous incoming bytes The device asserts the NDAC or NRFD lines and finishes processing the data before the device unasserts NDAC or NRFD to continue the hand
30. other tests 01 tst10 return testit t10 test 11 check IMR1 struct ck t11 WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to IMR2 WT imr2 0x00 turn off GLINT WT imrl 0x00 clear imrl WT imrO 0x00 clear imrO WT imrl 0x40 enable ERR IE WI auxcr Ox8a ton WT cdor Oxaa fill CDOR RD isr0 0x40 check for interrupt WT imrl 0x00 clear flags for other tests 01 tst11 33 return testit t11 tifdef INT TI EST Interrupt Test test 12 struct ck WT tauxmr 0x15 WT auxcr Oxlc WT auser 0x80 WT auser 0x00 WT auxcr Oxle WT imr2 0x80 WT imrl 0x00 WT imrO 0x00 WT imrO 0x10 WT auxcr Ox8a RD isrO 0x90 044 tst12 u 8 Xs t12 RE switch to 9914 mode reset chip reset chip reset chip page in to IMR2 turn on GLINT clear imrl clear imr0 7 enable BO II ton INTO and BO ESSA SZ set up conditions for an interrupt interrupt_pending asm cli out ou out ou out out tauxmr 0x15 auxcr auxcr auxcr tp tp tp outp auxcr tp tp imr0 tp auxcr Oxlc
31. schematic of the example board that plugs into the M68HC11 evaluation board M68HC11EVM PANDED MULTIPLEXED ADDRESS GPIB CONTROLLER GPIB GPIB CONNECTOR DECODE pee TRANSCEIVERS CONNEC TOR A D 7 0 A D 7 0 ASCLK RW ES SOCKET 10 A D1 12 A D3 14 A D5 NASCLK 1 A 07 A ECLK 2 i 14700 A Di 1 A D2 12 PDZ i D s A D3 13 H K AID les LA 15 5 A D6 16 A A DT Zoe GND SHLD GND SHLD J2 A 15 8 A 5 8 er SSWITCH DRESS SELECTOR Figure 2 Schematic of GPIB Device 4 The GAL decodes the address and expands the multiplexed address data bus of the Motorola 68HC11 so the NAT9914 appears at the M68HC11 memory address 0x1080 The following abel code defines the behavior of the GAL Timing Charts A GAL decodes the microcontroller bus and asserts a chip enable signal when the microcontroller reads or writes to the I O location the NAT9914 occupies This GAL also expands a multiplexed address data bus for the NAT9914 In the example device the GAL has a propagation delay of 15 ns NAT9914 and M68HC11 CPU Read Timing Diagram lt gt 225 ei gt 220 P v ON mm M68HC11 lt i ons
32. series of tests read and write to each register and print an error message if any of the tests fail The tests must be run with no other devices attached to the GPIB port Although this collection of tests can run in any order additional GPIB tests inserted before this collection of tests might set bits that a soft reset command to the NAT9914 would not clear To use Test c on a microcontroller compile Test c and adjust the reset vector to point to the main body of the pro gram To observe the read write operation of the microcontroller connect a logic analyzer to all address data lines 2 Add microcontroller initialization code to the function initialize_microcontroller With the exception of interrupt vectors the M68HC11 initially powers up in the configuration that the NAT9914 and its board require For interrupts the external interrupt vector has to be set to point to handle nat9914 interrupts An enable external interrupt CLD instruction should just precede the clear software reset c nswrst command to the NAT9914 3 Update NAT9914 dependent code In initialize NAT9914 remove the redundant lines outp r7210 auxmr c7210 sw9914 and outp r auxcr c ch rst Adjust the clock speed by altering outp r accr f icr f 1mhz ininitialize NAT9914 Reference Sources IEEE Specifications ANSTIEEE Standard 488 1 1987 Digital Interface for Programmable Instrumentation ANSI ANSI IEEE 488 2 1992 IEEE Standard Codes Formats
33. the rsv2 command to request a serial poll instead of the rsv bit The rsv2 command clears itself after the serial poll and mixing rsv2 and rsv can cause undefined behavior 7 s if srq byte amp b_rsv ldab 1 x clra bitb 64 98 beq 163 GPIBDEV5 526 outp r auxcr c rsv2 ldab 152 stab 4227 L63 ins pulx rts L62 globl clear status byte bits srg response byt gt 0 x srq byte gt 1 x clear status byte bits pshb psha des tsx GPIBDEV5 530 i DH void clear_status_byte_bits u_8 srq_byte ldab 2 x stab 1 x GPIBDEV5 540 this routine encapsulates writes to the NAT9914 s spmr register It allows the calling routine to clear any combination of bits without affecting the others by clearing the bits corresponding to the asserted bits of its input It presents a consistent interface for ceasing to request serial polls Its counterpart is set status byte bits iM DH u_8 srq_response_byte DH srq response byte u 8 inp r spsr ldab 4229 stab 0 x GPIBDEV5 541 srq_response_byte srq_response_byte amp srq_byte ldab 1 x comb pshb ldab 0 x tsy andb 0 y ins stab 0 x GPIBDEV5 542 srq_response_byte srq_response_byte amp b_rsv andb 191 stab 0 x GPIBDEV5 543 5 outp r_spmr srq_response_byte stab 4229 GPIBDEV5 549 DH 7 use the rsv2 command to stop requesting a serial poll inste
34. 0 byte amp b bo handle BO int if isr0 byte amp b bi handle BI int if isrl byte amp b get handle GET trigger if isrl byte amp b dcas handle DCAS int void handle DCAS int void This routine resets only the GPIB interface of the device and not the device itself Its primary use is recovering after an error on the GPIB If a GPIB error occurs and the device locks up or appears to hang the GPIB controller can issue the SDC or DCL command and place the device into its idle GPIB state clear its buffers and start over 7 68 reinitialize variables and buffers Ef index 0 GPIB_state idle_state outp r auxcr c_rhdf isr0 byte 0x00 isrl byte 0x00 update serial poll response byte KL clear status byte bits b mav b rsv error reading error writing error unknown command acknowledge command received and processed by releasing DAC holdoff outp r auxcr c nonvalid void handle BI int void The Byte In handler reads a byte from the NAT9914 and stores it in the input buffer If the device has not finished writing data from a previous command message the device overwrites the old data and issues an error message to the GPIB controller 7 assert GPIB state idle state GPIB state reading state GPIB state writing state assert index lt BUFFER SIZE update the gpib state x if GP
35. 0x01 acer bits shadow registers define b icr 0x20 define b accra 0x80 define b accrb 0xa0 define b accre Oxc0 define b accrf 0xd0 define b_accri 0xe0 bsr bits are identical to bcr isr2 bits define b nba 0x80 define b stbo 0x40 define b nl 0x20 define b eos 0x10 define b lloc 0x08 define b atni 0x04 define b_cic 0x01 adr bits define b edpa 0x80 define b dal 0x40 define b dat 0x20 spmr spsr bits define b rsv 0x40 define b mav 0x10 accra bits define b_bin 0x10 define b xeos 0x08 define b reos 0x04 accrb bits define b iss 0x10 define b inv 0x08 define b lwc 0x04 define b_speoi 0x02 define b_atct 0x01 accre bits define b_dhadt 0x08 define b_dhadc 0x04 accrf bits define define define define define define define hata hala huntl hall accri bits b ustd b ppl b dmae turbo 488 cmdr 0x08 0x04 0x02 0x01 0x08 0x04 0x01 bits define bt488 sc en 0x01 define bt488 sc 0x02 auxcr commands define c nswrst 0x00 define c swrst 0x80 define c nonvalid 0x01 define c valid 0x81 define c rhdf 0x02 define c nhdfa 0x03 define c hdfa 0x83 define c nhdfe 0x04 define c hdfe 0x84 define c nbaf 0x05 define c nfget 0x06 define c fget 0x86 define c nrtl 0x07 define c rtl 0x87 define c feoi 0x08 define c nlon 0x09 define c lon 0x89 define c nton 0x0a define c ton 0x
36. 1083 0x1083 0x1082 0x1081 0x1080 0x1081 0x1083 138 2 0x1087 170 1 0x1080 64 2 0x1081 0 0 3 text globl tst11 CLStIL EST 269 test 11 struct ck check WT tauxmr 0x15 a xcr xlc auxcr 0x80 auxcr 0x00 auxcr Oxle mr2 0x00 MEL 0x00 imrO 0x00 imrl 0x40 auxcr Ox8a aor Oxaa D isr0 0x40 imrl 0x00 IMR1 t11 switch to 9914 mode reset chip reset chip reset chip page in to IMR2 turn off GLINT clear imrl clear imrO enable ton ERR IE KA fill CDOR check for interrupt clear flags for other tests 56 0 tst11 tu 25 return testit t11 ldd t11 jsr _testit clra tsx rts area data et 212 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 128 byte 2 word 0x1081 byte 0 byte 2 word 0x1080 byte 0 byte 2 word 0x1080 byte 16 byte 2 word 0x1083 byte 138 byte 1 word 0x1080 byte 144 byte 0 blkb 3 area text globl tst12 i gt 0 x tst12 pshx 57 H ifdef INT TEST DN EST tsx 294 test 12 Interrupt Test Struct ck WT tauxmr WT aux
37. 5 280 E DH 7 read data from the NAT9914 into the input buffer To improve performance loop instead of exiting the interrupt handler and then calling the interrupt handler again i 4 i do E read the data into the buffer If the buffer is full then the routine doesn t accept the new byt x d if index lt BUFFER_SIZE ldab _index clra cpd 15 tsx bhs 129 GPIBDEV5 281 H io buffer index u 8 inp r dir ldd 4 io buffer pshb psha ldab index clra tsy addd 0 y puly xgdy ldab 4231 stab 0 y GPIBDEV5 282 3 index ldab _index incb stab index L29 GPIBDEV5 289 i 89 assert index lt BUFFER SIZE check for another incoming byte SECH isr0 byte isr0 byte amp b bi ldab isr0 byte andb 223 stab isr0 byte GPIBDEV5 290 isr0_byte isr0_byte u_8 inp r_isr0 orab 4224 stab _isr0_byte L27 GPIBDEV5 291 while isr0 byte amp b bi ldab isr0 byte clra bitb 32 bne 126 GPIBDEV5 295 DH S if a complete message has been received interpret befor xiting i x H if isr0 byte amp b end parse_input_buffer ldab o isr0 byte clra bitb 8 beq 131 jsr o parse input buffer L31 tsx rts L21 globl handle BO int handle BO int GPIBDI DH EV5 312 Eod void handle BO int void This routine places the next byte from the output buffer into the NAT9914 If the device was reading data an
38. 57 ldab _io buffer 2 clra cpd 82 bne 157 ldab _io_buffer 3 clra cpd 69 bne 157 GPIBDEV5 491 io buffer 1 A 88 7 io_buffer 2 R amp amp d io_buffer 3 E adjust tare jsr o adjust tare tsx bra 158 L57 GPIBDEV5 496 else if the device received an unrecognized command send an error message i g 7 set status byte bits b rsv error unknown command ldd 68 jsr set status byte bits L58 97 L52 tsx rts L50 globl _set_status_byte_bits srq_response_byt 27 Oy x srq byte gt 1 x set_status_byte_bits pshb psha des tsx GPIBDEV5 508 p AF F Status Byte management routines 7 p F p FP void set_status_byte_bits u_8 srq_byte ldab 2 x stab 1 x GPIBDEV5 516 this routine encapsulates writes to the NAT9914 s spmr register It allows the calling routine to set any combination of bits without affecting the others It presents a consistent interface for requesting serial polls Its counterpart is x clear status byte bits PEU H u 8 srq response byte H S srq_response_byte u_8 inp r_spsr ldab 4229 stab 0 x GPIBDEV5 517 srq response byte srq response byte srg byte orab 1 x stab 0 x GPIBDEV5 518 srq_response_byte srq_response_byte amp b_rsv andb 191 stab 0 x GPIBDEV5 519 outp r spmr srq_response_byte stab 4229 GPIBDEV5 525 DH 7 use
39. 7 jsr _testit clra tsx rts L7 area data globl t8 t s byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 51 H tst8 byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte blkb area 0x1083 0x1082 0x1081 0x1080 0x1083 13 7 2 0x1083 31 2 0x1082 64 1 0x1087 0 0 3 text globl tst8 EST 198 test 8 struct ck 011 K p DEE RD dir tst8 return testit t8 ldd _ jsr clra check DIR by listening for silence tauxmr 0x15 auker Oxlc auxcr 0x80 auxcr 0x00 auxcr Oxle imr2 0x00 Amel 0x00 imrO0 0x00 auxcr 0x89 auxcr Oxlf 0x40 0x00 t8 testit D t8 switch to 9914 mode reset chip reset chip reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 lon page to BCR assert DAV and handshake check DIR 52 L8 LE tst9 tsx rts area data globl t9 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 0 byte 2 word 0x1081 by
40. 8a define c gts 0x0b define c_tca 0x0c define c_tcs 0x0d define c_nrpp 0x0e define c_rpp 0x8e define c nsic 0x0 define c sic 0x8 define c nsre 0x10 define c sre 0x90 define c rqc 0x11 define c rlc 0x12 define c ndai 0x13 define c dai 0x93 define c pts 0x14 define c nstdl 0x15 define c stdl 0x95 define c nshdw 0x16 define c shdw 0x96 40 define define define define define define define define define define define define define define define define c_nvstdl c_vstdl c nrsv2 c_rsv2 c sw7210 c regf cC regt oh rst nist Ge amb c_piimr2 c pibcr c clrpi C pieosr c piaccr c7210 sw9914 0x15 0x17 0x97 0x1 0x98 0x99 0x1 0x9a 0x1 0x1 0x9d 0x1 0x1 e f 0x9c 0x9e Ox9f 41 Test s H area data sglobil tL ese le byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte byte word byte 1 byte 1 word byte 1 byte 1 word byte byte 1 word byte byte word byte byte word byte byte blkb area 2 0x1085 21 2 0x1083 28 0x1083 0x1083 0x1083 0x1082 0x1081 0x1080 0x1083 0x1080 0x1081 0x1082 0x1083 0x1082 text globl Cart tstl EST 49 Sr tests c 7 15 97 42 Th properl ACCR will in
41. FER SIZE rts 133 globl handle GET trigger handle GET trigger GPIBDEV5 387 5 Device Dependent Routines p void handle GET trigger void This routine performs a device specific trigger action nr 7 DH i ZS insert code to implement the device specific trigger action i x DH s release DAC holdoff to acknowledge to other routines and to the GPIB controller that the device specific trigger action has been completed x z isrl byte isrl byte amp b_get ldab Larl byte andb 127 stab Larl byte GPIBDEV5 388 i outp r auxcr c nonvalid 93 ldab 1 stab 4227 rts L46 globl _read_voltage _read_voltage GPIBDEV5 405 p void read voltage void This routine is an example of a device specific execute query V A S read the device specific data i x DH format the device specific data i xy DH output the data to the output buffer i xy output data to io buffer 1 ldd 49 jsr output data to io buffer GPIBDEV5 406 output data to io buffer ldd 46 jsr output data to io buffer GPIBDEV5 407 output data to io buffer 2 ldd 50 jsr output data to io buffer GPIBDEV5 408 i output data to io buffer V ldd 86 jsr output data to io buffer tsx rts L47 globl _adjust_tare _adjust_tare GPIBDEV5 414 r
42. GPIB controller and exits 7 assert GPIB state idle state GPIB state reading state GPIB state writing state update the GPIB state if GPIB_state idle state only write if data has been written to the output buffer if index 0 isr0 byte isr0 byte amp b_bo else index 0 GPIB_state writing_state If the controller and the device are both trying to read data set an error 70 flag in the serial poll response byte f else if GPIB state reading state set status byte bits error writing isr0 byte isr0 byte amp b bo write the data bytes to the NAT9914 until the listener stops listening or the device runs out of data To improve performance loop instead of exiting the interrupt handler and then calling the interrupt handler again kf while isr0_byte amp b_bo assert index lt BUFFER SIZE output a byte from the output buffer outp r cdor io buffer index index check if NAT9914 is ready to send another byte isr0 byte isr0 byte amp b bo isr0 byte isr0 byte u 8 inp r isr0 If the device is out of data update the serial poll respons sending data and reset the buffer e if io buffer index 1 NEWLINE clear status byte bits b mav b rsv GPIB state idle state index 0 isr0 byte isr0 byte amp b_bo
43. IB state idle state index 0 GPIB state reading state if the controller is sending data to the device while the device is trying to send data to the controller set an error flag in the status byte to warn the controller xy else if GPIB state writing state clear status byte bits b mav set status byte bits b rsv error reading GPIB state reading state index 0 outp r auxcr c nbaf read data from the NAT9914 into the input buffer To improve performance loop 69 instead of exiting the interrupt handler and then calling the interrupt handler again xj do read the data into the buffer If the buffer is full then the routine doesn t accept the new byt EA if index lt BUFFER SIZE io_buffer index u_8 inp r_dir index assert index lt BUFFER SIZE check for another incoming byte unless th nd of the string is detected uA isr0 byte isr0 byte amp b bi if isrO byte amp b_end isr0 byte isr0 byte u 8 inp r isr0 while isr0 byte amp b bi if a complete message has been received interpret befor xiting if isr0 byte amp b end parse input buffer void handle BO int void This routine places the next byte from the output buffer into the NAT9914 If the device was reading data and received a spurious command to write the function issues an error message to the
44. INSTRUMENTS The Software is the Instrument Wy NATIONAL Application Note 110 Designing a GPIB Device Using the NAT9914 Andrew Thomson Introduction This application note describes how to build a GPIB device using the NAT9914 and a common microcontroller It discusses methods to implement GPIB commands and provides a flexible structure to build a GPIB interface into your instrument This application note supplements the descriptions in the NAT99 4 Reference Manual of hardware and software considerations of a GPIB device More information about the NAT9914 and its command set and registers can be found in the NAT9914 Reference Manual More help on the GPIB interface itself can be found in the IEEE 488 1 and IEEE 488 2 specifications Appendix A contains a comprehensive tutorial on the GPIB including a historical summary Appendix B contains soft ware listings of the programs described later in this document Determining Performance Requirements Several factors determine how fast a GPIB interface needs to be e Amount of data transferred a device such as a digital multimeter may transfer only a few bytes every few sec onds A device such as an oscilloscope can transfer several megabytes at a time A large amount of data requires a faster GPIB interface e Typical application of the device in a production test environment a slow device can increase testing time there fore increasing testing cost In a laboratory an engineer
45. L if gpib address 31 clra cpd 31 bne L9 IBDEV5 175 E gpib address 30 ldab 30 stab 0 x IBDEV5 177 return gpib address ldab 0 x clra pulx rts L8 globl route nat9914 interrupts 85 route nat9914 interrupts GPIBDEV5 198 Fx PRE ie F a 8 Handle Interrupt Routines z A po void route nat9914 interrupts void route nat9914 interrupts handles the hardware interrupt from the NAT9914 It determines what caused the interrupt and calls the appropriate function If no interrupts are pending then it does nothing s read isr0 and isrl the values must be saved because the act of reading the bits in the registers clears the bits SC isr0 byte isr0 byte inp r isr0 ldab isr0 byte orab 4224 stab isr0 byte GPIBDEV5 199 i isrl byte isrl byte inp r isrl ldab Larl byte orab 4225 stab Larl byte GPIBDEV5 203 DH A determine the cause of the interrupt and handle it i SR S if isr0 byte amp b bo handle BO int ldab J isr0 byte clra bitb 16 beg 112 jsr _handle BO int L12 GPIBDEV5 204 E if isr0 byte 8 b bi handle BI int ldab isr0 byte clra bitb 32 tsx beq 114 jsr handle BI int L14 GPIBDEV5 205 if isrl byte amp b get handle GET trigger ldab Larl byte clra bitb 128 tsx beq 116 jsr handle GET trigger 86 L16 GPIBDEV5 206 if isrl byte am
46. Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imr0 WT auxcr Oxlf page in to use spsr WT spmr Oxaa set spmr RD spsr Oxaa check spsr 01 tst6 return testit t6 31 test 7 check CDOR and CPTR by talking and hearing it back struct ck ELT WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imr0 WT auxcr Ox8a address to talk WT cdor 0x55 assert data to cdor RD cptr 0x55 hear it on the line 01 tst7 return testit t7 test 8 check DIR by listening for silence struct ck SLT se 4 WI tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imr0 WT auxcr 0x89 lon WT auxcr Ox1f page to BCR WT bcr 0x40 assert DAV and handshake RD dir 0x00
47. PI leads to greater productivity by featuring software command standards and instant interchangeability Rather than learning a different command set for each instrument you can focus on solving measurement problems 12 Although you can mix SCPI and non SCPI instruments in a system your complete system must adhere to IEEE 488 2 for you to fully benefit from these standards See Appendix C Standard Commands for Programmable Instruments SCPI for more information GPIB Hardware Configuration A GPIB hardware setup consists of two or more GPIB devices instruments and or interface boards that are connected by a GPIB cable The cable assembly consists of a shielded 24 conductor cable with a plug and a receptacle male female connector at each end With this design you can link devices in a linear configuration a star configuration or a combination of these two configurations see Figures A 2 and A 3 TS HILL UU DL Device A Device B Device C 13 Figure A 3 Star Configuration GPIB Signals and Lines The GPIB has 16 signal lines and 8 ground return or shield drain lines see Figure A 4 All GPIB devices share the same 24 bus lines The 16 signal lines fall into three groups Eight data lines e Five interface management lines Three handshake lines Je DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DIO4 4 16
48. PPR7 66 0 PPR8 67 1 PPR1 68 1 PPR2 69 1 PPR3 6A 1 PPR4 6B 1 PPR5 6C 1 PPR6 6D 1 PPR7 6E 1 PPR8 6F Physical Representation of the PPR Message To send a PPR message true a device drives the corresponding GPIB DIO signal low with an open collector driver For example to send the PPR4 message true a device drives the GPIB DIO4 signal low Because devices drive the DIO signals with open collector drivers during parallel polls more than one device can share a PPR message If a Controller detects a PPR message being sent true the Controller knows that one or more of the devices sharing the PPR message is sending the PPR message true 27 Clearing and Triggering Devices A Controller can clear devices in several ways It can assert the IFC line to clear all devices or it can send the Device Clear DCL command message to clear all devices on the bus To clear a single device a Controller can address the device to listen then send the Selected Device Clear SDC command message After a device receives DCL or SDC its clear state is device dependent Generally sending DCL or SDC is a less extreme method of clearing a device than asserting IFC Most devices support the DCL and SDC method all devices support the IFC method All devices in multidevice measurement systems must often be sampled as closely together as possible You can trig ger devices simultaneously by using the Group Execute Trigger GET command message Th
49. Protocols and Common Commands for Use with IEEE Stan dard 488 1 1987 IEEE Standard Digital Interface for Programmable Instrumentation ANSI SCPI Specifications Fred Bode Executive Director SCPI Consortium 8380 Hercules Drive Suite P3 La Mesa CA 91942 Phone 619 697 8790 FAX 619 697 5955 GPIB Transceivers National Semiconductor http www national com Texas Instruments 972 644 5580 http www ti com sc GPIB Connectors Emulation Technology Inc 409 982 0660 L Com Inc 1 800 343 1455 http www L com com GPIB Hardware and Resources National Instruments http www natinst com e GPIB cables e GPIB controllers e NAT9914 Reference Manual 10 Appendix A GPIB Tutorial Introduction to the GPIB This appendix discusses the history of the GPIB GPIB hardware configurations and serial polling History of the GPIB Hewlett Packard developed the original GPIB and called it the HP IB in the late 1960s Hewlett Packard developed its HB IB to connect and control programmable instruments that Hewlett Packard had manufactured The introduction of digital controllers and programmable test equipment created the need for a standard high speed interface that would permit communication between instruments and controllers from various vendors In 1975 the IEEE published ANSI IEEE Standard 488 1975 IEEE Standard Digital Interface for Programmable Instrumentation which contained the electrical mechanical and functio
50. R po p TX r VX by enabling dat t5 switch to 9914 mode reset chip reset chip reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 set to ton try to output some data make sure it is talking correctly disable talk with dat no talking 48 WT adr 0 S65 i return testit t5 ldd 4 t5 _testit jsr Gir tsx rts L5 a 0x00 area data globl t6 t6 by wo by by wo by by wo by byt wo by by wo by by wo byt by wo by by wo by by wo by by wo by by wo byt by bl ar tst6 EST 156 H te rd te te rd te te rd te e rd te te rd te te rd e te rd te te rd te te rd te te rd te te rd kb ea 2 0x1 21 2 0x1 28 2 0x1 128 170 0x1 170 0 3 085 083 083 1083 1083 1082 1081 1080 1083 1085 085 text globl tst6 enable talking for other tests 49 test 6 Struct ck 0 tst6 L6 Bu return testit t6 check WT auxcr WT auxcr WT auxcr WT auxcr WT imr2 WT imrl WT mr WT auxcr WT spmr RD spsr WT tauxmr O0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 Ox1f Oxaa Oxaa ldd t6 jsr _testit
51. ad of the rsv bit d The rsv2 command clears itself after the serial poll and mixing rsv2 and rsv can cause undefined behavior 99 ZC if srq byte amp b_rsv ldab clra bitb beq GPIBDEV5 550 ldab stab L66 ins pulx rts L65 Lem 64 L66 5 outp r auxcr c nrsv2 24 4227 area memory abs org 0x0010 gl isrl byte bl gl isr0 byte zb gl lo buffer bl egi index bl gl GPIB state bl obl kb 1 obl kb 1 obl kb 1 obl kb 1 obl kb 1 isrl byte isr0 byte io buffer index GPIB state 341398A 01 Jan98
52. check DIR 0 tst8 return testit t8 test 9 check PPR by initiating a parallel poll struct ck t9 WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imrO WT ppr 0xaa fill the PPR with data WT auser Ox1f page to BCR 32 WT bcr 0x88 set EOI and ATN high RD cptr Oxaa O tst9 return testit t9 f REC Kk e ke e ke e ke e e e e e CkCkckckckckckckckckckckckck ck KKK KKK KK IMR tests disable interrupts with GLINT and check them by reading INTO and INT1 the GLINT bit is used in both tests k kk kok kk kk kk kk kk kk kk k Ck k Ck k Ck k Ck k Ck k Ck k kCKCkCKCk Ck A k ck k ck ck ck kk kk sk ke ke e k IMR2 is implicitly tested sinc test 10 check IMRO struct ck t10 WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to IMR2 WT imr2 0x00 turn off GLINT WT imrl 0x00 clear imrl WT imr0 0x00 clear imr0 WT imrO 0x10 enable BO IE WT auxcr 0x8a ton RD isr0 0x90 INTO and BO WT imr0 0x00 clear flags for
53. clra tsx rts area data globl t7 by WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt byt WO byt by te rd ce 2 0x1 2 2 0x1 28 2 0x1 128 2 085 083 083 1083 1083 1082 1081 1080 SPMR SPSR by writing and checking toL sac switch to 9914 mode reset chip reset chip reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 page in to use spsr set spmr check spsr 50 word byte byte word byte byte word byte byte blkb area tst7 EST 177 H 0x1 138 0x1 85 0x1 85 0 3 083 087 086 text globl tst7 a OPE CESSES check CDOR and CPTR by talking and hearing it back struct ck t7 WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip S WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imrO 0x00 clear imrO WT auxcr Ox8a address to talk 7 WI dor 0x55 assert data to cdor RD cptr 0x55 hear it on the line 0 DH tst7 i z return testit t7 ldd t
54. cr WT auxcr WT auxcr WT auxcr WT imr2 WT imrl WT mr WT mr WT auxcr RD isr0 0 tst12 nop u_8 i switch to 9914 mode IMR2 clear imrl clear imrO t 121 0x15 Oxlc reset chip 0x80 reset chip 0x00 reset chip Oxle page in to 0x80 turn on GLINT 0x00 0x00 0x10 enable BO IE 0x8a JA bor AY 0x90 INTO and BO set up conditions for an interrupt interrupt_pending ldab 1 1 stab _interrupt_pending e297 3 outp tauxmr 0x15 ldab 21 stab 422 298 ldab 28 stab 422 299 ldab 128 stab 422 23005 clra clrb stab 422 301 ldab 30 stab 422 3023 ldab 16 stab 422 30325 ldab 138 stab 422 9 A 7 7 T 4 7 asm outp outp outp outp outp outp Teli tju switch to 9914 mode auxcr Oxlc reset chip auxcr 0x80 reset chip auxcr 0x00 reset chip auxcr Oxle page in to IMR2 imr0 0x10 enable BO IE auxcr 0x8a ton 58 nop nop nop TEST 310 wait for the interrupt asm nop n nop n 2 nop n i nop n S trigger_logic_analyzer 0x20 ldab 32 stab 4369 TEST 313 check for the interrupt z if interrupt
55. d received a spurious command to write issues an error message to the GPIB controller and exits nes CEN DH 7 assert GPIB state idle state H GPIB state reading state S GPIB state writing state DH update the GPIB state x z if GPIB_state idle_state ldab _GPIB state clra cpd 1 bne 134 90 the function GPIBDEV5 315 only write if data has been written to the output buffer RY d if index 0 ldab _index clra cpd 0 bne 136 GPIBDEV5 316 i isr0 byte isr0 byte amp b bo ldab isr0 byte andb 239 stab _isr0_byte bra 135 L36 GPIBDEV5 319 i x else index 0 clra clrb stab index GPIBDEV5 320 H GPIB state writing state ldab 3 stab _GPIB state bra 135 L34 GPIBDEV5 326 i S If the controller and the device are both trying to read data set an error flag in the serial poll response byte E F else if GPIB_state reading_state ldab _GPIB state clra cpd 42 bne 138 GPIBDEV5 327 E set status byte bits error writing ldd 2 jsr set status byte bits GPIBDEV5 328 F isr0_byte isr0 byte amp b_bo ldab _isr0O_byte andb 239 stab _isr0O_byte L38 135 L40 141 GPIBDEV5 335 i DH write the data bytes to the NAT9914 until the listener stops listening or the device runs out of data To improve performance loop instead of exiting the interrupt handler and then call
56. d stores it in the input buffer If the device has not finished writing data from a previous command message the acknowledge command received and processed by releasing DAC holdoff device overwrites the old data and issues an error message to the GPIB controller Ro ORS DH z assert GPIB state idle state H GPIB state reading state GPIB state writing state d assert index lt BUFFER SIZE DH update the gpib state i e d if GPIB_state idle_state ldab _GPIB state clra cpd 41 bne 122 GPIBDEV5 256 H index 0 clra clrb stab index GPIBDEV5 257 H GPIB state reading state ldab 2 stab _GPIB state bra 123 L22 GPIBDEV5 264 i DH if the controller is sending data to the device while the device is trying to 7 send data to the controller set an error flag in the status byte to warn the 3 controller i Kh A else if GPIB_state writing_state ldab _GPIB state clra cpd 3 88 bne 124 GPIBDEV5 265 i clear status byte bits b mav ldd 16 jsr clear status byte bits GPIBDEV5 266 A set_status_byte_bits b_rsv error_reading ldd 65 jsr set status byte bits GPIBDEV5 267 H GPIB state reading state ldab 2 stab _GPIB state GPIBDEV5 268 index 0 clra clrb stab _index GPIBDEV5 269 outp r auxcr c_nbaf ldab 5 stab 4227 L24 L23 L26 GPIBDEV
57. e in to imr2 WT imr2 0x00 clear GLINT bit and imr2 WT imrl 0x00 clear imrl WT imrO 0x00 clear imrO WT auxcr Ox8a ton KY RD isr0 0x10 BO bit set no interrupts RD isrl 0x00 RD adsr 0x02 9914A is TADS WT auxcr 0x0a clear ton RD adsr 0x00 TADS cleared 01 tst1 return testit t1 29 Test 2 check ISR2 with CDOR struct ck WT 011 tst2 tauxmr auxcr auxcr auxcr auxcr imr2 imri imr0 isr2 cdor isr2 t2 0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 0x00 Oxaa 0x80 return testit t2 med switch to 9914 mode reset chip reset chip reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 all clear set nba bit in isr2 by writing to cdor make sure nba bit is set Test 3 check BCR by reading from a write to BSR struct ck 011 tst3 tauxmr auxcr auxcr auxcr auxcr imr2 imrl imr0 auxcr ber bsr t3 0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 0x1 0x40 0x40 return testit t3 test 4 struct ck WT tauxmr auxcr auxcr auxcr auxcr imr2 imri imr0 el switch to 9914 mode reset chip reset chip reset chip
58. ed its status information in a different format The IEEE 488 2 Solution The IEEE 488 2 standard eliminates the IEEE 488 1 problems through the following solutions e JEFE 488 2 contains a minimum set of required device interface capabilities e EEE 488 2 specifies a way of presenting data through data formats and codes e EEE 4882 defines a specific protocol for sending device messages and the syntax for multiple commands in a single string e IEEE 488 2 contains a common command set e EEE 488 2 contains a standard status reporting model SCPI Specification The SCPI specification expands the IEEE 488 2 common command set by defining a single comprehensive command set that is suitable for all instruments For example all SCPI compatible voltmeters regardless of manufacturer or model respond to the same command for reading AC voltage Their response format is also the same SCPI embraces many of the commands and protocols that the hardware independent portion of the IEEE 488 2 stan dard defines Figure A 1 illustrates the structure of the GPIB standards Command Hierarchy Standard Response Format Standard Program Command Set Pa Software Firmware p y D Common Commands L Syntax Data Structures amp Handshaking Control gt Mechanical Electrical Standards Figure A 1 Structure of the GPIB Standards The combination of IEEE 488 2 and SC
59. est Enable Register you can configure an instrument to assert the SRQ line based on the bits of its status register IEEE 488 2 defines a dual role for the RQS bit This bit is also known as the Master Summary Status MSS bit The MSS bit indicates whether there is at least one reason for the instrument to request service The status of this bit is returned only in response to the status byte STB query its status is not sent in response to a serial poll because this bit is not part of the IEEE 488 1 status byte see Figure A 8 Standard Event Status Register ESR N Power On O User Request O1 Command Error A Execution Error Device Dependent Error N Query Error Request Control Operation Complete Logical OR Queue Not Empty Standard Event Status Enable Output Queue Register ESE lt NRf gt Service read by Serial Poll Request Generation Status Byte Register lt read by STB d Service Request ET Enable Register SRE lt NRf gt SRE Figure A 8 IEEE 488 2 Standard Status Structures 25 Parallel Polling Parallel polling is another way to get information from a device that requests service Parallel polling differs from serial polling in two ways all configured devices are polled simultaneously that is in parallel and a Controller initiates a parallel poll sequence
60. ge if this line is asserted the information is a command message from the Controller to all devices The devices on the GPIB monitor the ATN line determine the data type and treat the data appropriately GPIB Addressing Protocol In a classroom an instructor either speaks to the entire class or to a particular student To speak to a student the instructor first addresses that student by name Addressing on the GPIB follows the same idea Before any communication can take place on the bus you must address the Talker and Listener Before any data passes between devices the Controller determines who talks and who listens In the classroom we address people by their names However on the GPIB each device including the Controller has a unique primary GPIB address in the range of 0 to 30 decimal The Controller places a command message spec ifying the addresses of the Talker and Listener devices on the bus The Controller sends a single byte 8 bits of information for a Talker or Listener address command message Address command messages have the following format Bt 7 6 5 4 3 2 11 0 Data TA LA X X X X X Bits 0 through 4 contain the binary GPIB primary address of the device in communication and either bit 5 Listener Address LA or bit 6 Talker Address TA will be set if the device is a Talker or a Listener Bit 7 is never used and is considered a don t care bit For simplicity assume
61. groups of columns The left or first group of columns hex 00 1F represents the primary GPIB addresses Moving to the right to the next group of columns hex 20 3F you will find the corresponding listen addresses MLA The listen address of a device is formed by adding hex 20 to the GPIB primary address Again move right to the next group of columns hex 40 5F for the corresponding talk addresses MTA You form the talk address of a device by adding hex 40 to the GPIB primary address Secondary Addressing A device can have a secondary address A secondary address is in the range of 0 to 30 decimal IE hex To form a secondary address command bit pattern add 96 decimal 60 hex to the secondary address You address a device with a secondary address by sending the primary GPIB address then the corresponding secondary address With secondary addressing you can assign up to 961 talk and listen addresses Most instruments do not use secondary addressing In the Multiline Interface Command Messages table the group of columns on the right hex 60 7F represents the secondary GPIB address commands Unaddressing Command Messages The CIC uses two special command messages to clear the bus of Talkers and Listeners before assigning new Talkers and Listeners These command messages are Untalk and Unlisten The Untalk UNT command hex SF ASCII unaddresses the current Talker The Untalk command is merely a command for convenience because
62. has an independent Sense bit 26 The meaning of the PPR message and the local ist message is device dependent Configuring a Device for Parallel Polls To configure a device to respond to parallel polls you must supply the device with two pieces of data e The PPR message that the device should send to the Controller PPR1 PPR2 or PPR8 The value of the Sense bit of the device You can configure devices locally or remotely You ocally configure Parallel Poll function subset PP2 a device by setting knobs or switches on the front panel of the device or by physically manipulating the device in some other way You remotely configure Parallel Poll function subset PP1 a device by sending messages across the GPIB from the Controller to the device If a device has not been configured to respond to parallel polls it does not respond to parallel polls Some devices support only local configuration and some support only remote configuration Some devices do not sup port any parallel polls Parallel Poll function subset PPO Determining the PPE Message The PPE message contains the parallel poll configuration data for a device Table A 2 shows how you determine the value of DIO 7 1 for the PPE message As with all commands the DIO 8 is a don t care bit Table A 2 Determining the PPE Message Sense Bit S PPR Message PPE Message to Send hex 0 PPRI 60 0 PPR2 61 0 PPR3 62 0 PPR4 63 0 PPR5 64 0 PPR6 65 0
63. he talking device from sending more data If you do not clear the remaining data from the bus you can recover it later Students can use the count method in the classroom Students count the words of someone who is talking The Listener announces that he or she will listen to only a specified number of words Beyond this number of words the Listener will not hear any further information from the Talker If the Listener wants more information he or she requests more words from the Talker Combinations of Termination Methods You can use any combination of the three termination methods to terminate communication on the GPIB For example you can specify an EOS character and also use the EOI line method In this case when the end of the string is reached the device sending the data will send an EOS character and assert the EOI line When you use more than 22 one method the first termination method recognized causes the termination In this example the EOS character or EOI line causes termination depending on which method the device recognizes first In general when you use more than one termination method at a time all methods are logically ORed together for a result Therefore if you use all three methods the communication termination will take place if the device sees the EOS character the system asserts the EOI line or the count value has been reached Serial Polling Servicing SRQs In the classroom an instructor is in charge of
64. ine b rlc 0x02 define b mac 0x01 imr0 bits define b dma0 0x80 76 define define define defin b_dmal b_bi_ie b_bo_ie b_end_i define define define isrl define define define define define define define define imrl defin b spas ie b rlc ie b mac ie bits b get b err b unc b apt b dcas b ma b srq B xc bits b get i defin define define define define define define adsr define define define define define define define define fe Amr define define define define define define define define define define define define define b err i b unc ie b apt ie b dcas ie b ma ie b srg ie b ifc ie bits b rem b llo b atn b lpas b tpas b la b ta b ulpa bits b glint b stbo ie b nlen b lloc ie b atni ie b cic ie bcr bits b bcr atn b bcr dav b bcr ndac b bcr nrfd b bcr eoi b bcr srq b bcr ifc 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x08 0x04 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 77 define accr define define define define define define b bcr ren 0x01 fields shadow registers f icr 0x20 f accra 0x80 f accrb 0xa0 f_accre 0xc0 f accrf 0xd0 f_accri 0xe0
65. ing the interrupt handler again i K 7 while isr0 bytesb bo ldab _isr0_ byte clra 91 GPIBDI GPIBDI GPIBDI GPIBDI GPIBDI GPIBDI bitb 16 tsx beq L42 EV5 3401 E assert index lt BUFFER SIZE output a byte from the output buffer outp r cdor io buffer index ldd 4 io buffer pshb psha ldab index clra tsy addd 0 y puly xgdy ldab 0 y stab 4231 EV5 341 H index ldab _index incb stab _index EV5 345 check if NAT9914 is ready to send another byte x isr0 byte isr0 byte amp b bo ldab _isr0_ byte andb 239 stab isr0O byte EV5 346 isr0_byte isr0_byte u 8 inp r_isr0 orab 4224 stab _isr0_byte EV5 351 If the device is out of data update the serial poll respons sending data and reset the buffer SCH if io buffer index 1 NEWLINE ldd _io_buffer 1 pshb psha ldab _index clra tsy addd 0 y puly xgdy ldab 0 y clra cpd 10 bne 140 KK 3023 i clear status byte bits b mav b rsv ldd 80 JSE clear_status_byte_bits 92 register stop GPIBDEV5 354 n GPIB state idle state ldab 1 stab _GPIB state GPIBDEV5 355 index 0 clra clrb stab _index GPIBDEV5 356 i isr0 byte isr0 byte amp b bo ldab _isr0_ byte andb 239 stab isr0 byte tsx jmp 140 L42 GPIBDEV5 361 i i assert index 0 amp amp index BUF
66. interrupts now sorts out what caused the interrupt and processes it completely before return ing microcontroller control back to the main program The NAT9914 INT pin can be configured for active low or active high by setting or clearing the INV bit ofthe ACCRB register The INT pin defaults to active low The NAT9914 drives the INT pin with an open collector gate so wire an external pullup resistor to it Parsing The versatility of your device will specify the complexity of the parsing routine This example device uses a simple parsing algorithm Both the buffer size and the parsing algorithm can easily be altered to accommodate more complex command sets Reporting Device Status The NAT9914 will return a status byte to the controller when the GPIB controller serial polls your device The SPMR register contains the status byte The act of setting the RSV bit of the SPMR register asserts the SRQ line and requests a serial poll IEEE 488 2 defines the MAV bit but leaves the lower nibble of the status byte device specific The NAT9914 handles serial polls without intervention by the microcontroller This feature makes the status byte an ideal place to keep status information and error messages Configure the SPMR through routines that strip away any writes to the RSV bit and replace writes to that particular bit with calls to rsv2 In the example device set_srq_bits and clear srg bits handle this function Some GPIB controllers auto
67. is command message causes all devices that have triggering capability and that are currently addressed to initiate a preprogrammed action The action could be for example to take a measurement or begin a sweep 28 Appendix B Software Listings Test c tests c 7 15 97 This file contains tests to determine whether the NAT9914 is connected properly It reads and writes to each register except the hidden registers in ACCR It is designed to be used unconnected to any other GPIB devices and will interfere with them and they may confuse the tests define INT TEST include test h define trigger_logic_analyzer a unsigned char TRIGGER_ADDRESS a define inp io address unsigned char io address define outp io address o data unsigned char io address o data u 8 interrupt pending XK ckckckckckckckck ck ck ck kk ck kckck ck TEST TABLES AND SPECIAL TEST ROUTINES ck ck ck ck ck ck ck kk kk XX ko ko ko Updated May 28 1997 fully functional JA ec x kkkkkkkkkkkkkkkkkkkkkkkk Simple tests 1 9 FER KK k k k kk ke ke ke ke ke ke e e x Test 1 check ADSR and ISRO by programming to talk with ton struct ck tl1 WT tauxmr 0x15 switch to 9914 mode WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle pag
68. l 0x00 E WT imrO 0x00 WT auxcr 0x8a WT cdor 0x55 RD isrl 0x40 0 tst4 i E return testit t4 ldd t4 jsr _testit clra tsx rts L4 area data g1obl ES 55 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 t4 ERR flag switch to 9914 mode reset chip reset chip set try ERRor flag set becaus reset chip page in to imr2 clear GLINT bit clear imrl clear imr0 to ton to output some data answered no on 47 d byte 0 byte 2 word 0x1 byte 30 byte 2 word 0x1 byte 0 byte 2 word 0x1 byte 0 byte 2 word 0x1 byte 0 byte 2 word 0x1 byte 13 byte 2 word 0x1 byte 85 byte 1 word 0x1 byte 85 byte 2 word 0x1 byte 32 byte 1 word 0x1 byte 0 byte 2 word 0x1 byte 0 byte 0 blkb 3 area text globl _tst5 tst5 EST 135 test 5 struct WT ck tauxmr auxcr auxcr auxcr auxcr imr2 imrly imr0 auxcr cdor Cptr adr CPET 083 082 081 080 083 8 087 086 084 086 084 check 0x15 Oxlc 0x80 0x00 Oxle 0x00 0x00 0x00 0x8a 0x55 0x55 0x20 0x00 AD
69. matically status poll devices and display the previous poll results instead of retrieving newer status data You may wish to disable auto serial polling when testing your device You can configure the NAT9914 with STBO IE in IMR2 to interrupt when the GPIB controller serial polls your device and wait for the microcontroller to write a byte to the SPMR before the NAT9914 responds to the serial poll For more information on status reporting refer to the NAT9914 Reference Manual Other Topics Changing the End of Message Condition When Listening The EOSR register stores the EOS byte To change the EOS byte write a new value to the EOSR register Be careful of changing the EOS character any time except start up Sending Binary Data When transferring binary data use EOI not EOS To disable EOS clear the XEOS and REOS bits in the ACCRA register To end a binary data transmission write the feoi command to the AUXCR register before writing the last byte to the CDOR Compiling the Software All assert statements are left in the code to ease debugging especially of a buffer overflow You can enable the assert statements by replacing define assert a with include assert h To compile the software for a microcontroller 1 Test the glue between the microcontroller and the NAT9914 with Test c The short program Test c was designed to test the connections on the microcontroller and ensure that it can com municate with the NAT9914 This
70. n 0x0a define c ton 0x8a define c gts 0x0b define c_tca 0x0c define c_tcs 0x0d define c_nrpp 0x0e define c_rpp 0x8e define c nsic OxOf define c sic 0x8 define c nsre 0x10 define c sre 0x90 define c rqc 0x11 define c rlc 0x12 define c ndai 0x13 define c dai 0x93 define c pts 0x14 define c nstdl 0x15 define c stdl 0x95 define c nshdw 0x16 define c shdw 0x96 define c nvstdl 0x17 define c vstdl 0x97 define c_nrsv2 0x18 define c rsv2 0x98 define c sw7210 0x99 define c regf Oxla define c regt 0x9a define c ch rst Oxlc define c nist Oxld define c_ist 0x9d define c piimr2 Oxle define c pibcr 0x1 define c clrpi 0x9c define c pieosr 0x9e define c piaccr 0Ox9f NAT9914 in 7210 mode commands define c7210 sw9914 0x15 typedef unsigned char u 8 buffer and GPIB state declarations define BUFFER SIZE 15 define idle stat 1 define reading state 2 define writing state 3 function declarations void initialize device void u 8 get gpib address void void route nat9914 interrupts void void handle DCAS int void void handle BI int void void handle BO int void void handle GET trigger void void parse input buffer void void read voltage void void adjust tare void void output data to io buffer u 8 void initialize microcontroller void void initialize NAT9914 void void set status byte bits u 8 void clear status byte bits u 8
71. n method of terminating data strings Talkers and Listeners have the following properties e Talkers Are instructed by the Controller to talk Place data on the GPIB Permit only one device to talk at a time e Listeners Are instructed by the Controller to listen Read data that the Talker places on the GPIB Permit several devices to be Listeners simultaneously You can compare GPIB operation to a classroom The instructor Controller controls the communication of data between the students devices The instructor decides who talks and who listens On the GPIB a device cannot talk or listen unless the Controller explicitly tells it to do so Figure A 6 shows a system setup example tk t 225 System Controller Plotter Figure A 6 System Setup Example 19 Data and Command Messages In aclassroom when the instructor tells the students who is the Talker and who are the Listeners his or her information is a command not the actual data information that the instructor will send On the GPIB this distinction is not so intuitive The bus management line ATN determines what type of message you are sending on the bus If this line is unasserted the information on the bus is a data messa
72. nal specifications of an interfacing system The original IEEE 488 1975 was revised in 1978 primarily for editorial clarification and addendum This bus is now used worldwide and is known by three names e General Purpose Interface Bus GPIB e Hewlett Packard Interface Bus HP IB e EEE 488 Bus Because the original IEEE 488 document contained no guidelines for preferred syntax and format conventions work continued on the specification to enhance system compatibility and configurability among test systems This work resulted in a supplement standard IEEE 488 2 Codes Formats Protocols and Common Commands that you use with IEEE 488 which was renamed IEEE 488 1 IEEE 488 2 does not replace IEEE 488 1 Many devices still conform only to IEEE 488 1 IEEE 488 2 builds on IEEE 488 1 by defining a minimum set of device interface capabilities a common set of data codes and formats a device message protocol a generic set of commonly needed device commands and a new status reporting model In 1990 a consortium of test and measurement companies developed the Standard Commands for Programmable Instrumentation SCPI document SCPI defines specific commands that each instrument class which usually includes instruments from various vendors must obey Thus SCPI guarantees complete system compatibility and configurabil ity among these instruments You no longer need to learn a different command set for each instrument and you can easily replace
73. nd Listeners All buses operate under rules that ensure that data passes reliably and that instruments do not use the bus simultaneously To determine which device has active control of the bus devices are categorized as Controllers Talkers or Listeners Whenever two devices communicate one device will be a Talker and the other will be a Listener In addition one device will always be a Controller Controllers Most GPIB systems consist of one computer and a variety of instruments In this type of system the computer is typically the System Controller If multiple computers are connected several devices can have Controller capability but only one Controller is active or Controller In Charge CIC at a time Active control can pass from the current CIC to an idle Controller For each GPIB system you must define a System Controller You usually define the System Controller through jumper settings on the GPIB interface board a software configuration file or both Only one device on the bus the System Controller can make itself the CIC The four primary responsibilities of a Controller are the following e Defining the communication links e Responding to devices requesting service e Sending GPIB commands e Passing receiving control 18 Talkers and Listeners You can set most GPIB devices to be either Talkers or Listeners However some devices only talk or only listen Each device accepts its own command set and has its ow
74. nse_byte use the rsv2 command to stop requesting a serial poll instead of the rsv bit The rsv2 command clears itself after the serial poll and mixing rsv2 and rsv can cause undefined behavior x if srq byte amp b rsv outp r auxcr c nrsv2 75 Gpibdevc h gpibdevc h gi define Base Address 0x1080 defin rror reading 1 0 define error writing 1 lt lt 1 define error unknown command 1 lt lt 2 define NEWLINE 0x0a line feed define PORT D 0x1008 define interrupt vector OxFFF2 define i o addresses of the registers on the nat9914 define r isr0 Base Address define r imr0 Base Address define r_isrl Base Address 1 define r_imrl Base Address 1 define r adsr Base Address 2 define r imr2 Base Address 2 define r eosr Base Address 2 define r bcr Base Address 2 define r accr Base Address 2 define r bsr Base Address 3 define r auxcr Base Address 3 define r isr2 Base Address 4 define r adr Base Address 4 define r spmr Base Address 5 define r spsr Base Address define r cptr Base Address define r ppr define r dir Base Address 5 6 Base Address 6 7 define r cdor Base Address 7 NAT9914 registers in 7210 mode define r7210 auxmr Base Address 5 isr0 bits define b intO 0x80 define b inti 0x40 define b bi 0x20 define b bo 0x10 define b end 0x08 define b spas 0x04 def
75. nsfers data faster and costs less TNT4882 The TNT4882 offers a faster interface to the GPIB The TNT4882 also has the fast HS488 transfer capabilities and internal FIFOs You can transfer up to 1 5 Mbytes s using a 488 1 handshake or up to 8 Mbytes s using the newer HS488 GPIB protocol Even though the TNT4882 also has integrated GPIB transceivers and is useful for large data transfers where speed is critical the TNT4882 has a 9914 mode Code written for the NAT9914 can be ported to the TNT4882 with few modifications Determining the Appropriate GPIB Specifications Command Hierarchy Standard Response Format Standard Program Command Set Software Firmware v amp Common Commands n Syntax Data Structures Hardware Handshaking Control Mechanical Electrical Standards Figure 1 Structure of the GPIB Standards IEEE 488 1 IEEE 488 1 specifies the handshaking basic control mechanical and electrical characteristics of the GPIB but does not specify the format of command strings or responses All GPIB devices must comply with 488 1 Both the NAT9914 and the TNT4882 handle all of the low level 488 1 requirements Because IEEE 488 1 has fewer requirements an IEEE 488 1 device is easier to implement than its 488 2 or the SCPI equivalent The example device discussed later in this application note is 488 1 compliant IEEE 488 2 All IEEE 488 2 devices are also 488 1 devices In addition to 488 1
76. ntroller places data on the DIO lines and waits at least T1 seconds 2 After the T1 delay the Talker waits until the Listener unasserts NRFD NRFD unasserted not Not Ready For Data indicates that the Listener can receive the data byte 3 The Talker asserts DAV to indicate that new data is valid on the DIO lines 4 The Listener asserts NRFD to signal a Not Ready Status Don t Send More Yet 5 When the Listener accepts the current byte by placing it in some internal buffer or by otherwise processing it the Listener unasserts NDAC 6 The Talker unasserts DAV 7 The Listener asserts NDAC then the Talker executes step 1 to begin transferring the next byte Physical and Electrical Specifications To achieve the GPIB s high data transfer rate you must limit the physical distance between devices and the number of devices on the bus This limitation is necessary because the GPIB is a transmission line system Any distance beyond the maximum allowable cable length as well as any excess GPIB device loads can surpass interface circuit drive capability The IEEE 488 standard dictates the following limits e The total length of all cables is less than or equal to 2 m times the number of connected devices up to a total of 20 m e No more than 15 devices are connected to each bus with at least two thirds of the devices powered on If you must exceed these limits you can purchase bus extenders and expanders Controllers Talkers a
77. od in a classroom setting the instructor and students would use a certain word to finish all com munication within the classroom As with the GPIB the instructor and students would define this method and the word used before any communication took place In the GPIB and in the classroom the termination signal is sent by using the normal data path data lines in GPIB or speech in the classroom EO Method The EOI method uses the GPIB EOI line which is separate from the eight data lines on the GPIB In the EOI method when the Talker sends the last byte of data in the transmission it sets the EOI line high to specify that the byte is the last byte to be sent The Listener monitors the EOI line and recognizes when there is no more data You must establish ahead of time whether the Talker will use the EOI method so you can correctly configure the Listener to watch the EOI line Students could use the EOI method in the classroom they would wave device cards in the air to signal when they have finished speaking This form of communication is separate from the method of sending data speech but the other Listeners can monitor this communication while they receive data hear the speech Count Method The count method uses neither the EOI line nor the EOS character In the count method the device that receives information specifies the number of bytes to read Through this method a listening device reads a specified amount of data and prevents t
78. one of the following values idle_state 1 reading_state 2 writing_state 3 u 8 GPIB state buffer variables index is an offset from the base address of the i o buffer io buffer is both the GPIB input and output buffer SE 81 u 8 index u 8 io buffer BUFFER SIZE isr0 byte and isrl byte hold data from the NAT9914 status registers which has not yet p been processed u 8 isr0_byte u 8 isrl byte void main DH 3 initialize device jsr _initialize device L2 L3 GPIBDEV5 66 DH i do i A all non GPIB device code goes in this loop i xu DH ifndef USING_INTERRUPTS route nat9914 interrupts S endif d while 1 tsx bra L2 Ll globl _initialize_device _initialize_device GPIBDEV5 82 PM Ko Initialization routines ie WEY void initialize device void initialization sequences for both the microcontroller and the NAT9914 P EE z initialize_microcontroller jsr _initialize microcontroller GPIBDEV5 86 DH E initialize software variables before the device begins accepting GPIB commands i 7 7 index 0 clra clrb stab index 82 GPIBDEV5 87 R GPIB_state idle_state ldab 1 stab _GPIB state GPIBDEV5 89 DH d initialize NAT9914 jsr _initialize NAT9914 cli GPIBDEV5 90 H asm cli tsx rts L5 globl initialize microcontroller initialize microcontroller GPIBDEV5
79. p b dcas handle DCAS int ldab isrl byte clra bitb 8 tsx beq 118 jsr handle DCAS int L18 tsx rti L11 globl handle DCAS int handle DCAS int GPIBDEV5 221 s vp H DH void handle DCAS int void This routine resets only the GPIB interface of the device and not the device itself Its primary use is recovering after an error on the GPIB If a GPIB error occurs and the device locks up or appears to hang the GPIB controller can issue the SDC or DCL command and place the device into its idle GPIB state clear its buffers and start over p 4 EP DH reinitialize variables and buffers i x index 0 clra clrb stab _index GPIBDEV5 222 GPIB state idle state ldab 1 stab _GPIB state GPIBDEV5 223 H outp r auxcr c rhdf ldab 2 stab 4227 GPIBDEV5 224 isr0 byte 0x00 clra clrb stab isr0 byte GPIBDEV5 225 i isrl byte 0x00 clra clrb stab Larl byte GPIBDEV5 229 d update serial poll response byte i Ri clear status byte bits b mav ldd 87 jsr clear status byte bits GPIBDEV5 237 b rsv z error_reading 87 error_writing error_unknown_command i Ves i x i outp r auxcr c nonvalid ldab 1 stab 4227 tsx rts L20 globl handle BI int handle BI int GPIBDEV5 255 p DH void handle BI int void The Byte In handler reads a byte from the NAT9914 an
80. pecific task A command does not return information A command might tell a device to generate voltage or set a configuration option A query requests information from the device A query might request the temperature or a voltage reading Command Set for the Example Device This example device parses the incoming data for an ASCII string beginning with either a VOLT query or TARE command With an expanded parsing routine this device could become 488 2 or SCPI compliant Designing the Hardware Your hardware will connect a microcontroller to a NAT9914 and the NAT9914 to the GPIB connector through two GPIB transceivers In this example the glue between the Motorola 68HC11 and the NAT9914 comes directly from the 68HC11 manual and the wiring between the NAT9914 and the transceivers comes directly from the NAT9914 data sheet A set of DIP switches are included so the user can select a GPIB address but otherwise the design is copied from the M68HC11 manual and the NAT9914 data sheet The Motorola 68HC11 microcontroller actually runs on an evaluation board connected to the NAT9914 board with a 50 pin ribbon cable The program TEST C checks the connection between the microcontroller and the NAT9914 TEST C writes to each address and alerts the user to errors in wiring Note the reverse order of the data lines entering the NAT9914 On the NAT9914 DO is the most significant bit of the data bus Schematic The following diagram shows the
81. pending 0 ldab o interrupt pending clra cpd 0 bne 113 TEST 314 F trigger logic analyzer 0x21 ldab 33 stab 4369 bra 114 L13 EST 317 i S else 2 trigger logic analyzer 0x22 ldab 34 stab 4369 L14 EST 3213 A H reset NAT9914 to not interfere with subsequent tests S outp imr0 0x00 clra clrb stab 4224 pulx rts L12 globl int handler int handler EST 330 EB clear a flag to indicate that the interrupt handler was called successfully p wy pragma interrupt handler int handler void int_handler E signal rest of program that the interrupt has been handled i 7 interrupt_pending 0 clra clrb 59 stab _interrupt_pending TEST 334 7 handle the interrupt by writing out some output in this case Oxaa i 7 outp cdor Oxaa ldab 170 stab 4231 rti L15 area memory abs org 0xf000 globl main main TEST 346 p endif DH p E Main program x Set the starting address pe RF pragma abs_address 0xF000 of the program void main L17 EST 34932 loop start p trigger_logic_analyzer 0x01 ldab 1 stab 4369 EST 35037 A tstl JSL TSE EST 3515 bst2 3 jsr Latz EST 35241 ESESNI 7 jsre 4 TSTS EST 333 tst4 jsr _tst4 EST 354 1 A ESTS ISE STI EST 35511 LStotc jsr _tst6 EST 356 A tst7 ISE ESET
82. r BASE ADDRESS 7 define cdor BASE ADDRESS 7 define tauxmr BASE ADDRESS 5 isr0 bits define b intO 0x80 define b intl 0x40 define b bi 0x20 define b bo 0x10 37 define define define define imr0 define define define define defin b end b spas B LG b mac bits b dma0 b_dmal b_bi_ie b_bo_ie b_end_i define define define isrl define define define define define define define define imrl b spas ie b rlc ie b mac ie bits b get b err b unc b apt b dcas b ma b srq b ifc bits defin defin b get i b err i define define define define define define adsr define define define define define define define define imr2 define define define define define define b unc ie b apt ie b dcas ie b ma ie b srq ie b ifc ie bits b rem BELG b_atn b_lpas b_tpas b_la b_ta b_ulpa bits b_glint b_stbo_ie b_nlen b_lloc_ie b_atni_ie b_cic_ie ber bits 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x08 0x04 0x01 38 define b_bcr_atn 0x80 define b_bcr_dav 0x40 define b_bcr_ndac 0x20 define b bcr nrfd 0x10 define b bcr eoi 0x08 define b bcr srq 0x04 define b bcr ifc 0x02 define b bcr ren
83. rd 0x1082 byte 64 byte 1 word 0x1083 byte 64 byte 0 blkb 3 area text globl tst3 bebo 45 TEST 90 p Test 3 check BCR by reading from a write to BSR i struct ck t3 d WT tauxmr 0x15 WT auxcr Oxlc reset chip A WT auxcr 0x80 reset chip 3 WT auxcr 0x00 reset chip L WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl P WT imrO 0x00 clear imr0 H WT auxcr 0x1 page in to bcr register z WT bcr 0x40 set DAV internal to the NAT9914 A RD bsr 0x40 read internal DAV signal 0 DH tst3 i 7 return testit t3 ldd t3 jsr _testit clra tsx rts L3 area data globl _t4 t byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 0 byte 2 word 0x1081 byte 0 byte 2 word 0x1080 byte 0 byte 2 46 0x1 byte 138 byte 2 0x1 byte 85 byte 1 0x1 byte 64 byte 0 blkb 3 area text globl _tst4 word 083 word 087 word 081 tst4 EST 111 B H test 4 check struct ck ISR1 with n WT tauxmr 0x15 E WT auxcr Oxlc s WT auxcr 0x80 E WT auxcr 0x00 S WT auxcr Oxle WT imr2 0x00 WT imr
84. requirements IEEE 488 2 specifies data formats for commands and responses The specification also standardizes error handling and status reporting and it requires all devices to include certain commands and optionally several more commands Designing a 488 2 device requires more complicated firmware but some end users find 488 2 devices easier to program The NAT9914 and TNT4882 both can be used in 488 2 compliant devices IEEE 488 2 will help a user if he has other 488 2 devices or if he is comfortable with 488 2 SCPI SCPI adds to the 488 2 specifications by defining a single command set for all instruments Many major instrument manufacturers make SCPI compliant devices For a complete line of oscilloscopes or other instruments with large command sets SCPI provides a seamless coherent interface while standardizing the command set Designing a Command Set Command Set Completeness Your command set should enable the user to control all functions of the device Any functionality available through the front panel should also be available remotely ASCII strings Devices generally use 7 bit ASCII strings ASCII strings are easy to read when debugging platform independent and almost universally accepted among GPIB instruments Capital letters are required by IEEE 488 2 and commonly used in 488 1 instruments Some devices also send 8 bit binary data in an IEEE specified format Commands and Queries A command tells the device to perform a s
85. shake Most GPIB devices hold off the trigger and device clear commands with an NDAC holdoff Some devices also perform a holdoff on the last byte in a message string and parse the message before releasing the holdoff Detecting GPIB Events GPIB events affecting the device are recorded in the ISRO ISR1 and ISR2 registers They give access to the current GPIB status of the device and latch GPIB information for the microcontroller The act of reading one of the ISR registers also clears it Firmware can either poll the ISR registers or ignore them until the NAT9914 interrupts Polling One way to detect GPIB activity is to periodically poll the ISR registers Most bits will not affect your device but the device firmware usually polls the BO BI END GET and DCAS bits This method is straightforward and does not have the overhead of interrupt calls Interrupts The NAT9914 can be configured to interrupt when any enabled ISR bit sets Note that by reading ISRO bits INTO and INT1 your program may be able to handle the interrupt slightly faster To configure interrupts for use on the NAT9914 set the IMR bits corresponding to the ISR conditions which will request an interrupt Then set the global interrupt bit in IMR2 In the example device interrupt vector points to route nat9914 interrupts and a Return from Interrupt instruction RTI replaces the Return from Subroutine instruction RTS at the end of route nat9914 interrupts route nat9914
86. t no interrupts 9914A is TADS clear ton TADS cleared 43 globl t2 SEZ H byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 0 byte 2 word 0x1081 byte 0 byte 2 word 0x1080 byte 0 byte 1 word 0x1084 byte 0 byte 2 word 0x1087 byte 170 byte 1 word 0x1084 byte 128 byte 0 blkb 3 area text globl _tst2 LSt2 EST 70 p Test 2 check ISR2 with CDOR struct ck t2 WT tauxmr 0x15 WT auxcr Oxlc reset chip WT auxcr 0x80 reset chip WT auxcr 0x00 reset chip WT auxcr Oxle page in to imr2 WT imr2 0x00 clear GLINT bit WT imrl 0x00 clear imrl WT imr0 0x00 clear imr0 RD isr2 0x00 all clear 44 WT cdor Oxaa set nba bit in isr2 by writing to cdor RD isr2 0x80 make sure nba bit is set 0 s tst2 i S return testit t2 ldd t2 jsr _testit clra tsx rts L2 area data globl t3 33 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 0 byte 2 word 0x1081 byte 0 byte 2 word 0x1080 byte 0 byte 2 word 0x1083 byte 31 byte 2 wo
87. te 0 byte 2 word 0x1080 byte 0 byte 2 word 0x1086 byte 170 byte 2 word 0x1083 byte 31 byte 2 word 0x1082 byte 136 byte 1 word 0x1086 byte 170 byte 0 blkb 3 area text globl _tst9 TEST 220 ps 4 test 9 check PPR by initiating a parallel poll struct ck t9 NI i WT tauxmr 0x15 switch to 9914 mode auxcr Oxlc reset chip 53 r auxcr 0x80 reset chip r auxcr 0x00 reset chip I auxcr Oxle page in to imr2 imr2 0x00 clear GLINT bit imrl 0x00 clear imrl imr0 0x00 clear imrO I ppr Oxaa fill the PPR with data T auxcr Oxlf page to BCR r bcr 0x88 set EOI and ATN high RD cptr Oxaa 0 tst9 i S return testit t9 ldd 4 t9 jsr testit clra tsx rts L9 area data globl t10 E104 byte 2 word 0x1085 byte 21 byte 2 word 0x1083 byte 28 byte 2 word 0x1083 byte 128 byte 2 word 0x1083 byte 0 byte 2 word 0x1083 byte 30 byte 2 word 0x1082 byte 0 byte 2 word 0x1081 byte 0 byte 2 word 0x1080 byte 0 byte 2 word 0x1080 byte 16 byte 2 word 0x1083 byte 138 54 byte 1 word 0x1080 byte 144 byte 2 word 0x1080 byte 0 byte 0 blkb 3 area text globl _tst10 ES D TEST 247 i DH
88. ted as a data message When ATN is asserted information on the bus is interpreted as a command message Attention ATN Notifies devices of current data type s asserted by Controller In Charge Controller ATN asserted Command messages ATN unasserted pp Listener s Data messages 15 Remote Enable REN The System Controller uses the REN line to put devices into a remote state Each device has its own remote local state capabilities The IEEE 488 standard requires a device to go into a remote programming state whenever the REN line is asserted and addressed to listen E oo Enables devices for remote programming Is asserted by System Controller End or Identify EO Some devices terminate their output data by using the EOI line A Talker asserts EOI along with the last byte of data A Listener stops reading data when the EOI is asserted More details of transfer termination are presented later This line is also used in parallel polling which will be discussed later End Or Identify EO EE te Signals end of data Signals the execution of a Parallel Poll s asserted by current Talker Service Request SRQ A device asserts the SRQ line at any time in order to notify the CIC that it needs service The SRQ line remains asserted until the device is serial polled The Controller must monitor SRQ poll the device and determine the type of service the device
89. the class and controls activity The GPIB works in a similar fashion the Controller bus controls when tasks are performed In the classroom a student must have permission to speak and on the GPIB no device can communicate unless it is addressed to talk on the bus A device may however need to communicate with the Controller before the Controller tells it to talk In a classroom students who have something to say usually raise their hands On the GPIB any device can assert the SRQ line which is separate from the data lines SRQ informs the Controller that a device needs attention The next section discusses how the SRQ line is asserted and how the device that asserts it is identified Serial Polling Devices This section investigates how the GPIB handles the SRQ line Remember the SRQ line purpose signaling to the Controller that a device needs attention When SRQ is asserted it is the responsibility of the Controller to determine who requested service by checking all devices individually Checking the devices individually is known as polling the devices The Controller can poll devices in two ways in serial or in parallel This appendix discusses serial polling Serial polling obtains specific information from a device When you serial poll the Controller sends a special com mand message Serial Poll Enable SPE to the device directing it to return its serial poll status byte The SPE message sets the IEEE 488 1 serial poll mode in the de
90. the remaining bits is device dependent 7 RQS 5 4 3 2 1 O Status Byte Register ESR and SRE Registers The IEEE 488 2 standard defines a set of commands for controlling the GPIB The standard also defines a new method of working with the SRQ line on the GPIB This section applies only to those GPIB devices that are IEEE 488 2 compatible If a device is only IEEE 488 1 compatible the previous section applies Status Byte Model for IEEE 488 2 IEEE 488 2 describes a scheme for status reporting This scheme is required for all IEEE 488 2 instruments With this scheme the Controller can obtain status information for every instrument in the system This scheme builds on and extends the IEEE 488 1 status byte shown in the above table Three bits of this status byte are defined The IEEE 488 2 standard defines the RQS bit like the IEEE 488 1 standard IEEE 488 2 adds the Event Status Bit ESB and the 24 Message Available MAV bit The manufacturer defines other bits The ROS bit indicates the device has requested service by asserting the SRQ line The ESB indicates that one of the standard events defined in the Standard Event Status Register has occurred By setting the corresponding bits in the Standard Event Status Enable Register you define which standard events will set the ESB The MAV bit indicates whether a message is available in the instrument output queue By setting the corresponding bits in the Service Requ
91. vice so when the device is addressed to talk it returns a single 8 bit status byte This serial poll status byte is different for each type of instrument except for one bit you must refer to the instrument user manual for information on the other bits Bit 6 hex 40 of any serial poll status byte indicates whether a device requested service by asserting the SRQ line The device uses the other seven bits of the status byte to specify why it needs attention After the Controller reads the status byte it sends another command message Serial Poll Disable SPD to the device The SPD message terminates the serial poll mode thus returning the device to its normal Talker Listener state Once a device requesting service is serial polled it usually unasserts the SRQ line 23 When a serial poll is conducted the following sequence of events occurs System Controller GPIB Device Se coos Se UNListen UNL Controller Listen Address Serial Poll Enable SPE m Generates Serial Poll Byte Device Talk Address Device Set as Talker Byle from Device Byte from Device Serial Poll Byte Returned Serial Poll Disable SPD Turns off Serial Poll Mode UNTalk UNT All Devices Figure A 7 Events During a Serial Poll Status Byte Model for IEEE 488 1 IEEE 488 1 defines only bit 6 the RQS bit of the serial poll status byte see the following table If a device is requesting service it sets ROS The meaning of
92. x BUFFER SIZE place the data byte on the output buffer x io buffer index data out index index 1 void parse_input_buffer parse the message and call the correct routine Also reset the buffer and set the device in idle state If the command just received is invalid send an error messag to the GPIB controller xD check ranges on variables EZ assert GPIB state idle state GPIB state reading state GPIB state writing state assert index gt 0 amp amp index lt BUFFER SIZE reset the state variables since the device now has stopped reading GPIB data index 0 GPIB state idle state isr0 byte isr0 byte amp b end parse the message in the input buffer XJ if io buffer 0 V amp amp io bufferl 1 0 amp amp io buffer 2 L amp amp io buffer 3 T amp amp io_buffer 4 read_voltage terminate the data string and request service now that the data is in the buffer gt output data to io buffer NEWLINE set status byte bits b mav b rsv else if io buffer 0 T amp amp 73 io buffer 1 io buffer 2 io buffer 3 adjust tare A 88 R amp amp I H else if the device received an unrecognized command send an error message set status byte bits b rsv error unknown command

local copy

Contents

Download Pdf Manuals

Related Search

Related Contents