Home

Freescale Semiconductor

1. Read CLK A23 A22 A21 A20 DIS CLKOSEL Write RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Figure 6 9 CLKO Select Register SIM_CLKOSR 6 5 7 1 Reserved Bits 15 10 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 7 2 Alternate GPIOB Peripheral Function for A23 A23 Bit 9 e 0 Peripheral output function of GPIOB7 is defined to be A23 e Peripheral output function of GPIOB7 is defined to be the oscillator clock MSTR OSC in Figure 3 4 6 5 7 3 Alternate GPIOB Peripheral Function for A22 A22 Bit 8 e 0 Peripheral output function of GPIOB6 is defined to be A22 e 1 Peripheral output function of GPIOB6 is defined to be SYS CLK2 6 5 7 4 Alternate GPIOB Peripheral Function for A21 A21 Bit 7 e 0 Peripheral output function of GPIOBS is defined to be A21 e 1 Peripheral output function of GPIOBS is defined to be SYS CLK 6 5 7 5 Alternate GPIOB Peripheral Function for A20 A20 Bit 6 e 0 Peripheral output function of GPIOB4 is defined to be A20 e 1 Peripheral output function of GPIOB4 is defined to be the prescaler clock FREF in Figure 3 4 6 5 7 6 Clockout Disable CLKDIS Bit 5 e 0 CLKOUT output is enabled and will output the signal indicated by CLKOSEL e 1 CLKOUT is tri stated 56F8357 Technical Data Rev 15 114 Freescale Semiconductor Preliminary Register Descriptions 6 5 7 7 CLockout S
2. Value Value Characteristic Comments Symbol Unit Notes 160 pin LQFP 160MAPBGA Junction to ambient Roa 38 5 39 90 C W 2 Natural convection Junction to ambient 1m sec Regma 35 4 46 8 C W 2 Junction to ambient Four layer board 2s2p RoJMA 33 TBD C W 1 2 Natural convection 2s2p Junction to ambient 1m sec Four layer board 2s2p RoJMA 31 5 TBD C W 1 2 2s2p Junction to case Roc 8 6 TBD C W 3 Junction to center of case Yo 0 8 TBD C W 4 5 I O pin power dissipation Pio User determined Ww Power dissipation Pp P p lpp X Vpp P yo Ww Maximum allowed Pp Pomax TJ TA ROJA WwW Theta JA determined on 2s2p test boards is frequently lower than would be observed in an application Determined on 2s2p ther mal test board Junction to ambient thermal resistance Theta JA Roja was simulated to be equivalent to the JEDEC specification JESD51 2 in a horizontal configuration in natural convection Theta JA was also simulated on a thermal test board with two internal planes 2s2p where s is the number of signal layers and p is the number of planes per JESD51 6 and JESD51 7 The correct name for Theta JA for forced convection or with the non single layer boards is Theta JMA Junction to case thermal resistance Theta JC Rgjc was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as
3. D 15 00BSC S E 15 00 BSC m METALIZED MARK FOR e 1 00 BSC 14 13 2 1 10 9 6 5 4 3 2 1 PIN TIDENTIFICATION S 0 50 BSC ra GR GR 3 GR Q 5 Q 6 6 6 4 9 6 0 o 0 0 06 B 0 6 8 ee c E Soo e A 00O O 0 0 0 0 0 6 e PA Z 030 Z us 9 6 9 9 4 1 e 9 0 e r Ae Z 4000 ee le d ri 0 0 0 442 n ni w 4000 00 06 06 A1 QO 0 15 Z 6 0 0 0 0 0 0 0 0 0 0 0 0 O Ik z La 0 0 0 0 0 0 0 0 0 0 0 0 0 DETAIL K E o o o e o o M ROTATED 90 CLOCKWISE 6 0 0 0o 0 0 0 0 0 0 0 0 O Ix AN OP 99999999 o9 oe 160x b e 0 30 Z Xx Y VIEW M M A 0 10 Z CASE 1268 01 ISSUE O DATE 04 06 98 Figure 11 3 160 pin MBGA Mechanical Information 56F8357 Technical Data Rev 15 Freescale Semiconductor 165 Preliminary 11 2 56F8157 Package and Pin Out Information This section contains package and pin out information for the 56F8157 This device comes in a 160 pin Low profile Quad Flat Pack LQFP Figure 11 4 shows the package outline for the 160 pin LQFP package Figure 11 5 shows the mechanical parameters for this package and Table 11 3 lists the pin out for the 160 pin LQFP Vpp io Vpp2 CLKO TXDO RXDO SCLK1 MOSI1 MISO1 ss1 Al A2 A3 A4 A5 Vcap4 Vpp_lo A6
4. PLL 6 hemm 3 4 ad 6 7 4 3 2 Fault Inputs AA PAB A A i A T Lp PDB CDBR 44 CDBW i PAM RW Control DES e Ss S A0 5 or GPIOA8 13 an XAB1 Exe E A6 7 or GPIOE2 3 8 24 001 128K x 16 Flash xz gee all A8 15 or GPIOAQ 7 2Kx16RAM ges t GPIOB0 3 A16 19 44 TEMP SENSH 8K x 16 Go System Bus 1 gt GPIOB4 A20 Boot Flash n 7 prescaler_clock Quadrature CDBR Jl Control Stc o E d a gt EIAS PIOB5 7 A21 23 A Decoder 0 or Data Memory 4 CDBW 4 38 clk0 3 Qui 4K x 16 Flash ES GPIOC 8K x 16 RAM S External Data 2 gt D0 6 or GPIOF9 15 yy ui Bus Switch 9 7 y D7 15 or GPIOFO 8 Quadrature S Decoder 1 or IPBus Bridge IPBB gt WR Ti Ee Peripheral RD Immer Bor RW IPRDB Bus Control 6 NM SUE SP11 or GPIOG Device Selects Control b gt i wis iun ut Quad Eis asta Time co Decoding DS C81 or GPIOD9 GPIOE See Table 2 2 for explanation Timer D or resets GPIOE de AA FlexCAN System SPIO or SCI or Scio or COP Interrupt Integration S Clock O 4 XTAL GPIOE GPIOD GPIOE Watchdog Controller o Module pa Generator E lt Q EXTAL A IRQA A IRQB CLKO CLKMODE 56F8357 56F8157 Block Diagram 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Table of Contents Part 1 Overview lehrt pm 6 Part 8 General Purpo
5. 7 SIM LSH ID 0 SIM R ONCE SW STOP WAIT_ CONTROL TW EBL RST DISABLE DISABLE SIM_ R 1 RSTSTS Fw SWR COPR EXTR POR R 2 SIM SCRO La FIELD R 3 SIM SCR1 FIELD W R 4 SIM SCR2 La FIELD R 5 SIM SCR3 La FIELD SIM MSH R 6 ID W R W R W 8 SIM PUDR Reserved SIM CLKOSR A A23 A22 A21 A20 CLKDIS CLKOSEL B SIM_GPS C3 C2 C1 co C SIM PCE ADCB ADOA cam DEC1 DECO TMRD TMRC TMRB TMRA scn SCIO PAM EN 1 1 1 1 1 1 1 1 1 1 1 D SIM_ISALH ISAL 23 22 E SIM_ISALL ISAL 21 6 S 2 2 S 3 S 0 232 m Reserved Figure 6 2 SIM Register Map Summary 6 5 1 SIM Control Register SIM CONTROL Base 0 6 5 4 3 2 1 0 Read EMI ONCE SW STOP_ WAIT_ Write MODE EBL RST DISABLE DISABLE RESET 0 0 0 0 0 0 0 Figure 6 3 SIM Control Register SIM_CONTROL 6 5 1 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 56F8357 Technical Data Rev 15 Freescale Semiconductor 109 Preliminary 6 5 1 2 EMI MODE EMI MODE Bit 6 This bit reflects the current non clocked state ofthe EMI MODE pin During reset this bit coupled with the EXTBOOT signal is used to initialize address bits 19 16 either as GPIO or as address These set
6. Prescaler Four Fouti2 Postscaler Post caler CLK 124870 LI epp ostscaler C x D 6 O E Si 2 Bus E m Bus Interface amp Control Ai iere z LL Lock LCK ET Detector Y Loss of Loss of Reference Reference Clock Interrupt Clock di Detector Figure 3 1 OCCS Block Diagram 3 2 External Clock Operation The system clock can be derived from an external crystal ceramic resonator or an external system clock signal To generate a reference frequency using the internal oscillator a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins 3 2 1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel resonant crystal resonator in the frequency range specified for the external crystal in Table 10 13 A recommended crystal oscillator circuit is shown in Figure 3 2 Follow the crystal supplier s recommendations when selecting a crystal since 56F8357 Technical Data Rev 15 Freescale Semiconductor 39 Preliminary crystal parameters determine the component values required to provide maximum stability and reliable start up The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start up stabilization time Crystal Frequency 4 8MHz optimized for 8MHz EXTAL XTAL EXTAL XTAL Sample External Crystal Parameters Rz Rz R 750
7. Figure 5 15 Fast Interrupt 0 Vector Address Low Register FIVALO 5 6 13 1 Fast Interrupt 0 Vector Address Low FIVALO Bits 15 0 The lower 16 bits of the vector address are used for Fast Interrupt 0 This register is combined with FIVAHO to form the 21 bit vector address for Fast Interrupt 0 defined in the FIMO register 5 6 14 Fast Interrupt 0 Vector Address High Register FIVAHO Base D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 16 Fast Interrupt 0 Vector Address High Register FIVAHO 5 6 14 1 Reserved Bits 15 5 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 14 2 Fast Interrupt 0 Vector Address High FIVAHO Bits 4 0 The upper five bits of the vector address are used for Fast Interrupt 0 This register is combined with FIVALO to form the 21 bit vector address for Fast Interrupt 0 defined in the FIMO register 5 6 15 Fast Interrupt 1 Match Register FIM1 Base E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 U 0 uU 0 uU FAST INTERRUPT 1 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 17 Fast Interrupt 1 Match Register FIM1 56F8357 Technical Data
8. Figure 5 10 Interrupt Priority Register IPR7 5 6 8 1 Timer A Channel 0 Interrupt Priority Level TMRAO IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 8 2 Timer B Channel 3 Interrupt Priority Level TMRB3 IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 92 Freescale Semiconductor Preliminary Register Descriptions 5 6 8 3 Timer B Channel 2 Interrupt Priority Level TMRB2 IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 10 IRQ is priority level 1 11 IRQ is priority level 2 5 6 8 4 Timer B Channel 1 Interrupt Priority Level TMRB1 IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled d
9. GPIO Port GPIO Bit ral Functional Signal Package Pin 0 Peripheral PhaseA1 TBO SCLK1 6 1 Peripheral PhaseB1 TB1 MOSI1 7 2 Peripheral Index TB2 MISO1 8 3 Peripheral Home TB31 SSI1 9 4 Peripheral PHASEAO TAO 155 GPIOC 5 Peripheral PHASEBO TA1 156 6 Peripheral Index0 TA2 157 7 Peripheral Home TA3 158 8 Peripheral ISAO 126 9 Peripheral ISA1 127 10 Peripheral ISA2 128 0 GPIO CS2 55 1 GPIO CS3 56 2 GPIO CS4 57 3 GPIO CS5 58 4 GPIO CS6 59 5 GPIO CS7 60 GPIOD 6 Peripheral TXD1 49 7 Peripheral RXD1 50 8 Peripheral PS CSO 53 9 Peripheral DS CS1 54 10 Peripheral ISBO 61 11 Peripheral ISB1 63 12 Peripheral ISB2 64 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 129 Table 8 3 GPIO External Signals Map Continued Pins in italics are NOT available in the 56F8157 device GPIO Port GPIO Bit Beatie Functional Signal Package Pin 0 Peripheral TXDO 4 1 Peripheral RXDO 5 2 Peripheral A6 17 3 Peripheral AT 18 4 Peripheral SCLKO 146 5 Peripheral MOSIO 148 6 Peripheral MISOO 147 GPIOE 7 Peripheral SS0 145 8 Peripheral TCO 133 9 Peripheral TC1 135 10 Peripheral TDO 129 11 Peripheral TD1 130 12 Peripheral TD2 131 13 Peripheral TD3 132 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 149 5 Peripheral D12 150 6 Peripheral D13 151 7 Peripheral D14 152 GPIOF 8 Peripheral D15 153
10. Base E 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Read ISAL 21 6 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 15 I O Short Address Location Low Register SIM_ISAL 6 5 10 2 Input Output Short Address Low ISAL 21 6 Bit 15 0 This field represents the lower 16 address bits of the hard coded I O short address 6 6 Clock Generation Overview The SIM uses an internal master clock from the OCCS CLKGEN module to produce the peripheral and system core and memory clocks The maximum master clock frequency is 120MHz Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz The SIM provides power modes Stop Wait and clock enables SIM_PCE register CLK_DIS ONCE_EBL to control which clocks are in operation The OCCS power modes and clock enables provide a flexible means to manage power consumption Power utilization can be minimized in several ways In the OCCS crystal oscillator and PLL may be shut down when not in use When the PLL is in use its prescaler and postscaler can be used to limit PLL and master clock frequency Power modes permit system and or peripheral clocks to be disabled when unused Clock enables provide the means to disable individual clocks Some peripherals provide further controls to disable unused subfunctions Refer to Part 3 On Chip Clock Synthesis OCCS and the 56F8300 Peri
11. M SE SNe est IO 56F8357 Sy Sy ey En Boe Y Ss Sy eS em EEN PHASEAO TAO GPIOC4 PHASEBO TA1 GPIOC5 aq NDEXO TA2 GPIOC6 HOMEO TA3 GPIOC7 SCLKO GPIOE4 MOSIO GPIOE5 MISOO GPIOE6 850 GPIOE7 SPHASEB TB1 MOSI1 GPIOC1 INDEX TB2 MISO1 GPIOC2 HOME TB3 SS1 GPIOC3 PWMAO 5 S SAO 2 GPIOC8 10 E AULTAO 3 PWMBO 5 Se ISBO 2 GPIOD10 12 FAULTBO 3 NAO 7 aq REF ANBO 7 Temp_Sense CAN_RX CAN_TX A A 4 A TCO 1 GPIOE8 9 TDO 3 GPIOE10 13 IRQA IRQB EXTBOOT EMI MODE RESET RSTO PHASEA1 TBO SCLK1 GPIOCO Introduction Quadrature Decoder 0 or Quad Timer A SPIO or GPIO Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA PWMB ADCA ADCB Temperature Sense Diode FlexCAN Quad Timer C and D or GPIO INTERRUPT PROGRAM CONTROL Figure 2 1 56F8357 Signals Identified by Functional Group 160 pin LQFP 1 Alternate pin functionality is shown in parenthesis pin direction type shown is the default functionality 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 17 Power Power Power Ground Ground Other Supply Ports PLL and Clock External Address Bus or GPIO External Data Bus External Bus Control SCI
12. e Two Serial Peripheral Interfaces SPIs both with configurable 4 pin port or eight additional GPIO lines SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B Inthe 56F8357 SPII can also be used as Quadrature Decoder 1 or Quad Timer B Inthe 56F8157 SPI1 can alternately be used only as GPIO e Computer Operating Properly COP Watchdog timer Two dedicated external interrupt pins Up to 76 General Purpose I O GPIO pins External reset input pin for hardware reset External reset output pin for system reset Integrated Low Voltage Interrupt Module e JTAG Enhanced On Chip Emulation OnCE for unobtrusive processor speed independent debugging e Software programmable Phase Lock Loop PLL based frequency synthesizer for the core clock 1 1 5 Energy Information e Fabricated in high density CMOS with 5V tolerant TTL compatible digital inputs e On board 3 3V down to 2 6V voltage regulator for powering internal logic and memories can be disabled e On chip regulators for digital and analog circuitry to lower cost and reduce noise e Wait and Stop modes available e ADC smart power management Each peripheral can be individually disabled to save power 1 2 Device Description The 56F8357 and 56F8157 are members of the 56800E core based family of controllers Each combines on a single chip the processing power of a Digital Signal Processor DSP and the functionality of a microcontroller with a flexible set of periph
13. 107 12 2 Electrical Design Considerations 171 6 5 Register Descriptions 108 12 3 Power Distribution and I O Ring 6 6 Clock Generation Overview 121 Implementation 172 6 7 Power Down Modes Overview 121 6 8 Stop and Wait Mode Disable Function 122 Part 13 Ordering Information 173 GO ROSS e g suing dota cede rr det And 123 Part 7 Security Features 123 7 1 Operation with Security Enabled 123 7 2 Flash Access Blocking Mechanisms 124 56F8357 Technical Data Rev 15 Freescale Semiconductor 5 Preliminary Part 1 Overview 1 1 56F8357 56F8157 Features 1 1 1 Core Efficient 16 bit 56800E family controller engine with dual Harvard architecture e Up to 60 Million Instructions Per Second MIPS at 60 MHz core frequency e Single cycle 16 x 16 bit parallel Multiplier Accumulator MAC e Four 36 bit accumulators including extension bits e Arithmetic and logic multi bit shifter e Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions e Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support e Software subroutine and interrupt stack with depth limited only by memory e JTAG EOnCE debug programming interface 1 1 2 Differences Bet
14. 11 Same operation as 10 6 5 2 SIM Reset Status Register SIM RSTSTS Bits in this register are set upon any system reset and are initialized only by a Power On Reset POR A reset other than POR will only set bits in the register bits are not cleared Only software should clear this register Base 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 9 U U 0 0 W 0 U SWR COPR EXTR POR Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 4 SIM Reset Status Register SIM RSTSTS 56F8357 Technical Data Rev 15 110 Freescale Semiconductor Preliminary Register Descriptions 6 5 2 1 Reserved Bits 15 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 2 2 Software Reset SWR Bit 5 When 1 this bit indicates that the previous reset occurred as a result of a software reset write to SW RST bit in the SIM CONTROL register This bit will be cleared by any hardware reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit will clear it 6 5 2 3 COP Reset COPR Bit 4 When 1 the COPR bit indicates the Computer Operating Properly COP timer generated reset has occurred This bit will be cleared by a Power On Reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit will clear it 6 5 2 4 External Reset EXTR B
15. A7 A8 A9 A10 A11 A12 A13 A14 A15 Vss D7 D8 D9 Vpp wo D10 GPIOBO GPIOB1 GPIOB2 GPIOB3 GPIOB4 PWMBO PWMB1 PWMB2 4 Orientation Mark N Pin 1 EMI MODE HOMEO INDEXO PHASEBO PHASEAO EXTBOOT Vss Vss ANB7 ANB6 ANB5 be 81 Na CO s ot e e ec Cl o x Wee cc E D oO e Cl e e E N o Oo o 29 82889a855EleBsaa8BBaSa2a sl5eganogas 2 0929 992 agz22000 amp Kx 0000009 99ulyt tt 5 8 2222na n tct aaaonaa gt weg ECKE 3 gt amp aaooo 000000 ES amp Figure 11 4 Top View 56F8157 160 Pin LQFP Package 56F8357 Technical Data Rev 15 ANB4 ANB3 ANB2 ANB1 ANBO VssA ADC Mona ADC VREFH VREFP VREFMID VREFN VREFLO NC ANA7 ANA6 ANAS ANA4 ANA3 ANA2 ANA1 ANAO CLKMODE RESET RSTO Vpp wo Vcap3 EXTAL XTAL VDDA OSC PLL O
16. EMI CSn EMI Chip Selects 2 pins SCI1 SCI1 2 pins EMI CSn EMI Chip Selects 3 pins PWMB current sense PWMB current sense E 14 14 2 pins SCIO SCIO 2 pins EMI Address pins EMI Address 4 pins SPIO SPIO 2 pins TMRC TMRC 4 pins Dedicated GPIO GPIO F 16 16 16 pins EMI Data EMI Data 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 127 Table 8 3 GPIO External Signals Map Pins in italics are NOT available in the 56F8157 device GPIO Port GPIO Bit M isset Functional Signal Package Pin 0 Peripheral A8 19 1 Peripheral A9 20 2 Peripheral A10 21 3 Peripheral A11 22 4 Peripheral A12 23 5 Peripheral A13 24 6 Peripheral A14 25 GPIOA 7 Peripheral A15 26 8 Peripheral AO 154 9 Peripheral A1 10 10 Peripheral A2 11 11 Peripheral A3 12 12 Peripheral A4 13 13 Peripheral A5 14 0 GPIO A16 33 1 GPIO A17 34 2 GPIO A18 35 GPIOB 3 GPIO A19 36 4 GPIO A20 Prescaler clock 37 5 GPIO A21 SYS CLK 46 6 GPIO A22 SYS CLK2 47 7 GPIO A23 Oscillator Clock 48 This is a function of the EMI MODE EXTBOOT and Flash security settings at reset 56F8357 Technical Data Rev 15 128 Freescale Semiconductor Preliminary Pins in italics are NOT available in the 56F8157 device Table 8 3 GPIO External Signals Map Continued Configuration
17. 10 m PWMBO 5 x ISBO 2 GPIOD10 12 FAULTBO 3 ANAO 7 N lt REF ANBO 7 E TCO 1 GPIOES 9 y GPIOE10 13 IRQA IRQB EXTBOOT EMI MODE RESET RSTO A Ad A 1 Alternate pin functionality is shown in parenthesis pin direction type shown is the default functionality 56F8357 Technical Data Rev 15 Quadrature Decoder 0 or Quad Timer A SPIO or GPIO SPI 1 or GPIO GPIO PWMB ADCA ADCB Quad Timer C or GPIO INTERRUPT PROGRAM CONTROL 18 Freescale Semiconductor Preliminary Signal Pins 2 2 Signal Pins After reset each pin is configured for its primary function listed first Any alternate functionality must be programmed Note Signals in italics are NOT available in the 56F8157 device Note The 160 Map Ball Grid Array is not available in the 56F8157 device If the State During Reset lists more than one state for a pin the first state is the actual reset state Other states show the reset condition of the alternate function which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral For example the AS GPIOAO pin shows that it is tri stated during reset If the GPIOA_PER is changed to select the GPIO function of the pin it will become an input if no other registers are changed Note LQFP Pin numbers and MBGA Ball
18. 12 A3 52 RD 92 VppA osc PLL 132 TD3 13 A4 53 PS 93 XTAL 133 TCO 14 A5 54 DS 94 EXTAL 134 Vpp io 15 VcAp4 55 GPIODO 95 VcAp3 135 TC1 16 Vpp io 56 GPIOD1 96 Vpp io 136 TRST 17 A6 57 GPIOD2 97 RSTO 137 TCK 18 A7 58 GPIOD3 98 RESET 138 TMS 19 A8 59 GPIOD4 99 CLKMODE 139 TDI 20 AQ 60 GPIOD5 100 ANAO 140 TDO 21 A10 61 ISBO 101 ANA1 141 Vpp1 22 A11 62 Vcap1 102 ANA2 142 CAN TX 23 A12 63 ISB1 103 ANA3 143 CAN RX 24 A13 64 ISB2 104 ANA4 144 Vcap2 25 A14 65 IRQA 105 ANA5 145 sso When the on chip regulator is disabled these four pins become 2 5V Vpp cong 56F8357 Technical Data Rev 15 160 Freescale Semiconductor Preliminary 56F8357 Package and Pin Out Information Table 11 1 56F8357 160 Pin LQFP Package Identification by Pin Number Continued Pin No as Pin No Signal Name Pin No Signal Name Pin No Signal Name 26 A15 66 IROB 106 ANA6 146 SCLKO 27 Vss 67 FAULTBO 107 ANA7 147 MISOO 28 D7 68 FAULTB1 108 TEMP_SENSE 148 MOSIO 29 D8 69 FAULTB2 109 VREFLO 149 D11 30 D9 70 DO 110 VREFN 150 D12 31 Von wo 71 D1 111 VREFMID 151 D13 32 D10 72 FAULTB3 112 VREFP 152 D14 33 GPIOBO 73 PWMAO 113 VREFH 153 D15 34 GPIOB1 74 Vss 114 VpDA ADC 154 AO 35 GPIOB2 75 PWMA1 115 VssA ADC 155 PHASEAO 36 GPIOB3 76 PWMA2 116 ANBO 156 PHASEBO 37 GPIOB4 77 Vpp wo 117 ANB1 157 INDEXO 38 PWMBO 78 PWMA3 118 ANB2 158 HOMEO 39 PWMB1 79 PWMA4 119 ANB3 159 EMI_M
19. 6 01 Output Voltage open drain Vop Pin Group 4 0 3 6 0 V Ambient Temperature Automotive TA 40 125 C Ambient Temperature Industrial Ta 40 105 C Junction Temperature Automotive Ty 40 150 C Junction Temperature Industrial Ty 40 125 C Storage Temperature Automotive TsTG 55 150 C Storage Temperature Industrial TsTG 55 150 C 1 If corresponding GPIO pin is configured as open drain Note Pins in italics are NOT available in the 56F8157 device Pin Group 1 TXDO 1 RXD0 1 SSO MISOO MOSIO Pin Group 2 PHASEAO PHASEA1 PHASEBO PHASEB1 INDEXO INDEX1 HOMEO HOME1 ISBO 2 ISA0 2 TD2 3 TC0 1 SCLKO Pin Group 3 RSTO TDO Pin Group 4 CAN_TX Pin Group 5 A0 5 D0 15 GPIODO 5 PS DS Pin Group 6 A6 15 GPIOBO 7 TDO 1 Pin Group 7 CLKO WR RD Pin Group 8 PWMAO 5 PWMBO 5 Pin Group 9 IRQA IRQB RESET EXTBOOT TRST TMS TDI CAN RX EMI MODE FAULTAO 3 FAULTBO 3 Pin Group 10 TCK Pin Group 11 XTAL EXTAL Pin Group 12 ANAO 7 ANBO 7 Pin Group 13 OCR DIS CLKMODE 56F8357 Technical Data Rev 15 132 Freescale Semiconductor Preliminary General Characteristics Table 10 2 56F8357 56F8157 ElectroStatic Discharge ESD Protection Characteristic Min Typ Max Unit ESD for Human Body Model HBM 2000 V ESD for Machine Model MM 200 V ESD for Charge Device Model CDM 500 V Table 10 3 Thermal Characteristics
20. For details see Part 6 5 8 FAULTA3 87 M14 Schmitt Input FAULTA3 This fault input pin is used for disabling selected Input pull up PWMA outputs in cases where fault conditions originate enabled off chip To deactivate the internal pull up resistor set the PWMA1 bit in the SIM PUDR register See Part 6 5 6 for details PWMBO 38 N1 Output In reset PWMBO 5 Six PWMB output pins output is PWMB1 39 P1 disabled pull up is PWMB2 40 N2 enabled PWMB3 43 N3 PWMB4 44 P2 PWMB5 45 M3 56F8357 Technical Data Rev 15 34 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset ISBO 61 N8 Schmitt Input ISBO 2 These three input current status pins are used for Input pull up top bottom pulse width correction in complementary channel enabled operation for PWMB GPIOD10 Schmitt Port D GPIO These GPIO pins can be individually Input programmed as input or output pins ISB1 63 L8 Output GPIOD11 At reset these pins default to ISB functionality ISB2 64 P8 To deactivate the internal pull up resistor clear the appropriate GPIOD12 bit of the GPIOD PUR register For details see Part 6 5 8 FAULTBO 67 N9 Schmitt Input FAULTBO 3 These four fault input pins are used for Input pull up disabling
21. Rev 15 Freescale Semiconductor 99 Preliminary 5 6 15 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 but cannot be modified by writing 5 6 15 2 Fast Interrupt 1 Vector Number FAST INTERRUPT 1 Bits 6 0 This value determines which IRQ will be a Fast Interrupt 1 Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first see Part 5 3 3 IRQs used as fast interrupts must be set to priority level 2 Unexpected results will occur if a fast interrupt vector is set to any other priority Fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt Fast interrupt 0 has priority over Fast Interrupt 1 To determine the vector number of each IRQ refer to Table 4 5 5 6 16 Fast Interrupt 1 Vector Address Low Register FIVAL1 Base F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 1 Write VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 18 Fast Interrupt 1 Vector Address Low Register FIVAL1 5 6 16 1 Fast Interrupt 1 Vector Address Low FIVAL1 Bits 15 0 The lower 16 bits of vector address are used for Fast Interrupt 1 This register is combined with FIVAHI to form the 21 bit vector add
22. TCK frequency of operation not fop DC SYS_CLK 4 MHz 10 19 using EOnCE TCK clock pulse width tow 50 z ns 10 19 TMS TDI data set up time tos 5 ns 10 20 TMS TDI data hold time ton 5 ns 10 20 TCK low to TDO data valid tov gt 30 ns 10 20 TRST assertion time trast 272 ns 10 21 1 TCK frequency of operation must be less than 1 8 the processor rate 2 T processor clock period nominally 1 60MHz 56F8357 Technical Data Rev 15 152 Freescale Semiconductor Preliminary JTAG Timing TCK Input Vu Vir Vin Mul Figure 10 19 Test Clock Input Timing Diagram TCK Input Input TDO Output Output Data Valid TDO f Output TDO Output Output Data Valid Figure 10 20 Test Access Port Timing Diagram TRST Input TRST Figure 10 21 TRST Timing Diagram 56F8357 Technical Data Rev 15 Freescale Semiconductor 153 Preliminary 10 16 Analog to Digital Converter ADC Parameters Table 10 24 ADC Parameters Characteristic Symbol Min Typ Max Unit Input voltages VADIN VREFL VREFH V Resolution Res 12 12 Bits Integral Non Linearity INL E 2 4 3 2 LSB Differential Non Linearity DNL 0 7 lt 1 LSB2 Monotonicity GUARANTEED ADC internal clock fapic 0 5 5 MHz Conversion range Rap VREFL VREFH V ADC channel power up time tADPU 5 6 16
23. They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 9 5 SCIO Transmitter Empty Interrupt Priority Level SCIO_XMIT IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 9 6 Timer A Channel 3 Interrupt Priority Level TMRA3 IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 11 IRQ is priority level 2 5 6 9 7 Timer A Channel 2 Interrupt Priority Level TMRA2 IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 95 Preliminary 5 6 9 8 Timer A Channel 1 Interrupt Priority Level TMRA1 IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They a
24. This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 4 2 GPIOE Interrupt Priority Level GPIOE IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 4 3 GPIOF Interrupt Priority Level GPIOF IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 4 4 FlexCAN Message Buffer Interrupt Priority Level FCMSGBUF IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 85 Preliminary 5 6 4 5 FlexCAN Wake Up Interrupt Priority Level FCWKUP IPL Bits 7 6 This field is used to set the i
25. clear bit 9 in the GPIOF PUR register D4 88 L14 GPIOF13 D5 89 L12 GPIOF14 D6 90 L11 GPIOF15 56F8357 Technical Data Rev 15 24 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Nama No Ball No Type During Signal Description Reset D7 28 K1 Input In reset Data Bus D7 D14 specify part of the data for external Output output is program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR D7 D15and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOFO Input Port F GPIO These eight GPIO pins can be individually Output programmed as input or output pins D8 29 K3 GPIOF1 At reset these pins default to data bus functionality D9 30 K2 To deactivate the internal pull up resistor clear the appropriate GPIOF2 GPIO bit in the GPIOF PUR register GPIOES 3 Ka Example GPIOFO clear bit 0 in the GPIOF_PUR register D11 149 A5 GPIOF4 D12 150 A4 GPIOF5 D13 151 B5 GPIOF6 D14 152 C4 GPIOF7 D15 153 A3 GPIOF8 RD 52 P5 Output In reset Read Enable RD is asserted during external memory read output is cycles When RD is asserted low pins DO D15 beco
26. corresponds to a functional group of pins See Table 2 2 to identify which pins can deactivate the internal pull up resistor Base 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 EMI 0 0 0 0 0 rie Fe PWMA1 CAN Mope RESET IRQ XBOOT PWMB PWMAO Cl CTRL SS JTAG CIE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 8 SIM Pull up Disable Register SIM_PUDR 56F8357 Technical Data Rev 15 112 Freescale Semiconductor Preliminary Register Descriptions 6 5 6 1 Reserved Bit 15 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 6 2 PWMA1 Bit 14 This bit controls the pull up resistors on the FAULTA3 pin 6 5 6 3 CAN Bit 13 This bit controls the pull up resistors on the CAN_RX pin 6 5 6 4 EMI_MODE Bit 12 This bit controls the pull up resistors on the EMI MODE pin 6 5 6 5 RESET Bit 11 This bit controls the pull up resistors on the RESET pin 6 5 6 6 IRQ Bit 10 This bit controls the pull up resistors on the IRQA and IRQB pins 6 5 67 XBOOT Bit 9 This bit controls the pull up resistors on the EXTBOOT pin 6 5 6 8 PWMB Bit 8 This bit controls the pull up resistors on the FAULTBO FAULTBI FAULTB2 and FAULTB3 pins 6 5 6 9 PWMA0 Bit 7 This bit controls the pull up resistors on the FAULTAO FAULTAI and FAULTA2 pins 6 5 6 10 Reserved Bit 6 This bit field is reserved or n
27. in the IO cells as a function of capacitive load In these cases TotalPower X Intercept Slope Cload frequency 10MHz where e Summation is performed over all output pins with capacitive loads TotalPower is expressed in mW e Cload is expressed in pF Because of the low duty cycle on most device pins power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate In this case power from these buses can be significant E the external static component reflects the effects of placing resistive loads on the outputs of the device Sum the total of all V R or IV to arrive at the resistive load contribution to power Assume V 0 5 for the purposes of these rough calculations For instance if there is a total of 8 PWM outputs driving 10mA into LEDs then P 8 5 01 40mW In previous discussions power consumption due to parasitics associated with pure input pins is ignored as it is assumed to be negligible 56F8357 Technical Data Rev 15 158 Freescale Semiconductor Preliminary 56F8357 Package and Pin Out Information Part 11 Packaging Note The 160 Map Ball Grid Array is not available in the 56F8157 device 11 1 56F8357 Package and Pin Out Information This section contains package and pin out information for the 56F8357 This device
28. 0 or GPIO SCI 1 or GPIO JTAG EOnCE Port When the on chip regulator is disabled these at GPIOB6 A22 SYS_CLK2 e GPIOB7 A23 oscillator clock iL be Me Vpp io VDDA OSC PLL VDDA ADC lt B YY YY VssA_ADC OCR_DIS gt Vcap1 Moar x Vpp1 amp Vpp2 CLKMODE EXTAL XTA CLKO mi AO A5 GPIOAS 13 mi A6 A7 GPIOE2 3 4 A8 A15 GPIOAO 7 m GPIOBO 3 A16 19 GPIOBA A20 prescaler clock GPIOB5 A21 SYS CLK DO D6 GPIOF9 15 Dz D15 GPIOFO 8 RD imi WR f PS CSO GPIODF8 gt a DS CS1 GPIOFD9 C GPIODO 5 CS2 7 pe gt TXDO GPIOEO RXDO GPIOE1 TXD1 GPIOD6 RXD1 GPIOD7 TCK gt TMS TDO gt TDI TRST m four pins become 2 5V Vop_core Figure 2 2 56F8157 Signals Identified by Functional Group 160 pin LQFP Ney E et aaa ES CO USS O E E Nes ass 56F8157 Sey ey E ER Sk eke eS Ses ES ey Ao PHASEAO TAO GPIOC4 PHASEBO TA1 GPIOC5 INDEXO TA2 GPIOC6 HOMEO TA3 GPIOC7 SCLKO GPIOE4 MOSIO GPIOE5 MISOO GPIOE6 850 GPIOE7 SCHU GPIOCO _ MOSI1 GPIOC1 _ MISO1 GPIOC2 51 GPIOC3 GPIOC8
29. 149 10 11 Quad Timer Timing Table 10 19 Timer Timing 2 Characteristic Symbol Min Max Unit See Figure Timer input period Pin 2T 6 ns 10 14 Timer input high low period PinHL 1T 3 ns 10 14 Timer output period Pour 1T 3 mE ns 10 14 Timer output high low period Boma 0 5T 3 ns 10 14 1 In the formulas listed T the clock cycle For 60MHz operation T 16 67ns 2 Parameters listed are guaranteed by design meme NR e e Laf Pin gt PiNHL 4 PiNHL fe gt ra Pout gt PouTHL gt lt POUTHL Figure 10 14 Timer Timing 10 12 Quadrature Decoder Timing gt Table 10 20 Quadrature Decoder Timing 2 Characteristic Symbol Min Max Unit See Figure Quadrature input period Pin 4T 12 ns 10 15 Quadrature input high low period Put 27 6 ns 10 15 Quadrature phase period Dou 1T 3 ns 10 15 1 In the formulas listed T the clock cycle For 60MHz operation T 16 67ns 2 Parameters listed are guaranteed by design 56F8357 Technical Data Rev 15 150 Freescale Semiconductor Preliminary Serial Communication Interface SCI Timing Pph Pen Pen Pen ka ka Phase A Input PHL E P gt IN PHL Phase B P Input HE Pin PHL Figure 10 15 Quadrature Decoder Timing 10 1
30. 3 External Clock Source The recommended method of connecting an external clock is given in Figure 3 4 The external clock source is connected to XTAL and the EXTAL pin is grounded When using an external clock source set the OCCS_COHL bit high as well XTAL EXTAL Note When using an external clocking source with XTAL EXTAL this configuration the input CLKMODE should be high and the COHL bit in the OSCTL register External Vss should be set to 1 Clock Figure 3 4 Connecting an External Clock Signal 3 3 Registers When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual use the register definitions without the internal Relaxation Oscillator since the 56F8357 56F8157 do NOT contain this oscillator Part 4 Memory Map 4 1 Introduction The 56F8357 and 56F8157 devices are 16 bit motor control chips based on the 56800E core These parts use a Harvard style architecture with two independent memory spaces for Data and Program On chip RAM and Flash memory are used in both spaces This chapter provides memory maps for Program Address Space including the Interrupt Vector Table Data Address Space including the EOnCE Memory and Peripheral Memory Maps On chip memory sizes for each device are summarized in Table 4 1 Flash memories restrictions are identified in the Use Restrictions column of Table 4 1 Note Data Flash and Program RAM are NOT available on the 56F8157 device Tab
31. 3 Security High Half Register FMSECL 4 Security Low Half Register Reserved Reserved FMPROT 10 Protection Register Banked FMPROTB FMUSTAT 11 13 Protection Boot Register Banked User Status Register Banked FMCMD 14 Command Register Banked Reserved FMOPT 0 1A Reserved 16 Bit Information Option Register 0 Hot temperature ADC reading of Temperature Sensor value set during factory test FMOPT 1 1B 16 Bit Information Option Register 1 Not used FMOPT 2 1C 16 Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor value set during factory test 56F8357 Technical Data Rev 15 70 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map FC_BASE 00 F800 FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMCR 0 Module Configuration Register FCCTLO 3 Control Register 0 Register FCCTL1 4 Control Register 1 Register FCTMR 5 Free Running Timer Register FCMAXMB 6 Maximum Message Buffer Configuration Register FCRXGMASK_H 8 Receive Global Mask High Register FCRXGMASK_L 9 Receive Global Mask Low Register FCRX14MASK_H A Receive Buffer 14 Mask High Register FCRX14MASK_L B Receive Buffer
32. 4 Interrupt Disable INT_DIS Bit 5 This bit allows all interrupts to be disabled 0 Normal operation default e Ir All interrupts disabled 5 6 30 5 Reserved Bit 4 This bit field is reserved or not implemented It is read as 1 and cannot be modified by writing 5 6 30 6 IRQB State Pin IRQB STATE Bit 3 This read only bit reflects the state of the external IRQB pin 5 6 30 7 IRQA State Pin IRQA STATE Bit 2 This read only bit reflects the state of the external IRQA pin 5 6 30 8 IRQB Edge Pin IRQB Edg Bit 1 This bit controls whether the external IRQB interrupt is edge or level sensitive During Stop and Wait modes it is automatically level sensitive e 0 IRQB interrupt is a low level sensitive default e 1 IRQB interrupt is falling edge sensitive 56F8357 Technical Data Rev 15 104 Freescale Semiconductor Preliminary Resets 5 6 30 9 IRQA Edge Pin IRQA Edg Bit 0 This bit controls whether the external IRQA interrupt is edge or level sensitive During Stop and Wait modes it is automatically level sensitive e 0 IRQA interrupt is a low level sensitive default e 1 RQA interrupt is falling edge sensitive 5 7 Resets 5 7 1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted The reset vector will be presented until the second rising clock edge after RESET is released 5 7 2 ITCN After Reset After reset all of the
33. 50 STL AVES ug WWS gt 0 0 052 0 75 DCAOE MDAR 1 N A since device captures data before it deasserts RD 2 If RWSS RWSH 0 and the chip select does not change then RD does not deassert during back to back reads 3 Substitute BMDAR for MDAR if there is no chip select 4 MDAR is active in this calculation only when the chip select changes 56F8357 Technical Data Rev 15 Freescale Semiconductor 143 Preliminary 10 9 Reset Stop Wait Mode Select and Interrupt Timing Table 10 17 Reset Stop Wait Mode Select and Interrupt Timing er Typical Typical Characteristic Symbol Min Max Unit See Figure RESET Assertion to Address Data and traz 21 ns 10 5 Control Signals High Impedance Minimum RESET Assertion Duration tra 16T ns 10 5 RESET Deassertion to First External Address tRDA 63T 64T ns 10 5 Output Edge sensitive Interrupt Request Width tirw 1 5T ns 10 6 IRQA IRQB Assertion to External Data tibm 18T ns 10 7 Memory Access Out Valid caused by first instruction execution in the interrupt service tiom FAST 14T routine IRQA IRQB Assertion to General Purpose tic 18T ns 10 7 Output Valid caused by first instruction execution in the interrupt service routine tig FAST 14T Delay from IRQA Assertion exiting Wait tto tir 22T ns 10 8 External Data Memory Access tip FAST 18T Delay from IRQA Assertion to External Data tr ns 10 9 Memory Access ex
34. 56800E core when an interrupt of sufficient priority exists and to what address to jump in order to service this interrupt 5 2 Features The ITCN module design includes these distinctive features Programmable priority levels for each IRQ Two programmable Fast Interrupts e Notification to SIM module to restart clocks out of Wait and Stop modes Drives initial address on the address bus after reset 5 3 Functional Description The Interrupt Controller is a slave on the IPBus It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels excluding certain interrupts of fixed priority Next all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level Within a given priority level 0 is the highest priority while number 81 is the lowest 5 3 1 Normal Interrupt Handling Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority an interrupt vector address is generated Normal interrupt handling concatenates the VBA and the vector number to determine the vector address In this way an offset is generated into the vector table for each interrupt 56F8357 Technical Data Rev 15 76 Freescale Semiconductor Preliminary 5 3 2 Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be Interrupt Nest
35. 56F8357 Technical Data Rev 15 36 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Name Pin No Ball No Type State During Reset Signal Description TDO GPIOE10 129 B10 TD1 GPIOE11 130 A10 TD2 GPIOE12 131 D10 TD3 GPIOE13 132 E10 Schmitt Input Output Schmitt Input Output Input pull up enabled TDO 3 Timer D Channels 0 1 2 and 3 Port E GPIO These GPIO pins can be individually programmed as input or output pins At reset these pins default to Timer functionality To deactivate the internal pull up resistor clear the appropriate bit of the GPIOE_PUR register See Part 6 5 6 for details IRQA IRQB 65 66 K9 P9 Schmitt Input Input pull up enabled External Interrupt Request A and B The IRQA and IRQB inputs are asynchronous external interrupt requests during Stop and Wait mode operation During other operating modes they are synchronized external interrupt requests which indicate an external device is requesting service They can be programmed to be level sensitive or negative edge triggered To deactivate the internal pull up resistor set the IRQ bit in the SIM_PUDR register See Part 6 5 6 for details RESET 98 J14 Schmitt Input Input pull up enabled Reset This input is a
36. A Channel 1 TMRA 66 0 2 P 84 Timer A Channel 2 TMRA 67 0 2 P 86 Timer A Channel 3 SCIO 68 0 2 P 88 SCI 0 Transmitter Empty SCIO 69 0 2 P 8A SCI 0 Transmitter Idle SCIO 71 0 2 P 8E SCI 0 Receiver Error SCIO 72 0 2 P 90 SCI 0 Receiver Full ADCB 73 0 2 P 92 ADC B Conversion Compete End of Scan 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 45 Table 4 5 Interrupt Vector Table Contents Continued Peripheral A Se pee ee Interrupt Function ADCA 74 0 2 P 94 ADC A Conversion Complete End of Scan ADCB 75 0 2 P 96 ADC B Zero Crossing or Limit Error ADCA 76 0 2 P 98 ADC A Zero Crossing or Limit Error PWMB 77 0 2 P 9A Reload PWM B PWMA 78 0 2 P 9C Reload PWM A PWMB 79 0 2 P 9E PWMA 80 0 2 P A0 core 81 1 P A2 SW Interrupt LP 1 Two words are allocated for each entry in the vector table This does not allow the full address range to be referenced from the vector table providing only 19 bits of address 2 If the VBA is set to 0200 or VBA 0000 for Mode 1 EMI MODE 0 the first two locations of the vector table are the chip reset addresses therefore these locations are not interrupt vectors 4 4 Data Map Note Data Flash is NOT available on the 56F8157 device Table 4 6 Data Memory Map Begin End 522 Address EX 20 X FF FFFF EOnCE X FF FFOO 256 locations allo
37. BDC and BLDC Brush and Brushless DC motors SRM and VRM Switched and Variable Reluctance Motors and stepper motors The PWM incorporates fault protection and cycle by cycle current limiting with sufficient output drive capability to directly drive standard optoisolators A smoke inhibit write once protection feature for key parameters is also included A patented PWM waveform distortion correction circuit is also provided Each PWM is double buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16 The PWM module provides reference outputs to synchronize the Analog to Digital Converters through two channels of Quad Timer C The 56F8157 incorporates a Quadrature Decoder capable of capturing all four transitions on the two phase inputs permitting generation of a number proportional to actual position Speed computation capabilities accommodate both fast and slow moving shafts An integrated watchdog timer in the Quadrature Decoder can be programmed with a time out value to alert when no shaft motion is detected Each input is filtered to ensure only true transitions are recorded This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces SCIs two Serial Peripheral Interfaces SPIs and two Quad Timers Any of these interfaces can be used as General Purpose Input Outputs GPIOs if that function is not required An internal i
38. Counter Register DEC1_REVH 6 Revolution Hold Register DEC1_UPOS 7 Upper Position Counter Register DEC1_LPOS 8 Lower Position Counter Register DEC1_UPOSH 9 Upper Position Hold Register DEC1_LPOSH A Lower Position Hold Register DEC1_UIR B Upper Initialization Register DEC1_LIR C Lower Initialization Register DEC1_IMR D Input Monitor Register Table 4 19 Interrupt Control Registers Address Map ITCN_BASE 00 F1A0 Register Acronym Address Offset Register Description IPRO 0 Interrupt Priority Register 0 IPR 1 1 Interrupt Priority Register 1 IPR 2 2 Interrupt Priority Register 2 IPR 3 3 Interrupt Priority Register 3 IPR 4 4 Interrupt Priority Register 4 IPR 5 5 Interrupt Priority Register 5 IPR6 6 Interrupt Priority Register 6 IPR 7 7 Interrupt Priority Register 7 IPR 8 8 Interrupt Priority Register 8 IPR9 9 Interrupt Priority Register 9 VBA A Vector Base Address Register FIMO B Fast Interrupt Match Register 0 FIVALO C Fast Interrupt Vector Address Low 0 Register FIVAHO D Fast Interrupt Vector Address High O Register 56F8357 Technical Data Rev 15 60 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 19 Interrupt Control Registers Address Map Continued ITCN_BASE 00 F1A0 Register Acronym Address Offset Register Description FIM1 E Fast Interrupt Mat
39. IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 3 2 Flash Memory Command Complete Priority Level FMCC IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 3 3 Flash Memory Error Interrupt Priority Level FMERR IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 3 4 PLL Loss of Lock Interrupt Priority Level LOCK IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 It is disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 83 Preliminary 5 6 3 5 Low Voltage Detector Interrupt Priority Level LVI IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priori
40. ITCN registers are in their default states This means all interrupts are disabled except the core IRQs with fixed priorities e Illegal Instruction e SW Interrupt 3 e HW Stack Overflow e Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels 56F8357 Technical Data Rev 15 Freescale Semiconductor 105 Preliminary Part 6 System Integration Module SIM 6 1 Overview The SIM module is a system catchall for the glue logic that ties together the system on chip It controls distribution of resets and clocks and provides a number of control features The system integration module is responsible for the following functions Reset sequencing Clock generation amp distribution Stop Wait control Pull up Enables for Selected Peripherals System status registers Registers for software access to the JTAG ID of the chip Enforcing Flash security These are discussed in more detail in the sections that follow 6 2 Features The SIM has the following features Flash security feature prevents unauthorized access to code data contained in on chip Flash memory Power saving clock gating for peripheral Three power modes Run Wait Stop to control power utilization Stop mode shuts down 56800E core system clock peripheral clock and PLL operation Stop mode entry can optionally disable PLL and Oscillator low
41. KQ CLKMODE 0 i Note If the operating temperature range is limited to below 85 C 105 C junction then R 10 Meg Q CL1 CL2 Figure 3 2 Connecting to a Crystal Oscillator Note The OCCS COHL bit must be set to 1 when a crystal oscillator is used The reset condition on the OCCS COHL bit is 0 Please see the COHL bit in the Oscillator Control OSCTL register discussed in the 56F8300 Peripheral User Manual 3 2 2 Ceramic Resonator Default It is also possible to drive the internal oscillator with a ceramic resonator assuming the overall system design can tolerate the reduced signal integrity A typical ceramic resonator circuit is shown in Figure 3 3 Refer to the supplier s recommendations when selecting a ceramic resonator and associated components The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins Resonator Frequency 4 8MHz optimized for 8MHz 2 Terminal 3 Terminal EXTAL XTAL EXTAL XTAL Sample External Ceramic Resonator Parameters R 750 KQ Rz Rz L JE CL1 CL2 CLKMODE 0 C1 C2 Figure 3 3 Connecting a Ceramic Resonator Note The OCCS_COHL bit must be set to 0 when a ceramic resonator is used The reset condition on the OCCS COHL bit is 0 Please see the COHL bit in the Oscillator Control OSCTL register discussed in the 56F8300 Peripheral User Manual 56F8357 Technical Data Rev 15 40 Freescale Semiconductor Preliminary Registers 3 2
42. O Vector Address Low Register 5 6 13 FIVAHO D Fast Interrupt 0 Vector Address High Register 5 6 14 FIM1 E Fast Interrupt 1 Match Register 5 6 15 FIVAL1 F Fast Interrupt 1 Vector Address Low Register 5 6 16 FIVAH1 10 Fast Interrupt 1 Vector Address High Register 5 6 17 IRQPO 11 IRQ Pending Register 0 5 6 18 IRQP1 12 IRQ Pending Register 1 5 6 19 IRQP2 13 IRQ Pending Register 2 5 6 20 IRQP3 14 IRQ Pending Register 3 5 6 21 IRQP4 15 IRQ Pending Register 4 5 6 22 IRQP5 16 IRQ Pending Register 5 5 6 23 ICTL 1D Interrupt Control Register 5 6 30 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 79 Reserved Figure 5 2 ITCN Register Map Summary 56F8357 Technical Data Rev 15 Add Register Offset Name 12 11 10 R 0 IPRO Lr BKPT UOIPL STPCNT IPL R 1 PRI Lr TX REGIPL TRBUFIPL R 2 IPR2 L FMCBEIPL FMCCIPL FMERR IPL IRQB IPL IRQA IPL R GPIOD GPIOE GPIOF 3 ra LT A da Ge FCERRIPL FCBOFF IPL R SPI1_RCV GPIOA GPIOB GPIOC 4 IPR4 Lr SPlo RCVIIPL SPI1_XMIT IPL ish ac ipt B ss prs P Jpect_xiraipt DECI HIRO IPL SCH RCV scii RERR IPL SCH TDL IPL SCH SMIT IPL
43. Otherwise it is tied to ground For details see Table 4 4 Note When this pin is tied low the customer boot software should disable the internal pull up resistor by setting the XBOOT bit of the SIM_PUDR see Part 6 5 6 EMI_MODE 159 B2 Schmitt Input External Memory Mode This input is tied to Vpp in order to Input pull up enable an extra four address lines for a total of 20 address enabled lines out of reset This function is also affected by EXTBOOT and the Flash security mode For details see Table 4 4 If a 20 bit address bus is not desired then this pin is tied to ground Note When this pin is tied low the customer boot software should disable the internal pull up resistor by setting the EMI MODE bit of the SIM PUDR see Part 6 5 6 56F8357 Technical Data Rev 15 38 Freescale Semiconductor Preliminary Introduction Part 3 On Chip Clock Synthesis OCCS 3 1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS The material contained here identifies the specific features of the OCCS design Figure 3 1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 Peripheral User Manual CLKMODE XTAL 1 BIS Crystal Gier OSC RTL E Prescaler CLK SYS_CLK2 Source to SIM PLLCID PLLDB PLLCOD H e PLL Tm
44. RESET 0 0 o 1fo o o o 0 0 0 1 1 1 0 0 Figure 5 26 ITCN Control Register ICTL 56F8357 Technical Data Rev 15 Freescale Semiconductor 103 Preliminary 5 6 30 1 Interrupt INT Bit 15 This read only bit reflects the state of the interrupt to the 56800E core 0 No interrupt is being sent to the 56800E core e 1 An interrupt is being sent to the 56800E core 5 6 30 2 Interrupt Priority Level IPIC Bits 14 13 These read only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken This field is only updated when the 56800E core jumps to a new interrupt service routine Note Nested interrupts may cause this field to be updated before the original interrupt service routine can read it e 00 Required nested exception priority levels are 0 1 2 or 3 01 Required nested exception priority levels are 1 2 or 3 e 10 Required nested exception priority levels are 2 or 3 e 11 Required nested exception priority level is 3 5 6 30 3 Vector Number Vector Address Bus VAB Bits 12 6 This read only field shows the vector number VAB 7 1 used at the time the last IRQ was taken This field is only updated when the 56800E core jumps to a new interrupt service routine Note Nested interrupts may cause this field to be updated before the original interrupt service routine can read it 5 6 30
45. SPIO_XMIT IPL W E IPL e a R 6 IPRe Lr TMRCOIPL TMRD3IPL TMRD2IPL TMRD1IPL TMRDOIPL DECO XIRQ IPL DECO_HIRQ IPL R 7 per Lr TMRAOIPL TMRB3IPL TMRBZIPL TMRBIIPL TMRBOIPL TMRC3IPL TMRC2IPL TMRC1 IPL R 8 IPRS SCIO_ROVIPL sco re RN SCIO TIDLIPL SCIO XMITIPL TMRA3IPL TMRA2IPL TMRA1IPL R PWMA RL 9 reg kel PWMAFIPL PWMBFIPL iX PWMB RLIPL ADCA ZC IPL ABCB_ZCIPL ADCA CCIPL ADCB CC IPL R VECTOR BASE ADDRESS A VBA W R 8 veao 7 FAST INTERRUPT 0 R FAST INTERRUPT 0 C FIVALO Le VECTOR ADDRESS LOW R FAST INTERRUPT 0 D PARO Ho VECTOR ADDRESS HIGH R E rum ke FAST INTERRUPT 1 R FAST INTERRUPT 1 SF FIVAL1 vo VECTOR ADDRESS LOW RENS 0 0 0 Kabes 0 0 0 0 0 FAST INTERRUPT 4 R PENDING 16 2 IC W R PENDING 32 17 12 IRQP4 82 17 W R PENDING 48 33 13 IRQP2 ee W R PENDING 64 49 14 IRQP3 64 43 W R PENDING 80 65 15 IRQP4 W Reserved 80 Freescale Semiconductor Preliminary Register Descriptions 5 6 1 Interrupt Priority Register 0 IPRO Base 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 3 Interrupt Priority Register 0 IPRO 5 6 1 1 Reserved Bits 15 14 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 1 2 EOnCE Breakpoint Unit 0 Interrupt Priority Level BKPT UO IPL Bits13 12 Th
46. Supply Voltage VppA osc PLL 3 3 3 3 6 V Internal Logic Core Supply Voltage Vpp coRE OCR DIS is High 2 25 2 5 2 75 V Device Clock Frequency FSYSCLK 0 60 MHz Input High Voltage digital Vu Pin Groups 2 5 5 V 1 2 5 6 9 10 Input High Voltage analog VIHA Pin Group 13 2 VppatO 3 Input High Voltage XTAL EXTAL Vinc Pin Group11 Vopa 0 8 Vppa 0 3 XTAL is not driven by an external clock Input high voltage XTAL EXTAL Vinc Pin Group 11 2 VppA 0 3 V XTAL is driven by an external clock Input Low Voltage Vi Pin Groups 1 2 5 0 3 m 0 8 V 6 9 10 11 13 Output High Source Current lou Pin Groups 1 2 3 m 4 mA Vou 24V Voy min Pin Groups 5 6 7 8 Pin Groups 8 12 Output Low Sink Current len Pin Groups 4 mA VoL 0 4V VoL max 1 2 3 4 14 Pin Groups 5 6 7 8 Pin Group 8 12 Ambient Operating Temperature Ta 40 125 C Automotive Ambient Operating Temperature Ta 40 105 C Industrial Flash Endurance Automotive Ne TA 40 C to 10 000 Cycles Program Erase Cycles 125 C Flash Endurance Industrial Ne TA 40 C to 10 000 Cycles Program Erase Cycles 105 C Flash Data Retention Tr Ty lt 85 C avg 15 Years Total chip source or sink current cannot exceed 200mA See Pin Groups in Table 10 1 56F8357 Technical Data Rev 15 134 Freescale Semiconductor Preliminary 10 2 DC Electrical Characteristics DC Electrical Characteris
47. TMRA2 LOAD 23 Load Register TMRA2 HOLD 24 Hold Register TMRA2 CNTR 25 Counter Register TMRA2 CTRL 26 Control Register TMRA2 SCR 27 Status and Control Register TMRA2 CMPLD1 28 Comparator Load Register 1 TMRA2 CMPLD2 29 Comparator Load Register 2 TMRA2 COMSCR 2A Comparator Status and Control Register TMRA3 CMP1 30 Compare Register 1 TMRA3 CMP2 31 Compare Register 2 TMRA3 CAP 32 Capture Register TMRA3 LOAD 33 Load Register TMRA3 HOLD 34 Hold Register TMRA3 CNTR 35 Counter Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 11 Quad Timer A Registers Address Map Continued TMRA_BASE 00 F040 Register Acronym Address Offset Register Description TMRA3_CTRL 36 Control Register TMRA3_SCR 37 Status and Control Register TMRA3_CMPLD1 38 Comparator Load Register 1 TMRA3_CMPLD2 39 Comparator Load Register 2 TMRA3_COMSCR 3A Comparator Status and Control Register Table 4 12 Quad Timer B Registers Address Map TMRB_BASE 00 F080 Quad Timer B is NOT available in the 56F8157 device Register Acronym Address Offset Register Description TMRBO CMP1 0 Compare Register 1 TMRBO CMP2 1 Compare Register 2 TMRBO CAP 2 Capture Register TMRBO LOAD 3 Load Register TMRBO HOLD 4 Hold Register TMRBO CNTR 5 Counter Register TMRBO CTRL
48. TMRC1_CTRL 16 Control Register TMRC1_SCR 17 Status and Control Register TMRC1_CMPLD1 18 Comparator Load Register 1 TMRC1_CMPLD2 19 Comparator Load Register 2 TMRC1_COMSCR 1A Comparator Status and Control Register Reserved TMRC2 CMP1 20 Compare Register 1 TMRC2 CMP2 21 Compare Register 2 TMRC2 CAP 22 Capture Register TMRC2 LOAD 23 Load Register TMRC2 HOLD 24 Hold Register TMRC2 CNTR 25 Counter Register TMRC2 CTRL 26 Control Register TMRC2 SCR 27 Status and Control Register TMRC2 CMPLD1 28 Comparator Load Register 1 TMRC2 CMPLD2 29 Comparator Load Register 2 TMRC2 COMSCR 2A Comparator Status and Control Register TMRC3 CMP1 30 Compare Register 1 TMRC3 CMP2 31 Compare Register 2 TMRC3 CAP 32 Capture Register TMRC3 LOAD 33 Load Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 55 Table 4 13 Quad Timer C Registers Address Map Continued TMRC_BASE 00 FOCO Register Acronym Address Offset Register Description TMRC3_HOLD 34 Hold Register TMRC3_CNTR 35 Counter Register TMRC3_CTRL 36 Control Register TMRC3_SCR 37 Status and Control Register TMRC3_CMPLD1 38 Comparator Load Register 1 TMRC3_CMPLD2 39 Comparator Load Register 2 TMRC3_COMSCR 3A Comparator Status and Control Register Table 4 14 Quad Timer D Registers Address Map TMRD_BASE 00 F100 Quad T
49. bits are set to make them falling edge sensitive This is because there is no clock available to detect the falling edge A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode The FlexCAN module can wake the device from Stop mode and a reset will do just that or IROA and IRQB can wake it up 56F8357 Technical Data Rev 15 78 Freescale Semiconductor Preliminary Register Descriptions 5 6 Register Descriptions A register address is the sum of a base address and an address offset The base address is defined at the system level and the address offset is defined at the module level The ITCN peripheral has 24 registers Table 5 3 ITCN Register Summary ITCN_BASE 00 F1A0 SC Base Address Register Name Section Location IPRO 0 Interrupt Priority Register 0 5 6 1 IPR1 1 Interrupt Priority Register 1 5 6 2 IPR2 2 Interrupt Priority Register 2 5 6 3 IPR3 3 Interrupt Priority Register 3 5 6 4 IPR4 4 Interrupt Priority Register 4 5 6 5 IPR5 5 Interrupt Priority Register 5 5 6 6 IPR6 6 Interrupt Priority Register 6 5 6 7 IPR7 7 Interrupt Priority Register 7 5 6 8 IPR8 8 Interrupt Priority Register 8 5 6 9 IPR9 9 Interrupt Priority Register 9 5 6 10 VBA SA Vector Base Address Register 5 6 11 FIMO B Fast Interrupt O Match Register 5 6 12 FIVALO c Fast Interrupt
50. bits 256 x 16 bits Please see 56F8300 Peripheral User Manual for additional Flash information 4 6 EOnCE Memory Map Table 4 8 EOnCE Memory Map Address Register Acronym Register Name X FF FF8A OESCR External Signal Control Register X FF FF8bE OBCNTR Breakpoint Unit 0 Counter X FF FF90 OBMSK 32 bits Breakpoint 1 Unit 0 Mask Register X FF FF91 Breakpoint 1 Unit 0 Mask Register X FF FF92 OBAR2 32 bits Breakpoint 2 Unit 0 Address Register X FF FF93 Breakpoint 2 Unit 0 Address Register X FF FF94 OBARI1 24 bits Breakpoint 1 Unit 0 Address Register X FF FF95 Breakpoint 1 Unit 0 Address Register X FF FF96 OBCR 24 bits Breakpoint Unit 0 Control Register X FF FF97 Breakpoint Unit 0 Control Register X FF FF98 OTB 21 24 bits stage Trace Buffer Register Stages X FF FF99 Trace Buffer Register Stages X FF FF9A OTBPR 8 bits Trace Buffer Pointer Register X FF FF9B OTBCR Trace Buffer Control Register X FF FF9C OBASE 8 bits Peripheral Base Address Register X FF FF9D OSR Status Register X FF FF9E OSCNTR 24 bits Instruction Step Counter X FF FF9F Instruction Step Counter X FF FFAO OCR bits Control Register X FF FFFC OCLSR 8 bits Core Lock Unlock Status Register 56F8357 Technical Data Rev 15 48 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 8 EOnCE Memo
51. by Pin Number Continued Pin No E Pin No Signal Name Pin No Signal Name Pin No Signal Name 26 A15 66 IROB 106 ANA6 146 SCLKO 27 Vss 67 FAULTBO 107 ANA7 147 MISOO 28 D7 68 FAULTB1 108 NC 148 MOSIO 29 D8 69 FAULTB2 109 VREFLO 149 D11 30 D9 70 DO 110 VREFN 150 D12 31 Von wo 71 D1 111 VREFMID 151 D13 32 D10 72 FAULTB3 112 VREFP 152 D14 33 GPIOBO 73 NC 113 VREFH 153 D15 34 GPIOB1 74 Vss 114 VpDA ADC 154 AO 35 GPIOB2 75 NC 115 VssA_ ADC 155 PHASEAO 36 GPIOB3 76 NC 116 ANBO 156 PHASEBO 37 GPIOB4 77 Von wo 117 ANB1 157 INDEXO 38 PWMBO 78 NC 118 ANB2 158 HOMEO 39 PWMB1 79 NC 119 ANB3 159 EMI_MODE 40 PWMB2 80 Vss 120 ANB4 160 Vss 56F8357 Technical Data Rev 15 168 Freescale Semiconductor Preliminary 56F8157 Package and Pin Out Information 160X 0 20 C A B D n LN L M SECTION G G o NOTES 1 DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y 14 5M 1994 3 DATUMS A B AND D TO BE DETERMINED Ak WHERE THE LEADS EXIT THE PLASTIC BODY AT DATUM PLANE H 4 DIMENSIONS D1 AND El DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25mm PER SIDE DIMENSIONS D1 AND El ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH 5 DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD 0 20 H A B D W
52. clear bit O in the GPIOE_PUR register RXDO 5 D2 Input Input Receive Data SCIO receive data input pull up GPIOE1 Input enabled Port E GPIO This GPIO pin can be individually Output programmed as an input or output pin After reset the default state is SCI output To deactivate the internal pull up resistor clear bit 1 in the GPIOE PUR register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 27 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset TXD1 49 P4 Output In reset Transmit Data SCI1 transmit data output output is GPIOD6 Input disabled Port D GPIO This GPIO pin can be individually Output pull up is programmed as an input or output pin enabled After reset the default state is SCI output To deactivate the internal pull up resistor clear bit 6 in the GPIOD_PUR register RXD1 50 N5 Input Input Receive Data SCI1 receive data input pull up GPIOD7 Input enabled Port D GPIO This GPIO pin can be individually Output programmed as an input or output pin After reset the default state is SCI input To deactivate the internal pull up resistor clear bit 7 in the GPIOD PUR register TCK 137 D8 Schmitt Input pulled Test Clock Input This input pin provides a gated clock to Input low synchronize the test logic and shift serial data to
53. comes in a 160 pin Low profile Quad Flat Pack LQFP and 160 Map Ball Grid Array Figure 11 1 shows the package lay out for the 160 pin LQFP and Figure 11 2 for the160 Map Ball Grid Array Figure 11 5 shows the mechanical parameters for the LQFP package and Figure 11 3 for the MBGA Table 11 1 lists the pin out for the 160 pin LQFP and Table 11 2 lists the pin out for the 160 MBGA a oo ps 9 f Q m A GER o S o 9 el D D D wtanw DN Die tziz To 2x aaaasa za 00588 SEO SE ECE ESSE SZ3R S8s SG 2SHS SAB ABS SBE S22 Vpp io A Orientation Mark i Naa Vpp2 ANB3 CLKO
54. direct hardware reset on the processor When RESET is asserted low the device is initialized and placed in the reset state A Schmitt trigger input is used for noise immunity When the RESET pin is deasserted the initial chip operating mode is latched from the EXTBOOT pin The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks To ensure complete hardware reset RESET and TRST should be asserted together The only exception occurs ina debugging environment when a hardware device reset is required and the JTAG EOnCE module must not be reset In this case assert RESET but do not assert TRST Note The internal Power On Reset will assert on initial power up To deactivate the internal pull up resistor set the RESET bit in the SIM_PUDR register See Part 6 5 6 for details RSTO 97 J13 Output Output Reset Output This output reflects the internal reset state of the chip 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 37 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin arate Name No Ball No Type During Signal Description Reset EXTBOOT 124 B11 Schmitt Input External Boot This input is tied to Vpp to force the device Input pull up to boot from off chip memory assuming that the on chip Flash enabled memory is not in a secure state
55. e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 97 Preliminary 5 6 10 8 ADC B Conversion Complete Interrupt Priority Level ADCB_CC IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 0 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 11 Vector Base Address Register VBA Base A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read VECTOR BASE ADDRESS Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 13 Vector Base Address Register VBA 5 6 11 1 Reserved Bits 15 13 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 11 2 Interrupt Vector Base Address VECTOR BASE ADDRESS Bits 12 0 The contents of this register determine the location of the Vector Address Table The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus VAB 20 0 The lower eight bits are determined based upon the highest priority interrupt They are then appended onto VBA before presenting the full VAB to the 56800E core see Part 5 3 1 for details 5 6 12 Fast Interrupt 0 Match Register FIMO Base B 15 14 13 12
56. in a unified Up to two Quadrature Decoders C efficient architecture Optional on chip regulator FlexCAN module Two Serial Communication Interfaces SCIs Access up to 4MB of off chip program and 32MB of data memory Chip Select Logic for glueless interface to ROM and Up to two Serial Peripheral Interfaces SPIs SRAM 256KB of Program Flash Up to four general purpose Quad Timers 4KB of Program RAM Computer Operating Properly COP Watchdog JTAG Enhanced On Chip Emulation OnCETM for unobtrusive real time debugging Up to 76 GPIO lines 160 pin LQFP Package and 60MAPBGA 8KB of Data Flash 16KB of Data RAM 16KB Boot Flash Up to two 6 channel PWM modules Four 4 channel 12 bit ADCs RSTO EMI MODE HEED Confi ti Vep Vcap Vss Mona Neen E enges RESET Exraoor 5 2 Ar 2 5V regulator PWM Outputs PWMA est Digital Reg Analog Reg Current Sense Inputs or GPIOC Port 16 Bit rin Voltage 56800E Core SES Fault Inputs Data ALU 16 x 16 36 gt 36 Bit MAC Three 16 bit Input Registers Four 36 bit Accumulators Bit Manipulation Unit Program Controller and PWM Outputs Address Generation Unit PWMB Hardware Looping Unit Current Sense Inputs or GPIOD Peripherals Quad
57. pA Bias Current low drive mode IBIASL Gg 80 110 LA Quiescent Current power down mode Ipp 0 1 uA 10 8 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices Figure 10 4 shows sample timing and parameters that are detailed in Table 10 16 The timing of each parameter consists of both a fixed delay portion and a clock related portion as well as user controlled wait states The equation t D P M W should be used to determine the actual time of each parameter The terms in this equation are defined as t Parameter delay time Fixed portion of the delay due to on chip path delays P Period of the system clock which determines the execution rate of the part De when the device is operating at 60MHz P 16 67 ns M Fixed portion of a clock period inherent in the design this number is adjusted to account for possible derating of clock duty cycle W Sum of the applicable wait state controls The Wait State Controls column of Table 10 16 shows the applicable controls for each parameter and the EMI chapter of the 56F8300 Peripheral User Manual details what each wait state field controls When using the XTAL clock input directly as the chip clock without prescaling ZSRC selects prescaler clock and prescaler set to 1 the EMI quadrature clock is generated using both edges of the EXTAL clock input In this situation only parameter valu
58. priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 2 Timer D Channel 3 Interrupt Priority Level TMRD3 IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8357 Technical Data Rev 15 90 Freescale Semiconductor Preliminary Register Descriptions 5 6 7 3 Timer D Channel 2 Interrupt Priority Level TMRD2 IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 7 4 Timer D Channel 1 Interrupt Priority Level TMRD1 IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 7 5 Timer D Channel 0 Interrupt Priority Level TMRDO IPL Bits 7 6 This field is used
59. selected PWMB outputs in cases where fault FAULTB1 68 L9 enabled conditions originate off chip FAULTB2 69 L10 To deactivate the internal pull up resistor set the PWMB bit in FAULTB3 72 P11 the SIM_PUDR register For details see Part 6 5 8 ANAO 100 G13 Input Analog ANAO 3 Analog inputs to ADC A channel 0 Input ANA1 101 H13 ANA2 102 G12 ANA3 103 F13 ANA4 104 F12 Input Analog ANA4 7 Analog inputs to ADC A channel 1 Input ANA5 105 H14 ANA6 106 G14 ANA7 107 E13 VREFH 113 D14 Input Analog Vnern Analog Reference Voltage High VreFH must be less Input than or equal to Vppa Apc VreFP 112 D13 Input Analog Vrerp VrermiD amp Vreen Internal pins for voltage reference Output Input which are brought off chip so they can be bypassed Connect VREFMID 111 E14 Output to a 0 1uF low ESR capacitor VREFN 110 F14 VREFLO 109 E12 Input Analog VrerLO Analog Reference Voltage Low This should Input normally be connected to a low noise Vss 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 35 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Nama No Ball No Type During Signal Description Reset ANBO 116 C13 Input Analog ANBO 3 Analog inputs to ADC B channel 0 Input ANB1 117 B14 ANB2 118 C12 ANB3 119 B13 ANB4 120 A14 Input Analog ANBA 7 Analog inputs to ADC B channel 1 In
60. the case temperature The basic cold plate measurement technique is described by MIL STD 883D Method 1012 1 This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink Thermal Characterization Parameter Psi JT jy is the resistance from junction to reference point thermocouple on top cen ter of case as defined in JESD51 2 Y y is a useful value to use to estimate junction temperature in steady state customer envi ronments Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipaion of other components on the board and board thermal resistance 6 See Part 12 1 for more details on thermal design considerations 7 TJ Junction temperature TA Ambient temperature TBD numbers will be available late Q4 2005 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Note The 56F8157 device is guaranteed to 40MHz and specified to meet Industrial requirements only Table 10 4 Recommended Operating Conditions VREFLO OV Vss Vssa Apc OV Vppa Vopa Apc Vppa osc PLL Characteristic Symbol Notes Min Typ Max Unit Supply voltage Vpp io 3 3 3 3 6 V ADC Supply Voltage VppaA ADC VREFH must be 3 3 3 3 6 V VREFH less than or equal to VppA ApC Oscillator PLL
61. the internally JTAG EOnCE port The pin is connected internally to a pull down resistor TMS 138 A8 Schmitt Input pulled Test Mode Select Input This input pin is used to sequence Input high the JTAG TAP controller s state machine It is sampled on the internally rising edge of TCK and has an on chip pull up resistor To deactivate the internal pull up resistor set the JTAG bit in the SIM PUDR register Note Always tie the TMS pin to Vpp through a 2 2K resistor TDI 139 B8 Schmitt Input pulled Test Data Input This input pin provides a serial input data Input high stream to the JTAG EOnCE port It is sampled on the rising internally edge of TCK and has an on chip pull up resistor To deactivate the internal pull up resistor set the JTAG bit in the SIM PUDR register TDO 140 D7 Output In reset Test Data Output This tri stateable output pin provides a output is serial output data stream from the JTAG EOnCE port It is disabled driven in the shift IR and shift DR controller states and pull up is changes on the falling edge of TCK enabled 56F8357 Technical Data Rev 15 28 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin plate Nama No Ball No Type During Signal Description Reset TRST 136 D9 Schmitt Input pulled Test Reset As an input a low signal on this pi
62. the charge on C1 and C2 are averaged via S3 with the result that a single ended analog input is switched to a differential voltage centered about VREfH VreFH 2 The switches switch on every cycle of the ADC clock open one half ADC clock closed one half ADC clock Note that there are additional capacitances associated with the analog input pad routing etc but these do not filter into the S H output voltage as S1 provides isolation during the charge sharing phase One aspect of this circuit is that there is an on going input current which is a function of the analog input voltage Vggr and the ADC clock frequency Analog Input G 4 gt ANS S3 S H DN e P O NR 2 KE ee dk C1 C2 1pF Parasitic capacitance due to package pin to pin and pin to package base coupling 1 8pf Parasitic capacitance due to the chip bond pad ESD protection devices and signal routing 2 04pf Equivalent resistance for the ESD isolation resistor and the channel select mux 500 ohms Sampling capacitor at the sample and hold circuit Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time 1pf Pon Figure 10 23 Equivalent Circuit for A D Loading 10 18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application Power consumption is given by the following equation Total power A intern
63. 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 U 0 0 0 uU 0 uU U FAST INTERRUPT 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 14 Fast Interrupt 0 Match Register FIMO 5 6 12 1 Reserved Bits 15 7 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 12 2 Fast Interrupt 0 Vector Number FAST INTERRUPT 0 Bits 6 0 This value determines which IRQ will be a Fast Interrupt 0 Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first see Part 5 3 3 IRQs used as fast interrupts must be set to priority level 2 Unexpected results will occur if a fast interrupt vector is set to any other priority Fast interrupts automatically become the 56F8357 Technical Data Rev 15 98 Freescale Semiconductor Preliminary Register Descriptions highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt Fast interrupt 0 has priority over Fast Interrupt 1 To determine the vector number of each IRQ refer to Table 4 5 5 6 13 Fast Interrupt 0 Vector Address Low Register FIVALO Base C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read FAST INTERRUPT 0 Write VECTOR ADDRESS LOW RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
64. 14 Mask Low Register FCRX15MASK_H C Receive Buffer 15 Mask High Register FCRX15MASK_L D Receive Buffer 15 Mask Low Register FCSTATUS 10 Error and Status Register FCIMASK1 11 Interrupt Masks 1 Register FCIFLAG1 12 Interrupt Flags 1 Register FCR T_ERROR_CNTRS 13 Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMBO_CONTROL 40 Message Buffer 0 Control Status Register FCMBO_ID_HIGH 41 Message Buffer 0 ID High Register FCMBO_ID_LOW 42 Message Buffer 0 ID Low Register FCMBO_DATA 43 Message Buffer 0 Data Register FCMBO_DATA 44 Message Buffer 0 Data Register FCMBO_DATA 45 Message Buffer 0 Data Register FCMBO_DATA 46 Message Buffer 0 Data Register FCMSB1_CONTROL 48 Message Buffer 1 Control Status Register FCMSB1_ID_HIGH 49 Message Buffer 1 ID High Register 56F8357 Technical Data Rev 15 Freescale Semiconductor 71 Preliminary Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMSB1_ID_LOW 4A Message Buffer 1 ID Low Register FCMB1_DATA 4B Message Buffer 1 Data Register FCMB1_DATA 4C Message Buffer 1 Data Register FCMB1_DATA 4D Message Buffer 1 Data Register FCMB1_DATA 4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL 50 Message Buffer 2 Control Status Register FCMB2_ID_HIGH 51 Message Buffer 2 ID High Register
65. 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 80 65 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 24 IRQ Pending 4 Register IRQP4 5 6 22 1 IRQ Pending PENDING Bits 80 65 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 56F8357 Technical Data Rev 15 102 Freescale Semiconductor Preliminary Register Descriptions 5 6 23 IRQ Pending 5 Register IRQP5 Base 16 Figure 5 25 IRQ Pending Register 5 IRQP5 5 6 23 1 Reserved Bits 96 82 This bit field is reserved or not implemented The bits are read as 1 and cannot be modified by writing 5 6 23 2 IRQ Pending PENDING Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number e 1 No IRQ pending for this vector number 5 6 24 Reserved Base 17 5 6 25 Reserved Base 18 5 6 26 Reserved Base 19 5 6 27 Reserved Base 1A 5 6 28 Reserved Base 1B 5 6 29 Reserved Base 1C 5 6 30 ITCN Control Register ICTL Base 1D 15 14 1 WZ dol 9 e 6G 5 4 3 2 1 0 Read INT IPIC VAB IRQB STATE IRQASTATE RGB IRGA INT_DIS IRQB ROA Write EDG EDG
66. 3 Serial Communication Interface SCI Timing Table 10 21 SCI Timing Characteristic Symbol Min Max Unit See Figure Baud Rate BR fuax 16 Mbps RXD Pulse Width RXDpw 0 965 BR 1 04 BR ns 10 16 TXD Pulse Width TXDpw 0 965 BR 1 04 BR ns 10 17 1 Parameters listed are guaranteed by design 2 fmax is the frequency of operation of the system clock ZCLK in MHz which is 60MHz for the 56F8357 device and 40MHz for the 56F8157 device 3 The RXD pin in SCIO is named RXDO and the RXD pin in SCI1 is named RXD1 4 The TXD pin in SCIO is named TXDO and the TXD pin in SCI1 is named TXD1 RXD SCI receive data pin Input RXDpw Figure 10 16 RXD Pulse Width TXD SCI receive data pin Input TXDpw Figure 10 17 TXD Pulse Width 56F8357 Technical Data Rev 15 Freescale Semiconductor 151 Preliminary 10 14 Controller Area Network CAN Timing Note CAN is not available in the 56F8157 device Table 10 22 CAN Timing Characteristic Symbol Min Max Unit See Figure Baud Rate BRean Z 1 Mbps X Bus Wake Up detection T WAKEUP 5 us 10 18 1 Parameters listed are guaranteed by design CAN RX CAN receive data pin Input T wAKEUP Figure 10 18 Bus Wakeup Detection 10 15 JTAG Timing Table 10 23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation fop DC SYS CLK 8 MHz 10 19 using EOnCE
67. 3 in the GPIOC_PUR register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 33 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset PWMAO 73 M11 Output In reset PWMAO 5 These are six PWMA outputs output is PWMA1 75 P12 disabled pull up is PWMA2 76 N11 enabled PWMA3 78 M12 PWMA4 79 P13 PWMA5 81 N12 ISAO 126 A11 Schmitt Input ISAO 2 These three input current status pins are used for Input pull up top bottom pulse width correction in complementary channel enabled operation for PWMA GPIOC8 Schmitt Port C GPIO These GPIO pins can be individually Input programmed as input or output pins ISA1 127 C11 Output GPIOC9 In the 56F8357 these pins default to ISA functionality after reset ISA2 128 D11 GPIOC10 In the 56F8157 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear the appropriate bit of the GPIOC_PUR register For details see Part 6 5 8 FAULTAO 82 N13 Schmitt Input FAULTAO 2 These three fault input pins are used for Input pull up disabling selected PWMA outputs in cases where fault FAULTA1 84 N14 enabled conditions originate off chip FAULTA2 85 M13 To deactivate the internal pull up resistor set the PWMAO bit in the SIM_PUDR register
68. 56F8357 Technical Data Rev 15 Freescale Semiconductor 117 Preliminary Base C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Wi EMI ADCB ADCA CAN DEC1 DECO TMRD TMRC TMRB TMHRA SCI1 SCIO SPI1 SPIO PWMB PWMA rite RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 12 Peripheral Clock Enable Register SIM PCE 6 5 9 1 External Memory Interface Enable EMI Bit 15 Each bit controls clocks to the indicated peripheral e l Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 2 Analog to Digital Converter B Enable ADCB Bit 14 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 3 Analog to Digital Converter A Enable ADCA Bit 13 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 4 FlexCAN Enable CAN Bit 12 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 5 Decoder 1 Enable DEC1 Bit 11 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled
69. 6 2 When GPIOC 3 0 are programmed to operate as peripheral I O then the choice between decoder timer and SPI inputs outputs is made in the SIM GPS register and in conjunction with the Quad Timer Status and Control Registers SCR The default state is for the peripheral function of GPIOC 3 0 to be programmed as decoder functions This can be changed by altering the appropriate controls in the indicated registers 56F8357 Technical Data Rev 15 Freescale Semiconductor 115 Preliminary Quad Timer Controlled GPIO Controlled GPIOC_PER Register SIM_ GPS Register SPI Controlled 0 1 0 1 0 Pad Control Figure 6 10 Overall Control of Pads Using SIM_GPS Control Table 6 2 Control of Pads Using SIM_GPS Control 1 Control Registers SI e Be Pin Function A a a ES ZS Comments l rb EDO e 8 EE O O Su a a O O SE GPIO Input 0 0 EN GPIO Output 0 1 Quad Timer Input 1 0 0 See the Switch Matrix for Inputs to the Timer Quad Decoder Input 2 table in the 56F8300 Peripheral User Manual Quad Ti Output for the definition of the timer inputs based on ec eee 1 0 1 the Quad Decoder Mode configuration Quad Decoder Input SPI input 1 1 See SPI controls for determining the direction SPI output of each of the SPI pins 1 This applies to the four pins that serve as Quad Decoder Quad Timer SPI GPIOC functions A separate set o
70. 6 5 9 6 Decoder 0 Enable DECO Bit 10 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 56F8357 Technical Data Rev 15 118 Freescale Semiconductor Preliminary Register Descriptions 6 5 9 7 Quad Timer D Enable TMRD Bit 9 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 8 Quad Timer C Enable TMRC Bit 8 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 9 Quad Timer B Enable TMRB Bit 7 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 10 Quad Timer A Enable TMRA Bit 6 Each bit controls clocks to the indicated peripheral e Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 11 Serial Communications Interface 1 Enable SCI1 Bit 5 Each bit controls clocks to the indicated peripheral e Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 12 Serial Communications Interface 0 Enable SCIO Bit 4 Each bit controls clocks to the indicated peripheral e 1 Clo
71. 6 Control Register TMRBO SCR 7 Status and Control Register TMRBO CMPLD1 8 Comparator Load Register 1 TMRBO CMPLD2 9 Comparator Load Register 2 TMRBO COMSCR A Comparator Status and Control Register TMRB1 CMP1 10 Compare Register 1 TMRB1 CMP2 11 Compare Register 2 TMRB1 CAP 12 Capture Register TMRB1 LOAD 13 Load Register TMRB1 HOLD 14 Hold Register TMRB1 CNTR 15 Counter Register TMRB1 CTRL 16 Control Register TMRB1 SCR 17 Status and Control Register TMRB1 CMPLD1 18 Comparator Load Register 1 TMRB1 CMPLD2 19 Comparator Load Register 2 TMRB1 COMSCR 1A Comparator Status and Control Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 53 Table 4 12 Quad Timer B Registers Address Map Continued TMRB_BASE 00 F080 Quad Timer B is NOT available in the 56F8157 device Register Acronym Address Offset Register Description TMRB2_CMP1 20 Compare Register 1 TMRB2_CMP2 21 Compare Register 2 TMRB2_CAP 22 Capture Register TMRB2_LOAD 23 Load Register TMRB2_HOLD 24 Hold Register TMRB2_CNTR 25 Counter Register TMRB2_CTRL 26 Control Register TMRB2_SCR 27 Status and Control Register TMRB2 CMPLD1 28 Comparator Load Register 1 TMRB2 CMPLD2 29 Comparator Load Register 2 TMRB2 COMSCR 2A Comparator Status and Control Register TMRB3 CMP1 30 Compare Register 1 TMRB3 CM
72. 75 V Vpp33 ranges from 3 0 to 3 6 Short Circuit Current Iss 700 mA output shorted to ground Bias Current l pias 5 8 7 mA Power down Current lod 0 2 HA Short Circuit Tolerance TRsc 30 minutes output shorted to ground 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 137 Table 10 10 PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start up time Tps 0 3 0 5 10 ms Resonator Start up time Trs 0 1 0 18 1 ms Min Max Period Variation Try 120 200 ps Peak to Peak Jitter Tpy 175 ps Bias Current IBIAS 1 5 2 mA Quiescent Current power down mode lpp 100 150 uA 10 2 1 Temperature Sense Note Temperature Sensor is NOT available in the 56F8157 device Table 10 11 Temperature Sense Parametrics Characteristics Symbol Min Typical Max Unit Slope Gain m 7 762 mV C Room Trim Temp 2 Trt 24 26 28 C Hot Trim Temp Industrial THT 122 125 128 C Hot Trim Temp Automotive THT 147 150 153 C Output Voltage Vrso 1 370 V VppA Apc 3 3V Ty 0 C Supply Voltage VpDA ADC 3 0 3 3 3 6 V Supply Current OFF IDD OFF 10 pA Supply Current ON IDD ON EM 250 uA Accuracy from 40 C to 150 C Tacc 6 7 0 6 7 C Using Vis mT Viso Resolution 51 Res 0 104 C bit T Includes the ADC conversion of the analog Tempe
73. 8 ENOB SINAD 1 76 6 02 Absolute error includes the effects of both gain error and offset error 7 Please see the 56F8300 Peripheral User s Manual for additional information on ADC calibration Assumes each voltage reference pin is bypassed with 0 1uF ceramic capacitors to ground The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC This allows the ADC to operate in noisy industrial environments where inductive flyback is possible 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 155 ADC absolute error before calibration and after calibration VDCin 0 60V Cy o og aoe before calibration c 50L cf2 31 668245 d pon pa rd N TS PO A o QU Dm i Se Je 2 Nue od E po A As o awe Ke V VAN 2 0 x a Se p after calibration 2 50F percent reduction of range of error 28 0 dabas calm 20 4 lt mean after cal 1 0 0 5 10 15 20 25 30 35 40 45 serial number ADC absolute error before calibration and after calibration VDCin 2 70V cfi 0 010380 ch 31 668245 before calibration 50 N d Pu after calibration mean before cal 19 1 mean after cal 2 2 0 5 10 15 20 25 30 35 40 45 serial number ADC absolute error LSBs Figure 10 22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC 0 60V and 2 70V
74. 9 Peripheral DO 70 10 Peripheral D1 71 11 Peripheral D2 83 12 Peripheral D3 86 13 Peripheral D4 88 14 Peripheral D5 89 15 Peripheral D6 90 1 See Part 6 5 8 to determine how to select peripherals from this set 56F8357 Technical Data Rev 15 130 Freescale Semiconductor Preliminary JTAG Information Part 9 Joint Test Action Group JTAG 9 1 JTAG Information Please contact your Freescale marketing representative or authorized distributor for device package specific BSDL information Part 10 Specifications 10 1 General Characteristics The 56F8357 56F8157 are fabricated in high density CMOS with 5V tolerant TTL compatible digital inputs The term 5V tolerant refers to the capability of an I O pin built on a 3 3V compatible process technology to withstand a voltage up to 5 5V without damaging the device Many systems have a mixture of devices designed for 3 3V and 5V power supplies In such sytems a bus may carry both 3 3V and 5V compatible I O voltage levels a standard 3 3V I O is designed to receive a maximum voltage of 3 3V 10 during normal operation without causing damage This 5V tolerant capability therefore offers the power savings of 3 3V I O levels combined with the ability to receive 5V levels without damage Absolute maximum ratings in Table 10 1 are stress ratings only and functional operation at the maximum is not guaranteed Stress beyond these rati
75. 96F8357 56F8157 Data Sheet Preliminary Technical Data 56F8300 16 bit Digital Signal Controllers MC56F8357 Rev 15 01 2007 e freescale com 2 freescale semiconductor Document Revision History Version History Description of Change Rev 1 0 Initial Public Release Rev 2 0 Added Package Pins to GPIO Table in Part 8 General Purpose Input Output GPIO Added Typical Min values to Table 10 17 Editing grammar spelling consistency of language throughout family Updated values in Regulator Parameters Table 10 9 External Clock Operation Timing Requirements Table 10 13 SPI Timing Table 10 18 ADC Parameters Table 10 24 and lO Loading Coefficients at 10MHz Table 10 25 Rev 3 0 Corrected Table 4 6 Data Memory Map changed address X FFO000 to X FFFFOO Rev 4 0 Added Part 4 8 added the word access to FM Error Interrupt in Table 4 5 documenting only Typ numbers for LVI in Table 10 6 updated EMI numbers and write up in Part 10 8 Rev 5 0 Rev 6 0 Replace any reference to Flash Interface Unit with Flash Module removed references to JTAG pin Updated numbers in Table 10 7 and Table 10 8 with more recent data Corrected typo in Table 10 3 in Pd characteristics DE corrected pin number for D14 in Table 2 2 added note to Veap pin in Table 2 2 corrected thermal numbers for 160 LQFP in Table 10 3 removed unneccessary notes in Table 10 12 corrected temperature range in T
76. CR DIS D6 D5 D4 NC D3 NC NC D2 NC NC 166 Freescale Semiconductor Preliminary 56F8157 Package and Pin Out Information Table 11 3 56F8157 160 Pin LQFP Package Identification by Pin Number Pin No ra Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 Von wo 41 Vss 81 NC 121 ANB5 2 Vpp2 42 Von wo 82 NC 122 ANB6 3 CLKO 43 PWMB3 83 D2 123 ANB7 4 TXDO 44 PWMB4 84 NC 124 EXTBOOT 5 RXDO 45 PWMB5 85 NC 125 Vss 6 SCLK1 46 GPIOB5 86 D3 126 GPIOC8 7 MOSI1 47 GPIOB6 87 NC 127 GPIOC9 8 MISO1 48 GPIOB7 88 D4 128 GPIOC10 9 Sst 49 TXD1 89 D5 129 GPIOE10 10 A1 50 RXD1 90 D6 130 GPIOE11 11 A2 51 WR 91 OCR DIS 131 GPIOE12 12 A3 52 RD 92 VppA osc PLL 132 GPIOE13 13 A4 53 PS 93 XTAL 133 TCO 14 A5 54 DS 94 EXTAL 134 Von io 15 VcAp4 55 GPIODO 95 Voap3 135 TC1 16 Vpp io 56 GPIOD1 96 Vpp io 136 TRST 17 A6 57 GPIOD2 97 RSTO 137 TCK 18 AT 58 GPIOD3 98 RESET 138 TMS 19 A8 59 GPIOD4 99 CLKMODE 139 TDI 20 AQ 60 GPIOD5 100 ANAO 140 TDO 21 A10 61 ISBO 101 ANA1 141 Vpp1 22 A11 62 Vcap1 102 ANA2 142 NC 23 A12 63 ISB1 103 ANA3 143 NC 24 A13 64 ISB2 104 ANA4 144 Voap2 25 A14 65 IRQA 105 ANA5 145 sso When the on chip regulator is disabled these four pins become 2 5V Vpp cong 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 167 Table 11 3 56F8157 160 Pin LQFP Package Identification
77. DDR 2 Data Direction Register 0 x 0000 GPIOA_PER 3 Peripheral Enable Register 0 x 3FFF GPIOA_IAR 4 Interrupt Assert Register 0 x 0000 GPIOA IENR 5 Interrupt Enable Register 0 x 0000 GPIOA IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOA IPR 7 Interrupt Pending Register 0 x 0000 GPIOA IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOA PPMODE 9 Push Pull Mode Register 0 x 3FFF GPIOA RAWDATA A Raw Data Input Register Table 4 30 GPIOB Registers Address Map GPIOB BASE 00 F300 Register Acronym Address Offset Register Description Reset Value GPIOB PUR 0 Pull up Enable Register 0 x OOFF GPIOB DR 1 Data Register 0 x 0000 GPIOB DDR 2 Data Direction Register 0 x 0000 GPIOB PER 3 Peripheral Enable Register 0 x 000F for 20 bit EMI address at reset 0 x 0000 for all other cases See Table 4 4 for details 56F8357 Technical Data Rev 15 66 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 30 GPIOB Registers Address Map Continued GPIOB_BASE 00 F300 Register Acronym Address Offset Register Description Reset Value GPIOB_IAR 4 Interrupt Assert Register 0 x 0000 GPIOB_IENR 5 Interrupt Enable Register 0 x 0000 GPIOB_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOB_IPR 7 Interrupt Pending Register 0 x 0000 GPIOB_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOB_PPMODE 9 Push Pull Mode Registe
78. F240 4 21 Temperature Sensor TSENSOR X 00 F270 4 22 SCI 0 SCIO X 00 F280 4 23 SCI 1 SCH X 00 F290 4 24 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 49 Table 4 9 Data Memory Peripheral Base Address Map Summary Continued Peripheral Prefix Base Address Table Number SPI 0 SPIO X 00 F2A0 4 25 SPI 1 SPI1 X 00 F2BO 4 26 COP COP X 00 F2CO 4 27 PLL OSC CLKGEN X 00 F2D0 4 28 GPIO Port A GPIOA X 00 F2E0 4 29 GPIO Port B GPIOB X 00 F300 4 30 GPIO Port C GPIOC X 00 F310 4 31 GPIO Port D GPIOD X 00 F320 4 32 GPIO Port E GPIOE X 00 F330 4 33 GPIO Port F GPIOF X 00 F340 4 34 SIM SIM X 00 F350 4 35 Power Supervisor LVI X 00 F360 4 36 FM FM X 00 F400 4 37 FlexCAN FC X 00 F800 4 38 Table 4 10 External Memory Integration Registers Address Map EMI_BASE 00 F020 Register Acronym Address Offset Register Description Reset Value CSBAR 0 0 Chip Select Base Address Register 0 0x0004 64K when EXT_BOOT 0 or EMI_MODE 0 0x0008 1M when EMI_MODE 1 Selects entire program space for CSO CSBAR 1 1 Chip Select Base Address Register 1 0x0004 64K when EMI MODE 0 0x0008 1M when EMI MODE 1 Selects A0 A19 addressable data space for CS1 CSBAR 2 2 Chip Select Base Address Register 2 CSBAR 3 3 Chip Select Base Address Register 3 CSBAR 4 4 Chip Select Base Address Re
79. FCMB2_ID_LOW 52 Message Buffer 2 ID Low Register FCMB2 DATA 53 Message Buffer 2 Data Register FCMB2 DATA 54 Message Buffer 2 Data Register FCMB2 DATA 55 Message Buffer 2 Data Register FCMB2 DATA 56 Message Buffer 2 Data Register Reserved FCMB3 CONTROL 58 Message Buffer 3 Control Status Register FCMB3 ID HIGH 59 Message Buffer 3 ID High Register FCMB3 ID LOW 5A Message Buffer 3 ID Low Register FCMB3 DATA 5B Message Buffer 3 Data Register FCMB3 DATA 5C Message Buffer 3 Data Register FCMB3 DATA 5D Message Buffer 3 Data Register FCMB3 DATA 5E Message Buffer 3 Data Register Reserved FCMB5 CONTROL 68 FCMB4 CONTROL 60 Message Buffer 4 Control Status Register FCMBA ID HIGH 61 Message Buffer 4 ID High Register FCMBA ID LOW 62 Message Buffer 4 ID Low Register FCMB4 DATA 63 Message Buffer 4 Data Register FCMB4 DATA 64 Message Buffer 4 Data Register FCMB4_DATA 65 Message Buffer 4 Data Register FCMB4_DATA 66 Message Buffer 4 Data Register Reserved Message Buffer 5 Control Status Register 56F8357 Technical Data Rev 15 72 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMB5_ID_HIGH 69 Message Buffe
80. GPIOF PPMODE 9 Push Pull Mode Register 0x FFFF GPIOF RAWDATA A Raw Data Input Register I Table 4 35 System Integration Module Registers Address Map SIM BASE 00 F350 Register Acronym Address Offset Register Description SIM CONTROL 0 Control Register SIM RSTSTS 1 Reset Status Register SIM SCRO 2 Software Control Register 0 SIM SCR1 3 Software Control Register 1 SIM SCR2 4 Software Control Register 2 SIM SCR3 5 Software Control Register 3 SIM MSH ID 6 Most Significant Half JTAG ID SIM LSH ID 7 Least Significant Half JTAG ID SIM PUDR 8 Pull up Disable Register SIM CLKOSR A Clock Out Select Register SIM GPS B Quad Decoder 1 Timer B SPI 1 Select Register SIM PCE C Peripheral Clock Enable Register SIM ISALH D 1 0 Short Address Location High Register SIM ISALL E 1 0 Short Address Location Low Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 69 Table 4 36 Power Supervisor Registers Address Map LVI_BASE 00 F360 Register Acronym Address Offset Register Description LVI_CONTROL 0 Control Register LVI_STATUS 1 Status Register Table 4 37 Flash Module Registers Address Map FM_BASE 00 F400 Register Acronym Address Offset Register Description FMCLKD 0 Clock Divider Register FMMCR 1 Module Control Register FMSECH
81. HASEB1 7 D1 Schmitt Input Phase B1 Quadrature Decoder 1 PHASEB input for Input pull up decoder 1 enabled TB1 Schmitt Input TB1 Timer B Channel 1 Output MOSM Schmitt SPI 1 Master Out Slave In This serial data pin is an output Input from a master device and an input to a slave device The Output master device places data on the MOSI line a half cycle before the clock edge the slave device uses to latch the data To activate the SPI function set the PHSB ALT bit in the SIM GPS register For details see Part 6 5 8 GPIOC1 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output In the 56F8357 the default state after reset is PHASEB1 In the 56F8157 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit 1 in the GPIOC PUR register 56F8357 Technical Data Rev 15 32 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin state e Name No Ball No Type During Signal Description Reset INDEX1 8 E2 Schmitt Input Index1 Quadrature Decoder 1 INDEX input Input pull up enabled TB2 Schmitt TB2 Timer B Channel 2 Input Output MISO1 Schmitt SPI 1 Master In Slave Out This serial data pin is an input to Input a master device and an output from a slave
82. IDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0 08mm DETAIL F DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN A PROTRUSION AND AN E1 I N ADJACENT LEAD IS 0 07mm J al EXACT SHAPE OF CORNERS MAY VARY NIL 7 156X e gt x C3 0 08 C C ax el2 MILLIMETER SEATING l 160X e DIM MIN MAX PLANE A 1 60 0 08 C A B D AL 0 05 0 15 A2 135 145 b 0 17 027 bl 017 023 c 0 09 020 er 0 09 0 16 D 26 00 BSC D1 24 00 BSC e 0 50 BSC E 26 00 BSC A E Hl 24 00 BSC L 045 0 75 d L1 1 00 REF 0 25 R1 0 08 GAGE R2 0 08 020 PLANE S 0 20 D 0o 79 01 0 02 ul 13 03 me 139 DETAIL F Figure 11 5 160 pin LAFP Mechanical Information 56F8357 Technical Data Rev 15 Freescale Semiconductor 169 Preliminary Part 12 Design Considerations 12 1 Thermal Design Considerations An estimation of the chip junction temperature Ty can be obtai
83. IOE_PUR register Example GPIOE2 clear bit 2 in the GPIOE PUR register A8 19 G2 Output In reset Address Bus A8 A15 specify eight of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR A8 A15 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOAO0 Schmitt Port A GPIO These eight GPIO pins can be individually Input programmed as input or output pins A9 20 H1 Output GPIOA1 After reset the default state is Address Bus A10 21 H2 To deactivate the internal pull up resistor clear the appropriate GPIOA2 GPIO bit in the GPIOA_PUR register A11 22 H4 e GPIOA3 Example GPIOAO clear bit O in the GPIOA_PUR register A12 23 H3 GPIOA4 A13 24 J1 GPIOA5 A14 25 J2 GPIOA6 A15 26 J3 GPIOA7 56F8357 Technical Data Rev 15 22 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset GPIOBO 33 L1 Schmitt Input Port B GPIO These four GPIO pins can be programmed as Input pull up input or output pins Output enabled A16 Output Address Bus A16 A19 specify one of the
84. Load Register TMRD2_HOLD 24 Hold Register TMRD2_CNTR 25 Counter Register TMRD2_CTRL 26 Control Register TMRD2_SCR 27 Status and Control Register TMRD2_CMPLD1 28 Comparator Load Register 1 TMRD2_CMPLD2 29 Comparator Load Register 2 TMRD2_COMSCR 2A Comparator Status and Control Register TMRD3_CMP1 30 Compare Register 1 TMRD3_CMP2 31 Compare Register 2 TMRD3_CAP 32 Capture Register TMRD3_LOAD 33 Load Register TMRD3_HOLD 34 Hold Register TMRD3_CNTR 35 Counter Register TMRD3_CTRL 36 Control Register TMRD3_SCR 37 Status and Control Register TMRD3_CMPLD1 38 Comparator Load Register 1 TMRD3_CMPLD2 39 Comparator Load Register 2 TMRD3_COMSCR 3A Comparator Status and Control Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Table 4 15 Pulse Width Modulator A Registers Address Map PWMA_BASE 00 F140 PWMA is NOT available in the 56F8157 device Register Acronym Address Offset Register Description PWMA PMCTL 0 Control Register PWMA PMFCTL 1 Fault Control Register PWMA PMFSA 2 Fault Status Acknowledge Register PWMA PMOUT 3 Output Control Register PWMA PMCNT 4 Counter Register PWMA PWMCM 5 Counter Modulo Register PWMA PWMVALO 6 Value Register 0 PWMA PWMVAL1 7 Value Register 1 PWMA PWMVAL2 8 Value Register 2 PWMA PWMVALS3 9 Value Register 3 PWMA_PWMVAL4 A Value
85. Most designs will want to change the DRV state to DRV 1 instead of using the default setting To deactivate the internal pull up resistor set the CTRL bit in the SIM_PUDR register PS 53 N6 Output In reset Program Memory Select This signal is actually CSO in the output is EMI which is programmed at reset for compatibility with the CS0 disabled 56F80x PS signal PS is asserted low for external program pull up is memory access enabled Depending upon the state of the DRV bit in the EMI bus control register BCR CSO is tri stated when the external bus is inactive CS0 resets to provide the PS function as defined on the 56F80x devices GPIOD8 Input Port D GPIO This GPIO pin can be individually Output programmed as an input or output pin To deactivate the internal pull up resistor clear bit 8 in the GPIOD_PUR register DS 54 L5 Output In reset Data Memory Select This signal is actually CS1 in the EMI output is which is programmed at reset for compatibility with the 56F80x CS1 disabled DS signal DS is asserted low for external data memory pull up is access enabled Depending upon the state of the DRV bit in the EMI bus control register BCR CS1 is tri stated when the external bus is inactive CS1 resets to provide the DS function as defined on the 56F80x devices GPIOD9 Input Port D GPIO This GPIO pin can be individually Output programmed as an input or output pin To deactivate the inter
86. Note The absolute error data shown in the graphs above reflects the effects of both gain error and offset error The data was taken on 14 parts three each from three processing corner lots and two from the fourth processing corner lot as well as three from one nominally processed lot each at three temperatures 40 C 27 C and 150 C giving the 42 data points shown above for two input DC voltages 0 60V and 2 70V The data indicates that for the given population of parts calibration significantly reduced by as much as 28 the collective variation spread of the absolute error of the population It also significantly reduced by as much as 80 the mean average of the absolute error and thereby brought it significantly closer to the ideal value of zero Although not guaranteed it is believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes 56F8357 Technical Data Rev 15 156 Freescale Semiconductor Preliminary Equivalent Circuit for ADC Inputs 10 17 Equivalent Circuit for ADC Inputs Figure 10 23 illustrates the ADC input circuit during sample amp hold S1 and S2 are always open closed at the same time that S3 is closed open When S1 S2 are closed amp S3 is open one input of the sample and hold circuit moves to VerryH VrerH 2 while the other charges to the analog input voltage When the switches are flipped
87. ODE 40 PWMB2 80 Vss 120 ANB4 160 Vss 56F8357 Technical Data Rev 15 Freescale Semiconductor 161 Preliminary 1 2 3 4 5 6 7 8 9 10 11 12 1413 ZO OS PES FUN xs ES OS ZUR SN DON SN JR ES YOR INDEXOPHASEAO D15 D142 D14 SCLKO Moni TMS TCO OD ISAO ANB7 ANB5 ANB4 lan SO SO SN EN SN Kod P Ne A Nt Nests WE EP KZ uw Neu Ge od Ka TXDO MODE HOMEO PHASEBO D13 MOSIO CAN RX TDI TC1 TDO EXTBOOT ANB6 ANB3 ANB1 PHASEA1 Vpp2 A0 D14 ISA1 ANB2 ANBO VDDA ADC PHASEB1 RXDO Cup MISOO 580 CAN TX TDO TCK TRST TD2 ISA2 Vssa Apc VREFP VREFH HOME1 INDEX1 A1 A2 Vppio Vss Vss VcaP2 Mon TD3 SENSE VrerLo ANA7 VREFMID y a EN ms N Y fF x A4 A3 A5 Vpp wo Vpp io ANA4 ANA3 Vereen A6 A8 A7 Vcapt Vss ANA2 ANAO ANAG z ES z E a a SA SR LA NU Ne Nu Mo AQ A10 A12 Af Vcap3 CLK ANA T ANAS MODE 77 SO TES EOS N lan ZC van WP S WU GU L y A13 A14 A15 Vss EXTAL RSTO RESET D7 D9 Von io GPIOD2 Vppio Moar RQA Von o Vss XTAL gga An OCH DIS LU We cA or Xo o Xu WN ES E Nue Al E UL GPIOBO GPIOB2 GPIOB1 WR DS GPIOD1GPIOD5 ISB1 FAULTB1 FAULTB2 D6 D5 D3 D4 ex 5 r3 iN i P NY Ne NY Sy Kay A N 7 A ak GPIOB3 GPIOB4 PWMB5 GPIOB7 PWMAO PWMA3 FAULTA2 FAULTA3 PWMBO PWMB2 PWMB3 GPIOB5 RXD1 PS GPIOD3 ISBO FAULTBO D1 PWMA2 PWMAS FAULTAO FAULTA1 J J CJ CJ C C us p L J D PWMB1 PWMB4 GPIOB6 TXD1 RD GPIODO GPIOD4 IsB2 IRQB DO FAULTB3PWMA1 PWMA4 D2 Figure 11 2 Top View 56F8357 160 Pin MAPBGA Package 56F8357 Tech
88. OMR MA and MB bits operate in this device For all other bits see the DSP56800E Reference Manual Note The OMR is not a Memory Map register it is directly accessible in code through the acronym OMR 56F8357 Technical Data Rev 15 Freescale Semiconductor 107 Preliminary 6 5 Register Descriptions Table 6 1 SIM Registers SIM_BASE 00 F350 Address Offset Address Acronym Register Name Section Location Base 0 SIM_CONTROL Control Register 6 5 1 Base 1 SIM_RSTSTS Reset Status Register 6 5 2 Base 2 SIM_SCRO Software Control Register 0 6 5 3 Base 3 SIM_SCR1 Software Control Register 1 6 5 3 Base 4 SIM_SCR2 Software Control Register 2 6 5 3 Base 5 SIM_SCR3 Software Control Register 3 6 5 3 Base 6 SIM_MSH_ID Most Significant Half of JTAG ID 6 5 4 Base 7 SIM_LSH_ID Least Significant Half of JTAG ID 6 5 5 Base 8 SIM_PUDR Pull up Disable Register 6 5 6 Base A SIM_CLKOSR CLKO Select Register 6 5 7 Base B SIM_GPS GPIO Peripheral Select Register 6 5 8 Base C SIM_PCE Peripheral Clock Enable Register 6 5 9 Base D SIM_ISALH 1 0 Short Address Location High Register 6 5 10 Base E SIM_ISALL 1 0 Short Address Location Low Register 6 5 10 56F8357 Technical Data Rev 15 108 Freescale Semiconductor Preliminary Register Descriptions Add Register Offset Name 6 5 4 3 2 1 0
89. P2 31 Compare Register 2 TMRB3 CAP 32 Capture Register TMRB3 LOAD 33 Load Register TMRB3 HOLD 34 Hold Register TMRB3 CNTR 35 Counter Register TMRB3_CTRL 36 Control Register TMRB3_SCR 37 Status and Control Register TMRB3_CMPLD1 38 Comparator Load Register 1 TMRB3_CMPLD2 39 Comparator Load Register 2 TMRB3_COMSCR 3A Comparator Status and Control Register Table 4 13 Quad Timer C Registers Address Map TMRC BASE 00 FOCO Register Acronym Address Offset Register Description TMRCO_CMP1 0 Compare Register 1 TMRCO_CMP2 1 Compare Register 2 TMRCO_CAP 2 Capture Register TMRCO_LOAD 3 Load Register TMRCO_HOLD 4 Hold Register TMRCO_CNTR 5 Counter Register 56F8357 Technical Data Rev 15 54 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 13 Quad Timer C Registers Address Map Continued TMRC_BASE 00 FOCO Register Acronym Address Offset Register Description TMRCO_CTRL 6 Control Register TMRCO_SCR 7 Status and Control Register TMRCO_CMPLD1 8 Comparator Load Register 1 TMRCO_CMPLD2 9 Comparator Load Register 2 TMRCO_COMSCR A Comparator Status and Control Register Reserved TMRC1_CMP1 10 Compare Register 1 TMRC1_CMP2 11 Compare Register 2 TMRC1_CAP 12 Capture Register TMRC1_LOAD 13 Load Register TMRC1_HOLD 14 Hold Register TMRC1_CNTR 15 Counter Register
90. PLL powered off Stop2 5 1mA Ou A 1454A External Clock is off All peripheral clocks are off ADC powered off PLL powered off 1 No Output Switching 2 Includes Processor Core current supplied by internal voltage regulator 56F8357 Technical Data Rev 15 136 Freescale Semiconductor Preliminary DC Electrical Characteristics Table 10 8 Current Consumption per Power Supply Pin Typical On Chip Regulator Disabled OCR_DIS High Mode Ipp Core l 1 DD_IO Ipp ap Ipp osc PLL Test Conditions RUN1 MAC 150mA 13uA 50mA 2 5mA 60MHz Device Clock All peripheral clocks are enabled All peripherals running Continuous MAC instructions with fetches from Data RAM ADC powered on and clocked Wait3 86mA 13uA lf 2 5mA 60MHz Device Clock All peripheral clocks are enabled ADC powered off Stop1 900A 13pA OLA 155uA 8MHz Device Clock All peripheral clocks are off ADC powered off PLL powered off Stop2 100uA 13pA 1 No Output Switching OLA 1454A External Clock is off All peripheral clocks are off ADC powered off PLL powered off Table 10 9 Regulator Parameters Characteristic Symbol Min Typical Max Unit Unloaded Output Voltage VRNL 2 25 2 75 V OmA Load Loaded Output Voltage VRL 2 25 2 75 V 200 mA load Line Regulation 250 mA load VR 2 25 2
91. PWMA FlexCAN Quadrature Decoder I and Quad Timers B and D are NOT available on the 56F68157 device Table 4 5 Interrupt Vector Table Contents Vector Priority Vector Base 3 Peripheral N mber Level Address Interrupt Function Reserved for Reset Overlay Reserved for COP Reset Overlay core 2 3 P 04 Illegal Instruction core 3 3 P 06 SW Interrupt 3 core 4 3 P 08 HW Stack Overflow core 5 3 P 0A Misaligned Long Word Access core 6 1 3 P 0C OnCE Step Counter core 7 1 3 P 0E OnCE Breakpoint Unit 0 Reserved core 9 1 3 P 12 OnCE Trace Buffer core 10 1 3 P 14 OnCE Transmit Register Empty core 11 1 3 P 16 OnCE Receive Register Full Reserved core 14 2 P 1C SW Interrupt 2 core 15 1 P 1E SW Interrupt 1 core 16 0 P 20 SW Interrupt 0 core 17 0 2 P 22 IRQA core 18 0 2 P 24 IRQB Reserved LVI 20 0 2 P 28 Low Voltage Detector power sense PLL 21 0 2 P 2A PLL FM 22 0 2 P 2C FM Access Error Interrupt FM 23 0 2 P 2E FM Command Complete FM 24 0 2 P 30 FM Command data and address Buffers Empty Reserved FLEXCAN 26 0 2 P 34 FLEXCAN Bus Off FLEXCAN 27 0 2 P 36 FLEXCAN Error FLEXCAN 28 0 2 P 38 FLEXCAN Wake Up FLEXCAN 29 0 2 P 3A FLEXCAN Message Buffer Interrupt GPIOF 30 0 2 P 3C GPIOF GPIOE 31 0 2 P 3E GPIOE GPIOD 32 0 2 P 40 GPIOD GPIOC 33 0 2 P 42 GPIOC 56F8357 Technical Data Rev 15 44 Fre
92. Pin Groups 0 2 5 pA Vout 3 0V to High Impedance State 1 2 3 4 5 6 7 8 5 5V or OV Schmitt Trigger Input Vuys Pin Groups 0 3 V Hysteresis 2 6 9 10 Input Capacitance Cinc 4 5 pF _ EXTAL XTAL Output Capacitance Coutc 5 5 m pF EXTAL XTAL Input Capacitance Cin 6 pF Output Capacitance Cour 6 pF See Pin Groups in Table 10 1 56F8357 Technical Data Rev 15 Freescale Semiconductor 135 Preliminary Table 10 6 Power On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1 75 1 8 1 9 V LVI 2 5 volt Supply trip point VEI2 5 2 14 V LVI 3 3 volt supply trip point VEI3 3 cm 2 7 V Bias Current l pias 110 130 uA 1 When Vpp core drops below Vez 5 an interrupt is generated 2 When Von core drops below Ve 3 an interrupt is generated Table 10 7 Current Consumption per Power Supply Pin Typical On Chip Regulator Enabled OCR DIS Low Mode Ipp io Ipp ADC Ipp osc PLL Test Conditions RUN1 MAC 155mA 50mA 2 5mA 60MHz Device Clock All peripheral clocks are enabled All peripherals running Continuous MAC instructions with fetches from Data RAM ADC powered on and clocked Wait3 91mA Stop1 6mA 70uA OuA 2 5mA 1554A 60MHz Device Clock All peripheral clocks are enabled ADC powered off 8MHz Device Clock All peripheral clocks are off ADC powered off
93. Program Flash and 8KB of Data Flash each programmable through the JTAG port with 4KB of Program RAM and 16KB of Data RAM It also supports program execution from external memory A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field programmable software routines that can be used to program the main Program and Data Flash memory areas Both Program and Data Flash memories can be independently bulk erased or erased in pages Program Flash page erase size is 1KB Boot and Data Flash page erase size is 512 bytes The Boot Flash memory can also be either bulk or page erased A key application specific feature of the 56F8357 is the inclusion of two Pulse Width Modulator PWM modules These modules each incorporate three complementary individually programmable PWM signal output pairs each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs to enhance motor control functionality Complementary operation permits programmable dead time insertion distortion correction via current sensing by software and separate top and bottom output polarity control The up counter value is programmable to support a continuously variable PWM frequency Edge aligned and center aligned synchronous pulse width control 0 to 100 modulation is supported The device is capable of controlling most motor types ACIM AC Induction Motors both BDC and BLDC Brush and Brushless DC motors SRM and VRM Swi
94. Q is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 Interrupt Priority Register 8 IPR8 Base 8 15 14 5 4 3 2 1 0 Read PEUT TMRA3IPL TMRA2IPL TMRA IPL Write RESET 0 0 0 0 0 0 0 0 Figure 5 11 Interrupt Priority Register 8 IPR8 SCIO Receiver Full Interrupt Priority Level SCIO RCV IPL 5 6 9 1 Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 11 IRQ is priority level 2 SCIO Receiver Error Interrupt Priority Level SCIO RERR IPL 5 6 9 2 Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 9 3 Reserved Bits 11 10 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 94 Register Descriptions 5 6 9 4 SCIO Transmitter Idle Interrupt Priority Level SCIO_TIDL IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2
95. R registers will change from port to port Tables 4 29 through 4 34 define the actual reset values of these registers 8 3 Configuration There are six GPIO ports defined on the 56F8357 56F8157 The width of each port and the associated peripheral function is shown in Table 8 1 and Table 8 2 The specific mapping of GPIO port pins is shown in Table 8 3 56F8357 Technical Data Rev 15 126 Freescale Semiconductor Preliminary Table 8 1 56F8357 GPIO Ports Configuration Configuration Available a Md Pins in Peripheral Function Reset Function 56F8347 A 14 14 14 pins EMI Address pins EMI Address B 8 8 8 pins EMI Address pins EMI Address C 11 11 4 pins DEC1 TMRB SPI1 DEC1 TMRB 4 pins DECO TMRA DECO TMRA 3 pins PWMA current sense PWMA current sense D 13 13 6 pins EMI CSn EMI Chip Selects 2 pins SCI1 SCI1 2 pins EMI CSn EMI Chip Selects 3 pins PWMB current sense PWMB current sense E 14 14 2 pins SCIO SCIO 2 pins EMI Address pins EMI Address 4 pins SPIO SPIO 2 pins TMRC TMRC 4 pins TMRD TMRD F 16 16 16 pins EMI Data EMI Data Table 8 2 56F8157 GPIO Ports Configuration Available SE Bai Pins in Peripheral Function Reset Function 56F8157 A 14 14 14 pins EMI Address pins EMI Address B 8 8 8 pins EMI Address pins EMI Address C 11 11 4 pins SPI1 SPI1 4 pins DECO TMRA DECO TMRA 3 pins Dedicated GPIO GPIO D 13 13 6 pins
96. RQ Pending 1 Register IRQP1 5 6 19 1 IRQ Pending PENDING Bits 32 17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 20 IRQ Pending 2 Register IRQP2 Base 13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 48 33 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5 22 IRQ Pending 2 Register IRQP2 56F8357 Technical Data Rev 15 Freescale Semiconductor 101 Preliminary 5 6 20 1 IRQ Pending PENDING Bits 48 33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 21 IRQ Pending 3 Register IRQP3 Base 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PENDING 64 49 RESET 1 1 1 1 1 1 d 1 1 1 d 1 1 1 1 1 Figure 5 23 IRQ Pending 3 Register IRQP3 5 6 21 1 IRQ Pending PENDING Bits 64 49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 22 IRQ Pending 4 Register IRQP4 Base
97. Register 4 PWMA_PWMVAL5 B Value Register 5 PWMA_PMDEADTM C Dead Time Register PWMA_PMDISMAP1 D Disable Mapping Register 1 PWMA_PMDISMAP2 E Disable Mapping Register 2 PWMA_PMCFG F Configure Register PWMA_PMCCR 10 Channel Control Register PWMA_PMPORT 11 Port Register PWMA_PMICCR 12 PWM Internal Correction Control Register Table 4 16 Pulse Width Modulator B Registers Address Map PWMB_BASE 00 F160 Register Acronym Address Offset Register Description PWMB_PMCTL 0 Control Register PWMB_PMFCTL 1 Fault Control Register PWMB_PMFSA 2 Fault Status Acknowledge Register PWMB_PMOUT 3 Output Control Register PWMB_PMCNT 4 Counter Register PWMB_PWMCM 5 Counter Modulo Register PWMB_PWMVALO 6 Value Register 0 56F8357 Technical Data Rev 15 58 Freescale Semiconductor Preliminary Table 4 16 Pulse Width Modulator B Registers Address Map Continued Peripheral Memory Mapped Registers PWMB_BASE 00 F160 Register Acronym Address Offset Register Description PWMB_PWMVAL1 7 Value Register 1 PWMB_PWMVAL2 8 Value Register 2 PWMB_PWMVAL3 9 Value Register 3 PWMB_PWMVAL4 A Value Register 4 PWMB_PWMVAL5 B Value Register 5 PWMB_PMDEADTM C Dead Time Register PWMB_PMDISMAP1 D Disable Mapping Register 1 PWMB_PMDISMAP2 E Disable Mapping Register 2 PWMB_PMCFG F Configure Register PWMB_PMCCR 10 Channel Control Regist
98. able 10 14 added ADC calibration information to Table 10 24 and new graphs in Figure 10 22 Rev 7 0 Adding clarifing notes to Table 4 4 to help clarify independent program flash blocks and other Program Flash modes clarification in Table 10 23 corrected Digital Input Current Low pull up enabled numbers in Table 10 5 Removed text and Table 10 2 replaced with note to Table 10 1 Rev 8 0 Added 56F8157 information edited to indicate differences in 56F8357 and 56F8157 Reformatted for Freescale look and feel Updated Temperature Sensor and ADC tables then updated balance of elec trical tables for consistency throughout the family Clarified UO power description in Table 2 2 added note to Table 10 7 and clarified Section 12 3 Rev 9 0 Added output voltage maximum value and note to clarify in Table 10 1 also removed overall life expectancy note since life expectancy is dependent on customer usage and must be determined by reliability engineering Clarified value and unit measure for Maximum allowed Pp in Table 10 3 Cor rected note about average value for Flash Data Retention in Table 10 4 Added new RoHS compliant orderable part numbers in Table 13 1 Rev 10 0 Added 160MAPBGA information TA equation updated in Table 10 4 and additional minor edits throughout data sheet Rev 11 0 Updated Table 10 24 to reflect new value for maximum Uncalibrated Gain Error Rev 12 0 Deleted formula for Max Ambient Operatin
99. address lines for external program or data memory accesses GPIOB1 34 L3 A17 Depending upon the state of the DRV bit in the EMI bus control register BCR A0 A23 and EMI control signals are tri stated GPIOB2 35 L2 when the external bus is inactive A18 GPIOB3 36 M1 ded SS Wed DER the DRV state to DRV 1 A19 instead of using the default setting After reset the startup state of GPIOBO 3 GPIO or address is determined as a function of EXTBOOT EMI MODE and the Flash security setting See Table 4 4 for further information on when this pin is configured as an address pin at reset In all cases this state may be changed by writing to GPIOB PER To deactivate the internal pull up resistor clear the appropriate GPIO bit in the GPIOB PUR register GPIOB4 37 M2 Schmitt Input Port B GPIO These four GPIO pins can be programmed as Input pull up input or output pins Output enabled A20 Output Address Bus A20 A23 specify one of the address lines for external program or data memory accesses Depending upon the state of the DRV bit in the EMI bus control register BCR A20 A23 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting prescaler_ Output Clock Outputs can be used to monitor the prescaler_clock clock SYS_CLK SYS_CLK2 or oscillator_clock on GPIOB4 through GPIOB7 respectively GPIOB5 46 N4 A21 Afte
100. airs including Vppa Vssa Ceramic and tantalum capacitors tend to provide better performance tolerances e Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vpp and Vss GND pins are less than 0 5 inch per capacitor lead e Use at least a four layer Printed Circuit Board PCB with two inner layers for Vpp and Vss Bypass the Vpp and Vos layers of the PCB with approximately 100uF preferably with a high grade capacitor such as a tantalum capacitor Because the device s output signals have fast rise and fall times PCB trace lengths should be minimal 56F8357 Technical Data Rev 15 Freescale Semiconductor 171 Preliminary Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance This is especially critical in systems with higher capacitive loads that could create higher transient currents in the Vpp and Vas circuits Take special care to minimize noise levels on the Vrep Vppa and Vsga pins Designs that utilize the TRST pin for JTAG port or EOnCE module functionality such as development or debugging systems should allow a means to assert TRST whenever RESET is asserted as well as a means to assert TRST independently of RESET Designs that do not require debugging functionality such as consumer products should tie these pins together Because the Flash memory is programmed through the JTAG EOnCE port the designer should provide an inte
101. al static component B internal state dependent component C internal dynamic component D external dynamic component E external static A the internal static component is comprised of the DC bias currents for the oscillator leakage current PLL and voltage references These sources operate independently of processor state or operating frequency B the internal state dependent component reflects the supply current required by certain on chip resources only when those resources are in use These include RAM Flash memory and the ADCs 56F8357 Technical Data Rev 15 Freescale Semiconductor 157 Preliminary C the internal dynamic component is classic C V F CMOS power dissipation corresponding to the 56800E core and standard cell logic D the external dynamic component reflects power dissipated on chip as a result of capacitive loading on the external pins of the chip This is also commonly described as C V F although simulations on two of the IO cell types used on the device reveal that the power versus load curve does have a non zero Y intercept Table 10 25 IO Loading Coefficients at 10MHz Intercept Slope PDUO8DGZ ME 1 3 0 11mW pF PDUOADGZ ME 1 15mW 0 11mW pF Power due to capacitive loading on output pins is first order a function of the capacitive load and frequency at which the outputs change Table 10 25 provides coefficients for calculating power dissipated
102. an external clock source 56F8357 Technical Data Rev 15 20 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset XTAL 93 K12 Input Chip driven Crystal Oscillator Output This output connects the internal Output crystal oscillator output to an external crystal If an external clock is used XTAL must be used as the input and EXTAL connected to GND The input clock can be selected to provide the clock directly to the core This input clock can also be selected as the input clock for the on chip PLL CLKO 3 D3 Output In reset Clock Output This pin outputs a buffered clock signal output is Using the SIM CLKO Select Register SIM_CLKOSR this pin disabled can be programmed as any of the following disabled CLK_MSTR system clock IPBus clock oscillator output prescaler clock and postscaler clock Other signals are also available for test purposes See Part 6 5 7 for details AO 154 C3 Output In reset Address Bus AO A5 specify six of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR A0 A5 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV s
103. ble 43 10 10 Serial Peripheral Interface SPI Timing 146 44 Data Map 46 10 11 Quad Timer Timing 150 4 5 Flash Memory Map oo oo o o 47 10 12 Quadrature Decoder Timing 150 4 6 EOnCE Memory Map 48 10 13 Serial Communication Interface 4 7 Peripheral Memory Mapped Registers 49 SCI Timing 151 4 8 Factory Programmed Memory 76 10 14 Controller Area Network CAN Timing 152 10 15 JTAG TIMING 2 04 25 29er Gla wees ae 152 Part 5 Interrupt Controller ITCN casada 76 10 16 Analog to Digital Converter 5 1 IDIROOMCUDID utpote d cQ TP 76 ADC Parameters 154 5 2 Features NEEN WEEK NEE EE EEN 76 10 17 Equivalent Circuit for ADC Inputs 157 5 3 Functional Descripti0N 76 10 18 Power Consumption 157 5 4 Block Diagram om RR RR 78 5 5 Operating Modes 2o casas wee as 78 Part 11 Packaging AI A 159 5 6 Register Descriptions isse ea sos 79 11 1 56F8357 Package and Pin Out 5 7 Eeler minis dirias 105 Informati n sss as n 159 11 2 56F8157 Package and Pin Out Part 6 System Integration Module SIM 106 Information 166 ECH OVOrVIBW cus nocuit px m abra S eur arn ee 106 6 2 Features cordobes trati 106 Part 12 Design Considerations 170 6 3 Operating Modes 107 12 1 Thermal Design Considerations 170 6 4 Operating Mode Register
104. cated 256 locations allocated X FF FEFF External Memory External Memory X 01 0000 X 00 FFFF On Chip Peripherals On Chip Peripherals X 00 F000 4096 locations allocated 4096 locations allocated X 00 EFFF External Memory External Memory X 00 3000 X 00 2FFF On Chip Data Flash X 00 2000 8KB X 00 1FFF On Chip Data RAM X 00 0000 16KB3 1 All addresses are 16 bit Word addresses not byte addresses 2 In the Operating Mode Register OMR 3 The Data RAM is organized as a 2K x 32 bit memory to allow single cycle long word operations 56F8357 Technical Data Rev 15 46 Freescale Semiconductor Preliminary Flash Memory Map 4 5 Flash Memory Map Figure 4 1 illustrates the Flash Memory FM map on the system bus The Flash Memory is divided into three functional blocks The Program and boot memories reside on the Program Memory buses They are controlled by one set of banked registers Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers The top nine words of the Program Memory Flash are treated as special memory locations The content of these words is used to control the operation of the Flash Controller Because these words are part of the Flash Memory content their state is maintained during power down and reset During chip initialization the content of these memory locations is loaded into Flash Memory control registers detailed in the Flash Mem
105. ch Register 1 FIVAL1 F Fast Interrupt Vector Address Low 1 Register FIVAH1 10 Fast Interrupt Vector Address High 1 Register IRQP 0 11 IRQ Pending Register 0 IRQP 1 12 IRQ Pending Register 1 IRQP 2 13 IRQ Pending Register 2 IRQP 3 14 IRQ Pending Register 3 IRQP 4 15 IRQ Pending Register 4 IRQP 5 16 IRQ Pending Register 5 ICTL 1D Interrupt Control Register Table 4 20 Analog to Digital Converter Registers Address Map ADCA_BASE 00 F200 Register Acronym Address Offset Register Description ADCA_CR 1 0 Control Register 1 ADCA_CR 2 1 Control Register 2 ADCA_ZCC 2 Zero Crossing Control Register ADCA_LST 1 3 Channel List Register 1 ADCA_LST 2 4 Channel List Register 2 ADCA_SDIS 5 Sample Disable Register ADCA_STAT 6 Status Register ADCA_LSTAT 7 Limit Status Register ADCA_ZCSTAT 8 Zero Crossing Status Register ADCA_RSLT 0 9 Result Register 0 ADCA_RSLT 1 A Result Register 1 ADCA_RSLT 2 B Result Register 2 ADCA_RSLT 3 C Result Register 3 ADCA_RSLT 4 D Result Register 4 ADCA_RSLT 5 E Result Register 5 ADCA_RSLT 6 F Result Register 6 ADCA_RSLT 7 10 Result Register 7 ADCA_LLMT 0 11 Low Limit Register 0 ADCA_LLMT 1 12 Low Limit Register 1 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 61 ADCA_BASE 00 F200 Table 4 20 Analog to Digital Converter Registers Address Map Continued Register Acronym Address Offs
106. cks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 13 Serial Peripheral Interface 1 Enable SPI1 Bit 3 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 14 Serial Peripheral Interface 0 Enable SPIO Bit 2 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 56F8357 Technical Data Rev 15 Freescale Semiconductor 119 Preliminary 6 5 9 15 Pulse Width Modulator B Enable PWMB 1 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e O0 The clock is not provided to the peripheral the peripheral is disabled 6 5 9 16 Pulse Width Modulator A Enable PWMA 0 Each bit controls clocks to the indicated peripheral e 1 Clocks are enabled e 0 The clock is not provided to the peripheral the peripheral is disabled 6 5 10 1 0 Short Address Location Register SIM_ISALH and SIM ISALL The I O Short Address Location registers are used to specify the memory referenced via the I O short address mode The I O short address mode allows the instruction to specify the lower six bits of address the upper address bits are not directly controllable This register set allows limited control of the full address as shown in Figure 6 13 Note If thi
107. cription SPIO_SPSCR 0 Status and Control Register SPIO_SPDSR 1 Data Size Register SPIO_SPDRR 2 Data Receive Register SPIO_SPDTR 3 Data Transmitter Register Table 4 26 Serial Peripheral Interface 1 Registers Address Map SPI1_BASE 00 F2B0 Register Acronym Address Offset Register Description SPI1_SPSCR 0 Status and Control Register SPI1_SPDSR 1 Data Size Register SPI1_SPDRR 2 Data Receive Register SPI1_SPDTR 3 Data Transmitter Register Table 4 27 Computer Operating Properly Registers Address Map COP_BASE 00 F2C0 Register Acronym Address Offset Register Description COPCTL 0 Control Register COPTO 1 Time Out Register COPCTR 2 Counter Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Table 4 28 Clock Generation Module Registers Address Map CLKGEN_BASE 00 F2D0 Register Acronym Address Offset Register Description PLLCR 0 Control Register PLLDB 1 Divide By Register PLLSR 2 Status Register SHUTDOWN 4 Shutdown Register OSCTL 5 Oscillator Control Register Table 4 29 GPIOA Registers Address Map GPIOA_BASE 00 F2E0 Register Acronym Address Offset Register Description Reset Value GPIOA_PUR 0 Pull up Enable Register 0 x 3FFF GPIOA_DR 1 Data Register 0 x 0000 GPIOA_
108. ctive low signal is low deasserted A high true active high signal is low or a low true active low signal is high Examples Signal Symbol Logic State Signal State Voltage PIN True Asserted Vu VoL PIN False Deasserted ViH VoH PIN True Asserted Vin Vou PIN False Deasserted Vi Nor 1 Values for VIL VOL VIH and VOH are defined by individual product specifications 56F8357 Technical Data Rev 15 Freescale Semiconductor 15 Preliminary Part 2 Signal Connection Descriptions 2 1 Introduction The input and output signals of the 56F8357 and 56F8157 are organized into functional groups as detailed in Table 2 1 and as illustrated in Figure 2 1 In Table 2 2 each table row describes the signal or signals present on a pin Table 2 1 Functional Group Pin Allocations Functional Group Number of Pins in Package 56F8357 56F8157 Power Vpp or VppA 9 9 Power Option Control 1 1 Ground Vss or Vssa 7 7 Supply Capacitors amp Vpp 6 6 PLL and Clock 4 4 Address Bus 24 24 Data Bus 16 16 Bus Control 10 10 Interrupt and Program Control 6 6 Pulse Width Modulator PWM Ports 26 13 Serial Peripheral Interface SPI Port 0 4 4 Serial Peripheral Interface SPI Port 1 4 Quadrature Decoder Port 0 4 4 Quadrature Decoder Port 1 4 E Serial Communications Interface SCI Ports 4 4 CAN Ports 2 Analog to Digital Converter ADC Ports 21 21 Timer Module Por
109. d to enable or disable security Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification the device will disable external P space accesses restricting code execution to internal memory disable EXTBOOT 1 mode and disable the core EOnCE debug capabilities Normal program execution is otherwise unaffected 56F8357 Technical Data Rev 15 Freescale Semiconductor 123 Preliminary 7 2 Flash Access Blocking Mechanisms The 56F8357 56F8157 have several operating functional and test modes Effective Flash security must address operating mode selection and anticipate modes in which the on chip Flash can be compromised and read without explicit user permission Methods to block these are outlined in the next subsections 7 2 1 Forced Operating Mode Selection At boot time the SIM determines in which functional modes the device will operate These are e Internal Boot Mode External Boot Mode e Secure Mode When Flash security is enabled as described in the Flash Memory module specification the device will boot in internal boot mode disable all access to external P space and start executing code from the Boot Flash at address 0x02 0000 This security affords protection only to applications in which the device operates in internal Flash sec
110. device The MISO Output line of a slave device is placed in the high impedance state if the slave device is not selected The slave device places data on the MISO line a half cycle before the clock edge the master device uses to latch the data To activate the SPI function set the INDEX_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOC2 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output In the 56F8357 the default state after reset is INDEX1 In the 56F8157 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit 2 in the GPIOC_PUR register HOME1 9 E1 Schmitt Input Home Quadrature Decoder 1 HOME input Input pull up enabled TB3 Schmitt TB3 Timer B Channel 3 Input Output SS1 Schmitt SPI 1 Slave Select In the master mode this pin is used to Input arbitrate multiple masters In slave mode this pin is used to select the slave To activate the SPI function set the HOME_ALT bit in the SIM_GPS register For details see Part 6 5 8 GPIOC3 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output In the 56F8357 the default state after reset is HOME1 In the 56F8157 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit
111. e The MSB of the address will be forced to 0 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Product Documentation 1 5 Product Documentation The documents in Table 1 2 are required for a complete description and proper design with the 56F8357 56F8157 devices Documentation is available from local Freescale distributors Freescale semiconductor sales offices Freescale Literature Distribution Centers or online at http www freescale com Table 1 3 Chip Documentation Topic Description Order Number DSP56800E Detailed description of the 56800E family architecture DSP56800EERM Reference Manual and 16 bit controller core processor and the instruction set 56F8300 Peripheral User Detailed description of peripherals of the 56F8300 MC56F8300UM Manual devices 56F8300 SCI CAN Detailed description of the SCI CAN Bootloaders MC56F83xxBLUM Bootloader User Manual 56F8300 family of devices 56F8357 56F8157 Electrical and timing specifications pin descriptions MC56F8357 Technical Data Sheet and package descriptions this document Errata Details any chip issues that might be present MC56F8357E MC56F8157E 1 6 Data Sheet Conventions This data sheet uses the following conventions OVERBAR This is used to indicate a signal that is active when pulled low For example the RESET pin is active when low asserted A high true active high signal is high or a low true a
112. e edge 20 4 ns Data invalid tpi 10 10 10 11 Master 0 ns 10 12 Slave 0 ns Rise time tr 10 10 10 11 Master 11 5 ns 10 12 10 13 Slave 10 0 ns Fall time tr 10 10 10 11 Master 9 7 ns 10 12 10 13 Slave 9 0 ns 1 Parameters listed are guaranteed by design 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 147 SS SS is held High on master Input tc p tr gt tr SCLK CPOL 0 teL Output t CH re ir tr t SCLK CPOL 1 PS Output MISO Input MOSI Output Figure 10 10 SPI Master Timing CPHA 0 SS SR Input to SS is held High on master P w tr R teL SCLK CPOL V 2 Output iu lt tF teL SCLK CPOL 1 Output tcH Let tps tr Le toy ref gt MOSI Output Figure 10 11 SPI Master Timing CPHA 1 56F8357 Technical Data Rev 15 148 Freescale Semiconductor Preliminary SS Input SCLK CPOL 0 Input SCLK CPOL 1 Input MISO Output SCLK CPOL 0 Input SCLK CPOL 1 Input MISO Output MOSI Input cl E tcH Serial Peripheral Interface SPI Timing Figure 10 13 SPI Slave Timing CPHA 1 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary
113. e user can change the size of the heat sink the air flow around the device the interface material the mounting arrangement on printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device To determine the junction temperature of the device in the application when heat sinks are not used the Thermal Characterization Parameter Py can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation T Tr Gr x Pp where Tr Thermocouple temperature on top of package C Wir Thermal characterization parameter C W Py Power dissipation in package W 56F8357 Technical Data Rev 15 170 Freescale Semiconductor Preliminary Electrical Design Considerations The thermal characterization parameter is measured per JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire When heat sink is used the junction temperature is determined from a thermocouple inserted at the interface between the case of t
114. eescale Semiconductor Preliminary 29 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin plate Nama No Ball No Type During Signal Description Reset INDEXO 157 A1 Schmitt Input Index Quadrature Decoder 0 INDEX input Input pull up enabled TA2 Schmitt TA2 Timer A Channel 2 Input Output GPIOC6 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output After reset the default state is INDEXO To deactivate the internal pull up resistor clear bit 6 of the GPIOC PUR register HOMEO 158 B3 Schmitt Input Home Quadrature Decoder 0 HOME input Input pull up enabled TA3 Schmitt TA3 Timer A Channel 3 Input Output GPIOC7 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output After reset the default state is HOMEO To deactivate the internal pull up resister clear bit 7 of the GPIOC PUR register SCLKO 146 A6 Schmitt Input SPI 0 Serial Clock In the master mode this pin serves as Input pull up an output clocking slaved listeners In slave mode this pin Output enabled serves as the data clock input GPIOE4 Schmitt Port E GPIO This GPIO pin can be individually Input programmed as an input or output pin Output After reset the default state is SCLKO To deactivate the internal pull up resistor clear bit 4 in the GPIOE_PUR regi
115. efault e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 5 Timer B Channel 0 Interrupt Priority Level TMRBO IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 8 6 Timer C Channel 3 Interrupt Priority Level TMRC3 IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 8 7 Timer C Channel 2 Interrupt Priority Level TMRC2 IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 0 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 93 Preliminary 5 6 8 8 Timer C Channel 1 Interrupt Priority Level TMRC1 IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IR
116. el List Register 1 ADCB LST2 4 Channel List Register 2 ADCB SDIS 5 Sample Disable Register ADCB STAT 6 Status Register ADCB LSTAT 7 Limit Status Register ADCB ZCSTAT 8 Zero Crossing Status Register ADCB RSLT 0 9 Result Register 0 ADCB_RSLT 1 A Result Register 1 ADCB_RSLT 2 B Result Register 2 ADCB_RSLT 3 C Result Register 3 ADCB_RSLT 4 D Result Register 4 ADCB_RSLT 5 E Result Register 5 ADCB_RSLT 6 F Result Register 6 ADCB_RSLT 7 10 Result Register 7 ADCB_LLMT 0 11 Low Limit Register 0 ADCB_LLMT 1 12 Low Limit Register 1 ADCB_LLMT 2 13 Low Limit Register 2 ADCB_LLMT 3 14 Low Limit Register 3 ADCB_LLMT 4 15 Low Limit Register 4 ADCB_LLMT 5 16 Low Limit Register 5 ADCB_LLMT 6 17 Low Limit Register 6 ADCB_LLMT 7 18 Low Limit Register 7 ADCB_HLMT 0 19 High Limit Register 0 ADCB_HLMT 1 1A High Limit Register 1 ADCB HLMT 2 1B High Limit Register 2 ADCB HLMT 3 1C High Limit Register 3 ADCB HLMT 4 1D High Limit Register 4 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 63 Table 4 21 Analog to Digital Converter Registers Address Map Continued ADCB_BASE 00 F240 Register Acronym Address Offset Register Description ADCB_HLMT 5 1E High Limit Register 5 ADCB_HLMT 6 1F High Limit Register 6 ADCB HLMT 7 20 High Limit Register 7 ADCB_OFS 0 21 Offset Register 0 ADCB_OFS 1 22 Offset Register 1 ADCB_OFS 2 23 Offset Regi
117. elect CLKOSEL Bits 4 0 Selects clock to be muxed out on the CLKO pin e 00000 SYS_CLK from OCCS DEFAULT e 00001 Reserved for factory test 56800E clock e 00010 Reserved for factory test XRAM clock e 00011 Reserved for factory test PFLASH odd clock e 00100 Reserved for factory test PFLASH even clock 00101 Reserved for factory test BFLASH clock e 00110 Reserved for factory test DFLASH clock e 00111 Oscillator output e 01000 Fout from OCCS e 01001 Reserved for factory test IPB clock 01010 Reserved for factory test Feedback from OCCS this is path to PLL 01011 Reserved for factory test Prescaler clock from OCCS 01100 Reserved for factory test Postscaler clock from OCCS e 01101 Reserved for factory test SYS CLK2 from OCCS e 01110 Reserved for factory test SYS CLK DIV2 e 01111 Reserved for factory test SYS CLK D 10000 ADCA clock 10001 ADCB clock 6 5 8 GPIO Peripheral Select Register SIM GPS The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC The default peripheral is Quad Decoder 1 and Quad Timer B NOT available in the 56F8157 device these peripherals work together The four I O pins associated with GPIOC can function as GPIO Quad Decoder I Quad Timer B or as SPI 1 signals GPIO is not the default and is enabled disabled via the GPIOC PER as shown in Figure 6 10 and Table
118. ent Sense inputs and four Fault inputs fault tolerant design with dead time insertion supports both center aligned and edge aligned modes Inthe 56F8157 one Pulse Width Modulator module with six PWM outputs three Current Sense inputs and three Fault inputs fault tolerant design with dead time insertion supports both center aligned and edge aligned modes Four 12 bit Analog to Digital Converters ADCs which support four simultaneous conversions with quad 4 pin multiplexed inputs ADC and PWM modules can be synchronized through Timer C channels 2 and 3 Quadrature Decoder In the 56F8357 two four input Quadrature Decoders or two additional Quad Timers Inthe 56F8157 one four input Quadrature Decoder which works in conjunction with Quad Timer A Temperature Sensor can be connected on the board to any of the ADC inputs to monitor the on chip temperature Quad Timer Inthe 56F8357 four dedicated general purpose Quad Timers totaling six dedicated pins Timer C with two pins and Timer D with four pins In the 56F8157 two general purpose Quad Timers Timer A works in conjunction with Quadrature Decoder 0 or GPIO and Timer C works in conjunction with GPIO FlexCAN CAN Version 2 0 B compliant module with 2 pin port for transmit and receive 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary e Two Serial Communication Interfaces SCIs each with two pins or four additional GPIO lines
119. entation Part 13 Ordering Information Table 13 1 lists the pertinent information needed to place an order Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts Table 13 1 Ordering Information Supply Pin Frequency Ambient Part Voltage Package Type Count MHz Temperature Order Number Range MC56F8357 3 0 3 6 V Low Profile Quad Flat Pack LQFP 160 60 40 to 105 C MC56F8357VPY60 MC56F8157 3 0 3 6 V Low Profile Quad Flat Pack LQFP 160 60 40 to 105 C MC56F8157VPY MC56F8357 3 0 3 6 V Low Profile Quad Flat Pack LQFP 160 60 40 to 105 C MC56F8357VPYE MC56F8357 3 0 3 6 V Low Profile Quad Flat Pack LQFP 160 60 40 to 125 C MC56F8357MPYE MC56F8157 3 0 3 6 V Low Profile Quad Flat Pack LQFP 160 60 40 to 105 C MC56F8157VPYE MC56F8357 3 0 3 6 V Mold Array Process Ball Grid Array 160 60 40 to 105 C MC56F8357VVF MAPBGA This package is RoHS compliant 56F8357 Technical Data Rev 15 Freescale Semiconductor 173 Preliminary 56F8357 Technical Data Rev 15 174 Freescale Semiconductor Preliminary Power Distribution and I O Ring Implementation 56F8357 Technical Data Rev 15 Freescale Semiconductor 175 Preliminary 56F8357 Technical Data Rev 15 176 Freescale Semiconductor Preliminary How to Reach Us Home Page www freescale com E mail suppo
120. er PWMB_PMPORT 11 Port Register PWMB PMICCR 12 PWM Internal Correction Control Register Table 4 17 Quadrature Decoder 0 Registers Address Map DECO BASE 00 F180 Register Acronym Address Offset Register Description DECO_DECCR 0 Decoder Control Register DECO_FIR 1 Filter Interval Register DECO_WTR 2 Watchdog Time out Register DECO_POSD 3 Position Difference Counter Register DECO_POSDH 4 Position Difference Counter Hold Register DECO_REV 5 Revolution Counter Register DECO_REVH 6 Revolution Hold Register DECO_UPOS 7 Upper Position Counter Register DECO_LPOS 8 Lower Position Counter Register DECO_UPOSH 9 Upper Position Hold Register DECO_LPOSH A Lower Position Hold Register DECO_UIR B Upper Initialization Register DECO_LIR C Lower Initialization Register DECO_IMR D Input Monitor Register 56F8357 Technical Data Rev 15 Freescale Semiconductor 59 Table 4 18 Quadrature Decoder 1 Registers Address Map DEC1_BASE 00 F190 Quadrature Decoder 1 is NOT available in the 56F8157 device Register Acronym Address Offset Register Description DEC1_DECCR 0 Decoder Control Register DEC1_FIR 1 Filter Interval Register DEC1_WTR 2 Watchdog Time out Register DEC1_POSD 3 Position Difference Counter Register DEC1_POSDH 4 Position Difference Counter Hold Register DEC1_REV 5 Revolution
121. erals to create an extremely cost effective solution Because of its low cost configuration flexibility and compact program code the 56F8357 and 56F8157 are well suited for many applications The device includes many peripherals that are especially useful for motion control smart appliances steppers encoders tachometers limit switches power supply and control automotive control 56F8357 only engine management noise suppression remote utility metering industrial control for power lighting and automation applications The 56800E core is based on a Harvard style architecture consisting of three execution units operating in parallel allowing as many as six operations per instruction cycle The MCU style programming model and optimized instruction set allow straightforward generation of efficient compact DSP and control code The instruction set is also highly efficient for C C Compilers to enable rapid development of optimized control applications The 56F8357 and 56F8157 support program execution from internal or external memories Two data operands can be accessed from the on chip data RAM per instruction cycle These devices also provide two external dedicated interrupt lines and up to 76 General Purpose Input Output GPIO lines depending on peripheral configuration 56F8357 Technical Data Rev 15 8 Freescale Semiconductor Preliminary Device Description 1 2 1 56F8357 Features The 56F8357 controller includes 256KB of
122. ers Characteristic Symbol Min Typ Max Unit Program time 1 Tprog 20 us Erase time Terase 20 ms Mass erase time Tme 100 ms 1 There is additional overhead which is part of the programming sequence See the 56F8300 Peripheral User Manual for details Program time is per 16 bit word in Flash memory Two words at a time can be programmed within the Pro gram Flash module as it contains two interleaved memories 2 Specifies page erase time There are 512 bytes per page in the Data and Boot Flash memories The Program Flash module uses two interleaved Flash memories increasing the effective page size to 1024 bytes 56F8357 Technical Data Rev 15 Freescale Semiconductor 139 Preliminary 10 5 External Clock Operation Timing 10 Table 10 13 External Clock Operation Timing Requirements Characteristic Symbol Min Typ Max Unit Frequency of operation external clock driver fosc 0 120 MHz Clock Pulse Width tpw 3 0 ns External clock input rise time trise 10 ns External clock input fall time tral 10 ns Parameters listed are guaranteed by design See Figure 10 3 for details on using the recommended connection of an external clock driver The high or low pulse width must be no smaller than 8 0ns or the chip will not function External clock input rise time is measured from 10 to 90 aR WDM E
123. es must be adjusted for the duty cycle at XTAL DCAOE and DCAEO are used to make this duty cycle adjustment where needed 56F8357 Technical Data Rev 15 Freescale Semiconductor 141 Preliminary DCAOE and DCAEO are calculated as follows DCAOE 0 5 MAX XTAL duty cycle if ZSRC selects prescaler clock and the prescaler is set to 1 0 0 all other cases MIN XTAL duty cycle 0 5 if ZSRC selects prescaler clock and the prescaler is set to 1 0 0 all other cases Example of DCAOE and DCAEO calculation DCAEO I Assuming prescaler is set for 1 and prescaler clock is selected by ZSRC if XTAL duty cycle ranges between 45 and 60 high DCAOE 50 60 0 1 DCAEO 45 50 0 05 The timing of write cycles is different when WWS 0 than when WWS gt 0 Therefore some parameters contain two sets of numbers to account for this difference Use the Wait States Configuration column of Table 10 16 to make the appropriate selection DO D15 Note During read modify write instructions and internal instructions the address lines do not change state Figure 10 4 External Memory Interface Timing Note When multiple lines are given for the same wait state configuration calculate each and then select the smallest or most negative 56F8357 Technical Data Rev 15 142 Freescale Semiconductor Preliminary External Memory Interface Timing Table 10 16 External Memory Interface T
124. escale Semiconductor Preliminary Table 4 5 Interrupt Vector Table Contents Continued Interrupt Vector Table Reserved Vector Priority Vector Base Peripheral Number Level Address Interrupt Function GPIOB 34 0 2 P 44 GPIOB GPIOA 35 0 2 P 46 GPIOA Reserved SPI1 38 0 2 P 4C SPI 1 Receiver Full SPI1 39 0 2 P 4E SPI 1 Transmitter Empty SPIO 40 0 2 P 50 SPI 0 Receiver Full SPIO 41 0 2 P 52 SPI 0 Transmitter Empty SCI1 42 0 2 P 54 SCI 1 Transmitter Empty SCH 43 0 2 P 56 SCI 1 Transmitter Idle Reserved SCI1 45 0 2 P 5A SCI 1 Receiver Error SCH 46 0 2 P 5C SCI 1 Receiver Full DEC1 47 0 2 P 5E Quadrature Decoder 1 Home Switch or Watchdog DEC1 48 0 2 P 60 Quadrature Decoder 1 INDEX Pulse DECO 49 0 2 P 62 Quadrature Decoder 0 Home Switch or Watchdog DECO 50 0 2 P 64 Quadrature Decoder 0 INDEX Pulse TMRD 52 0 2 P 68 Timer D Channel 0 TMRD 53 0 2 P 6A Timer D Channel 1 TMRD 54 0 2 P 6C Timer D Channel 2 TMRD 55 0 2 P 6E Timer D Channel 3 TMRC 56 0 2 P 70 Timer C Channel 0 TMRC 57 0 2 P 72 Timer C Channel 1 TMRC 58 0 2 P 74 Timer C Channel 2 TMRC 59 0 2 P 76 Timer C Channel 3 TMRB 60 0 2 P 78 Timer B Channel 0 TMRB 61 0 2 P 7A Timer B Channel 1 TMRB 62 0 2 P 7C Timer B Channel 2 TMRB 63 0 2 P 7E Timer B Channel 3 TMRA 64 0 2 P 80 Timer A Channel 0 TMRA 65 0 2 P 82 Timer
125. ess lines 1 1 Mode 1 External Boot Flash Memory is not secured EMI configuration is determined by the state of the EMI MODE pin 1 This bit is only configured at reset If the Flash secured state changes this will not be reflected in MB until the next reset 2 Changing MB in software will not affect Flash memory security Table 4 3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P space memory map configuration 1 Use external P space memory map configuration If MB 0 at reset changing this bit has no effect The device s external memory interface EMI can operate much like the 56F80x family s EMI or it can be operated in a mode similar to that used on other products in the 56800E family Initially CSO and CS1 are configured as PS and DS in a mode compatible with earlier 56800 devices Eighteen address lines are required to shadow the first 192K of internal program space when booting externally for development purposes Therefore the entire complement of on chip memory cannot be accessed using a 16 bit 56800 compatible address bus To address this situation the EMI MODE pin can be used to configure four GPIO pins as Address 19 16 upon reset Software reconfiguration ofthe highest address lines A20 23 is required if the full address range is to be used The EMI MODE pin also affects the reset vector address as provided in Table 4 4 Additional pins mus
126. et Register Description ADCA_LLMT 2 13 Low Limit Register 2 ADCA_LLMT 3 14 Low Limit Register 3 ADCA_LLMT 4 15 Low Limit Register 4 ADCA_LLMT 5 16 Low Limit Register 5 ADCA_LLMT 6 17 Low Limit Register 6 ADCA_LLMT 7 18 Low Limit Register 7 ADCA_HLMT 0 19 High Limit Register 0 ADCA_HLMT 1 1A High Limit Register 1 ADCA_HLMT 2 1B High Limit Register 2 ADCA_HLMT 3 1C High Limit Register 3 ADCA HLMT 4 1D High Limit Register 4 ADCA HLMT 5 1E High Limit Register 5 ADCA HLMT 6 1F High Limit Register 6 ADCA HLMT 7 20 High Limit Register 7 ADCA OFS 0 21 Offset Register 0 ADCA_OFS 1 22 Offset Register 1 ADCA_OFS 2 23 Offset Register 2 ADCA_OFS 3 24 Offset Register 3 ADCA_OFS 4 25 Offset Register 4 ADCA_OFS 5 26 Offset Register 5 ADCA_OFS 6 27 Offset Register 6 ADCA_OFS 7 28 Offset Register 7 ADCA_POWER 29 Power Control Register ADCA_CAL 2A ADC Calibration Register 56F8357 Technical Data Rev 15 62 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 21 Analog to Digital Converter Registers Address Map ADCB_BASE 00 F240 Register Acronym Address Offset Register Description ADCB_CR 1 0 Control Register 1 ADCB_CR 2 1 Control Register 2 ADCB_ZCC 2 Zero Crossing Control Register ADCB LST 1 3 Chann
127. evel 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 96 Freescale Semiconductor Preliminary Register Descriptions 5 6 10 4 Reload PWM B Interrupt Priority Level PWMB_RL IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 10 5 ADC A Zero Crossing or Limit Error Interrupt Priority Level ADCA_ZC IPL Bits 7 6 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 0 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 6 ADC B Zero Crossing or Limit Error Interrupt Priority Level ADCB ZC IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 7 ADC A Conversion Complete Interrupt Priority Level ADCA_CC IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default
128. f control bits is used for each pin 2 Reset configuration 3 Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins 56F8357 Technical Data Rev 15 116 Freescale Semiconductor Preliminary Register Descriptions Base B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read C3 C2 C1 CO Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 11 GPIO Peripheral Select Register SIM GPS 6 5 8 1 Reserved Bits 15 4 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 8 2 GPIOC3 C3 Bit 3 This bit selects the alternate function for GPIOC3 e 0 HOMEI TB3 default see Switch Matrix Mode bits of the Quad Decoder DECCR register in the 56F8300 Peripheral User Manual 1 SSI 6 5 8 3 GPIOC2 C2 Bit 2 This bit selects the alternate function for GPIOC2 0 INDEX1 TB2 default e MISOI 6 5 8 4 GPIOC1 C1 Bit 1 This bit selects the alternate function for GPIOCI e 0 PHASEBI TBI default 7MOSII 6 5 8 5 GPIOCO C0 Bit 0 This bit selects the alternate function for GPIOCO 0 PHASEALI TBO default e SCLKI 6 5 9 Peripheral Clock Enable Register SIM PCE The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings feature The clocks can be individually controlled for each peripheral on the chip
129. g Temperature Automotive and Max Ambient Operating Temperature Industrial in Table 10 4 Added RoHS compliance and pb free language to back cover Rev 13 0 Corrected Section 6 4 title from Operation Mode Register to Operating Mode Register Added information corrected state during reset in Table 2 2 Clarified external reference crystal frequency for PLL in Table 10 14 by increasing maximum value to 8 4MHz Rev 14 0 Replaced Tri stated with an explanation in State During Reset column in Table 2 2 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Document Revision History Continued Version History Description of Change Rev 15 Added the following note to the description of the TMS signal in Table 2 2 Note Always tie the TMS pin to Vpp through a 2 2K resistor Added the following note to the description of the TRST signal in Table 2 2 Note For normal operation connect TRST directly to Nee If the design is to be used in a debugging environment TRST may be tied to Vgg through a IK resistor Please see http www freescale com for the most current data sheet revision 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 56F8357 56F8157 General Description Note Features in italics are NOT available in the 56F8157 device Up to 60 MIPS at 60MHz core frequency Temperature Sensor DSP and MCU functionality
130. gister 4 CSBAR 5 5 Chip Select Base Address Register 5 CSBAR 6 6 Chip Select Base Address Register 6 CSBAR 7 7 Chip Select Base Address Register 7 56F8357 Technical Data Rev 15 50 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 10 External Memory Integration Registers Address Map Continued EMI_BASE 00 F020 Register Acronym Address Offset Register Description Reset Value CSOR 0 8 Chip Select Option Register 0 Ox5FCB programmed for chip select for program space word wide read and write 11 waits CSOR 1 9 Chip Select Option Register 1 Ox5FAB programmed for chip select for data space word wide read and write 11 waits CSOR 2 SA Chip Select Option Register 2 CSOR 3 B Chip Select Option Register 3 CSOR4 C Chip Select Option Register 4 CSOR 5 D Chip Select Option Register 5 CSOR 6 E Chip Select Option Register 6 CSOR7 F Chip Select Option Register 7 CSTC 0 10 Chip Select Timing Control Register 0 CSTC 1 11 Chip Select Timing Control Register 1 CSTC 2 12 Chip Select Timing Control Register 2 CSTC 3 13 Chip Select Timing Control Register 3 CSTC 4 14 Chip Select Timing Control Register 4 CSTC 5 15 Chip Select Timing Control Register 5 CSTC 6 16 Chip Select Timing Control Register 6 CSTC 7 17 Chip Select Timing Control Register 7 BCR 18 Bus Control Register 0x016B sets the default number of
131. h Pull Mode Register 0 x 1FFF GPIOD_RAWDATA A Raw Data Input Register Table 4 33 GPIOE Registers Address Map GPIOE_BASE 00 F330 Register Acronym Address Offset Register Description Reset Value GPIOE_PUR 0 Pull up Enable Register 0 x 3FFF GPIOE DR 1 Data Register 0 x 0000 GPIOE DDR 2 Data Direction Register 0 x 0000 GPIOE PER 3 Peripheral Enable Register 0 x 3FFF GPIOE_IAR 4 Interrupt Assert Register 0 x 0000 GPIOE_IENR 5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOE_IPR 7 Interrupt Pending Register 0 x 0000 GPIOE_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOE_PPMODE 9 Push Pull Mode Register 0 x 3FFF GPIOE RAWDATA A Raw Data Input Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Table 4 34 GPIOF Registers Address Map GPIOF_BASE 00 F340 Peripheral Memory Mapped Registers Register Acronym Address Offset Register Description Reset Value GPIOF_PUR 0 Pull up Enable Register 0 x FFFF GPIOF_DR 1 Data Register 0 x 0000 GPIOF_DDR 2 Data Direction Register 0 x 0000 GPIOF_PER 3 Peripheral Enable Register 0 x FFFF GPIOF_IAR 4 Interrupt Assert Register 0 x 0000 GPIOF_IENR 5 Interrupt Enable Register 0 x 0000 GPIOF IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOF IPR 7 Interrupt Pending Register 0 x 0000 GPIOF IESR 8 Interrupt Edge Sensitive Register 0 x 0000
132. he package and the interface material A clearance slot or hole is normally required in the heat sink Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink Because of the experimental difficulties with this technique many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface From this case temperature the junction temperature is determined from the junction to case thermal resistance 12 2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level Use the following list of considerations to assure correct operation e Provide a low impedance path from the board power supply to each Vpp pin on the hybrid controller and from the board ground to each Vgg GND pin e The minimum bypass requirement is to place six 0 01 0 1uF capacitors positioned as close as possible to the package supply pins The recommended bypass configuration is to place one bypass capacitor on each of the Vpp Vss p
133. i 121 ANB2 TXDO Pin 1 3 ANB1 RXDO 7 ANBO PHASEA1 C VESA ADC PHASEB1 1 VppA ape INDEX1 VREFH HOME1 4 Ver Al VREFMID A2 Cl VREFN A3 VREFLO Moo TEMP_SENSE A5 ANA7 Veap4 ANA6 Vpp io ANA5 A6 E ANA4 AT ANA3 A8 ANA2 A9 E ANA A10 31 ANAO AT CLKMODE A12 E RESET A13 E RSTO A14 Vpp io A15 FE vcap3 Vss EXTAL D E 4 XTAL D8 VDDA OSC PLL D9 OCR DIS Voto EE D6 D10 D5 GPIOBO D4 GPIOB1 FAULTA3 GPIOB2 D3 GPIOB3 FAULTA2 GPIOB4 FAULTA1 PWMBO 41 81 D2 PWMB1 FAULTAO PWMB2 CH 4 PWMAS e st iO Ok e e EN oem e WD Oe e Cl OO e Cl e MO NHN Oo st o SEET EEEETEEKEEE SCEEEEEECEEEEE 2z2zz2znnnt ttct aaooaoa gt ES 52 SS ZS ZS SE 000 00600000 iz aa RR fa Figure 11 1 Top View 56F8357 160 Pin LQFP Package 56F8357 Technical Data Rev 15 Freescale Semiconductor 159 Preliminary Table 11 1 56F8357 160 Pin LQFP Package Identification by Pin Number Pin No Fidi Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 Vpp i0 41 Vss 81 PWMA5 121 ANB5 2 Vpp2 42 Vpp io 82 FAULTAO 122 ANB6 3 CLKO 43 PWMB3 83 D2 123 ANB7 4 TXDO 44 PWMB4 84 FAULTA1 124 EXTBOOT 5 RXDO 45 PWMB5 85 FAULTA2 125 Vss 6 PHASEA1 46 GPIOB5 86 D3 126 ISAO 7 PHASEB1 47 GPIOB6 87 FAULTA3 127 ISA1 8 INDEX1 48 GPIOB7 88 D4 128 ISA2 9 HOME1 49 TXD1 89 D5 129 TDO 10 A1 50 RXD1 90 D6 130 TD1 11 A2 51 WR 91 OCR DIS 131 TD2
134. ification by Pin Number Continued SE Signal Name e Signal Name i Signal Name dn Signal Name J3 A15 P9 IRQB G14 ANA6 A6 SCLKO J4 Vss N9 FAULTBO E13 ANA7 D4 MISOO K1 D7 L9 FAULTB1 E11 TEMP_SENSE B6 MOSIO K3 D8 L10 FAULTB2 E12 VREFLO A5 D11 K2 D9 P10 DO F14 VREFN Ad D12 E5 Vpp Io N10 D1 E14 VngErMID B5 D13 K4 D10 P11 FAULTB3 D13 VREFP C4 D14 L1 GPIOBO M11 PWMAO D14 VREFH A3 D15 L3 GPIOB1 G11 Vss C14 Mona Apc C3 AO L2 GPIOB2 P12 PWMA1 D12 Vssa Apc A2 PHASEAO M1 GPIOB3 N11 PWMA2 C13 ANBO B4 PHASEBO M2 GPIOB4 E9 Vpp io B14 ANB1 A1 INDEXO N1 PWMBO M12 PWMA3 C12 ANB2 B3 HOMEO P1 PWMB1 P13 PWMA4 B13 ANB3 B2 EMI_MODE N2 PWMB2 E7 Vss A14 ANB4 E6 Vss 56F8357 Technical Data Rev 15 164 Freescale Semiconductor Preliminary 56F8357 Package and Pin Out Information X D gt LASER MARK FOR PIN 1 Y IDENTIFICATION IN THIS AREA M LN N NOTES DIMENSIONS ARE IN MILLIMETERS INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y 14 5M 1994 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z DATUM Z SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE gt gt gt MILLIMETE Rq DIM MIN MAX Aj0 20 A 1 32 1 75 Al 027 0 47 A2 1 18 REF b 0 35 0 65
135. imer D is NOT available in the 56F8157 device Register Acronym Address Offset Register Description TMRDO_CMP1 0 Compare Register 1 TMRDO_CMP2 1 Compare Register 2 TMRDO_CAP 2 Capture Register TMRDO_LOAD 3 Load Register TMRDO_HOLD 4 Hold Register TMRDO_CNTR 5 Counter Register TMRDO_CTRL 6 Control Register TMRDO_SCR 7 Status and Control Register TMRDO_CMPLD1 8 Comparator Load Register 1 TMRDO_CMPLD2 9 Comparator Load Register 2 TMRDO_COMSCR A Comparator Status and Control Register TMRD1_CMP1 10 Compare Register 1 TMRD1_CMP2 11 Compare Register 2 TMRD1_CAP 12 Capture Register TMRD1_LOAD 13 Load Register TMRD1_HOLD 14 Hold Register TMRD1_CNTR 15 Counter Register TMRD1_CTRL 16 Control Register TMRD1_SCR 17 Status and Control Register TMRD1_CMPLD1 18 Comparator Load Register 1 TMRD1_CMPLD2 19 Comparator Load Register 2 56F8357 Technical Data Rev 15 56 Freescale Semiconductor Preliminary Table 4 14 Quad Timer D Registers Address Map Continued Quad Timer D is NOT available in the 56F8157 device Peripheral Memory Mapped Registers TMRD_BASE 00 F100 Register Acronym Address Offset Register Description TMRD1_COMSCR 1A Comparator Status and Control Register TMRD2_CMP1 20 Compare Register 1 TMRD2_CMP2 21 Compare Register 2 TMRD2_CAP 22 Capture Register TMRD2_LOAD 23
136. iminary Register Descriptions 5 6 5 1 SPIO Receiver Full Interrupt Priority Level SPIO_RCV IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 5 2 SPIT1 Transmit Empty Interrupt Priority Level SPI1 XMIT IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 3 SPI1 Receiver Full Interrupt Priority Level SPI1 RCV IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 5 4 Reserved Bits 9 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 5 5 GPIOA Interrupt Priority Level GPIOA IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ
137. iming Characteristic Symbol Walt States D M Wait States Unit Configuration Controls WD WWS 0 1 477 0 50 Address Valid to WR Asserted a WWSS ns WWS gt 0 1 564 0 75 DCAOE WR Width Asserted to WR t WWS 0 0 186 10 25 DCAOE WWS WR ns Deasserted WWS gt 0 0 256 0 Data Out Valid to WR Asserted WWS 0 9 568 0 25 DCAEO WWS 0 1 721 0 00 tpwrR WWSS ns WWS gt 0 9 227 0 50 WWS gt 0 1 808 0 25 DCAOE Valid Data Out Hold Time after WR tpoH 2 287 0 25 DCAEO WWSH ns Deasserted Valid Data Out Set Up Time to vu 1 022 0 49 DEAE ses E WR Deasserted 9 041 0 50 i F ES t Valid Address after WR WAG 3 918 0 25 DCAEO WWSH ns Deasserted RD Deasserted to Address Invalid roa 2 229 0 00 RWSH ns Address Valid to RD Deasserted tARDD 1 887 1 00 RWSS RWS ns Valid Input Data Hold after RD ORD 0 00 N A ENT ns Deasserted RD Assertion Width trp 0 212 1 00 RWS ns Address Valid to Input Data Valid Aen ines 1200 ss os 19 751 1 25 DCAOE i Address Valid to RD Asserted tARDA 2 121 0 00 RWSS ns RD Asserted to Input Data Valid a 12 306 1 00 En 17 630 1 25 DCAOE RWSS RWS WR Deasserted to RD Asserted twRRD 1 923 0 25 DCAEO WWSH RWSS ns Dn Dn RWSS RWSH RD Deasserted to RD Asserted t 2 0 00 ns RDRD 0 234 MDARS 4 UB UD WWS 0 1 279 0 75 DCAEO WR Deasserted to WR Asserted ARNG WWSS WWSH ns WWS gt 0 0 938 1 00 RD Deasserted to WR Asserted p dde 0 046 0
138. ing Functional Description serviced The following tables define the nesting requirements for each priority level Table 5 1 Interrupt Mask Bit Definition SR 9 SR 8 Permitted Exceptions Masked Exceptions 0 0 Priorities O 1 2 3 None 0 1 Priorities 1 2 3 Priority 0 1 0 Priorities 2 3 Priorities O 1 1 1 Priority 3 Priorities 0 1 2 1 Core status register bits indicating current interrupt mask within the core Table 5 2 Interrupt Priority Encoding 1 Current Interrupt Priority Required Nested IPIC_LEVEL 1 0 Level Exception Priority 00 No Interrupt or SWILP Priorities 0 1 2 3 01 Priority 0 Priorities 1 2 3 01 Priority 1 Priorities 2 3 11 Priorities 2 or 3 Priority 3 1 See IPIC field definition in Part 5 6 30 2 5 3 3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual The interrupt controller recognizes fast interrupts before the core does A fast interrupt is defined to the ITCN by 1 Setting the priority of the interrupt as level 2 with the appropriate field in the IPR registers 2 Setting the FIMn register to the appropriate vector number 3 Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt When an interrupt occurs its vector number is compared with the FIMO and FIM register values If a match occurs and it is a level 2 interrupt the ITCN handles it as a fast i
139. ion Descriptions to see which signals are multiplexed with those of other peripherals Also shown in Figure 1 2 are connections between the PWM Timer C and ADC blocks These connections allow the PWM and or Timer C to control the timing of the start of ADC conversions The Timer C channel indicated can generate periodic start SYNC signals to the ADC to start its conversions In another operating mode the PWM load interrupt SYNC output signal is routed internally to the Timer C input channel as indicated The timer can then be used to introduce a controllable delay before generating its output signal The timer output then triggers the ADC To fully understand this interaction please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals 56F8357 Technical Data Rev 15 Freescale Semiconductor 11 Preliminary 5 zc JTAG EOnCE pe ede pe L M pdb m 15 0 e Program pab 20 0 Flash Program cdbw_m 31 0 we RAM 56800E 24 CHIP lt Address TAP GET EMI 16 Controller ra z Data zi 10 L Control TAP gt Linking o gt Module xab1 23 0 4 Data RAM xab2 23 0 gt External Ba Data Flash JTAG Port gt cdbr_m 31 0 Leg xdb2 m 15 0 a t To Fla
140. iority level 1 e 11 IRQ is priority level 2 5 6 6 2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level DEC1_HIRQ IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 56F8357 Technical Data Rev 15 88 Freescale Semiconductor Preliminary Register Descriptions 5 6 6 3 SCI1 Receiver Full Interrupt Priority Level SCI1 RCV IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 6 4 SCI1 Receiver Error Interrupt Priority Level SCI1 RERR IPL Bits 9 8 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 5 Reserved Bits 7 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 6 6 SCI1 Transmitter Idle Interrupt Priority Level SCI1 TIDL IPL Bits 5 4 This fie
141. is field is used to set the interrupt priority levels for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 10 IRQ is priority level 2 11 IRQ is priority level 3 5 6 1 3 EOnCE Step Counter Interrupt Priority Level STPCNT IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 0 IRQ is priority level 2 11 IRQ is priority level 3 5 6 1 4 Reserved Bits 9 0 This bit field 1s reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 2 Interrupt Priority Register 1 IPR1 Base 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read uU U 0 0 0 uU 0 0 uU 0 RX_REG IPL TX_REGIPL TRBUF IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 4 Interrupt Priority Register 1 IPR1 56F8357 Technical Data Rev 15 Freescale Semiconductor 81 Preliminary 5 6 2 1 Reserved Bits 15 6 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 2 2 EOnCE Receive Register Full Interrupt Priority Level RX_REG IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It i
142. is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 87 Preliminary 5 6 5 6 GPIOB Interrupt Priority Level GPIOB IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 5 7 GPIOC Interrupt Priority Level GPIOC IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 11 IRQ is priority level 2 5 6 6 Interrupt Priority Register 5 IPR5 Base 5 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 Read DEC1 XIRQ DEC1 HIRQ SCM RCV scn SCH SMIT Sp SMIT Write IPL IPL IPL IPL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5 8 Interrupt Priority Register 5 IPR5 5 6 6 1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level DEC1 XIRQ IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is pr
143. it 3 If 1 the EXTR bit indicates an external system reset has occurred This bit will be cleared by a Power On Reset or by software Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it Basically when the EXTR bit is 1 the previous system reset was caused by the external RESET pin being asserted low 6 5 2 5 Power On Reset POR Bit 2 When 1 the POR bit indicates a Power On Reset occurred some time in the past This bit can be cleared only by software or by another type of reset Writing a 0 to this bit will set the bit while writing a 1 to the bit position will clear the bit In summary if the bit is 1 the previous system reset was due to a Power On Reset 6 5 2 6 Reserved Bits 1 0 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 3 SIM Software Control Registers SIM SCRO SIM SCR SIM SCR2 and SIM SCR3 Only SIM SCRO is shown below SIM SCRI SIM SCR2 and SIM SCR3 are identical in functionality Base 2 15 14 13 12 11 10 9 8 Th 6 5 4 3 2 1 0 Read FIELD Write POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 5 SIM Software Control Register 0 SIM SCRO 56F8357 Technical Data Rev 15 Freescale Semiconductor 111 Preliminary 6 5 3 1 Software Control Data 1 FIELD Bits 15 0 This register is reset only by the Power On Reset POR It has no par
144. iting Stop tip FAST IRQA Width Assertion to Recover from Stop tiw 1 5T ns 10 9 State In the formulas T clock cycle For an operating frequency of 60MHz T 16 67ns At 8 MHz used during Reset and Stop modes T 125ns 2 Parameters listed are guaranteed by design 3 During Power On Reset it is possible to use the device s internal reset stretching circuitry to extend this period to 2217 4 The minimum is specified for the duration of an edge sensitive IRQA interrupt required to recover from the Stop state This is not the minimum required so that the IRQA interrupt is accepted 5 The interrupt instruction fetch is visible on the pins only in Mode 3 56F8357 Technical Data Rev 15 144 Freescale Semiconductor Preliminary Reset Stop Wait Mode Select and Interrupt Timing RESET traz F troa A0 A15 D0 D15 First Fetch PS DS N RD WR First Fetch Figure 10 5 Asynchronous Reset Timing igw Figure 10 6 External Interrupt Timing Negative Edge Sensitive A0 A15 PS DS First Interrupt Instruction Execution RD WR a First Interrupt Instruction Execution General 4 Purpose I O Pin 3 tic IRQA IRQB L4 b General Purpose I O Figure 10 7 External Level Sensitive Interrupt Timing 56F8357 Technical Data Rev 15 Freescale Semiconductor 145 Preliminary First Interrupt Vec
145. lar Figure 6 16 Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions Both put the CPU to sleep For lowest power consumption in Stop mode the PLL can be shut down This must be done explicitly before entering Stop mode since there is no automatic mechanism for this When the PLL is shut down the 56800E system clock must be set equal to the oscillator output 56F8357 Technical Data Rev 15 122 Freescale Semiconductor Preliminary Resets Some applications require the 56800E STOP and WAIT instructions be disabled To disable those instructions write to the SIM control register SIM CONTROL described in Part 6 5 1 This procedure can be on either a permanent or temporary basis Permanently assigned applications last only until their next reset 6 9 Resets The SIM supports four sources of reset The two asynchronous sources are the external RESET pin and the Power On Reset POR The two synchronous sources are the software reset which is generated within the SIM itself by writing to the SIM CONTROL register and the COP reset Reset begins with the assertion of any of the reset sources Release of reset to various blocks is sequenced to permit proper operation of the device A POR reset is first extended for 2 clock cycles to permit stabilization of the clock source followed by a 32 clock window in which SIM clocking is initiated It is then followed by a 32 clock window in which peripherals are relea
146. ld is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 6 7 SCI Transmitter Empty Interrupt Priority Level SCI1 XMIT IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 89 Preliminary 5 6 6 8 SPIO Transmitter Empty Interrupt Priority Level SPI_XMIT IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 4 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 Interrupt Priority Register 6 IPR6 Base 6 SA RECS alala 0 Read 0 0 LLL TMROO IPL TMRD3 IPL TMRD2 IPL TMRD1 IPL TMRDO IPL ae aa dde Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 9 Interrupt Priority Register 6 IPR6 5 6 7 1 Timer C Channel 0 Interrupt Priority Level TMRCO IPL Bits 15 14 This field is used to set the interrupt
147. le 4 1 Chip Memory Configurations On Chip Memory 56F8357 56F8157 Use Restrictions Program Flash 256KB 256KB Erase Program via Flash interface unit and word writes to CDBW Data Flash 8KB Erase Program via Flash interface unit and word writes to CDBW Data Flash can be read via one of CDBR or XDB2 but not both simultaneously Program RAM 4KB None Data RAM 16KB 16KB None Program Boot Flash 16KB 16KB Erase Program via Flash Interface unit and word to CDWB 56F8357 Technical Data Rev 15 Freescale Semiconductor 41 Preliminary 4 2 Program Map The operating mode control bits MA and MB in the Operating Mode Register OMR control the Program memory map At reset these bits are set as indicated in Table 4 2 Table 4 4 shows the memory map configurations that are possible at reset After reset the OMR MA bit can be changed and will have an effect on the P space memory map as shown in Table 4 3 Changing the OMR MB bit will have no effect Table 4 2 OMR MB MA Value at Reset OMR MB OMR MA Flash Secured n i i ep EXTBOOT Pin Chip Operating Mode State 0 0 Mode 0 Internal Boot EMI is configured to use 16 address lines Flash Memory is secured external P space is not allowed the EOnCE is disabled 0 1 Not valid cannot boot externally if the Flash is secured and will actually configure to 00 state 1 0 Mode 0 Internal Boot EMI is configured to use 16 addr
148. lease see CodeWarrior MC56F83xx DSP5685x Family Targeting Manual The LOCKOUT RECOVERY instruction will have an associated 7 bit Data Register DR that is used to control the clock divider circuit within the FM module This divider FM CLKDIV 6 0 is used to control the period of the clock used for timed events in the FM erase algorithm This register must be set with appropriate values before the lockout sequence can begin Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value 56F8357 Technical Data Rev 15 124 Freescale Semiconductor Preliminary Flash Access Blocking Mechanisms The value of the JTAG FM_CLKDIV 6 0 will replace the value of the FM register FMCLKD that divides down the system clock for timed events as illustrated in Figure 7 1 FM_CLKDIV 6 will map to the PRDIVS bit and FM CLKDIV 5 0 will map to the DIV 5 0 bits The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz 200kHz The Writing the FMCLKD Register section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values Flash Memory SYS_CLK input DIVIDER 2 clock A 7 FMCLKD I EE 7 FM CLKDIV T JTAG 7 l FM_ERASE A Figure 7 1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow EXAMPLE 1 If
149. me disabled inputs and an external device is enabled onto the data bus pull up is When RD is deasserted high the external data is latched enabled inside the device When RD is asserted it qualifies the AO A23 PS DS and CSn pins RD can be connected directly to the OE pin of a static RAM or ROM Depending upon the state of the DRV bit in the EMI bus control register BCR RD is tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting To deactivate the internal pull up resistor set the CTRL bit in the SIM_PUDR register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 25 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset WR 51 L4 Output In reset Write Enable WR is asserted during external memory write output is cycles When WR is asserted low pins DO D15 become disabled outputs and the device puts data on the bus When WR is pull up is deasserted high the external data is latched inside the enabled external device When WR is asserted it qualifies the AO A23 PS DS and CSn pins WR can be connected directly to the WE pin of a static RAM Depending upon the state of the DRV bit in the EMI bus control register BCR WR is tri stated when the external bus is inactive
150. minary Table 1 2 Bus Signal Names Name Function Program Memory Interface pdb m 15 0 Program data bus for instruction word fetches or read operations cdbw 15 0 Primary core data bus used for program memory writes Only these 16 bits of the cdbw 31 0 bus are used for writes to program memory pab 20 0 Program memory address bus Data is returned on pdb_m bus Primary Data Memory Interface Bus cdbr_m 31 0 Primary core data bus for memory reads Addressed via xab1 bus cdbw 31 0 Primary core data bus for memory writes Addressed via xab1 bus xab1 23 0 Primary data address bus Capable of addressing bytes words and long data types Data is written on cdbw and returned on cdbr_m Also used to access memory mapped UO Secondary Data Memory Interface xdb2_m 15 0 Secondary data bus used for secondary data address bus xab2 in the dual memory reads xab2 23 0 Secondary data address bus used for the second of two simultaneous accesses Capable of addressing only words Data is returned on xdb2_m Peripheral Interface Bus IPBus 15 0 Peripheral bus accesses all on chip peripherals registers This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor Write data is obtained from cdbw Read data is provided to cdbr_m 1 Byte accesses can only occur in the bottom half of the memory address spac
151. mpliant and an internal interrupt controller are a part of the 56F8357 1 2 2 56F8157 Features The 56F8157 controller includes 256KB of Program Flash programmable through the JTAG port with 16KB of Data RAM It also supports program execution from external memory A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field programmable software routines that can be used to program the main Program Flash memory area which can be independently bulk erased or erased in pages Program Flash page erase size is 1KB Boot Flash page erase size is 512 bytes and the Boot Flash memory can also be either bulk or page erased 56F8357 Technical Data Rev 15 Freescale Semiconductor 9 Preliminary A key application specific feature of the 56F8157 is the inclusion of one Pulse Width Modulator PWM module This module incorporates three complementary individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality Complementary operation permits programmable dead time insertion distortion correction via current sensing by software and separate top and bottom output polarity control The up counter value is programmable to support a continuously variable PWM frequency Edge aligned and center aligned synchronous pulse width control 0 to 100 modulation is supported The device is capable of controlling most motor types ACIM AC Induction Motors both
152. n provides a Input high reset signal to the JTAG TAP controller To ensure complete internally hardware reset TRST should be asserted whenever RESET is asserted The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG EOnCE module must not be reset In this case assert RESET but do not assert TRST To deactivate the internal pull up resistor set the JTAG bit in the SIM PUDR register Note For normal operation connect TRST directly to Vss If the design is to be used in a debugging environment TRST may be tied to Vss through a 1K resistor PHASEAO 155 A2 Schmitt Input Phase A Quadrature Decoder 0 PHASEA input Input pull up enabled TAO Schmitt TAO Timer A Channel 0 Input Output GPIOC4 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output After reset the default state is PHASEAO To deactivate the internal pull up resistor clear bit 4 of the GPIOC_PUR register PHASEBO 156 B4 Schmitt Input Phase B Quadrature Decoder 0 PHASEB input Input pull up enabled TA1 Schmitt TA1 Timer A Channel Input Output GPIOC5 Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output After reset the default state is PHASEBO To deactivate the internal pull up resistor clear bit 5 of the GPIOC_PUR register 56F8357 Technical Data Rev 15 Fr
153. n this mode the 56800E controls chip operation Debug Mode The 56800E is controlled via JTAG EOnCE when in debug mode All peripherals except the COP and PWMs continue to run COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven see the PWM chapter in the 56F8300 Peripheral User Manual for details Wait Mode In Wait mode the core clock and memory clocks are disabled Optionally the COP can be stopped Similarly it is an option to switch off PWM outputs to disable any motor from being driven All other peripherals continue to run Stop Mode When in Stop mode the 56800E core memory and most peripheral clocks are shut down Optionally the COP and CAN can be stopped For lowest power consumption in Stop mode the PLL can be shut down This must be done explicitly before entering Stop mode since there is no automatic mechanism for this The CAN along with any non gated interrupt is capable of waking the chip up from Stop mode but is not fully functional in Stop mode Operating Mode Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NL CM XP SD R SA EX U MB MA Type R W RW RW RW RW RW RW RW R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X Figure 6 1 OMR The reset state for MB and MA will depend on the Flash secured state See Part 4 2 and Part 7 for detailed information on how the Operating Mode Register
154. nal pull up resistor clear bit 9 in the GPIOD PUR register 56F8357 Technical Data Rev 15 26 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin plate Nama No Ball No Type During Signal Description Reset GPIODO 55 P6 Input Input Port D GPIO These six GPIO pins can be individually Output pull up programmed as input or output pins enabled CS2 Output Chip Select CS2 CS7 may be programmed within the EMI module to act as chip selects for specific areas of the external GPIOD1 56 L6 memory map CS3 Depending upon the state of the DRV bit in the EMI Bus GPIOD2 57 K6 Control Register BCR CS2 CS7 are tri stated when the CS4 external bus is inactive esp Se NE Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOD4 59 P7 CS6 At reset these pins are configured as GPIO GPIOD5 60 L7 To deactivate the internal pull up resistor clear the appropriate CS7 GPIO bit in the GPIOD_PUR register Example GPIODO clear bit 0 in the GPIOD_PUR register TXDO 4 B1 Output In reset Transmit Data SCIO transmit data output output is GPIOE0 Input disabled Port E GPIO This GPIO pin can be individually Output pull up is programmed as an input or output pin enabled After reset the default state is SCI output To deactivate the internal pull up resistor
155. ned from the equation T Ta Rega x Po where TA Ambient temperature for the package C Roya Junction to ambient thermal resistance C W Pp Power dissipation in the package W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance Unfortunately there are two values in common usage the value determined on a single layer board and the value obtained on a board with two planes For packages such as the PBGA these values can be different by a factor of two Which value is closer to the application depends on the power dissipated by other components on the board The value obtained on a single layer board is appropriate for the tightly packed printed circuit board The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated When a heat sink is used the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Roja RoJc Reca where Roja Package junction to ambient thermal resistance C W Ru Package junction to case thermal resistance C W Reca Package case to ambient thermal resistance C W R oic is device related and cannot be influenced by the user The user controls the thermal environment to change the case to ambient thermal resistance R eca For instance th
156. ngs may affect device reliability or cause permanent damage to the device Note All specifications meet both Automotive and Industrial requirements unless individual specifications are listed Note The 56F8157 device is guaranteed to 40MHz and specified to meet Industrial requirements only CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level 56F8357 Technical Data Rev 15 Freescale Semiconductor 131 Preliminary Note The 568157 device is specified to meet Industrial requirements only CAN is NOT available on the 56F 8157 device Table 10 1 Absolute Maximum Ratings Vss Vssa anc 0 Characteristic Symbol Notes Min Max Unit Supply Voltage Vpp o 0 3 4 0 V ADC Supply Voltage VDDA ADC VREFH must be less than or equal 0 3 4 0 V VREFH to VppA Apc Oscillator PLL Supply Voltage VppA osc PLL 0 3 4 0 V Internal Logic Core Supply Voltage Vop coRE OCR DIS is High 0 3 3 0 V Input Voltage digital ViN Pin Groups 1 2 5 6 9 10 0 3 6 0 V Input Voltage analog VINA Pin Groups 11 12 13 0 3 4 0 V Output Voltage Vout Pin Groups 1 2 3 5 6 7 8 0 3 4 0 V
157. nical Data Rev 15 162 Freescale Semiconductor Preliminary 56F8357 Package and Pin Out Information Table 11 2 56F8357 160 MAPBGA Package Identification by Pin Number Rm Signal Name FR Signal Name n Signal Name Fe Signal Name F4 Vpp Io K11 Vss N12 PWMA5 A13 ANB5 C2 Vpp2 K7 Vpp Io N13 FAULTAO B12 ANB6 D3 CLKO N3 PWMB3 P14 D2 A12 ANB B1 TXDO P2 PWMB4 N14 FAULTA1 B11 EXTBOOT D2 RXDO M3 PWMB5 M13 FAULTA2 J11 Vss C1 PHASEA1 N4 GPIOB5 L13 D3 A11 ISAO D1 PHASEB1 P3 GPIOB6 M14 FAULTA3 C11 ISA1 E2 INDEX1 M4 GPIOB7 L14 D4 D11 ISA2 E1 HOME1 P4 TXD1 L12 D5 B10 TDO E3 A1 N5 RXD1 L11 D6 A10 TD1 E4 A2 L4 WR K14 OCR_DIS D10 TD2 F2 A3 P5 RD K13 Vppa osc pLL E10 TD3 F1 A4 N6 PS K12 XTAL A9 TCO F3 A5 L5 DS J12 EXTAL EI Vpp io G4 Veapt P6 GPIODO H11 Vcap3 B9 TC1 K5 Vpp lo L6 GPIOD1 K10 Vpp io D9 TRST G1 A6 K6 GPIOD2 J13 RSTO D8 TCK G3 A7 N7 GPIOD3 J14 RESET A8 TMS G2 A8 P7 GPIOD4 H12 CLKMODE B8 TDI H1 A9 L7 GPIOD5 G13 ANAO D7 TDO H2 A10 N8 ISBO H13 ANA1 AT Vpp1 H4 A11 K8 Vcap1 G12 ANA2 D6 CAN TX H3 A12 L8 ISB1 F13 ANA3 B7 CAN_RX J1 A13 P8 ISB2 F12 ANA4 E8 Vcap2 J2 A14 K9 IRQA H14 ANAS D5 sso When the on chip regulator is disabled these four pins become 2 5V Vpp cong 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 163 Table 11 2 56F8357 160 MAPBGA Package Ident
158. nput Input SPI 0 Slave Select SSO is used in slave mode to indicate to pull up the SPI module that the current transfer is to be received enabled GPIOE7 Input Port E GPIO This GPIO pin can be individually Output programmed as input or output pin After reset the default state is SSO To deactivate the internal pull up resistor clear bit 7 in the GPIOE_PUR register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 31 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset PHASEA1 6 C1 Schmitt Input Phase A1 Quadrature Decoder 1 PHASEA input for Input pull up decoder 1 enabled TBO Schmitt TBO Timer B Channel 0 Input Output SCLK1 Schmitt SPI 1 Serial Clock In the master mode this pin serves as Input an output clocking slaved listeners In slave mode this pin Output serves as the data clock input To activate the SPI function set the PHSA ALT bit in the SIM GPS register For details see Part 6 5 8 GPIOCO Schmitt Port C GPIO This GPIO pin can be individually Input programmed as an input or output pin Output In the 56F8357 the default state after reset is PHASEA1 In the 56F8157 the default state is not one of the functions offered and must be reconfigured To deactivate the internal pull up resistor clear bit O in the GPIOC PUR register P
159. nput Input On Chip Regulator Disable Tie this pin to Vss to enable the on chip regulator Tie this pin to Vpp to disable the on chip regulator This pin is intended to be a static DC signal from power up to shut down Do not try to toggle this pin for power savings during operation VcaAp1 62 K8 Supply Supply VcAp1 4 When OCR DIS is tied to Vss regulator enabled connect each pin to a 2 2uF or greater bypass Vcap2 144 E8 capacitor in order to bypass the core logic voltage regulator required for proper chip operation When OCR DIS is tied to Vcap3 95 H11 Vpp regulator disabled these pins become Vpp core and should be connected to a regulated 2 5V power supply VcAp4 15 G4 Note This bypass is required even if the chip is powered with an external supply When the on chip regulator is disabled these four pins become 2 5V Vpp cong Vpp1 141 AT Input Input Vpp1 2 These pins should be left unconnected as an open circuit for normal functionality Vpp2 2 C2 CLKMODE 99 H12 Input Input Clock Input Mode Selection This input determines the function of the XTAL and EXTAL pins 1 External clock input on XTAL is used to directly drive the input clock of the chip The EXTAL pin should be grounded 0 A crystal or ceramic resonator should be connected between XTAL and EXTAL EXTAL 94 J12 Input Input External Crystal Oscillator Input This input can be connected to an 8MHz external crystal Tie this pin low if XTAL is driven by
160. nterrupt The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers instead of generating an address that is an offset from the VBA The core then fetches the instruction from the indicated vector adddress and if it is not a JSR the core starts its fast interrupt handling 56F8357 Technical Data Rev 15 Freescale Semiconductor 77 Preliminary 5 4 Block Diagram 5 5 anyO Priority gt Level y Level Kei 82 gt 7 Priority 7 INT1 __ 274 7 Encoder 7 Decode H l L LS INT p lp VAB CONTROL Ll IPIC Y m any3 P Level3 Priority um Level 82 27 IACK Priority 7 SR 9 8 Encoder 7 l PIC_EN INT82__ 2 gt 4 CC Z Decode 4 Figure 5 1 Interrupt Controller Block Diagram Operating Modes The ITCN module design contains two major modes of operation Functional Mode The ITCN is in this mode by default Wait and Stop Modes During Wait and Stop modes the system clocks and the 56800E core are turned off The ITCN will signal a pending IRQ to the System Integration Module SIM to restart the clocks and service the IRQ An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode Also the IRQA and IRQB signals automatically become low level sensitive in these modes even if the control register
161. nterrupt controller is also a part of the 56F8157 1 3 Award Winning Development Environment Processor Expert M PE provides a Rapid Application Design RAD tool that combines easy to use component based software application creation with an expert knowledge system The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation compiling and debugging A complete set of evaluation modules EVMs and development system cards will support concurrent engineering Together PE CodeWarrior and EVMs create a complete scalable tools solution for easy fast and efficient development 56F8357 Technical Data Rev 15 10 Freescale Semiconductor Preliminary Architecture Block Diagram 1 4 Architecture Block Diagram Note Features in italics are NOT available in the 56F8157 device and are shaded in the following figures The 56F8357 56F8157 architecture is shown in Figure 1 1 and Figure 1 2 Figure 1 1 illustrates how the 56800E system buses communicate with internal memories the external memory interface and the IPBus Bridge Table 1 2 lists the internal buses in the 56800E architecture and provides a brief description of their function Figure 1 2 shows the peripherals and control blocks connected to the IPBus Bridge The figures do not show the on board regulator and power and ground signals They also do not show the multiplexing between peripherals or the dedicated GPIOs Please see Part 2 Signal Connect
162. nterrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 4 IRQ is priority level 0 e 10 IRQ is priority level 1 e l IRQ is priority level 2 5 6 4 6 FlexCAN Error Interrupt Priority Level FCERR IPL Bits 5 4 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQis priority level 0 e 0 IRQ is priority level 1 e l IRQ is priority level 2 5 6 4 7 FlexCAN Bus Off Interrupt Priority Level FCBOFF IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e l IRQ is priority level 2 5 6 4 8 Reserved Bits 1 0 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 5 Interrupt Priority Register 4 IPR4 Base 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SPIO RCV SPI1_XMIT SPI1_RCV 0 0 0 0 GPIOA GPIOB GPIOC Write IPL IPL IPL PL IPL IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 7 Interrupt Priority Register 4 IPR4 56F8357 Technical Data Rev 15 86 Freescale Semiconductor Prel
163. numbers do not always correlate in Table 2 2 Please contact factory for exact correlation Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset Vpp lo 1 F4 Supply UO Power This pin supplies 3 3V power to the chip UO interface and also the Processor core throught the on chip Vpp 10 16 K5 voltage regulator if it is enabled Vpp io 31 E5 Vpp io 42 K7 Vpp 10 77 E9 Vpp 10 96 K10 Vpp wo 134 F11 VpDA ADC 114 C14 Supply ADC Power This pin supplies 3 3V power to the ADC modules It must be connected to a clean analog power supply VppA osc 92 K13 Supply Oscillator and PLL Power This pin supplies 3 3V power to PLL the OSC and to the internal regulator that in turn supplies the Phase Locked Loop It must be connected to a clean analog power supply 56F8357 Technical Data Rev 15 Freescale Semiconductor 19 Preliminary Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Nama No Ball No Type During Signal Description Reset Vss 27 J4 Supply Vss These pins provide ground for chip logic and UC drivers Vss 41 K11 Vss 74 G11 Vss 80 E7 Vss 125 J11 Vss 160 E6 VssA ADC 115 D12 Supply ADC Analog Ground This pin supplies an analog ground to H the ADC modules OCR DIS 91 K14 I
164. o http www freescale com epp nformation in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life o
165. ory chapter of the 56F8300 Peripheral User Manual These configuration parameters are located between 01_FFF7 and 01_FFFF Program Memory Data Memory BOOT_FLASH_START 1FFF 16KB FM BASE 14 Banked Registers Boot Unbanked Registers BOOT FLASH START 02 0000 FM BASE 00 i PROG FLASH START 01 FFFF PROG FLASH START 01 FFF7 PROG FLASH START 01 FFF6 Configure Field 7 FM PROG MEM TOP 01 FFFF DATA FLASH START 0FFF 128KB 8KB Program DATA_FLASH_START 0000 BLOCK 1 Odd 2 Bytes 01_0003 Note ae ees Po ytes 01_ BLOCK 1 Even 2 Bytes 01 0002 NOT available in the BLOCK 1 Odd 2 Bytes 01 0001 56F8157 device PROG_FLASH_START 01_0000 BLOCK 1 Even 2 Bytes 01_0000 PROG_FLASH_START 00_FFFF 128KB Program IR BLOCK 0 Odd 2 Bytes 00 0003 BLOCK 0 Even 2 Bytes 00_0002 IR BLOCK 0 Odd 2 Bytes 00_0001 PROG_FLASH_START 00_0000 BLOCK 0 Even 2 Bytes 00_0000 Figure 4 1 Flash Array Memory Maps Table 4 7 shows the page and sector sizes used within each Flash memory block on the chip Note Data Flash is NOT available on the 56F8157 device 56F8357 Technical Data Rev 15 Freescale Semiconductor 47 Preliminary Table 4 7 Flash Memory Partitions Flash Size Sectors Sector Size Page Size Program Flash 256KB 16 8K x 16 bits 512 x 16 bits Data Flash 8KB 16 256 x 16 bits 256 x 16 bits Boot Flash 16KB 4 2K x 16
166. ot accessible in reset configuration since the address is above P 00 FFFF The higher bit address GPIO and or chip selects pins must be reconfigured before this external memory is accessible o A OU N gt 6 Booting from this external address allows prototyping of the internal Boot Flash 7 Two independent program Flash blocks allow one to be programmed erased while executing from another Each block must have its own mass erase 4 3 Interrupt Vector Table Table 4 5 provides the reset and interrupt priority structure including on chip peripherals The table is organized with higher priority vectors at the top and lower priority interrupts lower in the table The priority of an interrupt can be assigned to different levels as indicated allowing some control over interrupt priorities All level 3 interrupts will be serviced before level 2 and so on For a selected priority level the lowest vector number has the highest priority The location of the vector table is determined by the Vector Base Address VBA register Please see Part 5 6 11 for the reset value of the VBA In some configurations the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table In these instances the first two locations in the vector table must contain branch or JMP instructions All other entries must contain JSR instructions 56F8357 Technical Data Rev 15 Freescale Semiconductor 43 Preliminary Note
167. ot implemented It is read as 0 and cannot be modified by writing 6 5 6 11 CTRL Bit 5 DE ER This bit controls the pull up resistors on the WR and RD pins 6 5 6 12 Reserved Bit 4 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 6 5 6 13 JTAG Bit 3 This bit controls the pull up resistors on the TRST TMS and TDI pins 6 5 6 14 Reserved Bits 2 0 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 6 5 7 CLKO Select Register SIM_CLKOSR The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules The default value is SYS_CLK All other clocks primarily muxed out are for test purposes only and are subject to significant phase shift at high frequencies 56F8357 Technical Data Rev 15 Freescale Semiconductor 113 Preliminary The upper four bits of the GPIOB register can function as GPIO A 23 A20 or as additional clock output signals GPIO has priority and is enabled disabled via the GPIOB_PER If GPIOB 7 4 are programmed to operate as peripheral outputs then the choice between A 23 A20 and additional clock outputs is done here in the CLKOSR The default state is for the peripheral function of GPIOB 7 4 to be programmed as A 23 A20 This can be changed by altering A 23 A20 as shown in Figure 6 9 Base A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
168. pheral User Manual for further details 6 7 Power Down Modes Overview The 56F8357 56F8157 operate in one of three power down modes as shown in Table 6 3 56F8357 Technical Data Rev 15 Freescale Semiconductor 121 Preliminary Table 6 3 Clock Operation in Power Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory Active Peripherals are active and can produce interrupts if they clocks disabled have not been masked off Interrupts will cause the core to come out of its suspended state and resume normal operation Typically used for power conscious applications Stop System clocks continue to be generated in The only possible recoveries from Stop mode are the SIM but most are gated prior to 1 CAN traffic 1st message will be lost reaching memory core and peripherals 2 Non clocked interrupts 3 COP reset 4 External reset 5 Power on reset All peripherals except the COP watchdog timer run off the IPBus clock frequency which is the same as the main processor frequency in this architecture The maximum frequency of operation is SYS_CLK 60MHz 6 8 Stop and Wait Mode Disable Function Permanent E Disable AD Q D FLOP C 56800E Reprogrammable e ES STOP DIS Disable D Qa E D FLOP Clock C Select fe R Note Wait disable circuit Reset is simi
169. power vs fast restart must be explicitly done Wait mode shuts down the 56800E core and unnecessary system clock operation Run mode supports full part operation Controls to enable disable the 56800E core WAIT and STOP instructions Calculates base delay for reset extension based upon POR or RESET operations Reset delay will be either 3 x 32 clocks for reset exept for POR which is 2 clock cycles Controls reset sequencing after reset Software initiated reset Four 16 bit registers reset only by a Power On Reset usable for general purpose software control System Control Register Registers for software access to the JTAG ID of the chip 56F8357 Technical Data Rev 15 106 Freescale Semiconductor Preliminary 6 3 Operating Modes Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip it must understand the various chip operating modes and take appropriate action These are 6 4 Reset Mode which has two submodes POR and RESET operation The 56800E core and all peripherals are reset This occurs when the internal POR is asserted or the RESET pin is asserted COP reset and software reset operation The 56800E core and all peripherals are reset The MA bit within the OMR is not changed This allows the software to determine the boot mode internal or external boot to be used on the next reset Run Mode This is the primary mode of operation for this device I
170. put ANB5 121 A13 ANB6 122 B12 ANB7 123 A12 TEMP 108 E11 Output Analog Temperature Sense Diode This signal connects to an SENSE Output on chip diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die Must be bypassed with a 0 01uF capacitor CAN_RX 143 B7 Schmitt Input FlexCAN Receive Data This is the CAN input This pin has Input pull up an internal pull up resistor enabled To deactivate the internal pull up resistor set the CAN bit in the SIM_PUDR register CAN_TX 142 D6 Open Open FlexCAN Transmit Data CAN output with internal pull up Drain Drain enable at reset Output Output Note If a pin is configured as open drain output mode internal pull up will automatically be disabled when it outputs low Internal pull up will be enabled unless it has been manually disabled by clearing the corresponding bit in the PUREN register of the GPIO module when it outputs high If a pin is configured as push pull output mode internal pull up will automatically be disabled whether it outputs low or high TCO 133 AQ Schmitt Input TCO Timer C Channel 0 and 1 Input pull up Output enabled GPIOE8 Schmitt Port E GPIO These GPIO pins can be individually Input programmed as input or output pins TC1 135 B9 Output GPIOE9 At reset these pins default to Timer functionality To deactivate the internal pull up resistor clear the appropriate bit of the GPIOE_PUR register
171. r 0 x OOFF GPIOB RAWDATA A Raw Data Input Register Table 4 31 GPIOC Registers Address Map GPIOC BASE 00 F310 Register Acronym Address Offset Register Description Reset Value GPIOC_PUR 0 Pull up Enable Register 0 x O7FF GPIOC_DR 1 Data Register 0 x 0000 GPIOC_DDR 2 Data Direction Register 0 x 0000 GPIOC_PER 3 Peripheral Enable Register 0 x O7FF GPIOC_IAR 4 Interrupt Assert Register 0 x 0000 GPIOC_IENR 5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR 7 Interrupt Pending Register 0 x 0000 GPIOC_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOC_PPMODE 9 Push Pull Mode Register 0 x O7FF GPIOC_RAWDATA A Raw Data Input Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 67 Table 4 32 GPIOD Registers Address Map GPIOD_BASE 00 F320 Register Acronym Address Offset Register Description Reset Value GPIOD_PUR 0 Pull up Enable Register 0 x 1FFF GPIOD_DR 1 Data Register 0 x 0000 GPIOD_DDR 2 Data Direction Register 0 x 0000 GPIOD_PER 3 Peripheral Enable Register 0 x 1FCO GPIOD_IAR 4 Interrupt Assert Register 0 x 0000 GPIOD_IENR 5 Interrupt Enable Register 0 x 0000 GPIOD_IPOLR 6 Interrupt Polarity Register 0 x 0000 GPIOD_IPR 7 Interrupt Pending Register 0 x 0000 GPIOD_IESR 8 Interrupt Edge Sensitive Register 0 x 0000 GPIOD_PPMODE 9 Pus
172. r 5 ID High Register FCMB5_ID_LOW 6A Message Buffer 5 ID Low Register FCMB5 DATA 6B Message Buffer 5 Data Register FCMB5 DATA 6C Message Buffer 5 Data Register FCMB5 DATA 6D Message Buffer 5 Data Register FCMB5 DATA 6E Message Buffer 5 Data Register Reserved FCMB6 CONTROL 70 Message Buffer 6 Control Status Register FCMB6 ID HIGH 71 Message Buffer 6 ID High Register FCMB6 ID LOW 72 Message Buffer 6 ID Low Register FCMB6 DATA 73 Message Buffer 6 Data Register FCMB6 DATA 74 Message Buffer 6 Data Register FCMB6 DATA 75 Message Buffer 6 Data Register FCMB6 DATA 76 Message Buffer 6 Data Register Reserved FCMB7 CONTROL 78 Message Buffer 7 Control Status Register FCMB7 ID HIGH 79 Message Buffer 7 ID High Register FCMB7 ID LOW 7A Message Buffer 7 ID Low Register FCMB7 DATA 7B Message Buffer 7 Data Register FCMB7 DATA 7C Message Buffer 7 Data Register FCMB7 DATA 7D Message Buffer 7 Data Register FCMB7 DATA 7E Message Buffer 7 Data Register Reserved FCMB8 CONTROL 80 Message Buffer 8 Control Status Register FCMBS8 ID HIGH 81 Message Buffer 8 ID High Register FCMB8 ID LOW 82 Message Buffer 8 ID Low Register FCMB8 DATA 83 Message Buffer 8 Data Register FCMB8 DATA 84 Message Buffer 8 Data Register FCMB8 DATA 85 Message Buffer 8 Data Register FCMB8 DATA 86 Message Buffer 8 Data Register Reserved 56F8357 Technical Data Rev 15 F
173. r for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e La so freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST O Freescale Semiconductor Inc 2005 2006 All rights reserved MC56F8357 Rev 15 01 2007
174. r reset the default state is GPIO SYS_CLK These pins can also be used to extend the external address GPIOB6 47 P3 bus to its full length or to view any of several system clocks In A22 these cases the GPIO_B_PER can be used to individually SYS_CLK2 disable the GPIO The CLKOSR register in the SIM see Part GPIOB7 48 M4 eer can then be used to choose between address and clock A23 unctions oscillator_ clock 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 23 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset DO 70 P10 Input In reset Data Bus DO D6 specify part of the data for external program Output output is or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR DO D6 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOF9 Input Port F GPIO These seven GPIO pins can be individually Output programmed as input or output pins D1 71 N10 GPIOF10 After reset these pins default to the EMI Data bus function D2 83 P14 To deactivate the internal pull up resistor clear the appropriate GPIOF11 GPIO bit in the GPIOF_PUR register E SS Ss Example GPIOF9
175. rature Sense voltage 2 The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPTO and FMOPT1 3 See Application Note AN1980 for methods to increase accuracy 4 Assuming a 12 bit range from OV to 3 3V 5 Typical resolution calculated using equation Res VrerH Vngrio X 1 212 m 56F8357 Technical Data Rev 15 138 Freescale Semiconductor Preliminary AC Electrical Characteristics 10 3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10 5 Unless otherwise specified propagation delays are measured from the 50 to the 50 point and rise and fall times are measured between the 10 and 90 points as shown in Figure 10 1 Input Signal Rise Time Note The midpoint is Vy Vi Vi 2 Figure 10 1 Input Signal Measurement References Figure 10 2 shows the definitions of the following signal states Active state when a bus or signal is driven and enters a low impedance state Tri stated when a bus or signal is placed in a high impedance state e Data Valid state when a signal level has reached VoL or Voy Data Invalid state when a signal level is in transition between Vo and Voy Data1 Valid Data2 Valid Data3 Valid Data Invalid State lt Tri stated Data Active Data Active Figure 10 2 Signal States 10 4 Flash Memory Characteristics Table 10 12 Flash Timing Paramet
176. re disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 10 Interrupt Priority Register 9 IPR9 Base 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read PWMA_F IPL PWMB_F IPL SE PWM RL IPL ADCA_ZC IPL ABCB ZC IPL ee ior p Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 12 Interrupt Priority Register 9 IPR9 5 6 10 1 PWM A Fault Interrupt Priority Level PIWMA F IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 10 2 PWM B Fault Interrupt Priority Level PWMB_F IPL Bits 13 12 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 10 3 Reload PWM A Interrupt Priority Level PWMA_RL IPL Bits 11 10 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority l
177. reescale Semiconductor Preliminary 73 Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMB9_CONTROL 88 Message Buffer 9 Control Status Register FCMB9_ID_HIGH 89 Message Buffer 9 ID High Register FCMB9_ID_LOW 8A Message Buffer 9 ID Low Register FCMB9_DATA 8B Message Buffer 9 Data Register FCMB9_DATA 8C Message Buffer 9 Data Register FCMB9_DATA 8D Message Buffer 9 Data Register FCMB9_DATA 8E Message Buffer 9 Data Register Reserved FCMB10_CONTROL 90 Message Buffer 10 Control Status Register FCMB10 ID HIGH 91 Message Buffer 10 ID High Register FCMB10 ID LOW 92 Message Buffer 10 ID Low Register FCMB10 DATA 93 Message Buffer 10 Data Register FCMB10 DATA 94 Message Buffer 10 Data Register FCMB10 DATA 95 Message Buffer 10 Data Register FCMB10 DATA 96 Message Buffer 10 Data Register Reserved FCMB11 CONTROL 98 Message Buffer 11 Control Status Register FCMB11 ID HIGH 99 Message Buffer 11 ID High Register FCMB11 ID LOW 9A Message Buffer 11 ID Low Register FCMB11 DATA 9B Message Buffer 11 Data Register FCMB11 DATA 9C Message Buffer 11 Data Register FCMB11 DATA 9D Message Buffer 11 Data Register FCMB11 DATA 9E Message Buffer 11 Data Register Reserved FCMB12 CONTROL A0 Message Buffer 12 Control Sta
178. ress for Fast Interrupt 1 defined in the FIMI register 5 6 17 Fast Interrupt 1 Vector Address High Register FIVAH1 Base 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 uU 0 W 0 uU 0 FAST INTERRUPT 1 Write VECTOR ADDRESS HIGH RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 19 Fast Interrupt 1 Vector Address High Register FIVAH1 5 6 17 1 Reserved Bits 15 5 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 17 2 Fast Interrupt 1 Vector Address High FIVAH1 Bits 4 0 The upper five bits of vector address are used for Fast Interrupt 1 This register is combined with FIVAL1 to form the 21 bit vector address for Fast Interrupt 1 defined in the FIMI register 56F8357 Technical Data Rev 15 100 Freescale Semiconductor Preliminary Register Descriptions 5 6 18 IRQ Pending 0 Register IRQPO Base 11 Figure 5 20 IRQ Pending 0 Register IRQPO 5 6 18 1 IRQ Pending PENDING Bits 16 2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81 e 0 IRQ pending for this vector number 1 No IRQ pending for this vector number 5 6 18 2 Reserved Bit 0 This bit is reserved or not implemented It is read as 1 and cannot be modified by writing 5 6 19 IRQ Pending 1 Register IRQP1 Figure 5 21 I
179. rface to this port to allow in circuit Flash programming 12 3 Power Distribution and I O Ring Implementation Figure 12 1 illustrates the general power control incorporated in the 56F8357 56F8157 This chip contains two internal power regulators One of them is powered from the Vppa osc pL Pin and cannot be turned off This regulator controls power to the internal clock generation circuitry The other regulator is powered from the Vpp jo pins and provides power to all of the internal digital logic of the core all peripherals and the internal memories This regulator can be turned off if an external Vpp corp voltage is externally applied to the Ne Ap pins E In summary the entire chip can be supplied from a single 3 3 volt supply if the large core regulator is enabled If the regulator is not enabled a dual supply 3 3V 2 5V configuration can also be used Notes Flash RAM and internal logic are powered from the core regulator output V ppl and Vpp2 are not connected in the customer system All circuitry analog and digital shares a common Vgg bus VpDA_OSC_PLL Vpp Vppa_apc dL Voip VREFH REG REG VREFP 1 0 ADC VREFMID CORE I VREFN OSC VREFLO Vss Vssa ADC Figure 12 1 Power Management 56F8357 Technical Data Rev 15 172 Freescale Semiconductor Preliminary Power Distribution and I O Ring Implem
180. rt freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com RoHS compliant and or Pb free versions of Freescale products have the unctionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go t
181. ry Map Continued Address Register Acronym Register Name X FF FFFD OTXRXSR 8 bits Transmit and Receive Status and Control Register X FF FFFE OTX ORX 32 bits Transmit Register Receive Register X FF FFFF OTX1 ORX1 Transmit Register Upper Word Receive Register Upper Word 4 7 Peripheral Memory Mapped Registers On chip peripheral registers are part of the data memory map on the 56800E series These locations may be accessed with the same addressing modes used for ordinary Data memory except all peripheral registers should be read written using word accesses only Table 4 9 summarizes base addresses for the set of peripherals on the 56F8357 and 56F8157 devices Peripherals are listed in order of the base address The following tables list all of the peripheral registers required to control or access the peripherals Note Features in italics are NOT available on the 56F8157 device Table 4 9 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number External Memory Interface EMI X 00 F020 4 10 Timer A TMRA X 00 F040 4 11 Timer B TMRB X 00 F080 4 12 Timer C TMRC X 00 FOCO 4 13 Timer D TMRD X 00 F100 4 14 PWM A PWMA X 00 F140 4 15 PWM B PWMB X 00 F160 4 16 Quadrature Decoder 0 DECO X 00 F180 4 17 Quadrature Decoder 1 DEC1 X 00 F190 4 18 ITCN ITCN X 00 F1A0 4 19 ADCA ADCA X 00 F200 4 20 ADCB ADCB X 00
182. s disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 0 IRQ is priority level 2 e 11 IRQ is priority level 3 5 6 2 3 EOnCE Transmit Register Empty Interrupt Priority Level TX REG IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 0 IRQ is priority level 2 e 11 IRQ is priority level 3 5 6 2 4 EOnCE Trace Buffer Interrupt Priority Level TRBUF IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 1 through 3 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 1 e 0 IRQ is priority level 2 11 IRQ is priority level 3 5 6 3 Interrupt Priority Register 2 IPR2 Base 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read T FMCBE IPL FMCC IPL FMERR IPL LOCK IPL LVI IPL IRQB IPL IRQA IPL rite RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 5 Interrupt Priority Register 2 IPR2 56F8357 Technical Data Rev 15 82 Freescale Semiconductor Preliminary Register Descriptions 5 6 3 1 Flash Memory Command Data Address Buffers Empty Interrupt Priority Level FMCBE IPL Bits 15 14 This field is used to set the interrupt priority level for IRQs This
183. s register is set to something other than the top of memory EOnCE register space and the EX bit in the OMR is set to 1 the JTAG port cannot access the on chip EOnCE registers and debug functions will be affected Hard Coded Address Portion Instruction Portion 6 Bits from I O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24 Bit for Short UO Address Figure 6 13 I O Short Address Determination With this register set an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I O Short addressing mode to reference them The ISR should restore this register to its previous contents prior to returning from interrupt Note The default value of this register set points to the EOnCE registers Note The pipeline delay between setting this register set and using short I O addressing with the new value is three cycles 56F8357 Technical Data Rev 15 120 Freescale Semiconductor Preliminary Clock Generation Overview Base D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ISAL 23 22 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 6 14 I O Short Address Location High Register SIM_ISALH 6 5 10 1 Input Output Short Address Low ISAL 23 22 Bit 1 0 This field represents the upper two address bits of the hard coded I O short address
184. se Input Output 1 1 56F8357 56F8157 Features 6 GPIO acs 2 beds ee ri 126 1 2 Device Description 8 8 1 introduci n iios sisse be nai dep 126 1 3 Award Winning Development Environmen 10 IL Memory Maps ies e er ehe 126 1 4 Architecture Block Diagram 11 8 3 Configuration u a auauai 126 1 5 Product Documentation 15 1 6 Data Sheet Conventions 15 Part 9 Joint Test Action Group JTAG 131 9 1 JTAG Information e 2620628006 131 Part 2 Signal Connection Descriptions 16 2 1 Introdiction usi sm mem niii 16 Part 10 Specifications da tases D LEE 131 22 Signal PINS cei seb e Ces E dace eaa 19 10 1 General Characteristics 131 A 10 2 DC Electrical Characteristics 135 Part 3 On Chip Clock Synthesis OCCS 39 10 3 AC Electrical Characteristics 139 3 1 IMMOGUCHON zs usos diab dered ad 39 10 4 Flash Memory Characteristics 139 3 2 External Clock Operation rem 39 10 5 External Clock Operation Timing CE 140 3 9 Registers viaria digi acd ds R REGE 41 10 6 Phase Locked Loop Timing 140 10 7 Crystal Oscillator Timing 141 Part 4 Memory Map 41 10 8 External Memory Interface Timing 141 441 IMTOdUCION is ara 0 5 ar 41 10 9 Reset Stop Wait Mode Select and 4 2 Program Map O Om 42 Interrupt Timing O EE ERE 144 4 3 Interrupt Vector Ta
185. sed to implement Flash security and finally followed by a 32 clock window in which the core is initialized After completion of the described reset sequence application code will begin execution Resets may be asserted asynchronously but are always released internally on a rising edge of the system clock Part 7 Security Features The 56F8357 56F8157 offer security features intended to prevent unauthorized users from reading the contents of the Flash memory FM array The Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array However part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program as this code would defeat the purpose of security At the same time the user may also wish to put a backdoor in his program As an example the user downloads a security key through the SCI allowing access to a programming routine that updates parameters stored in another section of the Flash 7 1 Operation with Security Enabled Once the user has programmed the Flash with his application code the device can be secured by programming the security bytes located in the FM configuration field which occupies a portion of the FM array These non volatile bytes will keep the part secured through reset and through power down of the device Only two bytes within this field are use
186. sh IPBus Control Logic Bridge A Flash Memory Module NOT available on the 56F8157 device IPBus Figure 1 1 System Bus Interfaces Note Flash memories are encapsulated within the Flash Memory FM Module Flash control is accomplished by the I O to the FM over the peripheral bus while reads and writes are completed between the core and the Flash memories Note The primary data RAM port is 32 bits wide Other data ports are 16 bits 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Architecture Block Diagram To From IPBus Bridge Interrupt Controller CLKGEN OSC PLL Low Voltage Interrupt Timer A gt Quadrature Decoder 0 POR amp LVI Y System POR SIM RESET ar Timer D 4 COP Reset Timer B a p COP v Quadrature Decoder 1 SYNC Output 13 pu Output ch3i ch2i Timer C D e ch3o ch20 ADCB we 24 M Y ADCA EU TEMP SENSE lp Note ADC A and ADC B use the same volt age reference circuit with Vru VRerp VngrMip VREEN 8nd Vggr o pins IPBus NOT available on the 56F8157 device Figure 1 2 Peripheral Subsystem 56F8357 Technical Data Rev 15 Freescale Semiconductor 13 Preli
187. ster 56F8357 Technical Data Rev 15 30 Freescale Semiconductor Preliminary Signal Pins Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset MOSIO 148 B6 Input In reset SPI 0 Master Out Slave In This serial data pin is an output Output output is from a master device and an input to a slave device The disabled master device places data on the MOSI line a half cycle before pull up is the clock edge the slave device uses to latch the data enabled GPIOE5 Input Port E GPIO This GPIO pin can be individually Output programmed as an input or output pin After reset the default state is MOSIO To deactivate the internal pull up resistor clear bit 5 in the GPIOE_PUR register MISOO 147 D4 Input Input SPI 0 Master In Slave Out This serial data pin is an input to Output pull up a master device and an output from a slave device The MISO enabled line of a slave device is placed in the high impedance state if the slave device is not selected The slave device places data on the MISO line a half cycle before the clock edge the master device uses to latch the data GPIOE6 Input Port E GPIO This GPIO pin can be individually Output programmed as an input or output pin After reset the default state is MISOO To deactivate the internal pull up resistor clear bit 6 in the GPIOE_PUR register Sso 145 D5 I
188. ster 2 ADCB_OFS 3 24 Offset Register 3 ADCB_OFS 4 25 Offset Register 4 ADCB_OFS 5 26 Offset Register 5 ADCB_OFS 6 27 Offset Register 6 ADCB_OFS 7 28 Offset Register 7 ADCB_POWER 29 Power Control Register ADCB_CAL 2A ADC Calibration Register Table 4 22 Temperature Sensor Register Address Map TSENSOR BASE 00 F270 Temperature Sensor is NOT available in the 56F8157 device Register Acronym Address Offset Register Description TSENSOR CNTL 0 Control Register Table 4 23 Serial Communication Interface 0 Registers Address Map SCIO BASE 00 F280 Register Acronym Address Offset Register Description SCIO_SCIBR 0 Baud Rate Register SCIO_SCICR SCIO_SCISR 1 3 Control Register Status Register SCIO_SCIDR 4 Data Register 56F8357 Technical Data Rev 15 64 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 24 Serial Communication Interface 1 Registers Address Map SCI1_BASE 00 F290 Register Acronym Address Offset Register Description SCI1_SCIBR 0 Baud Rate Register SCI1_SCICR SCI1_SCISR 1 3 Control Register Status Register SCI1_SCIDR 4 Data Register Table 4 25 Serial Peripheral Interface 0 Registers Address Map SPIO_BASE 00 F2A0 Register Acronym Address Offset Register Des
189. t be configured as address or chip select signals to access addresses at P 10 0000 and above Note Program RAM is NOT available on the 56F8157 device 56F8357 Technical Data Rev 15 42 Freescale Semiconductor Preliminary Interrupt Vector Table Table 4 4 Program Memory Map at Reset Mode 0 MA 0 Mode 11 MA 1 Begin End Internal Boot External Boot Address Internal Boot EMI MODE 02 EMI_MODE 14 16 Bit External Address Bus 16 Bit External Address Bus 20 Bit External Address Bus P 1F FFFF External Program Memory External Program Memory External Program Memory P 10 0000 P 0F FFFF P 03 0000 P 02 FFFF On Chip Program RAM P 02 F800 4KB P 02 F7FF Reserved P 02 2000 116KB P 02 1FFF Boot Flash Boot Flash External Program Memory P 02 0000 16KB 16KB COP Reset Address 02 0002 COP Reset Address 02 0002 Not Used for Boot in this Mode Boot Location 02 00009 Boot Location 02 0000 P 01 FFFF Internal Program Flash Internal Program Flash P 01 0000 128KB 128KB P 00 0000 128KB COP Reset Address 00 0002 Boot Location 00 0000 If Flash Security Mode is enabled EXTBOOT Mode 1 cannot be used See Security Features Part 7 This mode provides maximum compatibility with 56F80x parts while operating externally EMI_MODE 0 when EMI_MODE pin is tied to ground at boot up EMI MODE 1 when EMI MODE pin is tied to Vpp at boot up N
190. t both the JTAG TAP controller by asserting TRST and the device by asserting external chip reset to return to normal unsecured operation 7 2 4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash Additionally the KEYEN bit that allows backdoor key access must be set An alternative method for performing analysis on a secured microcontroller would be to mass erase and reprogram the Flash with the original code but modify the security bytes To insure that a customer does not inadvertently lock himself out of the device during programming it is recommended that he program the backdoor access key first his application code second and the security bytes within the FM configuration field last Part 8 General Purpose Input Output GPIO 8 1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip specific information This information supercedes the generic information in the 56F8300 Peripheral User Manual 8 2 Memory Maps The width of the GPIO port defines how many bits are implemented in each of the GPIO registers Based on this and the default function of each of the GPIO pins the reset values of the GPIOx PUR and GPIOx_PE
191. t specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources RESET pin software reset and COP reset 6 5 4 Most Significant Half of JTAG ID SIM_MSH_ID This read only register displays the most significant half of the JTAG ID for the chip This register reads 01F4 Base 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 uU 0 1 1 1 1 1 U 1 U Write RESET 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 Figure 6 6 Most Significant Half of JTAG ID SIM MSH ID 6 5 5 Least Significant Half of JTAG ID SIM LSH ID This read only register displays the least significant half of the JTAG ID for the chip This register reads 601D Base 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 1 1 iU 0 uU 0 0 U uU 0 1 1 1 U 1 Write RESET 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 Figure 6 7 Least Significant Half of JTAG ID SIM LSH ID 6 5 6 SIM Pull up Disable Register SIM PUDR Most of the pins on the chip have on chip pull up resistors Pins which can operate as GPIO can have these resistors disabled via the GPIO function Non GPIO pins can have their pull ups disabled by setting the appropriate bit in this register Disabling pull ups is done on a peripheral by peripheral basis for pins not muxed with GPIO Each bit in the register see Figure 6 8
192. taic cycles ADC reference circuit power up time tVREF 25 ms Conversion time tADC 6 taic cycles Sample time taps 1 taic cycles Input capacitance Capi 5 pF Input injection current per pin lapi 3 mA Input injection current total lADIT 20 mA VrEFH Current IVREFH 1 2 3 mA ADC A current lADCA 25 mA ADC B current lADCB 25 mA Quiescent current lapca 0 10 uA Uncalibrated Gain Error ideal 1 EGAIN 004 015 Uncalibrated Offset Voltage VOFFSET 15 35 mV Calibrated Absolute Error AEcaL See Figure 10 22 LSBs Calibration Factor 17 CF1 0 010380 Calibration Factor 2 CF2 31 7 Crosstalk between channels 60 dB Common Mode Voltage V common VREFH VREFLO 2 V Signal to noise ratio SNR 64 6 db Signal to noise plus distortion ratio SINAD 59 1 db 56F8357 Technical Data Rev 15 154 Freescale Semiconductor Preliminary Table 10 24 ADC Parameters Continued Analog to Digital Converter ADC Parameters Effective Number Of Bits Characteristic Symbol Min Typ Max Unit Total Harmonic Distortion THD 60 6 db Spurious Free Dynamic Range SFDR 61 1 db ENOB 9 6 Bits 1 INL measured from Vin 1VREFH to Vin IV REFH 10 to 90 Input Signal Range LSB Least Significant Bit ADC clock cycles a E WN o
193. tate to DRV 1 instead of using the default setting GPIOA8 Input Port A GPIO These six GPIO pins can be individually Output programmed as input or output pins A1 10 E3 GPIOA9 After reset the default state is Address Bus A2 11 E4 To deactivate the internal pull up resistor clear the appropriate GPIOA10 GPIO bit in the GPIOA PUR register A3 12 F2 3 GPIOA11 Example GPIOAG clear bit 8 in the GPIOA PUR register A4 13 F1 GPIOA12 A5 14 F3 GPIOA13 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 21 Table 2 2 Signal and Package Information for the 160 Pin LQFP and MBGA Signal Pin State Name No Ball No Type During Signal Description Reset A6 17 G1 Output In reset Address Bus A6 A7 specify two of the address lines for output is external program or data memory accesses disabled pull up is Depending upon the state of the DRV bit in the EMI bus control enabled register BCR A6 A7 and EMI control signals are tri stated when the external bus is inactive Most designs will want to change the DRV state to DRV 1 instead of using the default setting GPIOE2 Schmitt Port E GPIO These two GPIO pins can be individually Input programmed as input or output pins A7 18 G3 Output GPIOE3 After reset the default state is Address Bus To deactivate the internal pull up resistor clear the appropriate GPIO bit in the GP
194. tched and Variable Reluctance Motors and stepper motors The PWMs incorporate fault protection and cycle by cycle current limiting with sufficient output drive capability to directly drive standard optoisolators A smoke inhibit write once protection feature for key parameters is also included A patented PWM waveform distortion correction circuit is also provided Each PWM is double buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16 The PWM modules provide a reference output to synchronize the Analog to Digital Converters through two channels of Quad Timer C The 56F8357 incorporates two Quadrature Decoders capable of capturing all four transitions on the two phase inputs permitting generation of a number proportional to actual position Speed computation capabilities accommodate both fast and slow moving shafts An integrated watchdog timer in the Quadrature Decoder can be programmed with a time out value to alarm when no shaft motion is detected Each input is filtered to ensure only true transitions are recorded This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces SCIs two Serial Peripheral Interfaces SPIs and four Quad Timers Any of these interfaces can be used as General Purpose Input Outputs GPIOs if that function is not required A Flex Controller Area Network FlexCAN interface CAN Version 2 0 B co
195. the system clock is the 8MHz crystal frequency because the PLL has not been set up the input clock will be below 12 8MHz so PRDIV8 FM CLKDIV 6 0 Using the following equation yields a DIV value of 19 for a clock of 200kHz and a DIV value of 20 for a clock of 190kHz This translates into an FM CLKDIV 6 0 value of 13 or 14 respectively YS CLK o 150 kHz lt 2 lt 200 kHz DIV 1 EXAMPLE 2 In this example the system clock has been set up with a value of 32MHz making the FM input clock 16MHz Because that is greater than 12 8MHz PRDIV8 FM CLKDIV 6 1 Using the following equation yields a DIV value of 9 for a clock of 200kHz and a DIV value of 10 for a clock of 181kHz This translates to an FM CLKDIV 6 0 value of 49 or 4A respectively ES 150 kHz lt 238 DIV 1 lt 200 kHz Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register the clock divider value must be shifted into the corresponding 7 bit data register After the data register has been 56F8357 Technical Data Rev 15 Freescale Semiconductor 125 Preliminary updated the user must transition the TAP controller into the RUN TEST IDLE state for the lockout sequence to commence The controller must remain in this state until the erase sequence has completed For details see the JTAG Section in the 56F8300 Peripheral User Manual Note Once the lockout recovery sequence has completed the user must rese
196. tics Note The 56F8157 device is specified to meet Industrial requirements only CAN is NOT available on the 56F8157 device Table 10 5 DC Electrical Characteristics At Recommended Operating Conditions see Table 10 4 or P Test Characteristic Symbol Notes Min Typ Max Unit Conditions Output High Voltage VoH 2 4 V lon loHmax Output Low Voltage VoL 0 4 V loL loLmax Digital Input Current High liH Pin Groups 0 2 5 pA Vin 3 0V to pull up enabled or disabled 1 2 5 6 9 5 5V Digital Input Current High lir Pin Group 10 40 80 160 pA Vin 3 0V to with pull down 5 5V Analog Input Current High HHA Pin Group 13 0 2 5 pA Vin Mona ADC Input Current High lIHADC Pin Group 12 0 10 pA Vin VppA Digital Input Current Low lit Pin Groups 200 100 50 pA Vin OV pull up enabled 1 2 5 6 9 Digital Input Current Low li Pin Groups 0 2 5 pA Vin OV pull up disabled 1 2 5 6 9 Digital Input Current Low with liL Pin Group 10 0 2 5 HA Vin OV pull down Analog Input Current Low liL A Pin Group 13 0 2 5 uA Vin OV ADC Input Current Low liLADC Pin Group 12 0 10 uA Vin OV EXTAL Input Current Low lEXTAL 0 2 5 pA Vin VppA or OV clock input XTAL Input Current Low IXTAL CLKMODE High 0 2 5 uA Vin Vppa or OV cita CLKMODE Low 200 uA Vin Vppa or OV Output Current loz
197. ties 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQis priority level 0 e 0 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 6 Reserved Bits 5 4 This bit field is reserved or not implemented It is read as 0 and cannot be modified by writing 5 6 3 7 External IRQ B Interrupt Priority Level IRQB IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 0 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 3 8 External IRQ A Interrupt Priority Level IRQA IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 It is disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 0 IRQ is priority level 1 e l IRQ is priority level 2 5 6 4 Interrupt Priority Register 3 IPR3 Base 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Sec S Kg FCMSGBUF IPL FCWKUP IPL FCERR IPL FCBOFF IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 6 Interrupt Priority Register 3 IPR3 56F8357 Technical Data Rev 15 84 Freescale Semiconductor Preliminary Register Descriptions 5 6 4 1 GPIOD Interrupt Priority Level GPIOD IPL Bits 15 14
198. tings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset In addition this pin can be used as a general purpose input pin after reset 0 External address bits 19 16 are initially programmed as GPIO e 1 When booted with EXTBOOT 1 A 19 16 are initially programmed as address If EXTBOOT is 0 they are initialized as GPIO 6 5 1 3 OnCE Enable OnCE EBL Bit 5 e 0 OnCE clock to 56800E core enabled when core TAP is enabled e 1 OnCE clock to 56800E core is always enabled 6 5 1 4 Software Reset SW RST Bit 4 This bit is always read as 0 Writing a 1 to this bit will cause the part to reset 6 5 1 5 Stop Disable STOP DISABLE Bits 3 2 00 Stop mode will be entered when the 56800E core executes a STOP instruction e 01 The 56800E STOP instruction will not cause entry into Stop mode STOP DISABLE can be reprogrammed in the future e 10 The 56800E STOP instruction will not cause entry into Stop mode STOP DISABLE can then only be changed by resetting the device 11 Same operation as 10 6 5 1 6 Wait Disable WAIT DISABLE Bits 1 0 e 00 Wait mode will be entered when the 56800E core executes a WAIT instruction 01 The 56800E WAIT instruction will not cause entry into Wait mode WAIT DISABLE can be reprogrammed in the future e 10 The HawkV2 WAIT instruction will not cause entry into Wait mode WAIT DISABLE can then only be changed by resetting the device
199. to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 IRQ is priority level 2 5 6 7 6 Reserved Bits 5 4 This bit field is reserved or not implemented It is read as O and cannot be modified by writing 5 6 7 7 Quadrature Decoder 0 INDEX Pulse Interrupt Priority Level DECO_XIRQ IPL Bits 3 2 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities O through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 56F8357 Technical Data Rev 15 Freescale Semiconductor 91 Preliminary 5 6 7 8 Quadrature Decoder 0 HOME Signal Transition or Watchdog Timer Interrupt Priority Level DECO_HIRQ IPL Bits 1 0 This field is used to set the interrupt priority level for IRQs This IRQ is limited to priorities 0 through 2 They are disabled by default e 00 IRQ disabled default e 01 IRQ is priority level 0 e 10 IRQ is priority level 1 e 11 2 IRQ is priority level 2 5 6 8 Interrupt Priority Register 7 IPR7 Base 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Wi TMRAO IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRBO IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL rite RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
200. tor Instruction Fetch Figure 10 8 Interrupt from Wait State Timing tiw IRQA tir A0 A15 PS DS First Instruction Fetch RD WR Not IRQA Interrupt Vector Figure 10 9 Recovery from Stop State Using Asynchronous Interrupt Timing 10 10 Serial Peripheral Interface SPI Timing Table 10 18 SPI Timing Characteristic Symbol Min Max Unit See Figure Cycle time tc 10 10 10 11 Master 50 ns 10 12 10 13 Slave 50 ns Enable lead time Lon 10 13 Master ns Slave 25 ns Enable lag time tea 10 13 Master ns Slave 100 ns Clock SCK high time ton 10 10 10 11 Master 17 6 ns 10 12 10 13 Slave 25 ns Clock SCK low time teL 10 13 Master 24 1 ns Slave 25 ns 56F8357 Technical Data Rev 15 146 Freescale Semiconductor Preliminary Table 10 18 SPI Timing Continued Serial Peripheral Interface SPI Timing Characteristic Symbol Min Max Unit See Figure Data set up time required for inputs tos 10 10 10 11 Master 20 ns 10 12 10 13 Slave 0 ns Data hold time required for inputs ton 10 10 10 11 Master 0 ns 10 12 10 13 Slave 2 ns Access time time to data active from tA 10 13 high impedance state 4 8 15 ns Slave Disable time hold time to high impedance state tp 10 13 Slave 3 7 15 2 ns Data Valid for outputs tov 10 10 10 11 Master 4 5 ns 10 12 10 13 Slave after enabl
201. ts 6 2 JTAG Enhanced On Chip Emulation EOnCE 5 5 Temperature Sense 1 Dedicated GPIO 7 1 If the on chip regulator is disabled the Vcap pins serve as 2 5V Vpp core power inputs 2 Alternately can function as Quad Timer pins 3 Pins in this section can function as Quad Timer SPI 1 or GPIO 56F8357 Technical Data Rev 15 16 Freescale Semiconductor Preliminary Power Power Power Ground Ground Other Supply Ports PLL and Clock External Address Bus or GPIO External Data Bus External Bus Control SCI 0 or GPIO SCI 1 or GPIO JTAG EOnCE Port When the on chip regulator is disabled these four pins become 2 5V Vpp core GPIOB4 A20 prescaler_clock GPIOB5 A21 SYS_CLK GPIOB6 A22 SYS_CLK2 GPIOB7 A23 oscillator_clock Vpp io VpDA_OSC_PLL DDA_ADC Vss Vssa_ADC gt OCR_DIS Vcap Vcap4 P Vpp1 amp Vpp2 CLKMODE EXTALO XTA CLKO mi AQ A5 GPIOAS 13 AG AT GPIOE2 3 AB A15 GPIOAO 7 GPIOBO 3 A16 19 DO D6 GPIOF9 15 KG Dz D15 GPIOFO 8 RD WR PS CSO GPIODF8 VOR DS CS1 GPIOFD9 GPIODO 5 CS2 7 498 M TXDO GPIOEO RXDO GPIOE1 TXD1 GPIOD6 RXD1 GPIOD7 TDO TRST A m c ex cS 28 eu
202. tus Register FCMB12 ID HIGH A1 Message Buffer 12 ID High Register FCMB12 ID LOW A2 Message Buffer 12 ID Low Register FCMB12 DATA A3 Message Buffer 12 Data Register FCMB12 DATA A4 Message Buffer 12 Data Register FCMB12 DATA A5 Message Buffer 12 Data Register FCMB12 DATA A6 Message Buffer 12 Data Register 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4 38 FlexCAN Registers Address Map Continued FC_BASE 00 F800 FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description Reserved FCMB13 CONTROL A8 Message Buffer 13 Control Status Register FCMB13_ID_HIGH A9 Message Buffer 13 ID High Register FCMB13_ID_LOW SAA Message Buffer 13 ID Low Register FCMB13_DATA SAB Message Buffer 13 Data Register FCMB13_DATA AC Message Buffer 13 Data Register FCMB13_DATA AD Message Buffer 13 Data Register FCMB13_DATA AE Message Buffer 13 Data Register Reserved FCMB14_CONTROL BO Message Buffer 14 Control Status Register FCMB14 ID HIGH B1 Message Buffer 14 ID High Register FCMB14 ID LOW B2 Message Buffer 14 ID Low Register FCMB14 DATA B3 Message Buffer 14 Data Register FCMB14 DATA B4 Message Buffer 14 Data Register FCMB14_DATA B5 Message Buffer 14 Data Register FCMB14_DATA B6 Message Buffer 14 Data Register Reserved FCMB15 CONTROL B8 Message B
203. uffer 15 Control Status Register FCMB15 ID HIGH B9 Message Buffer 15 ID High Register FCMB15 ID LOW BA Message Buffer 15 ID Low Register FCMB15 DATA BB Message Buffer 15 Data Register FCMB15 DATA BC Message Buffer 15 Data Register FCMB15 DATA BD Message Buffer 15 Data Register FCMB15 DATA BE Message Buffer 15 Data Register Reserved 56F8357 Technical Data Rev 15 Freescale Semiconductor Preliminary 75 4 8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program The Serial Bootloader application can be used to load a user application into the Program and Data Flash NOT available in the 56F 8157 memories of the device The 56F83xx SCI CAN Bootloader User Manual MC56F83xxBLUM provides detailed information on this firmware An application note Production Flash Programming AN1973 details how the Serial Bootloader program can be used to perform production Flash programming of the on board Flash memories as well as other potential methods Like all the Flash memory blocks the Boot Flash can be erased and programmed by the user The Serial Bootloader application is programmed as an aid to the end user but is not required to be used or maintained in the Boot Flash memory Part 5 Interrupt Controller ITCN 5 1 Introduction The Interrupt Controller ITCN module is used to arbitrate between various interrupt requests IRQs to signal to the
204. urity mode Therefore the security feature cannot be used unless all executing code resides on chip When security is enabled any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored 7 2 2 Disabling EOnCE Access On chip Flash can be read by issuing commands across the EOnCE port which is the debug interface for the 56800E core The TRST TCLK TMS TDO and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped When the device boots the chip level JTAG TAP Test Access Port is active and provides the chip s boundary scan capability and access to the ID register Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled The 56800E core has an input which disables reading of internal memory via the JTAG EOnCE The FM sets this input at reset to a value determined by the contents of the FM security bytes 7 2 3 Flash Lockout Recovery If a user inadvertently enables Flash security on the device a built in lockout recovery mechanism can be used to reenable access to the device This mechanism completely reases all on chip Flash thus disabling Flash security Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration cfg files Add or uncomment the following configuration command unlock flash on connect 1 For more information p
205. wait states to 11 for both read and write accesses Table 4 11 Quad Timer A Registers Address Map TMRA_BASE 00 F040 Register Acronym Address Offset Register Description TMRAO CMP1 0 Compare Register 1 TMRAO CMP2 1 Compare Register 2 TMRAO CAP 2 Capture Register TMRAO LOAD 3 Load Register TMRAO HOLD 4 Hold Register TMRAO CNTR 5 Counter Register TMRAO CTRL 6 Control Register TMRAO SCR 7 Status and Control Register 56F8357 Technical Data Rev 15 Freescale Semiconductor 51 Preliminary Table 4 11 Quad Timer A Registers Address Map Continued TMRA_BASE 00 F040 Register Acronym Address Offset Register Description TMRAO_CMPLD1 8 Comparator Load Register 1 TMRAO_CMPLD2 9 Comparator Load Register 2 TMRAO COMSCR A Comparator Status and Control Register Reserved TMRA1 CMP1 10 Compare Register 1 TMRA1 CMP2 11 Compare Register 2 TMRA41 CAP 12 Capture Register TMRA1 LOAD 13 Load Register TMRA1 HOLD 14 Hold Register TMRA1 CNTR 15 Counter Register TMRA1 CTRL 16 Control Register TMRA1 SCR 17 Status and Control Register TMRA1 CMPLD1 18 Comparator Load Register 1 TMRA1 CMPLD2 19 Comparator Load Register 2 TMRA1 COMSCR 1A Comparator Status and Control Register Reserved TMRA2 CMP1 20 Compare Register 1 TMRA2 CMP2 21 Compare Register 2 TMRA2 CAP 22 Capture Register
206. ween Devices Table 1 1 outlines the key differences between the 56F8357 and 56F8157 devices Table 1 1 Device Differences Feature 56F8357 56F8157 Guaranteed Speed 60MHz 60 MIPS 40MHz 40 MIPS Program RAM 4KB Not Available Data Flash 8KB Not Available PWM 2x6 1x6 CAN 1 Not Available Quad Timer 4 2 Quadrature Decoder 2x4 1x4 Temperature Sensor 1 Not Available Dedicated GPIO 7 56F8357 Technical Data Rev 15 6 Freescale Semiconductor Preliminary 1 1 3 56F8357 56F8157 Features Memory Note Features in italics are NOT available in the 56F8157 device 1 1 4 Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On chip memory including a low cost high volume flash solution 256KB of Program Flash 4KB of Program RAM KB of Data Flash 16KB of Data RAM 16KB of Boot Flash Off chip memory expansion capabilities provide a simple method for interfacing additional external memory and or peripheral devices Access up to 4MB of external program memory or 32MB of external data memory External accesses supported at up to 60MHz zero wait states EEPROM emulation capability Peripheral Circuits Note Features in italics are NOT available in the 56F8157 device Pulse Width Modulator Inthe 56F8357 two Pulse Width Modulator modules each with six PWM outputs three Curr
207. xternal clock input fall time is measured from 90 to 10 External Clock tpw Note The midpoint is Vu Vi Vi 2 Figure 10 3 External Clock Timing 6 Phase Locked Loop Timing Table 10 14 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL fosc 4 8 8 4 MHz PLL stabilization time 40 to 125 C tolls 1 10 ms 1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly The PLL is optimized for 8MHz input crystal ZCLK may not exceed 60MHz For additional information on ZCLK and foyr 2 please refer to the OCCS chapter in the 56F8300 Peripheral User Manual This is the minimum time required after the PLL set up is changed to ensure reliable operation 56F8357 Technical Data Rev 15 140 Freescale Semiconductor Preliminary 10 7 Crystal Oscillator Timing Table 10 15 Crystal Oscillator Parameters Crystal Oscillator Timing Characteristic Symbol Min Typ Max Unit Crystal Start up time Tes 4 5 10 ms Resonator Start up time Trs 0 1 0 18 1 ms Crystal ESR Reser 120 ohms Crystal Peak to Peak Jitter Tp 70 250 ps Crystal Min Max Period Variation Tpy 0 12 1 5 ns Resonator Peak to Peak Jitter Try 300 ps Resonator Min Max Period Variation Trp 300 ps Bias Current high drive mode IBIASH 250 290

Freescale Semiconductor

Contents

Download Pdf Manuals

Related Search

Related Contents