Rev. 2.0 manual - Paul Scherrer Institut
Contents
1. Bi Bi A EI Mis AD E KE giallgisgisig alllal la zm HB s 88 332 GS 3 Biase e se 851818 l 8 8 Ja 8 8 8 8 8 8 8 8 8 8 U17 sho GeRERSERE BERR RESEERRRRRES EEE 2 g g g 8 8 2 8 is aanzSAIAIxF 22905 gs9Inz Ex 209959922 EPSP Ree A DU ET ia Ed 9 3 BBHH BR 9 89 EEE T uo 2 ge 33793 S 1018 OJ38 3 oio w op my o 8 ya E Ee di vetole 105 3 SS uo VO de ue oe 39 ron HG 0 roo Kai 2 la VO d ND myo canes 12 po Si Yn FFOADR1 0 TCA sO va 0 Te O es ni 0 p n p oO d DG ES 92 1 ns us Gc ho XC3S499 TQ144 gp eg xX ag Bi 5 dello mie 9 3 92 Ncco Jean o ayo Si m g qe lo e i ua 4 2 bp Ser iT emy 23_iyO ee gt fusca O ly Ya ugo im zm fe 7 VO taz N B fe 328 0 Eq e m d m atO 80 S 8 30 PND 79 PMPA Gio GH JD 32 ek pel o mak P 33 A EEPROM o poo ber 2 152 U19 35 A 3 8 pores L Ao vccL8 Smet 36 po Se MM get b5 z I 9 2 wpLZ X 22 diodi z X fo T PD2 FD10 Al WPL 66 8882 2 DO 9880 ER O Pps rpt 3e Ai SCS 9 o60600000Z590Z00050 PDA FD12 98 row 4 vss SDA g S2. MAX4794 2 1 3 B U39 sre SIS R11 3 E25 ORG X Sta e aO 3 DH i 1 H 2 8 af id id i OT5 5 o 8 8 8 5 8 B T6O RS E DTAPA Gh GN Ei GN ROFS D GND GND GND DSPEED sl aL ROFS T au E 1 1 SPEED DRS4 76 KR o T4 R il 25 GNDA 8 S i s il 0 OFS R32 45 S d R36 a THOR GE EE 8 OPTION Page 19 of 27 DRS4 Evaluation Board peul Scorer ln It Rev care ip Worones 1414 DRS4 WA igen PSI Date Dec 2008 Drawn by HU14 RS14 Filename DRS4 Evaluation Board SMW2 tch2 of 6 A B C D PAUL SCHERRER INSTITUT
3. DRS4 Evaluation Board User s Manual 3 3VANA aee D SMS en 3 FADC 8 42 Us R15 EL ATE S E E REC Sr 3 AD8695ART d we cam K T9 CAP 1206 8 8 8 Hr i T z s e 5 w ATTI LH 4 RTLA C30 100n alals B Bilis isa D Je em 8 8 4 gt U8 Rie 1 ATE GES 3 8 8 i E AD8605AR d wen cx E DI T10 PN REC 37 hod 2 GND N R17 2 Apc_P 22E IN Q SA 29 VIN lt Lamm 8 lt 30 8 SE 3 PSND U9 T c NCC ADC 32 VDD z 8 8 4 R18 Ez 9 95 1 Ee R19 S Z 2 Z 6 gran AD8695AR1 d ex BE D GE 2 ai e vola a T12 T 8 EES sie d E EEEE 4 1 8 3 3 o aw Ml T14 i 3 rz ADCCLK al U11 L 3 H 4 E R20 4 1 ATE ors 8 AD8961ART I 5 ae ep TS EEPROM Temp Sensor DRS4 16 bit DAC m U13 12 52 a LV ES d eno WP U15 U14 TEMP TRIM VOUTA LT vec 8 1 8 3 UB 3 H fees Hes CH 87 SCLK vech 4 voute 9e 2 s0 Hold 4 fes 3 CS E 3 gui 09 5 vourp 1 a Wh SCK S ES g rm ALS 3 s VIN vour 4 REF Ke 1 VSS SI Sol GND OI i paccs_ 5 CS LD iz e Zi 8 eck de R22 A25L16P Comme o A 8 LTC2600 ae e il ADRO3 d se a5 se DRS4 Evaluation Board Paul Scherrer Rev ei DE 1414 ADC DAC EEPROM 5 9 5232 Villigen PSI si Date Dec 2008 Drawn by HU14 RS14 Filename DRS4_Evaluation_ Board SW2 tch3 of 6 A B C D Page 20 of 27 ET
4. suo p Spee PPS RBS safe JS 3 S i Si 3 T T E E L aT gaa ds a oz 2 az eT Bal d a 3 2 amp E 3 z ds 8 3 8 5 3 UJ Co Co Co e CO ep ep g w fg R6 w cem R2 woo voc eee y 3 e 3 Qs i 2 a 3 4 E E 1 go R9 SIE a 2 oo 3 5 d L J e e 4 Drees amp TC E E c z goa P U QR 8 z C A Fa N JS LA E teen cis Te Te mmm E Z R7 R3 T i 15eE E 15eE O w o o 19en eu ANA LA ten oe HAL 4 d coe P en D gt FI a i P o eo cuors E ao 0 ao j 9N0 Q s amp 3 88 3 a8 oli 8 zd ug 43 98 3 38 48 8 eo 35 5 E RS Hou n a i er RR E i 4 2 Als prata Mafia th o Leni a A 3 A A ps A A 3g Y T WA i Y e EN Se Te Ze 9 8 18 ag 8 SH oR 98 a 8 2 ala 8 az 23 8 23 m 8 Ej p lt m Q 8 ag ag 5 S a e ap D g C e E KS e 2 a Oe S ER E Q 1 co 1 cse R8 R4 8 4 eec 4 oc bo Z DS 3 a BS Slo i A d 5 2 3 f j gt f f H z o 9S ES ol amp 5 Ble x Page 18 of 27 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual ES ES TR TR
5. v Bus 005 Device 005 ID 04b4 1175 Cypress Semiconductor Corp Device Descriptor bLength 18 bDescriptorType ii bcdUSB 2 00 bDeviceClass 0 Defined at Interface level bDeviceSubClass 0 bDeviceProtocol 1 bMaxPacketSize0 64 idVendor 0x04b4 Cypress Semiconductor Corp idProduct 0x1175 bcdDevice 0401 iManufacturer l S5 Ritt PSI iProduct 2 DRS4 Evaluation Board iSerial 3 REV1 bNumConfigurations 1 Configuration Descriptor bLength 9 bDescriptorType 2 wTotalLength 46 bNumInterfaces 1 bConfigurationValue 1 iConfiguration 0 bmAttributes 0x80 MaxPower 500mA If the board is correctly recognized one can access it with the command line program Under most Linux distributions however only the root user can directly access USB devices Some systems can be configured to allow non root access via the udev system but the exact instructions vary from distribution to distribution and can therefore not be given here Page 10 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual If the command line program works the oscilloscope application drsosc can be started It will open a X window and show exactly the same functionality as its Windows counterpart LC ritt pc6562 1 afs psi ch user r ritt meg online drivers drs drsosc Session Edit View Bookmarks Settings Help root pc6562 1 drsosc drsosc Start Here 7 DRS Oscilloscope Trigger Stop g Single Flo Ry T Fo
6. 8 518 LP2985 3 3 9 1 8 5 e738 H e738 GND Km o 2 5V ae U23 P t 525v RS A sli T Km Two Si 2 5V 38 U24 Si id E r N our t t o sli sli Dsg s 8 Ka E 1 2V Iz U25 z a LIN our t z fe OUT z sli REG1117 1 2 815 gs STA 3 oo ian 3 3V CPU FPGA ADC digital 3 3VANA ADC DAC 2 5V AVDD DRS4 analog 2 5V DVDD DRS4 FPGA digital 1 2V FPGA INT FP1 FP2 DRS4 Evaluation Board 2 RI HU 1 4 98_ 2 9 Paul Sct Rev FIDUCIAL POINT FIDUCIAL POINT ei pa POWER 20 5232 Villigen PSI Date Dec 2008 Drawn by HU14 RS14 Filename DRS4_Evaluation_ Board SMW2 tch6 of 6 B C D Page 23 of 27 ED PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 6 DRSA Evaluation Board Bill of Materials Count ComponentName RefDes PatternName Value Description EEPROM 16kx8 Lemo 00 90 Data Flash 1 WP HH 50 24LC128 SN 44 021 0547 AT45DB161D AD8061ART AD8605ART AD8605ART AD8605ART AD9245 ADCMP600 ADG936 ADG936 ADG936 ADG936 ADR03 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 Page 24 of 27 U19 J5 U
7. El PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DRS4 Evaluation Board User s Manual Board Revision 2 0 as of March 2009 Last revised April 27 2009 Stefan Ritt Paul Scherrer Institute CH 5232 Villigen PSI Switzerland Email stefan ritt psi ch Phone 41 56 310 3728 Please check for possible updates of this manual under http drs web psi ch datasheets J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Revision History Date Modification 2 March 09 Initial Revision 27 April 09 Mention input range added timing calibration description Page 2 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Table of Contents Revision History es poete Erro eh diea ue bo vto e ei e tabs e EE 2 Table of Contents letra alii ili BE era la 3 Tz Ke ee E alano ea aa ziali ie ia ail UL 4 1 1 Board descnpuona ee ee 4 1 2 lier M E 5 E EE e 7 Zali Windows PAA EE 7 2 2 TEX AAA ee EE EE 9 3y Development Hints ee ee 16 3 1 PoWer SUpPPI Ya EE EE l6 3 2 Analog DHDUE SR SRE EN EE 17 3 3 Control te ee dee Ee S 17 3 4 ADE ClO CK qu Gee 17 4 DRS4 Evaluation Board Schematies ie dtes tette date eia eri 18 5 DRS4 Evaluation Board Bill of Matenals eese 24 Page 3 of 27 Lk PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 1 Introduction The DRS4 chip which has been designed at the Paul
8. Scherrer Institute Switzerland by Stefan Ritt and Roberto Dinapoli is a Switched Capacitor Array SCA capable of digitizing eight channels at sampling speeds up to 6 GSPS This chip is available through the PSI technology transfer program for other institutes and organizations In order to simplify the design process to integrate the DRS4 chip into custom electronics an evaluation board has been designed which demonstrates the basic operation of the chip It has SMA connectors for four input channels CH1 to CH4 an USB 2 0 connector and a LEMO trigger input Figure 1 The board is powered through the USB port and contains an on board trigger logic It comes with MS Windows and Linux drivers and two application programs It is basically equivalent to a four channel 5 GSPS digital oscilloscope This manual describes the software installation the usage of the application programs and gives hints for developers seeking to build new electronics around the DRS4 chip 1 1 Board description Since the DRS4 chip has differential inputs the board uses four transformers ADT1 1WT from Mini Circuits to converted the 50 Ohm terminated single ended inputs into differential signals The transformers are followed by analog switches ADG936 form Analog Devices These switches allow the multiplexing of the DRS4 inputs between the input connectors and a reference voltage generated by the on board 16 bit DAC for calibration purposes The four analog inputs a
9. a VME board containing the DRS4 2 Installation 2 1 Windows XP Under MS Windows it is important to install the necessary driver before connection the DRS4 Evaluation Board with the PC The current distribution can be downloaded from http drs web psi ch download The Windows version contains a single program drs xx exe where xx is the version which can be executed to install the driver applications documentation and source code Executing this file starts the installer DRS Setup Welcome to the DRS Setup Wizard This wizard will guide you through the installation of DRS It is recommended that you close all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your computer Click Next to continue Cancel You can select which components to be installed Page 7 of 27 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DRS Setup Choose Components Choose which Features of DRS you want to install This will install the DRS software on your computer Select which optional things you want installed Description Select components to install Start Menu Shortcuts DRS source code Space required 2 8MB Then you can select the installation directory DRS Setup Choose Install Location Choose the folder in which to install DRS Choose a directory to install in to Destination Folde
10. jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual T CA N gt d e E Oo o EN EN E mra lE asm sisti d sibus mat Sew t B Eeee OJ6 1 440J7 1 CU24 o c c Leem O25 1 w Gi Gi 1 10410 8 12426 1 out a 4 10027 l CJ28 Kee OJ13 se ee 1 0029 o cda O14 i 0415 OJ31 DEC CJ16 032 1 70417 t 10018 7OJ19 i 1 OJ20 70421 10122 1OJ23 O a O 8 ES 3 g gw FM m a 2 c HM 2 5 r Se Te L 5 la 0 Mio d o HIE o Q rls o e ze 4 o x CA N Page 21 of 27 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual U16 VBUS D D GND lcls 8 USB CONN B u R12 3 220 R26 Hereen 36 UT to ADC 43 HN n t 2
11. start the domino wave 0 0x00 1 reinit trig Write a 1 to stop amp reset the DRS chip 0 0x00 2 soft trig Write a 1 to stop the DRS chip 8 read the data to RAM 0 0x00 3 eeprom write trig Write contents of RAM into EEPROM 32kB page 0 0x00 4 eeprom read trig Read contents of EEPROM into RAM 32kB page 0 0x02 18 led 1 on O blinks once at beginning of DRS chip readout 0 0x02 19 tcal en Switch on 1 off 0 264 MHz calib sig for DRS chips 0 0x02 20 tcal source System clock 0 or separate quartz 1 clock source 0 0x02 21 transp mode 1 send DRS inputs to outputs transparent mode 0 0x02 22 enable trigger1 Write a 1 to enable external trigger LEMO 0 0x02 23 readout mode O start from first bin 1 start from domino stop 0 0x02 24 neg trigger 1 trigger on high to low transition 0 0x02 25 acalib Write 1 to enable amplitude calibration 0 0x02 27 dactive 0 stop domino wave during readout 1 keep it running 0 0x02 28 standby 1 put chip in standby mode 0 0x02 29 trigger source1 Analog trigger source bits CH1 CH4 0 0x02 30 trigger source2 Analog trigger source bits CH1 CH4 0 0x02 31 enable trigger2 Write a 1 to enable analog trigger 1 0x04 31 16 DACO Set DAC 0 A ROFS 1 0x06 15 0 DAC1 Set DAC 1 B CMOFS 2 0x08 31 16 DAC2 Set DAC 2 2C CAL 2 0x0A 15 0 DAC3 Set DAC 3 D CAL 3 Ox0C 31 16 DAC4 Set DAC 4 E BIAS 3 OxOE 15 0 DAC5 Set DAC 5 F
12. 15 U11 U7 U8 U9 U10 U26 U1 U2 U3 U4 U13 C87 C88 C89 C90 C49 C86 C3 C9 C10 C4 C20 C98 C71 C72 C82 C23 C37 C40 C1 C2 C5 C6 C7 C8 C11 C12 C13 C15 C17 C19 C21 C22 C24 C28 C29 C30 C31 SO G8 CONN PSI2 SO 8 SM SOT23 5 SOT23 5 SOT23 5 SOT23 5 LFCSP VQ 32 SOT23 5 PQFP N20 PQFP N20 PQFP N20 PQFP N20 SC70 5 0402 0403 0404 0405 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 16Mbit 2 5V lu lu lu lu lu lu lu lu lu lu 3 3n 5 6n 12p 12p 15p 33n 56p 56p 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n Amplifier Amplifier Amplifier Amplifier ADC Comparator Capac Capac Capac Capac Capaci Capaci Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capac Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor Producer MICROCHIP Lemo ATMEL ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALOG DEVICES ANALO
13. 3 RES_0603 RES_0603 RES_0805 Page 26 of 27 C74 35 U18 U6 L2 L1 JPl JP2 U29 U28 U27 U23 U22 U12 U30 U14 Q1 U25 U24 U21 R2 R4 R6 R8 R35 R22 R24 R25 R28 R29 R30 R15 R16 R18 R20 R21 R27 R17 R19 R40 R41 R23 R37 R1 R3 R5 R7 R26 R33 R34 R13 R10 1210 DIL14P 2MM SSO G56 QFN 76 1008 1812 TP50MIL TP50MIL PLCC 4 PLCC 4 PLCC 4 SOT23 5 SOT23 5 SSOP16 MSOP 10 S0 G8 QUARZ NKS7 S0T223 SOT223 SOT223 0402 0402 0402 0402 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805 47u 24MHz 100E 100E 100E 100E OE 1k 2 2k 2 2k 4k7 4k7 4k7 4 7E 4 7E 4 7E 4 7E 10E 10k 22E 22E 100E 100E 100k 100k 150E 150E 150E 150E 220E 220E 220E 220E OE Capacitor JTAG UP DRS4 Inductor Inductor Jumper Jumper 150mA Low Dropout 150mA Low Dropout DAC MUX J XS75 12 30 30 800mA Low Dropout 800mA Low Dropout 800mA Low Dropout Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor MOLEX CYPRESS PSI EPCOS EPCOS AVAGO AVAGO AVAGO National National LINEAR
14. 7u 4 7u 4 7u 4 7u 4 7u 4 7u 4 7u 4 7u 4 7u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 100n Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capaci Capac Capaci Capac tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor tor Page 25 of 27 ED PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual PPP NPP PPP HB L a ba PP 2 CAP 1210 CONN MOLEX CY7C68013 56 DRS4 76 IND 1008 IND 1812 JMP2MM JMP2MM LED PLCC 4 LED PLCC 4 LED PLCC 4 LP2985 2 5 LP2985 3 3 LTC2600 MAX4704 MAX6662 QUARZ NKS7 REG1117 1 2 REG1117 2 5 REG1117 3 3 RES_0402 RES_0402 RES_0402 RES_0402 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_0603 RES_060
15. AVEFORM READOUT In order to reduce the noise due to aperture jitter the phase shift between these two clocks must be fixed and contain very small jitter 10ps The easiest way to generate this phase shift is to use the digital clock managers DCM in the FPGA as it is done on the evaluation board Rev 1 1 Since the DCMs have however an inherent phase jitter of 150ps this introduces some noise in form of a baseline variation when sampling a DC signal in the order of up to a few mV If this becomes a problem it is recommended to generate the phase shift between these two clocks with a low jitter delay circuit Page 17 of 27 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 5 DRS4 Evaluation Board Schematics A CA N a v 3 5 2 gt a R5 RI sel A el A o d w m e e 19en cH MIA 4 19en os A 2 coc H gl aa aa 5 al a al o dos cuore c c N 3 lo lo C 2 Ja Je 8 le 8 le 3 88 z8 x8 ola alg zB AB 3 98 3 38 w eS 28 2 E bal 5
16. Auto IL2_JL3_IL4 1 1 4 A LA Seale Scale Scale Scale Ly oz Cw Cw Cursor a 8 Jusna Utili Save Print Config L Measure aen J E The evaluation board Rev 2 0 still shows some small random spikes originating probably from the USB interface It is expected that future versions will improve this and reduce the noise level further Page 13 of 27 ET Jim PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual The DRS4 evaluation board is shipped pre calibrated in amplitude and time This calibration can be turned on or off using the check boxes Display calibrated waveforms and Display timing calibrated waveforms in the Config Dialog Configuration Voltage Calibration Display calibrated waveforms Execute Voltage Calibration Timing Calibration C Connect reference clock to channel 4 v Rotate waveforms relative to trigger v Display timing calibrated waveforms Execute Timing Calibration Display C Display Date Time The calibration can be re done any time by clicking on the Execute Voltage Calibration and Execute Timing Calibration buttons For the voltage calibration the inputs are switched to a calibration voltage generated by a DAC Three calibration points 0 4V OV 0 4V are taken and an offset and gain is evaluation For the timing calibration a 240 MHz clock is sampled in one channel and the devi
17. G GOSEOSSG PA INT 9 5 PD5 FD13 JP2 Serial Fas eR Re EE CEEEECEEERER IPA1 INT1 BEE 24LC128 SN aO 2 A2 SLOE PD7 FD15 FD15 GND ba WP GND master PA3 WU2 HA 8 ay HE x HE PAA4 FIFOADRO mode _L EE t HEI HER 8 BEE IPA5 FIFOADR1 SCH ER A6 PKTEND SD 3X PA7 FLAGD SLCS i5 No ap ar wo IRDY9 SLRD DMINU 18 Sg a d DY SLRD Wes ads dam Onw E 8 Qux IFCLK xTaLouT T32 GH M se I JTAG FPGA Platform Flash 3 0 0 cwm A z B RE U20 3 Zwee EnH 8 i Sy 8 J35 DI GS 5 voci OUTGND N Ia GND NC NO vCCO 8 m SD GND NC 19 CCLK 4 LK VCCINT 17 GND TDI DI TD moa oo us ab GND TOOLS ei NOLI GND TCK TK NOH oN Wb GND GND TMS 4 we roo NOP do GND Vref Ge we e E RESET CEO H3 NOH pone_ e GNI eo XCF02S V020 r Bu DRS4 Evaluation Board H Paul Scher ut Rev o part e ei Lab for electronics 1414 USB FPGA 20 5232 Villigen PSI pi ds Date Dec 2008 Drawn by HU14 RS14 Filename DRS4 Evaluation Board SW2 tch5 of 6 D Page 22 of 27 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual ET 3V gt mE ie U21 MM E N out No_1812 L GND or i 815 REG1117 3 3 315 ST g 8 LI ae 3 3V 38 U22 2 5 pi your o 3 ON OFF ByP 4 OT Mrs Lee
18. G DEVICES ANALOG DEVICES ANALOG DEVICES BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 12 11 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 C33 C35 C36 C38 C41 C43 C45 C47 C48 C50 C51 C52 C53 C54 C55 C56 C57 C58 C61 C62 C63 C64 C65 C66 C67 C68 C70 C76 C79 c91 C92 C25 C32 C39 C44 C46 C75 C77 C78 C80 C81 C83 C85 C14 C16 C18 C26 C27 C34 C42 C59 C60 C73 C84 C69 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 4 7u 4 7u 4 7u 4
19. MAXIM MAXIM ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual PrP PP H RES_0805 R11 0805 OE Resistor RES 0805 R12 0805 OE Resistor RES 0805 R14 0805 OE Resistor RES 0805 R32 0805 OE Resistor RES 0805 R36 0805 OE Resistor RES 1206 R9 1206 51E Resistor RES_1206 R31 1206 120E Resistor RF TRAFO T1 RF TRAFO 750hm Mini Circuits RF TRAFO T2 RF TRAFO 750hm Mini Circuits RF TRAFO T3 RF TRAFO 750hm Mini Circuits RF TRAFO T4 RF TRAFO 750hm Mini Circuits SMA_SMD J1 SMA_SMD SMA Connector Johnson SMA SMD S J2 SMA SMD SMA Connector Johnson SMA SMD S J3 SMA_SMD SMA Connector Johnson SMA_SMD_S J4 SMA_SMD SMA Connector Johnson SN74LVC2617 US SC 70 Pe aa TI USB_CONN_B U16 USB_CONN_B Lumberg Oszillator VX3 Q2 VX3 66MHz Oszillator VX3 XC3S400 TQ144 U17 TQFP144 FPGA XILINX XCF02S V020 U20 TSSOP20 EEPROM XILINX Page 27 of 27
20. Managers DCM ucf drs4 evall ucf Constraint file Assigns package pins and defines clock constraints 3s400 drs4 evall ise Xilinx ISE 9 2i project file 35400 drs4 evall bit Compiled firmware image directly for Spartan 35400 FPGA Page 5 of 27 ET Jim PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 3s400 drs4 evall mcs Compiled firmware image for FPGA EEPROM XCF02S 3s400 drs4 evall ipf Xilinx Impact project file to program FPGA via download cable The firmware for the USB microcontroller from Cypress is written in C and must be compiled with the Keil 8051 C compiler It contains the standard include and library files from the Cypress EZ USB development kit plus some DRS specific files CY7C68013A drs_eval c Main micro controller firmware file CY7C68013A dscr a51 USB descriptor tables CY7C68013A drs_eval hex Compiled firmware file Intel HEX format CY7C68013A drs evall iic Compiled firmware file For Cypress EZ USB Console download CY7C68014A Remaining files are standard files from EZ USB development kit The FPGA firmware implements a set of control and status registers through which the DRS4 can be controlled and read out The mapping of the control registers is as follows Ofs Bit Name Comment 0 0x00 0 start trig Write a 1 to
21. SAINI i IP 1 HF gt EH ii i ii Figure 2 PCB pad under the DRS4 chip Page 16 of 27 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual These vias should be solder filled or plugged The maximum power dissipation of the DRS4 chip is not critical 350 mW but an improved thermal stability helps the performance of any analog chip To maximize the coverage and adhesion between the DRS4 and the PCB the copper plane could be partitioned into several uniform sections providing several tie points during the reflow process 4 2 Analog Input If non differential signals should be digitized with the DRS4 chip they must be converted into differential signals for the DRS4 inputs The simplest solution is to connect the IN inputs to AGND and to connect the signals directly to the IN inputs This method has however the disadvantage that the crosstalk and noise immunity of the DRS4 chip are worsened The evaluation board uses passive transformers ADT1 1WT from Mini Circuits for this purpose While this is a good solution to reduce the power consumption of the board such that it can be powered from the USB power 500 mA 5V it has the disadvantage that it reduces the analog bandwidth of the system to about 200 MHz 3 dB The reason for this is the dynamic capacitive load of the DRS4 inputs which must be driven by the signal source Since the input impedance of the DRS4 becomes very small at high frequencies the sig
22. TLEVEL 4 Ox10 31 16 DAC6 Set DAC 6 G O OFS 4 Ox12 15 0 DAC7 Set DAC 7 H Page 6 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 5 0x14 31 24 configuration Bito DMODE Biti PLLEN Bit2 WSRLOOP 5 0x14 23 16 channel_config 1 1x8k 0x11 2x4k 0x33 4x2k 0xFF 8x1k 5 0x16 7 4 first chn First channel address to read out 0 9 5 0x16 3 0 last chn Last channel address to read out 1 9 6 0x18 31 16 trigger delay Trigger delay in ticks of roughly 0 56 ns 6 Ox1A 15 0 sampling freq Sampling frequency in ticks 1024 fsamp 0 120 2 7 Ox1C 31 16 zero supp thresh Not yet implemented 8 OdE 15 0 eeprom page Page number for EEPROM communication While the mapping of the status registers 1s like this Comment 0 0x00 31 16 OxCODE Magic number for DRS board identification 0 0x02 15 8 board type 5 for DRS4 USB Evaluation Board 1 1 IO 0x2 7 0 ds pe 4for DASA L1 0x4 0 running T while domino wave running or readout in progress 8 0x20 1 16 temperature temperature in 0 0625 deg G unis 9 0x4 31 16 serial_ome Serial number OMGboard SSS 0x26 15 0 version fw firmware version SVN reviso All registers are implemented as 32 bit registers so they can be mapped easily into some VME address space for example if one decides to build
23. ar regulators together with the usual decoupling capacitors are recommended for all power supplies The analog power supply AVpp powers only the domino circuit of the DRS4 chip and directly influences the jitter of the sampling frequency Long term variations in this power supply seconds are regulated by the on chip PLL but high frequency noise in the MHz region leads directly to an increase of the PLL jitter Therefore the evaluation board contains two separate 2 5V linear regulators for the DRS4 chip one for the AVpp power and one for the DVpp power Although the DVpp power is called digital power it powers also the analog output buffers of the DRS4 chip and needs the same good quality than the AVpp power in order to minimize the noise of the board The DRS4 chip also contains two grounds AGND and DGND They can be either routed separately on the board and be connected at the power source or they can be directly connected to an overall dedicated ground plane of the PCB Tests have been shown that the latter choice gives slightly less noise The bottom of the QFN76 package of the DRS4 has an exposed paddle connected to the internal DGND It is recommended that this paddle is matched by a PCB pad of similar size connected to analog ground to achieve the best electrical and thermal performance of the DRS4 The copper plane should have several vias to achieve a good heat dissipation to flow through the PCB as shown in Figure 2
24. ation from the expected period to the measured period is used to determine the effective width of each cell This calibration data both for voltage and timing is then stored in the EEPROM on the evaluation board from where it is obtained each time the oscilloscope is started Page 14 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For test purposes an internal 60 MHz reference clock signal can be connected to channel 4 via the Config menu To do so activate channel 4 then select the Config menu and click on Connect reference clock to channel 4 4 DRS Oscilloscope WS Til Stop O Normal RI Auto OiOzO3s 4OgxT Horizontal 20 ns div D Vertical Voltage Calibration Voltageon 0 Display calibrated waveforms Execute Voltage Calibration Timing Calibration 100my 100mV Rotate waveforms relative to trigger Display timing calibrated waveforms v Execute Timing Calibration Save Print Display Config Measure Display Date Time Cursor Connected to USB board serial 2034 firmware revision 13279 T 45 5 C The effect of the timing calibration can be tested by turning the timing calibration on and off via the Display timing calibrated waveforms check box You can save a waveform in an ASCII and a binary format by pressing the Save button After you open a file each trigge
25. coupled Maximum allowed input voltage 0 5 V to 42 8 V Trigger input Termination 500 Maximum allowed input voltage 0 5 V to 5 5 V 5V TTL compatible High Level Input Voltage 2 2 V max 1 2 Firmware Description Both the Windows and the Linux distribution contain a subdirectory firmware which contains the FPGA and Microcontroller firmware for the DRS4 Evaluation Board The FPGA firmware is written in pure VHDL thus making it easy to port it to other FPGA devices such as Altera or Lattice Only a few Xilinx basic components such as clock managers and I O blocks have been instantiated and must be adapted when another FPGA manufacturer than Xilinx is chosen The FPGA source code is contained in several files with following contents src drs4 evall vhd Top level entity Routing of clock signals global reset signal LEDs and LEMO input src drs4 evall app vhd Main file containing state machines for DRS4 readout serial interface to DAC EEPROM and temperature sensor trigger logic and reference clock generation src usb dpram vhd Instantiates block ram for waveform storage src usb racc vhd Interface to CY2C68013A microcontroller in slave FIFO mode Implements a set of status and control registers through which the main application can be controlled src usr clocks vhd Generates 66 MHz 132 MHz 264 MHz and a phase shifted 66 MHz clock out of the 33 MHz quartz input frequency via the Xilinx Digital Clock
26. ial 2609 firmware revision 10901 Board index type 20809 10901 38 4 C 2 66606668 Domino wave running PLL locked Control reg 68 E66061 DMODE circular TRANSP_MODE enabled Hardwar trigger enabled Readout from stop Frequency 0 999 GHz ij Oscilloscope application The second application is an oscilloscope like program which connects to the DRS4 board and works pretty much like a normal oscilloscope You can select the trigger mode trigger level and trigger source On Rev 1 1 of the DRS4 evaluation board only CHI can be selected as trigger source You enable a channel by clicking on the number 1 to 4 There are two cursors and a few utilities Page 12 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Connected to USB board serial 2011 firmware revision 13099 T 37 3 C The picture above shows an un calibrated evaluation board which shows Stop Single LA Force Trigger O Normal 4 Auto Horizontal I 100 ns div D L1 JL2 JL 3 JL 4 J CEE L gt Ala 4 la Scale Scale Scale Scale L a e Msnap Utility sw mw L pg IL ge about Te a noise level of about 8 mV RMS After offset and gain calibrations the noise level is reduced significantly cA Connected to USB board serial 2011 firmware revision 13099 T 37 8 C Stop Single Force Trigger D Normal 4
27. nal height drops if only driven passively Better performance is achieved with active differential drivers Tests have been made with the THS4513 from Texas Instruments giving a bandwidth of 450 MHz and the ADA4937 from Analog Devices giving 700 MHz A small bypass capacitor 1pF in the feedback loop of the buffer adds a high frequency pole which shows up as a peak in the response function but then pushes the bandwidth to 750 MHz The peaking can be reduced by adding a series resistor of a few Ohm between the buffer output and the DRS4 input The usual design rules like proper termination and matched impedance PCB traces apply as in any high frequency analog design 4 3 Control Voltages The DRS4 chip requires certain control voltages ROFS O OFS and BIAS The latter two are generated internally with some default voltage but can be overwritten by an external low impedance source It is recommended to connect these lines to an external 16 bit DAC so that the DRS4 input range can be fine tuned on a board by board basis to compensate for chip variations The ROFS signal should be driven by a high speed low noise buffer If this signal would be directly connected to the DAC output the signal height would change slightly during the chip readout and the measurement would show a varying baseline level 4 4 ADC Clock There is a very strict relation between the DRS4 output shift register clock SRCLK and the ADC clock see DRS4 data sheet W
28. ns a command line interface and an oscilloscope These applications are explained in section 3 2 2 Linux The drivers and applications are distributed for Linux in source code and must be compiled on each system First untar the tar ball Page 9 of 27 ET Jom PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual usr local tar xzvf drs 1 0 tar gz drs 1 0 drs 1 0 doc drs 1 0 doc DRS4_rev06 pdf drs 1 0 doc manual pdf drs 1 0 include drs 1 0 include ConfigDialog h drs 1 0 include DOFrame h drs 1 0 include DOScreen h Then change the directory and do a make Note that to compile the oscilloscope application it is necessary to have the wxWidgets package version 2 8 9 or later installed You can obtain this package in source form from http www wxwidgets org downloads If this package is present you can change to the drs directory and issue a make usr local ed drs 1 0 usr local drs 1 0 make g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX DHAVE LIBUSB c src musbstd c g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX DHAVE LIBUSB c src mxml c Now you can connect the DRS4 board to the PC On systems where the lsusb tool is installed one should be able to find the DRS4 evaluation board after connecting it with following command usr local drs 1 0 sbin lsusb d 04b4 1175
29. r C Program Files DRS Space required 2 8MB Space available 148 3GB After the installer has finished you can connect the DRS4 Evaluation Board to the Computer E DRS Setup Installation Complete Setup was completed successfully Completed BRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR Show details DRS Setup Now you will see the Found New Hardware dialog Page 8 of 27 ET jm PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for DRS4 evaluation board 4 If your hardware came with an installation CD WE or floppy disk insert it now What do you want the wizard to do ei O Install from a list or specific location Advanced Click Next to continue Where you can click Install the software automatically and then click Next After successful installation of the driver you will see the following window Found New Hardware Wizard All Programs as start Completing the Found New Hardware Wizard The wizard has finished installing the software for e DRS4 evaluation board Click Finish to close the wizard BE DRS Oscilloscope m DRS Command Line Interface T DRS4 Datasheet p Evaluation Board Manual Uninstall DRS Software Log Off Shut Down s ms5tuI The software comes with two applicatio
30. r AC coupled and have a input range of 1 V peak to peak The absolute maximum input voltage range is 0 5V to 2 8V The DRS4 is read out with a 14 bit ADC AD9245 from Analog Devices and a FPGA Xilinx Spartan 3 The USB connection is implemented with a micro controller Cypress CY2C68013A The high speed modus of the USB 2 0 bus allows for data transfer rates of more than 20 MB sec gt gree i B 1 refe n rej Sei E FE zi c LEICICIES Figure 1 Picture of the DRS4 Evaluation Board with different components Page 4 of 27 ET Jom PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For trigger purposes a 50 O terminated TTL compatible input is implemented Lemo connector Since the input is 50 O terminated care has to be taken that the trigger source is able to drive at least 2 2 V into 50 O A on board discriminator with programmable level allows for self triggering on any of the four input channels An 1 MBit EEPROM 25LC1025 from Microchip is used to store the board serial number and calibration information Two 14 pin headers carry all important logical signals which allow easy debugging with a logic analyzer or oscilloscope A JTAG adapter can be used to update the FPGA firmware through a Xilinx Platform Cable Adapter The specifications of the board inputs is summarized in following table Analog inputs Termination 500 Input range 1 V p p AC
31. r will write the waveform of the active channel s to that file When you are continuously running the file will grow very quickly If the file has the extension xml it will be written in ASCII form using XML encoding otherwise a raw binary file will be written with following contents Byte Contents 0 LSB First cell first channel 16 bit value 0 0 5 V 65535 0 5V 1 MSB 2 LSB Second cell first channel 16 bit value 3 MSB 2048 LSB First cell second channel 16 bit value Page 15 of 27 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 4 Development Hints The idea behind the evaluation board is to make first steps in using the DRS4 chip but then develop your own custom electronics around the chip The first thing to do there is to study carefully the DRS4 data sheet which can be obtained from http drs web psi ch datasheets Then have a look at the DRS4 Evaluation Board Reference Design which schematics is supplied at the end of this document When you start to design your own electronics there are however some important points which are not necessarily obvious from the data sheet or from the reference design These points together with some design tips are explained in this section 4 1 Power Supply As with any analog design the quality of the power supply is very important since it has an influence of the noise level measured by the DRS4 chip Low noise line
32. rce Trigger Normal 4 Auto 1OzC Horizontal 100 ns div D Vertical l 2 3 J 4 J Scale Scale Scale Scale Cursor A B KM Snap Utility Save Print Config Measure About Exit Connected to USB board serial 2011 firmware revision 13099 T238 4 C 1 13 10 E e e sa e Monday 2009 03 02 3 Running the Board 3 1 Command line Interface drscl Clicking on DRS Command Line Interface Windows or entering drscl Linux will start a simple application which connects to the DRS4 Evaluation Board If it finds the board it displays the board serial number and the firmware revision as on the following screen shot Page 11 of 27 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual ommand Line Interface DRS command line tool Revision 12947 Type help for a list of available commands Found mezz board on USB serial 2009 firmware revision 16961 GK Now you are ready to issue your first command info which shows some more information like the current board temperature The temperature sensor is on the bottom side just below the DRS4 chip If you keep issuing info commands and touch that sensor with your finger you should see the temperature increase ev DRS Command Line Interface DRS command line tool Revision 12947 Type help for a list of available commands Found mezz board on USB ser
Download Pdf Manuals
Related Search