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78M6613 Split-Phase Firmware Description Document

1. 30 Appendix B SLIP Interface oecccccesecscccc ccccceesceesceeecceccescteeedeececeecessececcacsacesaesaccusaesdeexsievsaservexeusanieasieats 31 B T Packet Format and 31 B 1 1 Packet FOmMat 31 B12 Starb and 31 Address UTEE 31 Bila Data 32 32 Rev 2 3 78M6613 Split Phase Firmware Description Document UG_6613_090 B PACKS TY DCS eR ROG ina 32 Example 1 Read Command Packet iiicii iisweieveiscecsevscevi cous cdvaceva cess cevacidacesscivacevscdtacscecees 37 Example 2 Write Command 8 37 Example 3 Contiguous Block Read Command Packet ccecceeeeeeeeeeeeceneeeeeeeeeeeeeenaaes 37 Example 4 Contiguous Block Write Command Packet ccccceceeeeeeeeeeeeeceeeeeeeeeeeeetaaes 38 Example 5 Device Information Command 8
2. 25 A 1 Identification COmMana wis sci ssscasssesessstsaseaesduuebagsdauebags duuebags usuais duumbagngadubans oadebadeumecuaddeancuateaee 25 25 AS Data Access Commands ers EEEE EEEE E 26 ALS 26 9 2 sisari EAEE EEEE EEEE 26 A339 26 A334 ConCatenated 845 27 A3 5 Repeat 27 A3 6 LE Data ACCESS 28 Write COMMANGS te tenons EEE E A E 29 A 4 1 MPU Register Write 8 5 29 A 4 2 Register Write 5 29 29 A 5 1 Complete Calibration 29 A 5 2 Atomic 8 1 8 8 45
3. 6 1 2 2 Floating Reference Sensor Configuration 7 1 3 Measurement Equations six cee neta res e E O 9 1 4 Sampling and Update Rates ccc cece cece cece cece eee EE HEHE EERE HEHE RHEE 9 2 Functional D SCription sssrin aaa auaa daaa aaa sede codecs sesceds aaia aaaeeeaa anaita i aatend 10 2 1 Initialization and 5 10 2 2 Sensor Hardware 10 2 3 AC Measurement and 10 2 4 Configuration and 12 2 41 ROGISUCUS x ee Se cea eee 12 24 2 Calibrations cs oes css evs
4. eenen nenen ennen 38 Example 6 CLI Toggle Command 38 B 3 Command 5 815 39 Revision Hst ae aA dae AAAA AAAA 40 Figures Figure 1 Simplified Connection Diagram with Fixed 6 Figure 2 Simplified Connection Diagram with Floating 7 Figure 3 Simplified Signal Processing 11 Figure 4 Split Phase Calibration Test 6 reer 19 o cht 16 Tables Tablet DI
5. gt X gt gt CT gt HPF gt re COMP uu i gt DELAY HPF gt f PRECISION JARAW X COMP REFERENCE RA cavat IA gt gt SINC p iY pecimator 7 sense las gt R gt HPF gt POINT MODULATOR gt gt gt CAL_IB vB gt Fact gt PEMY HPF lL ver COMP TEMPERATURE GAIN_ADJ IM gt PLL ycoour _ x gt gt LINE FREQUENCY FREQ gt TMP QUANTA A VA RAW B1 vet AFE gt F sN QUANTB WATTA WATTASUM WATTA TMP1 gt gt WATTBSUM iie R A WATTA WATTA BSUM WATT B VARA gt gt VAR 90 aF gt VARB VARASUM VAR A Tu QUANT VARA gt VARBSUM VARB VAR 90 PPO gt gt gt QUANT_VARB 2 x N v asa IASQSUM gt gt gt IrmsA i 5 Bsa y IBSQSUM 9 gt gt IrmsB VASQSUM VA VASQ y gt gt Vrms A VBSQSUM vBSQ iste ill VB1 gt gt Vrms B t VABSQSUM L _VABSQ y gt gt gt Vrms A B Figure 3 Simplified Signal Processing Flow Rev 2 11 78M6613 Split Phase Firmware Description Document UG_6613_090 2 4 Configuration and Control 2 4 1 Input Registers The following parameters are configurable by the user via input registers e Sensor range and configuration e Calibration targets and coefficients e Squ
6. The value of voltage and current are calculated as true RMS The calculation requires an accumulation of samples over time accumulation interval as follows 15 274 4 In v17 1 22 Vn rms 2 Similarly for power PWR 112V1 2 V2 Fn e fn Where n is the number of ADC samples in an accumulation interval for a given sample rate firms 1 4 Sampling and Update Rates This firmware utilizes an effective sampling rate of 3 641 samples per second for each sampled input While the CE continuously accumulates sampled data at the sampled rate status and measurement data updates to the MPU are less frequent These updates include e Sag status is updated at every Mux Chcle for low latency alarm detection e Measurement outputs and all other alarm conditions are updated every accumulation interval which is set to 500msec for this firmware build Rev 2 9 78M6613 Split Phase Firmware Description Document UG_6613_090 2 Functional Description This section summarizes the functional operation of the 78M6613 Refer to the 78M6613 Data Sheet and application notes for more information on IC operation and terminology 2 1 Initialization and Start up Upon power up both MPU and Compute Engine CE cores start executing the application code from designated blocks of Flash memory Status indicators for Ready and Active are available to the host via DIO pi
7. 22 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document CE Parameter QUANT VAR B QUANT IA QUANT IB Reserved Temperature Gain Adjust VREF_CORR Rimbalance_CORR Locatio n hex 1015 1016 1017 1018 1019 101A 101C LSB VMAX A IMAX B 1 8541E 10 Watt IMAX A 4 6351E 11 7 IMAX B 4 6351E 11 7 16384 is the default and is a gain of 1 Default 16384 Comment Compensation added to the VAR calculation for Phase B Used for compensation at low current levels Keep below 10000d Phase A input compensation added for input noise and truncation in the squaring calculation for Used for compensation at low current levels Keep below 10000d Phase B input compensation added for input noise and truncation in the squaring calculation for I Used for compensation at low current levels Keep below 10000d Reserved 32767 is the max giving a gain of 2 Vref correction Resistor Imbalance correction Rev 2 23 78M6613 Split Phase Firmware Description Document UG_6613_090 4 Serial Communication The serial communication with the 78M6613 takes place over a UART UARTO interface The default settings for the UART of the 78M6613 as implemented in this firmware are given below Baud Rate 38400bps Data Bits 8 Parity None Stop Bits 1 Flow Control None The host s serial interface
8. 26 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document 3 4 Concatenated Reads Multiple commands can also be added on a single line Requesting information in decimal from two locations and the block command from above are given below gt 327 35 20 2E lt CR gt Note The number of characters per line is limited to no more than 60 A 3 5 Repeat Command The repeat command can be useful for monitoring measurements and is efficient in demands from the host If the host requests the contents of eight consecutive addresses with the following command string If the host then desires this same request without issuing another command the repeat command can be used gt no carriage return needed for the repeat command The host only needs to send one character rather than an entire string Auxiliary Description Various Commands Typing a comma repeats the command issued from the previous command line This is very helpful when examining the value at a certain address over time such as the CE DRAM address for the temperature The slash is useful to separate comments from commands when sending macro text files via the serial interface All characters in a line after the slash are ignored Rev 2 27 78M6613 Split Phase Firmware Description Document UG_6613_090 A 3 6 CE Data Access The CE is the main signal processing unit in the dev
9. are the CLI command characters A following carriage return lt CR gt is used to initiate the commands A 1 Identification Command The command is used to identify the revisions of Demo Code and the contained CE code The host sends the command to the 78M6613 as follows gt lt CR gt The 78M6613 will reply to the host the following V1 00 2s FO W 78M6613 Split Phase 3 S2 Aug 16 2011 gt A 2 Reset Commands A soft reset of the device can be performed by using the Z command The soft reset restarts code execution at addr 0000 but does not alter XRAM contents The soft reset also sets all the registers to their default values To issue a soft reset to the device the host sends the following gt Z lt CR gt The W command acts like a hardware reset The energy accumulators in XRAM will reset back to zero Z Reset Description Allows the user to cause soft resets Usage Z Soft reset W Simulates watchdog reset Rev 2 25 78M6613 Split Phase Firmware Description Document UG_6613_090 A 3 Data Access Commands All the measurement calculations are stored in the data range of the device The host requests measurement information using the data access command which is a right parenthesis gt addr lt CR gt To request information the host sends the data access command the address in hex which is requested the format in which the data is desired Hex or Decimal and a carriage
10. C 0 1 C 0 01Hz 0 01Hz 1 000 Vpk 1 000 Vrms 1 000 Vrms Default gt wo 220 120000 7000 5900 6100 80000 100000 140000 700 700 Comment Measured value to fall within this set tolerance plus minus the target Watt value for the calibration to be complete Number of attempts to reach the target value within the programmed tolerance Target nominal temperature for calibration Target Watts used for calibration for both Phase A and Phase B Minimum Temperature Alarm Threshold A temperature below this threshold will set the alarm bit 0 of the Alarm Status Register Maximum Temperature Alarm Threshold A temperature above this threshold will set the alarm bit 1 of the Alarm Status Register Minimum Frequency Alarm Threshold A frequency below this threshold will set the alarm bit 2 of the Alarm Status Register Maximum Frequency Alarm Threshold A frequency above this threshold will set the alarm bit 3 of the Alarm Status Register Sets an alarm bit 4 of the Alarm Status Register if voltage drops below the SAG threshold and CESTATUS register bit5 or and bit6 are set Minimum voltage level selected to flag user bit 19 of the Alarm Status Register Peak voltage setting that user wishes to flag bit 6 of the Alarm Status Register Wideband Power Factor Negative Threshold A less negative wideband power factor than
11. sees a se 12 21419 COMM Ol eee 14 24 34 8 4 1 15 2 44 Sag Detection 6 5 16 2 4 5 Creep 5 16 2 4 6 Limit Registers 8 8 16 3 Split Phase M API Register Map cccccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseaaeaaaaaaa 17 Syl OULPUIU ER OCISLORS 17 EERU Aa Ee E E A E E A A 19 3 3 PRIAME R R 22 4 Serial Communication sce ete eae 24 4 1 CLI Firmware Applications Averell keke helen eden ok annb okt eau ihldcadd es ae Ree eee ae 24 42 SLIP Finmware AppliCauions ene ATS 24 5 Contact 24 Appendix A Command Line 868 iii ini lini
12. Calibration Status Voltage CAL A Command Status BIT2 Voltage CAL Command Status BIT3 Phase CAL A Command Status BIT4 Phase CAL B Command Status 5 Current CAL A Command Status BIT6 Current CAL B Command Status BIT7 Watt CAL A Command Status 8 Watt Cal B Command Status BIT9 29 Reserved BIT30 UPDATE_FLASH_MPU Command Status BIT31 UPDATE_FLASH_CE Command Status Set the value of this register to 1 to use RS232 mode as the UART interface point to point CMD UART CONF F1 0 A value of 0 sets the UART interface as RS485 mode 7 where DIOs are needed to control the host s Rx device s Tx_Enable bit and to use as the device s address to support multi drop RS485 devices Rev 2 39 78M6613 Split Phase Firmware Description Document UG_6613_090 Revision History Revision Date Description 1 0 5 2011 First publication Added Section 1 1 Terminology Added Section 2 4 3 Relay Control 2 12 2011 Added Section 3 Split Phase M API Register Map Added Section 4 2 SLIP Firmware Application Added Appendix B SLIP Interface 40 Rev 2
13. ICREEP A IMAX A ICREEP B IMAX B Unused NOM_TEMP Reserved Config Location hex AO N A4 A Al A7 BC LSB 1 000 Vrms 1 1000 Arms 1 1000 Arms 1 1000 Arms 1 1000 Arms Default 471500 52000 52000 Comment External RMS voltage corresponding to 250 mVpk Max ADC range VMAX Calculation VMAX 250mV V2 Rehunt Rseries Rshunt Minimum RMS current to be reported for Phase A Currents measured below this value will be ignored External RMS voltage corresponding to 250 mVpk Max ADC range IMAX Calculation IMAX 250mV V2 Rshunt Minimum RMS current to be reported for Phase B Currents measured below this value will be ignored External RMS voltage corresponding to 250 mVpk Max ADC range IMAX Calculation IMAX 250mV V2 Rshunt Unused Temp_raw_x reading at 22 C Needed to enable temperature compensation Reserved This register is 1 byte size and is used for controlling the Min Max and accumulation data as follows when the bit is set BITO WPulse goes into DIO6 BIT1 Reserved BIT2 Reserved BIT3 Start Min Max BIT4 Restart Min Maz BIT5 Allow Negative Power Factor Clear Counts BIT7 Clear Accumulation data Wh Rev 2 19 78M6613 Split Phase Firmware Description Document UG_6613_090 MPU Parameter Calibration Status Tolerance on Phase Reserved Calibrati
14. IMAX External RMS current corresponding to 250 mVpk at the current input of the 78M6613 It should be set IMAX Vpk V2 Rsense e VARs Reactive Power Q e VAs Apparent Power S e Watts Active Power P e VMAX External RMS voltage corresponding to 250 mVpk at the voltage input of the 78M6613 It must be set high enough to account for overvoltages Rev 2 5 78M6613 Split Phase Firmware Description Document UG_6613_090 1 2 Hardware Assignments The firmware supports two different hardware configurations for measuring a split phase load The settings in the CESTATE register must correlate to the selected hardware configuration represented in Section 1 2 1 and Section 1 2 2 All measurement results command routines and configuration registers are accessible through the TX and RX pins of serial 0 interface UVARTO RS232 Additional 78M6613 pins utilized by this firmware are listed in Table 1 Table 1 DIO Assignments DIO Direction Purpose DIO6 Output WPulse SLIP and CLI DIO17 Output Ready Active SLIP and CLI DIO7 DIO19 Output Relay Control SLIP and CLI DIO16 Output SAG SLIP and CLI DIO8 DI04 DIO5 Input RS485 Address SLIP only DIO15 Output RS485 Tx_Enable SLIP only DIO14 Input Invoke Boot Loader SLIP and CLI DIO17 Output Boot Loader Pulse SLIP and CLI RTC Real Time Clock LCD Driver and Battery Modes are not supported by this fir
15. UG_6613_090 78M6613 Split Phase Firmware Description Document 2 4 3 1 TC Command This section applies to the CLI version of the split phase firmware The SPI firmware controls the relays directly using the FO register described in Section 2 4 3 Refer to the 78M6613 Split Phase Evaluation Board User Manual for the specific hardware design The format of the TC command is as follows where it is not a case sensitive gt tc is the same as gt TC or gt Tc or gt tC gt TCxx where xx is a hex value with each bit represents the setting of each channel The value of each bit is determined as 1 closing and 0 opening 0 Both channels will be processed sequentially starting from the highest channel number first with a sequence delay time in between It is important to note that if the polarity for each Channel is inverted bit 1 of the Relay Config register OxFO will be set accordingly in order for the Relay Control to work properly The TC commands are summarized in the following table TCx Relay Control Commands Description Allows the user to control the relay of all channels in one command Usage The TC command can be used to turn on off relay of both channels Each bit represents the control 1 on O off for each channel where the LSB represents the lowest channel number Examples TC1 or TCO1 Relay ON for Outlet 1 OFF all others TC2 or TCO2 Relay ON for Outlet 2 OFF all others TC3 or TCO3 Relay ON for both cha
16. example OxDB data byte will appear as OxDBDD B 1 3 Device Address The SLIP based interface supports a single master and multi slave devices configuration Messages are broadcasted on the bus by the master The device address is contained in the message packet so that only the specific device responds to the broadcast request Since the device cannot detect presence of other devices on the network it is the task of the host to manage the device addresses from the initial response to make sure no two devices with the same address are present as collision will occur One byte device address ranging from 0x00 0x7F shall be assigned to each 78M66xx device Device address for each 78M66xx device shall be hardcoded using the DIO lines for example device addresses in the range of 0x00 to 0x07 can be assigned by using three input DIO lines The response packet shall be embedded with the responding device s address to identify the source of the packet and other devices shall ignore the response packet The packet transaction is always a command response pair such that the master will initiate the communication by sending a request packet to a device with an assigned address Only the addressed device will respond to the master by a NACK in the case of a bad packet or an ACK followed by a response packet in the case of a good packet to complete the transaction Rev 2 31 78M6613 Split Phase Firmware Description Document UG_6613_090
17. from simulations using the above equations V1 Line 1 Voltage V2 Line2 Voltage Vref ADC input Neutral V3P3_REF Va ADC input Line1 V3P3REF V1 and V2 are reconstructed as the resulting values from 1 Table 2 Simulation Results v MZ vrar va a ica een aei 120 120 0 120 120 120 100 120 9 768 109 768 100 120 0011429 80 120 19 535 99 535 80 120 0002381 60 120 29 303 89 303 60 120 001381 40 120 39 07 79 07 40 120 0004762 20 120 48 838 68 838 20 120 001619 0 120 58 605 58 605 0 120 0007143 va vret va E A 120 120 0 120 120 120 120 100 9 768 110 232 120 99 99885714 120 80 19 535 100 465 120 79 9997619 120 60 29 303 90 697 120 59 99861905 120 40 39 07 80 93 120 39 99952381 120 20 48 838 71 162 120 19 99838095 120 0 5 58 361 61 639 120 0 498904762 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document 1 9 Measurement Equations The Split Phase Library provides the user with continuously updated Wideband measurement data Wideband measurements are generally of interest when measuring in systems that tend to have non sinusoidal waveforms Table 3 lists the basic measurement equations for the Wideband methods Table 3 Measurement Equations Definitions Symbol Parameter Wideband Equation v Nuit I V O P i t vit Q Q 5 Sov PF PIS PA Phase Angle ACOS P S
18. port is required to implement these settings on its UART In addition the 78M6613 Split Phase Firmware is available with one of two protocols The two available protocols are briefly summarized below and fully documented in the Appendices 4 1 CLI Firmware Application The Command Line Interface CLI provides a simple ASCII interface to access input and output registers and to invoke commands The CLI interface connects to a HyperTerminal or any other terminal emulation SW The CLI interface can also be used to interface to a host processor Appendix A describes the CLI commands and syntax 4 2 SLIP Firmware Application The Serial Line Interface Protocol is a simple binary UART protocol defined to support single e g RS232 or multi point device e g RS485 interfaces Appendix B describes the SLIP protocol and command response format of the data packet 5 Contact Information For more information about Maxim products or to check the availability of the 78M6613 contact technical support at www maxim ic com support 24 Rev 2 6613 090 78M6613 Split Phase Firmware Description Document Appendix A Command Line Interface This appendix describes a serial interface protocol called Command Line Interface CLI This interface facilitates communication via UART between the energy measurement device and the host system by use of ASCll based commands and responses The characters following the command prompt symbol gt
19. 22 Unsigned Rev 2 17 78M6613 Split Phase Firmware Description Document UG_6613_090 Output Power Factor A Phase Angle A Wh A Net Vrms B Watts B Wh B Export Wh B Import Irms B VAR VAB Power Factor B Phase Angle B Wh B Net Watts Total Address A Data nr ex _ Resolution Type Description 0 001 Phase A Power Factor The output will be between 0 950 and 1 000 0 001 Signed Phase A phase angle The output will be between 180 000 and degrees 9 180 000 a E Phesss 0001 Serea Phase B Power Factor The output vil be 0 380 and 000 0 001 Phase B phase angle The output will be between 180 000 and degrees 180 000 1 1000 WattHr Energy Phase B Net 90 171000 watt Power Total Phase A and B Wh Total Export 1 1000 WattHr Energy Total Export Wh Total Import 1 1000 WattHr Energy Total Import Irms Total VAR Total VA Total Wh Total Net Vrms A B arooowatr unsonea eneayToaWey oooO Positive power factor is defined as current lagging voltage inductive Negative power factor is defined as voltage lagging current capacitive 18 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document 3 2 Input Registers MPU Parameter VMAX
20. 8 CO Master sends read command Request Packet to read MPU register 0x0200 lt C0 07 00 00 CO II Device sends ACK CO 07 00 00 00 00 07 31 CC 90 CO Device sends out register data 0x000731CC For a failed transaction gt 00 07 10 03 10 ED CO Master sends read command Request Packet to read MPU register 0x0310 CO 07 00 00 CO Device sends ACK Packet receipt successfully lt C0 07 00 84 00 00 00 00 31 CO Device sends out an error code of 0x84 Example 2 Write Command Packet In this example the master sends a command request to write data 0x000927C0 to the MPU register address 0x0200 of the device with device address 0x07 The device accepts the write command by sending out an ACK followed by a command response packet after successfully completing the write command gt C0 07 11 02 00 00 09 27 DB DC EF CO Master sends command request packet to write to the register addr 0x0200 CO 07 00 00 CO Device sends ACK lt CO 07 00 00 00 00 CO Device sends out command response packet after successful write Example 3 Contiguous Block Read Command Packet In this example the master sends a command request to read three contiguous MPU registers from starting address 0x0200 of the 661x device with device address 0x07 The device accepts the block read command by sending out an ACK followed by the register data The next example is when the command packet attempts to read an invali
21. Alarm Based on setting of CESTATUS register Bit 5 LOPENB Line open on Phase B Bit 6 MAXV A over maximum voltage on Phase A Bit 7 LOPENA Line open on Phase A Bit 8 MAXIA maximum current exceeded on Phase A Bit 9 Reserved 0 Bit 10 Reserved 0 Bit 11 PFA min Power Factor Min limit exceeded on Phase A Bit 12 PFA Max Power Factor Max limit exceeded on Phase A Bit 13 Reserved 0 Bit 14 maximum current exceeded on Phase B Bit 15 Reserved 0 Bit 16 Reserved 0 Bit 17 PFB min Power Factor Min limit exceeded on Phase B Bit 18 PFB Max Factor Max limit exceeded on Phase B Bit 19 Multi Fault When Vrms total lt Vmin 2 Vmin register 0xD5 Bit 20 MAXIT Total current Phase A and B Max limit exceeded Bit 21 CREEP A Alert current Creep Alert on Phase A Bit 22 CREEP B Alert current Creep Alert on Phase B Bit 23 FAULT Line Neutral reversed Bit 24 25 Reserved 0 Bit 26 CE_READY CE is now ready after power up Bit 27 31 Reserved 0 Vrms A 1 000 Vrms RMS Voltage Phase A Watts A 1 1000 Watt Power Phase A Wh A Export 4 1000 WattHr Energy Phase A Export Wh A Import 4 1000 WattHr Energy Phase A Import Irms A 1 1000 Arms RMS Current measurement Phase A VARA 1 1000 Watt Reactive Power measurement Phase A VAA 2C 1 1000 Watt Signed Apparent power measurement Phase A Alarm Status
22. B 1 4 Data The data packet consists of either the request data sent from the master to the device or the response data packet sent from the device to the master If a data byte is it is replaced by OxDBDC If it is OxDB it is replaced with OxDBDD The conversion is done before transmission See sample code below B 1 5 CRC 8 An 8 bit cyclic redundancy check CRC 8 calculated over the Data packet is embedded in the packet The CRC 8 represented by the polynomial C x x x x 1 After the computation of CRC Data packet and CRC 8 is encoded with the special SLIP character codes described in Section 2 2 Start Device Address Data CRC 8 End COQ XX Co 1Byte 1Byte 1Byte Offset 0 Offset 1 Offset n 3 SLIP character codes Code snippet for CRC 8 calculation Winks t creg uints t incre uinte t inData ULNES t ere inCre inData for 1S 07 LS Oe at if ore amp 0x80 0 cre lt 1 cre 0x07 else cre lt lt 1 i return crc B 2 Packet Types The master shall broadcast a command packet addressed to a specific device And the device shall reply by transmitting an ACK NACK packet followed by a response packet The different packet types can be classified as e ACK NACK Packet Handshake mechanism Command Packet Operational phase e Response Packet Reply to the command After sending the com
23. Commands To modify the contents of an individual MPU Input Register append the character and the value to a read command gt Jaddr n lt CR gt The JU command is used for updating default values of the CE input registers permanently in the flash Before issuing the JU command CE must first be turned off by the disable CE command gt CE0 lt CR gt gt U lt CR gt gt CE1 lt CR gt A 5 Calibration Commands There are often two types of built in calibration routines The first type provides complete calibration The second group called atomic calibration commands provides calibration for individual portions of the IC There is often one calibration coefficient for each voltage input and one for each current input A 5 1 Complete Calibration Command The CAL command provides single command calibration To use this command a precision voltage source and a precision current source are required Enter the following gt CAL lt CR gt The response is TCal OK VCal OK ICal 0 OK gt The device calibrates the temperature and saves to flash calibrates the voltage and saves them to flash and finally calibrates the current and saves to flash Rev 2 29 78M6613 Split Phase Firmware Description Document UG_6613_090 A 5 2 Atomic Calibration Commands The atomic calibration commands provide individual calibration of voltage current power and temperature A sequence of these commands results in a fully calibrate
24. HASE_ADJ_IA lt 16384 16384 lt PHASE_ADJ_IB lt 16384 Kh VMAX A IMAX A WRATE X 1 6826E 01 WattSec VMAX 4 2551E 07 Vpk VMAX A IMAX A 1 8541E 10 Watt VMAX A IMAX B 1 8541E 10 Watt VMAX A IMAX A 1 8541E 10 Watt Default 16384 16384 16384 16384 5061 20732 168225 Comment Gain constant for Phase A input Gain constant for Phase B input Gain constant for Phase A input Gain constant for Phase B input Line Out A Phase adjustment 15 PHASE_ADJ_IA 2 degrees Line Out B Phase adjustment 15 PHASE_ADJ_IB 2 degrees Bit 15 8 SAG_CNT Number of consecutive voltage samples below SAG Threshold to assert SAG alarm Bit 7 Reserved 1 Bit 6 1 detect SAG on V1 B Bit 5 1 detect SAG on VO A Bit 2 1 Floating Reference 0 Fixed Reference Bit 1 0 Reserved 0 Controls the number of pulses that are generated per measured Wh and VARh measurements Reserved The voltage threshold for SAG warnings 80vRMS when VMAX 471 5v VO must be above this to prevent SAG alarm Compensation added to the Watt calculation for Phase A Used for compensation at low current levels Keep below 10000d Compensation added to the Watt calculation for Phase B Used for compensation at low current levels Keep below 10000d Compensation added to the VAR calculation for Phase A Used for compensation at low current levels Keep below 10000d
25. O VASSIGIIMGINS Oe eh i a a ke ai le Go 6 Table 22 Simulation RESUS 4 5 5 05 aie ek danas dened 8 Table 3 Measurement Equations 8 9 4 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document 1 Introduction This document describes a firmware build specifically designed for the 78M6613 with a split phase measurement interface Split Phase M API Library and UART host interface Application Layer This firmware build is used as the base for all development and testing of the Split Phase M API Library The firmware provides simple methods for calibration alarm monitoring and access to the following measurement data over a low baud rate serial UART interface e Voltage rms Line1 Line2 e Current Line1 Line2 e Active Power Line1 Line2 aggregate e Apparent Power Line1 Line2 aggregate e Reactive Power Line1 Line2 aggregate e Power Factor Line1 Line2 e Energy Line 1 Line 2 Line Frequency 1 1 Terminology The following terminology is used throughout this document CLI Command Line Interface Application with ASCII based UART protocol e SLIP Serial Line Interface Protocol Application with binary UART protocol e CREEP Threshold value where measurement outputs are squelched to zero
26. acket Names EEA Packet Description Offset Field CmdRWStatus Variable 2 bytes Each bit represents status of the register read write operation Bit 0 Success Bit 1 Failure LSB represents first read write register operation in the command The maximum number of register addresses for both read write operations in a command is limited to 8 CmdRWStatus is not applicable to Device Information command CmdReturnCode variable 1 byte Successful operation Invalid Command Type K Incorrect Data Length Read only register f Reserved register j Invalid register address CmdResponseData variable n bytes Single Multiple Read lt data1 gt lt data2 gt lt data n gt Single Multiple Write lt none gt Contiguous Block Read lt data1 gt lt data2 gt lt data n gt Contiguous Block Write lt none gt Device Information ASCII string depicting the firmware version and the product number CLI Toggle Command lt none gt Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document Example 1 Read Command Packet In this example the master sends a command request to read MPU register address 0x0200 of the 661x device with device address 0x07 The device accepts the read command by sending out an ACK followed by the register data i e Ox000731CC The next example is when the command packet attempts to read an invalid register address For a successful transaction gt 00 07 10 02 00 8
27. an ACK followed by the response packet consisting of the device information string gt 00 07 30 90 CO Master sends the device information command lt CO 07 00 00 CO Device sends an ACK lt CO 07 00 00 00 56 33 2E 58 30 20 32 35 30 6D 73 20 46 30 Device sends response packet consisting of the string 20 4D 41 58 49 4D 20 37 38 4D 36 36 31 38 20 46 3 250ms FO MAXIM 78M6618 Feb 09 2011 65 62 20 30 39 20 32 30 31 31 49 CO Example 6 CLI Toggle Command Packet In this example the master sends the CLI toggle command and the device exits the multi point serial interface mode to CLI mode The device can toggle back to multi point serial interface mode via the Q command at the CLI prompt gt CO 07 00 00 CO Master sends the device information command CO 07 00 00 CO Device sends an ACK lt CO 07 00 00 00 00 CO II Successful operation 38 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document B 3 Command Registers The following command registers are unique to the Multi point Serial Interface MPU Parameter Location LSB hex Default Comment This register is used for calibration command Firmware s receipt byte as well as for Calibration status Firmware s transmission byte Calibration Command Bit 1 set performs calibration Calibration Status Bit 0 clear Calibration OK Bit 1 set Calibration Failed BITO Temperature Cal Status
28. d MPU register address gt 00 07 20 02 00 03 xx CO Master sends block read command request lt C0 07 00 00 CO Device sends ACK CO 07 00 00 00 00 09 27 DB DC 00 07 31 CC 00 00 75 30 DO CO Device sends out register data 0x000731CC 0x00007530 Master sends block read command to read twenty six 0x1A contiguous registers starting from address 0x0200 exceeding the maximum limit of sixteen registers read gt CO 07 20 02 00 1A 5E CO Master sends block read command request CO 07 00 00 CO Device sends ACK lt CO 07 00 00 81 8E CO Device sends out an error code of 0x81 Rev 2 37 78M6613 Split Phase Firmware Description Document UG_6613_090 Example 4 Contiguous Block Write Command Packet In this example the master sends a command request to write to three contiguous MPU registers from starting address 0x0200 of the 661x device with device address 0x07 The device accepts the block write command by sending out an ACK followed by the register data gt CO 21 02 00 00 09 27 DB DC 00 07 31 CC 00 00 75 30 6A CO Master sends block write command request CO 07 00 00 CO Device sends an ACK lt CO 07 00 00 00 00 CO Device sends out command response packet after successful write Example 5 Device Information Command Packet In this example the master sends the device information command The device accepts the command by sending out
29. d attached The FW sets line frequency voltage and current to zero readings when the voltage falls below a programmable threshold 2 4 6 Limit Registers Alarms The Limit registers set limits on result values and causes Status Register bits to be set when a limit is exceeded Limit registers use the same scaling applied to results and as such are user definable The user selectable alarms are the following e Min Max Temperature Alarm e Min Max Frequency Alarm e SAG Voltage Alarm Under voltage V1 input Over voltage V1 input e Over Current Line 1 and Line 2 e Power Factor Line 1 and Line 2 e Creep Alert low current alarm Line 1 and Line 2 16 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document 3 Split Phase M API Register Map This section contains the register map for the Split Phase M API Library All the registers are in a 4 byte format and are divided in three sections e Output Registers for reading metrology results system status etc e Input Registers for entering commands coefficients etc e CE I O Registers for Compute Engine settings and status 3 1 Output Registers Address Data ae Output hex Resolution Type Description Temperature Line Frequency 0 01 Hz Line Frequency Bit 0 Minimum Temperature Alarm Bit 1 Maximum Temperature Alarm Bit 2 Minimum Frequency Alarm Bit 3 Maximum Frequency Alarm Bit 4 SAG Voltage
30. d unit The following table provides a summary of the atomic calibration commands CLxx Atomic Calibration Commands Description Allows the user to Calibrate individual sections of the IC Usage CLV Calibrates voltage only CLI1 Calibrate current only CLT Calibrate temperature only CLV Command An example of an atomic calibration command would be to calibrate voltage with the CLV command The CLV command calibrates voltage to the target value and tolerance and saves the coefficients to flash The CLV command example is given below gt CLV lt CR gt The response is VCal OK gt CLI Command The user can then calibrate the current using the CLI command The CLI1 command calibrates the current channel 1 to the target value and tolerance and saves the coefficients to flash The CLI1 command example is given below gt CLI1 lt CR gt The response is ICal 0 OK gt CLT Command The CLT command is used for the temperature calibration With this command the CE register holding current temperature are read and entered into MPU register CO and the contents are then saved to flash The CLT command example is given below gt CLT lt CR gt The response is TCal OK gt 30 Rev 2 6613 090 78M6613 Split Phase Firmware Description Document Appendix B SLIP Interface This appendix describes a multi point serial interface protocol built on top of a Serial Line Interface Pr
31. elch or CREEP Thresholds e Alarm Thresholds and Mask Settings Updating Input Registers into Flash The default values of all input registers can be updated by the user at run time A Flash update routine is provided that saves the current value of any input register as the default 2 4 2 Calibration As with any measurement system there are also multiple sets of compensation coefficients or parameters that are used to compensate for system inaccuracies Input registers for all coefficients can be manually modified and saved to Flash Alternatively high level calibration routines can be invoked These routines automatically determine the coefficients for common parameters and save them to Flash memory The different types of compensation parameters include e Voltage Sensing Gain adjustment e Current Sensing Gain and offset QUANT adjustment Phase Voltage to current phase offset compensation introduced by transformer or filters in sense circuits e Temperature Offset for junction temperature at room temp e Temperature Coefficients for temperature curve e WATT and VAR offset QUANT adjustment The calibration routines compensate for sensors and system inaccuracy The new coefficients computed during calibration are stored in the on chip flash In order to perform a calibration an external voltage source and external current source or load is required The calibration routines have a target voltage and curren
32. es ACK NACK packet sent from the device Packet Packet Names Field Value Field Description Offset 2 ACK NACK XX 1 byte ACK 0x00 NACK 0x80 NACK for the checksum error Command Packet The command packet is sent from the master to the device Upon reception of the command packet the device sends an ACK packet to the master to inform the master that it has successfully received the command and is working on it After processing of the command the device responds to the master with the response packet The operational phase comprises of the register read write and device information command The 661x device register address is two bytes wide and register data is four bytes wide Refer to 661x Firmware Description Document FDD for the register details The following table shows the offset of the MPU CE and IO RAM registers Register Offset MPU 0x0000 CE 0x1000 RAM 0x2000 For example an offset of 0x1000 is added to the CE register addresses defined in the Firmware Description Document Rev 2 33 78M6613 Split Phase Firmware Description Document UG_6613_090 The read write command is limited to sixteen registers read write operation due to the receive and transmit buffer size limitation of the device The device may take up to a few seconds to complete the calibration command a MPU register see FDD for details Therefore the master shall allow the device enough time to p
33. for the delay between samples caused by the multiplexing scheme e Monitoring of the input signal frequency for frequency and phase information e Monitoring of the input signal amplitude for sag detection e Scaling of the processed samples based on calibration coefficients At the end of each accumulation interval these atomic measurement parameters are provided to the MPU for post processing Alternate multiplexer cycles also gather measurements of the IC s junction temperature for additional compensation in the MPU Post processing functions handled by the MPU at the end of every accumulation interval include e Compensation for environmental variables e Calculation of apparent power power factor phase angle and line frequency e Accumulation of energy data e Comparing of measurement outputs to configurable alarm thresholds e Scaling and formatting of output measurement data e Updating of all output registers data and alarm status 10 Rev 2 6613 090 78M6613 Split Phase Firmware Description Document Figure 3 shows the data processing flow
34. ice The commands are similar to the MPU access except that the host requests access to information from the CE data space using the CE data access command which is a right bracket gt Single Register CE Access An example of a command requesting the contents located at CE address 0x28 in decimal is as follows gt 28 lt CR gt An example of a command requesting the contents located at address 0x28 in hex is as follows gt 28 lt CR gt Consecutive CE Reads The host can request information form consecutive addresses by adding additional for decimal or additional for hex An example of requests for the contents in decimal of ten consecutive addresses starting with 0x28 would be An example of requests for the contents in hex of ten consecutive addresses starting with 0x28 would be gt 28 lt CR gt Note The number of characters per line is limited to no more than 60 28 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document A 4 Write Commands A 4 1 MPU Register Write Commands To modify the contents of an individual MPU Input Register append the character and the value to a read command gt addr n lt CR gt The U command is used for updating default values of the MPU input registers permanently in the flash Before issuing the U command CE must first be turned off by the disable CE command gt CE0 lt CR gt gt U lt CR gt gt CE1 lt CR gt 4 2 CE Register Write
35. mand packet the master must wait for a response from the device before sending out the next command packet In the case of a non responsive device a time out shall be activated by the master before re sending the command packet to the device 32 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document ACK NACK Packet Every time a request packet is sent from the master to the device the master should expect an ACK NACK packet back from the device ACK is to acknowledge the valid address and data integrity of the request packet NACK acknowledges the data integrity error like CRC error Only device with valid address should respond with a NACK packet to avoid message collision on the bus After sending out the NACK packet the device considers the transaction to be complete The device will be in receive mode ready to receive a new command packet from the master If NACK is received from the device the master shall be in transmit mode and resend the command The number of retries shall be at the discretion of the master The device shall consider each retry attempt as a new command request from the master Start Device Address Data CRC8 End XX responding COQ ACK NACK XX device address 1Byte 1Byte 1 Byte 1 Byte 1 Byte Offset 0 Offset 1 Offset 2 Offset 3 Offset 4 The table below describes in detail each field of the ACK NACK packet and its available valu
36. maxim integrated 78M6613 Split Phase Firmware Description Document December 2011 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document UG_6613_090 maxim integrated Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated 160 Rio Robles San Jose CA 95134 USA 1 408 601 1000 2011 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products Inc UG_6613_090 78M6613 Split Phase Firmware Description Document Table of Contents 1 6 5 5 Fe REE aLe E 2 bers ee re eer cer 5 1 2 Hardware ASsiQnm 6ntS orarin ri rari r TET E OIA E E E EE eee aa 6 1 2 1 Fixed Reference Sensor
37. mware 1 2 1 Fixed Reference Sensor Configuration In conventional configurations the AC neutral is connected to V3P3A which is the supply input of the analog circuitry and the reference potential for the A D Converter 78M6613 V3P LOAD Neutral Figure 1 Simplified Connection Diagram with Fixed Reference 6 Rev 2 6613 090 78M6613 Split Phase Firmware Description Document 1 2 2 Floating Reference Sensor Configuration In order to maintain a high impedance between the supply Line1 Line2 Neutral and the measurement subsystem a floating reference configuration is also available Vref Va 78M6613 2 AO A1 A3 V3P3_REF LOAD Neutral Figure 2 Simplified Connection Diagram with Floating Reference A virtual center or reference V3P3_REF has been created using a voltage divider R1 and R2 The V3P3A AD C reference potential is connected to the virtual center Two voltages are then acquired Line 1 and Neutral these measurements are referred to the virtual ground V3P3_REF For clarity Line 1 measurement is identified as Va and Neutral measurement is identified as Vref The equations to reconstruct the values of V1 and V2 are the following V1 Va Vref 1 V2 Va V a Vref O i ym Rev 2 7 78M6613 Split Phase Firmware Description Document UG_6613_090 Table 2 shows the results obtained
38. nnels TCO or TCOO Relay OFF for both channels Rev 2 15 78M6613 Split Phase Firmware Description Document UG_6613_090 2 4 4 Sag Detection Settings The 78M6613 Split Phase Firmware includes the sag detection function SAG is defined as a momentary or permanent decrease of line voltage amplitude The sag detection is often used to monitor the quality of the power line or utilize the sag alarm to notify external devices for example a host microprocessor of a pending power down The external device can then enter a power down mode for example saving data or recording the event before a power outage Figure 5 shows a typical sag event SAG_THRESHOLD l l l l l l l l l j l SAG_COUNTER l l Figure 5 Sag Event The sag detection is base on a voltage threshold SAG_THR and a counter value time The counter is updated at the ADC sample rate and starts whenever the voltage is below the SAG_THR value The alarm bit and alarm pin are set if the counter exceeds the predefined SAG_THR count SAG_CNT value SAG detection is enabled for VA or VB or both by setting bit 5 VA and or bit 6 VB to logic high 1 in the CE s CESTATUS register 0x100E 2 4 5 Creep Thresholds The 78M6613 includes a no load detection feature that eliminates what is commonly referred to as meter creep Meter creep is defined as power or energy that is read by the system when there is no loa
39. ns 2 2 Sensor Hardware Configuration A few parameters specific to the hardware implementation may require one time configuration The firmware allows for parameters to be modified by the user at run time and saved to Flash These hardware specific parameters include VMAX and IMAX registers define the upper and lower values of the ADC range These parameters allow the scaling of raw data to real world values VMAX and IMAX should be set to a value that reflects a peak of near 250mV at the selected voltage ADC input Values too far from this setting will cause undesired effects When changing a current sensor its associated IMAX value will need to be re evaluated The CESTATE register selects either the Fixed or Floating reference sensor configuration Refer to Section 1 2 for more information on sensor interface configurations 2 3 AC Measurement and Monitoring The integrated AFE and CE function as a data acquisition system controlled by the MPU The low voltage analog input signals are sampled and stored in CE DRAM where they are processed by the CE The CE a dedicated 32 bit signal processor performs the computations necessary to all the measurements The CE calculations and processes include e Multiplication of each current sample with its associated voltage sample to obtain the energy per sample when multiplied with the constant sample time Frequency insensitive delay cancellation on all channels to compensate
40. on procedures are dependent on production test setup they will be described in a separate document Rev 2 13 78M6613 Split Phase Firmware Description Document UG_6613_090 2 4 3 Relay Control Relay control is supported by the TC command The TC command can be used to open 0 or close 1 circuit of all 2 channels All necessary Sequence time between each channel Energized for closing circuit and De Energized for opening circuit delay times are set up and used by the library using the following default values Energized delay time Oms De Energized delay time Oms Ride ter LSB Default Comment Example Bit 1 Relay Polarity 0 Normal Polarity Relay 1 Inverted Polarity Configuration Bit 0 Relay Type 0 non latched 1 latched Parameter given in relay If the user desires 8 ms of Energize manufacturer s data sheet is delay then enter the Delay entered here The amount of following delay will be 1 ms plus the value gt AE 0 007 lt CR gt entered in AE Parameter given in relay If the user desires 8 ms of De Energize manufacturer s data sheet is delay then enter the Delay entered here The amount of following delay will be 1 ms plus the value entered in AF Bit 1 Relay for Outlet 2 0 DIO19 0 1 DIO19 1 Control Relay FO _ 0 Bit 0 Relay for Outlet 1 0 DIO7 0 1 DIO7 1 Note AC 1 1 inverts the bits above gt AF 0 007 lt CR gt Control Relay 14 Rev 2
41. on Voltage Calibration Current Calibration Phase Tolerance on Voltage Tolerance on Current Average Count for Voltage Average Count for Current Max Iteration for Voltage Max Iteration for Current Tolerance on Watts Location hex C4 C6 C7 LSB 1 1000 Arms 1 000 Vrms 0 1 1 000 Vrms 1 1000 Arms Default 100 120000 1000 10 10 CA 1 1000 Watt 10 Comment This register is used for calibration Status Calibration Status Bit 0 clear Calibration Bit 1 set Calibration Failed BITO Temperature Cal Status BIT1 Voltage CAL A Status BIT2 Voltage CAL B Status BIT3 Phase CAL A Status BIT4 Phase CAL B Status 5 Current CAL A Status BIT6 Current CAL B Status BIT7 Watt CAL A Status 8 Watt Cal B Status BIT9 29 Reserved BIT30 UPDATE_FLASH_MPU Status BIT31 UPDATE_FLASH_CE Status Measured value to fall within this set tolerance plus minus the target value Calibration Phase entry for the calibration to be complete Reserved Target line voltage rms used for calibration on both Phase A and Phase B Target load current rms used for calibration on both Phase A and Phase B Target Phase voltage to current Normally set to zero For both Phase A and Phase B Measured value to fall within this set tolerance of the target value Calibration Voltage entry for the calibration
42. otocol SLIP layer It defines a payload format suitable for communicating with one or more 78M66xx energy measurement devices on a single serial bus B 1 Packet Format and Definition The SLIP packet is transmitted in a block format The useful data is encapsulated by two control bytes These control bytes are necessary to determine when the block starts and ends It is recommended that the host allows the firmware sufficient time to process each byte of the packet by setting a 5ms inter character delay B 1 1 Packet Format Start Device Address Data CRC 8 End COQ XX XX XXn XX 1Byte 1Byte Variable nBytes 1Byte 1Byte Offset 0 Offset 1 Offset 2 Offset n 2 Offset n 3 B 1 2 Start and End A SLIP packet always starts and ends with an END character SLIP has 4 special character codes define END Decimal 192 indicates start or end of a packet define ESC 0xDB Decimal 219 indicates byte stuffing define ESC_END 0xDC Decimal 220 ESC ESC_END means END data byte define ESC_ESC 0xDD Decimal 221 ESC ESC_ESC means ESC data byte Within a SLIP packet a data byte having a value of END 0xC0 will be stuffed with ESC OxDB and immediately followed by 8 ESC_END 0xDC character for example 0xCO data byte will appear as OxDBDC Similarly a data byte having a value of ESC 0xDB will be immediately followed by an ESC_ESC 0xDD character for
43. return The contents of the addresses that would be requested by the host are contained in Register Map A 3 1 Individual Address Read The host can request the information in hex or decimal format In an address read command the character requests the information to be returned in hex format While the character requests information to be returned in decimal When requesting information in decimal the data is preceded by a ora An example of a command requesting the measured output located at address 0x28 in decimal is as follows gt 282 lt CR gt An example of a command requesting the measured output located at address 0x28 in hex is as follows gt 28 lt CR gt A 3 2 Consecutive Read The host can request information from consecutive addresses by adding additional for decimal or additional for hex An example of requests for the contents in decimal of ten consecutive addresses starting with 0x32 is An example of requests for the contents in hex of ten consecutive addresses starting with 0x32 would be gt 32 lt CR gt Note The number of characters per line is limited to no more than 60 A 3 3 Block Reads The block read command can also be used to read consecutive registers For decimal format gt startaddress endaddress For hexadecimal format gt startaddress endaddress The following block read command requests a block of measurement information in decimal format gt 20 3D lt CR gt
44. rocess a command and wait for the device response packet before timing out or sending a new command to the device During Operational phase after receiving the valid start character and device address the device shall start a timer of 250ms If this timer expires before receiving the end character the receive buffer of the device is flushed and the device is ready to receive the new command packet If the end character is received prior to expiration of this timer the timer will be stopped and reset The communication flow is depicted as follows Master Response Packet Start Device Address Data CRC 8 End CO XX XX XXn XX Co 1Byte Variable 1Byte n Bytes 1 Byte 1Byte Offset 0 Offset 1 Offset 2 Offset n 3 Offset n 4 Command Type Command Request Data XX XX 1Byte n Bytes Offset 2 Offset 3 34 Rev 2 6613 090 78M6613 Split Phase Firmware Description Document The following table describes in detail each field name and its available values Command Packet Sent from the master to the device Packe Packet Command Packet Description t Names Field Value Offset CmdType Variable 1 byte Read single or multiple 0x10 Write single or multiple 0x11 Contiguous Block Read 0x20 Contiguous Block Write 0x21 Device Information 0x30 CLI Toggle Cmd 0x00 3 CmdRequest Variable n bytes Single Multiple Read Data lt Regi
45. ster address gt lt Register address2 gt Single Multiple Write lt Register address1 gt lt data1 gt lt Register address2 gt lt data2 gt Contiguous Block Read lt Beginning block read register address lt number of registers to read gt Contiguous Block Write lt Beginning block write register address gt lt data1 gt lt data2 gt lt data3 gt Device Information lt none gt CLI Toggle Command lt none gt The following table describes the field size of each data packet Data Packet Field Size lt Register address gt 2 bytes lt Data gt 4 bytes lt Beginning block read write register address gt 2 bytes lt number of registers to read gt 1 byte Rev 2 35 78M6613 Split Phase Firmware Description Document UG_6613_090 Response Packet The Response packet is sent from the device to the master in reply to the Command packet Start Device Address Data CRC 8 End co responding XX XXn co device address 1Byte 1Byte Variable nBytes 1 Byte 1 Byte Offset 0 Offset 1 Offset 2 Offset n 5 Offset n 6 Cmd Read Write Status Cmd Return Code Command Response Data XX XX XX 2 Bytes 1Byte n Bytes Offset 2 Offset 4 Offset 5 only for read operation The table below describes in detail each field name and its available values Response Packet Sent from the Device Packet P
46. t for both phases to match The target calibration voltage and current values are specified in the registers Voltage Line1 and Line2 and OxC2 Current Line1 and Line2 Important factor for accurate calibration is to define the tolerance for example the coefficients are modified until the measured current or voltage is within the plus minus range of the specified tolerance from the target value The voltage calibration tolerance register is at address 0xC4 while the current tolerance is specified in register OxC5 Other settings for calibration are average counts and maximum number of iterations The average counts represent the number of voltage measurement register OxC6 or current measurements register 7 averaged and used to be compared against the target value The number of iterations sets the number of time the routine runs in order to bring the value of either voltage or current reading within the specified tolerance from the target NOTE All calibration should be done in the Fixed Reference Sensor Configuration 12 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document Figure 4 shows a split phase calibration test setup HOST CONNECTION 78M6613 PRECISION PRECISION AC VOLTAGE Neutral AC LOAD SOURCE CT2 Figure 4 Split Phase Calibration Test Setup The source and AC load should provide a stable reference during calibration Since the calibrati
47. this threshold will set an alarm bit 11 of the Alarm Status Register Only available if register OxF2 bit 2 is set to 1 Wideband Power Factor Positive Threshold A positive wideband power factor less than this threshold will set an alarm bit 12 of the Alarm Status Register Unused Unused Alarm mask for bits in the Alarm Status register A 0 masks the alarm from the register bit Alarm mask for an alarm pin if DIO is configured A 0 masks the alarm no report Rev 2 21 78M6613 Split Phase Firmware Description Document UG_6613_090 3 3 Parameters The following table lists the CE parameters for the firmware With the exception of CESTATE and QUANT registers the user does not typically need to alter any of these input registers as they are automatically set by Calibration Commands CE Parameter CAL CAL CAL VA CAL VB PHASE_ADJ_IA PHASE_ADJ_IB CESTATE WRATE Reserved SAG Threshold QUANTA QUANTB QUANT VAR A Locatio n hex 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 LSB 16384 is the default and is a gain of 1 32767 is max giving a gain of 2 16384 is the default and is a gain of 1 32767 is max giving a gain of 2 16384 is the default and is a gain of 1 32767 is max giving a gain of 2 16384 is the default and is a gain of 1 32767 is max giving a gain of 2 16384 lt P
48. to be complete Measured value to fall within this set tolerance plus minus the target value Calibration Current entry for the calibration to be complete Number of voltage measurements taken and averaged to be compared to the target value Calibration Voltage entry Number of current measurements taken and averaged to be compared to the target value Calibration Current entry Number of attempts to reach the target value Calibration Voltage entry within the programmed tolerance Number of attempts to reach the target value Calibration Current entry within the programmed tolerance Measured value to fall within this set plus minus tolerance of the target Watt value for the calibration to be complete 20 Rev 2 UG_6613_090 78M6613 Split Phase Firmware Description Document MPU Parameter Average Count for Watts Max Iteration for Watts Reserved Calibration Temperature Calibration Watts Temp Alarm Min Threshold Temp Alarm Max Threshold Frequency Minimum Threshold Frequency Maximum Threshold SAG Voltage Alarm Threshold Min Voltage Alarm Threshold Peak Voltage Alarm Threshold Unused PFA_ Neg Threshold PFA_ Pos Threshold Unused Unused Alarm Mask_Status Alarm Mask_Alarm Location hex W CC Q Oo m g N X 5 D7 D8 DC DE DF E0 E5 E6 m N LSB 0 1 C 1 1000 Watt 0 1

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