User Manual - Trenz Electronic
Contents
1. ve Trenz Electronic GmbH S partan 3E FPGA e U n infoOtrenz electronic de o electronic Wwww trenz electronic de Industrial Micromodule en Rev 1 19 as of 2011 10 04 User Manual Features Industrial temperature grade avail able on request m High density plug in Xilinx Spartan m Low cost versatile and ruggedized 3E module design m USB 2 0 interface with high speed 480 Mbit s data rate m Large SPI flash for configuration and Specifications user storage accessible via USB or SPI m FPGA Xilinx Spartan 3E XC3S500E connector XC3S1600E m Large DDR SDRAM USB controller Cypress EZ USB FX2 m FPGA configuration is implemented via USB 2 0 microcontroller CY7C68013A JTAG SPI Flash or USB S6LFX m 3 on board high power high effi Non volatile memory 16 MBit 64 ciency switch mode DC DC convert Mbit SPI Flash for FPGA configuration ers 1 A for each voltage rail 1 2 V and user data 2 5 V 3 3 V m Volatile memory 512 Mbit x 16 DDR m Power supply via USB or B2B carrier SDRAM with up to 666 Mbyte s board Flexible expansion via high density shockproof B2B board to board connectors Most I O s on the B2B connectors are routed as LVDS pairs Up to 110 FPGA user I Os Supply voltage range 4 0 V 5 5 V 1 push button 1 LED Small size only 40 5 mm x 47 5 mm m Evenly spread supply pins for good signal integrity i ie eire Pe eg sec cee ee ty Figure 2 TEO300 top view Figure 1 TEO300 bottom v2. m zip the 3 files change the zip file extension to fwu upload the file as explained in the next section Micromodule Configuration Trenz Electronic GmbH User Manual Micromodule Configuration The micromodule can now be programmed with its dedicated firmware upload tool Turn S1 S2 S3 and S4 on Open the ded icated firmware upgrade tool USB Firm ware Upgrade Tool double click the US BFirmwareUpgradeTool exe file in the USBFWUTool folder USB Firmware Upgrade Tool Device USB Device File name ar i Yersion 7 6 Press the button corresponding to the File name field and select for instance the sample firmware upload file TEO300_v1012 fwu in the USBFWUTOONFWUS folder Offnen Suchen in FwUs SS w ej 2 i Zuletzt verwendete D E Desktop Eigene Dateien g Arbeitsplatz m Abbrechen TEO300_v0812 fau v Dateityp Fw Update Files fwu vw D Netzwerkumgeb Dateiname un USB Firmware Upgrade Tool Device USB Device File name C TE0300 U5BFWUToollFWUs1TE0300_v1012 Upload Yersion 7 6 18 Spartan 3E FPGA Industrial Micromodule Press the Upload button to upload the micromodule firmware and check the FPGA uploading progress bar 4 USB Firmware Upgrade Tool USB Device Ed A FPGA uploading 22 Yersion 2 6 After successful completion of the firmware upload
3. 1 11 2009 07 23 FDR clarified changes LED section 1 12 2009 08 24 FDR added FPGA signal details for main user signals 1 13 2009 09 01 FDR improved On board Memories chapter 1 14 2009 09 03 FDR improved clock memory and con figuration chapters 1 14 2009 10 23 FDR PREPARE_FW de scription removed 1 15 2010 05 14 FDR Added reference design summaries 1 16 2010 01 20 FDR Fixed JTAG image 1 17 2010 01 21 FDR Fixed pin out de scription for pin 57 B0 LO8 N Add note on offset hole connectors 1 18 2011 03 25 FDR Updated Hirose connectors part numbers 1 19 2011 10 04 AIK Updated diagrams and ToC Table 17 revision history Trenz Electronic GmbH User Manual Legal Notices Document Warranty The material contained in this document is provided as is and is subject to being changed at any time without notice Trenz Electronic does not warrant the accuracy and completeness of the materials in this document Further to the maximum ex tent permitted by applicable law Trenz Electronic disclaims all warranties either express or implied with regard to this doc ument and any information contained herein including but not limited to the im plied warranties of merchantability fitness for a particular purpose or non infringe ment of intellectual property Trenz Elec tronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing use or
4. Appendix The following tables reports pin out in formation of B2B board to board recept acle connectors J4 and J5 respectively The reference design summaries report the resources needed by the reference design on TEO300 modules of different dimen sions 1200 and 1600 versions Trenz Electronic GmbH User Manual 27 FPGA ba dir FPGA FPGA B2B name nk name pin name 1 VccIO VccO 0 I I O VccO VccIO 2 3 VccIO VccO 0 I I O VccO VccIO 4 5 B3 LO1 P Cl IO LOIP 3 IO 3 3V Y Y 3 3V IO 3 IO L07P G6 B3 L07 P 6 7 B3 LO1 N C2 IO LOIN 3 IO 3 3V Y Y 3 3V IO 3 IO LO N G5 B3 L07 N 8 9 B3 L02 P Di IO LO2P 3 IO 3 3V Y Y 3 3V IO 3 IO LO3N Ei B3_L03_N 10 11 B3 L02 N D2 IEEE 3 IO 3 3V Y Y 3 3V IO 3 IO LO3P E2 B3 LO3P 12 13 GND GND 14 15 BO IO C3 C3 IO L25P 0 IO VccIO N Y VccIO IO O IO L19 P F7 BO L19 P 16 17 BO L24 N B4 IO L24 N O IO VccIO Y Y VccIO IO O Gee E7 BO LION 18 19 BO L24 P A4 10 L24P 0 IO VccIO Y Y VccIO IO O IO L21N E6 BO L21 N 20 21 BO IO C4 C4 IO O IO VccIO N Y VccIO IO O IO L21P D6 BO_L21 P 22 23 GND GND 24 IO_L23N IO L18N 25 BO L23 N D5 VREF 0 IO VccIO Y Y VccIO IO 0 VREF D7 BO LI8 N 26 27 BO L23 P C5 IO L23P 0 IO VccIO Y Y VccIO IO O IO_L18P C7 BO_L18 P 28 29 BO L20 P B6 IO L20P O IO VccIO Y Y VccIO IO O IO L17N F8 BO_L17 N 30 31 BO L20 N A6 IO L20N 0 IO VccIO Y Y VccIO IO O IO L17P ES BO
5. EDK for some reference designs m Interface USB host m JTAG SPI USB cable with flying leads EZ USB FX2 Microcontroller Firmware If the EEPROM has never been pro grammed before virgin board S1 can be switched to EEPROM The USB microcon troller will detect an empty EEPROM and will provide its default vendor ID and device ID to the USB host DIP on left off right switch S1 EEPROM S2 Run S3 X X S4 X X 11 Spartan 3E FPGA Industrial Micromodule If the EEPROM has been programmed be fore EEPROM not empty S1 must be switched to Off The USB microcontroller will detect a missing EEPROM and will provide its default vendor ID and device ID to the USB host DIP on left off right switch S3 X X SA X X Generic USB Microcontroller Driver installation If the USB microcontroller Cypress EZ ESB FX2 driver is not installed on the host computer then the easiest way to do it is the following m disconnect the micromodule or leave the micromodule unconnected configure the micromodule such that the USB microcontroller will provide its default vendor ID and device ID to the USB host i e S1 OFF see para graph EZ USB FX2 Microcontroller Firmware connect the micromodule to the host computer through the USB interface m wait until the operating system detects new hardware and starts the hardware assistant m if S1 is not already
6. Get Strings Download j vend Reg Req 0x00 value 0x0000 Index 00000 Length 0 Dir 0 OUT y Hex Bytes co B4 04 81 00 01 00 Pipe Length 128 Packet Size Packets cT Pipe y Length 64 Hex Bytes 5 v Reset Pipe Abort Pipe File Trans Pipe v Set IFace Interface jo AltSetting jo S EEPROM button refers to the small EE PROM 256 bytes whereas the Lg EEP ROM refers to the large EEPROM 64 KB Press the Lg EEPROM button select the USB iic file and press the Open button to start writing to EEPROM 13 Spartan 3E FPGA Industrial Micromodule Large 512 64K byte EEPROM Download Suchen in ea TEO300 v fh rf Er 2 B driver O CyConsole Zuletzt verwendete D S Desktop Eigene Dateien Arbeitsplatz fusb ic ioc EEPROM Files iic v I Schreibgesch tzt ffnen Abbrechen D ateiname Netzwerkumgeb Dateityp un Upgrade progress is displayed in status window and is completed when Download Successful text is displayed 7 EZ USB Interface Device juss Device D cea SE mon EEPROM Select Mon Packet Size Packets Bulk pe Length Hex Bytes 5 oi PARE we 4 _ Set lFace Interface AtSetting y BB 01 OC ES 82 29 FS 82 ES 83 3A FS 83 EO 22 50 06 ES 25 82 F8 E6 22 BB FE 06 ES 25 82 F8 EZ 22 ES 82 29 FS 82 ES 83 3A FS 83 E4 93 22 FS BB Ol OD ES 82 29 FS 82 ES 83 3A
7. O sec done BATCH CMD set ttribute position 1 attr packageName value Cancel a lt Output Error Warning No Cable Connection After successful programming you should In the Device Programming Properties read the message Program Succeeded window just leave the default settings and popping up for a few seconds in the press the OK button Boundary Scan panel Trenz Electronic GmbH 23 Spartan 3E FPGA Industrial Micromodule x _ 77777 1 gt 86 s 4 4444E E 22232238 SI Switch S3 back to the FX PON position In case you uploaded the reference design you should see the on board led blinking at 0 5 Hz For further information about indirect SPI over JTAG in system programming of SPI Flash memories please see Xilinx Applica tion Note XAPP974 Indirect Programming of SPI Serial Flash PROMs with Spartan 3A FPGAS Changes from TEO300 00 to TEO300 01 Clocks TEO300 00 has a 50MHz secondary clock whereas TEO300 01 has a 125MHz second ary clock Volatile Memory Interface TEO300 00 could access the DDR SDRAM only with Xilinx OPB on chip peripheral bus cores TEO300 01 can also access the DDR SDRAM through the dedicated Xilinx MIG memory interface generator memory in terface Trenz Electronic GmbH User Manual B2B Connectors Contact 14 of connector J5 has been ex tended from an input in TEO300 00 to an I O in TEO300 01 Theref
8. SPI Flash corresponding to the one present on the module STMicro electronics M25P32 in the example a 32 Mbit 4M x 8 Serial Flash memory 22 Spartan 3E FPGA Industrial Micromodule User Manual g Device Programming Properties Device 1 Programming Properties E FPGA SPI Flash Association unit Device 1 FPGA xc3s1200e Device 1 Attached FLASH M25P32 Property Name Verity 22 General CPLD And PROM Properties Select SF Flash E Erase Before Programming Y FPGA Device Specific Programming Properties F P G fay 5 P l F l cd h Assert Cable INIT during programming g After programming Flash automatically load FPGA with currently assigned bitst 03312008 M25P32 A un oer iMPACT will first erase the memory IR ZelBoundary Scan perations are ad SlaveSerial gt Get Device ID O SelectMAP m Get Device Signature Usercode Desktop Configuration p Check Idcode t Direct SPI Configuration gt Read Status Register ai SystemAce xc3s1200e E PROM File Formatter file TDO IE Progress Dialog 1 Modes Operations B Boundary Scan cable connection established Firmware version 1302 File version of C Xilinx 10 1 ISE data xusb_xlp hex 1302 Firmware hex file version 1302 Type 0x0004 ESN option OOOOOACB45B701 PLD file version 0012h PLD version 0012h PROGRESS_END End Operation Elapsed time 2 sec Atte
9. enumeration the USB microcontroller firmware switches the 1 2 V and 2 5 V power rails on if enough current is available from the USB bus When S3 is turned off the 1 2 V and 2 5 V power rails are always enabled FX2 PON on PON off Table 9 S3 default FX2 PON rails controlled by FX2 rails always enabled The 3 3 V power rail though is out of the control of the USB microcontroller and is supplied down converting the 5 V power supply provided by either the USB bus or the B2B receptacle connector In this case signals that are applied to the 3 3 V I O Spartan 3E FPGA Industrial Micromodule banks do not need to be disconnected when power rails are disabled by the USB microcontroller DIP Switch S4 S4 enables disables the FPGA configura tion through the SPI interface The FPGA configuration through the JTAG interface cannot be disabled When S4 is turned on the FPGA tries to configure from the SPI Flash memory The FPGA can be configured by the JTAG inter face at any time When S4 is turned off the FPGA waits to be configured by the JTAG interface For further information about direct pure SPI indirect SPI over JTAG in system programming of SPI flash memories please see Xilinx Application Notes XAP P951 Configuring Xilinx FPGAs with SPI Serial Flash and XAPP974 Indirect Pro gramming of SPI Serial Flash PROMs with Spartan 3A FPGAs S4 position SPI
10. has been added Ger te Manager Datei Aktion Ansicht 2 gt EH 2 a HM Prozessoren S Speichervolumes 9 Systemger te gt Tastaturen USB Controller gt CA 200 2 DEWESoft USB Device 0 2 Intel R ICH8 Family USB Universal Host Controller 2830 C amp Intel R ICHS Family USB Universal Host Controller 2831 02 Intel R ICHS Family USB Universal Host Controller 2832 amp Intel R ICH8 Family USB Universal Host Controller 2834 CS Intel R ICHS Family USB Universal Host Controller 2835 2 Intel R ICHS Family USB2 Enhanced Host Controller 2836 2 Intel R ICH8 Family USB2 Enhanced Host Controller 2834 amp USB Root Hub 2 USB Root Hub 2 USB Root Hub amp USB Root Hub 2 USB Root Hub amp USB Root Hub amp USB Root Hub FWU File Generation The TEO300 micromodule can be con figured by means of a firmware upgrade FWU file see next section Micromodule Configuration for further reference The first step in generating the FWU file is to generate the fpga bin file corresponding to a given FPGA design Open Xilinx IMPACT from Start Programs Xilinx ISE Accessories Im pact Select create new project EL iMPACT Project x want to F Load most recent project file when iMPACT starts create a new project ipf default ipf Browse OK Cancel 15 Spartan 3E FPGA Industrial Micromodule Select prepare PROM file A iMPACT Wel
11. switched to EEP ROM do it now m answer the hardware assistant gues tions as shown in the following ex ample Trenz Electronic GmbH Assistent fiir das Suchen neuer Hardware Willkommen User Manual Mit diesem Assistenten konnen Sie Software fur die folgende Hardwarekomponente installieren USB Device C Falls die Hardwarekomponente mit einer CD 4 oder Diskette geliefert wurde legen Sie diese jetzt ein Wie mochten Sie vorgehen O Software automatisch instal Software von einer Liste od lieren empfohlen er bestimmten Quelle installieren fur fortgeschrittene Benutzer Klicken Sie auf Weiter um den Vorgang fortzusetzen Assistent fiir das Suchen never Hardware Wahlen Sie die Such und Installationsoptionen Diese Quellen nach dem zutreffendsten Treiber durchsuchen Verwenden Sie die Kontrollk stchen um die Standardsuche zu erweitern oder einzuschr nken Lokale Pfade und Wechselmedien sind in einbegriffen Der zutreffendste Treiber wird installiert C wechselmedien durchsuchen Diskette CD Folgende Quelle ebenfalls durchsuchen CATEO3004 driver der Standardsuche mit Nicht suchen sondern den zu installierenden Treiber selbst wahlen Verwenden Sie diese Option um einen Geratetreiber aus einer Liste zu w hlen Es wird nicht garantiert dass der von Ihnen gew hlte Treiber der Hardware am besten entspricht Hardwareinstallation A Die Software die
12. 9 B2 GCLK L13 N V9 D3 2 103 3V Y Y 3 3V IO 3 IO L19P M5 B3 L19 P 50 GCLK15 IO L13P 51 B2 GCLK L13 P U9 D4 2 IO 33VY Y 33V IO 3 IO L19N M6 B3 L19N 52 GCLK14 53 2 5 V 3 3 V 25V 54 5 B2 L18 N Nil IO Li8N 2 10 33V Y Y 333V IO 2 IO LOOP P8 B2 L09 P 56 57 B2 L18 P P11 IO L18P 2 IO 33V Y Y 3 3V IO 2 IO LOON N8 B2 L09 N 58 59 B2 L20N R12 IO L20N 2 IO 33V Y N 33VIO 2 IO P9 B2 IO P9 60 61 B2 L20 P T12 IO L20P 2 IO 3 3V Y N 33VIO 2 IO RI B2 10 Ril 62 63 GND GND 64 IO L19N IO L15N 65 B219 N vi3 19 2 IO 33VY N 33V IO 2 D1 P10 B2 IO P10 66 VREF GCLK3 67 B2L19P V12 IO L19P 2 IO 3 3V Y N 33V IO 2 ts R9 B2 IO R9 68 69 B2 L22 N R13 izt 2 IO 3 3V Y Y 3 3V IO 2 IO L21N P12 B2 L21 N 70 71 B2122P P13 ii 2 103 3V Y Y 3 3V IO 2 IO L21P N12 B2L21P 72 73 1 2 V 12V 74 IO L24P 75 B2124P T14 a 2 103 3V Y N3 3V I 2 IPL23P V14 B2 IP V14 76 IO L24N 77 B2124N R14 so 2 103 3VYN3 3VI0 2 IO U13 B2 IO U13 78 79 GND GND 380 receptacle connector J5 pinout information Reference Design Summary Xilinx Spartan 3E 1200 Blatgen p xess 12008433204 Lang vidl Ip XXX System smhs Release Lls platgqen 2211nzcEDR 11 5 B tld EDR doo 70 UE Copyright c 1995 2009 Xilinx Inc All rights reserved Command Line platgen p xc3s1200efg320 4 lang vhdl lp Running post placement packing Design Summary Number of errors 0 Number of warnings IKS Logue Utrbiza ions Number of Slice F
13. FS 83 ES FO 22 50 06 ES 25 82 C8 F6 22 BB FE 05 ES 25 82 C8 F2 22 EB SF F5 FO EA 9E 42 FO ES 9D 42 FO E8 9C 45 FO 22 Disconnect the USB cable Dedicated USB Firmware Driver Installation Check the configuration switches against the following table Trenz Electronic GmbH User Manual DIP on left off right switch S1 EEPROM S2 Run S3 FX2 PON S4 X X Reconnect the USB cable to run the newly uploaded firmware in the USB microcon troller Under the default switch configura tion the USB microcontroller is now ready to provide dedicated vendor 1D and device ID Wait until the operating system detects new hardware and starts the hardware as sistant and answer the hardware assistant questions as shown in the following ex ample Assistent fiir das Suchen neuer Hardware Willkommen Mit diesem Assistenten konnen Sie Software fur die folgende Hardwarekomponente installieren DeweSoft USB Device C Falls die Hardwarekomponente mit einer CD oder Diskette geliefert wurde legen Sie diese eS jetzt ein Wie mochten Sie vorgehen Software iomach installieren empfohlen Klicken Sie auf Weiter um den Vorgang fortzusetzen 14 Spartan 3E FPGA Industrial Micromodule Hardwareinstallation Die Software die fur diese Hardware installiert wird DEWESoft USB Device hat den Windows Logo T est nicht bestanden der die Kompatibilit t mit Windows XP berpr ft Waru
14. L17 P 32 33 3 3 V 3 3 V 34 35 BO IO A7 A7 IO O IO VccIO N N VccIO IO O IO A8 BO IO A8 36 IO_L14N 37 BO IO G9 G9 IO O IO VccIO N Y VccIO IO 0 J GCLK11 D9 GCLK_L14 N 38 IP L13P IO L14P 39 GCLK L13 P B8 GCLK8 O I VccIO Y Y VccIO IO 0 GCLK10 C9 GCLK_L14 P 40 IP L13N IO L11N 41 GCLK L13 N B9 GCLK9 O I VccIO Y Y VccIO IO 0 J GCLK5 E10 GCLK_L11 N 42 IO L11P 43 GND Y VccIO IO 0 J GCLK4 D10 GCLK _ Li1 P 44 IO L12P 45 GCLK L12 P B10 GCLK6 O IO VccIO Y GND 46 47 GCLK L12 N A10 ae IO VccIO Y Y VccIO IO 0 IO LO9N Dil BO LOO N 48 49 BO L15 P E9 IO L15P 0 IO VccIO Y Y VccIO IO O IO LOOP Cii BO LO9 P 50 51 BO L15 N F9 IO L15N 0 IO VccIO Y N VccIO IO O IO All B0 IO All 52 53 2 5 V 2 5 V 54 55 BO LO8 P E11 IO LO8P O IO VccIO Y N VccIO IO O IO VREF B11 BO IO B11 56 57 BO L08 N F11 IO LO8N 0 IO VccIO Y N VccIO IO 0 IO A12 B0 IO A12 58 59 BO LO5 P A13 IO LO5P O IO VccIO Y Y VccIO IO O IO_LO6P F12 BO LO6 P 60 61 BO L05 N B13 EC O IO VccIO Y Y VccIO IO O IO LOGN E12 BO LO6 N 62 63 GND GND 64 65 BO LO4 N A14 IO LO4N 0 IO VccIO Y N VcclO IO 0 IO D13 BO IO D13 66 67 B0 LO4 P B14 IO LO4P 0 IO VccIO Y N VcclO IO 0 IO E13 BO IO E13 68 69 BO LO3N C14 Ar 0 IOVccI0 Y 33V I 2 TDI a2 TDI 70 71 BO LO3_P D14 IO L03P 0 IO VccIO Y 3 3V 02 TDO C16 TDO 72 73 1 2V 1 2V 74 75 BO LO1 N A16 IO LOIN 0 IO VccIO Y 3 3V I 2 TCK A17 TCK 76 77 BO_LO1_P B16 IO LO1P 0 IO VcclO Y 33VW I 2 TMS D15 TMS 78 79 GND GND 80 receptacle
15. OM File Formatter xl INFO iMPACT 501 1 Added Device xc3s400 successfully PROM File Generation Target Xilinx PROM 1 699 136 Bits used File Fpga in Location C xilinx You are done 17 Spartan 3E FPGA Industrial Micromodule E iMPACT C Xilinx default ipf PROM File Formatter m 01 x L File Edit View Operations Window Help 5 x BB8BEx Ro xi EE Boundary Scan ie SlaveSerial ED SelectMAP PROM ED Direct SPI Configuration xcf02s z B SystemA CE 81 02 Full xc3s400 E PROM File Formatter download bit E Operations are Operations PROM File Generation Succeeded 14 PROM File Formatter amp Writing file C Xilinx fpga prm Writing file C Xilinx fpga sig PROM File Generation Target Xilinx PROM 1 699 136 Bits used File Fpga in Location C xilinx f Don t forget to save your project for fur ther use E Exit iMPACT x Do you want to save project file before exiting Mo Cancel Once you have got your fpga in file you can proceed and generate your FWU file The FWU file is a ZIP file containing 3 files m Bootload ini booting settings m fpga bin FPGA programming file m usb bin FX2 firmware To create your FWU file you need to m replace the existing USBFWUTool FWUs fpga bin with the latest fpga bin Bootload ini and usb bin are always unchanged
16. SystemACE E PROM File Formatter Modes Eb Direct SPI Configuration BATCH CMD setMode BATCH CMD setMode spi 19 Spartan 3E FPGA Industrial Micromodule You can now select the file corresponding to your device In the following example we will show how to select the micromod ule reference device blinking mcs in the TEO300 folder Add Device Suchen in 6 TEO300 v e m a blink1600 mcs Zuletzt O 1st_program verwendete D Desktop r Eigene Dateien Arbeitsplatz Netzwerkumgeb Dateiname blinkin mes st ung an Design Files mes exo v Abbrechen Dateityp Select the part name corresponding to the SPI flash present on the module STMicro electronics M25P32 a 32 Mbit 4M x 8 Serial Flash memory E Select Device Part Name Select PROM Part Name Cancel IMPACT should now look like this Trenz Electronic GmbH User Manual iMPACT Direct SPI Configuration Ub Eile Edit View Operations Options Output Debug Window Help Ba Boundary Scan ad SlaveSerial aa SelectMAP il Desktop Configuration MOSI ig FaDirect SPI Configuration la System amp CE ss n m25p32 PROM File Formatter blinkin mes MISO Modes Operations B Direct SPI Configuration A Welcome to iMPACT ff BATCH CMD setMode spi ff BATCH CMD setMode spi Selected part M25P32 INFO iMPACT 501 1 A
17. T Receptacle Header h 0 5 Figure 7 stacking height h The stacking height of the TEO300 B2B connectors is 7 seven mm The stacking height does not include the solder paste thickness USB Connector The micromodule uses a mini USB B type receptacle connector Figure 8 mini USB B type receptacle connector Power Supply The module can be powered by the B2B connector or the USB connector If both power supplies are available the B2B con nector power supply takes precedence disabling the USB power supply automatic ally B2B Connector Power Supply The B2B connector power supply reguires a single nominal 5 V DC power supply The power is usually supplied to the module through the 5 V contacts 5Vb2b of the B2B connectors J5 see Appendix The re commended minimum supply voltage is Spartan 3E FPGA Industrial Micromodule 4 V The maximum supply voltage is 5 5 V The recommended maximum continuous supply current is 1 5 A USB Power Supply The module is powered by the USB con nector if the following conditions are met m the module is equipped with an USB connector m the module is connected to a USB bus no power supply is provided by the B2B connectors In this case other components e g ex tension or carrier boards may also be powered by the corresponding 5 Volt line 5V of the B2B connector J5 On board Power Rails Three on board voltage regulators provide the following p
18. a clock source for both the USB microcontroller and the FPGA as de tailed in Table 14 Trenz Electronic GmbH 9 Spartan 3E FPGA Industrial Micromodule Signal FPGA pin FPGA ball IO L12P 2 24MHZ1 bank 2 N9 Table 14 24 MHz clock signal details Main Clock Oscillator The module has a main SMD clock oscillat or providing a clock source for the FPGA as detailed in Table 15 Signal FPGA pin FPGA ball 100MHZ GCLKO U10 125MHZ bank 2 Table 15 main clock signal details Standard frequencies are 100 MHz and 125 MHz please visit Trenz Electronic website for current ordering information The lower the main clock frequency the lower the module power consumption Moreover as the main clock is preferably used as DDR SDRAM clock a lower clock frequency makes easier for the development tools to meet the timing requirements particularly for DDR SDRAM For customized boards this clock can be changed according to user requirements Interface Clock IFCLK The IFCLK line synchronizes the commu nication between the USB microcontroller and bank3 of the FPGA as detailed in Table 16 Signal FPGA pin FPGA ball LHCLK5 IFCLK bank 3 K4 Table 16 interface clock signal details bank 3 Digital Clock Manager DCM The DCMs of the FPGA can be used to syn thesize arbitrary clock frequencies from any on board clock network differential Trenz Electronic GmbH User Manual clock input pair or sing
19. ailable on request Software for SPI flash programming over USB as well as reference designs for high speed data transfer over USB are included Physical Features Board Dimensions The module measures 40 50 mm by 47 50 mm Board to Board Connectors Trenz Electronic GmbH User Manual 4 25 3 25 top view 40 50 36 25 Figure 3 module dimensions in mm top view The module has two B2B board to board receptacle connectors J4 and J5 for a total of 160 contacts Figure 5 Figure 5 micromodule receptacle The ordering numbers of the connector re ceptacles are given in Table 1 Spartan 3E FPGA Industrial Micromodule supplier header H11113CT ND Digikey H11113TR ND H11113DKR ND Hirose DF17 3 0 80DS 0 5V 57 Trenz Electronic 22684 Table 1 equivalent part numbers of the receptacle connectors J4 and J5 The on board receptacles mate with their corresponding headers on the carrier board Figure 6 Figure 6 mating header The ordering number of the headers is giv en in Table 2 supplier header H11148DKR ND Digikey H11148TR ND H11148CT ND Hirose DF17 4 0 80DP 0 5V 57 Trenz Electronic 22938 Table 2 equivalent part numbers of the mating connectors Figure 7 shows the definition of stacking height featured by the combination of the TEO300 receptacle with its corresponding header Trenz Electronic GmbH User Manual
20. ches by fixed connections DIP Switch S1 S1 enables disables the communication between the Cypress EZ USB FX2 micro controller and the I2C CMOS Serial EEP ROM Turn S1 off when programming the USB EEPROM storing the USB vendor ID and device 1D This will force the USB micro controller to provide its default vendor 1D and device ID EEPROM on EEPROM enabled Off off EEPROM disabled Table 7 S1 default EEPROM For further information please read para graph Software Configuration DIP Switch S2 S2 enables disables the reset line The reset line available also on 2 contacts of the B2B connector resets the USB micro controller and the FPGA Trenz Electronic GmbH User Manual S2 has to be turned off Reset if the user wants to program the SPI Flash memory in direct mode For programming the SPI Flash memory in indirect mode over JTAG S2 has to be turned on Run Run on Reset off system running system reset Table 8 S2 default Run For further information please read para graph Software Configuration DIP Switch S3 S3 conditionally unconditionally enables the 1 2 V and 2 5 V power rails When S3 is turned on the 1 2 V and 2 5 V power rails are controlled by the USB mi crocontroller At start up the USB micro controller switches off the 1 2 V and 2 5 V power rails and starts up the module in low power mode After
21. come to iMPACT Please select an action from the list below C Configure devices using Boundary Scan JT G Prepare a PROM File C Prepare a System ACE File C Prepare a Boundary Scan File SVF y C Configure devices using Slave Serial mode v Select BIN as output EL iMPACT Prepare PROM Files want to target a Xilinx PROM C Generic Parallel PROM C 3rd Party SPI PROM C PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format C MCS C TEK C UFP C format C EXO 7 BIN C ISC C HEX J Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name lipga Location jc ilins Browse lt Back New Cancel Trenz Electronic GmbH User Manual Set PROM File Name to fpga and change Location to a suitable name and location E iMPACT Specify Xilinx PROM Device J Enable Revisionina Number of Revisions 1 J Enable Compression Select a PROM bits Unspecifiex Add r Pozitiori Part flarn Delete All lt Back New Cancel Check Auto Select PROM El Add Device i Start adding device file to Data Stream O Navigate to your projects IMPLEMENTA TION folder and select download bit 16 Spartan 3E FPGA Industrial Micromodule Add Device Look in 3 implementation a ia mun jcache Sjopb_intc_0_wrapper i c
22. connector J4 pinout information FPGA FPGA ba ba FPGA FPGA B2B E dir dir A pin name nk nk name pin name 1 5Vb2b I I 5Vb2b 2 3 5Vb2b I I 5Vb2b 4 5 5V O I MR 6 7 B2B D P IO Y O RESET 8 9 B2B D N IO Y O RESET 10 11 GND GND 12 13 B3 L22 P P3 10 L22P 3 IO 3 3V Y N 3 3 V IO 3 IO L24P T2 B3 IO T2 14 15 B3 L22 N P4 IO L22N 3 IO 3 3V Y Y 3 3V IO 3 IO L21N PL B3 L21 N 16 17 B2 IP V4 V4 IP LO2P 2 I 33VN Y 33V IO 3 IO L21P P2 B3L21P 18 19 B3 L20 P N4 IO L20P 3 IO 3 3V Y Y 3 33 V IO 3 IO L23N R2 B3 L23 N 20 21 B3 L20 N N5 IO L20N 3 IO 3 3V Y Y 3 3V IO 3 IO L23P R3 B3 L23 P 22 23 GND GND 24 25 B2 LO4 N T5 IO LOAN 2 IO 3 3V Y N 3 3 V IO 3 IO LISN M3 B3 IO L18N 26 10_LO3P 27 B2 L04 P R5 IO L04P 2 IO 3 3V Y N 3 3 V IO 2 DOUT U4 B2 IO L03 28 BUSY 29 B2 L05 P R6 IO LOSP 2 IO 33V Y N 3 3V IO ME U5 B2 10 U5 30 31 B2 L05 N P6 IO LOSN 2 IO 3 3V Y Y 3 3 V IO 2 IO LOOP V5 B2 L06 P 32 33 B2 10 V7 V7 10 IO 3 3V N Y 3 3V IO 2 EEE V6 B2 L06 N 34 35 3 3 V 33V 36 37 B2 L07 N P7 IO LO7N 2 IO 3 3V Y N 3 3 V IO IO U6 B2 IO U6 38 39 B2 LO7P N7 IO LO07P 2 IO 3 3V Y Y 3 3V IO 3 EEE L5 B3 L17 N 40 IO L12N 41 B2 GCLK12 M9 D6 2 I 33VN Y 33V IO 3 IO L17P L6 B3 L17P 42 GCLK12 43 GND GND 44 45 B2 L10 N T8 IO LION 2 IO 333V Y N3 3V I 2 IP LO8P 17 B2 IP 17 46 47 B2 L10 P RS IO L10P 2 IO 3 3V Y N3 3V I 2 IP L11P U8 B2 IP U8 48 IO L13N 4
23. dded Device M25P32 successfully 11 Loading file E TEO300 blinkin mcs INFO iMPACT Elapsed time O sec done ff BATCH CMD set ttribute position 1 attr packageName value 5 lt Iad Output Error Warning No Cable Connection Right click the SPI PROM device and select the Program operation iMPACT Direct SPI Configuration bp Eile Edit View Operations Options Output Debug Window Help AH HEX HKU Gi 80 y X IMPACT Processes x 2a Boundary Scan Available Operations are aa slaveSerial gt Program IE Ba SelectMAP p Verify Verify tl Desktop Configuration mp Erase Erase 3Direct SPI Configuration Blank Check 5 Blank Check al System CE gt Readback ss_n Readback m25p32 PROM File Formatter blinkin mcs Assign New Configuration File j 1 Operations B Direct SPI Configuration Welcome to iMPACT BATCH CMD setMode spi BATCH CMD setMode spi Selected part M25P32 INFO iMPACT 501 1 Added Device M25P32 successfully 1 Loading file E TEO300 blinkin mcs INFO iMPACT Elapsed time O sec done BATCH CMD set ttribute position 1 attr packageName value 5 lt on al Output Eror Warning No Cable Connection In the Programming Properties window just leave the default settings and press the OK button T Programming Properties Category EB Progra
24. ded inputs Trenz Electronic GmbH User Manual Table 4 summarizes the maximum avail able FPGA user I Os divided by supply voltage type VccIO 3 3 V diff I O pairs lt 18 lt 23 diff inputs lt 1 none diff clocks lt 4 lt 1 s I Os lt 46 lt 58 s e inputs lt 2 lt 4 s e clocks lt 8 lt 3 Table 4 maximum FPGA user I Os by supply voltage Differential Pairs The micromodule has a total of 42 differ ential signal pairs routed pairwise with a differential impedance of 100 ohm to adja cent connector pins These lines can be used for high speed signaling up to 666 Mbit s per differential pair see Xilinx Application Note XAPP485 User Button and LED LED The LED is lit when the U LED line pin R10 is set high as detailed in the follow ing table Signal FPGA pin FPGA ball IO L15P 2 U LED Bank 2 R10 Table 5 user led signal details Push Button The push button is connected to the PB in put pin V16 as detailed in the following table Spartan 3E FPGA Industrial Micromodule Signal FPGA pin FPGA ball IP PB bank 2 V16 Table 6 user button signal details The input is normally low The input is pulled up when pressed Configuration Switches The micromodule hosts 4 DIP switches on the top side S1 S2 S3 and S4 For customers requesting a sufficient amount of units the micromodules can be manufactured replacing the swit
25. er of 4 input LUTs 85 038 GUC GE 29 504 2 Logic Distribution Number of occupied Slices 65 424 QUE OLE 14 752 43 Number of Slices containing only related logic 6 424 out of 6 424 100 Number of Slices containing unrelated logic SU or 6 424 0 See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs 85421 006 9T 29 5024 28 Number used as logic 6 063 Number used as a route thru 583 Number used for Dual Port RAMs 1 812 Two LUTs used per Dual Port RAM Number used as Shift registers 163 The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails Number of bonded IOBs 74 out of AO 29 LOB Flip Flops 36 IOB Master Pads i IOB Slave Pads Number of ODDR2s used 22 Number of DDR ALIGNMENT NONE 22 Number of DDR ALIGNMENT C0 0 Number of DDR ALIGNMENT C1 0 Number of RAMB16s ZO OE Of 36 69 Number of BUFGMUXs x OUE Of 24 20 Number of DCMs I U6 OE 8 12 Number of BSCANSs 1 OME OT 1 100 Number of MULT18X18S10s SOME Of 36 Number of RPM macros 1 Average Fanout of Non Clock Nets Sino Initializing temperature to 85 000 Celsius default Range 40 000 to 100 000 Celsius Initializing voltage to 1 140 Volts default Range 1 140 to 1 320 Volts Device speed data version PRODUCTION 1 27 2010 02 13 Design Summary Report Number of External IOBs Te QUE OL 250 29 Numbe
26. fur diese Hardware installiert wird Cypress Generic USB Device hat den W indows Logo T est nicht bestanden der die Kompatibilit t mit Windows XP berpr ft warum ist dieser Test wichtig Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder in Zukunft beeintrachtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller fur Software die den Windows Logo Test bestanden hat in Verbindung zu setzen Installation fortsetzen i Installation abbrechen 12 Spartan 3E FPGA Industrial Micromodule Assistent f r das Suchen neuer Hardware Fertigstellen des Assistenten Die Software f r die folgende Hardware wurde installiert Cypress Generic USB Device Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en Check that in the Device Manager under USB Controller the Cypress Generic USB Device has been added Ger te Manager Datei Aktion Ansicht 38 AxA A Prozessoren Speichervolumes Systemger te gt Tastaturen 4 USB Controller gt CA 200 2 Intel R ICHS Family USB Universal Host Controller 2830 gt Intel R ICH8 Family USB Universal Host Controller 2831 2 Intel R ICH8 Family USB Universal Host Controller 2832 62 Intel R ICHS Family USB Universal Host Controller 2834 2 Intel R ICH8 Family USB Universal Host Controller 2835 62 Intel R ICH8 Family USB2 E
27. hipscope_icon_O_wrapper a rs232_wrapper Recent chipscope_opb_iba_O_wrapper sdram_16mx16_wrapper dem_O_wrapper Dspi_adc_0_wrapper E IT spi mon 0 wrapper Desktop 3 dimb_cntlr_wrapper kdownload bit dmb_wrapper download_cclktemp bit g Jilmb_cntlr_wrapper system bit Jilmb_wrapper My Documents Imb_bram_wrapper mb_opb_wrapper microblaze_O_wrapper My Computer is opb_fx2_0_wrapper a a Ea Filename download bit Places Files of type FPGA Bit Files bit y Cancel The following warning is a normal situ ation F warning WARNING IMPACT 2257 Startup Clock has been changed to Cclk in the bitstream stored in memory but the original bitstream File remains unchanged This is probably the one and only file with your design E Add Device Would you like to add another device File to Data Stream Congratulations Trenz Electronic GmbH User Manual F Add Device You have completed the device File entry Click Ok to continue Click GENERATE FILE or select from menu Operations Generate file e iMPACT C Xilinx default ipf PROM File Formatter L Eile Edit View Operations Window Help IPE SBBRM BRIG BS Boundary Scan i 20 SlaveS erial e Ba SelectMAP Desktop Configuration Ba Direct SPI Configuration i E SystemACE tee PROM File Formatter xc3s400 dowenload bit Available Operations are Operations L PR
28. hould select the following product type HYB25D512160BF 6 SPI Flash TEO300 modules have a STMicroelectronics M25P32 32 Mbit low voltage serial Flash memory with 75 MHz SPI bus interface for configur ation and operating storage accessible through USB or SPI Serial EEPROM TEO300 modules have a Micron Technology 24LC128 128K I2C CMOS Serial EEPROM It used for EZ USB FX2 firmware vendor ID and device ID storage EEPROM accessible through the EZ USB FX2 microcontroller Module Configuration This section describes how to configure the TEO300 module and access some of its re sources The JTAG interface allows a fast freguent but volatile configuration of the TEO300 module However only through the JTAG Trenz Electronic GmbH User Manual interface it is possible to develop and de bug with Xilinx tools e g Xilinx Chip Scope Xilinx Microprocessor Debugger The SPI interface allows a fast frequent and non volatile configuration of the TEO300 module Configuration of the TEO300 module through a USB host is recommended for occasional non volatile on site operations such as firmware upgrade System Requirements TEO300 modules can be configured through a host computer with the following system requirements m Operating system Microsoft Windows 2000 Microsoft Windows XP Microsoft Vista m Xilinx ISE 10 1 or later for indirect SPI in system programming see Xilinx An swer AR 25377 m Xilinx
29. iew Trenz Electronic GmbH 1 Table of Contents FEE ms yo e I S Pr SE EE EE O E So A 1 on CE 1 aa p e A o UE O a ET o Eo as 3 Br LE S A N V tr eT 3 alles Ns iii SEE S V 3 e PI aa e rr eN NE NI 5 SL A A e PE PERO UI II h rtere Banane 6 eds E AO o E E N E S K EVS 7 Sa o UE O o A REN 7 AL A AA A PP o e 8 4 6 do R Ao o E PI Eo Pe irinn 9 dae s L Momor PP on o S kr iiiin 10 Module a lao 1 Oo ea EEE Om nm A S GREEN 11 Changes Mom TEOS00 00 to TEIL III nenne 24 Ds A e E e o o Nn 24 A ire ig E A A A E T T A E T E E E 24 a is a A eo ES Co a A o O 25 ENVIOnmenta Prot eTO ee s n n sis idos 26 o NPE NE e PE o E no S PAA 27 Spartan 3E FPGA Industrial Micromodule Applications m IP intellectual property development m Digital signal processing m Image processing m Cryptography m Industrial control m Low power design m General purpose prototyping platform Description The FPGA industrial micromodule integ rates a leading edge Xilinx Spartan 3E FPGA an USB 2 0 microcontroller config uration Flash DDR SDRAM and power sup plies on a tiny footprint A large number of configurable I Os are provided via B2B mini connectors The module is intended to be used as an OEM board or to be combined with our carrier boards It is a powerful system widely used for educational and research activities Boards with other configurations larger FPGA s or equipped with industrial temper ature grade parts are av
30. ions Output Debug Window Help ASIA wei E low X IMPACT Processe Flows o Add Device or Initialize JTAG chain An Assign New Configuration File dialog window should pop up automatically You can now select the file corresponding to your design In the following example we will show how to select the micromodule reference design blinking bit in the TEO300 folder Do not forget to select the Enable Programming of SPI Flash Device Attached to this FPGA option in the Same window Trenz Electronic GmbH User Manual F Assign New Configuration File Look in g E TE0300 a O 1st_program Ex blinkin bit blinkin1 600 bit File name blinkin bit Open File type All Design Files bit rbt nky isc bsd Y O None Enable Programming of SPI Flash Device Attached to this FPGA O Enable Programming of BPI Flash Device Attached to this FPGA An Add PROM File dialog window should pop up automatically You can now select the file corresponding to your design In the following example we will show how to select the micromodule reference design blinking mcs in the TEO300 folder Add PROM File Suchen in le temp_TEO300 v D rf E Zuletzt verwendete D Desktop Eigene Dateien Arbeitsplatz J Netzwerkumgeb Dateiname lbinkinmes st ung Dateityp mos Files mes v Abbrechen Select now the
31. le ended clock in put For further reference please read Xil inx data sheet DS485 Digital Clock Man ager DCM Module dcm module pdf and Xilinx application note XAPP462 Using Digital Clock Managers DCMs in Spartan 3 FPGAs xapp462 pdf On board Memories The TEO300 has three on board memories DDR SDRAM m SPI Flash m serial EEPROM DDR SDRAM TEO300 modules have a 512Mb DDR SDRAM component for operation code and data accessible through the FPGA Commercial grade modules mount the fol lowing component Micron Technology MT46V32M16BN 6 Industrial grade modules mount the fol lowing component Micron Technology MT46V32M16BN 6 IT You can get the exact part number of the component mounted on your module from the Micron FBGA decoder http www micron com support part_info fbga decoder When developing DDR SDRAM designs with Xilinx tools e g MIG MPMC you should select the following product type MT46V32M16 6 Should it be not available you can use one of the following product types MT46V32M16 5 MT46V32M16XX 5B MT46V32M16BN 5B MT46V32M16FN 5B MT46V32M16P 5B MT46V32M16TG 5B 10 Spartan 3E FPGA Industrial Micromodule TEO300 modules with the following part numbers TEO300 00 TEO300 00 415C TEO300 00B TEO300 01 TEO300 01B TEO300 01BLP are assembled with Oimonda HYB25DC512160CF 6 512Mb DDR SDRAM components When developing DDR SDRAM designs with Xilinx tools you s
32. lip Flops 5 885 out of 17 344 33 Number of 4 input LUTs Si Ob ONG OE T7244 46 LOG Le DISE7ILHUL LOHR Number of occupied Slices 6 622 Out of 8 672 76 Number of Slices containing only related logic 6622 O UE DE Or622 L00S Number of Slices containing unrelated logic Ot sie os 6 622 0 See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs 8 424 out of 17 344 48 Number used as logic 6 066 Number used as a route thru 383 Number used for Dual Port RAMs ES s Two LUTs used per Dual Port RAM Number used as Shift registers 1 63 The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails Number of bonded IOBs 74 out of 250 29 LOB Flip ELOpSs 36 IOB Master Pads 1 IOB Slave Pads Number of ODDR2s used 22 Number of DDR ALIGNMENT NONE 22 Number of DDR ALIGNMENT CO 0 Number of DDR ALIGNMENT C1 0 Number of RAMB16s 2 Ou OT 28 89 Number of BUFGMUXs G OU Of 24 20 Number of DCMs ll OE of 8 12 Number of BSCANs ll Ol OE 1 100 Number of MULT18X18S10s SOME Of 28 10 Number of RPM macros 2 Average Fanout of Non Clock Nets SES Initializing temperature to 85 000 Celsius default Range 40 000 to 100 000 Celsius Initializing voltage to 1 140 Volts default Range 1 140 to 1 320 Volts Device speed data version PRODUCTION 1 27 2010 02 13 Design Summary Report Number of Exte
33. m ist dieser Test wichtig Das Fortsetzen der Installation dieser Software kann die korrekte Funktion des Systems direkt oder in Zukunft beeintrachtigen Microsoft empfiehlt strengstens die Installation jetzt abzubrechen und sich mit dem Hardwarehersteller fur Software die den Windows Logo Test bestanden hat in Verbindung zu setzen Installation fortsetzen Installation abbrechen Assistent f r das Suchen neuer Hardware Wahlen Sie die Such und Installationsoptionen Een Y Verwenden Sie die Kontrollk stchen um die Standardsuche zu erweitern oder einzuschr nken Lokale Pfade und Wechselmedien sind in der Standardsuche mit einbegriffen Der zutreffendste Treiber wird installiert Wechselmedien durchsuchen Diskette CD Folgende Quelle ebenfalls durchsuchen CATEO3004 driver v Durchsuchen O Nicht suchen sondern den zu installierenden Treiber selbst w hlen Verwenden Sie diese Option um einen Ger tetreiber aus einer Liste zu w hlen Es wird nicht garantiert dass der von Ihnen gewahlte Treiber der Hardware am besten entspricht Ca Jas Assistent fiir das Suchen neuer Hardware Fertigstellen des Assistenten Die Software fur die folgende Hardware wurde installiert gt DEWESoft USB Device Klicken Sie auf Fertig stellen um den Vorgang abzuschlie en Trenz Electronic GmbH User Manual Check that in the Device Manager under USB Controller the DEWESoft USB Device 0
34. mming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLD And PROM Properties Erase Before Programming Read Protect PROM CoolRunner l Usercode 8 Hex Digits CPLD Specific Properties Write Protect Functional Test On The Fly Program XPLA UES Enter up to 13 characters PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF Spartan34N Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties Pulse PROG Program Key Assert Cable INIT during programming 20 Spartan 3E FPGA Industrial Micromodule MPACT will first erase the memory notice the mismatch between the two progress indicators Progress Dialog 61 Executing command Cancel and then write it notice the match between the two progress indicators E Progress Dialog 10 Executing command Cancel After successful programming you should read the message Program Succeeded popping up for a few seconds in the Direct SPI Configuration panel aaa EEx lDirect SPI Configuration SCLK p Erase MOSI ar ect E SystemACE mp Readback SS za E PROM File Formatter biinkin mes mso Program Succeeded porton irect onfiguration x ce Configuration Platform Cable USB 6 MHz usb hs Trenz Electronic GmbH User Manual Switch S2 back to the Run position In case
35. mpting to identify devices in the boundary scan chain configuration BATCH CMD Identify PROGRESS_START Starting Operation Identifying chain contents 1 Manufacturer s ID Xilinx xc3s1200e Version O INFO iMPACT 1777 Reading C Xilinx 10 1 ISE spartan3e data xc3s1200e bsd INFO iMPACT 501 1 Added Device xc3s1200e successfully Esecuting command PROGRESS END End Operation Elapsed time 0 sec BATCH CMD identifyMPM ac 5 Output Error Warning Configuration Platform Cable USB 6 MHz usb hs Lancel Right click the Flash device and select the Program operation and then write it EL iMPACT Direct SPI Configuration 6 Eile Edit View Operations Options Output Debug Window Help PA XBOX 283 fi O0 s WM X iMPACT Processes x Fa Boundary Scan Available Operations are ad SlaveSerial gt Program Ea SelectMAP il F 3 Verify ES Desktop Configuration Erase 8Direct SPI Configuration id Blank Check E System CE mb Readback ss_n Readb ck PROM File Formatter blinkin mes Assign New Configuration File MISO _____ Modes Operations Eb Direct SPI Configuration pa ka PJ Welcome to iMPACT BATCH CMD setMode spi BATCH CMD setMode spi Selected part M25P32 INFO iMPACT 501 1 Added Device M25P32 successfully 1 Loading file E TEO300 blinkin mcs INFO iMPACT Elapsed time
36. nhanced Host Controller 2836 CS Intel R ICHS Family USB2 Enhanced Host Controller 2834 2 USB Root Hub 2 USB Root Hub 6 USB Root Hub 2 USB Root Hub 2 USB Root Hub 6 USB Root Hub 2 USB Root Hub Now the USB microcontroller can be ac cessed from the host computer through dedicated software EZ USB FX2 EEPROM Programming First of all check that Si switched to EEPROM The USB EEPROM can be programmed by opening the dedicated software Cypress USB Console double click the CyCon sole exe file in the 1st_program CyCon sole folder is actually Trenz Electronic GmbH User Manual 7 Cypress USB Console File Options Help n E D Selected Script Select Device USB Address Name in Windows Device Mar from inf 4 USB Device Cypress Generic USB Device Device Properties Control Endpt Xfers Other Endpt Xfers Misc WendorlD 0x04B4 Class OxFF ProductlD 0x8613 Subclass OxFF Manufacturer Protocol xFF Product bedDevice Ox4001 Serial Number Device Configurations 1 Attributes 0x01 0x80 0x32 100 mA Configuration Interfaces 4 _Intfc_ Alt Setting Class Subclass Protocol 0 0 xFF Wendor OxFF OxFF 0 1 0 2 OxFF Vendor OxFF OxFF OxFF Vendor OxFF OxFF Interface Endpoints 0 Max Pkt Size Click Options gt EZ USB Interface to Open EZ USB Interface window 7 EZ USB Interface Get Dew Get Conf Get Pipes
37. of the two pad pairs placed on the right of connector J4 at the top right corner of the bottom side of the micromodule Figure 9 shows how to short circuit VccIO to internal 3 3 V power rail Figure 10 shows how to short circuit VccIO to internal 2 5 V power rail Spartan 3E FPGA Industrial Micromodule N i ke Figure 9 R102 pad pair blue high light for 3 3 V internal supply Two suitable ways of shirt circuiting the paid pair are by means of a zero ohm 0603 1608 metric chip resistor or a solder blob FPGA User I Os A total of 110 FPGA user I Os are available on corresponding contacts of B2B connect ors J4 and J5 see Appendix m 37 differential digital I O pairs each pair is configurable as 2 single en ded digital I Os corresponding to a maximum of 74 single ended digital I Os m 4 differential clock input pairs each pair is configurable as differential digital I O pair or 2 single ended clock inputs or 2 single ended digital I Os or combination thereof corresponding to from a maximum of 8 independent clock inputs to a maximum of 8 independent digital I Os m 1 differential clock input pair the pair is configurable as differential digital input pair or as 2 single ended clock inputs or 2 single ended digital in puts or combination thereof corres ponding to from a maximum of 2 inde pendent clock inputs to a maximum of 2 independent digital inputs 21 single ended digital I Os 5 single en
38. on FPGA configuration JTAG SPI JTAG off FPGA configuration JTAG Table 10 S4 default SPI DIP Switches Overview Figure 11 summarizes functions and loca tion of the four DIP switches Trenz Electronic GmbH User Manual off PON S3 power rails on FX2 PON enabled EEPROM disabled work reset line reset JTAG SPI FPGA configuration JTAG Figure 11 DIP switches overview JTAG and SPI The offset holes for J2 and J3 allow a re movable press fit of standard 0 100 inch header pins to connect the fly wires without any soldering necessary JTAG Header JTAG signals are available on the dedic ated header J2 through a JTAG program mer with flying leads as described in Table 11 Spartan 3E FPGA Industrial Micromodule User Manual TMS SPI S TDI SPI D TDO SPI O TCK SPI C GND GND Vref 3 3 V Vref 3 3 V Table 11 JTAG header J2 SPI Header SPI signals are routed to from bank 2 of the FPGA as detailed in Table 12 and made available on the dedicated header J3 ac cessible through an SPI programmer with flying leads as described in Table 13 Signal FPGA pin FPGA ball SPI S IO_LO1P_2 U3 Table 13 SPI header J3 SPI D IO LO3N 2 T4 SPIO IO L16N 2 N10 Clock Networks SPI C IO L26N 2 U16 Table 12 SPI signal details bank 2 24 MHz Clock Oscillator The module has a 24 MHz SMD clock oscil lator providing
39. on for users within the European Union in accordance with Directive 2002 96 EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment WEEE Users of electrical and electronic equip ment in private households are required not to dispose of waste electrical and elec tronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately By the 13 August 2005 Member States shall have ensured that systems are set up al lowing final holders and distributors to re turn waste electrical and electronic equip ment at least free of charge Member States shall ensure the availability and ac cessibility of the necessary collection facil ities Separate collection is the precondi tion to ensure specific treatment and re cycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Uni on Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment Presence of hazardous substances in elec trical and electronic equipment results in potential effects on the environment and 26 Spartan 3E FPGA Industrial Micromodule human health The symbol consisting of the crossed out wheeled bin indicates sep arate collection for waste electrical and electronic equipment
40. ore hardware designs developed for the TEO300 00 are compatible with the TEO300 01 whereas those developed for the TEO300 01 are compatible with the TEO300 00 if that con tact is configured as input Contact 76 of connector J5 has mistakenly been described as I O in TEO300 00 but it has always been an input only contact as documented for TEO300 01 Connector J4 has not been changed LED With TEO300 00 the LED is lit when the U_LED line on pin T15 is set high whereas with TEO300 01 the LED is lit when the U_LED line on pin R10 is set high Ordering Information For the latest product details and available options please visit www trenz electronic de shop trenz electronic de Revision History Rev Date Who Description 0 1 2008 04 24 FDR created 1 0 2008 08 01 FDR completed 1 01 2008 08 08 TT 50MHz to 125MHz clock 1 02 2008 10 17 FDR U_LED for TEO300 00 1 03 2008 10 17 FDR updated FUT from 1 9 to 2 6 24 Spartan 3E FPGA Industrial Micromodule Rev Date Who Description 1 04 2008 10 27 FDR DIP switches overview 1 05 2008 10 29 FDR stacking height 1 06 2008 12 08 FDR DIP switches revised 1 07 2009 02 16 FDR fixed DIP switches overview picture 1 08 2009 03 09 FDR clarified warning regarding 3 3 V power rail 1 09 2009 03 16 FDR fixed and improved switch settings 1 10 2009 06 03 FDR added FWU File Generation section
41. ous of their social responsibility and contribute to the preservation of our common living space That is why Trenz Electronic invests in the protection of our Environment REACH Registration Evaluation Authorisation and Restriction of Chemicals compliance statement Trenz Electronic is a manufacturer and a distributor of electronic products It is therefore a so called downstream user in the sense of REACH The products we sup ply to you are solely non chemical products goods Moreover and under normal and reasonably foreseeable circum stances of application the goods supplied to you shall not release any substance For that Trenz Electronic is obliged to neither register nor to provide safety data sheet According to present knowledge and to best of our knowledge no SVHC Sub stances of Very High Concern on the Can didate List are contained in our products Furthermore we will immediately and un solicited inform our customers in compli ance with REACH Article 33 if any sub Trenz Electronic GmbH User Manual stance present in our goods above a con centration of 0 1 weight by weight will be classified as SVHC by the European Chemicals Agency ECHA ROHS Restriction of Hazardous Substances compliance statement Trenz Electronic GmbH herewith declares that all its products are developed manu factured and distributed RoHS compliant WEEE Waste Electrical and Electronic Equipment Informati
42. ower supply rails needed by the components on the micromodule m 1 2V 1A max m 2 5 V 1A max m 3 3 V 1A max The power rails are available for the FPGA and can be shared with a baseboard by the corresponding lines of the B2B connect ors J4 and J5 Please note that the power consumption of the FPGA is highly de pendent on the design actually loaded So please use a tool like Xilinx Xpower to determine the expected power consump tion Even if the provided voltages of the mod ule are not used on the baseboard it is re commended to bypass them to ground with 10 nF 100 nF capacitors I O Banks Power Supply The Spartan 3E architecture organizes I Os into four I O banks see Table 3 Trenz Electronic GmbH User Manual Bank Supply Min Max Voltage V V BO VccIO 1 2 3 5 B1 2 5 B2 3 3 B3 3 3 Table 3 I O banks power supply Voltage for banks B1 B2 and Ba is fixed respectively to 2 5 V 3 3 V and 3 3 V Voltage VccIO for bank BO shall span from 1 2 V to 3 3 V VccIO can be supplied either externally or internally to the micro module Externally Supplied VccIO VccIO can be externally supplied over the B2B connector J4 If bank BO is not used then VccIO can be left open Internally Supplied VccIO If VccIO is not externally supplied it can be internally supplied by one of the intern al power rails of 2 5 V and 3 3 V This is possible by short circuiting one
43. performance of this document or of any in formation contained herein Limitation of Liability In no event will Trenz Electronic its sup pliers or other third parties mentioned in this document be liable for any damages whatsoever including without limitation those resulting from lost profits lost data or business interruption arising out of the use inability to use or the results of use of this document any documents linked to this document or the materials or inform ation contained atany or all such docu ments If your use of the materials or in formation from this document results in the need for servicing repair or correction of equipment or data you assume all costs thereof Copyright Notice No part of this manual may be reproduced in any form or by any means including electronic storage and retrieval or transla 25 Spartan 3E FPGA Industrial Micromodule tion into a foreign language without prior agreement and written consent from Trenz Electronic Technology Licenses The hardware firmware software de scribed in this document are furnished un der a license and may be used modified copied only in accordance with the terms of such license Environmental protection To confront directly with the responsibility toward the environment the global com munity and eventually also oneself Such a resolution should be integral part not only of everybody s life Also enterprises shall be consci
44. procedure the following message Should pop up USB Firmware Upgrade Tool E Firmware upgrade successful Reboot the micromodule with the new firmware by disconnecting and reconnect ing the USB cable You may want to test the sample application TEO300_API_Ex ample exe in the TEO300_API_Example Debug folder To generate your own firmware upload file please read the document Generating_FWU_file doc in the USB FWUTool folder SPI Direct In System Programming ISP Make sure S2 is switched to Reset off during programming Connect the host computer to the micro module through both the SPI flying leads cable and the USB cable Start Xilinx ISE MPACT The following ex ample shows the case of iMPACT 9 2 If the IMPACT Project window pops up press the Cancel button Trenz Electronic GmbH User Manual iMPACT Project want to v Browse C Load most recent project file when iMPACT starts O create a new project ipf default ipf Browse Cancel Double click the Direct SPI Configuration option in the Modes panel http www xilinx com Right click the Direct SPI Configuration panel to add a device and select Add SPI Device EL iMPACT Direct SPI Configuration Ud Eile Edit View Opel j vi rations Options Output Ao k DGX arzi lows tasi Kula Fa Boundary Scan Right clickto Add Device or Identify Device
45. r of External Input IOBs 10 Number of External Input IBUFs 10 Number of LOCed External Input IBUFs WO OUt OE LU 100 Number of External Output IOBs 36 Number of External Output DIFFMs 1 Number of LOCed External Output DIFFMs QUE One uh 100 Number of External Output DIFFSs 1 Number of LOCed External Output DIFFSs GW Of 4 100 Number of External Output IOBs 34 Number of LOCed External Output IOBs 34 out of 34 100 Number of External Bidir IOBs 28 Number of External Bidir IOBs 28 Number of LOCed External Bidir IOBs 28 QUE 08 28 100 Number of BSCANs LOQUE Ox di 100 Number of BUFGMUXs Bs QUE GL 24 20 Number of DCMs 1 s Uft o7fT 8 12 Number of MULT18X18SIOs gt Out f 36 Number of RAMB16s 23 QUE OL 36 69 Number of Slices 6424 out of 14752 43 Number of SLICEMs LOS Out 97 737 14 Number of LOCed Slices 65 out of 6424 1 Number of LOCed SLICEMs 23 COME OE 1098 3 Overall effort level ol High Router effort level rl High
46. rnal IOBs Te QUE OL 250 29 Number of External Input IOBs 10 Number of External Input IBUFs 10 Number of LOCed External Input IBUFs WO OUt OE LU 100 Number of External Output IOBs 36 Number of External Output DIFFMs 1 Number of LOCed External Output DIFFMs QUE One uh 100 Number of External Output DIFFSs 1 Number of LOCed External Output DIFFSs GW Of 4 100 Number of External Output IOBs 34 Number of LOCed External Output IOBs 34 out of 34 100 Number of External Bidir IOBs 28 Number of External Bidir IOBs 28 Number of LOCed External Bidir IOBs 28 QUE 08 28 100 Number of BSCANs LOQUE Ox di 100 Number of BUFGMUXs Bs QUE GL 24 20 Number of DCMs Lut of 8 12 Number of MULT18X18SIOs gt out 07728 10 Number of RAMB16s 23 QUE DL 28 89 Number of Slices 6622 Out OL 8612 76 Number of SLICEMs 1008 QUE 04 4550 255 Number of LOCed Slices 65 out of 6622 1 Number of LOCed SLICEMs 13 maite GI 1038 3 Overall effort level ol High Router effort level rl High Reference Design Summary Xilinx Spartan 3E 1600 pLlatgen p xess10008f3320 4 lang vidi Ip Zar System smhs Release iso platgen lane EDE breo BULL La EDR oo FO TT GODVYLIGR E 1995 2009 Xilinx Inc ALL rights reserved Command Line platgen p xc3s1600efg320 4 lang vhdl Running post placement packing Design Summary Number of errors 0 Number of warnings 16 KOOLS UELLIZICLONS Number of Slice Flip Flops 34885 Ol OL 29 504 19 Numb
47. you uploaded the test design you should see the on board led blinking at 0 5 HZ For further information about direct pure SPI in system programming of SPI Flash memories please see Xilinx Application Note XAPP951 Configuring Xilinx FPGAs with SPI Serial Flash SPI Indirect In System Programming ISP Check the configuration switches against the following table DIP on left off right switch S1 X X S2 Run S3 PON S4 X X Connect the host computer to the micro module through both the SPI flying leads cable and the USB cable Start Xilinx ISE MPACT The following ex ample shows the case of MPACT 10 1 If the iMPACT Project window pops up press the Cancel button iMPACT Project want to v Browse C Load most recent project file when iMPACT starts O create a new project ipf default ipf Browse Cancel Double click the Boundary Scan option in the Modes panel 21 Spartan 3E FPGA Industrial Micromodule File Edit View Operations Options Output Debug Window Help ABBA NINA BO 9 W Flows x f iMPACT Pi x aa SelectMAP Desktop Configuration a Direct SPI Configuration B System CE a PROM File Formatter Welcome to iMPACT iMPACT Version 10 1 Right click the Boundary Scan to initial ize the chain and select Initialize Chain EL iMPACT Boundary Scan 6 File Edit View Operations Opt
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