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F3SP28/F3SP38

1. 2 lee gt mi o o o mi Y Zo ae 5 ge a t Add on CPUs three CPUs max L gt CPU module Subunit 1 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Slot numbers 101 to 116 gt oO oO o o o amp ge a Subunit 2 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 Slot numbers 201 to 216 mj mi mj o mi gE a Subunit 3 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 Slot numbers 301 to 316 o o o o o So 23 ge a Subunit 4 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 Slot numbers 401 to 416 o o o o o a 2g a3 ge a Subunit 5 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 Slot numbers 501 to 516 io o o o mi a 2g 23 ome ge a Subunit 6 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 Slot numbers 601 to 616 o jo jo p fo Qo 23 ge a Subunit 7 701 702 703 704 705 706 707 708 709 710 711 712 71
2. iD Figure 2 6 WideField3 F020401 VSD E Object Ladder WideField3 or WideField2 defines blocks and instruction macros that compose a ladder program as objects a term commonly used in the computing world All objects are responsible for their provided functions and have a high degree of independence Consequently the language offers higher productivity better maintainability and more effective program reuse as compared to a structured programming language E Features Componentization With componentization blocks can be reused as complete components Devices that are used within a block are defined separately from the main program Thus blocks can be easily recombined without undesirable duplicate use of the same device Macro functions can also be turned into components IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 8 Index View You can display an outline view of a large program by hiding non required details This enables more efficient debugging Material feed Initialization Idling r feeit Flux coating Finish coat Fixation heating Cleaning Cooling Flux coating Power offggrquence F020402 VSD Group Tag Names You can group individual tag names into a group tag name to enable definition of data sets swo1 swo2 SW03 SWICH POM
3. Executable program y 1 AS eer E e i Block 1 i i 10001 Y00602 i X00501 X00502 10003 i I O i I I I l l Block n y l l l X00503 10002 Y00602 l PAN wy j X00501 X00502 10004 l l TX i i 10003 i i i We E EE E E E E EE E E EEE EREET E l F060401 VSD Figure 6 3 Executing All Blocks IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 4 2 6 6 Executing Specified Blocks This mode allows you to specify selected blocks of an executable program for execution using ACT INACT instructions In this way you can control the execution of blocks which are created on per function basis in modular programming Blocks to be executed are said to be active while blocks not to be executed are said to be inactive Use an ACT instruction to activate a block and an INACT instruction to inactivate a block Whether each block is active or inactive is indicated by a special relay M given below Special relays M2001 to M3024 for blocks 1 to 1024 Note that special relays M0001 to M0032 have the same values as special relays M2001 to M2032 The special relay for a block is set to 1 when the block is active and 0 when the block is inactive Active blocks are executed in ascending order of their block numbers By default only block 1 is active Executable program Block 1 4 Block 1 ACTIVE L o1 i yYoo602
4. ccccceceeeeeeeeeeeeeeeeeeeeeeeaneeeeeeeeeeeeees 6 59 6 15 1 Schematic Operation Diagram ceceeeeeeeseeeeeeeeeeeeeeees 6 59 6 15 2 Features ccccececcecccceceeeeeeecneeeeeeeeeeseccaaeeeeeeeeeseesnsaeeaeeeeeess 6 60 6 15 3 Specifications and Restrictions ccccecceeeeseceeeeeeeetees 6 60 G 15 4 FUNCIONS wudicsdireictnesncdeceavenleauea stancedsanencdisvudlitessetnanenvidecdaavads 6 64 6 15 5 Procedures for Using Sensor Control Functions 6 69 6 15 6 Error Handling vice cissicc tnccecndiieeeee A ce iis 6 70 6 15 7 Programming Precautions 0 c ccceeseeeeeeeeeneeeeeeenteeeeeenaes 6 71 6 16 Partial Download FUNCtions cccsceeeeeceeeeeeeeeeeeeneeeeeeeeeeeeeeeneeees 6 73 6 17 Functions for Storing Comments to CPU cessscecessseeeeeeeeteeeeees 6 74 6 17 1 Performing Setup to Download Comment eee 6 74 6 17 2 Number of Steps Needed for Comment 0000ceeeees 6 75 6 17 3 Online Editing of Comment 0 ccc ceeeeeeeeeneeeeeeeenteeeeeeaes 6 76 6 18 Functions for Storing Tag Name Definitions to CPU 6 77 6 19 Structures wicciiecii aise asin 6 78 I O Response Time Based on Scan Time ccccccesseeseeeeeees 7 1 7 1 Description Of Scan Titme ccccceceesseeeee cece eee eeeeeeeeeeceeeeeseesseeneeeeeeens 7 1 IM 34M06P13 01E 4th Edition Jan 31 2012 00 7 2 Setting Scan Monitoring Time cccccessseeeceseeeeeee
5. y nth scan Block 1 Special relay Executable program Function 1 M2001 1 Block 1 INACT INACT Block 2 Function1 fo q Block 2 Special relay Function 2 M2002 1 Block 2 Function 2 esos Block m Special relay ee mo Function m M200m 1 Initialization of block 2 Block n Funcion n Block 2 Special relay Function 2 M2002 0 Next scan Executable program y n 1 th scan Block 1 INACT M Function 1 7 l Block 1 Special relay Function 1 M2001 1 Block 2 Function 2 INACT Block m l l Block n Special relay Blockm J l Function m lt Function n M200m 1 Initialization of block m Block n Function n Block m Special relay Function m M200m 0 Next scan y n 2 th scan y Block 1 Special relay Function 1 M2001 1 F060405 VSD Figure 6 7 Operation When Specified Blocks Are Inactivated IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 10 6 4 5 Devices that are used in a block which is stopped by an INACT instruction are put into the following states by block initialization Table 6 5 State at Block Inactivation Device State at Block Inactivation Timer T Resets Continuous timer Retains the value held before block inactivation Counter C Retains the value held before block inactivation Destination of F OUT instruction Goes into an OFF state al other devices Retains the states held before block inactivation Use a SET instruction for a device in a block whose output v
6. F061103 VSD Figure 6 26 Communications Protocol of Personal Computer Link Functions In personal computer link communication the maximum size of text that can be transferred each time is 512 bytes IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 30 6 11 3 Interface Description EIA RS 232 C compliant Specifications of Personal Computer Link Functions Table 6 8 Specifications of Personal Computer Link Functions Transmission mode Half duplex transmission Synchronization Start stop synchronization Transmission rate bps 9600 19200 38400 57600 115200 Data format Start bit 21 Data length Fixed at 8 bits Parity bit None or Even Stop bit 1 bit fixed Error checking Parity check Checksum Yes No Control line RS 232 C Not used Xon Xoff Not used Configurable item Transmission rate data format checksum end character and protection Protocol Proprietary protocol End character Yes No Protection function Yes No Access range Access to all control data upload download programs CPU operation Run mode stop Stop mode and read error logs Transmission distance 8 m max External connection Dedicated cable 4 The check mark Y indicates that a user can configure the item by using the configuration function However there are restrictions on the way the transmi
7. X00502 pee If mov B00001 D0001 MOV 1 B00002 X00501 X00502 Y00601 i Ik O X00503 X00504 B00002 F041001 VSD Figure 4 28 File Registers B Unlike data registers D all file registers B retain their operation results when the power is turned off A file register is cleared to OFF 0 if you write the data value OFF 0 to the file register B using the programming tool WideField3 or WideField2 Unlike data registers D file registers are not cleared to OFF 0 even if you execute a Clear Device command from WideField3 or WideField2 clear the memory from WideField3 or WideField2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 Blank Page 5 1 5 1 1 5 1 2 5 1 Programs This chapter describes languages used for programming program types and program memory Programming Language Two types of programming language are available structured ladder language and mnemonic language In either case the written program is read sequentially by the sequence CPU to perform operations according to the program s process details Structured Ladder Language The structured ladder language is based on relay symbol representation and allows a programmer to do structured programming by breaking a program into functional parts A programmer can perform programming on a function by function basis r
8. CPU 1 CPU 2 CPU 4 kooo E t t Sesia 128 points 128 points 128 points gt shared registers Locs ID Z R0129 D ae 512 points 512 points 512 points ya shared registers eee E E g R0641 D CPU 3 256 points 256 points 256 points J shared registers aa lt R0897 f 128 points 128 points 128 points a cru registers a a coco erga A A a7 Extended shared registers CPU 1 CPU 2 CPU 4 eee ee eee S R1025 41536 points 1536 points 1536 points gt SPU ee oo r L R2561 D 384 points 384 points 384 points a Srs alas EIE lt R2945 768 points 768 points 768 points gt eS aes ooo i g lt R3713 CPU 4 extended 384 points 384 points 384 points gt shared registers EEE es oe ee 7 F040705 VSD Figure 4 25 Example of Shared and Extended Shared Register R Allocation when Four Sequence CPU Modules Are Installed AN CAUTION Even if the specified range includes less than 1024 shared registers R the extended shared registers R always begin with the number R1025 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 7 3 Setting Initial Data for Data Registers D Using the configuration function define the initial values of data registers D to be used at the beginning of program execution 4 34 Specify the starting number and the number of data registers to be configured followed by the initial data values After this configuration the preset initial data values are stor
9. ec eeeeeeeeeeeeeeeeeeeneeeeetneeeeeeeaas 6 28 6 11 2 Differences from Personal Computer Link Module 6 29 6 11 3 Specifications of Personal Computer Link Functions 6 30 6 11 4 Setting Up the Personal Computer Link Functions 6 31 6 11 5 Communication Procedure eseeeeeceeeeeeeeeeeeeneeeeeeeees 6 32 6 11 6 Commands and Responses ecceseeceeeeeeeeteteeeeeeeeeeees 6 34 6 12 Device Management Functions ceccceeeeeeeeeeeeeeeeseeneeeeseeneeeeeees 6 42 6 13 Macro INStrUCtiOI issiria nsara isani anitae 6 43 6 13 1 What Are Macro Instructions c ccceeceeeeeeeeeeeeeeeeeeeees 6 43 6 13 2 Specification of Macro Instructions ceeseseeeeeeeeeees 6 46 6 13 3 Devices Dedicated to Macro Instructions 0 ceeeeee 6 47 6 13 4 Nesting Macro Instructions 0 ccs eeeeeeeeeteeeeeeetteeeeeeaes 6 50 6 13 5 Handling Macro Instruction Errors ccceeeeeeeeeeeeeteeeeeenaes 6 52 6 13 6 Protecting Macro Instructions cc ceeeeeeeeeeneeeeeeeteeeeeeneee 6 53 6 13 7 Debugging Operation ecceeceeeeeeeeeeeeeenneeeeetneeeeeneaas 6 53 6 13 8 Input Macro Instructions cccccceeeeeeeceeceeeeeeeeeeseeeeeeeees 6 54 6 13 9 Structure Macro Instructions ceceeeeeeeeceeeeeeeeeeeeeeeeeeeees 6 56 6 14 User Log Management Functions cccsssceeeeesseneeeesseeeeenseeneeenens 6 58 6 15 Sensor Control FUNCtiONS
10. Input output setup basis configurable on 16 point basis Output when stopped Reset hold external outputs Configurable on a module basis Configurable on 16 points when sequence stops Executior interval No Configurable from 200 us to 25 0ms in 100 us Sensor CB SEE Timing of interrupt No After instruction execution Immediate during instruction execution Input interrupt Timing of interrupt No always after instruction After instruction execution execution Immediate during instruction execution Priority of interrupts No Sensor CB interrupt has priority input interrupt has priority Peripheral processing time No Configurable from 100 us to 190 ms in 100us increments Run Stop configurable for shared relays E aes ee oh d No shared registers R extended shared relays Shared refreshing inter CPU module communications method refreshing E and extended shared registers R of each CPU module Simultaneity of shared refreshed data No No simultaneity in all cases Yes No Shared refreshing mode Peripheral process defined as control related No Control process process P rec ata refreshing No Peripheral process Control process EEE Common data refreshing No All nodes Some nodes range Note Sensor CB Sensor control block A CAUTION For F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 you can determine by configuration Yes N
11. Model Device No Signal Name Drawing No Description Device No Appx 3 2 Sheet No Signal Name Description olojn Iaa BR w O O MDINIDI ATR wld 2 3 4 5 6 7 8 9 0 CO Ol WMWINIDI aA R w ry OlO OI INI OD a AJOJN ojlo loin Iaoa A JN AJOJN IM 34M06P13 01E 4th Edition Jan 31 2012 00 E Register Devices Assignment Table System Name Model Device No Signal Name Drawing No Description Device No Appx 3 3 Sheet No Approved Checked Prepared Signal Name Description IM 34MO06P13 01E 4th Edition Jan 31 2012 00 E Timer Counter Setpoints Table System Name Model Device No Setpoint Drawing No Signal Name Appx 3 4 Sheet No Approved Checked Prepared Description O 1 O MOINI OI a AJOJN 2 3 4 5 6 7 8 9 0 olol MOI NI OD oa BR wy hd IM 34MO06P13 01E 4th Edition Jan 31 2012 00 FA M3 Index 1 Sequence CPU Instruction Manual Functions for F3SP22 0S F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S Index A ACTIINAGT fain citation aioe 6 6 B
12. T 2 0xN4 T 0 8xN4 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 8 E Examples of Calculation Some examples for calculating the instruction execution time are given below For information on the execution time of an MOV instruction see Appendix 3 List of Ladder Sequence Instructions of Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E 1 Differential Type Instructions fi Mov Dooo1 Dooo2 0 18 0 18 0 36 us for F3SP22 F3SP28 and F3SP38 sequence CPUs 0 07 0 07 0 14 us for F3SP53 F3SP58 and F3SP59 sequence CPUs 2 Relays BIN Format Use parenthesized execution time value from the List of Ladder Sequence Instructions if any mov 10002 D0001 Number of relay devices N1 1 3 2 2 5 5 7 us for F3SP22 F3SP28 and F3SP38 sequence CPUs 1 2 1 0 2 2 us for F3SP53 F3SP58 and F3SP59 sequence CPUs 3 I O Relays X Y Defined in BCD Format Use parenthesized execution time value from the List of Ladder Sequence Instructions if any Number of relay device defined in BCD format N2 1 3 2 3 5 6 7us for F3SP22 F3SP28 and F3SP38 sequence CPUs 1 2 1 4 2 6us for F3SP53 F3SP58 and F3SP59 sequence CPUs MOV D0001 Y00301 4 Index Modification 1 Basic Instructions an O Number of index modified 1 relay devices N3 1 0 09 1 0 1 09 us for F3SP22 F3SP28 and F3SP38 sequence CPUs 0 035 0 4 0
13. cccscccssssceeessssneeessseeeeeessseeeenees 2 4 2 3 1 Remote I O System 0 ecceeeceeeeeeeeeeeeeeeetneeeeeeneeeeeeneeeeeeeaas 2 4 2 3 2 Personal Computer Link System ce ceeeeeeeeeeeeeenteeeeeeaes 2 5 233 FA Link Systemes ca vd ean 2 5 2 3 4 FL net System aaausseeeseeeerresrrrreersrrssennnentinnasttnnearinnaaennneaeana 2 6 2 4 Programming Tool cccceceeeeeseeeceeeeeeeeeeesseeeeeseeeeneeeeseeeeeseeeseeeeeseeaees 2 7 2 4 1 WideField3 WideField2 ccccccceeeceeseeeeeeeeeseteeeeneeeeenees 2 7 3 Basic Operations of Sequence CPU Module ccccccceeeeees 3 1 3 1 Operating Modes of Sequence CPU Module ccccssssseeseereee 3 1 3 2 Operation at Power On Off c c sceeceeeeeeeeeseeeeeeeeeeeeseneeaneeseeeeeeeeeees 3 2 3 2 1 Operation at POWer ON ccccceceeeeecenceeeceeeeeeesetsenieeeeeeeess 3 2 3 2 2 Operation at Power off c ccccccceeeeeesecceceeeeeeeeseseeneeaeeeeees 3 2 3 3 Operation in Case of Momentary or Complete Power Failure 3 3 IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 3 1 Operation in Case of Momentary Power Failure 0 3 3 3 3 2 Momentary Power Failure Detection Mode Setup 3 4 3 3 3 Operation in Case of Complete Power Failure 3 4 3 3 4 Data Latch Range at Power Failure eeseeeeeteeeeeeenees 3 4 3 4 Operation Processing Method cccccssseeecssseeeeeseeee
14. F3SP25 F3SP35 8192 max including remote I O points 4096 max F3SP22 0S F3SP28 3S F3SP53 4S F3SP28 3N F3SP53 4H 4096 max including remote I O points F3SP38 6N F3SP38 6S F3SP58 6H F3SP58 6S 8192 max including remote I O points F3SP59 7S 8192 max including remote I O points Number of internal relays 1 8192 16384 16384 32768 65535 Number of link relays L 8192 8192 8192 16384 16384 Number of timers T 1024 2048 1024 2048 2048 Number of data registers D 8192 8192 16384 32768 65535 Number of file registers B 32768 32768 32768 262144 262144 Number of link registers W 8192 8192 8192 16384 16384 Program size 20K steps max 100K steps max 10K steps max F3SP22 30K steps max F3SP28 56K steps max F3SP53 120K steps max 254K steps max Number of program blocks 128 max 1024 max 1024 max 1024 max 1024 max Number of program macros 128 max 64 max 64 max 256 max 64 max 256 max 256 max Number of basis instructions 25 25 33 33 33 Number of application instructions 307 307 312 328 312 328 328 Other functions Sensor control functions Specification Sensor control functions Sensor control functions Basic instruction Instruction execution F3SP25 F3SP35
15. Special registers have specific functions such as indicating the internal state of a Appendix 2 1 Sequence Operation Status Table Appendix 2 1 Sequence Operation Status Registers Sequence Operation Status Registers Scan Time Run mode Function Latest scan time Description Stores the latest scan time in 100 us increments Minimum Scan time Run mode Minimum scan time Allows the latest scan time to be read in 100 us increments if it is shorter than the minimum scan time Maximum Scan Time Run mode Maximum scan time Allows the latest scan time to be read in 100 us increments if it is longer than the maximum scan time Scan Time Debug mode Latest scan time Stores the latest scan time in 100 us increments Minimum Scan Time Debug mode Minimum scan time Allows the latest scan time to be read in 100 us increments if it is shorter than the minimum scan time Maximum Scan Time Debug mode Maximum scan time Allows the latest scan time to be read in 100 us increments if it is longer than the maximum scan time Peripheral process Scan Time Latest scan time Stores the latest scan time in 100 us increments Tolerance Scan time of one control process Minimum Peripheral process Scan Time Minimum scan time Allows the latest scan time to be read in 100 us increments if it is shorter than the minimum scan time Tolerance Scan time of one co
16. 2 The CPU module can be configured to stop or continue execution of the program for this error event 3 When a major failure occurs with RDY off an incorrect power off time is recorded in the system log If a power off and an SPU error 1104 are recorded simultaneously it means that the RDY has turned off due to an SPU error Restrictions on module installation may have been violated Check the modules according to Section A1 2 Restrictions on Module Installation of the Hardware Manual IM 34M06C11 01E The ROM pack whose data has been erased is not defective Use it as is Data may have been written to the ROM pack under a wrong sequence CPU type Try writing to the ROM pack again The ROM pack or sequence CPU module may be defective if the same failure recurs Replace the ROM pack or the sequence CPU module Try writing to the ROM pack again The ROM pack or CPU module may be defective if the same failure recurs Replace the ROM pack or CPU module The error may be due to a transient memory failure caused by effects of noise Check the installation environment The module restarts with its factory settings when it is powered on after this error is detected Download the program again If the same failure recurs replace the module Check if there is a jump out of or into the subroutine Check if a scan timeout has been detected within the subroutine Check the depth of nesting when ca
17. F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 0 12 to 0 24 us per instruction 0 09 to 0 18 us per instruction 0 045 to 0 18 us per instruction 0 0175 to 0 07 us per instruction time Application instruction 0 24 us min per instruction 0 18 us min per instruction 0 18 us min per instruction 0 07 us min per instruction IM 34MO06P13 01E 4th Edition Jan 31 2012 00 TIP 9 2 To gain access to file register B using a personal computer link command refer to the conventions given below Module Personal computer link F3LC11 1N F3LC11 2N Restriction Convention Accessible file registers are B1 to B99999 Personal computer link F3LC11 1F F3LC12 1F Ethernet interface CPU personal computer link functions The device name of file registers B must be seven bytes long To gain access to the sensor control block using personal computer link module refer to the conventions given below Module Personal computer link F3LC11 1N F3LC11 2N Restriction Convention Asensor control block number is determined by adding 1 to the end of a number assigned to regular blocks You cannot access the blocks numbered from 100 to 1024 Personal computer link F3LC11 1F F3LC12 1F Asensor control block number is determined by adding 1 to the end of a number assigned to regular blocks Ethernet interface
18. Figure 6 24 Personal Computer Link Functions IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 28 6 11 1 System Configuration The figure below shows examples of system configuration using the personal computer link functions External equipment such as a personal computer or monitor is connected to the sequence CPU module of the FA M3 by using the programming tool connector on the front of the FA M3 and a dedicated programming tool cable Personal computer Monitor Programming tool cable Programming tool cable FA M3 FA M3 L Sequence CPU module L Sequence CPU module F061102 VSD Figure 6 25 Examples of Connection between a Sequence CPU Module and External Equipment Provide the programming tool cable with a ferrite core if you want to have the connected device compatible with the CE marking Manufacturer Product Series Name Kitagawa Industries K K RFC series eae a TDK Corporation ZCAT series NEC TOKIN Corporation ESD SR series IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 29 6 11 2 Differences from Personal Computer Link Module This subsection describes the differences between the F3LC10 1F personal computer link module and the personal computer link functions of the sequence CPU module E Function The transmission rate and data format of the CPU s personal computer link functions differ from those of the person
19. Fixed interval timing CBACT The sensor control block SCB is one block which is executed at high speed and at Block 1 fixed intervals separately from the normal scan p v 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 l 1 1 1 i 1 gt i 1 1 Block n F050208 VSD Figure 5 10 How the Sensor Control Block Is Executed 4th Edition Jan 31 2012 00 IM 34M06P13 01E 5 9 5 3 Program Memory The program memory contains programs as well as information required for program execution and management This section describes the structure of the program memory and its initial state with no program Table 5 1 Structure of Program Memory and Its Initial State Component Program management table Description An area for storing information required for managing all programs including program name step count and block management information Initial State In the initial state the program name is PROGRAM the block name is PROGRAM and the number of steps is zero Program An area for storing programs Contains a NOP instruction Configuration table An area for storing configuration information such as device capacities and operation methods Contains the initial values discussed in Subsection 1 2 3 Configuration I O
20. Macro instruction functions Available These functions allow the user to create and register new user defined instructions Scan monitoring time Variable from 10 to 200 ms Startup at power on or recovery from power failure Automatic Auto logging of power on time power off time and momentary power failure time Sensor control functions Available In addition to normal scanning these functions allow one specified block to be scanned at high speed fixed intervals Constant scan time 1 to 190 ms configurable in 0 1 ms increments Self diagnosis Detection of memory failure CPU failure and I O module failure syntax checking etc Link functions FA link FL net personal computer link and remote I O link fiber optic FA bus y bus Comment storage functions Available Circuit comment sub comment tag name definition including I O comment Other functions Online editing Forced SET RESET instructions Clock year month day hour minute second and day of the week Configuration setup of parameters including device capacities range of devices to be latched at power failure and external outputs to be latched at sequence stop Protection Stop refreshing function IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 5 Table 1 3 Functional Specification F3SPOO ON F3SPOO Oh Control method Specifications F3SP28 3N Repeated operation based on stored pr
21. Personal computer link ba Sequence CPU module Figure 6 17 Exclusive Access Control F060901 VSD Once a user acquires exclusive access control the system prohibits other tools or modules having no exclusive access control to perform the following operations Running or stopping a program debugging downloading debug operation use of debugging functions writing to devices and changing setpoints of timers T counters C IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 24 6 10 Sampling Trace Functions This section describes the sampling trace functions which records state transitions of specified devices The sampling trace functions store the states and contents of devices selected to be sampled sequentially in the sampling trace memory of the sequence CPU module Three sampling methods are available TRC instruction sampling End of Scan Sampling Periodic sampling You can define the trigger condition for sampling as the rising edge of a specified relay signal the falling edge of a specified relay signal or data coincidence with a selected register device The CPU monitors the trigger condition during scan end processing If the trigger condition becomes true the CPU takes 1024 samples starting from a specified negative delay before or a specified positive delay after the condition becomes true Using WideField3 or WideField2 you can configure the sa
22. 1 11 1 2 4 Components and Their Functions This section describes the LED indicators their states and the programming tool connector on the front side of the sequence CPU module These features are common to the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 CPU modules F3SP22 0S F3SP53 4H F3SP28 3N F3SP58 6H F3SP38 6N F3SP53 4S F3SP28 3S F3SP58 6S F3SP38 6S F3SP59 7S RDY RUN R j lt CPU module operation status LED indicators mr RDY READY green On Normal Off Major failure RUN RUN green On Program in progress Off Program at a stop ALM ALARM yellow On Minor failure Off Normal ERR ERROR red On Moderate failure Off Normal PROGRAMMER Major failure The CPU module is inoperable due to a hardware failure Moderate failure The CPU module cannot run or continue to run a program Minor failure The CPU module still can run or continue to run a program though it has detected a failure Programming tool connector Connected to a personal computer or handy programming console A personal computer or a monitor can be connected to this connector when the personal computer link function is in use F010201 VSD The table below summarizes combinations of the LED indicators as classified by the severity of failure T
23. Executes the program Stops the program Indicates whether sequence program of CPU in slot 2 is running CPU3 Sequence Program Execution Executes the program Stops the program Indicates whether sequence program of CPU in slot 3 is running CPU4 Sequence Program Execution Executes the program Stops the program Indicates whether sequence program of CPU in slot 4 is running For F3SP21 F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 and F3SP58 only SEE ALSO For details on the M210 Subunit Communication Error and M211 Subunit Transmitter Switching Has Occurred self diagnosis relays see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34MO6P13 01E 4th Edition Jan 31 2012 00 Appx 1 5 Appendix 1 5 FA Link Module Status Relays FA Link module status relays indicate the status of FA link SEE ALSO For details on FA link module status relays see the sections on special relays and special registers of FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E Table Appendix 1 5 FA Link Module Status Relays FA Link Module Status Relays No Name Function Description M257 to M480 M8321 to M8992 FA Link Error ON Error Indicates the status of FA OFF Normal links Appendix 1 6 FL net Interface Module Status FL net interface module status relays indicate the status of FL
24. F3SP22 F3SP53 F3SP28 F3SP58 F3SP38 F3SP59 When When Not When Executed Executed Executed Macro Call When Not Executed Parameter Macro Return Input Macro Instruction Call Output of Input Macro Structure Macro Instruction Call E Online Editing of Macro Instructions You can use the online edit functions of WideField3 or WideField2 to edit circuits containing macro instruction calls or input macro instruction calls However you can only use macro instructions that are already downloaded and cannot create any new macro instruction Circuits containing structure macro instruction calls cannot be edited online You can also use the online edit functions to edit macro instruction entities already downloaded but you cannot edit any circuits following the Macro Return MRET instruction E Making Macro Instructions Resident in ROM You can make macro instructions resident in a ROM pack just like programs This is automatically done when you transfer a program to the ROM pack using the ROM writer function of the CPU module IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 47 6 13 3 Devices Dedicated to Macro Instructions Table 6 17 Devices Dedicated to Macro Instructions Number of Device Devices Pointer register P P01 to P16 Macro relay H H0001 to H0512 Macro register A A0001 to A0512 Macro index register U U01 to U16 Structure pointer regi
25. Gives information that complements the present topic SEE ALSO Indicates a SEE ALSO reference Identifies a source to which to refer For the protection and safe use of the product and the system controlled by it be sure to follow the instructions and precautions on safety stated in this manual whenever handling the product Take special note that if you handle the product in a manner other than prescribed in these instructions the protection feature of the product may be damaged or impaired In such cases Yokogawa cannot guarantee the quality performance function and safety of the product When installing protection and or safety circuits such as lightning protection devices and equipment for the product and control system as well as designing or installing separate protection and or safety circuits for fool proof design and fail safe design of processes and lines using the product and the system controlled by it the user should implement it using devices and equipment additional to this product If component parts or consumable are to be replaced be sure to use parts specified by the company This product is not designed or manufactured to be used in critical applications which directly affect or threaten human lives and safety such as nuclear power equipment devices using radioactivity railway facilities aviation equipment shipboard equipment aviation facilities or medical equipment If so used it is the user s
26. Indicates that link refreshing has stopped M177 to M187 Devices Reserved for Extended Functions M188 Carry Flag Carry enabled Carry disabled Carry flag used by shift and rotate operations M189 to M192 For F3SP21 F3SP22 F3SP25 F3SP28 F3SP35 SEE ALSO Devices Reserved for Extended Functions F3SP38 F3SP53 and F3SP58 only For details on clock setup see the specifications of special registers Z for clock data IM 34MO6P13 01E 4th Edition Jan 31 2012 00 Appx 1 4 Appendix 1 4 Self diagnosis Status Relays Self diagnosis status relays indicate the results of self diagnosis by the sequence CPU Table Appendix 1 4 Self diagnosis Status Relays Self diagnosis Status Relays Self diagnosis Error Function Error No error Description Result of self diagnosis is stored in special registers Z17 to Z19 Battery Error Error Normal Indicates a failure in backup batteries Momentary Power Failure Momentary power failure No momentary power failure Indicates that a momentary power failure has occurred Inter CPU Communication Error Error Normal Indicates that a communication failure has occurred in shared relays E or shared registers R Existence of CPU1 Exists Does not exist Indicates whether or not a CPU exists in slot 1 Existence of CPU2 Exists Does not exist Indicat
27. Scan Sampling In scan sampling the CPU samples the states and data of specified contacts at the end of a scan It collects and stores the data each time the specified number of scans are completed END END END END I l l i Sampling Sampling F061003 VSD Figure 6 20 Scan Sampling at Two scan Intervals Periodic Sampling In periodic sampling the CPU samples the states and data of specified contacts at fixed time intervals It collects and stores the data after the specified period expires and before the next scan begins Specified period gt OY END END END END l Sampling Sampling F061004 VSD Figure 6 21 Periodic Sampling IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 26 AN CAUTION The sampling trace functions check the trigger condition when an END processing in a program is performed Therefore if the trigger condition becomes true during program execution but becomes false again before processing of the END processing begins sampling is not performed Sampling when a Negative Delay Is Defined Negative delay Trigger condition is established End of tracing Start of tracing A 7 y p 1024 sampled points are stored in the sampling trace memory F061005 VSD Figure 6 22 Sampling when a Negative Delay Is Defined Sampling when a Positive Delay Is Defined Trigger condition is Positive delay established End of tracing Start of tracing J pp Figure 6 23 Sampling
28. X00503 F040101 VSD Figure 4 1 Input Relays X IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 2 4 1 2 4 1 3 Output Relays Y Output relays are used to output the results of program based control to external equipment such as actuators In programs you can use these relays for example for contacts a and b coils and application instructions Output relay numbers are represented as Y Lmmnn where Lmm Slot number L Unit number 0 to 7 mm Slot position 01 to 16 nn Terminal number 1 to 64 X00502 Y00602 O X00501 X00502 Y00601 O Ps Output to X00503 X00504 Y00603 M external H O equipment X00501 X00502 Y00604 ji O X00503 F040102 VSD Figure 4 2 Output Relays Y Allocation of I O Addresses There is no need to allocate I O address through WideField3 or WideField2 I O relay numbers are determined by the position of the slot where an I O module is installed They are fixed discontinuous numbers and assigned on 64 relay basis for each slot An empty slot is regarded as being equivalent to 64 relays 1 2 3 4 1 2 3 4 T T T i i i ela eae emt AN Empty A Er Empty Empty 1 Empty P 3 3 3 pesee 1 slot 1 slot slot Us 2 2 2 Empty slot 32 32 32 32 32 32 64 relays relays relays relays relays relays relays Relay numbers X00201 to X00232 T S
29. table table Program Tag name definition table ROM Configuration table area I I O configuration table l Program control instruction table I I Timer counter setpoint table i i i Utility Pa AS F060801 VSD Figure 6 15 Contents of Program to Be Made Resident in ROM IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 20 Compatibility of a Sequence CPU Module with ROM Pack Data Written by another Sequence CPU Module For F3SP28 3S F3SP38 6S F3SP53 4S and F3SP58 6S of Rev 7 or Seep na F3SP28 3N F3SP38 6N F3SP53 4H F3SP58 6H and 59 7 These sequence CPU modules can only execute programs written to ROM packs using the same CPU type as shown in the table below Example The F3SP28 3N can only execute programs on ROM packs written using F3SP28 3N Thus a ROM pack written by F3SP28 3S may not be installed and used with F3SP28 3N Table 6 6 1 Compatibility of a CPU with ROM Pack Data Written by another CPU 1 2 CPU Compatible with CPU Used to Written ROM Pack Data Write Program Data to ROM Pack F3SP28 3N F3SP28 3N F3SP28 3S Rev 7 or earlier F3SP28 3S F3SP38 6N F3SP38 6N F3SP38 6S Rev 7 or earlier F3SP38 6S F3SP53 4H F3SP53 4H F3SP53 45S Rev 7 or earlier F3SP53 4S F3SP58 6H F3SP58 6H F3SP58 6S Rev 7 or earlier F3SP58 6S F3SP59 7S F3SP59 7S For F3SP28 3S F3SP38 6S F3SP53 4S and F3SP58 6S of Rev 8 or later These sequence CPU modules c
30. 0 to FFFF hexadecimal number 0 to FFFFFFFF hexadecimal number Character string constant 16 bit instruction 32 bit instruction e g AB etc e g ABCD etc Floating point constant 32 bit instruction eg 1 23 3 21 approximately 3 4x1038 to 3 4x1038 Program size that can be ROM resident 30K steps max 56K steps max 120K steps max Number of program blocks 1024 max Number of Basic instructions 33 instructions Application instructions 312 Number of macro instructions 64 max F Basic instruction Instruction 0 045 to 0 18 us per instruction 0 0175 to 0 07 us per instruction 0 045 to 0 18 us per instruction 0 0175 to 0 07 us per instruction execution time KO EE Application instruction 0 18 us min per instruction 0 07 us min per instruction 0 18 us min per instruction 0 07 us min per instruction Special module High speed Read instruction HRD special module High speed Write instruction HWR 64 instructions each Sampling trace functions Support for personal computer link functions by programming tool connection port User logging functions Available This function collects and displays the states of multiple devices for a maximum of 1024 scans Available The function allows a personal computer or a monitor to be connected to the programming tool connection port to pe
31. 262144 Non W00001 to W00001 to W00001 to Used in FA link and Link register latched W_ W72048 8192 W72048 16384 W72048 16384 FL net type discontinuous discontinuous discontinuous communications Special register Z Z0001 to 21024 1024 Z0001 to Z1024 1024 Z0001 to 21024 1024 Index register V V001 to V256 256 V001 to V256 256 V001 to V256 256 These devices default Shared register R0001 to R1024 1024 R0001 to R1024 1024 R0001 to R1024 1024 Ito zero in quantity Be Non sure to configure the latched R devices when using Extended type the CPU module in a shared register R1025 to R4096 3072 R1025 to R4096 3072 R1025 to R4096 3072 multi CPU configuration 1 See Table 1 5 Table 1 5 Device Capacities and Configuration Restrictions F3SP22 0S F3SP28 3N 3S F3SP53 4H 4S F3SP38 6N 6S F3SP58 6H 6S F3SP59 7S Default value Setup Restrictions Total for timers and counters 2048 max Default value for 100 ys and 1 ms timers 0 Default Default value Setup Restrictions Total for timers and counters 3072 max Default value for 100 ys and 1 ms timers 0 Setup Restrictions value Total for timers and counters 3072 max Default value for 100 s and 1 ms timers 0 2048 max 2048 max 2048 max Extended Shared relay 2048 max 2048 max 2048 max Shared register 1024 max 1024 max 1024 max Extended shared regist
32. Bmov R0001 Do001 D0100 X00501 X00504 E Eee l H BM V R0001 D0001 10 foe Make sure the range does not exceed the range set for the own CPU F040704 VSD Figure 4 24 Precautions when Using Shared or Extended Shared Registers R 2 of 2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 32 AN CAUTION 3 Simultaneity of data Using the configuration function you can select either Simultaneous or Non simultaneous for simultaneity of data of shared devices If you select the Simultaneous option simultaneity of data is guaranteed for units of devices shared relays E registers or extended shared relays E registers to be refreshed where one of the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 sequence CPU modules is combined with any one or more of these CPUs installed as add on CPU modules Simultaneity of data between shared relays E registers and extended shared relays E registers is not guaranteed however If any of the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 CPUs is combined with any of the F3SP21 F3SP25 and F3SP35 sequence CPU modules simultaneity of shared refreshed data cannot be guaranteed regardless of the configuration setting The Non simultaneous option is provided for compatibility with the F3SP21 F3SP25 and F3SP35 CPUs Select this option when these CPUs are replaced with the F3SP22 F3SP28 F3SP38 F3SP53 F3SP5
33. FA Link Z080 Z081 Z082 Local station number Local station number Local station number Local station status 0 Initialization in progress 1 Offline 2 Online System 6 FA Link System 7 FA Link System 8 FA Link System 1 FA Link Cyclic transmission time System 1 FA Link 1ms increments Local station status Initialization in progress Offline Online System 2 FA Link Cyclic transmission time System 2 FA Link ims increments Local station status Initialization in progress Offline Online System 3 FA Link Cyclic transmission time System 3 FA Link ims increments Local station status Cyclic transmission time Initialization in progress Offline Online System 4 FA Link System 4 FA Link ims increments Local station status Initialization in progress Offline Online System 5 FA Link Cyclic transmission time System 5 FA Link ims increments Local station status Initialization in progress Offline Online System 6 FA Link Cyclic transmission time System 6 FA Link ims increments Local station status Initialization in progress Offline Online System 7 FA Link Cyclic transmission time System 7 FA Link ims increments Local station status Initialization in progress Offline Online System 8 FA Link SEE ALSO For details on the FA link m
34. Functions for information on user logs Sensor CB Execution Time Time taken from starting of input refreshing for the sensor control block through program execution to completion of output refreshing Unit 10 us Maximum Sensor CB Execution Time The maximum time taken to execute the sensor control block Unit 10 us Model Information CPU model name and revision number of firmware 1 Only for F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 2 F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 For example module F3SP58 6S with firmware Rev1 Z121 Z122 Z123 Z124 Z125 Z126 01 Z127 Z128 den ane igi api F3SP05 F3SP08 F3SP21 F3SP25 F3SP35 For example module F3SP21 0N with firmware Rev 14 Z121 Z122 Z123 Z124 Z125 A Z126 14 Z127 Z128 a ap ve aah IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Blank Page Appx 3 1 Appendix 3 Forms for System Design E Program Coding Sheet System Name Model Instruction No Instruction Operand Sheet No Approved Checked Prepared Remarks O O MOINI DO oO BR wy hr 2 3 4 5 6 7 8 9 0 olojo NIJA AJOJN IM 34M06P13 01E 4th Edition Jan 31 2012 00 E Relay Devices Assignment Table System Name
35. IM 34MO6P12 03E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 44 E Purpose Using macro instructions offers the following two advantages Increased Programming Efficiency Like subroutines macro instructions allow grouping of similar processing Macro instructions differ from subroutines however on the following two points Parameters can be passed to macro instructions Subroutines require the use of instructions for passing parameters e g MOV instructions preceding a CALL instruction Macros can be handled as instructions A user need not be aware of the internal processing of a macro except for its input and output parameters Reuse of Use of macro subroutines instruction Reuse No Any usable subroutine macro Yes Yes Search for Create Check Create reusable subroutine a new subroutine its specifications a new instruction Find its I O Enter instruction lt y List the devices END used internally Copy subroutine see notes Note 1 Copy the block containing the subroutine under a different name 2 Delete all components other than the subroutine from the circuit diagram of the copied block Match I Os with 3 Using ladder diagram editing read the copied block devices used internally lt END F061303 VSD Figure 6 35 Differences between Subroutines and Macr
36. Partial Download Functions The partial download functions allow only specified blocks macros to be downloaded to a CPU to replace corresponding blocks macros of a program that has been downloaded earlier This reduces downloading time and improves debugging efficiency especially in large scale program development by a group of developers These functions are available only in STOP mode It allows multiple blocks or macro instructions to be specified for downloading Addition or deletion of block macro instructions by partial downloading is not allowed 6 16 Personal computer Downloading only blocks 2 and 4 from personal computer to CPU and hence replacing only blocks 2 Executable and 4 in the CPU program Block 1 Block 1 Function 1 Function 1 Block 2 JS Block 2 Function 2 Function 2 Block 3 Function 3 Block 3 Function 3 Block 4 Block 4 gt Function 4 Function 4 F061601 VSD Figure 6 47 Partial Download Functions eey erh 1 cri Caer Programmer A Programmer B Programmer A partially downloads block 4 _ 7 and debugs it Executable len gi Programmer B partially downloads block 2 program a and debugs it la Block 1 Block 1 Function 1 Function 1 Block 2 4 L gt Block 2 Function 2 Function 2 Block 3 Function 3 Block 3 Function 3 Eee oS Bocka Function 4 Functi
37. This section describes how to make programs resident in ROM setting initial values of devices to be resident in ROM as well as ROM management writer functions and ROM writer mode Making Programs Resident in ROM Programs that have been debugged and tuned can be made resident in the ROM pack To make a program resident in the ROM pack transfer the program to the ROM pack using the ROM writer functions of the sequence CPU module The items to be made resident in the ROM pack are programs themselves as well as program management information configuration information control tables timer T counter C setpoint tables and comment information All information required by the CPU to start program execution at power on is made resident in the ROM pack The maximum limits on program steps that can be stored on various ROM packs depend on whether only programs are stored in the ROM pack or tag name definitions are stored along with programs as shown in the table below Table 6 6 Limitations on Selection of ROM pack Program Sequence CPU Module Storage Program Tag Name Definition RK33 0N F3SP28 3N RK73 0N 30K steps RK33 0N No tag name definition F3SP53 4H RK73 0N 56K steps ean baciored F3SP38 6N RK33 0N 56K steps F3SP58 6H RK73 0N 120K steps RK33 0N 56K steps F3SP22 0S RK73 0N 10K steps 120K steps 2 RK33 0N 56K steps F3SP28 3S RK73 0N 30K steps 120K
38. Tool service Link service CPU service Synchronization processing F030905 VSD Figure 3 15 Executing Shared Refreshing as a Control related Process If you execute shared refreshing as a control related process the scan time lengthens However this ensures that shared refreshing is not affected by link refreshing or the command processing time IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 17 TIP Sequence of Shared Refreshing For a main CPU shared refreshing is executed in the order of CPU2 s shared relays E registers R CPU2 s extended shared relays E registers R CPU3 s shared relays E registers R CPU3 s extended shared relays E registers R CPU4 s shared relays E registers R and CPU4 s extended shared relays E registers R When the configuration item Shared Refreshing Execution is set to Peripheral Process Each single scan of peripheral processing refreshes CPU N s shared relays E registers R or extended shared relays E registers R The data that has been read is reflected in device areas during the synchronization process occurring after the completion of shared refreshing Note however that if the configuration item Shared Refreshing Data is set to Simultaneous refreshing may be delayed by as much as three scans of peripheral processing due to the need for synchronization with the CPU N When the configuration item Shared
39. and Extended Shared relays E are 1 bit variables that can be used to perform data communications between CPUs in a multi CPU system Internal Relays I Internal relays are auxiliary relays available for use in programs In programs you can use these relays for example for contacts a and b coils and application instructions Unlike I O relays X Y however these relays cannot directly exchange signals with external equipment There is no limit on the number of contacts a and b that can be used in a program n or le X00502 X00501 F040201 VSD Figure 4 4 Internal Relays I Using the configuration function you can define the data latch range at power failure for devices whose operation results are to be latched when power is turned off Anon latched device will be cleared to OFF 0 when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Device command from WideField3 or WideField2 A latched device retains its operation result even after power off and power on and is cleared to OFF 0 when you execute a Clear Device command from WideField3 or WideField2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 2 2 4 7 Shared Relays E and Extended Shared Relays E Shared and extended shared relays are used to perform communications between CPU modules in cases where a sequence CP
40. instead Passing Parameters to an Input Macro Instruction Use the pointer register P to pass parameters to an input macro instruction the same way as with ordinary macro instructions Up to three parameters can be directly coded in an NCALL instruction To pass more than three parameters use the Parameter PARA instruction Be careful when using the PARA instruction because it can be used by both macro and input macro instructions SEE ALSO For details on pointer registers P see Section 6 13 3 Devices Dedicated to Macro Instructions IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 55 Output of Logical Operation Result to the Power Rail The NMOUT instruction is used to specify the logical operation result of an input macro instruction The logical operation result to be output to the step following the Input Macro Instruction Call instruction depends on the status of the input parameter type of the NMOUT instruction Logical Operation Output of Input Macro device status output Constant OFF if 0 ON if otherwise Input Parameter Relay device OFF if 0 ON If 1 Register device OFF if 0 ON if otherwise If the NMOUT instruction is executed more than once the last instruction takes precedence If no NMOUT instruction is executed the logical operation result of an input macro is OFF SEE ALSO For details on the NMOUT instruction see Sequence CPU Instruction Manual Instructions
41. 0 basis N for all links combined 100 us timer 0 1 ms timer 0 2048 points on 1 point basis for 10 ms timer 512 timers and counters combined 16 Configuration of Timer T 100 ms timer 448 max for 100 us timers Timer Counter C 100 ms continuous 128 numbers are continuous timer Counter 1024 Shared Device E R Device Link Device L W capacities Link register W 2048 points on 1 point basis for timers and counters combined IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 8 Table 1 7 Configuration Range 2 5 F3SP38 6N F3SP38 6S F3SP58 6H F3SP58 6S F3SP59 7S Item Default Configuration Range 2048 points max on 32 point basis for all Shared relay E CPUs combined 2048 points max on 32 point basis for all CPUs combined 1024 points max on 2 point basis for all CPUs combined 3072 points max on 2 point basis for all CPUs combined Device Link relay L 2048 for each 16384 points max on 16 point basisote for capacities Link Device L W system all links combined Li f 2048 for each 16384 points max on 16 point basis Not for ink register W system all links combined 100 us timer 0 1 ms timer 0 3072 points on 1 point basis for timers and 10 ms timer 1024 counters combined 16 points max for 100 100 ms timer 896 Us timers timer numbers are continuous 100 ms continuous timer 128 1024 3072 points on 1 point basis for timers and coun
42. 01E 4th Edition Jan 31 2012 00 6 23 Exclusive Access Control This section describes exclusive access control a function for restricting operations on program operating mode or device data by other users during operation or debugging Exclusive access control is used to prevent a program operating mode or device data from being changed or a program or device data from being downloaded by other users say during operation or debugging Once you acquire an exclusive access control all modification and control related commands issued from other tools sequence CPU modules or personal computer links are rejected until you release the control While you hold the exclusive access control all modification and control related commands from other users remain disabled so you should release the access control as soon as you have completed the required processing If another user has already acquired an exclusive access control it is not available to you The following exclusive access control functions are provided Get exclusive access control This function acquires exclusive access control Release This function releases exclusive access control Forced Release This function allows a tool or module that has no exclusive access control to force holder of the exclusive access control to release it Personal computer Prohibition of access Acquisition of exclusive access control
43. 01E 4th Edition Jan 31 2012 00 6 8 2 6 8 3 6 21 Defining Current Values of Devices to Be Made Resident in ROM Define initial values to be made resident in data registers D or file registers B when program execution begins The data items to be defined are the type of device starting number and quantity of devices This configuration enables the current values of the specified devices to be stored in the ROM pack when the file to ROM transfer or CPU to ROM transfer ROM copy function of the ROM writer functions is executed You can determine whether or not to update the device data to be made resident in ROM with the current values when executing the file to ROM transfer or CPU to ROM transfer function When program execution begins the device data in the ROM pack is read and stored in the specified devices This configuration is useful when you want to set a large volume of initial data or save initial data for a program You can set initial values in a maximum of 32768 devices ROM Writer Functions and ROM Writer Mode ROM writer The sequence CPU module or an add on CPU module can be operated by reading a program stored in the ROM pack In the FA M3 R series you can achieve the same functions as those of a commercially available ROM writer such as writing a program to the ROM pack by using the sequence CPU module or add on CPU module These functions are called the ROM writer functions and inclu
44. 3 11 2 Input Interrupt Processing Control You can control the execution of input interrupt programs by means of programming Use the Enable Interrupt El instruction and Disable Interrupt DI instructions respectively to specify whether to execute enable or not execute disable an interrupt Interrupts are enabled by default An interrupt that is disabled by a DI instruction continues to be detected by the sequence CPU but its input interrupt program is not executed Such interrupts are processed in order of their occurrence if and after they are enabled by an El instruction A maximum of eight concurrent interrupts are accepted The ninth or subsequent concurrent interrupt generates an interrupt error 10001 Y00602 Occurrence of pml interrupt 1X00503 10002 Y00603 X00501 X00502 10004 li aia H No interrupt programs are executed in this interval F031102 VSD Figure 3 29 Input Interrupt Processing Control IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 28 3 11 3 Interrupt Timing Using the configuration function of WideField3 or WideField2 you can specify when an interrupt program is to be executed if an interrupt occurs during program execution The following two options are available Table 3 7 Interrupt Timing Options of Input Module Interrupt Processing Interrupt Timing Description After instruction default The sequence CPU switches execution to an inp
45. 3 Fiber optic FA bus module 7093 Subunit Communication Subunit 4 0 Normal transmission line Error Slot ubuni Unspecified transmission line or Z094 Subunit 5 Loaded with a wrong module 1 Abnormal transmission line Z095 Subunit 6 Subunit communication error or Sub unit transmitter switching has Z096 Subunit 7 occurred For information on error numbers codes to be saved in these special registers see Table 8 2 Details of Self diagnosis SEE ALSO For more information on the Z089 to Z096 special registers Subunit Communication Error Slot see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Appx 2 3 Appendix 2 3 Utility Registers Table Appendix 2 3 Utility Registers Utility Registers Function Description Stores year as a BCD coded value Z049 Last two digits of e g 1999 as 0099 write enabled calendar year 2000 as 0000 Stores month as a BCD coded value e g January as 0001 Stores day of month as a BCD coded write enabled Day of month value e g 28th as 0028 Clock Data Hour Stores hour as a BCD coded value write enabled e g 18 00 hours as 0018 Z053 Minute Stores minute as a BCD coded value write enabled e g 15 minutes as 0015 Z054 Stores second as a BCD coded value write enabled Second e g 30 seconds as 0030 Stores day of wee
46. 4 3 Operation When Specified Blocks Are Activated 25 6 7 6 4 4 Operation When Specified Blocks Are Inactivated 6 9 6 4 5 Operation When Specified Blocks Are Executed 6 10 6 5 Debugging Functions ccccssseeecessseeeeeseeeeeeeessseeeeessseeeeessseensesseenens 6 12 6 5 1 Forced SET RESET 0 cc cccsceceeceececeeeeeeeeseeeeeseeeesneeeesees 6 12 6 5 2 Changing Setpoints Current Values and Data Values 6 12 6 5 3 Stopping Refreshing eccceeeeeeeeeeeeeeeeeeeeenteeeeeeneeeeeseaas 6 13 6 6 Program Protection c0sceccessesesctecetesceescevesseceressuecetecssceeseeeseceese 6 14 IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 6 1 Executable Program Protection ccsceeeeseeeeeeesteeeeeees 6 14 6 6 2 Block Protection nigiri a aa 6 15 6 7 Online Editing seorsa 6 16 6 8 Making Programs Resident Using ROM Writer Functions 6 18 6 8 1 Making Programs Resident in ROM ere 6 18 6 8 2 Defining Current Values of Devices to Be Made Resident 1 ROM erein e E N E 6 21 6 8 3 ROM Writer Functions and ROM Writer Mode 6 21 6 9 Exclusive Access Control 2 ccccceceeseseeeeeeeeeeeeeeeesseeneeseeeeeeeesees 6 23 6 10 Sampling Trace Functions cccssseeecessseeeeeseseeeeessseeeeeeeseeeneeseenees 6 24 6 11 Personal Computer Link Functions ccceeceseesseeneeeeeeeeeeetees 6 27 6 11 1 System Configuration
47. 435 us for F3SP53 F3SP58 and F3SP59 sequence CPUs 2 Application Instructions Use parenthesized execution time value from the List of Ladder Sequence Instructions if any vo1 V02 i Number of index modified 1 MOV D0001 D0002 relay devices N3 2 3 2 2 0x2 7 2 us for F3SP22 F3SP28 and F3SP38 sequence CPUs 1 2 0 8x2 2 8 us for F3SP53 F3SP58 and F3SP59 sequence CPUs IM 34MO06P13 01E 4th Edition Jan 31 2012 00 8 1 Severity of Failure RAS Functions This chapter describes the RAS functions of the sequence CPU module such as the self diagnosis and error logging functions that work if the module fails Self diagnosis The sequence CPU performs self diagnosis on its device memory instruction codes and so on when the power is turned on or a program is being executed The results of self diagnosis are reflected in specific special relays M and registers Z If any failure is found during self diagnosis the CPU module updates the mode statuses of LED indicators and stops executing programs depending on the failure mode The table below shows the classification of errors Table 8 1 Severity of Failure and CPU Module LED Indicator Status FAIL Signal Contact Output LED Indicator Status The green RDY lamp goes out Failure Condition The core hardware is disabled Failure Mode CPU error Memory crash 8 1 Action of Output Module Between FAIL1 and COM
48. A device memory read write check error has occurred Asystem memory read write check error has occurred An invalid instruction has been encountered Hardware failure The error may be due to a transient memory failure caused by noise Check the installation environment Clear the memory by referring to CAUTION at the end of these tables and download the program again If the failure recurs replace the module There is a mismatch in SUB RET or JMP instructions Hardware failure Verify that JMP SUB and RET instructions are paired correctly The error may be due to a transient memory failure caused by effects of noise Check the installation environment Clear the memory by referring to CAUTION at the end of these tables and download the program again If the failure recurs replace the module The number of I O points has been exceeded The ROM pack is incompatible with the CPU A failure to read from or write to the ROM pack has been encountered The backup batteries have failed The subroutine return RET instruction was not executed or there is no return destination The maximum nesting depth of eight levels has been exceeded Hardware failure Mismatch between ROM pack and CPU Hardware Hardware failure Hardware failure Hardware failure Application error Application error 1 You may recover from this error by turning the power off and then on again
49. Bytes 1 STX code Station No CPU No ER Appanasaanand Pe response ill t77 enabled accordingly in the configuration F061110 VSD Figure 6 33 Response Format when Communication Is Abnormal No of Bytes pt When communication results in an abnormal end the string ER is returned along with the codes EC1 and EC2 EC1 Error code EC2 Detailed error code If the communication failure is due to an error in the CPU number the received 2 byte CPU number is returned If the failure is due to an error in the station number no response is returned If an ETX code in a command is not received no response may be returned If this happens be sure to perform a timeout process on the higher level computer or monitor IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 38 E Error Code in a Response A communication failure may occur when the sequence CPU module receives a command In that case the module returns the string ER and an error code as a response to the command The table below shows the error codes that may be returned as a response Table 6 11 Error Codes in a Response Semantics Possible Causes CPU number error The CPU number is outside the range of 1 to 4 The command does not exist The command is not executable The device name does not exist Device specification error Arelay device is incorrectly specified for read write access in word units Characters other than
50. CPU modules refer to BASIC CPU Modules and YM BASIC FA Programming Language IM 34M06Q22 01E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Copyrights and Trademarks E Copyrights Copyrights of the programs and online manual included in this CD ROM belong to Yokogawa Electric Corporation This online manual may be printed but PDF security settings have been made to prevent alteration of its contents This online manual may only be printed and used for the sole purpose of operating this product When using a printed copy of the online manual pay attention to possible inconsistencies with the latest version of the online manual Ensure that the edition agrees with the latest CD ROM version Copying passing selling or distribution including transferring over computer networks of the contents of the online manual in part or in whole to any third party is strictly prohibited Registering or recording onto videotapes and other media is also prohibited without expressed permission of Yokogawa Electric Corporation E Trademarks The trade and company names that are referred to in this document are either trademarks or registered trademarks of their respective companies IM 34MO06P13 01E 4th Edition Jan 31 2012 00 TOC 1 FA M3 Sequence CPU Instruction Manual Functions for F3SP22 0S F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S IM 34M06P13 01E 4th Edition CONTENTS Applicable Proquet ccscs
51. Edition Jan 31 2012 00 4 1 4 1 1 Devices This chapter describes the types and functions of devices available with the sequence CPU modules Relay devices are accessed on a one bit basis Thus a relay device number corresponds to a bit Register devices are accessed on a 16 bit basis Thus a register device number corresponds to 16 bits I O Relays X Y I O relays X Y are devices used to exchange data with external equipment I O relay X Y numbers are determined by the position of the slot where an I O module is installed They are fixed discontinuous numbers and are assigned on 64 relay basis for each slot The input relay X numbers never coincide with any of the output relay Y numbers Data held in the I O relays is not retained when the power is turned off For more information on I O relay X Y number definitions refer to Section 1 3 Basic Configuration Input Relays X Input relays are used to input the ON and OFF states of external equipment such as pushbuttons and limit switches In programs you can use these relays for contacts a and b and application instructions Input relay numbers are coded as X L mmnn where Lmm Slot number L Unit number 0 to 7 mm Slot position 01 to 16 nn Terminal number 1 to 64 X00502 Y00602 ll O Input from gt LU external lt X00501 X00502 Y00601 equipment X00503 X00504 Y00603 F K X00501 X00502 Z Y00604
52. Erases ROM pack data Table 6 3 Device Management Functions Device Management Functions Upload device data Function Overview Reads device information data from the sequence CPU module and saves it to a WideField3 or WideField2 file Download device data Reads device information data from a WideField3 or WideField2 file and writes it to the sequence CPU module Edit device data Edits device information data saved in a WideField3 or WideField2 file Compare device data Compares device information saved in the sequence CPU module with that saved in a WideField3 or WideField2 file IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 2 Operation Setup Functions The operation setup functions set up the sequence CPU module operating mode and initializes programs and devices You can set up operation by issuing a command from WideField3 or WideField2 personal computer link module or an add on CPU module E Run Mode In Run mode the CPU begins running a program from its first instruction similarly to when the power is turned on When the power is turned on or the operating mode is changed from Stop mode to Run mode the CPU sets all devices to 0 except for latching type devices before executing the program When the CPU switches to Run mode functions that are available only in Debug or Stop mode are disabled E Debug Mode In Debug mode the CPU begins running a program from its fir
53. Otherwise the output instruction may not be processed correctly This precaution is also true with other groups of 16 relays numbered 17 to 32 33 to 48 49 to 64 and so on Do not output data to relays within the same group both in the sensor control block and in a normal scan program 16n 16 16n 1 Example If a sensor control block controls 100032 the normal scan program must not control 100017 to 100031 F061506 VSD Figure 6 46 Precautions for Relay Output Simultaneity of multi device data Simultaneity of data for multiple devices is not guaranteed For example consider the case shown in Figure 6 44 where the sensor control block is executed during execution of a block transfer BMOV instruction in a normal scan There is a risk that the source data that is partially transferred may be overwritten after the execution of the sensor control block or data transferred partially to the destination may be read by the sensor control block Simultaneity of data is required when data of multiple devices is exchanged between a normal scan program and the sensor control block program using a block transfer BMOV instruction a long word instruction with IEEE single precision floating point data or two or more instructions If simultaneity of data is required when interrupt timing is configured as Immediate during instruction execution use any of the following means to ensure data simultaneity IM 34MO06P13 01E 4th Ed
54. STL Interrupt TIMING sidetite aids nis tt tiid n neds 3 28 3 11 4 Priority of Interrupts 20 0 2 cece ee eeee erect eeeeeeeeeeaeeeeeenaeeeeeeeaas 3 30 Ce oan Sassen cece ances ahs ance cc eeeccetc cen cceeceenccatanes 4 1 4 1 VO Relays X Y scesiecivccciccecteevectteessncesciecnveste catecesnetveseceasecsenueteestieensecs 4 1 4 1 1 Input Relays X oo eceeeccecsseeceeeesneeeeesseeeeeeseeeeecseeeeessseeeesenaes 4 1 41 2 Output Relays Yeer pices 4 2 4 1 3 Allocation of I O Addresses 000 0 ececcecceeeeeenteeeeetttieeeeeetteeeeeens 4 2 4 1 4 Configuring DIO Modules 0 ec eeeeeeeeeteeeeeteneeeeetneeeeeeene 4 3 4 2 Internal Relays I Shared Relays E and Extended Shared 23 Foe S A a S 4 6 4 2 1 Internal Relays U ers essed eevesenctes seveetesecddauevaecngens seaedexs dadeecs anced 4 6 4 2 2 Shared Relays E and Extended Shared Relays E 4 7 4 3 Link Relays L and Link Registers W cscscssessseseeseeeeeeeenees 4 11 43 1 Link Relays L onis 4 12 4 3 2 Link Registers W 2 cccccecceeeccecteedeccetteedecceteedecertaedecteneees 4 13 4 3 3 System Numbers essenin E AA 4 14 4 3 4 Configuring Link Relays L and Registers W 0 4 15 4 3 5 Link Refreshing Range ssseseesssesrsseerrsseerrssrerrsserrrsseeeens 4 16 4 4 Special Relays M iccsccceiccsadcsesiceeseiccnnivesticeetveettted fetecaniverteceisereaiieeis 4 18 4 4 1 Block Start Status Relays 4 18 4 4 2 Utility Relays oo eee ee eeeee
55. Scan Time of F3SP53 F3SP58 or F3SP59 Sequence CPU Common processing Calculation Fixed at 0 2 ms Processing Time Program execution 0 035 us x 20480 717 us Output refreshing Number of modules calculated on a 16 points basis 2 x 4 8 12 us x 8 96 us Shared refreshing When no add on CPU module is installed 0 00 ms Input refreshing Number of modules calculated on a 16 points basis 2 x 4 8 6 us x 8 48 us Synchronization processing Number of modules calculated on a 16 points basis 2 x 4 8 8 us x 8 64 us Peripheral processing Minimum peripheral processing time if not yet defined 0 2 ms Scan time which is the sum of all time spans listed above The output refreshing time and the minimum peripheral processing time are excluded from scan time calculation because the sum of these time spans is smaller than the program execution time IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 6 7 4 Example of I O Response Time Calculation Calculation of the minimum I O response time Input response time 16 ms Output response time 1ms Scan time 2ms Minimum I O response time Input response time Scan time Output response time 16ms 2ms 1ms 19ms X00502 Y00602 J la II ba Input refreshing Instruction execution Instruction execution l l Output l I
56. Sensor CB Timing of interrupt Immediate during instruction execution After Instruction Immediate during instruction execution Input interrupt Timing of interrupt After instruction After Instruction Immediate during instruction execution Priority of interrupts Sensor CB interrupt has priority Sensor CB interrupt has priority Input module has priority Input Output Setup Terminal usage Module used not used Used Used Not used Use with SCB Configurable on 16 terminal basis Data code BIN BIN BCD configurable on 16 terminal basis Input sampling interval 16 ms 16 ms 1 ms 250 us 62 5 us Always configurable on 16 terminal basis Output when stopped Reset hold external outputs when sequence stops Reset Reset hold configurable on 16 terminal basis ROM Setup Device current values to be resident in ROM Data registers D File registers B None Up to 32768 contiguous points from a starting number Note Configure on 32 terminal basis when using the same input module for both sensor control block and regular blocks SEE ALSO For more information on the subunit communication error see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 Table 1 10 Configuration Range 5 5 F3SP22 0S F3SP28 3N 3S F3SP53 4H 4
57. Sensor control block Input refreshing Interrupt of execution Program execution Continuation of BMOV instruction Output refreshing Next instruction EA EEA O AEE cues F061504 VSD Figure 6 44 Immediate Interrupt by Sensor Control Block during Instruction Execution IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 66 The table below summarizes the differences between these two interrupt timing options Table 6 27 Differences between the Two Interrupt Timing Options When Interrupt Timing When Interrupt Timing is Immediate is After Instruction Execution Processing time of instruction being executed Note 1 Switchover processing time Note 2 Execution or Synchronization processing time Note 3 delay Common processing time Note 3 Switchover processing time only Note 2 Input refreshing time Note 3 Switchover processing time Note 2 Simultaneity of data Guaranteed for each instruction No simultaneity of multi device data Note 1 For details on instruction processing time see the instruction list in the Appendix of Sequence CPU Instruction Manual Instructions IM 34M06P12 03E Note 2 9 to 30 us for F3SP22 F3SP28 and F3SP38 CPU modules and 3 to 10 us for F3SP53 F3SP58 and F3SP59 CPU modules Note 3 See Section 7 1 Description of Scan Time A CAUTION Setting execution interval when the interrupt timing is after instruction ex
58. Shorted Between FAIL2 and COM Output modules other than F3YD64 1A F3YD64 1M F3WD64 CN Default RESET Configurable to HOLD or RESET on 16 terminal basis F3YD64 1A F3YD64 1M F3WD64 ON yooooo Always HOLD Not configurable The red ERR lamp comes on The user program cannot be started or run any further Program error I O comparison error I O module error Memory error CPU error Instruction error Scan timeout t Startup error Invalid instruction found Excess number of I O points ROM pack error Subroutine error Interrupt error Subunit communication error Sensor CB scan timeout Battery error Shorted Default RESET Configurable to HOLD or RESET on 16 terminal basis Default RESET Configurable to HOLD or RESET on 16 terminal basis The yellow ALM lamp comes on An error has occurred but the program can continue execution Momentary power failure Inter CPU communication error Subunit transmitter switching has occurred Operation continues Operation continues 1 The table indicates the default severity level for this error which can be reclassified as a minor failure by configuration 2 Output relays YOOOOD of the advanced modules For some of the failure modes you can select the Stop or Run option to specify whether to stop or continue program execution if any of these failures occur This selection
59. System 4 System 5 System 6 System 7 System 8 Link Type Automatic setup Slot Number FA Link al 2 FA Link Setup Tool Startup Execute D System numbers L s8 7 6 54 Link Register w Link Device Assignment oocom 0 FL net 3 FL net Refresh Setup Execute L10001 p U1 Do Not Use Not available when set as not used Do Not Use Not available when set as not used Do Not Use Not available when set as not used Do Not Use Not available when set as not used Do Not Use Not available when set as not used Do Not Use Le Le Le Lel Led Lel Led Le LH LH LH LH LH LE be Cancel Not available when set as not used Default Figure 4 13 WideField3 Configuration Setup LE LE be LE LE LE bed kk F040305 VSD IM 34M06P13 01E 3 1 F040304 VSD 4th Edition Jan 31 2012 00 4 15 4 3 4 Configuring Link Relays L and Registers W Specify the range of link relays and registers to be included in each link system For each system specify the number of link relays and link registers to be used Table 4 4 Configuration of Device Capacities F3SP22 F3SP28 F3SP53 Device Capacities Link relays L for each system FA link or FL net OPCN 2 system F3SP38 F3SP58 F3SP59 Default System 1 to 4 2048 System 5 to 8 0 Configuration Range 8192 max for all systems combi
60. a 0 02 s period Generates a clock pulse with a 0 1 s period 0 2 s Clock Generates a clock pulse with a 0 2 s period 1 s Clock Generates a clock pulse with a 1 s period 2 s Clock Generates a clock pulse with a 2 s period 1 min Clock 30s Generates a clock pulse with a 1 min period 1 ms Clock 0 5ms 0 5ms Generates a clock pulse with a 1 ms period 2 ms Clock 1ms 4ms Generates a clock pulse with a 2 ms period Normal Subunit Transmission Line ON Normal transmiss OFF Unspecified or ab ion line or no fiber optic FA bus installed normal transmission line ON for One Scan at Sensor CB Start ON At startup OFF In all other Turns on for one scan when the sensor control block starts at the first cases execution of the sensor control block Blocks M036 to M048 have their rising and falling clock timing synchronized SEE ALSO For details on the MO66 Utility relay Normal Subunit Transmission Line see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34MO6P13 01E 4th Edition Jan 31 2012 00 Appx 1 3 Appendix 1 3 Sequence Operation and Mode Status Relays Sequence operation and mode status relays indicate the status of sequence operation and various modes Table Appendix 1 3 Sequence Operation and Mode Status Relays Sequence Operation and Mode Status Rela
61. a Structure Macro Instruction Use the structure Macro Instruction Call SCALL instruction to call a structure macro instruction SEE ALSO For details on the SCALL instruction see Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E Passing Structure Data to a Structure Macro Instruction When passing structure data code the name of the structure in the macro instruction call but use a structure pointer register Q within the macro instruction entity SEE ALSO For details on structure pointer registers Q see Section 6 13 3 Devices Dedicated to Macro Instructions Nesting structure Macros A structure macro instruction cannot call another structure macro instruction A structure macro instruction can call macro and input macro instructions but cannot use the PARA instruction IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 14 6 58 User Log Management Functions The user log management functions keep a record of error events in a user system including information on error occurrence and system operation status when Save User Log instructions are executed Stored user log records can then be read using instructions or WideField3 or WideField2 These functions are useful for analyzing faults and understanding the operating conditions of machinery m Handling User Logs A maximum of 64 user log records per CPU can be saved by executing user log instructions in a program Four data items
62. by monitoring a special relay M195 AC voltage N p i Power failure detection level Program execution v Interruption F030301 VSD Figure 3 2 Operation in Case of Momentary Power Failure A CAUTION While the sensor control block is active a momentary power failure may result in a sensor control block scan timeout In this case the sensor control block stops and must be restarted after the power is restored E Immediate Detection Mode If a momentary power failure occurs the sequence CPU module records the date and time in its error log file The sequence CPU module suspends processing until power is restored At this point the CPU sets the external outputs generated by a program to OFF and actuates the FAIL contact When power is restored the sequence CPU module performs a reset and start sequence and executes the program from its beginning IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 3 2 Momentary Power Failure Detection Mode Setup This configuration item defines the momentary power failure detection mode You can select either the standard mode or the immediate detection mode The default is the standard mode For details on each of these modes see Hardware Manual IM 34M06C11 01E AY CAUTION 3 3 3 3 3 4 Extended device configuration In a multi CPU configuration all CPU modules must be configured with the same momentary power failure detection mode Operation in Case of Comple
63. can be made using the configuration function This configuration item defaults to the Stop option for a moderate failure and to the Run option for a minor failure Moderate failure modes set to the Run option are treated as minor failure modes while minor failure modes set to the Stop option are treated as moderate failure modes SEE ALSO The fail signal contact reports the error state to the external environment when an error occurs AN CAUTION If you want the contacts of an output module to be held in case of a major or moderate failure in the sequence CPU module set the Output When Stopped option of the configuration function to Hold Note that the module action is independent of the output module type IM 34M06P13 01E 4th Edition Jan 31 2012 00 Table 8 2 Details on Self diagnosis 1 3 Failure Mode Major failure CPU error Special Relay that Turns ON Special Registers that Store Error Codes Etc Stored Error Code Failure Description The CPU malfunctions due to noise or for other reasons Hardware failure Hardware failure Corrective Actions Check the installation environment for possible problems such as noise sources If the failure recurs replace the module Moderate failure Startup error SPU error Memory error Invalid instruction found Program error Excess number of I O points ROM pack error Battery error Sub
64. computer Personal computer when running BASIC programs Program i ASCII stri PRINT Command string LINE INPUT lt i or Response ASCII string INPUTS ra Power CPU supply F061104 VSD Figure 6 27 Interaction between Command and Response Higher level computer Command STX code Station No CPU No Response wait time Command To FA M3 Parameters Checksum FA M3 ETX code Response STX code End character Station No CPU No Response wait time To higher level computer or monitor Command response Checksum ETX code End character F061105 VSD Figure 6 28 Brief Description of Command and Response Formats IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 11 6 6 34 Commands and Responses SEE ALSO For details on commands and responses see Personal Computer Link Commands IM 34M06P41 01E E Command Format and Elements The figure below shows the format of a command to be sent from the higher level computer or monitor to the FA M3 ETX code Checksum is set to Yes _ Required only if the configuration item End character is set to Yes F061106 VSD Figure 6 29 Command Format and Elements Only uppercase alphabetic characters from A to Z ASCII codes 41 to 5A in hexadecimal are used
65. configured to suit your application needs A rich set of functions are provided to facilitate program debugging and maintenance For example a forced SET RESET function independent of program operation results A carefully designed self diagnosis function supplements a highly reliable design Macro instruction functions allow you to create and register new instructions The sampling trace functions acquire and displays the states of multiple devices for a maximum of 1024 scans The programming tool connection port supports the personal computer link functions and thus enables connection to a higher level computer or a monitor without the need for a personal computer link module The log function records errors encountered in a program as well as messages created and registered in advance F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 or F3SP59 modules can be mounted in slots 2 to 4 of the main unit for use as add on CPU modules for sequence processes added to the main CPU module F3SP21 F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 or F3SP76 A ROM pack can be attached so that you can perform ROM based operation and store programs Program protection functions ensure security The partial download functions allow downloading of specified blocks only which increases debugging efficiency especially in collaborative program development F3SPOO OS Indirect specification via devices enables large volum
66. followed by the first extended shared relay E numbered E2049 Likewise if the number of shared registers R is smaller than 1024 the last of them is followed by the first extended shared register R numbered R1025 Example In a case where there are 1024 shared relays E and 2048 extended shared relays E If you define the starting number as 513 and the number of units as 1024 for the range of devices to be latched in case of power failure then the devices that are latched include E513 to E1024 shared relays E and E2049 to E2560 extended shared relays E Note The configuration range of each of link relays L and registers W to be latched in case of power failure is assigned numbers continuous from the starting number However the following exceptions apply The number following L W01024 is L W11024 The number following L W11024 is LW21024 The number following L W21024 is L W31024 The number following L W31024 is L W41024 The number following L W41024 is L W51024 The number following L W51024 is L W61024 The number following L W61024 is L W71024 The rules noted above are true when the number of link relays L or registers W to be used is defined as 1024 If the number is 2048 the number following L W02048 is L W10001 Example When there are 1024 link relays L each for link 1 link 2 and link 3 If you define the starting number as 10513 and the number of units as 1024 for the range of devices to be latched in
67. instruction using a pointer register P is to be executed repeatedly you can first transfer the values of the pointer registers P to macro relays H and macro registers A and then rewrite the instruction to use these relays and registers instead In this way you can shorten the execution time SEE ALSO For details on basic and application instructions see Sections 2 1 and 3 1 of Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 48 X00502 T MOV 1 Vo1 voi PARA 4 R0001 P04 R0002 AM EFG123 D0001 10001 Y00301 H P01 D0001 Mnemonic MCALL T EFG123 D0001 10001 Y00301 B02 10001 EFG123 macro instruction entity M033 MOV 1 A0001 MOV 2 u01 u01 P04 P01 A0001 Pointer registers within a macro instruction entity Note u01 R0002 D0001 A0001 MRET F061307 VSD Note Pointer registers can be used within a macro instruction entity Figure 6 37 An Example Using Pointer Registers P AN CAUTION If you pass a device with index modification as a parameter to a macro instruction the instruction receives the index modified device In the example shown in the above figure parameter R0001 V01 is the same as device R0002 because V01 1 Any index modification of a pointer register P is appl
68. interface module IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 4 4 4 1 4 18 Special Relays M Special relays have specific functions such as indicating the internal state of the sequence CPU module or detecting errors In programs these relays are used mainly for contacts a and b Block Start Status Relays Block Start Status relays indicate which blocks are executed when only specified blocks are executed These relays are numbered in ascending order as M001 M002 to correlate with block 1 block 2 Table 4 5 Block Start Status Relays Item Block Start Status Relays Relay Number Description Functionalit Explanation M0001 to M0032 Indicates whether block n ON Run is executed when the Block n start status f module is configured to M2001 to M3024 ORFE SIOP execute specified blocks only Note The Start Status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032 M0001 to M0032 have the same values as M2001 to M2032 Similarly Start Status relays M2033 to M3024 map to blocks 33 to 1024 A CAUTION Do not write to a special relay including those not listed in tables in this section e g M067 to M128 unless otherwise stated Special relays are used by the sequence CPU module Writing to these relays incorrectly may lead to system shutdown or other failures Using forced set reset instruction in debug mode is also prohibited A CAUTION Special relays with in
69. is turned on the CPU performs initialization to get ready for program execution During initialization the CPU performs I O collation and instruction interpretation to check whether its hardware and programs are normal If no error is detected the CPU begins executes a program from its beginning If equipped with a ROM pack the CPU reads programs from the pack and begins system operation If in the ROM Writer mode however the CPU does not read programs from the ROM pack Alternatively it enters a command wait state e g waits for a ROM transfer command from the WideField3 or WideField2 without executing a program Power on AA Self diagnosis YES The RDY LED indicator turns on lt ROM writer mode NO NO quipped with ROM pack YES Read programs from OM pack pg Program diagnosis Wait for command NO y Start program Stop The RUN LED The ERR LED indicator turns on indicator turns on F030201 VSD Figure 3 1 Operation at Power on Operation at Power off When the power is turned off the sequence CPU module records the date and time in its error log file and stops system operation TIP The error log function saves to an error log file information such as time of occurrence and type of error when a system error occurs or when the power is turned on or turned off SEE ALSO For details on the error log see
70. modes The following marks are used when explaining a function to indicate that the function is available in the cited mode or modes If no mark is indicated it means that the function can be used in all operating modes Some functions may lengthen the scan time Be sure to disable such functions after use and before actual operation Be especially careful when using any function that is enabled in Debug mode Always disable the function and enter Run mode after debugging and tuning Be sure to use the ROM writer functions when operating the ROM pack The following mark is used when explaining each ROM writer function to indicate that the function is available in ROM Writer mode ROM writer IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 3 6 3 1 6 4 Constant Scan Run The constant scan function executes a program repeatedly at certain time intervals You can set the constant scan time i e constant scan time interval to a value between 1 ms and 190 ms in 0 1 ms increments using the configuration function END END END 0 step instruction 0 step instruction 0 step instruction I I I l I I l l l I I l I l l I i 3ms i i 5ms i i 2ms i i i aaa oe I I l l I l l l i 10ms i 10ms i 10ms i SSS SS a a a m eS Sark SS gt F060301 VSD Figure 6 1 Operation Based on 10 ms Constant Scan If the scan time of a sequence program is longer than the preset constant scan time the constant scan setting is ignor
71. namely date of occurrence time of occurrence main code one word and subcode one word are saved in each user log record Up to sixty four 32 character messages associated with individual main codes can be stored in the CPU These stored messages can be retrieved along with main codes when log information is read The user log information area is maintained as a rotary buffer If the maximum number of log records allowed is exceeded existing log records are overwritten by new log records in chronological order Stored user log records can be read using WideField3 or WideField2 or Read User Log instructions You can check the special register Z105 for the number of stored user log records available y Ladder program ULOG D0001 D1000 User log record is stored when the instruction is executed User log information area Records are paar stored and 95 09 26 14 10 52 12 05 A A 95 09 26 14 21 12 17 04 __ i e order o i occurrence Ly Rotary buffer E F061401 VSD Figure 6 41 Handling User Logs AN CAUTION In some cases WideField3 or WideField2 may display two identical log records This happens if a save user log instruction is executed when stored user log records is read using WideField3 or WideField2 To solve the problem redisplay log records when not executing a save user log instruction SEE ALSO For details on the instructions related to user log
72. other than the file registers B SEE ALSO For details on indirect specification see Section 1 10 2 Indirect Specification of Sequence CPU Instruction Manual Instructions IM 34MO06P12 03E Index modification by constant With the new models index modification by constant is available SEE ALSO For details on index modification by constant see Section 1 10 1 Index Modification of Sequence CPU Instruction Manual Instructions IM 34MO06P12 03E Nesting of interlock areas program steps between IL and ILC Interlock areas may be nested up to 8 levels SEE ALSO For details on interlock see Section 2 18 Interlock IL Interlock Clear ILC of Sequence CPU Instruction Manual Instructions IM 34M06P12 03E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 10 3 10 4 New instructions The following instructions are added in the new models Table 10 1 List of Added Instructions Mnemonic Instruction Indirect Address Set Indirect Address Add Indirect Address Move Load Specified Bit Out Specified Bit Set Specified Bit Reset Specified Bit Input Macro Instruction Call Output of Input Macro Structure Macro Instruction Call Structure Move Structure pointer Declaration Set Date Set Time Set Date String Set Time String SEE ALSO For details on these new instructions see Sequence CPU Instructi
73. power supply for possible problems If a UPS is in use check that it has captured peak values of its supply voltage waveform If the failure still occurs frequently while there is no problem with the wave form the power supply module or sequence CPU module may be defective Replace it There may be a failure in one of the other CPUs ina multi CPU system Do not reset the CPU modules individually Rather reset them all at once from the main CPU If this failure mode recurs replace the CPU modules Check if there is any problem with the cable of the fiber optic FA bus module The fiber optic FA bus module may be defective Replace it 2 The CPU module can be configured to stop or continue execution of the program for this error event 3 Since debugging operation in Debug mode may extend the scan time the scan monitoring time increases threefold IM 34MO06P13 01E 4th Edition Jan 31 2012 00 SEE ALSO 8 5 For error log system log messages see also FA M3 Programming Tool WideField3 IM 34M06Q16 ODE or FA M3 Programming Tool WideField2 IM 34M06Q15 01E For details on the failure modes subunit communication error M210 and Subunit transmitter switching has occurred M211 see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E AN CAUTION You can clear the CPU memory and revert it to its factory settings by installing the sequence CPU module
74. processed as a single instruction The figure below presents an overview of macro instructions How to code a macro instruction in ladder diagram editing X00502 II MOV 1 D0001 M Macro ABC D0001 D0902 0 instruction call Mnemonic MCALL ABC D0001 D0002 0 calling side AM vo1 EFG123 D0002 Wo0001 Y00301 Mnemonic MCALL EFG123 D0002 W0001 Y00301 F081307 Vsp How to code a macro instruction entity ABC in ladder macro editing ABC macro instruction entity called side M033 P02 F061302 VSD Figure 6 34 Examples of Macro Instructions In the above figure ABC and EFG123 instructions are macro instructions When the CPU encounters the ABC instruction it executes the ABC macro instruction entity like a subroutine using D0001 and D0002 as parameters Macro instructions are created using ladder macro editing separately from normal instructions created using ladder diagram editing The Macro Return MRET instruction represents the end of a macro instruction entity For details on parameters P01 P02 and U01 in the figure see Subsection 6 13 3 Devices Dedicated to Macro Instructions SEE ALSO For details on the Macro Return MRET instruction see Section 3 13 4 Macro Call MCALL Parameter PARA Macro Return MRET of Sequence CPU Instruction Manual Instructions
75. refreshing as a peripheral process or a control related process Link refreshing executed as a peripheral process does not affect the scan time Executing link refreshing as a control related process may lengthen the scan time but it ensures that link refreshing is not affected by the shared refreshing or command processing time Include link refreshing in peripheral processes if a short scan time is important Alternatively include it in control related processes if the speed of exchanging link data is important Common processing Input refreshing Output refreshing Instruction execution Peripheral Synchronization processing processing po Common processing Input refreshing including link refreshing Output refreshing Instruction execution Peripheral processing Synchronization processing 1 Link service Peripheral processes Shared refreshing Link refreshing Command processing Tool service Link service CPU service F031005 VSD Figure 3 23 Executing FL net Link Refreshing as a Peripheral Process Peripheral processes Shared refreshing Command processing Tool service CPU service F031006 VSD Figure 3 24 Executing FL net Link Refreshing as a Control related Process IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 24 When executed as a peripheral process link r
76. separation see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E SEE ALSO For details on unit number see Section 1 3 2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 14 1 3 2 Slot Number A slot number indicates the position of a slot where a module is installed A slot number is defined as a three digit integer as shown below Slot number Ao Slot positions 01 to 16 are assigned to the slot on the immediate right of the power supply module through to the rightmost slot of a base module Unit number Main unit 0 Subunit 1 to 7 F010302 VSD Figure 1 2 Slot Numbers 1 of 2 Fiber optic FA bus type 2 module can be installed in any position FA M3 main unit 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 0j6 Slot numbers 001 to 016
77. system configuration A CPU module installed in the Nth N 1 to 4 slot is called the Nth CPU module or CPU N TIP ABASIC CPU module refers to a CPU module which is controlled by BASIC programs IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 2 Main CPU module lt gt gE WU alll cel BO 001 002 003 004 005 006 007 008 009 010 011 012 013 lt Slot numbers Add on CPU modules F020201 VSD Figure 2 2 Example of Multi CPU System Configuration A CAUTION Be careful not to install any CPU module in the 5th or later slot and turn on the power Otherwise the memory is cleared and factory settings are restored IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 3 2 2 2 Handling I O Modules in Multi CPU System E Input Modules With input modules you can read input data through multiple CPUs To do this configure the CPUs so that they share the same input sampling interval for the input module in question Be careful as the sampling interval that can be set varies depending on the CPU type E Output Modules and Special Modules with YOOOOO Output Relays Y Combination of F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 CPU Modules You can output data from multiple sequence CPU modules separately to the output relays of the same output module on 16 point basis To do this configure the unused out
78. when a Positive Delay Is Defined lt i 1024 sampled points are stored in the sampling trace memory F061006 VSD IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 27 6 11 Personal Computer Link Functions This section describes the personal computer link functions that allow a personal computer or a display device to be connected to a sequence CPU module The programming tool connector on the front of the CPU module functions in the same way as the RS232 C communication port on the F3LC11 1F personal computer link module This means you can connect higher level equipment such as a personal computer or FA computer or a monitor to the CPU module to perform one to one communication as you do with the personal computer link module This feature is called the personal computer link functions You can monitor and configure devices as well as start stop download and upload programs by entering commands from the higher level computer Personal computer or Personal computer monitor with PC interface running WideField2 _ _____ 35 Personal computer X00503 X00504 Y00602 Hi if oH J T ___ i bs i N X00501 X00502 Y00601 Perosnal computer l f C link function l y N X00503 Capability of N programming tool S i connection ia Sequence CPU module F061101 VSD
79. 0 E List of Supported Devices Use commas or spaces to separate parameters A device name should be represented in six or seven characters or bytes Their abbreviations can be also used however For example X00201 can be abbreviated as X201 and V00002 as V02 or V2 The following example shows a case when you read the data of CPU1 s five input relays beginning with input relay X00201 The response wait time is assumed to be 100 ms Table 6 13 List of Supported Devices device a Command P gt Response wait time Batted gt CPU number Device Name Xnnnnn Input relay Station number which is fixed at 01 F061111 VSD Ynnnnn Output relay Innnnn Internal relay Bit Ennnnn Shared extended shared relay Lnnnnn Link relay Mnnnnn Special relay Tnnnnn Timer Cnnnnn Counter 4 2 3 4 5 6 device Dnnnnn Data register Rnnnnn Shared register Word Vnnnnn Index register Bnnnnnn File register Wnnnnn Link register Specify Znnnnn Special register a time out relay as TUnnnn and an end of count relay as CUnnnn Specify the current value of a countdown timer as TPnnnn the current value of a countdown counter as CPnnnn the current value of a count up timer as TInnnn the current value of a count up counter as Clnnnn the setpoint of a timer as TSnnnn and the setp
80. 0 and 1 are used for bit setting Value outside the setting Word setting is out of the valid range of 0000 to FFFF range The specified starting position in a command such as Load Save is out of the valid address range The specified bit count word count etc exceeded the specifications range i The specified data count and the device parameter count etc do not match Attempted to execute monitoring without having specified a monitor command BRS WRS Parameter error A parameter is invalid for a reason other than those given above 7 Communication error An error has occurred during communication Checksum error Value of checksum differs Bit omitted or changed characters Internal buffer overflow The amount of data received exceeded stipulated value No end of process response is returned from the CPU for reasons such as CPU power failure timeout CPU processing error The CPU has detected an error during processing A Cancel PLC command was issued during execution of a Internal error command other than a Load PLD or Save PSV command An internal error was detected See Table 6 14 Detailed Error Codes for more information Command error Data count out of range Monitor error Timeout error IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 39 If a parameter error occurs the detailed error code field indicates the number of the faulty parameter If
81. 0001 0512 to CPU1 and E0513 1024 to CPU2 CPU1 10001 _ E0010 Ik a E0513 X00502 Pa 10003 eS Sel CPU2 K sn X00503 E0010 O DN Y00603 O X00501 X00502 E0513 10003 F040202 VSD Figure 4 5 Shared Relays E Using the configuration function you can define the data latch range at power failure for devices whose operation results are to be latched when power is turned off By default all shared relays E are non latched A non latched device will be cleared to OFF 0 when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Devices command from WideField3 or WideField2 A latched device retains its operation result even after power off and power on and is cleared to OFF 0 when you execute a Clear Devices command from WideField3 or WideField2 When using shared or extended shared relays E observe the precautions given below AN CAUTION 1 Index modification of shared or extended shared relays E When applying index modification to a shared or extended shared relay E of the own CPU ensure that the resultant relay number does not exceed the range specified for the own CPU in the configuration Otherwise data held by a shared or extended shared relay E of other sequence CPU modules are overwritten and operation results are not correctly reflected x00503 E0010 Y007
82. 00035 v02 L00001 to L00016 including L00003 are refreshed L00033 to L00048 including L00035 are refreshed F040306 VSD Figure 4 14 Link Relay L Link Refreshing Range Link Register W For an instruction that handles word data the link register W specified in the instruction is refreshed For an instruction that handles long word data or IEEE single precision floating point data the link register W specified in the instruction and the data in link register W 1 are refreshed For an instruction that handles two or more words of data the specified range of words is refreshed if the range is specified by a constant while only the first word is refreshed if the range is specified by a register M035 J MOV D00001 W00012 H wo0012 is refreshed L M035 T MOV W00030 D00034 H w00030 and W00031 are refreshed M035 BMOV W00051 D00051 5 W00051 to W00055 are refreshed M035 voa T MOV D00001 W00061 W00061 is refreshed F040307 VSD Figure 4 15 Link Refreshing Range for Link Registers W IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 17 TIP Link relays L and link registers W specified in a program are included in link refreshing irrespective of whether the relevant instructions are executed If you want to include all link relays L and link registers W in link refreshing include the following code in your program
83. 01 NEST3 A01 P2 0 u01 Z106 x 64 Data of U01 is destroyed by NEST3 instruction MRET F0613081 VSD Figure 6 38 Example of Macro Device Separation when Nesting Macro Instructions IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 52 6 13 5 Handling Macro Instruction Errors When creating a program using a macro instruction tool an error is generated if There are two or more macro instructions of the same name Amacro instruction specified in a macro call MCALL is not found Amacro instruction entity contains two or more macro return MRET instructions An error is also generated and the special relay M201 for instruction processing errors is set to ON if A macro return MRET instruction is executed before a macro call MCALL special register Z022 contains the error code 2501 The depth of macro call nesting exceeds 7 levels special register Z022 contains the error code 2502 An error detected within a macro instruction entity is seen by the user as an error of the macro instruction Thus the user can know which parameters were passed to the macro instruction AN CAUTION Any error detected by self diagnosis except for a memory checksum error within a macro instruction entity is also seen by the user as an error of the macro instruction execution Table 6 21 Error Codes for Macro Instructions 2501 There is no return destination Instruction Macro instruction processing error 2502 The max
84. 03 is 006027 Y00702 10003 N Make sure the relay number does not exceed the range set for the own CPU E040203 vsp Figure 4 6 Precautions when Using Shared or Extended Shared Relays E 1 of 2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 9 AN CAUTION 2 Block move and operation of multiple devices When using shared or extended shared relays E in an instruction for transferring or operating data held by multiple devices ensure that the specified range of these relays does not exceed the range specified for the own CPU in the configuration Otherwise data held by shared or extended shared relays E of other sequence CPU modules are overwritten and so operation results are not correctly reflected X00601 X00604 psps 4 1751715155 4 X00601 X00602 Hie Make sure the range does not exceed the range set for the own CPU Fo40204 vD Figure 4 7 Precautions when Using Shared or Extended Shared Relays E 2 of 2 3 Simultaneity of data Using the configuration function you can select either Simultaneous or Non simultaneous for simultaneity of data of shared devices If you select the Simultaneous option simultaneity of data is guaranteed for units of devices shared relays E registers or extended shared relays E registers to be refreshed where one of the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 sequenc
85. 1 3 11 1 3 26 Method of Input Interrupt Processing This section describes input interrupt processing input interrupt processing control interrupt timing and priority of interrupts Input Interrupt Processing The sequence CPU module executes an input interrupt program when it detects the rising edge of an interrupt input from an input module You can register a maximum of four input interrupt programs with the sequence CPU module using input interrupt instructions INTP instructions The module can accept a maximum of eight concurrent interrupts Input interrupt programs are executed in the order of occurrence of their interrupt factors If any interrupt factor occurs during execution of an input interrupt program the factor is processed when the input interrupt program completes execution ee Interrupt factor 1 Interrupt factor 2 Executed when interrupt I N DR i y program 1 finishes i Interrupt program 2 A H HE gt Interval of waiting for completion of interrupt program 1 Interrupt program 1 F031101 VSD Figure 3 28 Input Interrupt Processing AN CAUTION Do not register an input interrupt program for an input module with two or more CPU modules Otherwise input interrupt processing may fail to be executed Do not use a TIMER instruction in any input interrupt program because the instruction may not work correctly IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 27
86. 1 and CPU2 have 512 shared relays and 512 shared registers Table 3 3 Durations of Interference with the Scan Time by Shared Refreshing Running as a Peripheral Process Duration of Shared Refreshing Other Sequence CPU Module F3SP22 28 38 53 58 159 0 916ms Duration of Synchronization Processing 1 138ms Duration of Interference with Scan Time Duration of Synchronization Processing 1 138ms Duration of Interference with Scan Time of Peripheral Processing Duration of Shared Refreshing 0 916ms F3SP21 25 35 3 908ms 1 138ms 1 138ms 3 908ms Table 3 4 Durations of Interference with the Scan Time by Shared Refreshing Running as a Control related Process Duration of Shared Refreshing Other Sequence CPU Module F3SP22 28 38 53 58 159 0 916ms Duration of Synchronization Processing 0 866ms Duration of Interference with Scan Time Duration of Extended Shared Refreshing plus Duration of Shared Refreshing 1 782ms Duration of Interference with Scan Time of Peripheral Processing 3 908ms F3SP21 25 35 0 866ms 4 774ms IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 19 3 9 3 CPU Service CPU service exchanges data and process commands between the sequence CPU and a BASIC CPU CPU service is processed concurrently with instruction execution so it does not affect the scan time The sequence CPU does not execute th
87. 1024 VON CAUTION Do not write to a special relay including those not listed in tables in this section e g M067 to M096 unless otherwise stated Special relays are used by the sequence CPU module Writing to these relays incorrectly may lead to system shutdown or other failures Using forced set reset instruction in debug mode is also prohibited AN CAUTION Special relays with index modification cannot be specified as destinations for data output and if specified will result in instruction processing errors during execution AN CAUTION Special relays cannot be specified as output destinations in block transfer and table output ladder instructions and if specified will cause instruction processing errors during execution Block transfer instructions BMOV BSET SMOV etc Table output instructions ULOGR FIFWR etc IM 34M06P13 01E 4th Edition Jan 31 2012 00 Appendix 1 2 Utility Relays Appx 1 2 Utility relays are used to provide timing in a program or issue instructions to the CPU module Table Appendix 1 2 Utility Relays Utility Relays Always ON Function Always OFF Description Used for initialization or as a dummy contact in a program 1 Scan ON at Program Start Turns on for one scan only after a program starts execution 0 01 s Clock Generates a clock pulse with a 0 01s period 0 02 s Clock 0 1 s Clock Generates a clock pulse with
88. 12 03E The instruction execution time varies somewhat depending on the contents of the input parameter or output parameter devices or the number of devices included in data transfer The execution time lengths listed in the List of Ladder Sequence Instructions are typical Use these values of the instruction execution time for reference purposes only when calculating the scan time The instruction execution time varies somewhat with the conditions under which an instruction is executed as shown below Use the instruction execution time T values given in the List of Ladder Sequence Instructions to calculate the instruction execution time under certain execution conditions Table 7 5 Calculation of Instruction Execution Time Execution Conditions When executed Instruction Execution Time ys Differential type instruction When not executed F3SP22 F3SP28 F3SP38 T 0 18 F3SP53 F3SP58 F3SP59 T 0 07 16 bits Relay BIN format T 2 5xN1 T 1 0xN1 32 bits T 3 5 xN1 T 1 4xN1 16 bits T 3 5xN2 T 1 4xN2 I O relays X Y defined in BCD format 32 bits T 4 5xN2 T 1 8xN2 sos Basic instruction Index modification T 1 0xN3 T 0 4xN3 Application instruction T Instruction execution time given in List of Ladder Sequence Instructions N1 Number of relay devices N2 Number of relay devices defined in BCD format N3 Number of index modified devices
89. 16 terminal basis Other Combinations of CPU Modules You may not use the same output module with multiple CPUs Configure all CPUs that do not use the output module so that the output module is set to Not Used IM 34M06P13 01E 4th Edition Jan 31 2012 00 AN CAUTION When using a Direct Refresh DREF instruction Set the output relays Y to be refreshed by a DREF instruction of a program to the option Not Used If you set them to the option Use or Use with SCB the values one scan earlier may be overwritten with the values output by the DREF instruction because of the timing of output refreshing which is executed concurrently with instructions E Specifying Data Code Specify whether data held in I O relays X Y should be handled as BIN data or BCD data when they are used in a Compare Arithmetic or Move instruction All internal operations are based on BIN data For this reason if you set the data code of an I O relay to BCD data is automatically converted from BCD to BIN for an input relay and from BIN to BCD for an output relay This option enables you to handle data easily without worrying about the data representation during programming especially in cases where data handled by external equipment are in BCD data code By default I O relays of all I O modules are handled as BIN data You can specify the data code on 16 relay basis E Specifying Input Sampling Interval Se
90. 2 E0001 to E2048 2048 points max for all CPUs Extended shared relay E combined in increments of 32 E2049 to E4096 AN CAUTION The starting number for extended shared relays E is always E2049 even if the range of shared relays E used is less than 2048 Apply the same allocation of shared extended shared relays E to all CPUs If the allocation differs among CPUs shared refreshing will not execute correctly and as a result operation result will not be correctly reflected Shared relays CPU 1 CPU2 o CPU 4 E0001 y i i CPU 1 gt 256 points 256 points 256 points J shared relays E0257 amp 32 fp F CPU 2 1024 points 1024 points aera 1024 points pi shared relays E1281 M E lt n CPU 3 512 points 512 points 512 points T shared relays Eia ER o o aes ae 256 points 256 points 256 points J shared relays Extended shared relays CPU 1 CPU 2 CPU 4 E2049 N CPU 1 1024 points 1024 points 1024 points gt extended We Se ce ala Shared relays E3073 CPU 2 256 points 256 points aie 256 points gt extended J shared relays po S CPU 3 E3329 512 points 512 points 512 points gt extended Looe shared relays E3841 gt CPU 4 256 points 256 points 256 points gt extended area ee ere J shared relays F040205 VSD Figure 4 8 Example of Shared and Extended Shared Relay E Allocation with Four Sequence CPU Modules Installed IM 34M06P1
91. 3 01E 4th Edition Jan 31 2012 00 4 3 4 11 Link Relays L and Link Registers W This section describes link relays L link registers W their settings system numbers as well as the link refreshing range Link relays L are 1 bit variables used for data communications with FA link systems and FL net systems Link registers W are 16 bit variables used for data communications with FA link systems and FL net systems AN CAUTION In this section FL net nodes are called stations Link relays L and link registers W are devices used to exchange data with other programmable controllers via FA link modules and FL net OPCN 2 Interface modules Before using link relays specify the range of links for both the local and remote stations Using the configuration function you can define the data latch range at power failure for devices whose operation results are to be latched when power is turned off By default all link relays L and link registers W are non latched A non latched device will be cleared to OFF 0 when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Devices command from WideField3 or WideField2 A latched device retains its operation result even after power off and power on and is cleared to OFF 0 when you execute a Clear Devices command from WideField3 or WideField2 IM 34M0
92. 3 714 715 716 Slot numbers 701 to 716 EA mi o o o o 2g ge E a F010303 VSD Figure 1 3 Slot Numbers 2 of 2 Install fiber optic FA bus type 2 modules in both the main unit and a subunit and connect these modules with a fiber optic cable You can attach up to seven subunits to the main unit Subunit numbers are assigned by setting the rotary switch on the front panel of each fiber optic FA bus type 2 module IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 15 1 3 3 I O Relay Number Each input relay X or output relay Y number is defined as a slot number followed by an I O relay number The I O relay number is a number corresponding to each terminal of an I O module Example The output relay number for terminal 6 of an F3YCO8 ON module installed in slot 005 is defined as follows Yo05 06 i A Terminal number Slot number 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 lt Slot numbers Oo o oO o o Y00506 F3YC08 0N F010304 VSD Figure 1 4 Output Relay Number The input and outp
93. 30 30 32 30 31 2C 31 36 42 39 03 0D Bree Hexadecimal ASCII code The ASCII codes are added together as 30 31 30 31 41 42 52 44 58 30 30 32 30 31 2C 31 36 3B9 in hexadecimal The checksum is the low order byte B9 of the sum 3B9 in hexadecimal expressed as a character string B9 F061108 VSD Figure 6 31 Checksum Calculation ETX End of Text Code A control code indicating the end of text The corresponding character code is 3 CR Carriage Return Code A control code indicating the termination of text The corresponding character code is 0D which is the ASCIl code decimal numeral of 13 This code is required only if the configuration item End character is set to Yes IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 37 E Response Format and Elements The format of a response that is sent from the FA M3 to a higher level computer or monitor is shown here For details on individual elements and characters used see E Command Format and its Elements given earlier in this section When Communication is Normal Variable length Command response seia ee a aaa response only if 1 ae enabled accordingly 1 in the configuration F061109 VSD Figure 6 32 Response Format when Communication is Normal When communication ends successfully the string OK is returned along with a command response When Communication is Abnormal No of
94. 3072 Number of file registers B 32768 32768 32768 262144 262144 262144 Number of link registers W 8192 8192 8192 16384 16384 16384 Number of special registers Z 1024 1024 1024 1024 1024 1024 Number of labels 1024 1024 1024 1024 1024 1024 Number of input interrupt processing routines 4 4 4 4 4 4 Decimal constant 16 bit instruction 32 bit instruction 32768 to 32767 2147483648 to 2147483647 Hexadecimal constant 16 bit instruction 32 bit instruction 0 to FFFF hexadecimal number 0 to FFFFFFFF hexadecimal number Character Constants string constant 16 bit instruction 32 bit instruction e g AB e g ABCD IEEE single precision floating point constant 32 bit instruction e g 1 23 3 21 Approximately 3 4x10 to 3 4x10 Index constant 0 to 2047 Program size ROM resident Program Tag Name Definition size 10K steps max 30K steps max 56K steps max 120K steps max 254K steps max 360K steps max ROM resident size Program Tag Name Definition 120K steps max 360K steps max Number of program blocks 1024 max Basic Number of instructions 37 instructions Application instructions 329 Number of macro instructions 256 max Basic I
95. 3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPUs support the high speed processing of Application Instructions where these devices are used Extended shared relays E Extended shared registers R Link registers for FA link system 3 or later W File registers B IM 34MO06P13 01E 4th Edition Jan 31 2012 00 9 6 9 6 Instructions The following instructions have been added to the list of instructions available with the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPU modules Load Differential Up Load Differential Down Logical Differential Up Logical Differential Down Logical Differential Up Using Specified Device Logical Differential Down Using Specified Device Inverter Flip Flop Activate Sensor Control Block Inactivate Sensor Control Block Disable Sensor Control Block Enable Sensor Control Block Read Free Run Timer IM 34MO06P13 01E 4th Edition Jan 31 2012 00 10 10 1 10 2 10 1 Difference between F3SPO0 OS and F3SPOO ON O0H This chapter describes the difference in function and specifications between the F3SP28 38 53 58 NN OH old models and the F3SP28 38 53 58 59 OS new models CPU modules Partial Download Functions The new models are provided with partial download functions which allow only specified blocks or macros to be downloaded to a CPU overwriting corresponding blocks or macros of a program that has been
96. 4MO06P13 01E 4th Edition Jan 31 2012 00 8 6 8 2 Updating Error Status Indicators after Correcting Moderate or Minor Failures After eliminating the cause of a moderate or minor failure initialize the states of special relays M special registers Z and LED indicators as instructed below E Updating Error Status after Removing Moderate Failures To reset special relays M and special registers Z as well as turn off the ERR LED indicator after eliminating the cause of a moderate failure use the following procedure 1 Turn on the power again 2 Switch the sequence CPU to Run or Debug mode using WideField3 or WideField2 m Updating Error Status after Removing Minor Failures To reset special relays M and special registers Z as well as turn off the ALM LED indicator after eliminating the cause of a minor failure use the following procedure 1 Turn on the power again 2 Switch the sequence CPU to Run or Debug mode using WideField3 or WideField2 3 Perform Cancel Alarm IM 34MO06P13 01E 4th Edition Jan 31 2012 00 9 1 Differences from F3SP25 and F3SP35 Sequence CPUs This chapter describes the differences from F3SP25 and F3SP35 sequence CPUs You must read this chapter before replacing sequence CPU module F3SP25 or F3SP35 with sequence CPU module F3SP22 F3SP28 F3SP38 F3SP53 or F3SP58 ON OH 9 1 Number of I O points Specification Comparison of Functional Specifications
97. 61024 is followed by L W70001 The above rule applies when the number of link relays or registers to be used is defined as 1024 If the number used is 2048 L Wn2048 is followed by L Wn0001 If the number used is 8192 L W08192 is followed by L W10001 Non latching type Non latching type Non latching type IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 5 3 4 Operation Processing Method This section outlines data operation processing scan processing in the sequence CPU module Details are explained in subsequent sections The CPU employs a stored program iterative operation method In this method a created program is pre stored in the memory of the sequence CPU module The sequence CPU executes instructions one at a time starting from the first step of the program After executing the last step in the program the CPU performs required processing such as self diagnosis It then repeats the instructions from the first step Each of these iterative cycles is called one scan and the time required for one scan is called a scan time In the case of F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 CPU modules the CPU executes instructions and peripheral processes concurrently to perform each scan in a shorter time Common processing instruction execution input refreshing output refreshing and synchronization processing are classified as a system of control related processes while tool servi
98. 6P13 01E 4th Edition Jan 31 2012 00 4 3 1 Link Relays L 4 12 Link relays are used to exchange data with other programmable controllers via FA link modules or FL net OPCN 2 Interface modules In programs you can use these relays for example for contacts a and b coils and application instructions In addition you can exchange ON OFF data between CPUs by using link relays L of the local station as coils and those of remote stations as contacts Station 1 10001 10010 i gt O L0513 X00502 Pa 10003 i oo bS l P F J Station n Zoos x00603 Lodo T Y00703 i W he X00601 X00602 10513 i E 10003 i Figure 4 9 Link Relays L The relay number is coded as Lmnnnn where m System number 1 0 to 7 nnnn Link relay number Table 4 2 Range of Link Relay Numbers F040301 VSD Configuration Range FA link H Module High speed configuration 1 to 1024 Fiber optic FA Link H Module Normal configuration 1 to 2048 FL net OPCN 2 Interface Module 1 to 8192 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 3 2 Link Registers W 4 13 Link registers are used to exchange data with other programmable controllers via FA link modules or FL net OPCN 2 Interface modules In programs you can read from or write to link registers on 16 bit or 32 bit basis using application instructions When you use a long word the low order 16 bits a
99. 6S Device F3SP28 3N 3S F3SP58 6H 6S F3SP59 7S Remarks F3SP53 4H 4S Range Quantity Range Quantity Range Quantity Input relay x x00201 to X71664 X00201 to X71664 X00201 to X71664 The range used discontinuous 4096 discontinuous 8192 discontinuous 8192 depends on the Output relay y Y00201 to Y71664 Y00201 to Y71664 Y00201 to Y71664 module type discontinuous discontinuous discontinuous Internal relay 1 1100001 to 116384 16384 100001 to 132768 32768 100001 to 165535 65535 Shared relay E0001 to E2048 2048 E0001 to E2048 2048 E0001 to E2048 2048 These devices default to zero in quantity Be Non sure to configure the Fear n o E E2049t0E4096 2048 E2049 to E4096 2048 E2049t0E4096 2048 devices when using multi CPU configuration Non Used in FA link and Link relay latched L a 8192 a 16384 a 16384 FL net type communications Special relay M M0001 to M9984 9984 M0001 to M9984 9984 M0001 to M9984 9984 100 us Configurable for up to Timer T0001 to T0016 T0001 to T0016 T0001 to T0016 16 timers 1ms Timer j Om imac T l l Configuration limit 100 ms T0001 to T2048 2048 in T0001 to T3072 3072 in T0001 to T3072 3072 in correlated to counters total total total I C 1 mer Continuous 100 ms timer Timer Latch d Configuration limit Counter type C 1C0001 to C2048 C0001 to C3072 C0001 to C3072 ap to Timers Data register TA D D00001 to D16384 16384 D00001 to D32768 32768 D00001 to D65535 65535 File register o ie eyi 221 Pore
100. 8 and F3SP59 sequence CPU modules SEE ALSO For details on index modification see Section 1 10 in Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 33 E Configuring Shared and Extended Shared Registers R for Multiple CPUs Configure the range of shared and extended shared registers R to be used by each CPU in a multi CPU system configuration where add on CPU modules are installed You can allocate any number of registers to each CPU in increments of 2 Table 4 13 Configuration of Shared Registers R F3SP22 F3SP28 F3SP53 F3SP38 F3SP58 F3SP59 Default Configuration Range Shared register R 1024 max for all CPUs combined in increments of 2 Pavice Extended shared Capacities 3072 max for all CPUs combined in increments of 2 Extended shared registers R can only be used with sequence CPU modules F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 and F3SP59 AN CAUTION Assign the same range of shared and extended shared registers R for all CPU modules No error will result however even if the range is not the same among the CPU modules Rather data in other CPU modules may appear wrongly assigned to register numbers or data in the CPU module may appear that way when referenced from other CPU modules Shared registers
101. 8400 8 bits Even 1 bit Communication mode 5 38400 8 bits None 1 bit Communication mode 6 57600 8 bits Even 1 bit Communication mode 7 57600 8 bits None 1 bit Communication mode 8 115200 8 bits Even 1 bit Communication mode 9 115200 8 bits None 1 bit The personal computer link functions are set to communication mode 0 when the sequence CPU module is shipped from the factory the CPU memory is cleared or the functions are not configured AN CAUTION Be careful when setting the transmission rate WideField3 or WideField2 supports all of the communication modes listed above However you should first refer to the user s manual of the personal computer that runs WideField3 or WideField2 to check available transmission rates and data formats Then temporarily change the transmission rate of the personal computer link functions using WideField3 or WideField2 to make sure the Sequence CPU module can communicate with the personal computer in the communication mode you want to use Finally configure the personal computer link functions according to that communication mode The personal computer link functions automatically reverts to the previous transmission rate if communication is not established after a temporary change in the transmission rate If you configure the personal computer link functions using a communication mode not supported by the personal computer all communications with the
102. A CAUTION Precautions when setting Terminal Usage in Input Output Setup Configure the input module on long word basis i e 32 relays 32 terminals terminals 1 to 32 or terminals 33 to 64 and the output module on word basis i e 16 relays or 16 terminals If you set either of terminals 1 to 16 or terminals 17 to 32 to Used and the other to Not Used all terminals 1 to 32 are refreshed on long word basis Let s suppose you configured the input module incorrectly on word basis for example you set terminals 1 to 16 to the option Used with normal scan and terminals 17 to 32 to the option Use with SCB Since input refreshing is performed on long word basis input X relays used under a normal scan are refreshed by the Refresh instruction of the sensor control block when the normal scan is in progress Consequently the simultaneity of data is not guaranteed before and after the refreshing Simultaneity of data is also not guaranteed for input X relays used in the sensor control block When using output modules and special modules with YOOOOO output relays Y in a multi CPU system configuration Combination of F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 CPU Modules You can output data from multiple sequence CPU modules separately to the output relays Y of the same output module on 16 relay basis To do this set the unused output terminals to the option Not Used on
103. Asensor control block number is determined by adding 1 to the end of a number assigned to regular blocks You cannot access the blocks numbered from 100 to 1024 CPU personal computer link functions Asensor control block number is determined by adding 1 to the end of a number assigned to regular blocks You cannot access the blocks numbered from 100 to 1024 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 9 3 9 2 Configuration Specification F3SP25 F3SP35 F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 Internal relay I 8192 units for 16384 units for No configuration is required for these types of both types of both types of Shared Relay E eae ite eb eae relays Data register D 8192 units for both types of registers No configuration is required for these types of i Shared register R combined registers Device capacities 100 s timer No 16 max F3SP22 F3SP28 and F3SP53 2048 max for Jems itim r 46 max all timers combined i F3SP38 F3SP58 F3SP59 3072 max for all timers combined Error time action Operating mode in Sensor CB scan timeout No Yes case of error Terminal usage Use Not used Configurable on 16 point basis including Module used Not used Configurable on a module basis Use Not used Use with Sensor CB Note Input sampling interval 16ms 1ms configurable on a module 16 ms 1 ms 250 us 62 5 us Always
104. BLOCKmH INACT BLOCKS H T Condition Condition II ACT BLOCKn Y INACT_ BLOCK1 x INACT BLOCK H y Block 2 t Condition Block 3 H Condition Block 1 Block m Condition t Condition Block n Condition F060408 VSD Figure 6 10 Example Where Block Activation is Controlled by a Scheduler Create a scheduler using block 1 which is active by default IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 5 6 5 1 6 5 2 6 12 Debugging Functions This section describes the following functions forced set reset function for forcibly changing the status of a relay functions for changing setpoints current values and data values of registers as well as the stop refreshing function for stopping I O refreshing link refreshing and shared refreshing Forced SET RESET A forced SET RESET forcibly sets a specified bit device to ON OFF regardless of program execution You can apply forced set or forced reset to a maximum of 32 bit devices at one time Only bit devices are supported i e X Y I E L T and C devices If a forced SET is applied to a timer T or a counter C the timer expires or the counter terminates A forced SET or forced RESET remains valid until you perform any of the following Cancel the forced set or forced reset Change the operating mode to RUN mode Turn off the power Download a program or other data AN CAUTION Before turning off the power cancel all instanc
105. Chapter C3 of FA M3 Programming Tool WideField3 IM 34M06Q16 O0E or Chapter B23 of FA M3 Programming Tool WideField2 IM 34M06Q15 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 3 3 3 1 3 3 Operation in Case of Momentary or Complete Power Failure This section describes settings for operation in case of momentary power failure specifying the momentary power failure detection mode as well as operation in case of complete power failure specifying the data latch range in case of complete power failure Operation in Case of Momentary Power Failure Two types of power failure detection mode are available for detecting a momentary power failure the standard mode and the immediate detection mode The CPU operates differently in case of a momentary power failure depending on the type of power failure detection mode selected The immediate detection mode can be selected by configuration only when the F3PU10 00 F3PU16 0N F3PU20 00 F3PU26 0N F3PU30 00 or F3PU36 00 power supply module is used E Standard Mode If a momentary power failure occurs the sequence CPU module records the date and time in its error log file The sequence CPU module suspends processing until the power is restored This causes a delay in the scan time and timer update process When the power is restored the sequence CPU module resumes execution at the point where processing was suspended A program can detect a momentary power failure
106. Data latch range at power failure 10K 10240 steps 30K 30720 steps 56K 57346 steps F3SP38 F3SP58 120K 122880 steps 254K 260096 steps Interrupt definitions Circuit comments subcomments F050301 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 Blank Page 6 1 6 Functions This chapter describes the functions provided by the sequence CPU module such as the execution of specified blocks and debugging operations 6 1 Function List The following tables summarize the functions provided by the sequence CPU module and add on CPU modules Table 6 1 Functions Provided by Sequence CPU Modules and Add on CPU Modules Functions of Sequence CPU Module Operation setup functions Function Overview Specify the operating mode of the sequence CPU module and its actions Constant scan Executes a sequence program at certain time intervals Executing all blocks specified blocks Specifies how an executable program is processed Specified blocks are executed using ACT and INACT instructions Debugging functions Functions that support debugging such as forced set reset Program protection Protect programs by means of password These functions have two modes executable program protection and block protection Online editing Make on line modifications or changes to a program in the program memory of the sequence CPU module Sampling trace functions Acquire an
107. Devices and Chapter 5 Programs Configuration of a ladder diagram Ladder symbols Mnemonic language Program input for simulation Performance check End lt Chapter 1 General Description Chapter 2 Basic Instructions and Chapter 3 Application Instructions of Sequence CPU Instruction Manual Instructions 3rd or later edition Verification of basic logic Program modification lt lt Chapter 6 Functions End of flow Program storage on floppy hard disk or in ROM pack Target machine Start Wiring I O verification Debugging Trial operation End Input Verification of I Os with LED lamps Output Forced SET and RESET instructions lt Chapter 6 Functions Program downloading Program modification lt Chapter 6 Functions End of flow Program storage on floppy hard disk or in ROM pack F000001 VSD IM 34MO06P13 01E 4th Edition Jan 31 2012 00 E Other User s Manuals Be sure to read each of the following manuals in addition to this manual For information on the instructions used with sequence CPUs refer to Sequence CPU Instruction Manual Instructions IM 34M06P12 03E For information on the commands and responses of personal computer link functions Personal Computer Link Commands IM 34M06P41 01E
108. E ALSO For details on link data updating and link refreshing see FA Link H Module Fiber optic FA Link H Modules IM 34M06H43 01E and FL net OPCN 2 Interface Module IM 34M06H32 02E IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 21 3 10 2 Link Refreshing Link refreshing reads data from or writes data to devices such as link relays L and registers W of the sequence CPU module via an FA link module or FL net OPCN 2 interface module installed in the local unit It maps the link data in the storage area of the sequence CPU module to those of the FA link module The sequence CPU module reads the link data of the FA link module or FL net OPCN 2 interface module automatically so data communication is transparent to a user Station 1 X00502 X00501 L00033 L00001 Station 1 link relay area X00601 L00001 L00033 Station 1 Jink register areal Station n link register area F Ww i L00003 X00604 N Figure 3 20 Link Refreshing IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 22 E Execution of FA Link Refreshing FA link refreshing is executed in peripheral processing Link refreshing runs concurrently with instruction execution so it does not affect the scan time Peripheral processes oo Common processing Shared refreshing Input refreshing 4 Output refreshing oe Link refreshi
109. I O comparison error ad j Z028 comparison pock No o error I O comparison error Z029 instruction No Store as a bit pattern the slot number for which an I O error has occurred Z033 Main unit s ith 1 0 Z034 Subunit 1 Z033 to O error lot no with I O error Z035 Subunit 2 Z040 16 2 1 Z036 Subunit 3 0 bel 1 0 Z037 Subunit 4 Z038 Subunit 5 Z039 Subunit 6 Z040 Subunit 7 Z041 Main unit Z042 Subunit 1 Slot number Z043 Subunit 2 16 1 Z044 Module Subunit 3 fof 4 fo recognition i Z045 J Subunit 4 0 No modules are recognized Z046 Subunit 5 Unable to read write 1 Modules are recognized Z047 Subunit 6 Z048 Subunit 7 Z089 Main unit Slot number Z090 Subunit 1 16 1 Z091 Subunit 2 O j 110 Subunit Fiber optic FA bus module Z092 Commu Subunit 3 0 Normal transmission line Z093 nication error Subunit 4 Unspecified transmission line or slot Loaded with a wrong module Z094 Subunit 5 1 Abnormal transmission line Subunit communication error or Z095 Subunit 6 Sub unit transmitter switching has occurred Z096 Subunit 7 For information on error numbers codes to be saved in these special registers see Table 8 2 Details of Self diagnosis SEE ALSO For details on the Z089 to Z096 special registers Communication error slot see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 Uti
110. IM 34MO6P12 03E AN CAUTION The NMOUT instruction takes effect only if executed within a macro instruction that has been called by NCALL that is an input macro It is ignored if executed within a macro instruction that has been called by MCALL Nesting Input Macros Macro and input macro instructions when combined may be nested up to 8 levels IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 56 6 13 9 Structure Macro Instructions The Structure Macro Instruction passes a number of parameters collectively in a structure to a macro instruction By using a structure it simplifies data passing and improves representation in cases where there are many related parameters Passing all data in a structure called MITAKA Ladder block Macro instruction ROAD S 1 at ery H ROAD MITAKA 0 SIRCT Q1 Road_Val if MOV Qt Road_Frm Dooot H S ROAD FUCHUU 0 100200 if MITAKA is passed and 100205 if FUCHUU is passed Structure object definition MITAKA Road_Frm D00100 MITAKA Road_To D00101 Structure type definition CITY MITAKA Road_Val 100200 sae bas Road_Frm WORD Road_To WORD FUCHUU Road_Frm D00102 Road Val RELAY FUCHUU Road_To D00103 ere T tee FUCHUU Road_Val 100205 F061310 VSD Figure 6 40 Benefits of Structure Macro Instructions SEE ALSO For details on structures see FA M3 Pro
111. M034 BSET 0 L00001 64 M034 a BSET 0 woo001 1024 F040308 VSD Figure 4 16 To include L00001 to L01024 and W00001 to W01024 in Link Refreshing If link relays L and link registers W are specified by index modification define the index modification range as shown below so that they will be included in link refreshing M034 H BSET 0 wo0021 10 F040309 VSD Figure 4 17 When Using Registers W00021 to W00030 with Index Modification AN CAUTION 1 Index modification indirect specification Index modification indirect specification must not be made across different systems When specifying link relays and registers with index modification or indirect specification see TIP to link refresh to ensure that all relevant devices are link refreshed 2 Block move and operation involving multiple devices Block move or operation for multiple devices must not be made across different systems Be careful especially when specifying the number of bytes of data to be moved or the number of devices for operation using devices When specifying the number of bytes of data to be moved or the number of devices for operation using devices see TIP to ensure that all relevant devices are link refreshed 3 Multi CPU configuration Multiple CPU modules cannot share the same FA link module or FL net OPCN 2 interface module Ensure that only one CPU module is accessing an FA link module or FL net OPCN 2
112. Number of modules calculated on a 16 point basis 2 x 4 8 12 us x 8 96 us Shared refreshing When no add on CPU module is installed 0 00 ms Input refreshing Number of modules calculated on a 16 point basis 2 x 4 8 6 us x 8 48 us Synchronization Processing Number of modules calculated on a 16 point basis 2 x 4 8 8 us x 8 64 us Peripheral processing Minimum peripheral processing time if not yet defined 0 2 ms Scan time which is the sum of all time spans listed above The output refreshing time and the minimum peripheral processing time are excluded from scan time calculation because the sum of these time spans is smaller than the program execution time IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 5 When the CPU Is F3SP53 F3SP58 or F3SP59 Module configuration User program Four 32 point input modules Four 32 point output modules 20K steps 20K steps for the ladder program below consisting of instructions only where the average execution time of these instructions is assumed to be 0 035 us ONCUWT onv TN E E 32 point input 32 point output module s modules F070302 VSD Figure 7 3 Module Configuration of F3SP53 F3SP58 or F3SP59 Sequence CPUs 10001 10002 10064 CY LU 10065 10066 10128 i I 10129 10130 10192 Figure 7 4 Program fo F070302_2 VSD r F3SP53 F3SP58 or F3SP59 Table 7 4
113. O Function 1 special relay M2001 1 O i eg AE E SNE EAEE ETE E A E E a E See X00501 X00502 10003 Block 2 OE _ Function 2 a pa i INACTIVE special relay M20020 Block m SS gt Boek m X00503 Y00603 Function m ACTIVE Ik a special relay Ma0om 1 X00501 X00502 10004 Block n x O Meaig lI LU Function n ae 10003 INACTIVE ao special relay M200n 0 F060402 VSD Figure 6 4 Execution of Specified Blocks Executing block 1 and block m only IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 4 3 Operation When Specified Blocks Are Activated A block that is specified for activation by an ACT instruction is initialized at the end of that scan and is actually started in the next scan Executable program Block 1 Function 1 Block 2 Function 2 Block m Function m Block n Function n Executable program Block 1 Function 1 Block 2 Function 2 ATE seactas Sp Block m Function m Block n Function n Figure 6 5 Operation When Specified Blocks are Activated Block 1 Function 1 nth scan Special relay M2001 1 o y ACT Block 2 Next scan n 1 th scan PY Block 1 Special relay Function 1 M2001 1 Block 2 Special relay Function 2 M2002 1 ACT Blockm Next scan n 2 th scan Block 1 Function 1 Special relay M2001 1 Block 2 Function 2 Sp
114. ON Refreshing of input relays X and output relays Y for external equipment specified in the sensor control block cannot be stopped IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 6 6 6 1 Program Protection You can protect your programs against unauthorized access for security reasons There are two modes of protection executable program protection and block protection Protection is enabled by defining a password using WideField3 or WideField2 A password must consist of eight alphanumeric characters beginning with a letter The protection information is saved with an executable program or block by WideField3 or WideField2 AN CAUTION Program protection is only designed to prevent unauthorized read access It does not protect against program deletion or CPU operation modification due to erroneous operations or writing Executable Program Protection Executable program protection protects an entire executable program When this protection is enabled all functions that act upon an executable program downloading uploading monitoring online editing etc are prohibited X00503 X00504 Personal computer X00501 X005 X00503 Monitoring debugging operation and printing Y00601 O Uploading x ca F060601 VSD Figure 6 12 Executable Program Protection When executable program protection
115. Operation during Response Wait Time Command Using three letters specify the type of access such as reading or writing from a higher level computer or monitor to the sequence CPU module Parameters These include device name number of devices data etc The actual parameters vary depending on the command used Some commands require no parameters Checksum A checksum can be added to the transmission text for data validation You can select whether to add a checksum in the configuration If checksum is set to Yes a checksum must be appended to a command before transmission from the higher level computer or monitor to the FA M3 Moreover a checksum is automatically appended to the response transmitted from FA M3 If checksum is set to No this element must not be appended to a command How the checksum is calculated is explained below Add the ASCII codes of the characters following the STX character and preceding the checksum Extract the low order byte of the sum and express its hexadecimal value as a character string 2 characters 2 bytes to obtain the checksum IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 36 Transmission text character string i Checksum a O A Range of checksum calculation gt lt i ion gt STX O0 1 0 1 A B R D X 0 0 2 0 1 1 6 BY 9 JETX CR sey 02 30 31 30 31 41 42 52 44 58
116. P01 POMP02 POMP03 Define POMP OUTO1 OUTO2 OUTO3 data structure OUT MCN1 MCN1 SWICH MCN2 SWICH MCN3 SWICH MCN1 POMP MCN2 POMP MCN3 POMP MCN2 Name MCN1 0UT MCN3 OUT MCN3 OUT data sets MCN3 F020403 VSD Easy Data Exchange with Windows based Applications You can select data items such as device names and comments on a Microsoft Excel screen and copy them to WideField3 or WideField2 drag and drop function You can also copy ladder circuits created using WideField3 or WideField2 to Windows applications such as Microsoft Word IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 1 3 1 Basic Operations of Sequence CPU Module This chapter describes the basic operating modes of the sequence CPU module and add on CPU modules as well as their methods of program execution Operating Modes of Sequence CPU Module The sequence CPU module has three operating modes Run mode Debug mode and Stop mode E Run Mode The Run mode is a state in which the sequence CPU module is running a program and is used for actual system operation You can monitor the operating status of a sequence CPU module or devices However you can use none of the debug functions available from the WideField3 or WideField2 programming tool In this mode the RDY and RUN LED indicators turn on E Debug Mode The Debug mode is used when debugging and tuning programs You can execute programs in the same way as with the Run mode In Debug mode you can use d
117. PU4 area Area whose data is used by each CPU F030903 VSD Figure 3 13 Example of Shared Refreshing Configuration In the example shown in the figure above if data need not be shared among add on CPU modules the refreshing intervals of CPU2 CPU3 and CPU4 are shortened if CPU3 and CPU4 CPU2 and CPU4 and CPU2 and CPU3 respectively are excluded from shared refreshing TIP If you exclude a CPU module from shared refreshing its scan time shortens because data updating done by its synchronization process is disabled However this prohibits sharing of data in all areas of the other CPU modules E Simultaneity of Shared Refreshed Data You can specify by configuration whether to maintain simultaneity of shared refreshed data If you select Simultaneous for this configuration item when a sequence CPU module F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 or F3SP76 module is combined with any number of F3SP22 F3SP28 F3SP38 F3SP53 FS3P58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 modules defined as add on CPU modules simultaneity of shared refreshed data is guaranteed by the unit of shared devices shared relays E and registers R or extended shared relays E and registers R being refreshed If anyone of the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 modules is combined with any of the F3SP21 F3SP25 F3SP35 and F3BPOO modules simultaneity of data is not g
118. Refreshing Execution is set to Control Process Each single scan of control related processing refreshes the CPU N s shared relays E registers R or extended shared relays E registers R Note however that when the configuration item Shared Refreshing Data is set to Simultaneous refreshing may be delayed by as much as three scans due to the need for synchronization with the CPU N Reference to a CPU s Own Write Area You can read data in a CPU s write area from other CPUs That is you can read the data alternately from shared relays E registers R and from extended shared relays E registers R in that area during the synchronization process of each scan Note however that when the configuration item Shared Refreshing Data is set to Simultaneous for any of the other CPUs refreshing may be delayed by as much as the longest of those CPUs scans due to the need for synchronization with the slowest CPU CPU2 CPU2 CPU3 Shared refreshing of Shared refreshing of extended Shared refreshing of shared relays registers shared relays registers shared relays registers Data updates Refreshing may be are reflected delayed by three by this common scans of peripheral A processing to ensure processing simultaneity of data Instruction execution Instruction execution Instruction execution Instruction execution H With this common processing it becomes possible to alternately refer to
119. Rogle S ugn 4 36 4 8 4 FA Link Module Status Registers 4 38 4 8 5 Sequence CPU Module Status Registers cee 4 39 4 9 Index Registers V sc ccccccciecccsccdecteseccecdsennceecssascaecaceeceecdansececeeveccatis 4 40 4 10 Fil Registers B erior R 4 41 POE INS ina aaa aaa aA aaRS Ra 5 1 5 1 Programming Language ssssssssseennnrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nenne 5 1 5 1 1 Structured Ladder Language ccceeeeseeeeeeeeeeeeeeesteeeeeeaaes 5 1 5 1 2 Mnemonic Language cecesceeeeeeeeeeeeeeeeeeenaeeeeeeneeeeeeenaas 5 1 5 2 Program Types and Configuration ccccsssccsssereeeesseeeeeseeeeeeseees 5 2 5 2 1 Blocks and Executable Programs 5 2 5 2 2 Component Programs of an Executable Program 4 5 4 5 3 Program Memory ccessececesseeeeeeseeeseeeseeeeseeeseeeseeeseaeseeeseaeseseseeneeeeesees 5 9 PUG COINS associa sence cctecececetenweenctdacscneteawccactcasccaeteasecactensscnctensecnsuanus 6 1 6 1 Function List siosio R 6 1 6 2 Operation Setup FunctionS s ssssssssssnunnnennnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnn na 6 2 6 3 Constant SCAM asosa 6 4 6 3 1 Setting the Constant Scan Time eeeeeeeeeeeeeeeetteeeeeeaes 6 4 6 4 Executing All Blocks Specified BlOCKS cccssstceesereeeeeeeeeeeseees 6 5 6 41 Executing All BIOCKS 00 eee ceeeee ener eeeeenneeeeeeecaeeeeeenaeeeeeeaaes 6 5 6 4 2 Executing Specified BIOCKS eceeceeeeeeeeeeeneeeeeeenteeeeeeaaes 6 6 6
120. S F3SP38 6N 6S F3SP58 6H 6S F3SP59 7S Communications Setup Item Communication mode Connection port for programming tool Used Unused Default Value Mode 0 9600bps even parity Unused Value Range 9600bps Even Parity 9600bps No Parity 19200bps Even Parity 19200bps No Parity 38400bps Even Parity 38400bps No Parity 57600bps Even Parity 57600bps No Parity 115200bps Even Parity 115200bps No Parity Unused Used Checksum CPU personal No Yes No computer link End character Program protection No No Yes No Yes No FA link setup Mapping between FA link and FL net numbers and slot numbers None Yes No Link number from 1 to 8 Slot numbers from 1 to 16 FL net Refreshing Shared Refreshing Common data refreshing mode Peripheral process Peripheral process or Control process Common data refreshing range Shared refreshing range partial disabling of refreshing All nodes All refreshed All nodes or Some nodes Node numbers 1 to 254 Enable Disable refreshing configurable separately for shared relays E shared registers R extended shared relays E and extended shared registers R of each CPU module Shared refreshed data Simultaneous Simultaneous Non simultaneous Shared refreshing mode Peripheral process IM 34M06P13 01E Peripheral process Control process 4th Edition Jan 31 2012 00
121. Standards JIS Class 3 Ground For compliance to CE Marking use braided or other wires that can ensure low impedance even at high frequencies for grounding 1 Japanese Industrial Standard JIS Class D Ground means grounding resistance of 100 Q max Configure and route cables with noise control considerations Perform installation and wiring that segregates system parts that may likely become noise sources and system parts that are susceptible to noise Segregation can be achieved by measures such as segregating by distance installing a filter or segregating the grounding system Configure for CE Marking Conformance For compliance to CE Marking perform installation and cable routing according to the description on compliance to CE Marking in the Hardware Manual IM 34M06C11 01E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 vi Keep spare parts on hand Stock up on maintenance parts including spare modules in advance Preventive maintenance replacement of the module or its battery is required for using the module beyond 10 years For enquiries on battery replacement service for purchase contact your nearest Yokogawa Electric representative or sales office The module has a built in lithium battery Lithium batteries may exhibit decreased voltage and in rare cases leakage problems after 10 years Discharge static electricity before operating the system Because static charge can accumulat
122. U module and add on CPU modules are installed Shared relays E are available with the F8SP21 F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 sequence CPU modules as well as with any add on sequence CPU modules that are combined with one of these sequence CPUs Extended shared relays E are only available if one of the F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 sequence CPU modules is combined with any one or more of these CPU modules installed as add on CPU modules In programs you can use these relays for example for contacts a and b coils and application instructions You can exchange ON OFF data between CPUs by using shared relays E of the own CPU as coils and those of the other CPUs as contacts AN CAUTION If you write data to a device area not belonging to the own CPU data of shared and extended shared relays E of the other CPUs are overwritten and so operation results are incorrectly reflected By default no shared relays are allocated as devices When using add on CPU modules configure the range of shared relays to be used Allocate the same device range for all of the CPU modules Otherwise the shared relays E will not be correctly refreshed IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 8 The following figure shows an example of how specific shared relays are shared if you allocate shared relays E
123. Use a MOV P instruction If you use a BMOV or BSET instruction an error will be generated 2 Set special relay M172 to ON within the same scan as that in step 1 use a DIFU instruction 3 Set special relay M172 to OFF in the scan subsequent to that in step 2 Also stop writing the clock data to special registers Z049 to Z054 in that scan Note that no change is made to the clock data and the data reverts to its original values if the values being set are incorrect The accuracy of clock data is as follows Maximum daily error 8 s 2 s when actually measured The clock accuracy is reset to the maximum daily error of 1 2 s 2 s however when the power is turned off and on again In addition it is possible to input a corrective value from the programming tool If you input a precise corrective value the clock data is corrected during the power off and on sequence thus offsetting the cumulative amount of error IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 38 4 8 4 FA Link Module Status Registers FA Link module status registers indicate the status of FA link Table 4 17 FA Link Module Status Registers FA Link Module Status Registers Type No Name Stored Data Description Z075 Local station number System 1 FA Link Z076 Local station number System 2 FA Link Z077 Z078 Local station number Local station number System 3 FA Link System 4 FA Link Z079 Local station number System 5
124. User s aN Manual eee T REM OUTION Sequence CPU Instruction Manual Functions for F3SP22 0S F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S IM 34M06P13 01E vigilantplant YOKOGAWA IM 34MO6P13 01E Yokogawa Electric Corporation 4th Edition Blank Page Applicable Product Range free Multi controller FA M3 Model Name F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 Name Sequence CPU Modules The document number and document model code for this manual are given below Refer to the document number in all communications including when purchasing additional copies of this manual Document No IM 34M06P13 01E Document Model Code DOCIM Media No IM 34M06P13 01E CD Ath Edition Jan 31 2012 YHQ IM 34MO6P13 01E 4th Edition Jan 31 2012 00 All Rights Reserved Copyright 1992 Yokogawa Electric Corporation Important E About This Manual This Manual should be passed on to the end user Before using the controller read this manual thoroughly to have a clear understanding of the controller This manual explains the functions of this product but there is no guarantee that they will suit the particular purpose of the user Under absolutely no circumstances may the contents of this manual be transcribed or copied in part or in whole without permission The contents of this manual are subject to change without prior notice Every effort has be
125. When creating programs using ladder language refer to FA M3 Programming Tool WideField3 IM 34M06Q16 OHE or FA M3 Programming Tool WideField2 IM 34M06Q15 01E FA M3 Programming Tool WideField IM 34M06Q14 01E and FA M3 Programming Tool WideField Application IM 34M06Q14 02E For information on the specifications configuration installation wiring trial operation maintenance and inspection of the FA M3 as bilo as information on the system wide limitation of module installation refer to Hardware Manual IM 34M06C11 01E For information on the specifications of products other than the power supply module base module I O module cable and terminal block unit refer to their respective user s manuals Read the following user s manuals as required For information on the functions of F3SP21 F3SP25 and F3SP35 sequence CPU modules refer to Sequence CPU Functions for F3SP21 F3SP25 and F3SP35 IM 34MO06P12 02E For information on the functions of fiber optic FA bus modules refer to Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E For information on the functions of FA link H and fiber optic FA link H modules refer to FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E For information on the FL net functions refer to FL net OPCN 2 Interface Module IM 34M06H32 02E For information on the functions of BASIC
126. When the timer T expires its time out relay turns on The time out relay is used for a contact a or b The timer T is reset at the falling edge of the timer input and the current value returns to the timer s setpoint Timer input 1 X00502 e e ee i i H TIM T001 1s X00501 10001 Ben en eee YOBT i i O x00301 TOOT Y00603 ON Timer input X00502 OFF Setpoint Current value T001 Time out relay ON T001 OFF F040501 VSD Figure 4 18 Timer T TIP The setpoint of a timer refers to the duration from the time the timer starts running starting time until the timer expires The setpoint can be specified using a Timer instruction When a timer is running its current value decrements as time passes The current value is set to the setpoint when the timer starts running and becomes 0 when the timer expires IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 5 2 4 24 100 ms Continuous Timer A 100 ms continuous timer T is a synchronized scan decremental timer which updates its current value and turns on off its time out relay using an end of scan process Setpoint 0 1 to 3276 7 s The 100 ms continuous timer retains its current value and the state of its time out relay even when its input condition is OFF When its input condition turns ON again the timer resumes counting from its retained value When its input condition turns off after the continuous timer expires the
127. X00501 E00513 wee E0001 eS O TRIERO EI EA E E n E 1 s f meg Slot 1 shared relay area 7 Slot 1 shared register area A SLOT2 CPU Slot 2 shared relay area Slot 2 shared register area Slot 2 shared relay area iN Slot 2 shared register area E0001 X00604 a 5 MOV R0001 Dooot X00601 001 E0513 yA If If O X00603 Figure 3 12 Shared Refreshing F030902 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 9 2 3 15 Configuration of Shared Refreshing This subsection describes the shared refreshing range partial disabling of refreshing simultaneity of shared refreshed data and shared refreshing mode changing to control related process E Shared Refreshing Range Partial Disabling of Refreshing Using configuration you can disable shared refreshing for selected device types of shared relay E extended shared relay E shared register R and extended shared register R of each CPU module Disabling shared refreshing between CPU modules that do not need to exchange data shortens the overall shared refreshing interval SLOT1 SLOT2 SLOT3 SLOT4 CPU1 CPU2 CPU3 CPU4 Shared register Shared register Shared register Shared register area area area area Read write Read Read Read CPU1 area Read Read write Stop Read Stop Read CPU2 area Read Read write Stop Read f Read Read write C
128. a Function 1 X00501 10001 1H 1 10001 T001 10001 TIM T010 10ms 10001 T001 10002 H H y KO Function n X00502 CNT C001 100 X00501 10016 H co01 X00504 Y00602 H 5 X00501 T001 Y00601 H X00503 F050101 VSD Figure 5 1 Structured Ladder Language Mnemonic Language The mnemonic language is designed for describing a program by breaking its process details into instruction input parameter and output parameter Like the structured ladder language the mnemonic language allows the programmer to perform programming on a function by function basis Instruction section D 10001 OUT Y00602 LD X00501 AND X00502 1 MOV D0001 D0002 Instruction Input parameter Output parameter section section section F050102 VSD Figure 5 2 Mnemonic Language IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 2 5 2 1 E Blocks 5 2 Program Types and Configuration There are two types of programs blocks and executable programs Blocks and Executable Programs A block refers to a collection of circuits entered using WideField3 or WideField2 Parts of a program written on a function by function basis using the structured ladder language or mnemonic language are managed as blocks As a program can be maintained or reused on block basis program development becomes easier CPU modules F3SPOO ON and F3SPOO OH allow up to 10K steps per block CPU module F3SPOO OS allows up to 56K steps per block 10K ste
129. a clock pulse with a 1 min period M047 1 ms clock 0 5ms 0 5ms Generates a clock pulse with a 1 ms period M048 2 ms clock 1ms 4ms Generates a clock pulse with a 2 ms period Normal Subunit ON Normal transmission line or no fiber optic FA bus installed M066 transmission f i aae line OFF Unspecified or abnormal transmission line On for one scan ON When the block Turns on for one scan when the sensor control M067 at sensor CB starts block starts at the first execution of the sensor startup OFF In all other cases control block Blocks M036 to M048 have their rising and falling clock timing synchronized Updates are done at the end of a scan SEE ALSO For details on the M066 Utility relay Normal Subunit Transmission Line see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 20 4 4 3 Sequence Operation and Mode Status Relays Sequence operation and mode status relays indicate the status of sequence operation and various modes Table 4 7 Sequence Operation and Mode Status Relays Sequence Operation and Mode Status Relays Function Description ON Run mode Indicates the status of CPU M129 Run mode flag OFF Other modes operation ON Debug mode Indicates the status of CPU MEN Debug mode flag OFF Other modes operation ON Stop mode Indicat
130. a communication error occurs the detailed error code field indicates details on the error Table 6 12 Detailed Error Codes Error Code EC1 Meaning Detailed Error Code EC2 03 Device specification The EC2 field provides a hexadecimal representation of the number error assigned to the faulty parameter Value outside the The number is one among the ordinal parameter numbers at which 04 setting range an error has occurred first Data count out of 05 E range Example 1 2 3 4 5 6 7 Parameter S M1 if l I j numbers T 0101ABRW 03 Y00501 1 10002 0 1 10012 1 xX t Erroneous device number 08 Parameter error In this example the respective error codes take the values shown below EC1 03 EC2 06 b7 b6 bs b4 b3 b2 b1 bO me 8 Each bit has the following meaning a b7 Reserved 41 Communication b6 Reserved error b5 Framing error b4 Overrun error b3 Parity error b2 Reserved b1 Reserved b0 Reserved 10 Self diagnostic error 20 Program error including parameter error 40 Inter CPU communication error 80 Device access error 90 Communication protocol error AQ Parameter error BO Operating mode error protected exclusive access CQ Device block specification error FO Internal system error CPU processing error The EC2 error code has no meaning for any value of EC1 other than those listed above IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 4
131. able 1 11 LED Indicator Combinations Based on the Severity of Failure Status Major Moderate Minor LED Indicator Failure Failure Failure O ON OFF A ON or OFF Table 1 12 Weight F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 12 1 2 5 External Dimensions F3SP22 Unit mm F3SP28 F3SP38 i 83 2 a 28 9 e E a a gt i ii LI ee 100 il i LAF ee y F010202 VSD F3SP53 F3SP58 F3SP59 113 2 L gt 83 2 30 0 28 9 m 2 rel A or i F010203 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 13 1 3 Basic Configuration This section describes units slot numbers and I O relay numbers which form the basic configuration of an FA M3 Units slots and input output relays are identified with unique numbers These numbers are used in parameters of ladder instructions and configuration setup 1 3 1 Unit A unit is a system with the minimum configuration consisting of the following modules Install these modules on the base module to compose the unit Table 1 13 Unit Components Modules Name Description Five types are available allowing different number of
132. able Interrupt El instruction to prevent all interrupt programs from being executed during exchange of multi device data 2 Write an application program to perform flag control between the normal scan program and the input interrupt program using relays IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 30 AN CAUTION 3 11 4 Simultaneity of refreshed data when input interrupt programs are executed immediately during instruction execution If input interrupt processing is configured with the timing option of Immediately during instruction execution an input interrupt program may be executed even during synchronization processing input refreshing and common processing When an input interrupt program is executed during synchronization processing or input refreshing values of devices I O relays X Y shared and extended shared relays E shared and extended shared registers R and link relays and registers L W which are being refreshed may be read by programs If these device values are overwritten by the input interrupt program simultaneity of data before and after the execution of the input interrupt program is lost To prevent all input interrupt programs from being executed during synchronization processing input refreshing and common processing execute a Disable Interrupt DI instruction at the end of a normal scan program Along with this instruction execute an Enable Interrupt El instruction at the start of t
133. acro instructions is to call another macro instruction or an input macro instruction when executing a macro instruction Calling a structure macro instruction within a structure macro instruction body is not allowed Calling another macro instruction or an input macro instruction from a structure macro instruction body is allowed but the PARA instruction cannot be used Nesting macro instruction calls beyond seven levels will cause an instruction processing error The nesting depth is stored in special register Z106 A value of 0 is stored in the special register Z106 during non nested execution of a macro instruction Table 6 20 Calls between Macros Input Macros and Structure Macros Calling Side Called Side Availability Block Macro v Block Input macro v Block Structure macro v Macro Macro A Macro Input macro A Macro Structure macro x Input macro Macro A Input macro Input macro A Input macro Structure macro x Structure macro Macro A Structure macro Input macro A Structure macro Structure macro x v Callis allowed PARA instruction can be used A Parameters passed using the PARA instruction are overwritten X Call is not allowed A CAUTION Parameters 1 to 3 passed to macro instructions are saved when macro instructions are nested However parameters 4 to 16 passed using PARA parameter instructions are not saved If a Parameter PARA instruction is executed in a called macro instruc
134. al computer link module For details see Subsection 6 11 4 Setting Up the Personal Computer Link Functions Table 6 7 Transmission Rate and Data Format of CPU s Personal Computer Link Functions Transmission Rate bps 9600 9600 19200 19200 38400 38400 57600 57600 115200 115200 Data Length Stop Bits A dedicated programming tool cable is required to connect a personal computer or monitor to the CPU module To set the transmission rate data format checksum end character and protection function use the configuration item Communication mode setup is by switches in the case of the personal computer link module The event transmission function is not supported If the sequence CPU module receives an MDR module reset command as a PC line command it resets only the communication port The maximum number of personal computer link modules that can be installed remains the same even if the CPU s personal computer link functions are used E Communications Protocol A brief description of the communications protocol of the personal computer link functions is given below Sending station Receiving station Communication STX protocol of personal computer link functions Station No CPU No Response wait time Command Parameters Checksum ETX CR STX Station No CPU No OK Command response Checksum ETX CR
135. all Structure Macro Instruction Call F061304 VSD The Structure Macro Instruction Call instruction passes multiple data items collectively in a structure to a macro instruction and is especially useful in reducing the number of items to be passed to a macro instruction and providing better representation of a group of related data items IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 13 2 Specification of Macro Instructions E Number of Macro Instructions 6 46 Macro instruction entities to be called are downloaded along with user ladder programs from a personal computer to the sequence CPU module using WideField3 or WideField2 The table below lists the maximum number of macro instruction entities allowed in one executable program during downloading A macro instruction can be called any number of times in a user ladder program Table 6 15 Maximum Number of Macro Instructions Allowed by CPU Type F3SP22 0S F3SP28 3N F3SP28 3S F3SP38 6N F3SP38 6S F3SP53 4H F3SP53 4S F3SP58 6H F3SP58 6S F3SP59 7S Macro Call MCALL 64 Input Macro Instruction Call NCALL 0 not available 256 in total Structure Macro Instruction Call SCALL 0 not available E Size of Macro Instruction Program The size of a macro instruction program is limited by the total size of that program and user programs combined E Macro Instruction Execution Time Table 6 16 Macro Instruction Execution Time Instruction Mnemonic
136. alue is to be retained when the block is inactivated This device is set to OFF X00503 10002 X00501 X00502 10003 X00301 10005 10004 Use a SET instruction to retain the output value of this device F060406 VSD Figure 6 8 Example of Devices Initialized When a Block is Inactivated Operation When Specified Blocks Are Executed Example Where Each Block Controls the Next Block to Be Activated Block 1 operat Condition y peer ACT BLOCK2 Block 1 INACT BLOCK1 t Condition oe ee ears Block 2 Condition Block 2 ACT BLOCKm Condition __ INACT_ BLOCK2 gt gt Block m gt L Block m Condition Conditions tf ACT BLOCK1 Re INACT _ BLOCKm A F060407 VSD Figure 6 9 Example Where Each Block Controls the Next Block to Be Activated IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 11 Example Where Block Activation is Controlled by a Scheduler Block 1 Block 1 wee Condition a II ACT _ BLOCK2 J INACT BLOCK H Condition I ACT BLOCK3 INACT BLOCK Condition 1 ACT BLOCK1 J y ACT
137. ammable controllers PLC computerized numerical controllers CNC and other factory automation FA controllers including personal computers PC from multiple vendors For details on FL net see FL net OPCN 2 Interface Module IM 34M06H32 02E Computers FA controllers FA devices PC gews SERVER PC PC m j le 5 Information network upper LAN Ethernet TCP IP UDP FL net OPCN 2 Ethernet controller network Smart display PLC PLC oo oo oo Field network i Sensors and actuators F020305 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 7 2 4 Programming Tool The FA M3 programming tool WideField3 and WideField2 or simply WideField3 and WideField2 is available as a programming tool for the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPU modules 2 4 1 WideField3 WideField2 Description Software Model Compatible Sequence CPU Modules F3SP05 F3SP08 F3SP21 F3SP22 F3SP25 F3SP35 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3FP36 F3SP66 F3SP67 F3SP71 F3SP76 FA M3 Programming Tool WideField3 SF630 O0CW Compatible Sequence CPU Modules F3SP05 F3SP08 F3SP21 F3SP25 F3SP35 FA M3 Programming Tool WideField2 SF620 MCW F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3FP36 F3SP66 F3SP67 Description Software Model EES laisia 3 g a elel TSI alta on
138. an execute programs written to ROM packs using the same CPU type or some other CPU type as shown in the table below Example The F3SP28 3S can execute programs written to the ROM pack using F3SP28 3S or F3SP28 3N Table 6 6 2 Compatibility of a CPU with ROM Pack Data Written by another CPU 2 2 CPU Compatible with CPU Used to Written ROM Pack Data Write Program Data to ROM Pack F3SP28 3S Rev 8 or later F3SP28 3S or F3SP28 3N 7 F3SP38 6S Rev 8 or later F3SP38 6S or F3SP38 6N 7 F3SP53 4S Rev 8 or later F3SP53 4S or F3SP53 4H F3SP58 6S Rev 8 or later F3SP58 6S or F3SP58 6H 4 A compatible CPU may take several extra seconds to start up from ROM pack data written by a different CPU type The actual duration depends on the program size Note that CPUs of different types may calculate the number of timer instruction steps and comment steps differently Thus a ROM pack written by a CPU may result in a ROM pack error when executed on a compatible but different CPU type and cannot be accessed due to an excessive step count AN CAUTION Do not use the CPU to ROM transfer function to directly write a program read to CPU from a ROM pack written by another CPU to the ROM pack Write the program to the ROM pack using the File to ROM transfer function after changing the CPU type by uploading the program with the programming tool or using the CPU to ROM transfer function after downloading the program IM 34M06P13
139. ardless of the module type System numbers 12 3 4 5 6 7 8 Figure 4 11 Assignment of System Numbers System 1 L System 2 L System 3 L System 4 L System 5L System 6 L System 7 L System 8 L EE EEEE 00001 10001 20001 30001 40001 50001 60001 70001 F040303 VSD To manually assign system numbers to modules independent of their slot positions use configuration to assign fixed system numbers to slot positions Slot 1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 Slot9 Slot 4 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 Slot 9 eal fe System numbers L gt 2 3 4 5 6 7 8 Figure 4 12 Changing System Number Assignment G Project Settings Configuration Project Settings 5 Project Settings L CPU Type Settings E Executable Program Settings i Execution Block Components jij Protection Settings E CPU Properties H User Log Message Configuration E Run Operation Setup E Input Output Setup EHE Device Setup Device Area Setup E Latch Range Setup at Power Failure i Script Setup i Interrupt Setup 99 Built in Functions Setup E Error Handling Setup 9 Initial Data Setup E Inter CPU Shared Memory Setup 9B FA Link Setup E Sampling Trace Setup FA Link FL net System Setup Manual setup Automatic setup assigns system number by slot number order System 1 System 2 System 3
140. ate the results of self diagnostics by the sequence CPU Table Appendix 2 2 Self diagnosis Status Registers Self diagnosis Status Registers Function Description Self diagnosis error No Self diagnosis error block Self diagnosis Error No Store the results of self diagnosis 2019 Self diagnosis error instruction No 7022 Instruction processing error No 2023 Instruction Processing Instruction processing Store errors occurring during Error error block No instruction processing Instruction processing 2024 error instruction No Z027 I O comparison error No Z028 VO Comparison Error 1 O comparison error block Store detailed information on I O p No comparison errors Z029 I O comparison error instruction No Store as a bit pattern the slot number for which an I O error has occurred Z033 Main unit Slot no with I O error 7034 Subunit 1 Z033 to 040 1 O Error 16 2 1 Z035 Subunit 2 0 ee 1 0 Z036 Subunit 3 Z037 Subunit 4 Z038 Subunit 5 Z039 Subunit 6 Z040 Subunit 7 Z041 Main unit Z042 Subunit 1 Slot number Z043 Subunit 2 16 1 z044 S Subunit ofifo Module Recognition Z045 Subunit 4 0 No modules are recognized Z046 Subunit 5 Unable to read write Z047 Subunit 6 1 Modules are recognized Z048 Subunit 7 Z089 Main unit Slotnumber Z090 Subunit 1 16 1 z091 Subunit 2 0 fe 1 0 Z092 oe Subunit
141. ays X used in the sensor control block AN CAUTION Relationship between shared refreshing and link refreshing Shared and extended shared relays E shared and extended shared registers R link relays L and link registers W are not refreshed by I O refreshing of the sensor control block Instead these devices are refreshed during common synchronization processing in a normal scan IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 62 E Maximum Number of I O refreshed Words The maximum number of words that can be configured for refreshing depends on the type of unit main unit or subunit where the module is installed the execution interval and the number of installed CPU modules including BASIC CPU modules as show in the table below You can calculate the number of words according to the following equation Number of O refreshed words Number of words of I O modules in main unit to be refreshed Number of F3XH04 modules in main unit to be refreshed that use pulse catch function Number of words of I O modules in subunit to be refreshed x 4 Number of F3XH04 modules in subunit to be refreshed that use pulse catch function x 4 Table 6 23 Maximum Number of I O refreshed Words Handled by Sensor Control Block for each CPU Maximum Number of I O refreshed Words Two CPUs Three CPUs Four CPUs Execution Interval Example 1 Number of CPU modules installed 2 Execution interval of sen
142. block protection c ccceceeceeeeeeeeceeeeeeeeeeteees 6 15 Cc clear GOVICES ee ceccccceeeeeeeeceeceeeeeeeeteteeeiaeeeeeeetees 6 2 clear MEMONY ce eeeeececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenaees 6 2 configuration cece ceceeeeeeeeeeeeeeeeeeeeeeteteenaees 1 7 9 3 constant SCAN eeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeaeaeaeaeaeaes 6 4 D Debug mode ee eeeeeeccecceeeeeeeeeeeeenteeteeeeees 3 1 6 2 debugging fUNCTIONS 0 eect eeteeeeetteeeeeeeaee 6 12 debugging operation ccceccceeeeeeeeeeeeeeeeeee 6 53 device MANAGEMENT eeeeeeeeeteeeeeeetteteeeees 6 42 E Error OG iiin aia aisian 3 2 3 3 8 1 exclusive ACCESS control 6 23 executing all bloCkS ssseeesssssssrneseennansannnseennnannan 6 5 executing specified blocks eeeeeeeeeeeeneen 6 6 F F3SP25 and F3SP35 differences from 9 1 F3SPOO OS and F3SPOO ON O4 differences from ccceceeeeeeeeeteteeeeeeees 10 1 TANG unanini an a deedesawesadesate 1 11 8 1 forced Set reSet ccccccececeeeeeeeeeeeceeeeeeeeeeteees 6 12 functions for storing comments to CPU 6 74 functions for storing tag name definitions to CPU eeeeeeeteeeeeeeees 6 77 H high speed processing of application instruction Ssni a 9 5 l VO relay NUMDBEN cecrnerencenniinmi a 1 15 index register V ccccceeseeeeseeeeeeeeseeeeeeeeees 4 40 input interrupt processing cccc
143. case of power failure then the devices included in the latching are L10513 to L11024 link relays L for link 1 and L20001 to L20512 link relays L for link 2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 9 Table 1 9 Configuration Range 4 5 F3SP22 0S F3SP28 3N 3S F3SP53 4H 4S F3SP38 6N 6S F3SP58 6H 6S F3SP59 7S Item Initial data of data register Data register D Default Value None Value Range Configurable for up to 1024 contiguous points from a starting number Operation Control Scan monitoring time 200 ms Configurable from 10 to 200 ms in increments of 10 ms Constant scan Do not Use Configurable from 1 0 to 190 0 ms in increments of 0 1 ms I O module error Stop I O comparison error Stop Error time action Instruction parameter error Scan timeout Stop Stop operating mode in Subroutine error Stop case of error Interrupt error Subunit communication error Stop Run Sensor CB scan timeout Stop Run Stop configurable Program execution mode All Blocks All Blocks Specified Blocks Momentary power failure detection mode Peripheral processing time Valid for all power supply modules except F3PU01 0N Standard mode Not set up Standard Immediate 100 us to 190 ms in increments of 100 us Interrupt Setup Execution interval 200 us 200 us to 25 0 ms in increments of 100 us
144. ce personal computer link service CPU service link refreshing and shared refreshing are classified as a system of peripheral processes The CPU performs these two kinds of processes concurrently to speed up the control related processes Peripheral processes Oh a ee tose ate ea et ae ee j Input refreshing for Common processing i sensor control block Shared i Fixed Program execution for Input refreshing refreshing interval of sensor control block us 5 i Output refreshing for g Ear longer sensor control block Output Peripheral Link refreshing H refreshing processes One scan are performed i aie ees within this a Input refreshing for Instruction time range Command sensor control block execution F4 processing Ear TEE ie SE Gee Tool service Program execution for Link service sensor control block gt Execution interrupt Pa 72 CPU service Output refreshing for i i sensor control block i Synchronization processing E EEE eee ccc ntee If synchronization processing begins y g beg any peripheral process is interrupted temporarily and resumes at the next scan Shows a case when the sensor Control related process control function is used Peripheral process F030401 VSD Figure 3 3 Processing Method SEE ALSO For details on the sensor control function see Section 6 15 Sensor Control Fun
145. configuration table An area for storing configuration information such as I O module setup and output mode Hold reset in case sequence stops Contains the initial values discussed in Subsection 1 2 3 Configuration Program control instructions table An area for storing information required for managing the execution of program control instructions such as JMP instructions and subroutine instructions Contains 0 indicating that there are no program control instructions such as JMP or subroutine instructions Timer counter setpoint table An area for storing timer and counter setpoints Contains 0 indicating that there are neither timers nor counters Utility An area for storing information such as circuit comments and subcomments Contains 0 See subsection 1 2 3 Configuration for more information AN CAUTION No program can be executed when the program memory is in its initial state Structure of Program Memory Program management table Program Program F3SP22 F3SP28 F3SP53 F3SP59 Configuration table Device ranges Error time action RAM V O configuration table Output when stopped setup Sampling interval setup Data code setup table Program control instruction Jumps subroutines labels table Timer counter setpoint Utility registration tables etc Figure 5 11 Structure of Program Memory
146. cting Counters Select the range of counters C to be used Table 4 12 Configuration of Counters C Timer T F3SP22 F3SP28 F3SP53 4 27 When a counter is running its current value decrements until it reaches 0 at which time the counter is F3SP38 F3SP58 F3SP59 Default T0001 to T1024 Configuration Range 2048 max for counters and timers Device Capacities Counter C C0001 to C1024 combined in increments of 1 Timer numbers T0001 to T2048 Counter numbers C0001 to C2048 Default T0001 to T2048 Configuration Range 3072 max for counters and timers C0001 to C1024 IM 34M06P13 01E combined in increments of 1 Timer numbers T0001 to T3072 Counter numbers C0001 to C3072 4th Edition Jan 31 2012 00 4 7 4 7 1 4 28 Data Register D Shared Register R and Extended Shared Register R This section describes data registers D shared registers R extended shared register R and how to set the initial data Data registers D are 16 bit variables that can be used without restrictions in a program Shared registers R and extended shared registers R are 16 bit variables that can be used for communications between CPUs in a multi CPU system Data Registers D Data registers serve as memory for storing the results of program based operation Each data register has 16 bits 1 word In programs you can read from or write to data regis
147. ction TIP Common processing includes self diagnosis updating of special relays M and special registers Z as well as updating of timers The END processing is sometimes known as an END scan IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 6 TIP The input refreshing process reflects data from input contacts of say a DI module to input relays X The output refreshing process reflects data from output relays Y to output contacts of say a DO module TIP The synchronization process synchronizes the system of control related processes with the system of peripheral processes In particular it reflects data to the link refresh and shared refresh inter PLC communication devices System of Control related Processes This system performs basic operations of the sequence CPU module such as instruction execution and I O refreshing Execution of the system of control related processes is called one scan and the execution time required by the system is usually called the scan time System of Peripheral Processes This system supports the programming tool WideField3 and performs communication between the CPU module and a personal computer or an FA link module The system of peripheral processes is concurrent with and independent of the system of control related processes Therefore neither the number of modules connected nor the content of each peripheral process affects the operation of the system of control rela
148. ction processing error will result Ina ladder instruction for continuous data transfer or table format data output see examples below you are not allowed to specify a special register Z as the output destination If you do so an instruction processing error will result Instructions for continuous data transfer Block Move Instruction BMOV Instruction Block Set Instruction SMOV Instruction etc Instructions for table format data output User Log Read Instruction ULOGR Instruction FIFO Write Instruction FIFWR Instruction etc Instruction BSET Instruction String Move IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 36 4 8 2 Self diagnosis Status Registers Self diagnosis status registers indicate the results of self diagnostics by the sequence CPU Table 4 15 Self diagnosis Status Registers Self diagnosis Status Registers Self diagnosis error Stored Date Self diagnosis error No Self diagnosis error block No Self diagnosis error Descriptions Store the results of self diagnosis Z019 instruction No Z022 HET processing Instruction Pane A Instruction processing Store errors occurring during instruction Z023 processing wget error error block No processing 2024 Instruction processing error instruction No Z027 I O comparison error No vO
149. cute the sensor control Execution Time TIP The measured execution time of the sensor control block is updated at each normal scan input refreshing process 6 15 5 Procedures for Using Sensor Control Functions The table below summarizes the procedures for using the sensor control functions Table 6 34 Procedures for Using Sensor Control Functions WideField3 Function Reference to WideField2 Items Discussed Earlier Defining O refreshed words of sensor Coniiguration Maximum Number of I O refreshed control block 9 Words Defining the execution interval Input Output Setup Execution Interval Setting and Accuracy Defining the interrupt timing Interrupt Setup Interrupt Timing Defining the priority of interrupts Priority of Interrupts Activating Deactivating Sensor Control Block editing Block Procedure Setup Item Edit Item Creating normal scan programs Creating sensor control programs Registering sensor control block Component definition TIP You can use the sensor control block irrespective of whether the configuration item Program Execution Mode is set to All Blocks or Specified Blocks IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 70 6 15 6 Error Handling The table below summarizes the errors that may be reported when the sensor control functions are in use Table 6 35 Errors Related to Sensor Control Functions Type of Error Description Th
150. cwssvesssececetecstssersvaveceteewesesseavsveceseteeut esas vesseeeesetseeeas i DMD OPEN aaa E T E ii ahoro l Loule ppn E E viii Copyrights and Trademarks cccccccceccceeeeeeeeeeeeeeeeeeaaeeaeeaaaaaeaeeeeeeaeeaaee x 1 Specifications and Basic Configuration eseeeeeeeees 1 1 1 1 COVENVICW eiicndetnecacccesiiessienelececetiendstennlebsebechiasnretieadedemiieseeestuasees neces 1 1 1 2 SPOCITI CATIONS issa aea aaa aKO aara 1 3 1 2 1 List of Specification Szo 1 3 1 2 2 Device List eee inaani aaa 1 6 1 2 3 Configuration 2c0 ecient ioi e 1 7 1 2 4 Components and Their Functions ccccceeeeeseeeseteeees 1 11 1 2 5 External DIMENSIONS 0 cece eeeeeeeeeeeeeeeeeeteeeeeeeeeeaaeees 1 12 1 3 Basic Configuration cccccssssececessseeeeessseeesesesseeeeessseeesessseenseesseenens 1 13 W340 Uihit E EE E A A ane Se en eee 1 13 t32 Slot NUMO ceciren otne eheaezs teteensentedeneeth ppeneee NEERA 1 14 133 VO Relay NUMDEr senri a ATAA 1 15 2 System Configuration aaaassaaeeaeennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnne 2 1 2 1 Basic System Configuration ssssssssesnnnrnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnn nnn 2 1 2 2 Multi CPU System Configuration sssssassennnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 2 1 2 2 1 Multi CPU System Configuration eeeeeeeeeeeeeeeeene eenen 2 1 2 2 2 Handling I O Modules in Multi CPU System 2 3 2 3 Extended System Configuration
151. d displays states of multiple devices for up to 1024 scans Personal computer link functions Perform communications equivalent to that of a personal computer link module when a personal computer or a monitor is connected to the programming tool connector port Macro instructions Allow the user to create and register new customized instructions User log management functions Allow the user to keep a log of or record of errors in the user s system the way they occurred the system s operating condition and so on Sensor control functions Execute a single block at high speed and at fixed intervals separately from the normal scan Partial download functions Download specified blocks or macros only Functions for storing comments to CPU Store circuit comments and subcomments to a sequence CPU module Functions for storing tag name definitions to CPU Store tag name definitions to a sequence CPU module Structures Represent a group of data items under a unified name Table 6 2 ROM Management Writer Functions ROM Management Writer Functions File to ROM transfer function Function Overview Writes programs or data to the ROM pack CPU to ROM transfer ROM copy function Writes a program or data to the ROM pack Compare file and ROM pack function Compares the contents in the ROM to the program in WideField3 or WideField2 Clear ROM pack function
152. de file to ROM transfer CPU to ROM transfer and file and ROM pack comparison The ROM writer functions work in a dedicated mode different from the normal operating mode of the sequence CPU module This dedicated mode is called the ROM Writer mode The ROM Writer mode is maintained even when you turn on or off the power At power on no programs are read from the ROM pack Sequence CPU Program memory ROM pack ROM Writer mode F060802 VSD Figure 6 16 ROM Writer Functions and ROM Writer Mode IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 22 Using the ROM writer functions you can save a debugged and or tuned program to the ROM pack To transfer the program to the ROM pack use the ROM management function of WideField3 or WideField2 The following details the ROM writer functions E File to ROM Transfer Function This function writes programs data and a tag name definitions to a ROM pack It first transfers a program to the CPU memory and then writes the program to the ROM pack You can specify whether to make the current values of devices resident in ROM and whether to write tag name definitions to the ROM pack Tag name definitions if to be written are written directly to the ROM pack without first being transferred to the CPU memory m CPU to ROM Transfer ROM Copy Function This function writes a program or data in the CPU directly to the ROM without transferring it using the ROM management func
153. dex modification cannot be specified as destinations for data output and if specified will result in instruction processing errors during execution AN CAUTION Special relays cannot be specified as output destinations in block transfer and table output ladder instructions and if specified will cause instruction processing errors during execution Block transfer instructions BMOV BSET SMOV etc Table output instructions ULOGR FIFWR etc IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 19 4 4 2 Utility Relays Utility relays are used to provide timing in a program or issue instructions to the CPU module Table 4 6 Utility Relays Item Utility Relays No Name Function Description M033 Always ON ON OS l OFF Used for initialization or as a dummy contact in ON a program M034 Always OFF OFF 1 scan ON at Mison OOOO Turns on for one scan only after a program MoS program start eee starts execution M036 0 01 s clock 0 005s 9 905s Generates a clock pulse with a 0 01s period M037 0 02 s clock 0 01s 0 01s Generates a clock pulse with a 0 02 s period M038 0 1 s clock 0 05s 0 05s Generates a clock pulse with a 0 1 s period M039 0 2 s clock 0 1s 0 1s Generates a clock pulse with a 0 2 s period M040 1 s clock 0 5s 0 5s Generates a clock pulse with a 1 s period M041 2 s clock 1s 1s Generates a clock pulse with a 2 s period M042 1 min clock 30s 30s Generates
154. downloaded earlier SEE ALSO For details on the partial download functions see Section 6 16 Partial Download Functions Storing Comments or Tag Name Definitions in CPU The new models allow circuit comments subcomments or tag name definitions to be stored in the memory of a CPU module or the ROM pack SEE ALSO For details on the download comments function see Section 6 17 Functions for Storing Comments to CPU For details on the download tag name definitions function see Section 6 18 Functions for Storing Tag Name Definitions to CPU For details on the ROM pack function see Section 6 8 3 ROM Writer Functions and ROM Writer Mode IM 34MO06P13 01E 4th Edition Jan 31 2012 00 10 3 10 2 New Instructions and Instruction Related Functions Structures The new models introduce a new concept of structures to handle device addresses Some instructions are added to handle structures SEE ALSO For details on structures see FA M3 Programming Tool WideField3 IM 34M06Q16 O10E or FA M3 Programming Tool WideField2 IM 34M06Q15 01E Indirect specification With the new models indirect specification is available to address devices Thus some instructions are added to handle this new function Using indirect specification allows you to address all file registers B including those which cannot be accessed using index modification You can also use indirect specification to address devices
155. e allocated for each timer T type The size of the first device numbers assigned to these timers T are related in the following manner 100 us timer lt 1 ms timer lt 10 ms timer lt 100 ms timer lt 100 ms continuous timer 100 us 1 ms 10 ms and 100 ms timers and 100 ms continuous timers are assigned device numbers of the sequence CPU in the given order Table 4 11 Configuration of Timers Configuration of Timer T and Counter C 100 us timer F3SP22 F3SP28 F3SP53 F3SP38 F3SP58 F3SP59 Default 1 ms timer 10 ms timer 100 ms timer 100 ms continuous timer Configuration Range Default 2048 for timers and counters combined in increments of 1 16 max for 100 us timers Timer numbers are continuous IM 34M06P13 01E Configuration Range 3072 for timers and counters combined in increments of 1 16 max for 100 us timers Timer numbers are continuous 4th Edition Jan 31 2012 00 4 6 4 26 Counters C This section describes the function and operation of counters as well as selection of counters in the configuration All counters are decremental counters C and have two types of input count input and counter reset input When a counter instruction is executed a counter decrements its current value each time it detects a rising edge in its count input and terminates when its current value reaches 0 When the counter C termina
156. e CPU fails to maintain the execution interval because it is exceeded Sensor CB scan timeout error by the sum of the fixed interval I O refreshing time and the execution time of sensor control programs The CPU has insufficient time to execute a regular program because the Scan timeout execution time of sensor control programs is too long Thus the normal scan time exceeds the scan monitoring time An I O module has failed during fixed interval I O refreshing in the sensor control block I O module error AN CAUTION If multiple I O module errors are detected during I O refreshing in the sensor control block the CPU only reports the first detected error by means of an alarm indicator Table 6 36 Sensor CB Scan Timeout Special Relay M Item Self diagnosis Status No Name Description Status M212 Sensor CB scan ON Error Indicates that the CPU cannot maintain the timeout OFF Normal execution interval of the sensor control block Table 6 37 Actions when an Error Is Encountered in Sensor Control Block Type of Error Action in Case of Error Encountered Sensor Control Block Effect on Normal Scans The program either runs or stops depending on Sensor CB scan timeout Sto the Error time Action defined for Sensor CB Special relay M212 turns on P scan timeout error in Operation Control of configuration For errors configurable with Operation Control of configuration the Other errors sensor control bl
157. e CPU modules is combined with any one or more of these CPUs installed as add on CPU modules Simultaneity of data between shared relays E registers and extended shared relays E registers is not guaranteed however If any of the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 CPUs is combined with any of the F3SP21 F3SP25 and F3SP35 sequence CPU modules simultaneity of shared refreshed data cannot be guaranteed regardless of the configuration setting The Non simultaneous option is provided for compatibility with the F3SP21 F3SP25 and F3SP35 CPUs Select this option when these CPUs are replaced with the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPU modules IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 10 E Configuring Shared and Extended Shared Relays E in a Multi CPU System Specify the range of shared and extended shared relays E to be used by each CPU when add on CPU modules are installed You can allocate any number of relays on 32 relay basis Extended shared relays E are only available if one of the F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 sequence CPU modules is combined with one or more CPUs from the same list installed as add on CPUs Table 4 1 Configuration of Shared Relays E F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 Default Configuration Range 2048 max for all CPUs combined Shared relay E in increments of 3
158. e CPU service unless it receives a command ENTER OUTPUT etc to be processed from a BASIC CPU I Sequence CPU BASIC CPU module Common process Input refreshing Output refreshing Instruction execution Synchronization processing Figure 3 18 CPU Service Peripheral processes 2 _ Shared refreshing Link refreshing Command processing Tool service Link service CPU service o es F030908 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 20 3 10 Method of Link Data Updating This section describes methods of link data updating and link refreshing for FA link systems and FL net systems 3 10 1 Link Data Updating Link data updating is a process of exchanging data with sequence CPU modules in remote stations through link relays L and registers W You must configure in advance the ranges of link relays L and registers W to which data is written in the local and remote stations F3LPOO F3LX00 F3LPOD F3LXOO F3LPOD F3LXOO Link relays Link SS e A t D m FA link module or FA link module or FA link module or FL net module in FL net module in FL net module in local station remote station remote station ae Data allocated to each FA link module or FL net module F031001 VSD Figure 3 19 Link Data Updating SE
159. e data handling and creation of efficient programs F3SPOO OS Structure macros simplify passing of data to macros and updating of these data structures F3SPO0 OS Sensor control Configuration setup of parameters including device size range of devices to be latched in case of power failure and external output to be retained in case of sequence stop Constant scan at an interval of 1 to 190 ms in 0 1 ms increments Sampling trace Debugging forced SET RESET instructions online editing etc Error logging user logging Clock year month day hour minute second and day of week Support for programming tool connection port with the personal computer link functions Program protection Program data storage in ROM pack Circuit sub comment tag name definitions storage in ROM pack F3SPOO OS Circuit sub comment storage function and tag name definition storage function F3SPOO OS Partial download functions F3SPOO OS See Section 1 2 Specifications for more information IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 3 1 2 Specifications This section describes the basic specifications of the FA M3 sequence CPU module for each CPU type For functional specifications see Section 1 2 1 List of Specifications For the types and number of devices see Section 1 2 2 Device List For configuration setup ranges see Section 1 2 3 Configuration For the names and functions of the components of the seq
160. e in dry conditions first touch grounded metal to discharge any static electricity before touching the system Never use solvents such as paint thinner for cleaning Gently clean the surfaces of the FA M3 controller with a cloth that has been soaked in water or a neutral detergent and wringed Donot use volatile solvents such as benzine or paint thinner or chemicals for cleaning as they may cause deformity discoloration or malfunctioning Avoid storing the FA M3 controller in places with high temperature or humidity Since the CPU module has a built in battery avoid storage in places with high temperature or humidity Since the service life of the battery is drastically reduced by exposure to high temperatures take special care storage temperature should be from 20 C to 75 C There is a built in lithium battery ina CPU module and temperature control module which serves as backup power supply for programs device information and configuration information The service life of this battery is more than 10 years in standby mode at room temperature Take note that the service life of the battery may be shortened when installed or stored at locations of extreme low or high temperatures Therefore we recommend that modules with built in batteries be stored at room temperature Always turn off the power before installing or removing modules Failing to turn off the power supply when installing or removing modules
161. e the tool service if there is no command to be processed oe ON ete ee Bie a Monitor display X00503 X00504 Y00602 H oH Personal computer X00501 X00502 Y00601 O m ae _ won gt l Upload Download Sequence CPU Peripheral processes Common processing Shared refreshing Input refreshing Output N Le refreshing lt 7 Link refreshing Instruction i Command processing execution Tool service Link service _ CPU service Synchronization processing F030701 VSD Figure 3 9 Execution of Commands Sent from the WideField3 WideField2 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 8 3 8 1 3 12 Method of Executing Commands through Personal Computer Link The CPU uses the personal computer link service to execute commands sent through the personal computer link These commands include downloading and uploading programs and reading from and writing to devices Personal Computer Link Service The personal computer link service executes commands sent from a personal computer or a monitor connected to the personal computer link module Since the personal computer link service runs concurrently to the execution of instructions it does not affect the scan time The CPU does not execute the personal comp
162. ebugging functions such as forced SET RESET instructions and online edit through WideField3 or WideField2 These functions however affect the scan time Disable the functions at the end of debugging and tuning and set the CPU to Run mode In this mode the RDY and RUN LED indicators turn on The Debug mode includes a pause state in which the sequence CPU module suspends program execution during such debugging operation as scan operation In this state the RUN LED indicator turns off and all external outputs being generated by the program are latched E Stop Mode The Stop mode is a state in which the sequence CPU module stops program execution In this mode you can remove programs and clear devices in addition to using forced SET RESET instructions online editing and debug operation In this mode the RUN LED indicator turns off The external outputs being generated by the program are set to ON hold or OFF reset according to the setting of the configuration item Output When Stopped of Input Output Setup By default all external outputs are set to OFF Table 3 1 LED Indicator Combinations Based on the Operating Mode Operating Mode LED Indicator O ON OFF A ON or OFF IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 2 3 2 1 3 2 2 3 2 Operation at Power on off This section describes the operations when power is turned off or turned on Operation at Power on When the power
163. ecial relay M2002 1 Block m Function m Special relay M200m 1 F060403 VSD IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 8 Devices that are used in a block which is activated by an ACT instruction are put into the following states by block initialization Table 6 4 State at Block Activation Device State at Block Activation Timer T Resets Continuous timer Retains the value held before block activation Counter C Retains the value held before block activation Destination of Be instruction Goes into an OFF state al other devices Retains the states held before block activation Use a SET instruction for a device in a block whose output value is to be retained when the block is activated This device is set to OFF X00503 10002 Y00603 L X00501 X00502 10003 X00301 10005 ser vooso1 004 T Use a SET instruction to retain the output value of this device F060404 VSD Figure 6 6 Example of Devices Initialized When a Block is Started IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 9 6 4 4 Operation When Specified Blocks Are Inactivated A block that is specified for inactivation by an INACT instruction is initialized at the end of that scan and is actually stopped in the next scan
164. ecution If the interrupt timing is set to be after instruction execution you should set the execution interval to 1 ms or longer With this interrupt timing option the CPU does not switch to the sensor control block during common processing or refreshing Although the common processing time or refreshing time varies depending on the duration of synchronization processing such as shared refreshing or link refreshing you should set the execution interval to at least 1 ms Otherwise the execution interval of the sensor control block cannot be maintained and this may result in a sensor CB scan timeout error Debug operation when the interrupt timing is after instruction execution If the interrupt timing is set to be after instruction execution a sensor scan timeout error may occur when switching from Run to Debug mode or from Debug to Run mode or when canceling a forced set reset in Debug mode Simultaneity of data when the interrupt timing is immediate Simultaneity of data for multiple devices is not guaranteed if the sensor control block is executed immediately during instruction execution For example consider the case shown in the previous figure where the sensor control block is executed during execution of a block transfer BMOV instruction in a normal scan There is a risk that the source data that is partially transferred may be overwritten after the execution of the sensor control block or data transferred partially to the d
165. ed in the specified data registers when the program starts This configuration is useful when a large volume of initial data needs to be set by a program or when the initial data needs to be saved You can set initial data in a maximum of 1024 data registers Starting number 1 Quantity 1024 Figure 4 26 Setting Initial Data for Data Registers D The initial data is transferred at the start of program execution D0001 a F040706 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 35 4 8 4 8 1 Special Registers Z Special registers have specific functions such as indicating the internal state of a programmable controller or detecting errors Sequence Operation Status Registers Sequence operation status registers indicate the status of sequence operation Table 4 14 Sequence Operation Status Registers Type Sequence Operation Status Registers No Name Stored Data Description 2001 Scan time L testiscan time Stores the latest scan time in 100 us Run mode increments Minim miscaritime Allows the latest scan time to be read in Z002 Minimum scan time 100 us increments if it is shorter than the Run mode ae minimum scan time Maximini scaritim e Allows the latest scan time to be read in Z003 Maximum scan time 100 us increments if it is longer than the Run mode A maximum scan time Scan time Stores the latest sca
166. ed and the program is executed using its own scan time END END instruction END 0 step instruction 0 step 0 step instruction 0 step l l l l l I l l l l l I l l l l l I l l l l l 1ms I I 3ms I ims I ae gt ys AAA Sao ae ee a gt i l l l l l l l l 2ms i 3ms 2ms ea er SS eS ee ye PIR SSS SS SSeS gt N Program s scan time F060302 VSD Figure 6 2 Operation Based on 2 ms Constant Scan Setting the Constant Scan Time You can set the constant scan time using the system configuration of project setting in WideField3 or Operation Control of configuration of WideField2 You can set the constant scan time to a value between 1 ms and 190 ms in 0 1 ms increments To disable constant scan select the option Do not use default AN CAUTION The constant scan time must be shorter than the scan timeout interval If the constant scan time is longer than the scan timeout interval a scan timeout error occurs IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 4 Executing All Blocks Specified Blocks Select the program execution mode All Blocks or Specified Blocks using the executable program configuration of project setting in WideField3 or Operation Control of configuration of WideField2 6 4 1 Executing All Blocks This mode executes all blocks of an executable program sequentially from block 1 The default program execution mode is All Blocks All blocks are executed
167. ed in the program memory of the sequence CPU module at the end of a given scan Y Addition 0001 poea O 00501 X00502 10003 Z X00503 10002 a Y00603 O LY X00501 X00502 a 1000 J CPU program memory l sai o o fo o The addition is reflected at the end of a given scan i L F060701 VSD Figure 6 14 Online Editing o WARNING Do not perform online editing when machinery under control is in operation When online edited data is written to the sequence CPU module scan time may become much longer than usual Scan time lengthens by as much as 10 ms for every 10K step increase in the program size During this time external refreshing or communications with external equipment are not allowed Edited changes are reflected to the CPU module at the end of conversion line deletion or online edit operations in WideField3 or WideField2 Special considerations of sequence processing apply during this update process before all changes are reflected If there is a differential type instruction in a circuit that is modified or added online or in the circuit following a circuit that is modified inserted or deleted online beware that the instruction will be executed as if its preceding value is OFF This means that the instruction may cause a differential output even if its input condition is always ON Different
168. ee ee teeeeeeeeeeeeeeeteneaeeeeeeeaees 4 19 4 4 3 Sequence Operation and Mode Status Relays 5 4 20 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 4 4 Self diagnosis Status Relays 0 0 eccececeeeeeeeeeeeeeeeeeeneeees 4 21 4 4 5 FA Link Module Status Relays cccceeeeeeeeeeeteeeeeeneeees 4 22 4 4 6 FL net Interface Module Status Relays eneeeneeeeeeen 4 22 4 5 Timers 1 ccvecececevcatectsctectsctens enc coehtbve anaU auaa ara aE narai 4 23 4 5 1 100 us 1 ms 10 ms and 100 ms Timers cccccceceeees 4 23 4 5 2 100 ms Continuous TimMer esseistinen 4 24 4 5 3 Selecting TIMES rececccncnineikiien ia 4 25 4 6 Counters C iccccide neat einasi a auaa aaeain aniano ridae tiie 4 26 46 1 Selecting Counters 2 cceceseeeeeestereeeecseneecessteeneeeseeneneestene 4 27 4 7 Data Register D Shared Register R and Extended Shared Register R wcsccccccssccccsccvccccteecctecenesteccteescteecenestueceesstuectee suneceeesceneciis 4 28 4 7 4 Data Registers D 0 cccceeeccececeeeceee cesses eeeeeeeteaeeeeaeeeeneeees 4 28 4 7 2 Shared Registers R and Extended Shared Registers R 4 29 4 7 3 Setting Initial Data for Data Registers D 0 4 33 4 8 Special Registers Z s cccssseeceeesseeeeessseeeeeessseeeeessseeeeeseeeeeenssseenees 4 35 4 8 1 Sequence Operation Status Registers c cccceeee 4 35 4 8 2 Self diagnosis Status Registers ceeeeeeeeeeeeeeeeeneees 4 35 48 39 Utility
169. eeeeeee 3 26 input sampling interval eceeeeeeeeeeeeeeeees 4 4 INCEMUPE esca a a 3 26 L LED irina E 1 11 3 1 8 1 link refreshing enccrenicnenarencieanieani 3 21 IM 34M06P13 01E 4th Edition M Macro INStFUCTION accedi eeeeentteeeeeeneeeeeeaee 6 43 momentary power failure detection 3 4 O online CCILING eee eee eeeteeeeeette eter teteeeeetnteeeeteee 6 16 Operating MOdE ccceceeeeeeeeeteeeeeeeteteees 3 1 6 2 P power failure 2 0 0 eee cece eeeceeceeeeeeeeeeetaeeeeeeeeeteees 3 4 power failure detection c cccececeeeseeeeeeeeees 3 3 program MEMOLSY 0 0 eee eeneeeeee teeter teenenneeeeeeeens 5 9 R relay devices forced SET RESET 05 6 12 FESpONSE ee 6 34 ROM management cceeeeceeeesteeeeetteeeeeeeaes 6 18 RUN MOG 1 cece eeeseeeeceeeeeeeeeseeeeeeees 3 1 4 20 4 35 S Sampling TrACE ceeeeeeeeeeeeeeeeeeeeteeeeeeeteeeeeeaes 6 24 scan IMG siii aii a 3 5 7 1 self diagnosis and corrective actions 8 2 sensor control sensor control block functions 6 59 Shared refreshing eccceeeeeeeeeeeeeeeeeeeeesueeeeeenaes 3 15 Stop MOdE cccececeeeseeeseseeeeeeeeeeeeeeeeeeeseneees 3 1 6 2 Stop emeShing 2 s cccceeseceeesesenecceseseccdeesbeaeeereae 6 13 co 0 e 0 ee eee 6 56 6 78 U user log MANAGEMENT eeeceeeeeeteeeeetteeeeeeees 6 58 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Bla
170. eeeeeeeeeeees Appx 3 1 Relay Devices Assignment Table eeeeeeeeeeeeeeeees Appx 3 2 Register Devices Assignment Table cccccceceeeeeeeeeeeeeeees Appx 3 3 Timer Counter Setpoints Table ssssssssnsnnnnnnnnnnnnnnnnnnnnnnnnnnn Appx 3 4 WRG sc cistisiiesie be edecedicebevedetenevedenecaedtiedctetscedecedeasderettiececelesederenwteneseds Index 1 IM 34M06P13 01E 4th Edition Jan 31 2012 00 Revision Information 2 c2cccecceeceecceeceeceecceeceecceeceeceeeseneeeceeseeeseeeseneeeesees i IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 1 1 Specifications and Basic Configuration This chapter explains the CPU module specifications and the basic configuration of the Range free Multi controller FA M3 1 1 Overview This section describes the overview features and main functions of the sequence CPU module E Overview Models F3SP28 3N F3SP38 6N F3SP53 4H F3SP58 6H F3SP22 0S F3SP28 3S F3SP38 6S F3SP53 4S F3SP58 6S and F3SP59 7S are CPU modules with built in memory for use with the Range free Multi controller FA M3 In addition to high speed operation and large memory capacity these modules have many more features that help increase development and maintenance efficiency E Features High speed Operation 20K steps 1 ms with shortest scan interval of 200 us High speed I P R S which means High speed Instruction High speed Performance High speed Response High
171. eeeeesseeeenseseenens 3 5 3 5 Method of Executing Peripheral Processes cccsssssseereeeeeeees 3 7 3 6 Method of I O ProCeSSinng sccccessseeeessseeeesseeeeeeeseeneeeesseeeeensseeeenees 3 8 3 6 1 Method of I O Processing 2 ccceceeeeeeeeseeeteteeeseeeeeeeeees 3 8 36 2 Response Delay acciisscsi ceiiegedesiaad os cnsvadecevesisiecabanpessasasienaiadjenss 3 9 3 6 3 I O Processing in Multi CPU System 3 10 3 7 Method of Executing Commands from WideField3 ccesee 3 11 S f 1 TOO SENCE auceo a AAE E EEA 3 11 3 8 Method of Executing Commands through Personal Computer Link cccceeceseeeseeeeeeeeeeeeseesseaeeeeeeeeeeeeeens 3 12 3 8 1 Personal Computer Link Service ccceeeeeeceeeeeeeeees 3 12 3 9 Method of CPU to CPU Data Communication c ccsseeeessseeres 3 13 3 9 1 Method of Updating Shared Data 0 0 eeeeeeeeteeeeeeee 3 13 3 9 2 Configuration of Shared Refreshing cceeeeeseeeeeeees 3 15 3 9 3 CPU SOrviCe eccune i a 3 19 3 10 Method of Link Data Updating cccccsssseneeeesseneeeeseeeeenseeteeennees 3 20 3 10 1 Link Data Updating neresno iaa 3 20 3 10 2 Link RefresNiNg eee aE EA 3 21 3 11 Method of Input Interrupt Processing sssssssssssesesennnnnnnnnnrnennnnnnnn 3 26 3 11 1 Input Interrupt Processing ces csecceceeeeeeeeeeeteeeeeeeeeeeees 3 26 3 11 2 Input Interrupt Processing Control ccecceeeseeeeeeeeeees 3 27
172. efreshing updates the link relays L and link registers W of system 1 or system 2 in each cycle of peripheral processing Link relays registers of Link relays registers of Link relays registers of System 1 FL net1 System 2 FL net2 System 1 FL net1 Results of link refreshing are reflected by this common processing Instruction execution Instruction execution Instruction execution Instruction execution One scan One scan One scan One scan F031007 VSD Figure 3 25 FL net Link Refreshing as a Peripheral Process When executed as a control related process link refreshing updates the link relays L and link registers W of system 1 or system 2 in each cycle of control processing Link relays registers of Link relays registers of Link relays registers of System 1 FL net1 System 2 FL net2 System 1 FL net1 Results of link refreshing are reflected by this common processing Instruction execution Instruction execution 7 Instruction execution Instruction execution One scan One scan One scan One scan py DK DK DK Figure 3 26 Executing FL net Link Refreshing as a Control related Process F031008 VSD TIP Table 3 6 shows an example of how link refreshing affects the scan time For more information see Section 7 1 Description of Scan Time Table 3 6 Durations of Interference by FL net Link Refreshing with the Scan Time Duration of Interference with Scan Time of Per
173. en add on CPU s are installed and shared refreshing is configured as a control related process In a single refreshing cycle this task updates the contents of shared extended shared relays E or shared extended shared registers R included in the configuration for each CPU When an add on CPU module is installed and shared refreshing is configured as a control related process 0 003 x number of shared relays set in the sequence CPU module for refreshing 32 number of shared registers set in the sequence CPU module for refreshing 2 0 10 ms if the sequence CPU module for which the devices are refreshed is F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 or F3SP76 0 014 x number of shared relays set in the sequence CPU module for refreshing 32 number of shared registers set in the sequence CPU module for refreshing 2 0 10 ms if the sequence CPU for which the devices are refreshed is other than those listed above Not performed if no add on CPU module is installed or shared refreshing is configured as a peripheral process 0 00 ms FL net link refreshing Updates the contents of link relays L and link registers W when FL net interface module s is installed and FL net link refreshing is configured as a control related process 0 0005 x Number of link relays to be refreshed 16 Number of link registers to be refreshed 0 30 ms Not performed if no FL net interface module is insta
174. en made to ensure accuracy in the preparation of this manual However should any errors or omissions come to the attention of the user please contact the nearest Yokogawa Electric representative or sales office E Safety Precautions when Using Maintaining the Product The following safety symbols are used on the product as well as in this manual A Danger This symbol on the product indicates that the operator must follow the instructions laid out in this user s manual to avoid the risk of personnel injuries fatalities or damage to the instrument Where indicated by this symbol the manual describes what special care the operator must exercise to prevent electrical shock or other dangers that may result in injury or the loss of life D Protective Ground Terminal Before using the instrument be sure to ground this terminal Function Ground Terminal Before using the instrument be sure to ground this terminal NITA Alternating current Indicates alternating current Direct current Indicates direct current IM 34M06P13 01E 4th Edition Jan 31 2012 00 The following symbols are used only in the user s manual A WARNING Indicates a Warning Draws attention to information essential to prevent hardware damage software damage or system failure A CAUTION TIP Indicates a Caution Draws attention to information essential to the understanding of operation and functions Indicates a TIP
175. ence CPU module Each sequence CPU module refreshes the terminals independently according to the definition Be careful not to configure the CPUs so that more than one CPU refreshes the same terminal of the output module Otherwise the resultant output of the output module will be indefinite SEE ALSO For details on the parameters set for I O modules and their limitation of use see Subsection 2 2 2 Handling I O Modules in Multi CPU System and subsection 4 1 4 Configuring DIO Modules Main CPU module sequence CPU or BASIC CPU module supply module Power gt 001 002 mle 005 006 007 008 009 010 011 012 013 lt Slot numbers Add on CPU modules sequence CPU or BASIC CPU modules F030603 VSD Figure 3 8 Example of Multi CPU System IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 11 3 7 3 7 1 Method of Executing Commands from WideField3 Commands from WideField3 or WideField2 are executed by the tool service These commands include downloading and uploading of programs as well as monitoring of devices Tool Service The tool service executes commands sent from the FA M3 programming tool WideField3 or WideField2 Since the tool service runs concurrently to the execution of instructions it does not affect the scan time The CPU does not execut
176. ent complex reusable input conditions as a single instruction By calling the Output of Input Macro NMOUT instruction internally an input macro instruction can also output the result of logical operation to the next instruction N INLET1 Converting into a Macro instruction Increased reusability and readability F061309 VSD Figure 6 39 Benefits of Input Macro Instructions E How to Use Creating an Input Macro Instruction Input macro instructions can be created like ordinary macro instructions Macro instructions called by the Input Macro Instruction Call NCALL instruction are called input macro instructions Thus the same macro instruction entity can be either an input macro instruction if called by NCALL or a macro instruction if called by MCALL Calling an Input Macro Instruction Use the Input Macro Instruction Call NCALL instruction to call an input macro instruction SEE ALSO For details on the NCALL instruction see Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E Where to Code an Input Macro Instruction Call NCALL Instruction You can code an NCALL instruction along with the LOAD AND or OR logical operator You cannot use it in place of an output instruction at the right end of a ladder rung To call a macro instruction at the position of an output instruction use the MCALL instruction
177. er 3072 max 3072 max IM 34M06P13 01E 3072 max 4th Edition Jan 31 2012 00 1 7 1 2 3 Configuration This section describes the configuration function The configuration setup ranges are summarized in the table below E Configuration Function The sequence CPU contains the predefined defaults of device sizes and operation methods You can use these defaults to run programs In some applications however they may not suit your specific purpose of use In such a case flexibility allows for defaults to be changed to meet your needs Changing the defaults is called configuration and can be performed through the FA M3 programming tool WideField3 hereinafter simply referred to as WideField3 and the FA M3 programming tool WideField2 E Tables of Configuration Ranges Table 1 6 Configuration Range 1 5 F3SP22 0S F3SP28 3N F3SP28 3S F3SP53 4H F3SP53 4S Item Default Configuration Range 2048 points max on 32 point Shared relay E basis for all CPUs combined Extended shared relay 2048 points max on 32 point E basis for all CPUs combined 1024 points max on 2 point basis Shared register R for all CPUs combined Extended shared 0 3072 points max on 2 point basis register R for all CPUs combined System 1 to 4 2048 8192 points max on 16 point Link relay L System 5 to 8 0 basis for all links combined System 1 to 4 2048 8192 points max on 16 point System 5 to 8
178. eripheral processes whose purpose is to support communication and WideField3 or WideField2 Thus the system of control related processes can run at extremely high speeds Under normal conditions the scan time of the sequence CPU module is equivalent to the time taken by the system of control related processes The following paragraphs explain the processing tasks and time of each of these systems System of Control related Processes The latest minimum and maximum of scan times taken by the system of control related processes are stored in special registers Z001 to Z003 in that order IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 2 Common processing Table 7 1 Scan Time of System of Control related Processes Processing Task Self diagnosis Processing Time Fixed at 0 2 ms Program execution Output refreshing Executes ladder programs The scan time is calculated using the program execution time or output refreshing time whichever is greater Writes the contents of output relays Y to an output module The scan time is the sum of the execution times of basic and application instructions It varies depending on the execution time of each instruction word For details see Section 7 5 Instruction Execution Time 12 us x number of modules calculated on a 16 points basis Shared refreshing Updates the contents of shared extended shared relays E and shared extended shared registers R wh
179. es of forced set or forced reset Changing Setpoints Current Values and Data Values Changing Setpoints You can change the setpoints of timers T and counters C Changing Current Values You can change the current values of timers T and counters C If you set a current value of 0 a timer expires and a counter terminates Changing Word or Long word Data Values You can change the data values of word devices other than timers T and counters C such as data registers D If you specify a bit device such as an internal relay I instead of a word device 16 or 32 bits of device data are changed beginning with the first device address IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 13 6 5 3 Stopping Refreshing You can prevent external equipment input relays X and output relays Y FA link or FL net systems relays L and link registers W as well as add on CPU modules shared relays E and shared registers R from being refreshed by the results of program execution This allows you to visually check I O data on the monitor In the case of relays input relays X and output relays Y for external equipment you can stop refreshing X input relays and Y output relays separately Y00602 X00502 YG0601 X00504 Y00603 I 00501 X00502 90604 X00503 i External equipment The output is not refreshed F060504 VSD Figure 6 11 Stopping Output Refreshing A CAUTI
180. es the status of CPU Misi Stop mode flag OFF Other modes operation ON Pause Indicates the status of M132 Pause flag program execution during OFF Run debug mode operation M133 Execution fla ON Specified blocks Indicates whether all blocks or 9 OFF All blocks specified blocks are executed M135 RAM ROM based ON ROM based operation Indicates whether operation is operation flag OFF RAM based operation based on the ROM or RAM ON Power on operation Indicates whether operation M136 Power on operation flag OFF Other modes of was initiated by power on or operation reset M137 Sensor CB execution ON Run Indicates the status of sensor status OFF Stop control block operation M172 F ON Time being set write enabled Set clock time OFF Requests to set clock data ON Offline Indicates that input refreshing M173 Input offline flag OFF Online has stopped ON Offline Indicates that output Mie Output offline flag OFF Online refreshing has stopped ON Offline Indicates that shared M175 Shared l O offline flag OFF Online refreshing has stopped ON Offline Indicates that link refreshing M176 Link I O offline flag OFF Online has stopped M177 to M187 Devices reserved for extended functions ON Carry enabled A carry flag used by shift and M188 Carry flag OFF Carry disabled rotate operations M189 to M192 Devices reserved for extended functions SEE ALSO IM 34M06P13 01E For more detail
181. es whether or not a CPU exists in slot 2 Existence of CPU3 Exists Does not exist Indicates whether or not a CPU exists in slot 3 Existence of CPU4 Exists Does not exist Indicates whether or not a CPU exists in slot 4 Instruction Processing Error Error Normal Information of instruction processing error is stored in special registers Z22 to Z24 I O Comparison Error Error Normal Indicates that the state of module installation is not consistent with the program I O Module Error Error Normal Indicates that no access is possible to I O modules The slot number of the error module is stored in special registers Z33 to Z40 Scan Timeout Error Normal Indicates that scan time has exceeded the scan monitoring time Subunit Communication Error Error Unspecified or normal line Subunit Transmitter Switching Has Occurred Error Unspecified or normal line An error has been detected in the fiber optic FA bus module The slot number of the error module is stored in special registers Z89 to Z96 Sensor CB Scan Timeout Error Normal Indicates that the execution interval of the sensor control block cannot be maintained CPU1 Sequence Program Execution Executes the program Stops the program Indicates whether sequence program of CPU in slot 1 is running CPU2 Sequence Program Execution
182. eseeeeeeesesneeenseseenens 7 4 7 3 Examples of Scan Time Calculation cccccessseseeeneeeeeeeeeeesseenees 7 4 7 4 Example of I O Response Time Calculation cssssseeceeeees 7 6 7 5 Instruction Execution Titme ccccsceeeeeceeeeeeeeeeeeeeeeceeeeeseeneeeneeeeeeens 7 7 8 RAS PUNCHONS isea aaa a eee 8 1 8 1 DO lf AIAQGMOSIS i scseccscccesizesscceessxeccetscascceeas cascceessxennnissasaacessaedencesgacacei iis 8 1 8 1 1 Setting Error time Action Operating Mode in Case of ETOT Ji vuetesccteeidecevetl nnn eeene eee hvdieisked saranda titative 8 5 8 2 Updating Error Status Indicators after Correcting Moderate or Minor Failures oivzccccscsnrecies ce cciatsedacdessvexvensdenheeszvcecerectueeracssivensnateueeesi 8 6 9 Differences from F3SP25 and F3SP35 Sequence CPUs 9 1 9 1 Comparison of Functional Specifications cccccseesseeeeeneee 9 1 9 2 Configuration ssni daresanecstebaus evevcacstestyenccets 9 3 9 3 Special Relays M and Special Registers Z cceecssseeenseeeerens 9 4 9 4 CPU Module to CPU Module Communication Method 9 5 9 5 High speed Processing of Application Instructions 2 00 9 5 9 6 WMSTPUCTIONS aeieea nre Raana cecnensatananuacieacteanaanaaneanecineaantanaanane 9 6 10 Difference between F3SPOO OS and F3SPOO ON OH 10 1 10 1 Partial Download FunctionS sssssssssesesessnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnne 10 1 10 2 Stori
183. estination may be read by the sensor control block Simultaneity of data is required when data of multiple devices is exchanged between a normal scan program and the sensor control block program using a block transfer BMOV instruction a long word instruction with IEEE single precision floating point data or two or more instructions If simultaneity of data is required when interrupt timing is configured as Immediate during instruction execution use any of the following means to ensure data simultaneity 1 Use a Disable Sensor Control Block CBD instruction and an Enable Sensor Control Block CBE instruction to prevent the sensor control block from being executed during exchange of multi device data 2 Write an application program to perform flag control between the normal scan program and the sensor control block using relays IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 67 E Priority of Interrupts You can specify the priority of interrupts by configuration using WideField3 or WideField2 for conflict resolution in the event that interrupt processing of an interrupt from an input module coincides with an interrupt from a sensor control block The table below lists the two options for Priority of Interrupts along with how they work Table 6 28 Options for Priority of Interrupts Functionality Priority of When an interrupt from an input When the time for executing a sensor Interrupts module occurs dur
184. extended shared registers R Hereafter shared relays E extended shared relays E shared registers R and extended shared registers R are collectively referred to as shared devices You must configure in advance the range of shared devices to be used for each installed CPU module The configuration of a CPU module must tally with the configuration of the other CPU modules You can both read from and write to shared devices within a CPU module s own area However you can only read from shared devices within the areas of the other CPU modules SLOT1 SLOT2 SLOT3 SLOT4 CPU1 CPU2 CPU3 CPU4 Shared register Shared register Shared register Shared register area area area area POT SRS as RSS S SRS Sasa pa E A E ees ryt A Read write i 1 ft 1 4 4 CPU1 area i an e DE E ES EEE EEE E sce eae F030901 VSD Figure 3 11 Example of Configuring Shared Registers R IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 14 The figure below shows an example of shared refreshing carried out between a sequence CPU module and an add on CPU module In this example shared relays E and shared registers R are allocated as shown below Sequence CPU module Shared relays E E0001 to E0512 Slot1 CPU Shared registers R R0001 to R0256 Add on CPU module Shared relays E E0513 to E1024 Slot2 CPU Shared registers R R0257 to R0512 SLOT1 CPU X00502 MOV 100 R0001
185. formation data from the sequence CPU module and saves it to a WideField3 or WideField2 file You can specify the range of devices to be saved E Download Device Data This function allows you to read device information data from a WideField3 or WideField2 file and writes it to the sequence CPU module You can either download all device data from the file or download part of the data by specifying a range of devices E Edit Device Data This function allows you to edit device information data in a WideField3 or WideField2 file You can view and change the current value of each device Compare Device Data This function allows you to compare device information data in the sequence CPU module with that in a WideField3 or WideField2 file You can make a comparison of all device data in the file or part of the data by specifying a range of devices If any mismatch is found the function shows the device name and content of the mismatch IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 13 6 13 1 6 43 Macro Instructions This section describes macro instructions Macro instructions allow reuse of created programs for increased programming efficiency In addition the use of macro instructions allows compact program codes structured by function thus improving program readability and maintainability What Are Macro Instructions E Overview A macro instruction enables a process requiring multiple instructions steps to be
186. gain In addition it is possible to input a corrective value from the programming tool If you input a precise corrective value the clock data is corrected during the power off and on sequence thus offsetting the cumulative amount of error IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Appx 2 4 Appendix 2 4 FA Link Module Status Registers FA Link module status registers indicate the status of FA link SEE ALSO For details on the FA link module status registers see Special relays registers sections in FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E Table Appendix 2 4 FA Link Module Status Registers FA Link Module Status Registers Z077 Local Station No System 3 FA link Z078 Z079 Z080 Name Local Station No Local Station No Local Station No Local Station No Local Station No Local Station No Function Description System 1 FA link System 2 FA link System 4 FA link System 5 FA link System 6 FA link System 7 FA link Local Station No System 8 FA link Local Station Status 0 Initialization in progress Offline Online System 1 FA Link Cyclic Transmission Time System 1 FA Link ims increments Local Station Status Initialization in progress Offline Online System 2 FA Link Cyclic Transmission Time System 2 FA Link ims increments Local Station Status Initialization in progress Offline Onli
187. gram is executed and output refreshing is completed Unit 10 us Maximum Sensor CB Refers to the maximum time taken to execute the sensor control execution time block Unit 10 us Sensor CB execution time IM 34MO06P13 01E 4th Edition Jan 31 2012 00 9 4 9 5 9 5 CPU Module to CPU Module Communication Method Data Sharing The availability of the simultaneity of data in CPU to CPU communication between shared relays E and shared registers R and between extended shared relays E and extended shared registers R is as shown in the following table Availability of F3SP22 Simultaneity of F3SP28 Data among F3SP25 F3SP38 CPU Modules F3SP35 F3SP53 F3SP58 F3SP59 F3SP25 F3SP35 F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 There is no simultaneity of data in CPU module to CPU module communication between shared relays E registers R and extended shared relays E registers R Stopping Shared Refreshing Partially You can exclude a particular CPU or CPUs from shared refreshing Defining Shared Refreshing as a Control related Process You can determine whether shared refreshing is performed as a control related process or a peripheral process High speed Processing of Application Instructions The F3SP25 and F3SP35 sequence CPUs do not support high speed processing for Application Instructions that use any of the devices listed below In contrast the F3SP22 F
188. gramming Tool WideField3 IM 34M06Q16 O00E or FA M3 Programming Tool WideField2 IM 34M06Q15 01E FON CAUTION A structure macro instruction may not call another structure macro instruction A structure macro instruction may be called only by a block A CAUTION If the type of a structure passed using a structure macro instruction is different from the structure type declared by a structure pointer declaration instruction in the called structure macro instruction the latter structure type is used during execution with no error generated AN CAUTION Structure macros use pointer registers P4 to P8 IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 57 E How to Use Structure Type Definition Defines the name and members of a structure type Structure Object Definition Allocates actual registers to structure data Creating Structure Macro Instructions Structure macro instructions can be created just like ordinary macro instructions Macro instructions called by the structure Macro Instruction Call SCALL instruction are called structure macro instructions Structure Type Declaration STRCT for Structure Macro Instructions At the very beginning of a structure macro instruction you must declare the type of the structure to be passed One structure type declaration is required if one structure is to be passed Two structure type declarations are required if two structures are to be passed Calling
189. hange data between CPUs in a multi CPU system configuration Shared registers R can be used regardless of how CPUs are combined Extended shared registers R can only be used with sequence CPU modules F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 and F3SP59 In programs you can read from or write to data registers on word or long word basis using application instructions When you use a long word string the low order 16 bits are stored in the data register with the number specified in the instruction and the high order 16 bits are stored in the data register with that number incremented by 1 Data can be exchanged between the own CPU module and other CPU modules by writing the data to shared registers in the own CPU module and reading it from other CPU modules If you write data to a device area not belonging to the own CPU module data held by shared registers R of other CPU modules are overwritten and so operation results are not correctly reflected By default no shared registers are allocated as devices When using add on CPU modules configure the range of shared registers to be used Allocate the same device range for all of the CPU modules Otherwise the shared registers R will not be correctly refreshed SEE ALSO Shared and extended shared registers R are used to exchange data data sharing between CPUs in a multi CcPU system configuration between sequence CPU modules and BASIC CPU modules For detail
190. he normal scan program Priority of Interrupts You can specify the priority of interrupts by configuration using WideField3 or WideField2 Priority of Interrupts of Interrupt Setup for conflict resolution in the event that input interrupt processing coincides with an interrupt from a sensor control block The table below lists the two options for Priority of Interrupts along with how they work Table 3 9 Options for Priority of Interrupts Functionality Priority of When an interrupt from an input When the time for executing a Interrupts module occurs during execution sensor control block arrives of a sensor control block during interrupt processing Suspends the interrupt process and resumes execution after executing the sensor control block Sensor CB interrupt has priority default Suspends the interrupt process after executing the sensor control block Suspends the execution of the Input interrupt sensor control block and resumes Executes the sensor control block has priority execution after executing the after executing the interrupt process interrupt process AN CAUTION The sequence CPU applies the rule of interrupt execution timing after completion of instruction execution or immediately during instruction execution discussed earlier even in the case where execution of the sensor control block or interrupt process is suspended due to priority of interrupts IM 34M06P13 01E 4th
191. hese relays in an input interrupt program there is no limitation on data input however Example Input interrupt program OUT 12 Normal scan program OUT 11 Not allowed OUT 117 Allowed The same rule applies to relays numbered 17 to 32 33 to 48 49 to 64 and so on If both the interrupt program and normal scan program output to these relays no output may be generated Simultaneity of multi device data when input interrupt programs are executed immediately during instruction execution Simultaneity of data for multiple devices is not guaranteed if input interrupt programs are executed immediately during instruction execution Simultaneity of data is required when data of multiple devices is exchanged between a normal scan program and an input interrupt program using a block transfer BMOV instruction a long word instruction with IEEE single precision floating point data or two or more instructions For example consider the case shown in Figure 3 30 where an input interrupt program is executed during execution of a block transfer BMOV instruction in a normal scan There is a risk that block data partially transferred may be overwritten after the execution of the input interrupt program If simultaneity of data is required when interrupt timing is configured as Immediate during instruction execution use any of the following means to ensure data simultaneity 1 Use a Disable Interrupt DI instruction and an En
192. ial type instructions include the following LDU LDD UP DWN UPX DWNX DIFU DIFD FF TIM CNT SFTR and input differential type instruction lf a circuit that contains a timer instruction is modified or added the time out relay may stay ON when the timer input is OFF or the timer may not start running when the timer input is ON depending on the preceding value In this case the rising edge of the next timer input enables normal operation IM 34MO06P13 01E 4th Edition Jan 31 2012 00 AN CAUTION 1 You are not allowed to modify the following instructions and circuits Subroutine Entry SUB instruction and Subroutine Return RET instruction as well as circuits that contain any of these instructions Interrupt INTP instruction and Interrupt Return IRET instruction for input modules as well as circuits that contain any of these instructions Structure Macro Instruction Call SCALL instruction Structure Move STMOV instruction as well as circuits that contain any of these instructions 2 Online editing affects peripheral processing Peripheral processing time may lengthen by approximately 200 ms though this depends on the program size or the location in the program where modifications are made During this time the CPU does not perform shared refreshing link refreshing or command processing IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 8 6 8 1 Making Programs Resident Using ROM Writer Functions
193. ied to the parameter that is passed In the example shown in the above figure P01 U01 is the same as device D0003 because P01 D0001 and U01 2 m Macro Relays H Macro Registers A and Macro Index Registers U These devices are dedicated to macro instructions Within a macro instruction entity you can read from and write to macro relays macro registers or macro index registers using basic or application instructions the same way as for internal relays I data registers D and index registers V These devices can be used within a macro instruction entity By using these devices in your macro entity you need not know which devices are used in the macro instruction call Needless to say the values of these devices remain unchanged IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 49 E Structure Pointer Registers Q Structure Pointer Registers are dedicated registers used for passing structure data to structure macro instructions It is used within structure macro instruction entities The relationship between structure pointer registers Q and structure macro instruction parameters is shown in the figure below S ROAD STR1 STR2 j j H O ee Parameter 2 j E EE EEEE Parameter 1 F061308 VSD Table 6 19 Relationship between a Structure Pointer Register Q and Structure Macro Instruction Parameters Operand Structure pointer register number 1 parameter 1 Q01 2 parameter 2 Q02 Within a st
194. if there is a jump out of or into the IL ILC loop Check if a scan timeout has been detected within the IL ILC loop 1 Check if there is a jump out of or into the macro instruction 2 Check if a scan timeout has been detected within a macro instruction 1 Although a macro instruction may call another macro instruction nesting the nesting may not be more than 7 levels deep There may be a mismatch between the I O relay X Y devices specified in the program and those contained in the installed I O module Check if the instruction parameter in question is consistent with the installed 1 0 module Check if the number of special module High speed Read HRD instructions or the number of special module High speed Write HWR instructions exceeded 64 There may be a mismatch between the slot number in READ WRITE instructions used in the program and that of the installed I O module Check if the instruction parameter in question is consistent with the installed I O module 2 The CPU module can be configured to stop or continue execution of the program for this error event IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Failure Mode Moderate failure Minor failure 1 0 comparis error I O module error 2 3 Subunit communication error Sensor CB scan timeout Momentary power failure Inter CPU communication error Subunit transmitter switching has occurred Tab
195. imum nesting depth seven levels is exceeded IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 13 6 6 13 7 6 53 Protecting Macro Instructions You can protect macro instructions against unauthorized read access The protection can be configured on per macro instruction basis by entering a password using WideField3 or WideField2 A password must consist of eight alphanumeric characters beginning with a letter The protection information is saved in the management information area of a macro instruction file A protected macro instruction can be edited printed or monitored only if the password matches TIP Executable program protection and block protection also apply to user created ladder programs containing macro instructions For instance if executable program protection is enabled downloading uploading monitoring online editing and other operations on the executable program are not allowed Debugging Operation E Forced Set and Forced Reset You can force bit devices to turn ON or turn OFF in macro instructions either in a macro call or within a macro instruction entity E Partial Operation Partial operation is not allowed within a macro instruction entity IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 13 8 6 54 Input Macro Instructions An Input Macro Instruction is a type of macro instruction that can be used as an input condition just like the Load or Compare instruction It can repres
196. in CPU for refreshing 2 0 10 ms if the CPU module for which the devices are refreshed is F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 or F3SP59 0 014 x number of shared relays set in CPU for refreshing 32 number of shared registers set in CPU for refreshing 2 0 10 ms if the CPU module for which the devices are refreshed is other than those listed above Not performed if no add on CPU module is installed or shared refreshing is configured as a control related process 0 00 ms FA link refreshing Updates the contents of link relays and registers when an FA link module is installed When an FA link module is installed 0 015 x number of relays used in FA link for refreshing 16 number of registers used in FA link for refreshing 0 06 ms Not performed if no FA link module is installed 0 00 ms FL net link refreshing Updates the contents of link relays L and link registers W when FL net interface module s is installed and FL net link refreshing is configured as a peripheral process 0 0005 x Number of link relays to be refreshed 16 Number of link registers to be refreshed 0 30 ms Not performed if no FL net interface module is installed or FL net link refreshing is configured as a control related process 0 00 ms Tool service Processes commands input from the WideField3 or WideField2 connected to the sequence CPU module Executes one command per service Varies with the ty
197. in commands and responses The individual elements are detailed below STX Start of Text Code This control code identifies the beginning of text The corresponding character code is 02 Station No The station No is fixed at 01 when the personal computer link functions of the sequence CPU module are used CPU No Identifies the target sequence CPU module or add on CPU module for a command using a number from 01 to 04 01 Sequence CPU module 02 Add on CPU module 1 03 Add on CPU module 2 04 Add on CPU module 3 IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 35 Response Wait Time You can specify the maximum waiting time time delay of up to 600 ms for a response following a command transmission Set a longer wait time if the communication software running on the higher level computer is say a BASIC interpreter Specify this time using one character 0 to F as shown below Table 6 10 Response Wait Time Response Wait Response Wait Character Time Character Time ms ms NI cn BS co po o TIM DO CE 9 gt co co Higher level ee eee Response wait time sree gt computer J or monitor 1 Pre Post Rasoonse processing procesing P Processing One scan Pause between scans One scan CPU module F061107 VSD 1 Even if the response wait time is set at 0 there is a delay of as much as the internal processing time Figure 6 30 CPU
198. in the 5th or higher slot of the main unit and turning on the power After confirming that the RDY lamp is lit you may then turn off the power In the case of a transient memory error due to noise download the application program again If the error disappears you can continue to use the module If the error recurs there may be a hardware failure In this case replace the sequence CPU module 8 1 1 Setting Error time Action Operating Mode in Case of Error E Setting Error time Action Operating Mode in Case of Error Using the configuration function you can select Stop stop execution for moderate failure or Run continue execution for minor failure for some faults such as an instruction error The table below summarizes the configuration items and their defaults If a failure for which you have selected the Run option actually occurs the CPU fails to correctly perform such tasks as accessing the I O module that caused the failure or processing instructions Configuration Item Default I O module error I O comparison error Instruction error Scan timeout Subroutine error Interrupt error Sensor CB scan timeout Stop moderate failure Subunit communication error SEE ALSO Run minor failure For details on the failure mode subunit communication error see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 3
199. ing execution of a control block arrives during input sensor control block interrupt processing Sensor CB Executes the input interrupt process after Suspends the input interrupt process interrupt has and resumes execution after executing priority default the sensor control block executing the sensor control block Suspends the execution of the sensor control block and resumes execution after executing the input interrupt process Executes the sensor control block after executing the input interrupt process Input interrupt has priority TIP The sequence CPU applies the rule of interrupt execution timing after completion of instruction execution or immediately during instruction execution discussed earlier even in the case where execution of the sensor control block or input interrupt process is suspended due to priority of interrupts E Activating Deactivating Sensor Control Block You can activate the sensor control block using an Activate Sensor Control Block CBACT instruction or stop the sensor control block using an Inactivate Sensor Control Block CBINA instruction At the start of operation the sensor control block defaults to the Stop status To activate the sensor control block execute an Activate Sensor Control Block CBACT instruction in a normal scan program An initial startup of the sensor control block takes place within 100 us after the execution of a CBACT instruction Table 6 29 Instruction
200. ipheral Processing 4 652 ms 0 ms Duration of Interference with Scan Time Number of Link Devices Refreshing as control Link relay L 8192 units related process Link register W 8192 units Refreshing as peripheral Link relay L 8192 units process Link register W 8192 units 3 782 ms 4 652 ms IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 25 E Inter mixing FA Link Modules and FL net Interface Modules Where FA link and FL net are intermixed in a system configuration FA link refreshing and FL net link refreshing are executed independently of each other If FL net link refreshing is configured as a peripheral process FA link refreshing and FL net link refreshing are executed in each cycle of peripheral processing System 2 FA link System 1 FL net System 3 FA link System 1 FL net System 2 FA link link refreshing link refreshing link refreshing link refreshing link refreshing Results of link refreshing are reflected by this common processing Instruction execution Instruction execution Instruction execution Instruction execution 1 I I I I 1 I 1 I I 1 I 1 I 1 i One scan i One scan H One scan i One scan i F031009 VSD Figure 3 27 Intermixing FA Link and FL net Even if FL net link refreshing is configured as a control related process FA link refreshing always remains executed as a peripheral process IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 1
201. is enabled the following functions are prohibited Downloading uploading monitoring circuit diagram monitoring debug operation changing timer T counter C setpoints online edit ROM writer functions and printing IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 6 2 Block Protection Block protection protects programs on per block basis This protection mode is only designed to prevent unauthorized read access In addition only the specified blocks are protected When block protection is enabled for a block its circuit diagrams and instructions are not displayed in WideField3 or WideField2 Personal computer be N NI Block m N X00501 X00502 Y00601 S Hi OH bzs 00509 l aN N ane aks ae n c ae 4 Only the protected block is excluded from display F060602 VSD Figure 6 13 Block Protection When block protection is enabled the following functions are prohibited Monitoring circuit diagram monitoring debug operation changing timer T counter C setpoints and online edit and printing IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 7 6 16 Online Editing Online editing allows you to make modifications or additions to your program during program execution This function is useful for making minor changes to the program during debugging or tuning Modifications changes made to the program are reflect
202. is necessary to set it again The maximum text length that can be transmitted or received each time by the personal computer link functions is 512 bytes However the maximum size that can be received by a higher level computer may be limited to 256 bytes in some cases In such cases make sure that the response text length does not exceed 256 bytes by reducing the number of devices to be read IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 12 6 42 Device Management Functions The device management functions enable you to upload download edit and compare device information data of the sequence CPU module using WideField3 or WideField2 You can specify the range of device data to be uploaded or downloaded You can also use these functions to perform initial setup of device data when for example replacing the CPU module The devices that you can configure using the device management functions are Internal relays I shared relays E time out relays and current values of timers T end of count relays and current values of timers C data registers D shared registers R link registers W index registers V and file registers B You cannot configure the following devices I O relays X Y setpoints of timers T and counters C special relays M and special registers Z The device management function serves the following four purposes E Upload Device Data This function allows you to read device in
203. it communication error and M211 Subunit transmitter switching has occurred self diagnosis relays see Fiber optic FA bus Module and Fiber optic FA bus Type 2 Module FA bus Type 2 Module IM 34M06H45 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 22 4 4 5 4 4 6 FA Link Module Status Relays FA Link module status relays indicate the status of FA links Table 4 9 FALink Module Status Relays kem FA Link Module Status Relay Name Function Description M257 a MAA ON Error M8321 to M8992 FA link error OFF Normal Indicate the status of FA links SEE ALSO For details on FA link module status relays see special relays registers sections of FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E FL net Interface Module Status Relays FL net interface module status relays indicate the status of FL net Table 4 10 FL net Interface Module Status Relays FL net Interface Module Status Relay Name Function Description M3521 to M3774 Node participation status i R cenlpetiag 1 Error 0 Normal 1 Run 0 Stop 1 Valid FL net system 1 M3777 to M4030 Upper layer operation signal error FL net system 1 M4033 to M4286 Operation status FL net system 1 4 M4289 to M4542 Common memory data valid O Invalid FL net system 1 1 Participating M4561 to M4814 Node participation status 0 Not participating FL net system 2 M4817 to M5070 Upper layer ope
204. ition Jan 31 2012 00 6 72 1 Use a Disable Sensor Control Block instruction CBD and an Enable Sensor Control Block CBE instruction to prevent the sensor control block from being executed during exchange of multi device data 2 Write an application program to perform flag control between the normal scan program and the sensor control block using relays Data simultaneity of devices to be refreshed Simultaneity of data is not guaranteed if in the sensor control block an access is made to I O relays X Y refreshed in a regular block or to shared extended shared relays E shared extended shared registers R link relays L or link registers W The sensor control block is executed even during normal scan input refreshing output refreshing and common processing If you read any of the above mentioned devices in the sensor control block a device value being refreshed may be read Likewise if you write to the device the device value being refreshed may be overwritten Consequently simultaneity of data may be lost To prevent the sensor control block from being executed during normal scan input refreshing output refreshing and common processing execute a Disable Sensor Control Block CBD instruction to disable the block at the end of a regular program and execute an Enable Sensor Control Block CBE instruction to enable the block at the beginning of the program IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 73
205. k oe 0000 to as a BCD coded value e g Wednesday as 0003 Constant Scan Value of constant scan 0 1 ms increments Time time e g 10 ms as 100 Constant Scan Value of constant scan 1 ms increments Time time e g 10 ms as 10 Scan Monitoring Value of scan monitoring 1 ms increments Time time e g 200 ms as 200 Month Available with the F3SP22 F3SP28 F3SP38 F3SP58 and F3SP59 only Setting Clock Data For CPU module F3SPOO OS use Set Date instruction DATE Set Time instruction TIME Set Date String instruction SDATE and Set Time String instruction STIME to set clock data For CPU module F3SPOO ON OH follow the procedure given below to set clock data 1 Write the clock data to special registers Z049 to Z054 use a MOV P instruction 2 Set special relay M172 to ON within the same scan as that in step 1 use a DIFU instruction 3 Set special relay M172 to OFF in the scan subsequent to that in step 2 Also stop writing the clock data to special registers Z049 to Z054 in that scan Note that no change is made to the clock data and the data reverts to its original values if the values being set are incorrect Clock Data Accuracy The accuracy of clock data is specified as Maximum monthly error 8 s 2 s when actually measured The clock accuracy is reset to the maximum daily error of 1 2 s 2 s however when the power is turned off and on a
206. le 8 2 Details on Self diagnosis 3 3 Special Relay that Turns ON on ey Special Registers that Store Error Codes Etc Z027 to Z029 Z033 to Z040 Z089 to Z096 Z089 to Z096 Stored Error Code Failed slot number Failed slot number Failed slot number Failure Description 2403 Special module High speed Read instruction HRDY special module High speed Write instruction HWR There is a failure to read from or write to the I O module There is a communication failure in the fiber optic FA bus module An attempt has been made to reset one of the other sequence CPU modules in a multi CPU system The scan monitoring time has been exceeded There is a failure to read from or write to the subunit The CPU fails to maintain the execution interval of the sensor control block as it is exceeded by the sum of its I O refreshing time and execution time The CPU indicates that a momentary power failure has occurred There is a communication failure in shared devices There is a problem with the paired cables attached to remote I O modules in a loop configuration Application error Application error Application error Open circuited cable Loss of power to subunit Hardware failure Application error Momentary power failure Hardware failure Open circuited cable Corrective Actions 1 There may be a mismatch between the slot numbe
207. lity Registers Table 4 16 Utility Registers 4 37 Utility Registers Z049 write enabled Z050 write enabled Z051 write enabled Z052 write enabled Z053 write enabled Clock data Stored Data Last two digits of calendar year Description Stores year as a BCD coded value e g 1999 as 0099 2000 as 0000 Month Stores month as a BCD coded value e g January as 0001 Day Stores day of month as a BCD coded value e g 28th as 0028 Hour Stores hour as a BCD coded value e g 18 00 hours as 0018 Minute Stores minute as a BCD coded value e g 15 minutes as 0015 Second Stores second as a BCD coded value e g 30 seconds as 0030 Day of week 0 to 6 Stores day of week as a BCD coded value e g Wednesday as 0003 Constant scan time Value of constant scan time 0 1 ms increments e g 10 ms as 100 Constant scan time Value of constant scan time 1 ms increments e g 10 ms as 10 Scan monitoring time Value of scan monitoring time 1 ms increments e g 200 ms as 200 For CPU module F3SPOO OS you can set clock data using the Set Date instruction DATE Set Time instruction TIME Set Date String instruction SDATE and Set Time String instruction STIME For CPU module F3SPOO ON OH use the following procedure to set time data 1 Write the clock data to special registers Z049 to Z054
208. lled or FL net link refreshing is configured as a peripheral process 0 00 ms Input refreshing Write the contents of input modules to CPU input relays X 6 us x number of modules calculated on a 16 point basis Synchronization processing Ensures synchronization of operation control related processing and the simultaneity of data between the system of control related processes and the system of peripheral processes When output relays Y are used 8 us x number of modules calculated on a 16 point basis When FA link modules are used 0 003 x number of relays used in FA link to be refreshed 16 number of registers used in FA link to be refreshed 0 05 ms When an FL net module is used and FL net link refreshing is configured as a peripheral process 0 0004 x number of link relays to be refreshed 16 number of link registers to be refreshed 0 30 ms When an add on CPU is installed and shared refreshing is configured as a peripheral process 0 002 x number of shared relays set in CPU for refreshing 32 number of shared relays set in the CPU itself 32 number of shared registers set in CPU for refreshing 2 number of registers set in the CPU itself 2 0 05 ms When an add on CPU module is installed and shared refreshing is configured as a control related process 0 002 x number of shared relays set in the CPU itself 32 number of shared registers set in the CPU itself 2 0 05 ms Peripheral
209. lling another subroutine in a given subroutine IM 34MO06P13 01E 4th Edition Jan 31 2012 00 8 3 Failure Mode Moderate failure Instruction error Macro instruction error I O comparison error Interrupt error Table 8 2 Details on Self diagnosis 2 3 Special Relay that Turns ON Special Registers that Store Error Codes Etc Z022 to Z024 Z027 to Z029 Stored Error Code Failure Description The interrupt return IRET instruction was not executed or there is no return destination There are more than eight pending interrupts Application error Application error A parameter is invalid Application error Data is invalid Application error There is an error in BIN to BCD conversion Application error There is an error in the pointers of the FIFO table Application error The value defining a ication error boundary between devices has been exceeded The FOR NEXT loop is not consistent ication error The IL ILC loop is not consistent ication error The macro return MRET instruction was not executed or there is no return destination ication error Macro call nesting is ication error deeper than 7 levels The condition of module ication error installation is not consistent with the program The number of special module High speed Read HRD instructions or special module High speed Write HWR instruc
210. low AN CAUTION 1 Index modification of shared or extended shared registers R When applying index modification to a shared or extended shared register R of the own sequence CPU module be careful that the register number which is directly specified in an instruction after adding the value of the index register must not exceed the range specified by configuration for the own CPU Otherwise data held by shared or extended shared registers R of other CPU modules are overwritten and so operation results are not correctly reflected X00501 v1 i MOV R0001 B0001 X00501 T001 A Y00602 i If 10003 Make sure the register number does not exceed the range set for the own CPU 040703 vsD Figure 4 23 Precautions when Using Shared or Extended Shared Registers R 1 of 2 2 Block move and operation of multiple devices When using shared or extended shared registers R in an instruction for transferring or operating data held by multiple devices be careful that the range of registers which is defined by the register number specified directly in the instruction and the number of registers included in the transfer and operation must not exceed the range specified by configuration for the own CPU Otherwise data held by shared or extended shared registers R of other CPU modules are overwritten and so operation results are not correctly reflected X00501 X00504 ae ere
211. may result in damage Do not touch components in the module In some modules you can remove the right side cover and install ROM packs or change switch settings While doing this do not touch any components on the printed circuit board otherwise components may be damaged and modules may fail to work Do not use unused terminals Do not connect wires to unused terminals on a terminal block or in a connector Doing so may adversely affect the functions of the module IM 34MO06P13 01E 4th Edition Jan 31 2012 00 vii E Waste Electrical and Electronic Equipment s Waste Electrical and Electronic Equipment WEEE Directive 2002 96 EC This directive is only valid in the EU This product complies with the WEEE Directive 2002 96 EC marking requirement The following marking indicates that you must not discard this electrical electronic product in domestic household waste Product Category With reference to the equipment types in the WEEE directive Annex 1 this product is classified as a Monitoring and Control instrumentation product Do not dispose in domestic household waste When disposing products in the EU contact your local Yokogawa Europe B V office E How to Discard Batteries The following description on DIRECTIVE 2006 66 EC hereinafter referred to as the EU new directive on batteries is valid only in the European Union Some models of this product contain batteries that cannot be removed by
212. ming Options Item Execution delay Immediate Execution of Input Interrupt Program during Instruction Execution Execution of Input Interrupt Program after the Completion of Instruction Execution Processing time of instruction being executed switching time or synchronization processing time common processing time input refreshing time switching time 4 Switching time only 3 Simultaneity of data 4 2 4 A CAU J Guaranteed on an instruction basis None for multiple devices The indicated time does not include the response time of an input module For details on the response time of input modules see Hardware Manual IM 34M06C11 01E For details on the instruction processing time see the appendix of Sequence CPU Instruction Manual Instructions IM 34MO6P12 03E 120 us for F3SP22 F3SP28 and F3SP38 modules and 100 us for F3SP53 F3SP58 and F3SP59 modules See Section 7 1 Description of Scan Time TION Output of data to relays with input interrupt programs executed immediately during instruction execution Be careful when outputting data to relays using an output instruction e g OUT SET or RST if input interrupt processing is configured with the timing option of Immediate during instruction execution In such cases do not output data in a normal scan program to any of the relays numbered 1 to 16 if data is output to any of t
213. modules 800 0 035 42865 steps Approximately 41 8K steps for F3SP53 F3SP58 and F3SP59 CPU modules IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 64 6 15 4 Functions The following sensor control functions are available Table 6 24 Sensor Control Functions Functions Description Allows the execution interval of the sensor control block to be set by WideField3 or WideField2 Allows the interrupt timing of the sensor control block to be set by WideField3 or WideField2 to either of the following options After instruction Immediate Allows the precedence of sensor control block interrupt and input module interrupt to be set by WideField3 or WideField2 Allows the sensor control block to be activated or inactivated by a dedicated instruction Di Prohibits the sensor control block from being executed or cancels the isable Enable nae f prohibition by a dedicated instruction On for One Scan at Sensor CB A special relay M that remains turned on for one scan when the Execution interval Interrupt timing Priority of interrupts Activate Inactivate Start function sensor control block is activated Execution status ni Start or Stop status of the sensor control block in a special haath rae Stores the processing time of the sensor control block in a special Execution time monitoring register Z E Execution Interval Setting and Accuracy Using the configuration and i
214. modules to be mounted One power supply module must always be mounted on the base module Base module Power supply module At least one CPU module is required Several types are available with different functionalities Various types are available with different types of O and number of I O points CPU module I O module Various types are available including analog I O and communication modules Special module The location where you install a module is called a slot E Main Unit Install the power supply module in the leftmost slot of the base module and the CPU module in the slot on the immediate right of the power supply module Then install required I O and special modules in the remaining slots A system with this configuration is called a main unit CPU module supply module Power k J I O and special modules F010301 VSD Figure 1 1 Main Unit E Subunit A subunit is an I O expansion unit It is connected to the main unit through a fiber optic FA bus fiber optic FA bus type 2 or FA bus type 2 module A maximum of seven subunits can be connected to the main unit and are identified by their unit numbers With fiber optic FA bus type 2 you can separate any single subunit into a maximum of eight stations For more information on the method of
215. mpling trace functions and subsequently view sampling trace results in time chart format from WideField3 as shown in the figure below Trace Results WFSAMPLE Single Trace times 500 1000 1500 2000 2500 3000 3500 4000 FEAF EEEE EAEE PEE ae ee Se ee Customize Display V Bit V fa ja fa 3166 2843 Zoom Range per 26600 699 z times 31848 934 ms Trace No Relative time Cursori Cursor o 495 10 075 41192 010 41181 8935 Width 4095 times se 1000 1500 2000 2500 3000 3500 4000 times 2900 2950 3000 3050 3100 Relay Address BCH1 100001 BCH 100002 BCH3 100003 BCH4 100004 BCHS 100005 BCH 100006 BCH 100007 BCH8 100008 Cursort BSeeeposoo Cursor Omgogsoms so gi Cursor2 2850 2900 2950 3000 3050 times Export Trace Result Past Data Axis 0 Load Past Result 1 ed 3100 Load trace Word Address Bl WCH1 000001 Dec B WCH2 D00002 Dec B WCH3 D00003 Dec E WCH4 D00004 Dec Format Dec Dec Dec Dec Cursor 10023 15654 28133 19923 22937 13594 24013 11683 Figure 6 18 View of Sampling Trace Results WideField3 IM 34M06P13 01E F061007 VSD 4th Edition Jan 31 2012 00 6 25 You can execute sampling trace in either Run or Debug mode Re executing sampling trace erases previ
216. n in order to prevent the process from affecting the scan time This means the peripheral processing time is affected by the program execution time Peripheral processes a ae Common processing i i Shared refreshin Input refreshing H 9 Output Ta j f refreshing T Link refreshing One scan nstruction i Command processing execution Peripheral i Tool service processing oo Hine service Pa service Synchronization processing y F030501 VSD Figure 3 4 Peripheral Processing E Specifying Peripheral Processing Time You can define the peripheral processing time Use this configuration item when the instruction execution time is so short that insufficient time is allocated to peripheral processes To secure enough time the scan time is lengthened or the delays of shared refreshing link refreshing and command processing included in the peripheral processes are shortened If at the end of instruction execution any peripheral process is found to have not run as long as the defined time the process is prolonged until the expiry of the defined time In that case the scan is also prolonged by as much as the extended portion of the defined time Beware that the CPU ignores the defined peripheral processing time if a constant scan time is defined ae core Common processing Input refreshing Output refreshing Instruction yer execution Peripheral Peripheral proces
217. n Indicates the status of a sensor control status OFF Stop block Utility Name Function Description Sensor CB scan ON Error The CPU fails to sustain the execution timeout OFF Normal interval of the sensor control block Item Utility No Name Function Description M3521 to M3774 Node Participation Status Participating _ Not participating M3777 to M4030 Upper Layer Operation Signal Error Error Normal M4033 to M4286 Operation Status Sa Stop Valid Invalid FL net system 1 FL net system 1 FL net system 1 M4289 to M4542 Common Memory Data Valid FL net system 1 M4561 to M4814 Node Participation Status Participating FL net system 27 Not participating M4817 to M5070 Upper Layer Operation Signal Error FL net system 22 Error Normal M5073 to M5326 Operation Status l aa a FL net system 27 M5329 to M5582 Common Memory Data Valid Hee FL net system 27 i If both FL net and FA link are installed FL net systems are allocated smaller system numbers 2 If both FL net and FA ink are installed FL net systems are allocated larger system numbers SEE ALSO For details see FL net OPCN 2 Interface Module IM 34M06H32 02E The following special registers Z have been added to the list of utility registers Utility Description Refers to the length of time from when input refreshing is started for the sensor control block to when the pro
218. n time in 100 us Ea Debug mode Latest scan time increments Minimum sean ume Allows the latest scan time to be read in Z005 Minimum scan time 100 us increments if it is shorter than the Debug mode ae A minimum scan time Maxim im scani time Allows the latest scan time to be read in Z006 Maximum scan time 100 us increments if it is longer than the Debug mode i maximum scan time Stores the latest scan time in100 us Z007 Peripheral process Latest s an tine increments scan time Tolerance Scan time of one control process Allows the latest scan time to be read in sa 100 us increments if it is shorter than the Z008 Miniuni peripheral Minimum scan time minimum scan time process scan time A Tolerance Scan time of one control process Allows the latest scan time to be read in 100 us increments if it is longer than the Z009 Maximum peripheral Maximum scan time maximum scan time process scan time Tolerance Scan time of one control process AN CAUTION Do not write to a special register Z including those not listed in the table above e g Z010 to Z016 unless otherwise stated This is because they are used by the CPU module for the system If you inadvertently write to these registers a failure such as a system shutdown may result You are not allowed to apply index modification to special registers Z in an attempt to specify them as the destination of data output If you do so an instru
219. nd Stopping Blocks in WideField User s Manual Online IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 61 Compatible Modules The sensor control block function can be used with all CPU modules However observe the precautions described below AN CAUTION Precautions when setting Terminal Usage in Input Output Setup Using the configuration function of WideField3 or WideField2 specify whether terminals of I O modules are to be refreshed by the sensor control block or normal scan All devices used in the sensor control block including input relays X and output relays Y are shared with the normal scan When using an input or output module with the sensor control block you must configure the input module on long word basis i e 32 relays 32 terminals terminals 1 to 32 or terminals 33 to 64 and the output module on word basis i e 16 relays or 16 terminals Let s suppose you configured the input module incorrectly on word basis for example you set terminals 1 to 16 to the option Used with normal scan and terminals 17 to 32 to the option Use with SCB Since input refreshing is performed on long word basis input relays X used under a normal scan are refreshed by the Refresh instruction of the sensor control block when the normal scan is in progress Consequently the simultaneity of data is not guaranteed before and after the refreshing Simultaneity of data is also not guaranteed for input rel
220. ne System 3 FA Link Cyclic Transmission Time System 3 FA Link ims increments Local station status O Initialization in progress Offline Online System 4 FA Link Cyclic Transmission Time System 4 FA Link ims increments Local Station Status Initialization in progress Offline Online System 5 FA Link Cyclic Transmission Time System 5 FA Link ims increments Local Station Status Initialization in progress Offline Online System 6 FA Link Cyclic Transmission Time System 6 FA Link ims increments Local Station Status Initialization in progress Offline Online System 7 FA Link Cyclic Transmission Time System 7 FA Link ims increments Local Station Status Initialization in progress Offline Online System 8 FA Link Available with the F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 and F3SP59 only TIP Cyclic Transmission Time Units that make up a system are known as stations System 8 FA Link ims increments IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Appx 2 5 Appendix 2 5 Sequence CPU Module Status Registers CPU module status registers indicate the status of a CPU Table Appendix 2 5 Sequence CPU Module Status Registers CPU Module Status Registers Number of User Log Records Function Description See Section 6 14 User Log Management
221. ned in increments of 16 Default 2048 for each system Configuration Range 16384 max for all systems combined in increments of 16 Link registers W for each system FA link or FL net OPCN 2 system System 1 to 4 2048 System 5 to 8 0 8192 max for all systems combined in increments of 16 2048 for each system IM 34M06P13 01E 16384 max for all systems combined in increments of 16 4th Edition Jan 31 2012 00 4 16 4 3 5 Link Refreshing Range This section describes the link refreshing range for an FA link or FL net OPCN 2 E Setting Link Refreshing Range for an FL net System You can select whether to perform link refreshing on per node basis by configuration You can specify not to read the common area i e refresh links of nodes not involved in data exchange so as to shorten the processing time required for link refreshing By default all nodes are refreshed E Setting Link Refreshing Range for an FA Link System Link refreshing of an FA link module is performed only for link relays L and link registers W that are used by instructions coded in a program Link Relay L If link relays L are directly coded in a program each word containing such a link relay is refreshed If link relays L are specified by index modification each word including the link relay L designated by the index register with index value of 0 is refreshed L00003 L
222. net Relays Table Appendix 1 6 FL net Interface Module Status Relays FL net Interface Module Status Rela M3521 to M3774 M3777 to M4030 M4033 to M4286 M4289 to M4542 M4561 to M4814 M4817 to M5070 M5073 to M5326 M5329 to M5582 Name Node Participation Status Upper Layer Operation Signal Error Operation Status Common Memory Data Valid Node Participation Status Upper Layer Operation Signal Error Operation Status Common Memory Data Valid Function 1 Participating 0 Not participating 1 Error 0 Normal 1 Run 0 Stop 1 Valid 0 Invalid 1 Participating 0 Not participating 1 Error 0 Normal 1 Run 0 Stop 1 Valid 0 Invalid 1 If both FL net and FA link are installed FL net are allocated smaller system numbers 2 If both FL net and FA ink are installed FL net are allocated larger system numbers SEE ALSO For details see FL net OPCN 2 Interface Module IM 34M06H32 02E TIP A system refers to a group of units connected to one FL net Description FL net system 1 FL net system 11 FL net system 1 FL net system 1 FL net system 2 7 FL net system 2 7 FL net system 2 7 FL net system 2 7 IM 34MO6P13 01E 4th Edition Jan 31 2012 00 Blank Page programmable controller or detecting errors Registers Sequence operation status registers indicate the status of sequence operation Appx 2 1 Appendix 2 Special Registers Z
223. ng One scan Instruction execution Command processing lt Tool service Link service CPU service Synchronization processing 4 F031003 VSD Figure 3 21 Executing FA Link Refreshing as a Peripheral Process Link refreshing updates the link relays L registers W of FA link 1 to FA link 8 in each cycle of peripheral processing Link relays registers of Link relays registers of Link relays registers of FA link 1 FA link 2 FA link 3 Results of link refreshing are reflected by this common processing Instruction execution Instruction execution Instruction execution Instruction execution One scan One scan One scan One scan yc DK gt lt Figure 3 22 FA Link Refreshing Sequence XK F031004 VSD TIP Table 3 5 shows an example of how link refreshing affects the scan time For more information see Section 7 1 Description of Scan Time Table 3 5 Durations of Interference by Link Refreshing with the Scan Time Duration of Duration of Interference with Number of Link Devices Interference with Scan Time of Peripheral Scan Time Processing Link relay L 1024 units Link register W 1024 units Link relay L 2048 units Link register W 2048 units Example 1 3 314 ms 16 38 ms Example 2 6 578 ms 32 7 ms IM 34M06P13 01E 4th Edition Jan 31 2012 00 E Execution of FL net Link Refreshing 3 23 You can specify by configuration whether to execute FL net link
224. ng Comments or Tag Name Definitions in CPU 10 1 10 3 New Instructions and Instruction Related Functions 10 2 10 4 Changes in Specifications cccssseeecessseeeeeeseeeeeeeesseeeessseeneeeseeenens 10 3 Appendix 1 Special Relays M ssssssssssseeeeeeeeeeeeeeeeeeees Appx 1 1 Appendix 1 1 Block Start Status RelayS ccccceseseeesseeeeeeeeeees Appx 1 1 Appendix 1 2 Utility Relay S ceisiai iiianoe neinean adanan aasia aaas Appx 1 2 Appendix 1 3 Sequence Operation and Mode Status Relays Appx 1 3 Appendix 1 4 Self diagnosis Status Relays cccccceseseesseeees Appx 1 4 Appendix 1 5 FA Link Module Status Relays cssesseeseeeeeees Appx 1 5 Appendix 1 6 FL net Interface Module Status Relays 2 Appx 1 5 Appendix 2 Special Registers Z ccesssssseeeeeeeeeeeeeeeeeeees Appx 2 1 Appendix 2 1 Sequence Operation Status Registers 006 Appx 2 1 Appendix 2 2 Self diagnosis Status Registers cceseesseeseenee Appx 2 2 Appendix 2 3 Utility Registers 5 ccssascncitestcitecniessanceasscettasenannnnesscntninaans Appx 2 3 Appendix 2 4 FA Link Module Status Registers c cccssseeeeee Appx 2 4 Appendix 2 5 Sequence CPU Module Status Registers Appx 2 5 Appendix 3 Forms for System DeSigQN ccccceeeeeeeeeeeees Appx 3 1 m Program Coding Sheet eeeeeeeeeeeeeeeeeeeeeeeeee
225. ng the FA M3 controller in the following locations Where the instrument will be exposed to direct sunlight or where the operating temperature exceeds the range 0 C to 55 C 32 F to 131 F Where the relative humidity is outside the range 10 to 90 or where sudden temperature changes may occur and cause condensation Where corrosive or flammable gases are present Where the instrument will be exposed to direct mechanical vibration or shock Where the instrument may be exposed to extreme levels of radioactivity Use the correct types of wire for external wiring Use copper wire with temperature ratings greater than 75 C Securely tighten screws Securely tighten module mounting screws and terminal screws to avoid problems such as faulty operation Tighten terminal block screws with the correct tightening torque as given in this manual Securely lock connecting cables Securely lock the connectors of cables and check them thoroughly before turning on the power Interlock with emergency stop circuitry using external relays Equipment incorporating the FA M3 controller must be furnished with emergency stop circuitry that uses external relays This circuitry should be set up to interlock correctly with controller status stop run Ground for low impedance For safety reasons connect the FG grounding terminal to a Japanese Industrial Standards JIS Class D Ground Japanese Industrial
226. nk Page Revision Information Document Name Sequence CPU Instruction Manual Functions for F3SP22 F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S Document No IM 34M06P13 01E Edition Date Revised Item ist Jul 2000 New publication 2nd Oct 2002 Included F3SP59 for OS Incorporated addendum errata 3rd June 2007 Included FL net Incorporated addendum errata Ath Jan 2012 Include F3SP22 0S Included WideField3 Incorporated errata Written by PLC Group International Sales Promotion Dept IA Systems Business Headquarters Yokogawa Electric Corporation Published by Yokogawa Electric Corporation 2 9 32 Nakacho Musashino shi Tokyo 180 8750 JAPAN Printed by Kohoku Publishing amp Printing Inc IM 34M06P13 01E 4th Edition Jan 31 2012 00 Blank Page
227. nput instrument Input refreshing CPU s data memory Input relay X area A j A Execution of operations X00502 ii Y00602 O x00501 X00502 Y90601 Ay tO X00503 10001 Y go603 10002 L0001 Xb0604 10100 jii i Operation CPU s data memory y results External output Output relay Y area instrument Output refreshing F030601 VSD Figure 3 6 Method of I O Processing IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 9 3 6 2 Response Delay The maximum response delay of the output module against a change in the input module is two scans For more information see Chapter 7 I O Response Time Based on Scan Time External input instrument is turned on X00502 Ik Y00602 o Instruction execution Instruction execution EE SENS SIEEN AEE NEEN The change is reflected at this moment of output refreshing The change is acquired at this moment of input refreshing i Response delay of 1 two scans External output instrument turns on F030602 VSD Figure 3 7 Response Delay IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 6 3 3 10 I O Processing in Multi CPU System The sequence CPU module performs refreshing when the configuration item Terminal Usage of Input Output Setup is set to Used or Use with SCB In the configuration define the terminals to be refreshed for each sequ
228. nstruction instruction execution time 0 045 to 0 18us per instruction 0 045 to 0 18us per instruction 0 0175 to 0 07us per instruction 0 045 to 0 18us per instruction 0 0175 to 0 07us per instruction Application instruction 0 18 us per instruction 0 18 us per instruction 0 07 us per instruction 0 18 us per instruction IM 34M06P13 01E 0 07us per instruction 4th Edition Jan 31 2012 00 Table 1 2 Functional Specification F3SPOO OS 2 2 Continued Special module High speed Read HRD Instruction special module High speed Write HWR Instruction Specifications F3SP22 0S F3SP28 3S F3SP53 4S F3SP38 6S F3SP58 6S F3SP59 7S 64 instructions each Sampling trace functions Available These functions collect and display the states of multiple devices for a maximum of 1024 scans Support for personal computer link functions by programming tool connection port Available These functions allow a personal computer or a monitor to be connected to the programming tool connection port to perform communications equivalent to the personal computer link module User log functions Available These functions allow the user to execute a user log command to log record the history of errors in the user system including information on the state of occurrence and system operation etc Number of personal computer link modules 6 max
229. nterrupt setting function of WideField3 or WideField2 set the execution interval of the sensor control block Table 6 25 Execution Interval Setpoints of Sensor Control Block ltem Configuration Range 200 us to 25 0 ms The setting range from 200us to 900us is only valid for the interrupt timing option of Immediate Unit of setpoint 100 us The accuracy of an execution interval is 100 ppm E Interrupt Timing Using the configuration and interrupt setting function of WideField3 or WideField2 set the timing for sensor control block interrupts during program execution Two interrupt timing options are available Table 6 26 Sensor Control Block Interrupt Timing The CPU switches to the sensor control block after the completion of instruction After instruction execution It does not however switch to the sensor control block during common processing or refreshing The CPU switches to the sensor control block during ladder instruction execution It also switches to the sensor control block during common processing or refreshing Immediate default IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 65 Program execution in normal scan LD Sensor control block OUT LD BMOV Input refreshing Program execution Output refreshing F061503 VSD Figure 6 43 Interrupt by Sensor Control Block after Instruction Execution Program execution in normal scan
230. ntrol process Maximum Peripheral process Scan Time A CAUTION Maximum scan time Allows the latest scan time to be read in 100 us increments if it is longer than the maximum scan time Tolerance Scan time of one control process Do not write to a special register Z including those not listed in the table above e g Z010 to Z016 unless otherwise stated This is because they are used by the sequence CPU module for the system If you inadvertently write to these registers a failure such as a system shutdown may result You are not allowed to apply index modification to special registers Z in an attempt to specify them as the destination of data output If you do so an instruction processing error will result In a ladder instruction for continuous data transfer or table format data output see examples below you are not allowed to specify a special register Z as the output destination If you do so an instruction processing error will result Instructions for continuous data transfer Block Move instruction BMOV instruction Block Set instruction BSET instruction String Move instruction SMOV instruction etc Instructions for table format data output User Log Read instruction ULOGR instruction FIFO Write instruction FIFWR instruction etc IM 34M06P13 01E 4th Edition Jan 31 2012 00 Appx 2 2 Appendix 2 2 Self diagnosis Status Registers Self diagnosis status registers indic
231. o Instructions Accumulation of Know how Know how can be accumulated in the form of macro instructions for creation of customized FA M3 controllers IM 34MO06P13 01E 4th Edition Jan 31 2012 00 E Types of Macro Instructions 6 45 There are three types of macro instructions the availability of which depends on CPU types as follows Table 6 14 Macro Instructions and their Availability by CPU Type F3SP22 0S F3SP28 3N F3SP28 3S Macro Instruction Type F3SP38 6N F3SP38 6S yP F3SP53 4H F3SP53 4S F3SP58 6H F3SP58 6S F3SP59 7S Macro Call MCALL Available Available Input Macro Instruction Call NCALL Not available Available Structure Macro Instruction Call SCALL Not available Available Macro Call Up to 16 parameters can be passed via a Macro Call instruction Input Macro Instruction Call The Input Macro Instruction Call instruction can be used as an input condition just like the Load or Compare instruction It can be used to represent complex or reusable input conditions in a single instruction Using an Output of Input Macro NMOUT instruction in an Input Macro Instruction call allows you to output the result of logical operations to the next instruction Converting gt into a Macro instruction N INLET1 Increased reusability and readability Figure 6 36 Benefits of Input Macro Instruction C
232. o options whether there is simultaneity with the data of shared devices The No option of this configuration item is designed for the interchangeability of the F3SP21 F3SP25 and F3SP35 modules Select this option when replacing these modules with the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 or F3SP59 modules A CAUTION If your sequence CPU is F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 or F3SP59 set the CPU s output relays Y to be refreshed to the option Unused by a direct Refresh DREF instruction in a program If you set them to the option Used or Used in CB sensor control block the values one scan earlier may be overwritten with the values output by the DREF instruction because of the timing of output refreshing that is executed concurrently with the instruction IM 34MO06P13 01E 4th Edition Jan 31 2012 00 9 4 9 3 Special Relays M and Special Registers Z The following special relays M have been added to the list of utility relays Utility Function Description Generates a clock pulse with a 1 ms period Sons elack Wis ims Generates a clock pulse with a 2 ms S period On for one Turns on for one scan when the sensor scan at Sensor ON ne er ene control block starts at the first execution of CB start OFF Im allother cases the sensor control block 1 ms clock 0 5ms 0 5ms Utility Name Function Description Sensor CB execution ON Ru
233. ocessing error processing error OFF No error is found is stored in special registers Z22 to Z24 ON Error Indicates that the state of module M202 1 O comparison error OFF Normal installation is not consistent with the program Indicates that no access is possible to I O M203 VO module error ON Error modules The slot number of the error OFF Normal module is stored in special registers Z33 to Z40 ON Error Indicates that scan time has exceeded M204 Scan timeout fe oes OFF Normal the scan monitoring time Subunit ON Error M210 ae OFF Unspecified or normal An error has been detected in the fiber communication error line optic FA bus module The slot number of Subunit transmitter ON Error the error module is stored in special M211 switching has OFF Unspecified or normal registers Z89 to Z96 occurred line M212 SensorCB scan ON Error sensor OLK anabe timeout OFF Normal Sou maintained M225 CPU1 sequence ON Run Indicates whether sequence program of program execution OFF Stop CPU in slot 1 is running M226 CPU2 sequence ON Run Indicates whether sequence program of program execution OFF Stop CPU in slot 2 is running M227 CPU3 sequence ON Run Indicates whether sequence program of program execution OFF Stop CPU in slot 3 is running M228 CPU4 sequence ON Run Indicates whether sequence program of program execution OFF Stop CPU in slot 4 is running SEE ALSO For details on the M210 Subun
234. ock either runs or stops depending on the Error time Action defined The block stops if the error is not configurable TIP If an error is encountered in the sensor control block the error block number stored in a special register Z is the last block number of a normal scan program plus one Table 6 38 Action of Sensor Control Block when an Error Is Detected in Normal Scan Type of Error For errors configurable with Operation Control of configuration the All types of error sensor control block either runs or stops depending on the Error time Action defined The block stops if the error is not configurable IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 71 6 15 7 Programming Precautions E Instructions Not Applicable to Sensor Control Block Instruction Corrective Actions Enable disable timers in a regular block Timer TIM instruction Reading timer relays in a sensor control block is allowed however Special module High speed F s TORN Read HRD Use the special module Read READ instruction instead eS High speed Use the special module Write WRITE instruction instead E Precautions when the Interrupt Timing Is Immediate Precautions when outputting data to relays If you have already output data to any of the relays numbered 1 to 16 using an OUT SET RST DIFU or DIFD instruction in the sensor control block do not also output data to any of these relays in a normal scan program
235. odule status registers Z see the Special relays M registers Z sections Cyclic transmission time System 8 FA Link ims increments in FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 39 4 8 5 Sequence CPU Module Status Registers CPU module status registers indicate the status of a CPU Table 4 18 Sequence CPU Module Status Registers CPU Module Status Registers Contents Description See Section 6 14 User 7105 Number of user log Log Management records Functions for information on user logs Refers to the length of time from when input refreshing is started Sensor CB for the sensor control block to Z109 ea when the program is executed execution time noes and output refreshing is completed Unit 10 us Refers to the maximum time Z111 Maximum Sensor taken to execute the sensor CB execution time control block Unit 10 us Z121 to Module informati n Module name and firmware Z128 revision number Note For example the values for module F3SP58 69 firmware Rev1 are as follows Z121 F3 Z122 SP Z123 58 Z124 6S Z125 R Z126 01 Z127 Z128 i IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 9 4 40 Index Registers V Index registers are used to modify devices numbers You can use these registers in both basic instructions and application instruc
236. ograms F3SP53 4H F3SP38 6N F3SP58 6H I O method Refresh method Direct I O instruction Programming language Structured ladder language and mnemonic language Number of I O points 4096 max 8192 max including remote I O points Number of internal relays I 16384 16384 32768 32768 Number of shared relays E 2048 2048 2048 2048 Number of extended shared relays E 2048 2048 2048 2048 Number of link relays L 8192 8192 16384 16384 Number of special relays M 9984 9984 9984 9984 Number of timers T Number of counters C 2048 in total 2048 in total 3072 in total 3072 in total Number of data registers D 16384 16384 32768 32768 Number of shared registers R 1024 1024 1024 1024 Number of extended shared registers R 3072 3072 3072 3072 Number of file registers B 32768 32768 262144 262144 Number of link registers W 8192 8192 16384 16384 Number of special registers Z 1024 1024 1024 1024 Number of labels 1024 1024 1024 1024 Number of input interrupt processing routines 4 4 4 4 Decimal constant 16 bit instruction 32 bit instruction 32768 to 32767 2147483648 to 2147483647 Hexadecimal constant Constants 16 bit instruction 32 bit instruction
237. oint of a counter as CSnnnn Only available with the F3SP22 F3SP25 F3SP28 F3SP35 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPU modules The countdown type of timers and counters has been made available with the FA M3 controller for such reasons as viewing them on a higher level computer Current value of count up type timer counter Setpoint Current value of countdown type timer counter The timer setpoint TSnnnn and counter setpoint CSnnnn are not available for a word writing command In the case of F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 and F3SP59 sequence CPU modules writing to this device is not possible with any of BWR BFL WWR and WFL commands Alternatively use a BRW or WRW command IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 41 E Precautions for Communications You should include timeout handling on the higher level computer to handle situations where a response is not returned due to say an incorrect station number specified in the command If the personal computer link functions are used to download a program then you should not load another program from another source personal computer link module Ethernet interface module etc at the same time Otherwise normal operation is not guaranteed When writing to a shared device the value may be immediately overwritten if another sequence CPU module is using the same device If a power failure occurs when a monitor command is in use it
238. on 4 F061602 VSD Figure 6 48 Partial Download Functions Used by Multiple Programmers A CAUTION Ifan error occurs at the time of partial downloading the step count of the error block becomes 0 If you then upload this defective program to a personal computer the step count for the corresponding block on the personal computer will also be O If you have to upload such a program save it under a different project name At the completion of partial downloading program checking and optimization are performed and this may take some time IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 17 6 17 1 6 74 Functions for Storing Comments to CPU F3SPO0 Os You can store circuit comments and subcomments to the CPU module Storing comments in the CPU module allows you to display them during circuit monitoring even if there is no project TIP These functions can only store circuit comments and subcomments To store I O comments use the functions for storing tag name definitions to CPU Performing Setup to Download Comments You can select whether to store download circuit comments and subcomments to a CPU module but you cannot select to download only circuit comments or only subcomments In WideField3 or WideField2 setup for downloading comments has to be performed in two places in the local device properties and when you execute the download function Firstly turn on the checkbox Store Circui
239. on Manual Instructions IM 34MO6P12 03E Changes in Specifications Table 10 2 List of Changes in Specifications CPU Types F3SP28 3N F3SP38 6N F3SP53 4H F3SP58 6H 10K steps Number of steps per block F3SP28 3S F3SP38 6S F3SP53 4S F3SP58 6S F3SP59 7S 56K steps Number of macro instructions 64 256 Number of circuits subcomments 30000 per block 3000 per program Number of timer steps 2 4 Compatible ROM pack RK33 RK73 1 RK93 is not compatible with the F3SP28 3S and F3SP53 4S RK33 RK73 RK93 7 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Blank Page Appx 1 FA M3 Sequence CPU Instruction Manual Functions for F3SP22 0S F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S IM 34M06P13 01E 4th Edition These appendices provide lists of special devices as well as formats of documentation which can be used when designing your system These formatted sheets can be conveniently copied for use as standard forms in your system design Four forms are provided as shown below Contents Appendix 1 Special Relays M ccccccsssccesscecececeseeseseeeeeeeeeeeeeeeeees Appx 1 1 Appendix 2 Special Registers Z ccccccccceeesseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaee Appx 2 1 Appendix 3 Forms for system Design seeceeeeeeeeeeeeeeeeeeeeeeeeeeee Appx 3 1 E Program Coding Sheet ccccccccecscsscsecsessesecseeseseeses
240. on Status Special Relay M M137 Sensor CB Execution ON Run Indicates the operating status of the sensor Status OFF Stop control block TIP The status of the sensor control block is updated when an Activate Sensor Control Block CBACT instruction is executed or during normal scan input refreshing after error detection when an Inactivate Sensor Control Block CBINA instruction is executed IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 69 E Execution Time Monitoring This function stores in a special register Z the time taken from when input refreshing for the sensor control block is started followed by program execution to when output refreshing is completed The time indicates the actual execution time of the sensor control block during the preset execution interval Sensor control block Input refreshing Execution Program execution Execution time interval Output refreshing Wait time before the next fixed interval scan Input refreshing Program execution Output refreshing F061505 VSD Figure 6 45 Schematic Diagram Showing Execution Time of Sensor Control Block Table 6 33 Special Registers Z for Execution Time of Sensor Control Block a Indicates the time taken from starting of input refreshing for the Sensor CB Execution Time sensor control block through program execution to completion of output refreshing Maximum Sensor CB Indicates the maximum time taken to exe
241. on in a block In the case where specified blocks are selected for execution a subroutine program which is called from a block being executed will be executed even if it is located in a block which is not selected for execution Subroutine program calls can be nested up to eight levels deep To nest a call is to call a subroutine from within another subroutine A Program l Program i execution i execution Block 1 ae 2 Ye i i A i i Block n 1 E ENT AE EE i l A l i E To Block n H i OW S eae en dete NN Subroutine program rasospaven Figure 5 7 How a Subroutine Program Is Executed IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 7 E Interrupt Programs An interrupt program is executed when any cause of interrupt occurs A maximum of four interrupt programs can be included in a program The relationship between a cause of interrupt and an interrupt program is described as a parameter of the Interrupt INTP Instruction INTP X00301 F050206 VSD Figure 5 8 INTP Instruction F Program Program i execution execution Bisck 1 Input interrupt fo pee gt y a Block n 1 l 2 LER EEEIEE E eee EEEE i A i y Block n i i en eT lt lt Input interrupt program F050207 VSD Figure 5 9 How an Interrupt Program Is Executed IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 8 E Sensor Control Block
242. ous data If you perform sampling trace setup using the configuration function the CPU begins sampling immediately after power on If you perform sampling trace setup using the configuration function and then permanently store the setup to ROM the CPU reverts to the ROM setup after a power on and off sequence even if you have redefined the settings using the programming tool SEE ALSO For details on how to configure the sampling trace functions see FA M3 Programming Tool WideField3 IM 34M06Q16 OE or FA M3 Programming Tool WideField2 IM 34M06Q15 01E How sampling is carried out is explained below TRC Instruction Sampling In TRC instruction sampling the CPU samples the states and data of specified contacts whenever the Sampling Trace TRC instruction is executed By executing the TRC instruction in a program you can perform sampling at any point within a scan The CPU collects data when the input condition relay of the Sampling Trace TRC instruction is set to ON The CPU stores results of up to four cycles of sampling if the TRC instruction is executed multiple times within the same scan Any fifth or subsequent Sampling Trace TRC instruction executions within a scan are ignored Sampling trace results are stored at the end of a scan END TRC END TRC TRC END TRC END l l I I I l l l I Sampling Sampling Sampling Sampling F061002 VSD Figure 6 19 Sampling when the Sampling Trace TRC Instruction is Executed
243. pe of command Link service Processes commands input from a personal computer link module Executes one command per service Varies with the type of command CPU service Processes commands input from another CPU module Executes one command per service Varies with the type of command IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 2 Setting Scan Monitoring Time This configuration item sets the scan monitoring time You can set the time to any value from 10 ms to 200 ms in 10 ms increments By default the time is set at 200 ms 7 3 Examples of Scan Time Calculation When the CPU is F3SP22 F3SP28 or F3SP38 Module configuration User program Four 32 point input modules Four 32 point output modules 5K steps 5K steps for the ladder program below consisting of instructions only where the average execution time of these instructions is assumed to be 0 09 us ONC TWN ONTHAWT 32 point input 32 point output modules modules F070301 VSD Figure 7 1 Module Configuration of F3SP22 F3SP28 or F3SP38 Sequence CPU 10064 10001 10002 10065 10066 m Sa ae F070301_2 VSD Figure 7 2 Program for F3SP22 F3SP28 or F3SP38 Table 7 3 Scan Time of F3SP22 F3SP28 or F3SP38 Sequence CPU Common processing Calculation Fixed 0 2ms Processing Time Program execution 0 09us x 5120 461 us Output refreshing
244. processing Performs peripheral processes Minimum peripheral processing time 0 2 ms if not configured or sum of program execution time output refreshing time whichever is greater Relationship between Types of I O Module and Number of Modules Calculated on a 16 points Basis Type of I O Module 4 point I O module Number of Modules Calculated on a 16 device Basis 8 point I O module 14 point I O relay 16 point I O relay 32 point I O relay 64 point I O relay IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 3 Shared refreshing System of Peripheral Processes The latest maximum and minimum of scan times taken by the system of peripheral processes are stored in special registers Z007 to Z009 in that order Table 7 2 Scan Time of System of Peripheral Processes Processing Task Updates the contents of shared extended shared relays E and shared extended shared registers R when add on CPU module s is installed and shared refreshing is configured as a peripheral process In a single refreshing cycle this task updates the contents of shared extended shared relays E and shared extended shared registers R included in the configuration setting for each CPU Processing Time When an add on CPU module is installed and shared refreshing is set as a peripheral process 0 003 x number of shared relays set in CPU for refreshing 32 number of shared registers set
245. ps 120K steps F3SP38 6S RK33 0N 56K steps 56K steps F3SP58 6S RK73 0N 120K steps 120K steps RK93 0N 120K steps 360K steps CPU memory 254K steps 360K steps RK33 0N 56K steps 56K steps 120K steps 120K steps 254K steps 360K steps CPU Module Where to Store Program Only F3SP59 7S For the step count of tag name definitions check the project properties the block tag name definition properties for each block or the macro tag name definition properties for each macro instruction You can separately specify whether to download common block and macro tag name definitions using the project properties the local device properties for each block or the local device properties for each macro instruction In addition at the time you execute the download program function you can choose to disable the downloading of tag name definitions regardless of the properties setup If you specify not to download tag name definitions when you execute the download program function any tag name definitions previously downloaded will be erased after the download If you edit tag name definitions online the tag name definition files on the personal computer will be updated but not those in the program memory of the CPU module If changes are made to the tag name definitions download them to the CPU module again TIP For programming efficiency we recommend that you maintain the tag name definition
246. ps per block for F3SP22 0S and 30K steps per block for F3SP28 3S A CAUTION An individual block cannot be executed by the CPU Block 1 Circuit X00503 X00504 Y00602 I H O X00501 X00502 Y00601 X00503 Block n 10001 Y00602 A LJ X00501 X00502 10003 N 1 Q F050201 VSD Figure 5 3 Blocks IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 3 E Executable Program An executable program refers to a program which is stored in a format that allows it to be executed by the CPU An executable program is composed by combining multiple blocks created using WideField3 or WideField2 Each executable program can contain a maximum of 1024 blocks You can either execute all or selected blocks of an executable program This simplifies program management Block 1 Circuit 1 X00503 X00504 Y00602 Executable j Lo program X00501 Y00601 A Block 1 O X00503 Block 2 Block 16 10001 Y00602 O X00501 X00502 10003 0 ss Block 16 Bloc F050202 VSD Figure 5 4 Example of an Executable Program IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 4 5 2 2 Component Programs of an Executable Program An executable program contains a maximum of 1024 blocks The sensor control block is regarded as a single separate block Programs that compose an executable program are classified into main routine programs sub
247. put relays Y of the output module as Not used on 16 point basis In addition all output relays within the same module must be configured with the same output mode hold or reset in the event that sequence processing stops Other Combinations of CPU Modules You may not use the same output module with multiple CPUs Configure all CPUs that do not use the output module so that the output module is set to Not Used SEE ALSO For details on modules that are not used see Section 4 1 4 IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 3 Extended System Configuration An extended system configuration refers to a system configured by adding remote I O modules a personal computer link module an FA link module and an FL net module to the basic system 2 3 1 Remote I O System The remote I O system refers to a system configured using fiber optic FA bus fiber optic FA bus type 2 and FA bus type 2 modules The number of remote I O points is included in the count of all I O points Fiber optic FA bus type 2 module Main unit Fiber optic cable Fiber optic FA bus type 2 module Subunit Fiber optic cable 100 m long F020302 VSD Figure 2 3 Example of System Using Fiber optic FA bus Type 2 Modules IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 3 2 2 3 3 2 5 Personal Computer Link System The personal computer link sy
248. r in a special module High speed Read HDR Instruction or a special module High speed Write HWR Instruction used in the program and that of the installed I O module Check if the instruction parameter in question is consistent with the installed 1 0 module Check if the subunit is turned off Check if there is any problem with the cable of the fiber optic FA bus module Do not reset the CPU modules individually Rather reset them all at once from the main CPU The I O module may be defective Replace it Check if the iteration counter values of the FOR NEXT loop are correct Check for the presence of an endless loop caused by JMP instructions Adjust the scan monitoring time according to the execution time of the application program Check if the subunit is turned off Check if there is any problem with the cable of the fiber optic FA bus module The fiber optic FA bus module may be defective Replace it In the case of interruption by the sensor control block after completion of instruction execution set the execution interval at 1 ms or longer preferably at the largest possible value Check the number of input output words in the sensor control block and the block s execution time and minimize both values Check and minimize any code section between CBD and CBE instructions during which execution of the sensor control block is disabled If this failure mode occurs too frequently check the
249. ram the displayed step count includes only the step count of the program IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 76 6 17 3 Online Editing of Comments If circuit comments subcomments are stored in a CPU module you can edit or delete them online but you cannot add new comments online AN CAUTION If you have added circuit comments or subcomments using offline program editing you should download the circuit comments and subcomments to the CPU module again IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 18 6 77 Functions for Storing Tag Name Definitions to CPU These functions store common block and macro tag name definitions along with a program to either the program memory of a sequence CPU module or the ROM pack If tag name definitions are to be stored in the program memory of a sequence CPU module the sum of the program and tag name definition step counts must be within the capacity of the program If tag name definitions are to be stored in the ROM pack the sum of the program and tag name definition step counts must be within the capacity of the ROM pack Table 6 39 Program Capacity for Storing Tag Name Definitions Program plus Tag Name Definitions CPU memory 10K steps F3SP22 0S RK33 0N 10K steps 56K steps RK73 0N 120K steps CPU memory 30K steps F3SP28 3S RK33 0N 30K steps 56K steps RK73 0N 120K steps CPU memory 56K steps F3SP53 4S RK33 0N 56K steps 56K steps RK73 0N 120K steps CPU memory 120K ste
250. ration procedure E Communication Procedure How to communicate with the FA M3 using a BASIC program on a personal computer is briefly described below For details on the statements and functions to be used in the program refer to the BASIC reference manual that is shipped with your personal computer 1 Open the RS 232 C communication file by entering a command using the following syntax OPEN COM OOOOO AS A OOOOO Enter communication parameters such as the parity data length and the number of stop bits A File number This number is used for subsequent input to and output from the file 2 Send a command to the FA M3 using the following syntax PRINT A String variable name or string 3 To receive a response from the FA M3 enter a command using the following syntax LINE INPUT A String variable name INPUT A String variable name IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 33 E Overview of Communication Communication control performed by the CPU module is based on the processing of commands and responses using a dedicated protocol At first the higher level computer or monitor has the transmission right When the computer sends a command the transmission right transfers to the CPU module The CPU module then sends a response to the higher level computer If the configuration item Use personal computer link function is enabled the CPU module does not send any command to the higher level
251. ration signal error 1 Error FL net system 2 7 0 Normal M5073 to M5326 Operation status ae FL net system 2 7 M5329 to M5582 Common memory data valid S T FL net system 2 7 i If both FL net and FA link are installed FL net are allocated smaller system numbers among the installed modules 2 If both FL net and FA link are installed FL net are allocated larger system numbers among the installed modules SEE ALSO For more details see FL net OPCN 2 Interface Module IM 34M06H32 02E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 5 4 5 1 4 23 Timers T There are five types of timer T 100 us 1 ms 10 ms and 100 ms timers and a 100 ms continuous timer For each type of timer T you can assign the number of timers using the configuration function However you can only assign a maximum of 16 100 us timers AY CAUTION Do not use a timer instruction in the sensor control block or an interrupt program The timer used will not operate correctly 100 us 1 ms 10 ms and 100 ms Timers 100 us 1 ms 10 ms and 100 ms timers are synchronized scan decremental timers T which update their current values and turn on off their time out relays using an end of scan process Setpoints 100 us timer 0 0001 to 3 2767 s 1 ms timer 0 001 to 32 767 s 10 ms timer 0 01 to 327 67 s 100 ms timer 0 1 to 3276 7 s Each timer starts counting at the rising edge of the timer input and expires when the current value reaches 0
252. re stored in the link register with the number specified in the instruction and the high order 16 bits are stored in the link register W with that number incremented by 1 Data exchange between the local station and remote stations can be achieved by writing data to link registers W of the local station and reading it from a remote station Before using link registers configure the range of links for the local station and remote stations Station 1 X00502 MOV 100 woo001 X00501 X00502 Y00601 Station n H X00503 X00504 J W D0001 X00501 T001 Y00602 ia O X00503 F040302 VSD Figure 4 10 Link Registers W The register number is coded as Wmnnnn where m System number 1 0 to 7 nnnn Link register number Table 4 3 Range of Link Register Number Configuration Module Range FA Link H module High speed configuration 1 to 1024 Fiber optic FA Link H module Normal configuration 1 to 2048 FL net OPCN 2 Interface module 1 to 8192 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 14 4 3 3 System Numbers Modules in FA link and FL net OPCN 2 systems are are automatically assigned system numbers based on their slot positions with the module having the smallest slot number named as system 1 If FA link modules and FL net OPCN 2 modules are intermixed the modules are assigned system numbers sequentially reg
253. refreshing l Input X00502 One scan errr EE gt i Output Y00602 F070401 VSD Figure 7 5 Minimum I O Response Time Calculation of the maximum I O response time Input response time 16 ms Output response time 1 ms Scan time 2 ms Maximum I O response time Input response time Scan time x 2 Output response time 16 ms 2 x 2 ms 1 ms 21 ms X00502 Y00602 gt IT Input refreshing Instruction execution Instruction execution A A i 1 l Output i l refreshing Input f I X00502 One scan i I o A gt Mme gt Y O Output Y00602 neiscan F070402 VSD Figure 7 6 Maximum I O Response Time TIP The I O response time refers to the total time taken to receive signal input from external input equipment execute instructions and turn on external output equipment Input response time refers to the time taken to load external input tag name using the input refreshing process Output response time refers to the time taken to reflect the result of instruction execution in external output equipment using the output refreshing process IM 34MO06P13 01E 4th Edition Jan 31 2012 00 7 7 7 5 Instruction Execution Time SEE ALSO For details on the execution time of each instruction see Appendix 3 List of Ladder Sequence Instruction of Sequence CPU Instruction Manual Instructions IM 34MO06P
254. responsibility to include in the system additional equipment and devices that ensure personnel safety Do not attempt to modify the product E Exemption from Responsibility Yokogawa Electric Corporation hereinafter simply referred to as Yokogawa Electric makes no warranties regarding the product except those stated in the WARRANTY that is provided separately Yokogawa Electric assumes no liability to any party for any loss or damage direct or indirect caused by the use or any unpredictable defect of the product IM 34MO06P13 01E 4th Edition Jan 31 2012 00 E Software Supplied by the Company Yokogawa Electric makes no other warranties expressed or implied except as provided in its warranty clause for software supplied by the company Use the software with one computer only You must purchase another copy of the software for use with each additional computer Copying the software for any purposes other than backup is strictly prohibited Store the original media that contain the software in a safe place Reverse engineering such as decompiling of the software is strictly prohibited Under absolutely no circumstances may the software supplied by Yokogawa Electric be transferred exchanged or sublet or leased in part or as a whole for use by any third party without prior permission by Yokogawa Electric IM 34MO06P13 01E 4th Edition Jan 31 2012 00 E General Requirements for Using the FA M3 Controller Avoid installi
255. rform communications equivalent to the personal computer link module ation etc able These functions allow the user to execute a user log instruction to log record the history rrors in the user system including information on the state of occurrence and system Number of personal computer link modules 6 max Available These functions allow a user to create and register new user defined instructions Scan monitoring time Variable from 10 to 200 ms Macro instruction functions Startup at power on or recovery from power failure Sensor control functions Link function Other functions Automatic Auto logging of power on time power off time and momentary power failure time Available In addition to normal scanning these functions allow one specific block to be scanned at high speed fixed intervals FA link FL net personal computer link and remote I O link fiber optic FA bus u bus Online editing Forced SET RESET instructions Clock year month day hour minute second and day of the week Configuration setup of parameters including device capacities range of devices to be latched at power failure and external outputs to be latched when sequence stops Protection IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 2 2 Device List Table 1 4 Device List 1 6 F3SP22 0S F3SP38 6N
256. rocessing of the normal scan 6 15 3 Specifications and Restrictions E Specifications Table 6 22 Specifications of Sensor Control Block Item Specifications Number of sensor control blocks 7 Execution interval 200 us to 25 0 ms in 100 us increments Compatible modules All types of modules Unit of O refreshed devices Per word basis i e in units of 16 relays or terminals Maximum number of 1 O refreshed words 4 to 512 Applicable instructions All instructions except for the Timer special module High speed Read HRD and special module High speed Write HWR instructions Applicable devices All device types Maximum program execution time 50 us to 24 95 ms Initial condition at normal program execution Sensor control block at a stop Interrupt timing Configurable as After instruction execution or Immediate during instruction execution The default is Immediate Priority of interrupts Selectable from Sensor CB interrupt has priority default or Input interrupt has priority Other functions I 2 3 Start or stop by means of instruction or tool or interrupt prohibition or prohibition cancellation by means of instruction See CAUTION in E Compatible Modules For details on writing to devices also used in normal scan see Section 6 15 7 Programming Precautions For start or stop by means of tools see Starting a
257. routine error Z017 to Z019 Z022 to Z024 A failure has occurred during CPU initialization Hardware failure Restrictions on module installation may have been violated Check the modules according to Section A1 2 Restrictions on Module Installation of the Hardware Manual IM 34M06C11 01E Check the installation environment for possible problems such as noise sources If the failure recurs replace the module The CPU for sequence computing has failed Hardware failure Check the installation environment for possible problems such as noise sources If the failure recurs replace the module A program checksum error has occurred Transient memory failure or hardware failure See CAUTION at the end of these tables for information on how to discriminate between these failures The error may be due to a transient memory failure caused by effects of noise Check the installation environment Clear the memory by referring to CAUTION at the end of these tables and download the program again If the failure recurs replace the module Inadvertent writing has been done to the M129 to M131 special relays for Run Debug and Stop mode flags Application error Check if there is any error in the values of index registers or in the parameters defining the number of devices in an instruction which writes to multiple devices such as a Block Move BMOV instruction
258. routine programs interrupt programs and sensor control block programs according to their functions Say GRY G Main routine program i i Block 1 Subroutine program Main routine program l H Block 2 i I 1 Subroutine program f i l Executable program a i Main routine program H Block n i Subroutine program H H Input interrupt program Sensor control block A H program Sensor control block y Y Figure 5 5 Component Programs of an Executable Program IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 5 E Main Routine Program A main routine program is always executed in each scan The main routine program is written using structured ladder language and is composed of multiple blocks You can execute a main routine program by either executing all blocks of the program or executing only specified blocks gt Sa 7 Program execution Block1 y y i SUB i RET Pi Me sta te Se Te ec H This subroutine ee a program is A excluded from the execution Block n 1 F050204 VSD Figure 5 6 How a Main Routine Program Is Executed IM 34M06P13 01E 4th Edition Jan 31 2012 00 5 6 E Subroutine Program A subroutine program is executed when a main routine program executes a CALL instruction Use a subroutine program when you want to run a specific process two or more times within one scan A subroutine program can be placed in any locati
259. rpton CBD Instruction Disables execution of the sensor control block CBE Instruction Enables execution of the sensor control block SEE ALSO For details on individual instructions see Sequence CPU Instruction Manual Instructions IM 34M06P12 03E VON CAUTION If the interval of execution disable is too long for the CPU to be able to execute the sensor control block at fixed intervals a sensor CB scan timeout error will result Consequently the CPU stops executing the sensor control block See subsection 6 15 6 Error Handling for more information E On for one scan at Sensor CB start Function This function causes a special relay M to remain turned on for one scan during the first execution of the sensor control block when the sensor control block is activated Table 6 31 Special Relay M which Turns ON for One Scan at Sensor Control Block Startup Description Turns on for one scan when the sensor On for One Scan at ON At block start i M097 Sensor CB Start OFF In all other cases control block starts at the first execution of the sensor control block TIP The On for one scan at Sensor CB start relay turns on when an Activate Sensor Control Block CBACT instruction is executed It then turns off at the end of the first execution of the sensor control block E Execution Status The CPU stores in a special relay M the execution status of the sensor control block Table 6 32 Sensor CB Executi
260. ructure macro instruction entity you can read from and write to structure data passed as parameters using basic or application instructions and referring to structure members using the lt structure pointer register number gt lt structure member name gt syntax Word processing long word processing and automatic BIN to BCD or BCD to BIN conversion can be used with structure pointer registers but index modification is not allowed High speed processing of application instructions is not performed however More specifically within a structure macro instruction entity high speed processing is not performed for MOV CAL CMP or logical operation instructions with structure pointer registers Q specified as parameters TIP When an instruction using a structure pointer register Q is to be executed repeatedly you can first transfer the member data to macro relays H and macro registers A and then rewrite the instruction to use these relays and registers instead In this way you can shorten the execution time SEE ALSO For details on basic and application instructions see Sections 2 1 and 3 1 of the Sequence CPU Instruction Manual Instructions IM 34M06P12 03E SEE ALSO For details on structures see FA M3 Programming Tool WideField3 IM 34M06Q16 O0E or FA M3 Programming Tool WideField2 IM 34M06Q15 01E IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 50 6 13 4 Nesting Macro Instructions Nesting m
261. s on clock setup see the specifications of special registers Z49 to Z54 for clock data 4th Edition Jan 31 2012 00 4 21 4 4 4 Self diagnosis Status Relays Self diagnosis status relays indicate the results of self diagnosis by the sequence CPU Table 4 8 Self diagnosis Status Relays Self diagnosis Status Relays Function Description ON Error Result of self diagnosis is stored in M193 Selfdiagnosis erfor OFF No error special registers Z17 to Z19 ON Error gt F M194 Battery error OFF Normal Indicates a failure in backup batteries ON Momentary power Momentary power failure Indicates that a momentary power failure M195 failure OFF No momentary power has occurred failure i Indicates that a communication failure M196 Inter CPU A ON Error has occurred in shared relays E or communication error OFF Normal shared registers R M197 Existence of CPU1 ON Exists Indicates whether or not a CPU exists in OFF Does not exist slot 1 M198 Existence of CPU2 ON Exists i Indicates whether or not a CPU exists in OFF Does not exist slot 2 M199 Existence of CPU3 ON Exists Indicates whether or not a CPU exists in OFF Does not exist slot 3 M200 Existence of CPU4 ON Exists Indicates whether or not a CPU exists in OFF Does not exist slot 4 M201 Instruction ON An error is found Information of instruction pr
262. s on the functions of BASIC CPU modules see BASIC CPU Modules and YM BASIC FA Programming Language IM 34M06Q22 01E IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 30 The following figure shows an example of how shared or extended shared registers R are shared if you allocate shared registers R0001 to R0256 for CPU 1 and shared registers R0257 to R0512 for CPU 2 CPU1 X00502 1 MOV 100 R0001 X00501 X00502 Z Y00601 Ik II O CPU2 i X00503 X00504 y AF MOV R0001 D0001 X00501 T001 Y00702 1 O X00503 F040702 VSD Figure 4 22 Shared Register R Using the configuration function you can define the data latch range at power failure for devices whose operation results are to be latched when power is turned off By default all shared registers R are non latched A non latched device will be cleared to OFF 0 when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Devices command from WideField3 or WideField2 A latched device retains its operation result even after power off and power on and is cleared to OFF 0 when you execute a Clear Devices command from WideField3 or WideField2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 31 When using shared or extended shared registers R observe the precautions given be
263. s on the personal computer without storing them in the CPU module during debugging and program development and download the tag name definitions to the CPU module after the programs are debugged IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 19 6 78 Structures A structure represents a group of data under a unified name It improves device representation and program readability The instructions related to structures are Structure Move STMOV Structure Pointer Declaration STRCT Structure Macro Instruction Call SCALL For details on structures see FA M3 Programming Tool WideField3 IM 34M06Q16 COE or FA M3 Programming Tool WideField2 IM 34M06Q15 01E For details on the instructions see Sequence CPU Instruction Manual Instructions IM 34M06P12 03E IM 34M06P13 01E 4th Edition Jan 31 2012 00 7 1 T I O Response Time Based on Scan Time This chapter discusses examples of calculating the scan time and I O response time It also explains such parameters as instruction execution time 7 1 Description of Scan Time As discussed earlier in Chapter 3 the sequence CPU module is designed so that two systems of processes i e a system of control related processes and a system of peripheral processes run concurrently and independently For this reason the system of control related processes whose main purpose is to execute programs and control related processes is not affected by the system of p
264. s timers Non latching type except for continuous timers Non latching type except for continuous timers Counter C All latched C0001 to C1024 All latched C0001 to C1024 All latched C0001 to C1024 Configurable for timers counters contiguous from a starting number Data register D All latched D00001 to D16384 All latched D00001 to D32768 All latched D00001 to D65535 Shared register R Non latching type Non latching type Non latching type Configurable on 2 register basis contiguous from a starting number 2 Extended shared register R Link register W aa on 16 register i If the upper limit of the range of shared relays E used is smaller than E2049 the last device number for shared relays E is followed by the first device number for extended shared relays E Likewise if the upper limit of shared registers R used is smaller than R1025 the last device number for shared registers R is followed by the first device number for extended shared registers R 2 The data latch range setup for link relay and link register are mapped to contiguous devices starting from their respective starting numbers with the following exceptions L W01024 is followed by L W10001 L W11024 is followed by L W20001 L W21024 is followed by L W30001 L W31024 is followed by L W40001 L W41024 is followed by L W50001 L W51024 is followed by L W60001 L W
265. s to Activate or Inactivate the Sensor Control Block etacton veseripton CBACT instruction Activates the sensor control block CBINA instruction Inactivates the sensor control block SEE ALSO For details on individual instructions see Sequence CPU Instruction Manual Instructions IM 34M06P12 03E TIP When the sensor control block stops the CPU holds or resets the data of output Y relays used or refreshed by the sensor control block according to the setting of the configuration item Output when Stopped When the sensor control block is activated the relays are always set to the Hold option TIP The initialization processing of timers counters and the destinations of OUT instructions does not apply to the sensor control block activated or inactivated by ACT INACT instructions IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 68 E Enabling Disabling Sensor Control Block You can temporarily disable the sensor control block using a CBD Disable Sensor Control Block instruction or enable the sensor control block using a CBE Enable Sensor Control Block instruction If the sensor control block is disabled the CPU does not execute it until it is enabled even if it is time for executing the sensor control block In this case the CPU immediately begins executing the block as soon as it is enabled Table 6 30 Instructions to Disable and Enable Execution of the Sensor Control Block nstcton vese
266. see Subsection 3 22 5 Save User Log ULOG Read User Log ULOGR and Clear User Log UCLR of Sequence CPU Instruction Manual Instructions IM 34M06P 12 036 IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 59 6 15 6 15 1 TIP You may assign any values from 32768 to 32767 to user log main codes Messages for main codes 1 to 64 can be stored in a CPU module You may also assign any values from 32768 to 32767 to user log sub codes Sensor Control Functions To enable request responses at speeds of several hundred microseconds a small PLC or sensor controller is often installed alongside the main PLC The sensor control functions play the role of such a controller enabling a program to be scanned at high speeds and fixed intervals independently and not affected by the main scan time which tends to lengthen due to advanced functionality or high performance of the system Using the sensor control functions you can execute one program block at high speeds and fixed intervals 200 us minimum independent of the regular scan These functions are useful for control applications requiring higher machining accuracy Schematic Operation Diagram The figure below shows the operation of a sensor control block Normal scan Sensor control block Input refreshing Input refreshing Fixed interval of Program execution 200 us or longer Normal program Output refreshing execution i time before
267. sequence CPU module will fail If this happens install the sequence CPU module in the fifth or higher slot of the main unit turn on the power make sure the RDY indicator has come on and then turn off the power This clears the sequence CPU module memory completely and reverts the CPU module to its factory settings IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 32 A CAUTION To use the personal computer link functions enable it using the configuration item Use personal computer link If you do not select this option communication with higher level equipment may fail E Checksum End Character and Protection 6 11 5 Set up these items using the configuration item communications setup By default all these items are disabled SEE ALSO For details on the configuration function see FA M3 Programming Tool WideField3 IM 34M06Q16 ODE or FA M3 Programming Tool WideField2 IM 34M06Q15 01E Communication Procedure To be able to perform communication the transmission specifications including the transmission rate and data format must be consistent between the CPU module and a personal computer FA computer or monitor Use the configuration function to set up the transmission specifications of the sequence CPU module To set the transmission specifications of a personal computer or FA computer use a communication software program To set the transmission specifications of a monitor follow its configu
268. seseeaeeees Appx 3 1 E Relay Devices Assignment Table cccccccesseeceseseteeseeeeees Appx 3 2 E Register Devices Assignment Table ccccccccsesseeeeeeteeees Appx 3 3 E Timer Counter Setpoints Table c ceccccccseseeseeeeecseeeeeeeeees Appx 3 4 IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Blank Page Appx 1 1 Appendix 1 Special Relays M Special relays have specific functions such as indicating the internal state of a sequence CPU module or detecting errors In programs these relays are used mainly for contacts a and b Appendix 1 1 Block Start Status Relays Block Start Status relays indicate which block is running when selected blocks are being executed These relays are numbered in ascending order as M001 M002 to correlate with block 1 block 2 Table Appendix 1 1 Block Start Status Relays Item Block Start Status Relays Sequence CPU ar Module Function Description F3SP05 F3SP08 F3SP21 M0001 to M0032 F3SP22 F3SP25 Indicates whether block n is M0001 to M0032 ON Run executed when the module is F3SP35 Block n start status 7 F3SP28 F3SP38 OFF Stop configured to execute F3SP53 F3SP58 M2001 to M3024 specified blocks only F3SP59 Note The Start Status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032 M0001 to M0032 have the same values as M2001 to M2032 Similarly Start Status relays M2033 to M3024 map to blocks 33 to
269. sing processing time Wait i Synchronization processing F030502 VSD Figure 3 5 Peripheral Processing Time The configurable range is from 0 1 ms to 190 ms on 0 1 ms basis If no peripheral processing time is defined the CPU operates with a peripheral processing time of 0 2 ms by default IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 6 3 6 1 3 8 Method of I O Processing This section describes how I O processing is performed I O response delay as well as I O processing in a multi CPU system Method of I O Processing As the method of I O processing the CPU uses batch refreshing In this method the sequence CPU module acquires all data changes in the input module into the input relay X area of the CPU s data memory before executing each scan The sequence CPU module uses data contained in this area when performing operations Operation results are output to the output relay Y area of the CPU s data memory each time an operation is performed The results are sent to the output module collectively and concurrently with the execution of instructions in the next scan Only modules that are installed in the system and configured in Input Output Setup as Used will have their input and output refreshed No error occurs even if a program tries to access input or output relays of a module which is not installed or a module which is configured in Input Output Setup as Not used External i
270. sor CB scan timeout error may result because the CPU is unable to maintain the execution interval of the sensor control block For details on the module operation in the event of a sensor CB scan timeout error see subsection 6 15 6 Error Handling Maximum program execution time us Maximum number of I O refreshed words discussed earlier Number of words actually refreshed x Number of CPU modules installed x 25 us 50 us Example 1 Execution interval 200 us Number of CPU modules installed 1 Maximum number of O refreshed words 4 from previous Table Number of words actually refreshed 2 Maximum program execution time 4 2 x 1x 25 50 100 us The sensor control block if composed of basic instructions only is equivalent to a program with the following number of steps 100 0 09 1111 steps Approximately 1 1K steps for F3SP22 F3SP28 and F3SP38 CPU modules 100 0 035 2856 steps Approximately 2 8K steps for F3SP53 F3SP58 and F3SP59 CPU modules Example 2 Execution interval 1ms Number of CPU modules installed 1 Maximum number of O refreshed words 36 from previous Table Number of words actually refreshed 6 Maximum program execution time 36 6 x 1 x 25 50 800 us The sensor control block if composed of basic instructions only is equivalent to a program with the following number of steps 800 0 09 8888 steps Approximately 8 7K steps for F3SP22 F3SP28 and F3SP38 CPU
271. sor control block at CPU1 1 ms Sum of input refreshed and output refreshed words for CPU1 Should be kept below 16 Execution interval of sensor control block at CPU2 500 us Sum of input refreshed and output refreshed words of CPU2 Should be kept below 8 The maximum number of O refreshed words is proportional to the execution interval You can calculate the maximum number for any execution interval not given in the above table by using the maximum numbers given for the execution intervals immediately above and below the required execution interval Example 2 Number of CPU modules installed 1 Execution interval of sensor control block 600 us Maximum number of O refreshed words 20 If the maximum number of I O refreshed words is exceeded the execution interval of the sensor control block cannot be maintained This may result in a sensor CB scan timeout error For details on the module operation in the event of a sensor CB scan timeout error see subsection 6 15 6 Error Handling IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 63 E Maximum Program Execution Time You should keep the program execution time of the sensor CB as short as possible Otherwise a program executed under a normal scan will be interrupted for a longer duration and the time interval of the normal scan will become longer Calculate the maximum program execution time using the equation given below If this maximum time is exceeded a sen
272. speed Scan Sensor Control Functions In addition to normal scanning each CPU module has an independent multiple constant scan function permitting fast scanning Fast response is also achievable with a single CPU You can execute a block of your program at a high speed constant scan 200 us minimum separately from normal scanning This feature enables you to eliminate the effects of a fault diagnosis program or MMI program as well as ensure stable control program operation Object Ladder The FA M3 Programming Tool WideField3 an object oriented ladder language development tool is available with the CPU module This tool not only increases software development productivity over and above structured programming but also simplifies program maintenance Function for Storing Comments F3SPOO0 OS Circuit comments subcomments and tag name definitions including I O comments can be stored in the sequence CPU or the ROM pack This function allows you to debug a program using tag names even during unscheduled maintenance IM 34M06P13 01E 4th Edition Jan 31 2012 00 1 2 Other Features E Functions A compact body allows for reduced panel enclosure size Large capacity programs and large device sizes are supported to cope with advanced complex control applications Index modification and structured ladder language simplifies program design and maintenance The device size and operating method can be flexibly
273. ssion rate and parity check are combined See subsection 6 11 4 Setting Up the Personal Computer Link Functions for more information 2 You can set the protection function to the Yes option to prevent inadvertent writing to the FA M3 A CAUTION The personal computer link functions use neither a control line nor Xon Xoff characters Be careful when using the function because a communication failure may occur at the higher level equipment side depending on the transmission rate IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 31 6 11 4 Setting Up the Personal Computer Link Functions This subsection describes the items you should define when using the personal computer link functions E Transmission Rate and Data Format You cannot set up the transmission rate and data format separately because they are shared by WideField3 or WideField2 and the personal computer link functions To define these items use WideField3 or WideField2 or the configuration function The table below shows the available combinations for transmission rate and data format Table 6 9 Combinations of Transmission Rate and Data Format Communication mode 0 9600 8 bits Even 1 bit Transmission Rate and Data Format Mode Transmission Data Rate bps Length Parity Stop Bits Communication mode 1 9600 8 bits None 1 bit Communication mode 2 19200 8 bits Even 1 bit Communication mode 3 19200 8 bits None 1 bit Communication mode 4 3
274. st instruction similarly to when the power is turned on When the operating mode is changed from Stop mode to Debug mode the CPU sets all devices to 0 except for latching type devices before executing the program Be sure to exit from Debug mode and enter Run mode after debugging and tuning E Stop Mode In Stop mode the CPU stops running the program The CPU either hold or reset external outputs depending on the settings of the configuration item Output when stopped This function does not work when the CPU has already stopped running the program St E Clear Memory This function deletes a program or programs and sets all devices except file registers B to 0 You must stop running the program before using this function Sto E Clear Devices This function sets all latching type devices except file registers B to O You must stop running the program before using this function To clear file registers B use the edit device function of the device management functions to set all the file register B data to 0 and then write the data to the sequence CPU module using the write device function SEE ALSO For details on the device management functions see Section 6 12 Device Management Functions IM 34MO6P13 01E 4th Edition Jan 31 2012 00 A CAUTION Observe the following precautions when using the functions described in this chapter Some functions are only available in some but not all of the operating
275. stem refers to a system configured by connecting a personal computer or a monitor to the main unit through a personal computer link module The sequence CPU module can be connected directly to a personal computer or a monitor Personal computer or monitor with PC interface Main unit computer link module F020303 VSD Figure 2 4 Example of Personal Computer Link System FA Link System The FA link system refers to a system that employs FA link communication to build a network system with programmable controllers The types of communication covered by an FA link system are FAlink H communication FA link H module and Fiber optic FA link H communication fiber optic FA link H module Unless otherwise specified the term FA link in this manual comprehensively refers to these two types of communication For more information on the FA link see FA Link H Module Fiber optic FA Link H Module IM 34M06H43 01E FA link Main unit Main unit Main unit i link H module Fiber optic FA link H ee F020304 VSD Figure 2 5 Example of FA Link System IM 34M06P13 01E 4th Edition Jan 31 2012 00 2 6 2 3 4 FL net System An FL net system is based on FL net which is an open network for connecting various progr
276. steps RK33 0N 56K steps F3SP53 4S RK73 0N 56K steps 120K steps RK33 0N 56K steps 56K steps sage RK73 0N 120K steps 720K steps RK93 0N 120K steps 360K steps RK33 0N 56K steps 56K steps F3SP59 7S RK73 0N 120K steps 120K steps RK93 0N 254K steps 360K steps Using configuration you can make the following two types of data resident in ROM These types of data are used to set initial values to be used by a program Setpoints of 1 024 data registers D worth of default data Either 32768 data registers D or file registers B worth of current values within the sequence CPU module See Section 6 8 2 Defining Current Values of Devices to Be Made Resident in ROM At power on data read from the ROM pack is stored in data registers D or file registers B specified with the configuration function Data registers D and file registers B included in the data retention in case of power failure revert to their respective default values If you edit both of the configuration items mentioned above for the same data register D only the setpoint of the second configuration item is effective IM 34MO6P13 01E 4th Edition Jan 31 2012 00 6 19 TIP Data retention in case of power failure is effective for devices not included in the configuration discussed above Program RAM configuration ROM pack configuration Program management Program management 1 1 1
277. ster Q Q01 Q02 Pointer P Registers Pointer registers are used specifically to pass parameters to macro instructions These registers can be used within macro instruction entities Structure macro instructions use structure pointer registers instead of pointer registers The relationship between pointer registers P and macro instruction parameters is shown in the following figure M EFG123 D0001 10001 Y00301 L Parameter 3 We oe Sel as Parameter 2 AEE EENET Parameter 1 F061305 VSD Table 6 18 Relationship between Pointer Registers and Macro Instruction Parameters Operand No Pointer Register No 1 A Parameters that can be directly passed using a macro instruction call lt gt Parameters that can be passed using a parameter instruction F061306 VSD Within a macro instruction entity you can read from and write to pointer registers using basic or application instructions in the same way as for devices passed as parameters You can also perform word long word processing index modification and automatic BIN to BCD or BCD to BIN conversion on these pointer registers High speed processing of application instructions is not performed however More specifically within a macro instruction entity high speed processing is not performed for MOV CAL CMP or logical operation instructions with pointer registers specified as parameters TIP When an
278. t Comment Subcomment in the storing to CPU settings in the local device properties for each relevant block macro instruction Then turn on the download comments checkbox when you execute the download program function Turning on this checkbox downloads comments to the CPU module according to the block properties Turning off the circuit comments subcomments checkbox when you execute the download program function will not download comments regardless of the block properties setup SEE ALSO For details on block properties and program downloading see FA M3 Programming Tool WideField3 IM 34M06Q16 O0E or FA M3 Programming Tool WideField2 IM 34M06Q15 01E FON CAUTION Note that if you turn off the checkbox for circuit comments subcomments when you execute the download program function comments will not be downloaded to the CPU module regardless of the local device properties setup IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 75 6 17 2 Number of Steps Needed for Comments Like program steps circuit comments subcomments also takes up program area Thus how much of the program area is consumed in terms of step count also depends on whether comments are downloaded to a CPU module E Calculating the Step Count of Comments if comments are downloaded The step count of a circuit comment or a circuit subcomment is the sum of the comment offset 1 step and step count of the character string as given below Step co
279. t status when the program stops HOLD RESET in the specifications section of each individual output module discussed in Hardware Manual IM 34M06C11 01E For a special module the setting for a stop of programs due to a major failure is always ignored By default all output modules are set to the option Reset You can perform this configuration on 16 relay basis A CAUTION When using output modules or special modules with YOOOOO output relays in a multi CPU system configuration Combination of F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 F3SP66 F3SP67 F3SP71 and F3SP76 CPU Modules You can output data from multiple sequence CPU modules separately to the output relays of the same output module on 16 relay basis To do this configure the sequence CPU modules so that all of them share the same output option Hold or Reset Also re configure any sequence CPU module whose output relays are set to the option Not Used so that it has the same settings as the other CPUs Other Combinations of CPU Modules You may not use the same output module with multiple CPUs IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 2 4 2 1 4 6 Internal Relays Il Shared Relays E and Extended Shared Relays E This section describes internal relays I shared relays E and extended shared relays E Internal relays l are 1 bit variables that can be used without restriction in a program Shared relays E
280. t the input sampling interval for input relays of input modules Note that this setting is ignored for some input modules For details refer to the data item response time in the specifications section of individual input modules given in Hardware Manual IM 34M06C11 01E You can select from five options namely 16 ms 1 0 ms 250 us 62 5 us and Always By default all input modules are set to 16 ms You can specify the sampling interval on 16 relay basis AN CAUTION If a single input module or special module with input relays XOO0 000 is used with two or more CPU modules in a multi CPU system configuration configure the CPUs so that they have the same sampling interval for all relays of that input module Also re configure any CPU whose input relays X were set to the option Not Used so that it has the same settings as the other CPUs Otherwise system operation may be unstable IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 5 E Specifying Output When Stopped Holding Resetting Output Relays When Sequence Stops Specify whether the output relays Y of an output module or special module with output relays YOOOOD should be placed in a Hold state or Reset state when a program stops due to a moderate or major failure or a switch to stop mode The setting is however ignored by some output modules in the event of a major failure Refer to the data item Outpu
281. te Power Failure If a complete power failure occurs the CPU operates as it does at power off You can configure the types and ranges of devices to be latched in case of a complete power failure This strategy allows the CPU to resume operation from its previous state after power is restored When power is restored the CPU executes the program from its beginning TIP Latching devices at power failure stores device states immediately before a power failure so that a program can continue execution in the same state after power is restored Data Latch Range at Power Failure This configuration item sets the range of devices to be latched in case of a complete power failure Specify the starting number and the number of devices for each device type The following table shows the default setting and the configurable range of each device type Table 3 2 Data Latch Range at Power Failure of Configuration Default F3SP38 F3SP58 F3SP22 F3SP59 F3SP28 F3SP53 10001 to 11024 Non latching type Configuration Range 10001 to 11024 Non latching type 10001 to 11024 Non latching type Configurable on 32 relay basis contiguous from a starting number Configurable on 16 relay basis Internal relay I Shared relay E Extended shared relay E Link relay L Non latching type Non latching type Non latching type Data Latch Range at Power Failure Timer T Non latching type except for continuou
282. ted processes Synchronization between Systems of Control related Processes and Peripheral Processes The system of peripheral processes executes concurrent with and independent of the system of control related processes For processes related to operation control e g run or stop or processes requiring simultaneity of data however the CPU synchronizes these two systems using a synchronization process included in the system of control related processes The time required for the synchronization process varies depending on its content Using debugging functions such as online editing affects the scan time A CAUTION If the ratio of the instruction execution time to the scan time is too small insufficient time may be allocated for executing the system of peripheral processes Consequently the responses of link refreshing shared refreshing tool service personal computer link service and CPU service will become extremely slow If this happens use a constant scan with an interval somewhat longer than the normal scan time or set up the peripheral processing time to secure sufficient time for executing the system of peripheral processes IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 5 3 7 Method of Executing Peripheral Processes Peripheral processes are executed concurrently with instructions in a program When the execution of program instructions is completed any peripheral process is interrupted until the next sca
283. ters combined Extended shared relay E Shared Device E R Shared register R 0 Extended shared register R 0 Configuration of Timers T counters C Counter Table 1 8 Configuration Range 3 5 F3SP22 0S F3SP28 3N 3S F3SP53 4H 4S F3SP38 6N 6S F3SP58 6H 6S F3SP59 7S Item Default Configuration Range Internal relay I 10001 to 11024 shared relay E Extended shared relay E Link relay L Non latched type Configurable on 16 point basis Non latched type Timer T except for Configurable on 1 point basis continuous continuous timers from the starting number Counter C All latched Data register D All latched Shared registers R Extended shared registers R Link register W Non latched type Configurable on 16 point basis Configurable on 32 point basis continuous Non latched type from the starting number Extended Configuration of the range device of devices to be latched in configuration case of power failure Configurable on 2 point basis continuous Non latched type from the starting number Note The configuration range of each of shared relays E and extended shared relays E and shared registers R and extended shared registers R to be latched in case of power failure is assigned numbers continuous from the starting number However if the number of shared relays E is smaller than 2048 the last of them is
284. ters on word or long word basis using application instructions When you use data registers on a long word basis the low order 16 bits are stored in the data register with the number specified in the instruction and the high order 16 bits are stored in the data register with that number incremented by 1 X00502 MOV 100 D0001 X00501 X00502 Y00601 X00503 X00504 H X00501 T001 i i ri O xoo503 F D0001 100 EErEE gt 1234 4 Y00602 f O D0002 5678 aaa D0003 1234 F040701 VSD Figure 4 21 Data Registers D Using the configuration function you can define the data latch range at power failure for devices whose operation results are to be latched when power is turned off By default all data registers D are latched A non latched device will be cleared to OFF 0 when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Device command from WideField3 or WideField2 A latched device retains its operation result even after power off and power on and is cleared to OFF 0 when you execute a Clear Device command from WideField3 or WideField2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 7 2 4 29 Shared Registers R and Extended Shared Registers R Shared registers and extended shared registers are used to exc
285. tes its end of count relay turns on The end of count relay is used for a contact a or b A counter C is reset at the rising edge of its counter reset input and its current value returns to its setpoint Count input is ignored when the counter reset input is on Setpoint 1 to 32767 Count input CNT C001 100 Counter Y00602 reset input A VU Counter reset input X00501 Count input ON X00502 OFF Current value co01 relay OFF End of count ON co01 F040601 VSD Figure 4 20 Counter C Using the configuration function you can define a range of counters whose current values are to be latched when power is turned off By default all counters are latched A non latched counter resets its current value to its setpoint when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Device command from WideField3 or WideField2 A latched counter retains its current value even after power off and power on and resets its current value to its setpoint when you execute a Clear Device command from WideField3 or WideField2 TIP A counter setpoint is used by a counter as its current value when it starts counting The counter setpoint can be set using a Counter CNT instruction IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 6 1 TIP said to have terminated Sele
286. the next fixed interval scan Input refreshing Interruption of Fixed interval of Program execution xed interva o execution g 200 us or longer ieee ine tocar An bg ence Output refreshing Yy Input refreshing Interruptionof A Program execution Fixed interval of ae e ee Ea eee E EE ge 200 us or longer Output refreshing Common processing y Input refreshing Fixed interval of Program execution 200 us or longer Output refreshing Output refreshing F061501 VSD Figure 6 42 Schematic Diagram of Sensor Control Block Operation IM 34MO06P13 01E 4th Edition Jan 31 2012 00 6 60 6 15 2 Features E Features The sensor control functions have the following features High Speed The minimum interval of block execution is as short as 200 us The sequence CPU module operates as if it contains another sequence CPU module with the minimum scan time of 200 us The maximum I O response delay is only 400 us i e twice the minimum interval of block execution You can use it for a process requiring fast I O response by isolating the process from the regular program It allows the use of a wide choice of modules including special modules for input output Fixed Interval The sensor control block is executed at fixed intervals The sensor control block function runs even during instruction execution refreshing or common p
287. the shared relays registers and extended shared relays registers of a CPU from the other CPUs Refreshing may be delayed by as much as the longest scan amongst these CPUs to ensure simultaneity of data 1 1 One scan N One scan NK One scan g y i i One scan i 1 F030906 VSD Figure 3 16 Shared Refreshing as a Peripheral Process CPU2 CPU2 Refreshing may be delayed CPU3 Shared refreshing of Shared refreshing of by Ahen esi a Shared refreshing of shared relays registers extended shared ensure simultaneity of data shared relays registers relays registers vin SE Data updates are reflected by this common processing Instruction execution Instruction execution Instruction execution Instruction execution With this common processing it becomes possible to alternately refer to the shared relays registers and extended shared relays registers of a CPU from the other CPUs Refreshing may be delayed by as much as the longest scan amongst these CPUs to ensure simultaneity of data One scan i One scan i One scan i One scan lt gt K gt K gt L gt i i i F030907 VSD Figure 3 17 Shared Refreshing as a Control related Process IM 34M06P13 01E 4th Edition Jan 31 2012 00 3 18 SEE ALSO Tables 3 3 and 3 4 show examples of how shared refreshing affects the scan time For more information see Section 7 1 Description of Scan Time These examples assume that both CPU
288. the user Make sure to dispose of the batteries along with the product Do not dispose in domestic household waste When disposing products in the EU contact your local Yokogawa Europe B V office Battery type Lithium battery bd Note The symbol above means that the battery must be collected separately as specified in Annex II of the EU new directive on batteries IM 34MO06P13 01E 4th Edition Jan 31 2012 00 Introduction E Overview of the Manual This manual describes the sequencing functions of sequence CPU modules For F3SP22 F3SP28 3N 3S F3SP38 6N 6S F3SP53 4H 4S F3SP58 6H 6S F3SP59 7S designed for use with the Range free Multi controller FA M3 m How to Read the Manual If you are a first time reader first go through this paragraph How to Read the Manual and proceed to Chapter 1 then Chapter 3 For efficiency read only the relevant remaining chapters according to your flow of work from system design to system operation The chart below shows the regular workflow from system design to system operation as well as chapters you should refer to in each step Work Flow from System Design to System Operation and Relevant Chapters Design Start System design Basic design Determination of system configuration lt Chapter 2 System Configuration Assignment of I Os registers and relays Coding Programming lt Chapter 4
289. timer T is reset its current value returns to the setpoint and the time out relay is set to OFF To reset a continuous timer before expiry write O to the timer using a MOV instruction MOV 0 Tnnn when the timer input is in an OFF state Timer input i X00502 pa homes TIM T241 10s X00501 10001 e Yoo6o1 f A O X00301 T2474 Y00603 f i 4 O oppa N Timer input ON X00502 Setpoint Current value T241 Time out relay T241 1 2 10s F040502 VSD Figure 4 19 100 ms Continuous Timers Using the configuration function you can define a range of timer devices whose current values are to be latched when power is turned off By default all timers are non latched A non latched timer resets its current value to its setpoint when you perform any of the following power on the module switch the operating mode to Run or Debug using WideField3 or WideField2 execute a Clear Device command from WideField3 or WideField2 A latched timer retains its current value even after power off and power on and resets its current value to its setpoint when you execute a Clear Device command from WideField3 or WideField2 IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 25 4 5 3 Selecting Timers Configure the device range to be used for each type of 100 us 1 ms 10 ms and 100 ms timers and 100 ms continuous timers To do so specify the number of timers to b
290. tion the relevant parameters are overwritten A CAUTION Errors generated in nested macro instructions are reported as errors of the first macro instruction SEE ALSO For details on the Parameter PARA instruction see Section 3 13 4 Macro Call MCALL Parameter PARA Macro Return MRETY of Sequence CPU Instruction Manual Instructions IM 34M06P12 03E IM 34M06P13 01E 4th Edition Jan 31 2012 00 6 51 When nesting macro instructions you may mistakenly overwrite macro devices such as relays registers and index registers in a called macro instruction and thereby destroy their data To avoid this problem check the depth of macro instruction nesting stored in special register Z106 and use macro devices separately for each level of nesting depth see the example below X00501 M 1 NEST1 D0001 D0002 0 NEST1 macro instruction entity X00502 II u01 Z106 i 64 l l 0 0 u01 A001 P1 1 v A01 A001 to A064 can be used M U01 NEST2 A01 P2 0 U01 Z106 i 64 Data of U01 is destroyed by NEST2 instruction MRET NEST2 macro instruction entity X00503 1 U01 Z106 64 y 64 1 U01 A001 P1 1 v A65 A065 to A128 can be used M U
291. tion of WideField3 or WideField2 You can specify whether to make the current values of devices resident in ROM and whether to write tag name definitions to the ROM pack A debugged and or tuned program or data in the CPU is not initialized when the CPU is changed to the ROM Writer mode It is therefore possible to write the program or data directly to ROM If tag name definitions are downloaded in the CPU they are also written directly the ROM pack This function is also used to write the same program to multiple ROM packs You can write the program to multiple ROM packs by simply changing the ROM packs one after another There is no need to transfer the program repeatedly E Compare File and ROM Function This function compares the content of the ROM pack with the program in WideField3 or WideField2 If the contents do not match the function shows the mismatches E ROM Clearance Function This function erases the content of a ROM AY CAUTION Change the CPU to the ROM Writer mode before using the ROM writer functions You cannot use the ROM Writer functions in other modes Be sure to disable the ROM Writer mode when you finish using the ROM writer functions The CPU does not execute any sequencing functions if the ROM Writer mode remains active Never try to switch off the module when the ROM pack is being overwritten or cleared Otherwise the ROM pack may develop a permanent error and become no longer usable IM 34MO6P13
292. tions exceeded the limit error code 2401 2402 Application error READ WRITE Corrective Actions Check if there is a jump out of or into the input interrupt program Check if a scan timeout was detected within the input interrupt program There are more than eight pending interrupts Check the detailed process of each interrupt the number of interrupts their frequency etc Check whether there are more than eight pending interrupts after powering on and before executing the program Check if any abnormal value is set in the instruction parameter Check if any abnormal value such as one based on division by 0 is set in the instruction parameter An invalid value may have been set in BIN to BCD conversion Check the parameter where the error has occurred Check if data written to the FIFO table has exceeded its capacity Check if an attempt has been made to read data values from the FIFO table when there is none Check if the default settings of the FIFO table are correct Also check if the table has been corrupted by any other part of the program Check if there is any error in the values of index registers or in the parameters defining the number of devices in an instruction for writing to multiple devices such as a Block Move BMOV instruction Check if there is a jump out of or into the FOR NEXT loop Check if a scan timeout has been detected within the FOR NEXT loop Check
293. tions to make index modifications Use these registers to address a device by adding the content of an index register to a device number which is directly specified in an instruction SEE ALSO For details on index registers see Section 1 10 1 Index Modification in Sequence CPU Instruction Manual Instructions IM 34MO06P12 03E X00502 mov 100 voi 10001 X00502 Y00601 V01 vo1 vo2 X00503 X00504 i H X00501 T001 7 Y00602 j i O X00503 i y Vv D 0001 100 D0101 I 0001 100 10101 F040901 VSD Figure 4 27 Index Registers AN CAUTION The sequence CPU module performs no check on whether an index modified device exceeds the device configuration range If an index register is incorrectly specified the device configuration range may be exceeded resulting in inadvertent selection of a different type of device A CAUTION An index register can be set to any value between 32768 and 32767 Therefore for devices such as file registers B whose size is larger than 32768 index modification cannot cover the entire device IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 10 4 41 File Registers B File registers B are used as extensions of data registers D Each file register consists of one word Like data registers D you can read from or write to file registers on a word basis or 32 bit basis using application instructions
294. uaranteed irrespective of the configuration settings The Non simultaneous option of this configuration item is intended for compatibility with the F3SP21 F3SP25 and F3SP35 modules Select this option when replacing these modules with the F3SP22 F3SP28 F3SP38 F3SP53 F3SP58 or F3SP59 modules IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 16 E Shared Refreshing Mode Changing to Control related Process You can change by configuration the mode of shared refreshing which updates the data of relays E and registers R shared with other CPUs so that it runs as a control related process Run shared refreshing as a peripheral process if a short scan time is important Alternatively run it as a control related process if the speed of exchanging shared data is important Peripheral processes en ne K Common processing i Shared refreshing Input refreshing i Pea we Link refreshing Instruction One scan execution i Command processing f Tool service i os Link service ae CPU service Synchronization processing i F030904 VSD Figure 3 14 Executing Shared Refreshing as a Peripheral Process Executing shared refreshing as a peripheral process reduces its effects on scanning Common processing Peripheral processes Input refreshing including shared refreshing Output refreshing Link refreshing Instruction execution Command processing
295. uence CPU module see Section 1 2 4 Components and Their Functions For the external dimensions of the sequence CPU module see Section 1 2 5 External Dimensions 1 2 1 Control method List of Specifications Table 1 1 Functional Specification F3SPO0 OS 1 2 Specifications F3SP22 0S F3SP28 3S F3SP53 4S F3SP38 6S Repetitive operation based on stored programs F3SP58 6S F3SP59 7S I O method Refresh method Direct I O instruction Programming language Structured ladder language and mnemonic language Number of I O points 4096 max 8192 max including remote I O points Number of internal relays I 16384 16384 16384 32768 32768 65535 Number of shared relays E 2048 2048 2048 2048 2048 2048 Number of extended shared relays E 2048 2048 2048 2048 2048 2048 Number of link relays L 8192 8192 8192 16384 16384 16384 Number of special relays M 9984 9984 9984 9984 9984 9984 Number of timers T Number of counters C 2048 in total 2048 in total 2048 in total 3072 in total 3072 in total 3072 in total Number of data registers D 16384 16384 16384 32768 32768 65535 Number of shared registers R 1024 1024 1024 1024 1024 1024 Number of extended shared registers R 3072 3072 3072 3072 3072
296. unt of a comment comment offset 1 step step count of the character string The step count of the character string is calculated as follows Sum the step counts of all characters in a character string using 0 25 steps for each single byte character and 0 5 steps for each double byte character and round up to the nearest integer TIP Example Assume that a comment is a character string consisting of four single byte character and five double byte characters Summing the step counts of individual characters yields 4 x 0 25 for single byte characters 5 x 0 5 for double byte characters 3 5 steps Rounding up to the nearest integer yields Step count of the character string 4 steps Adding 1 step for comment offset Step count of the comment 4 1 5 steps If no comments are downloaded One step of program area is consumed for each comment as comment offset A CAUTION One step of comment offset is added for each comment to the step count for a program even if the comments are not downloaded E Checking the Program Step Count including Comments The step count of a block or macro instruction containing comments is displayed on the status bar when the block is opened The displayed step count includes the step counts of circuit comments subcomments and block tag name definition specified to be downloaded to the CPU module in the local device properties window If you select to only download the prog
297. ut interrupt program program code between INTP and IRET instructions after it finishes executing a ladder instruction This switching does not take place however during synchronization processing common processing or input refreshing Immediate during instruction execution Execution of normal programs Next instruction dmon nai a aa aaa a i r The sequence CPU switches execution to an input interrupt program program code between INTP and IRET instructions during execution of a ladder instruction This switching takes place even during synchronization processing common processing or input refreshing Execution of input interrupt programs Execution of input interrupt program Part between INTP and IRET instructions F031103 VSD Figure 3 30 Execution of Input Interrupt Program after the Completion of Instruction Execution Execution of normal program BMOV Interruption of program execution Continuation of BMOV instruction Next instruction Figure 3 31 Immediate Execution of Input Interrupt Program during Instruction Execution Execution of input interrupt program Execution of input interrupt program Program code between INTP and IRET instructions F031104 VSD IM 34M06P13 01E 4th Edition Jan 31 2012 00 The 3 29 characteristics of these two interrupt timing options are summarized in the table below Table 3 8 Characteristics of Interrupt Ti
298. ut terminal numbers of a mixed l O module or special module with 32 input and output points each are assigned as 1 to 32 and as 33 to 64 respectively IM 34M06P13 01E 4th Edition Jan 31 2012 00 Blank Page 2 2 2 2 1 2 1 System Configuration This chapter describes the FA M3 system configuration and programming tools Basic System Configuration The basic system configuration refers to a system consisting of a main unit only For more information on the main unit see subsection 1 3 1 Unit Lo CPU module or BASIC CPU module supply module T Power F020101 VSD Figure 2 1 Example of Basic System Configuration when a 13 slot base module is used Multi CPU System Configuration This section describes a multi CPU system configuration and the handling of I O modules in a multi CPU system Multi CPU System Configuration A multi CPU system configuration refers to a system comprising multiple CPU modules A maximum of four CPU modules can be installed in the slots slots 001 to 004 on the main unit A CPU module installed in slot 001 serves as the main CPU module and CPU modules installed in slots 002 to 004 serve as add on CPU modules A maximum of four sequence CPU modules can be installed at the same time while only one F3BPQOO BASIC CPU module is allowed in this
299. uter link service if there is no command to be processed Personal computer or monitor Personal computer link Sequence CPU Peripheral processes Shared refreshing Common processing Input refreshing Output refreshing Link refreshing Instruction execution Command processing Tool service Link service CPU service Synchronization processing F030801 VSD Figure 3 10 Execution of Commands through Personal Computer Link IM 34MO06P13 01E 4th Edition Jan 31 2012 00 3 9 3 9 1 Method of CPU to CPU Data Communication CPU to CPU communication in a multi CPU system configured using add on CPUs is carried out using a shared data communication method and CPU services Communications between sequence CPU modules is carried out using shared data communications while communications between sequence CPU modules and other types of CPU modules such as BASIC CPU modules is carried out using shared data communications or CPU services This section describes methods for updating shared data configuration of shared refreshing and the CPU service Method of Updating Shared Data CPU to CPU data exchange in a multi CPU system configured using multiple CPU modules is carried out through shared relays E extended shared relays E shared registers R and
300. y x EN Y00401 to Y00432 i 2 3 4 5 1 2 3 4 5 T T passassi H i i i 1 1 1 1 i Empty i Empty i 1 slot p slot p 0U Empty slot 64 32 q 32 Empty slot 32 q 32 i 64 relays relays relays relays 64 relays relays relays H 7 T i i amp N X00201 to X00301 to Y00501 to Relay numbers X00264 X00332 Y00532 F040103 VSD Figure 4 3 Allocation of I O Addresses IM 34M06P13 01E 4th Edition Jan 31 2012 00 4 1 4 4 3 Configuring DIO Modules This section describes settings for terminal usage use not used sensor control block data code BIN BCD input sampling interval 16 ms 1 0 ms 250 us 62 5 us Always and holding resetting output relays when the program stops E Specifying Terminal Usage Using the configuration function select one of the three options Use Use with SCB and Not Used to specify whether the I O module is used in programs or used in the sensor control block or not used at all In this selection configure the I O module on 16 point basis see the second caution below when the selected option is Use with SCB Configure special modules containing I O relays X Y in the same way as discussed here I O relays that are included in the option Not Used are not refreshed at all By default all I O modules are set to the option Use SEE ALSO For details on the sensor control block see Section 6 15
301. ys M129 Run Mode Flag Function Run mode Other modes Description Indicates the status of CPU operation M130 Debug Mode Flag Debug mode Other modes Indicates the status of CPU operation M131 Stop Mode Flag Stop mode Other modes Indicates the status of CPU operation M132 Pause Flag Pause Run Indicates the status of program execution during debug mode operation M133 Execution Flag Specified blocks All blocks Indicates whether all blocks or specified blocks are executed M135 RAM ROM based Operation Flag ROM based operation RAM based operation Indicates whether operation is based on the ROM or RAM M136 Power on Operation Flag Power on operation Other modes of operation Indicates whether operation was initiated by power on or reset M137 Sensor CB Execution Status Run Stop Indicates the status of sensor control block execution M172 write enabled Set Clock Time Time being set Requests to set clock data M173 Input offline Flag Offline Online Indicates that input refreshing has stopped M174 Output offline Flag Offline Online Indicates that output refreshing has stopped M175 Shared O offline Flag Offline Online Indicates that shared refreshing has stopped M176 Link I O offline Flag Offline Online

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