AN 706 - Routing HPS Peripheral Signals to the FPGA
Contents
1. by ethernet ffF700000 compatible altr socfpga stmmac Ssnps dwmac 3 70a snps dwmac reg lt 0xff700000 0x2000 gt interrupts lt 0x0 0x73 0x4 gt interrupt names macirq mac address 00 00 00 OO OO OO clocks lt 0xd gt clock names stmmaceth status okay phy mode mii phy add r lt Oxfrrrt rrr snsp Related Information GSRD User Manual Device Tree Generator Refer to this location for information on device tree generation Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 2014 07 17 Board Setup and Booting Linux from the SD Card Board Setup and Booting Linux from the SD Card 15 Before you begin Board setup is based on the GSRD Getting Started Guides 1 Connect Ethernet Cable to the ENET1 Ethernet port Figure 8 Ethernet Connection on Cyclone V SoC Development Board Connect Ethernet Cable COLD WAAN iT k Se ia Se rE a Ai a on bi iene MME HT SZ BREEZE a H rr Ji ca ae EAH a ats pE ana fi Ai S io ir r 2 Slot in the SD card and power on the board 3 Program the FPGA sof file and perform a warm reset on the HPS component to reload the SD card image 4 The kernel automatically enables and initializes EMACO then executes the dynamic host configuration protocol DHCP to obtain an IP address 5 When the boot process has completed lo2. AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface 2014 07 17 AN 706 lt Subscribe GJ Send Feedback The Altera SoC integrates an ARM Cortex A9 based hard processor system HPS consisting of processor peripherals and memory interface with the FPGA fabric using a high bandwidth interconnect backbone The Cyclone V HPS Interface provides up to 67 I O pins to share with multiple peripherals through sets of configurable multiplexers The Arria V Interface provides up to 71 I O pins This application note describes the steps required to route an HPS peripheral through the FPGA interface using Qsys and Quartus II software A simple design example is included to demonstrate exporting HPS EMACO and 12C0 peripheral signals to the FPGA interface using a Cyclone V SoC Development Kit HPS Peripherals That Support Routing to the FPGA The types of peripherals in the HPS that are capable of routing to the FPGA fabric are e Ethernet Media Access Controller EMAC e Quad Serial Peripheral Interface QSPI e Serial Peripheral Interface SPI e Universal Asynchronous Receiver Transmitter UART e Inter Integrated Circuit I7C e Controller Area Network CAN In many cases routing the HPS IP signals to the FPGA external interface allows more signals to be exposed Table 1 Peripherals that Support Signal Routing from the HPS Domain to FPGA Domain The following table lists the interface type that is available depending on whet
3. PS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 2014 07 17 Getting Started Getting Started 5 1 Make a copy of the Cyclone V Golden Hardware Reference Design GHRD from your Cyclone V SoC Development Kit installation location or download the latest Cyclone V GHRD design example from the Rocketboards website to your project location 2 Download the AN 706 design files an706 design files zip provided 3 Open the GHRD project within the Quartus II software Generating the Initial HDL in Qsys 1 In the Quartus II navigation bar select Tools gt Qsys 2 In the Qsys window select File gt Open gt soc_system qsys 3 In the System Contents tab double click on nps_o to open the HPS Parameters window Figure 2 System Contents Window Qsys soc_system qsys C altera GSRD cv_soc_devkit_ghrd soc_system qsys File Edit System Generate View Tools Help 3 Interconnect Requirements f2h_cold_reset_req f2h_debug_reset_req R f2h_warm_reset_req f2h_stm_hw_events B A S lt J K 4 gt A GX Be Interface Protocols Memories and Memory Controllers Memory Interfaces and Controllers Peripherals PLL Processors and Peripherals Qsys Interconnect E E E h2f _Iw_axi_master f2h_irq0 f2h_irqi E hps_only_master JTAG to Avalon Master Bridge dk Clock Input dk_reset Reset Input Avalon Memory Mapped Master Reset Output System ID Peripheral Clock Input Reset Input Avalon M
4. Verilog file Qsys exposes the following EMACO0 and I2C0 interfaces in the file Table 3 EMACO Signals in the FPGA Domain es a n e a ee emac0_phy_txd_o 8 PHY Transmit Data emac0_phy_txen_o Out PHY Transmit Data Enable emac0_phy_txer_o 1 Out PHY Transmit Error emac0_phy_rxdv_i 1 In PHY Receive Data Valid emac0_phy_rxd_i In PHY Receive Data emac0_phy_col_i 1 In PHY Collision Detect AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback AN 706 Generating the Initial HDL in Qsys 2014 07 17 ee a emac0_phy_crs_i PHY Carrier Sense emac0O_gmii_mdo_ 1 Out MDIO signal data out o emac0_gmii_mdo_ 1 Out MDIO signal output enable oe emac0_gmii_mdc_o Out Management Data Clock emac0_phy_txclk_o 1 Out Transmit clock output to the PHY emacO_rst_clk tx 1 Out Transmit clock reset output to n_o the FPGA interface n_o Table 4 12CO Signals in the FPGA Domain ene reer i2c0_out_data Outgoing I C data enable i2c0_clk_clk i Out Outgoing I C clock enable i2c0_scl_in_clk 1 In Incoming I C clock source Related Information e Ethernet Media Access Controller Refer to the interface descriptions in the Ethernet Media Access Controller chapter of the HPS Technical Reference Manual for more detailed GMII interface signal descriptions Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 2014 07 17 Top Level Routing 9
5. ation GJ Send Feedback m AN 706 12C Test 2014 07 17 Figure 12 ethtool etho Command Output I2C Test The I C interface can be tested using the following commands gt 12cdetect 1 List the detected HPS I C ports gt i2cdetect r 0 List the I7C slave devices connected to the HPS UU is defined as device busy Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 m 2014 07 17 12C Test Figure 13 i2cdetect Command Outputs gt i2cset y 0 0x66 0x10 0x55 I2C0 writes the data value 0x55 to the data address 0x10 of slave device at 0x66 The command is written in the order device address data address data value gt i2cget y 0 0x66 0x10 Return data value at address 0x10 of the device slave at address 0x66 Figure 14 i2cset and i2cget Commands gt i2cdump y O 0x66 Register data dump from 0x00 to OxFF XX is defined as a non valid address AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback 20 Reference Documents Figure 15 i2cdump Command Output Mt am O E io O tin t E oe i ne D bi i m OL wo Reference Documents AN 706 2014 07 17 p H Lod od 1 A summary list of the reference documents and sites mentioned in this application note follows Related Information Altera Corporation HPS to FPGA Application Note AN 706 Design Example Cyclon
6. back AN 706 3 2014 07 17 HPS IP Interface to FPGA Design Example HPS IP Interface to FPGA Design Example This design example based on the Golden System Reference Design GSRD uses the Cyclone V SoC development kit resources to demonstrate routing the HPS EMACO and I2C0 peripheral signals to the FPGA interface The HPS component provides up to two EMAC peripherals which support 10 100 1000 Mbps operation The Cyclone V SoC Development board is populated with a Micrel KSZ9021RN RGMII PHY that interfaces to the HPS domain and a Renesas uPD60620A MII Dual Port PHY that interfaces to the FPGA domain The HPS and FPGA also share a common IC bus to various on board I C slaves Figure 1 High level Routing Layout of Cyclone V SoC Board Design Example Altera 5CSXFC6D6F3 1C6 FPGA Domain Qsys System GMIl Signals 2 Signals The following sections provide the necessary information to route the HPS peripherals to the FPGA interface such as Prerequisites on page 4 Getting Started on page 5 Generating the Initial HDL in Qsys on page 5 Top Level Routing on page 9 Timing Constraint Configuration on page 11 NW WN Quartus II Pin Assignments on page 11 AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback _ AN 706 4 Prerequisites 2014 07 17 7 Hardware Programming File Compilation and Generation on page 13 8 SD Card Image Updates on page 13 9 Board Setup and B
7. cts as a master to various on board I C slaves e Two Octal Digital Power Supply Managers with EEPROM e LCD e RTC e EEPROM Note A bi directional buffer alt_iobuff must be added in the design to connect the LC signals to an external open drain IO The buffer can be included by instantiating alt_iobuff in ghrd_top v Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 e e e e 1 1 2014 07 17 Timing Constraint Configuration The following Verilog code shows the alt_iobuf f instantiation for an I7C interface implemented through the FPGA ALT TOBUF scl iobu uf 2 1 50 oe Sel_ 0 4 6 scl_6 to fpga_12c_scl declared bi directional buffer for scl ALT_IOBUF sda_iobuf i 1 b0 oce sda_o_e o sda_o io fpga_i2c_sda declared bi directional buffer for sda Related Information alt_iobuff Primitive Refer to the alt_iobuff primitive information for more information Timing Constraint Configuration Replace the soc_system_timing sdc file in your project directory with the soc_system_timing sdc file provided in the project folder This new file is customized for the EMACO and I2C0 interface being tested on the Cyclone V SoC development board Quartus II Pin Assignments 1 Copy an706_de_pin_assignment tcl from the AN 706 design files into your project directory 2 In the Quartus II menu bar select Tools gt Tcl Scripts 3 In the Tcl Scripts window c
8. e I2C Controller Refer to the interface descriptions in the FC Controller chapter of the HPS Technical Reference Manual for more detailed I C interface signal descriptions Top Level Routing The top level RTL file defines the pin connections from the HPS EMAC to the Renesas MII PHY on the Cyclone V SoC development board Note Because MII is a 4 bit data width protocol connect only the lower 4 bits emac0O_phy_txd_o 3 0 and emac0_phy_rxd_i 3 0 of EMACO s RX and TX interface from the FPGA AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback 10 Top Level Routing Figure 6 Routing of the EMACO FPGA Interface to the On board MII PHY HPS to FPGA Signal Interface gmii_mdo_o_e gmii_mdo_o gmii_mdi_i gmii_mdc_o phy_txd_o 3 phy_txd_o 2 phy_txd_o 1 phy_txd_o 0 phy_txen_o phy_txer_o phy_rxd_i 3 phy_rxd_i 2 phy_rxd_i 1 phy_rxd_i 0 phy_rxdv_i phy_rxer_i clk_rx_i clk_tx_i phy_txclk_o gtx_clk rst_clk_ tx _n_o rst_clk_rx_n_o phy_col_i phy_crs_i PHY Signal Interface x V Shp ap tattle MDIO MDC PO_TXD 3 PO_TXD 2 PO_TXD 1 PO_TXD 0 PO_TXEN PO_TXER PO_RXD 3 PO_RXD 2 PO_RXD 1 PO_RXD 0 PO_RXDV PO_RXER PO_RXCLK PO_TXCLK PO_CRS PO_COL AN 706 2014 07 17 HPS 12C0 is routed through the FPGA interface and a
9. e V SoC Development Kit Golden System Reference Design User s Manual Compiling Golden Hardware Reference Design Ethernet Media Access Controller I2C Controller alt_iobuff Primitive GSRD Booting Linux Using Prebuilt SD Card Image GSRD Generating and Compiling the Preloader Preloader and U Boot Customization GSRD User Manual Device Tree Generator GSRD User s Manual Getting Started Guides GSRD SD Card RocketBoard website AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 or 2014 07 17 Revision History 21 Revision History a cheas July 2014 2014 07 17 Modified URLs of RocketBoards pages to versioned links e Correctd AN 706 design example URL e Added steps to the Board Setup and Booting Linux from the SD Card section July 2014 2014 07 03 Initial Release AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback
10. emory Mapped Slave JTAG UART Clock Input Reset Input Avalon Memory Mapped Slave Interrupt Sender PIO Parallel 1 0 E e e button_pio_external_connection m ck B dipsw_pio_external_connection B hps_0_f2h_cold_reset_req B hps_0_f2h_debug_reset_reg IClock Input 0 0 0 0 B hps_0_f2h_stm_hw_events B hps_0_f2h_warm_reset_reg pirpe yM lne hps_0_h2f_ reset Conduit B hps_0_hps_io B led_pio_external_connection s H E A hps_0_f2h_cold_reset_r hps_0_f2h_debug_reset hps_0_f2h_warm_reset hps_0_f2h_stm_hw_ev memory hps_0_hps_ io hps_0_h2f_reset Ox0001_ 0x0002_ Ox0001_ T 4 On the Peripheral Pins tab under the Ethernet Media Access Controller section click on the EMAC pin pull down and select FPGA The EMACO0 mode pull down automatically displays Full to indicate GMII mode Select the EMAC1 pin pull down as Unused AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback Altera Corporation AN 706 Generating the Initial HDL in Qsys 2014 07 17 Figure 3 Selecting FPGA for EMACO Pin in the HPS Parameters Window soc_system gt hps_0 Arria V Cyclone V Hard Processor System altera_hps Ethernet Media Access Controller EMAC pin FPGA 5 m EMACO mode er EMAC1 pin Unused sw EMAC 1 mode N A 5 On the Peripheral Pins tab
11. eplace the preloader mkpimage bin u boot img and socfpga dtb in the SD card AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback AN 706 14 Preloader Generation 2014 07 17 Note Information provided regarding SD card changes preloader and Linux software file changes and preloader generation are applicable to this reference design only Preloader Generation Because this design example modifies the default GHRD Qsys file it is essential to re generate the preloader with the preloader generator Related Information GSRD Generating and Compiling the Preloader Refer to this location for information on how to generate and compile the preloader U boot Setup Go to file location u boot socfpga include configs socfpga_cyclone h The EMACO parameters associated with the interface speed must be configured to MII in the socfpga_cyclone h file in the u boot source Change the define for CONFIG_EMAC_BASE and CONFIG_PHY_INTERFACE_MODE to the following define CONFIG_EMAC_BASE CONF IG_EMACO_BASE define CONFIG_PHY_INTERFACE_MODE SOCEFPGA_PHYSEL BENUM_MTI Related Information Preloader and U Boot Customization Refer to this location for information on how to customize u boot Device Tree Setup Generate the device tree EMACO is enabled in the device tree source as shown below and the I2CO0 code source maintains its default settings aliases ethernetO soc ethernet f f700000
12. gin as root at the kernel terminal AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback ee AN 706 16 Sample Application Example 2014 07 17 Figure 9 Kernel Login Example 0 1 ot ol 2 of fo fo fo 619 G G E m a be _ CIM di La OQ f T F Ti i 1 fo J E La LA 1 m a m Ld Lj i La Related Information e GSRD User s Manual Getting Started Guides Refer to this location for information on board setup in the GSRD User s Manual Getting Started Guides e GSRD SD Card Refer to this location for information on updating the SD Card Sample Application Example The default kernel image contains many useful commands and built in tools such as ethtools and mii tools Some examples are illustrated in this section EMAC Test Examples of commands that can be executed on EMACO are gt udhcpc Activate the dhcp server to request an IP address Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 me 2014 07 17 EMAC Test Figure 10 udhcpc Command Output EL j D mMM M fo La ta ta ie H EL gt 1fconfig eth0 Initialize and enable or disable the network interface Figure 11 ifconfig etho Command Output gt ethtool eth0 Display and allow edits to the EMAC device parameters AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corpor
13. her the IP interface is pinned out in the HPS domain or the FPGA domain Peripherals Interface Description HPS Domain FPGA Domain EMAC RGMII Interface GMII Interface QSPI Standard QSPI interface with four Standard QSPI interface with slave select signals four slave select signals achieved by connecting exported signals to bidirectional buffers 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYAN 101 Innovation Drive San Jose CA 95134 2 HPS Per
14. hoose an706_de_pin_assignment tcl and select Run AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface Altera Corporation GJ Send Feedback AN 706 12 Quartus II Pin Assignments 2014 07 17 Figure 7 Selecting pin_assigment tcl in the Tcl Scripts Window TCL Scripts lt pg slscfO7 gt Libraries a Project Open File an 06 de pin assignment tel create ghrd_qsys tcl create ghrd_quartus tcl ghrd_ reset tel ghrd_ se secript tel a ip intr_capturer intr capturer_hw tcl soc system 6 synthesis submodules hps sdram p parameters tel Preview Copyright T 1991 2014 Altera Corporation All rights reserved Your use of Altera Corporation s design tools logic functions and other software and tools and its AMPP partner logic functions and any output files from any of the foregoing including device programming or simulation files and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement the Altera Quartus II License Agreement the Altera MegaCore Function License Agreement or other applicable license agreement including without limitation that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors Please refer to the applicable agreement for further details The an706_de_pi
15. ipherals That Support Routing to the FPGA AN 706 2014 07 17 Peripherals Interface Description HPS Domain SPI Master MOSI MISO SPI interface configu rable to single or dual slaves SPI Slave MOSI MISO SPI interface configu UART IC CAN rable to single or dual slaves Standard UART interface with flow control signals Standard I C interface FPGA Domain MOSI MISO SPI interface with output enables that support up to four slaves interface achieved by connecting exported signals to bidirectional buffers MOSI MISO SPI interface with output enables that support up to four slaves interface achieved by connecting exported signals to bidirectional buffers Standard UART interface with flow control signals including DTR and DSR status and two user defined output signals are also available Standard I C interface achieved by connecting exported signals to a bidirectional buffer Standard CAN interface Standard CAN interface Please refer to the following Cyclone V Device Handbook chapters for descriptions of each peripheral signal interface Related Information Ethernet Media Access Controller Chapter Quad SPI Flash Controller Chapter SPI Controller Chapter UART Controller Chapter I2C Controller Chapter CAN Controller Chapter The CAN interface is only available for Cyclone V devices Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface G send Feed
16. n_assignment tcl script automatically assigns EMACO and I2C0 signal pins to their related FPGA pin location Table 5 Quartus Pin Assignments for EMACO and I2C0O ee enetl rx clk Input PIN Y24 enetl_rx_d 0 Input PIN_AB23 enetl rx _d 1 Input PIN AA24 Sime lies cz Input PIN _AB25 Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 T PR 13 2014 07 17 Hardware Programming File Compilation and Generation o sd eneti_rx_d 3 Input PIN_AE27 enetl_rx_error PIN_AE28 enetl tx clk fb PIN_W25 enet1_tx_d 2 PIN_AA25 enetl tx di3 PIN_AB26 enet1_tx_en PIN_AB22 enetl tx error PIN_AGS enet_dual_resetn PIN _AJl enet_fpga_mdio PIN_H13 Hardware Programming File Compilation and Generation After the Qsys system is set up the top level RTL file updated the related signal pin location assigned and timing constrained the design can be compiled and the SOF programming file generated In Quartus II software navigation bar select Processing gt Start Compilation to generate the SOF programming file SD Card Image Updates Update the default SD card image with the generated preloader binary u boot image file and DTB file following the steps described below 1 With your Linux machine prepare the SD card by following the information in GSRD Booting Linux Using Prebuilt SD Card Image Untar the sd_image bin tar gz file and program the image file sd_ image bin into the SD card 2 R
17. ooting Linux from the SD Card on page 15 Prerequisites This design example is based on the Cyclone V GSRD and tested with Quartus II version 14 0 Refer to the links listed below and review the recommended material before starting with this design example Related Information e Cyclone V SoC Development Kit Refer to this link for Cyclone V SoC Development Kit documentation and installation files e Golden System Reference Design User s Manual Refer to this document and step through the Getting Started Guides Prerequisites and the GHRD Overview In addition review the Development Flow Overview Hardware Requirements The hardware required for this design example is e Cyclone V SoC Development Kit e RJ45 Ethernet cable e SD MMC card preloaded with default GSRD image Software Requirements The software required for this design example is e Quartus II 14 0 and above e SoC EDS 14 0 and above e Factory default hardware template cv_soc_devkit_ghrd in SoC EDS 14 0 Design example files are provided in the AN 706 design example link and are listed in the table below Table 2 Required Software Files ghrd_top v Top level RTL file DOCmS E mmc im mac es cle Timing constraint file an706_de_pin_assignment tcl Pin assignment script file preloader mkpimage bin Generated preloader binary targeted to this project u boot img Modified u boot image for EMACO socfpga dtb Modified device tree for EMACO and I2C0 Altera Corporation AN 706 Mapping H
18. scroll down to the I2C Controllers section click on the I2C0 pin pull down and select FPGA The I2C0 mode pull down automatically displays Full Figure 4 Selecting FPGA for I2CO Pin in the HPS Parameters Window i nE soc_system gt hps_0 Arria V Cyclone V Hard Processor System i altera _hps 3 12C0 pin pce 12C0 mode Full v l 12C1 pin es m 12C1 mode NA 12C2 pin al 12C2 mode N A 12C3 pin m 12C3 mode NA l 6 Return to the System Contents tab and in the Export column double click on the EMAC0 and I2C0 signal pins to export them as conduits Altera Corporation AN 706 Mapping HPS IP Peripheral Signals to the FPGA Interface GJ Send Feedback AN 706 i T 7 2014 07 17 Generating the Initial HDL in Qsys Figure 5 Exporting Pins in System Contents Window e T T Description Clock E hps 0 Arria V Cydone V Hard Processor System f2h_cold_reset_req Reset Input f2h_debug_reset_req Reset Input f2h_warm_reset_req Reset Input f2h_stm_hw_events onduit I KNIPA GXSE f2h_axi_dock f2h_axi_slave h2f _Iw_axi_dock h2f_lw_axi_master AXI Master f2h_irq0 Interrupt Receiver f2h_irqi Interrupt Receiver E hps_only_master JTAG to Avalon Master Bridge Clock Input Reset Input Avalon Memory Mapped Master Reset Output 7 Select Generate gt Generate HDL from the Qsys menu bar In the project directory replace the top level RTL file ghrd_top v with the generated
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