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Hardware Development Guide for i.MX 6SoloLite

1. Clock Root Default Frequency MHz ARM_CLK_ROOT 792 PERCLK_CLK_ROOT 66 AHB_CLK_ROOT 132 IPG_CLK_ROOT 66 MMDC_CLK_ROOT 396 USDHCn_CLK_ROOT 198 SSIn_CLK_ROOT 63 5 OCRAM_CLK_ROOT 264 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 4 1 Using the Clock Connectivity Table Table 4 1 Clock roots continued Clock Root Default Frequency MHz CSI_CORE_CLK_ROOT 4 8 LCDIF_AXI_CLK_ROOT 264 ACLK_EIM_SLOW_CLK_ROOT 264 GPU2D_OVG_CORE_CLK_ROOT 528 GPU2D_CORE_CLK_ROOT 528 PXP_AXI_CLK_ROOT 87 3 EPDC_AXI_CLK_ROOT 87 3 LCDIF_PIX_CLK_ROOT 180 EPDC_PIX_CLK_ROOT 56 5 SPDIFO_CLK_ROOT 30 SPDIF1_CLK_ROOT 30 EXTERN_AUDIO_CLK_ROOT 30 ECSPI_CLK_ROOT 4 UART_CLK_ROOT 4 i During the power up sequence and u boot operation the core operates at 396 MHz Freescale s Linux kernel changes the frequency to 996 MHz when the OS becomes operational 4 2 Waking the core up from stop mode The following modules can wake the core up from stop mode e ECSPI e EIM e EPIT e GPC e GPIO e GPT e PC e KPP e SDMA e UART e USB Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Chapter 5 Using the IOMUX Design Aid This chapter provides users with the basic information required to use the IOMUX system design aid IOMux exe The IOMUX design aid
2. Figure 2 4 i MX6SL fanout example bottom view Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 3 i MX 6 Series Layout Recommendations The colors signify the following e Top layer Red etch Yellow pad Gray vias e Bottom layer Blue etch 2 1 2 Placing decoupling capacitors The fanout scheme creates a four quadrant structure that facilitates the placement of decoupling bulk capacitors on the bottom side of the PCB The 0201 decoupling and 0603 bulk capacitors should be mounted as close as possible to the power vias The distance should be less than 50 mils Additional bulk capacitors can be placed near the edge of the BGA via array Placing the decoupling capacitors close to the power balls is critical to minimize inductance and ensure high speed transient current demand by the processor A correct via size is critical for preserving adequate routing space The recommended geometry for the via pads is pad size 18 mils and drill 8 mils The following list provides the main recommendations for choosing the correct decoupling scheme for the i MX6 family boards e Place the largest capacitance in the smallest package that budget and manufacturing can support e For high speed bypassing select the required capacitance with the smallest package for example 0 22 uF and package 0201 e Minimize trace length inductance to small caps e Series indu
3. Freescale Semiconductor 2 27 i MX 6 Series Layout Recommendations Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 28 Freescale Semiconductor Chapter 3 Requirements for Power Management 3 1 Power management requirements overview e This chapter provides the power requirements for the following i MX 6SoloLite 3 1 1 Voltage domains overview The chip have several voltage domains that may need to be supplied with different voltages depending on system needs The chip internal regulators and its complementary PMIC PF0100 provide a complete and simple way to supply each voltage domain with different voltages when needed Section 3 4 Connection diagrams shows the internal regulators and the connections to PF0100 3 1 2 PF0100 overview PF0100 consists of the following components used to supply the 1 MX6 voltage domains as well as other blocks on the system e 4 buck regulators e 1 boost regulator e 8 LDOs The default PF0100 power up sequence is programmed to fit the requirements of the i MX 6 series families of processors However the PF0100 can be adjusted to meet the specific requirements for system applications by using the one time programmable OTP feature 3 2 Requirements for a generic interface between chip and PF0100 Table 3 1 shows the generic interface between the chip and PF0100 using a suitable power up sequence For more info about PF0100 functionality and the i MX 6SL p
4. Figure 2 16 Internal L3 DDR3 routing Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 13 i MX 6 Series Layout Recommendations ae PPR Figure 2 19 Internal L10 DDR3 routing Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 14 Freescale Semiconductor i MX 6 Series Layout Recommendations Figure 2 20 Bottom layer DDR3 routing The following table shows the total etch of the signals for the byte 0 and byte 1 groups The layout is an example using 2000 mils for the clock Table 2 5 Total signal etch DDR3 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Signals Length Mils DRAM_DO 990 27 DRAM_D1 983 71 DRAM_D2 984 54 DRAM_D3 985 65 DRAM_D4 989 39 DRAM_D5 983 84 DRAM_D6 981 65 DRAM_D7 980 52 DRAM_DQMO 1028 62 DRAM_SDQSO 1042 41 DRAM_SDQS0_B 1045 87 DRAM_D8 971 98 Freescale Semiconductor 2 15 i MX 6 Series Layout Recommendations 2 5 7 Table 2 5 Total signal etch DDR3 continued Signals Length Mils DRAM_D9 963 04 DRAM_D10 963 54 DRAM_D11 962 21 DRAM_D12 963 61 DRAM_D13 947 47 DRAM_D14 962 43 DRAM_D15 963 43 DRAM_DQM1 1034 17 DRAM_SDQS1 1026 07 DRAM_SDQS1_B 1010 68 DRAM_SDCLKO 1908 54 DRAM_SDCLKO_B 1903 28 LPDDR2 FBGA 168 routing example The figures in th
5. Falling Waveform Far Test Load Yes Defines a test load network and its associated electrical parameters for reference by golden waveforms under the Test Data keyword If Test_load_type is Differential the test load is a pair of the circuits shown in If the R_diff_near or R_diff_far subparameter is used a resistor is connected between the near or far nodes of the two circuits If Test_load_type is Single_ended R_diff_near and R_diff_far are ignored 8 5 Freescale naming conventions for model names and usage in i MX6 IBIS file The model names are defined per each Model selector The models may differ from each other by having different parameters such as voltage drive strength mode of operation and slew rate The mode of operation drive strength and slew rate parameters are programmable by software 8 5 1 Model Selector ddr The ddr model type supports the DDR protocol signals 8 5 1 1 DDR Model Selector ddr models exist for DDR3 DDR3L DDR3U and LPDDR2 protocols This model has the following parameters e DDR protocol e DDR IO type e Drive strength e ODT enable disable The IBIS model name is composed from the parameters values in two ways as follows e Without active ODT circuit lt ddr protocol gt _sel lt ddr_type gt _ds lt drive_strength gt _mio e With active ODT circuit lt ddr protocol gt odt_t lt ODT value gt _sel lt ddr_type gt _mi Hardware Development Gui
6. parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address freescale com SalesTermsandConditions Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners ARM is the registered trademark of ARM Limited 2013 Freescale Semiconductor Inc a pre pra So a a ARM C E oz Z freescale
7. ppm Ethernet 50 USB2 0 500 1 8 Unused analog interfaces Table 1 15 shows the recommended connections for unused analog interfaces see Table 1 10 recommendation 2 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 1 14 Freescale Semiconductor Design Checklist Table 1 15 Recommended connections for unused analog interfaces Module Contact name Recommendations if unused CCM CLK1_N CLK1_P Float USB USB_H1_DN USB_H1_DP USB_H1_VBUS USB_OTG_CHD _B Float USB_OTG_DN USB_OTG_DP USB_OTG_VBUS Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Design Checklist Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 1 16 Freescale Semiconductor Chapter 2 i MX 6 Series Layout Recommendations This chapter provides recommendations to assist design engineers with the correct layout of their i MX 6 series based system The majority of the chapter discusses the implementation of the DDR interface but it also provides recommendation for power the USB reference resistors ESD and related emissions This chapter uses the IMX6SLEVK board as its reference for illustrating the key concepts See the IMX6SLEVK board layout files as a companion to this chapter 2 1 Basic design recommendations The 1 MX 6SoloLite processor comes in a 13 x 13 mm package with 0 5 mm ball pitch The bal
8. 1 Each LDO voltage rail can be adjusted through LDO registers See the i MX 6SoloLite Applications Processors for Consumer Products data sheet IMX6SLCEC and the Power Management Unit PMU chapter of the i MX 6SoloLite Applications Processor Reference Manual IMX6SLRM for more details Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Requirements for Power Management 3 4 Connection diagrams Figure 3 1 i MX6SL PF0100 Connections Diagram 1 of 2 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 3 4 Freescale Semiconductor Requirements for Power Management PFUZE 100 Other Blocks in System DDR sD SW4 or VGEN4 Audio T Ethernet g y VGENS USB_OTG2_VBUS USB Connector USB_OTG1_VBUS D LDO3P0 vopuss_cap _ Notei Note 1 4 I2Cx_SCL SCL I2Cx_SDA T soa PWR_ON_REQ Kon Pore f ReseTemcu PMIC_STBY_REQ f stanpay GRQ Fine 1 GPIO I O logic level is configurable to either 3 3 V or 1 8 V after power up Pull up voltage has to be chosen accordingly Figure 3 2 i MX6SL PF0100 Connections Diagram 2 of 2 3 5 Video power recommendations VDD_PU_CAP is the supply for the internal graphic processing units GPU For graphic intensive operations the GPU requires a lot of power and may undergo large swings of instantaneous current requirements Therefore the power sup
9. HOL yozzany zeva svia 8 zqWAx yoaan NDMO WLX o zoqDeuu0D m OXO43Y LNI 43N3 OND aN 99 Zoro 8 1NI 13N3 PL ae spra zepun N zo isu pu 3x prTnoys oz _ ea ustym suetd ano SO a COAH a ag amiet sist ee msme F AOL sinesga oo 430938 1037 aa dna pE uia ayo sikeDaa 22 suacdad N xe ii 2g RS Tia N XL N3 X19034 Lox Tox 934 axa ee XH oaxt 544 zaqgow Ad SHO Ss Aq SHO_934 LaGOW LOXY boxy O34 owqowoaxy oagxy 934 m NXL oan PEME E EI ia oan 4 o1aw 934 dX Ss d XL te 8 S S to S oo Zoro 99 090 499 090 4909 E090 909 090 GND o 66v 66v eer eer Zory sovy sory vores sory _nst not sLABOa4 lenusieyip xu pue x1 toes desMisg podeatip SuL E n e a i E Sie o ANKO NOL ANOS sno papoau Se proua Ee N Pozo Sozo z020 tozo 397E090 JenuasayIp Xu Pue XL e UIUAIM SUIBU J 39843 aul stae O34 v AHOOZL ssblepadiui OhsnspePus Qao p pu aj6uls wyoos e pue ssuepadul jenuaJayjip a I wyooot pz yam pagno aq pinoys saed YIP Xy pue XL SUL T siaeOa4 stad a V shacds4 SSLON LNOAVT qeuzteyurd Toazquop zemM0g TNS uma Tans ei K oaoa 9 uo Teast yStH 29 Zoro Ob Lva bors z p er enoa eoe gt FHS so sikeDa4 ZMS H IHAAA STEA Freescale Semiconductor Figure 11 2 Reference schematic part 2 of 2 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 11 2 Using the FEC Interface Figure 11 2 provides a reference schematic which shows the connections requ
10. RTC_XTALI can be driven DC coupled with RTC_XTALO floated or driven with a complimentary signal The voltage level of this driving clock should not exceed the voltage of VDD_SNVS_CAP and the frequency should be lt 100 kHz under typical conditions Do not exceed VDD_SNVS_CAP or damage malfunction may occur The RTC_XTALI signal should not be driven if the VDD_SNVS_CAP supply is off This can lead to damage or malfunction For RTC_XTALI VIL and VIH voltage levels see the latest i MX 6 series datasheet Note that if this external clock is stopped the internal ring oscillator starts automatically 3 Loose tolerance 40 kHz oscillator An on chip loose tolerance ring oscillator is available of approximately 40 kHz If RTC_XTALLI is tied to GND and RTC_XTALO is floating the on chip oscillator is automatically engaged When a high accuracy real time clock is not required the system may use the on chip 40 kHz oscillator The tolerance is 50 The ring oscillator starts faster than an external crystal and is used until the external crystal reaches stable oscillation The ring oscillator also starts automatically if no clock is detected at RTC_XTALI at any time 4 Precision 24 MHz oscillator Connect a fundamental mode crystal between XTALI and XTALO An 80 Q typical ESR crystal rated for a maximum drive level of 250 uW is acceptable Alternately a 50 Q typical ESR crystal rated for a maximum drive level of 200 uW may be used
11. Review the switch or value with a second analog switch Alternately device data sheet for operating specifications peripheral devices with three state outputs may be used ensure the output is high impedance during the boot up interval 3 The BOOT_CFG signals are required for proper See the System Boot chapter in your chip reference functionality and operation and should not be left manual for the correct boot configuration Note that an floating incorrect setting may result from an improper booting sequence Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 1 2 Freescale Semiconductor Table 1 3 Boot mode input Design Checklist recommendations Checkbox Recommendation Explanation supplemental recommendation 1 For BOOT_MODE1 and BOOT_MODEDO use one of the following options to achieve logic 0 e Tie to GND through any size external resistor e Tie directly to GND e Float For logic 1 use one of the following e Tie directly to the VDD_SNVS_IN rail Tie to the VDD_SNVS_IN rail through an external resistor 10 kQ A value of 4 7 kQ is preferred in high noise environments If switch control is desired no external pulldown resistors are necessary Simply connect SPST switches directly to the VDD_SNVS_IN rail If desired a 4 7 KQ to 10 kQ series resistor can be used when current drain is critical Boot inputs BOOT_MODE1 and BOOT_MODEO each
12. VT information For more details see Section 8 4 2 VT information Test Data Rising Waveform Near Rising Waveform Far Falling Waveform Near Falling Waveform Far Test Load VT golden model information For more details see Section 8 4 3 Golden Model VT information Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Understanding the IBIS Model 8 4 1 IV information IV information is composed of four Current over Voltage tables Pullup Pulldown GND_ clamp and Power_clamp Each look up table describes a different part of the IO cell model as shown in Table 8 1 Pullup POWER Clamp Reference Reference POWER Pullup Clamp Pulldown Pulldown GND Clamp Reference Reference Figure 8 1 Model IV parameters structure 8 4 2 VT information The following table defines the keywords that provide the information about an output or I O buffer and Example 8 3 shows what they look like in an IBIS file Table 8 4 Ramp and waveform keywords Keyword Required Comment Ramp Yes Basic ramp rate information given as a dV dt_r for rising edges and dV dt_f for falling edges see the following equation dV _ __ 20 to 80 voltage swing dt time taken to swing above voltage Note The dV value is the 20 to 80 voltage swing of the buffer when driving into the specified load R_load for Ramp this
13. are generally preferred to Ramp for the following reasons e VT data may be provided under a variety of loads and termination voltages e VT tables may be used to describe transition data for devices as they turn on and turn off e Ramp effectively averages the transitions of the device without providing any details on the shapes of the transitions themselves All detail of the transition ledges would be lost The VT data should be included under two Rising Waveform and two Falling Waveform sections each containing data tables for a Vcc connected load and a Ground connected load although other loading combinations are permitted The most appropriate load is a resistive value corresponding to the impedance of the system transmission lines the buffer will drive own impedance For example a buffer intended for use in a 60 Q system is best modeled using a 60 Q load R_ fixture Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 8 6 Freescale Semiconductor The following figure shows how to interpret the model data Understanding the IBIS Model eI down GND clamp Power clamp Pulldown eI up GND clamp Power clamp Pullup eI recvr GND clamp Power clamp Power Clamp Enable Logic Package l Circuit Pulldown _ Pulldown V t v I GND Clamp J C_comp Figure 8 2 Model data interpretation 8 4 3 Golden Model VT in
14. have on chip pulldown devices with a nominal value of 100 kQ a projected minimum of 60 kQ and a projected maximum of 140 kQ Be aware that when these are logic high current is drawn from the VDD_SNVS supply In production when on chip fuses determine the boot configuration both boot mode inputs can be no connects Table 1 4 12C recom mendations Checkbox Recommendation Explanation supplemental recommendation 1 Verify the target 12C interface clock rates The bus can only operate as fast as the slowest peripheral on the bus If faster operation is required move the slow devices to another I C port 2 Verify that the target 12C address range is supported and does no conflict with other peripherals If there is an unavoidable address conflict move the offending device to another I2C port These chips support up to Three I2C ports for the i MX 6SoloLite If it is undesirable to move a conflicting device to another 12C port review the peripheral operation to see if it supports remapping the address 3 Do not place more than one set of pullup resistors on This can result in excessive loading Good design the 12C lines practice is to place one pair of pullups only Table 1 5 JTAG recommendations Checkbox Recommendation Explanation supplemental recommendation 1 Do not use external pullup or pulldown resistors on JTAG_TDO JTAG_TDO is configured w
15. 3V to Vout 1 0V and back 10us rise and 10us fall for any Voyz and for any lLoap 1MA lt lLoaD lt ILoapmax Output noise 10Hz 10MHz 10mV maximum Startup Voltage ramp up time Min ramp rate 0 1V us Max total ramp time 1ms 7 9 Checking for clock pitfalls Problems with the external clocks are another common source of board bring up issues Ensure that all of your clock sources are running as expected The XTALI XTALO and the RTC_XTALI RTC_XTALO clocks are the main clock sources for 24 MHz and 32 kHz reference clocks respectively on the i MX6 Although not required the use of low jitter external oscillators to feed CLK1_P N or CLK2_P N on the i MX6 can be an advantage if low jitter or special frequency clock sources are required by modules driven by CLK1_P N or CLK2_P N See the CCM chapter in your i MX6 chip reference manual for details If a 32 768 kHz crystal is not connected to the i MX6 an on chip ring oscillator is automatically used for the low frequency clock source When checking crystal frequencies use an active probe to avoid excessive loading A parasitic probe typically inhibits the 32 768 kHz and 24 MHz oscillators from starting up Use the following guidelines e RTC _XTALI clock is running at 32 768 kHz can be generated internally or applied externally e XTALI XTALO is running at 24 MHz used for the PLL reference e CLK1 P N can be used as oscillator inputs for low jitter special fre
16. KEY_c m DQ 20 of 197 muxed pins in use Status Bar 0 conflicts a e a Figure 5 1 IOMUX tool for the i MX6 families of applications processors Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 5 1 Using the IOMUX Design Aid 5 1 Application requirements The IOMUX application requires that the following be installed e Microsoft Windows XP or newer e Microsoft s NET Framework NET Framework to 4 0 or newer 5 2 lIOMUX tool version The IOMUX application 7 MX 6SoloLite IOMux Tool v3 3 or later supports the i MX 6SoloLite 5 3 IOMUX tool location To obtain the IOMUX tool for the chip consult your Freescale sales representative or download the IOMUX tool from www freescale com Note that the IOMUX tool must be version v3 3 or later 5 4 Learning to use the IOMUX tool Consult the IOMUX user s manual file inside the package for a detailed walkthrough of how to use the IOMUX tool Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 5 2 Freescale Semiconductor Chapter 6 Configuring JTAG Tools This chapter explains how to configure JTAG tools for debugging The JTAG module is a standard JEDEC debug peripheral It provides debug access to important hardware blocks such as the ARM processor and the system bus which can give users access and control over the entire chip To prevent JTAG manipulation while allowing access
17. Layout Recommendations Limited spacing between vias Figure 2 24 Poor GND plane 2 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 20 Freescale Semiconductor i MX 6 Series Layout Recommendations Spacing the vias some mils apart facilitates the GND copper flowing in the plane The following figures show good practices of ground planes Increasing space between vias improve flow GND layer Figure 2 25 Good layout GND plane detail Figure 2 26 Good layout GND plane detail Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 21 i MX 6 Series Layout Recommendations 2 6 DDR power recommendations for DDR3 only The following recommendations apply to the VREF POV75_REFDDR voltage reference plane Use 30 mils trace between decoupling cap and destination Maintain a 25 mils clearance from other nets Isolate VREF and or shield with ground Decouple using distributed 0 22 uF capacitors by the regulator controller and devices Place one 1 0 uF near the source of VREF one near the VREF pin on the controller and two between the controller and the devices The following recommendations apply to the VTT DDR_VTT voltage reference plane The figures are examples from the evaluation board for the VTT reference schematic Place the VTT island on the component side layer at the end of the bus behind the DRAM devices U
18. Processor Rev 1 Freescale Semiconductor Design Checklist Table 1 6 Power and decouple recommendations Checkbox Recommendation Explanation supplemental recommendation 1 Comply with the power up sequence guidelines as described in the data sheet to guarantee reliable operation of the device Any deviation from these sequences may result in the following situations e Excessive current during power up phase e Prevention of the device from booting e Irreversible damage to the processor worst case scenario 2 Do not overload coin cell backup power rail VDD_SNVS_IN Note that the following I Os are associated with VDD_SNVS_IN most inputs have on chip pull resistors and do not require external resistors e POR_B on chip pullup see Table 1 8 1 e ONOFF on chip pullup see Table 1 8 2 BOOT_MODEO on chip pulldown see Table 1 3 1 BOOT_MODE 1 on chip pulldown see Table 1 3 1 e TAMPER on chip pulldown e PMIC_STBY_REQ push pull output e PMIC_ON_REQ push pull output TEST_MODE on chip pulldown see Table 1 10 1 Freescale PMIC PMPF0100 VSNVS regulator is rated to supply 400 pA output current under worst case operating conditions The VDD_SNVS_IN regulator can supply larger current in transient situations without damaging the regulator Concerning i MX6 e When VDD_SNVS_IN VDD_HIGH_IN SNVS domain current is drawn from both equally e When
19. Rev Yes The revision level of this file The specification contains guidelines for assigning revision levels Date No Date this file was created Source No The source of the data in this file Data is taken from a simulation and validated on the board Notes No Component or file specific notes Disclaimer No May be legally required Copyright No The file s copyright notice Example 8 1 Header Information IBIS Ver 4 2 Comment Char char File Name mx6sl_416mapbgal3x13 consmr ibs File Rev 02 Date Mon Jul 23 12 12 30 2012 Source iolib cln401lp io35u50dgo7m5x0ylz wb _ 1 2p4 IBIS 1 2p6 RLC MB0432 1313 050e 01 16FEB2012 Notes FSL Viper 2012 01 31 8 3 Component and pin information The second section of an IBIS file is where the data book information regarding the component s pinout pin to buffer mapping and the package and pin electrical parameters is placed The following table explains the component and pin information notation and Example 8 2 shows what it looks like in an IBIS file Table 8 2 Component and Pin Information Keyword Required Comment Component Yes The name of the component being modeled Standard practice has been to use the industry standard part designation Note that IBIS files may contain multiple Component descriptions Manufacturer Yes The name of the component manufacturer Hardware Development Guide for i MX 6SoloLite Application
20. VCC BT_CFG OE C187 C186 0 1UF 0 1UF 0402_CC 0402_CG 16V 16V GND GND sws SW DIP 8 s A Bus isolation Ta u21 vec B3 20K 0402 oC H BT CFSo o LCD_DATO Sor ano ive OD TDAT2 YA 20K 0402 CC E BT CFGS 1v3 LCD_DAT3 326 20K 0402 CC BT CFG4 R32 20K_0402 CC ao Tae RSA 20K 0402 CC B BS LCD DATE R3 20K 0402 CC BT CFG7 aa RLCD DAT GND io 7aLVCZAPW GND u23 VCC_BT_CFG_OE vec H2 BT CFG8 140 1Yo 18 R3 pE a s LCD_DAT8 11 101 ie FE ne CD_DAT9 1g 1N2 Tag Ra 7K 002 CC ee 1A3 1Y8 LCD_DATI1 10E 2vo Hg 2 LOD_DAT12 20K_0402 M 2V1 by ic LCD DATIS ay 2Y2 DATIS Bg 20K 0402 CC 2y3 gt SE me CE CD_DATI5 end He 7aLVC2APW GND u24 VCG_BT_CFG_OE vec B353 20K_0402_ CC 2 1A0 1Y0 LCD_DATi6 ar I th y os A 1A2 1Y2 m 1 R38 20K 0402 CC oot en 1A3 13 LCD_DAT19 l q 10E R360 20K 0402 CC BT_CFG28 17 3 R361 4 7K __ 0402 CC SINET CLI BT CFG29 ae Par BSR x LCD_DAT21 AA 0402 CG BT CFO E E peed os 4 7K__0402 CC LCD DAT22 BS a i o lt 5 ES E k a Rags 20K 0402 CC _ BT _CFG31 a Se 4 7K 0402 CC LCD_DATos 10 GND GND 7ALVC244APW Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 N Figure 1 1 Boot control for development mode 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 14 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 6 11 1 10 Freescale Semiconductor Design Checklist 1 4 DDR ref
21. VDD_HIGH_IN gt VDD_SNVS_IN VDD_HIGH_IN supplies all SNVS domain current and current flows into VDD_SNVS_IN to charge a coin cell battery e When VDD_SNVS_IN gt VDD_HIGH_IN VDD_SNVS_IN supplies current to SNVS and some current flows into VDD_HIGH_IN Note VDD_HIGH_IN must be valid above the internal detector threshold for the current flow to occur Thus current flow only happens when VDD_HIGH_IN is powered to a level below VDD_SNVS_IN If VDD_HIGH_IN is off or low no extra current is drawn from VDD_SNVS_IN The whole circuit assumes it is charging a coin cell and starts charging when VDD_HIGH_IN is valid If you are driving VDD_SNVS_IN with a non battery power source it must be at the same level as VDD_HIGH_IN or current will flow between them e When VDD_SNVS_IN is not powered by a battery it is recommended that VDD_SNVS_IN VDD_HIGH_IN If VDD_SNVS_IN is tied to a battery the battery eventually discharges to a value equal to that of VDD_HIGH_IN and never subsequently charges above VDD_HIGH_IN The battery chemistry may add restrictions to VDD_HIGH_IN s voltage range External charging components should be based on the battery manufacturer s specifications Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 5 Design Checklist Table 1 6 Power and decouple recommendations continued Checkbox Recommendation Explanation supplemental recommendat
22. a few words and verify if they can be read correctly 3 If not recheck the DDR initialization sequence and whether the DDR has been correctly soldered onto the board It is also recommended that users recheck the schematic to ensure that the DDR memory has been connected to the i MX6 correctly Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 20 Freescale Semiconductor Chapter 8 Understanding the IBIS Model This chapter explains how to use the IBIS input output buffer information specification model which is an Electronic Industries Alliance standard for the electronic behavioral specifications of integrated circuit input output analog characteristics The model is generated in ASCII text format and consists of multiple tables that capture current vs voltage IV and voltage vs time VT characteristics of each buffer IBIS models are generally used to perform PCB board level signal integrity SI simulations and timing analyses The IBIS model s features are as follows e Supports fast chip package board simulation with SPICE level accuracy and faster than any transistor level model e Provides the following for portable model data I O buffers series elements terminators Package RLC parasitics Electrical board description 8 1 IBIS structure and content An IBIS file contains the data required to model a component s input output and I O buffers behaviorally in A
23. for manufacturing tests and software debugging the i MX 6SL series processor incorporates a secure JTAG controller for regulating JTAG access The secure JTAG controller provides four different JTAG security modes which are selected by e Fuse configuration For more information about the security modes see the Security section in the System JTAG Controller SJC chapter of the chip reference manual 6 1 JTAG tool requirements To use JTAG tools your system must have the following e Windows based PC e RVDS v4 1 package or newer e RealView ICE box connected to your computer Freescale recommends making the JTAG port accessible during platform initial validation bring up and for software debugging It is accessible in all development kits from Freescale Multiple tools are available for accessing the JTAG port for tests and software debugging Freescale recommends use of the ARM JTAG tools for compatibility with the ARM core However the JTAG chain as described in the following sections should work with non ARM JTAG tools For more information about configuring non ARM tools contact the third party tool vendor for support 6 2 Extra JTAG functionality Additional CoreSight debug components such as trace machines using DS 5 debug software and DSTREAMER hardware can be used for extra JTAG functionality However they are not mandatory for a basic configuration and are beyond the scope of this document NOTE There is no option
24. load defaults to 50 For CMOS drivers or I O buffers this load is assumed to be connected to the voltages defined by the Voltage Range keyword for falling edges and to ground for rising edges Rising Waveform No The actual rising low to high transition waveform provided as a VT table Falling Waveform No The actual falling high to low transition waveform provided as a VT table Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 5 Understanding the IBIS Model Example 8 3 Ramp and waveform keywords example Ramp variable typ min max daV dt_r 0 4627 0 3456n 0 4326 0 4568n 0 4962 0 3030n dv dt_f 0 4546 0 3481n 0 4272 0 3918n 0 4774 0 3569n R_load 0 2400k l Rising Waveform R_fixture 0 2400k V_fixture 0 0 V_fixture min 0 0 V_fixture max 0 0 time V typ V min V max 0 0S 0 3369uV 12 4052uV 41 7335nV 19 7866fS 0 6730uV 12 7375uV 0 3823uvV 20 8863fS 0 6917uV 12 7519uV 0 4013uvV 21 9489fS 0 7058uV 12 7657uV 0 4196uV Falling Waveform R_fixture 0 2400k V_fixture 0 0 V_fixture min 0 0 V_fixture max 0 0 time V typ V min V max l 10 0S On T ELEV 0 7211V 0 8270V 0 3334nS 0 7711V 0 7211V 0 8270V 0 3445nS 0 7711V 0 7211V 0 8269V The Ramp keyword is always required even if the Rising Waveform and Falling Waveform keywords are used However the VT tables under Rising Waveform and Falling Waveform
25. routing technique e DDR controller provides address mirroring when using two chip selects which aids address line routing for memories on both sides of board e Bus termination resistors are required Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 9 i MX 6 Series Layout Recommendations 2 5 4 2 Gigabyte recommendations The 512 Mbyte option has four memories You should follow these recommendations for best practice e Have a balanced routing for the T connection e Avoid having many layer transitions e Do not cross split reference planes during the routing The following figure shows the topology for the ADDR CMD CTRL signals It has a tree topology Note the balanced T routing i MX6SL Figure 2 9 ADDR CMD CTRL signal topology The routing for the data groups depends on the bus size The following figure shows the point to point data bus connection with routing by byte group 2 Bytes Group Figure 2 10 Point to point data bus connection routing by byte group NOTE i MX 6Solo only uses the first two pairs of the 2 Bytes groups All others are disabled 2 5 5 1 Gigabyte recommendations The following diagrams show the 1 Gbyte recommendations using both chip selects CS 1 0 and loading 512 Mbytes to each one This option has eight memories and requires the addition of a termination resistor Hardware Development Guide for i MX 6SoloLite Application
26. 00 4 NVCC33_I0 SW2 3 15 2 PF0100 2 NVCC18_1O VGEN4 1 8 0 35 PF0100 3 NVCC_1P2V VGEN1 1 2 0 1 PF0100 4 1 These voltage domains are supplied by i MX6 internal regulators The following table shows the PF0100 regulators that are available to supply the rest of the system circuitry for an i MX6SL interface Table 3 2 PF0100 regulators for other system circuitry i MX6SL Suppl Output voltage Step size Maximum load current rey V mV mA SW4 0 5 x SW3A_OUT 0 4 3 3 25 50 1000 VGEN2 0 8 1 55 50 250 VGEN3 1 8 3 3 100 100 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Requirements for Power Management Table 3 2 PF0100 regulators for other system circuitry i MX6SL continued Suppl Output voltage Step size Maximum load current PPY V mV mA VGEN5 1 8 3 3 100 100 VGEN6 1 8 3 3 100 200 3 3 1 MX6 internal regulators These chips have been equipped with 7 internal regulators that simplify the power supply scheme of the system The following table shows the regulators power requirements See Section 3 4 Connection diagrams for the distribution and connections of these LDOs Table 3 3 Internal regulator power requirements LDO Output voltage V LDO_ARM 1 1 LDO_SOC 1 2 LDO_PU 1 1 LDO_2P5 2 5 LDO_1P1 1 1 LDO_SNVS 1 1 LDO_USB 3 0
27. 0kohm pull up N A 100kohm pull up The PMIC_RDY WDOG _B and WDOG_RST_B DEB pins are programmable and can powered from either the NVCC33_IO or NVCC_LOW domains They will be powered from the NVCC33_IO domain by default See Table 7 8 Table 7 8 NVCC33_IO domain signals NVCC33_1O Parameter WDOG B Supply Domain Power NVCC33_I10 I O Voltage Range V 0 3 to NVCC33_IO 0 3 Min High level Input Voltage Viy min N A Max Low level Input Voltage Vi_ max N A High level Output Driver Impedance 50 250 ohms drive strength setting dependent Low level Output Driver Impedance 50 250 ohms drive strength setting dependent Active State Low I O type open drain or CMOS output programmable Internal Pull device Optional 100kohm pull up 7 5 Watchdog Reset Behavior When a watchdog time out reset event occurs and the processor asserts WDOG _B the PMIC should immediately assert the POR_B signal and execute the power down sequence However it is desirable to keep the VDD_SNVS_IN and 32k external clock powered up and running This can be useful for the processor to retain its RTC value and also to retain the captured AXI bus traffic in the SNVS domain When restarting the POR_B should continue to be asserted until the power up sequence in figure 2 is completed In some cases it may be desired that only the POR_B be asserted to reset the processor with all the processor rails remaining powered when a wa
28. 1 Output a specific set of addresses and controls to pins connected to the ROM 2 Perform a read command and scan out the values of the ROM data pins 3 Compare the values read with the known golden values Based on this procedure the tool can determine whether the interface between the two parts is connected properly and does not contain shorts or opens 10 3 Downloading the BSDL file The BSDL file for each i MX processor is stored on the Freescale website upon product release Contact your local sales office or fields applications engineer to check the availability of information prior to product releases 10 4 Pin coverage of BSDL Each pin is defined as a port within the BSDL file You can open the file with a text editor like Wordpad to review how each pin will function The BSDL file defines these functions as shown PORT DESCRIPTION TERMS in input only out three state output 0 Z 1 buffer two state output 0 1 inout bidirectional linkage OTHER vdd vss analog Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 10 1 Using BSDL for Board level Testing The appearance of linkage in a pin s file implies that the pin cannot be used with boundary scan These are usually power pins or analog pins that cannot be defined with a digital logic state 10 5 Boundary scan operation The boundary scan operation is control
29. 643 2F 128 386 7188 30 160 309 375 31 192 257 8125 32 224 220 9821 33 256 193 3594 34 320 154 6875 35 384 128 9063 36 448 110 4911 37 512 96 67969 38 640 77 34375 39 768 64 45313 3A 896 55 24554 3B 1024 48 33984 3C 1280 38 67188 3D 1536 32 22656 3E 1792 27 62277 3F 2048 24 16992 1 Shaded cells indicate frequency is outside of the range that guarantees operation Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Design Checklist 1 6 JTAG signal termination The following table is a JTAG termination chart see recommendations in Table 1 5 Table 1 13 JTAG interface summary JTAG signal I O type On chip termination External termination JTAG_TCK Input 47 kQ pullup Not required can use 10 kQ pullup JTAG_TMS Input 47 kQ pullup Not required can use 10 kQ pullup JTAG_TDI Input 47 kQ pullup Not required can use 10 kQ pullup JTAG_TDO 3 state output Keeper Do not use pullup or pulldown JTAG_TRSTB Input 47 kQ pullup Not required can use 10 kQ pullup JTAG_MOD Input 100 kQ pullup Use 1 kQ pulldown or tie to GND 1 7 Oscillator tolerance The following table provides 24 MHz oscillator tolerance guidelines see Table 1 7 recommendations 4 and 5 Because these are guidelines the designer must verify all tolerances per the official specifications Table 1 14 24 MHz crystal tolerance guidelines Interface Tolerance
30. AP SB_OTG1_VBUS LDO_USB j SB_OTG2_VBUS aR GND Figure 7 1 i MX 6SoloLite system on chip power block diagram 7 1 2 Table 7 1 shows the preliminary maximum supply requirements for each power rail from the PMIC into the power supply inputs of the i MX6Sololite SoC Maximum supply requirements Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 2 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 1 Maximum current supply requirements Power Supply Rail Suggested Max Current Requirement Comments 1 2V rail gt VDD_SOC_IN 1 95A VDD_PU_IN VDD_ARM_IN 2 8V 3 6V rail gt NVCC33_IO 300mA Requirement for MX6Sololite SoC only VDD_HIGH_IN Analog does not include external device The max current may differ according to the switching speed capacitive loading and number of GPIOs used for NVCC33_10 1 8V rail gt NVCC18_1O 125mA Requirement for MX6Sololite SoC only does not include external devices The max current may differ according to the switching speed capacitive loading and number of GPIOs used for NVCC18_ 10 1 2V rail LPDDR2 gt NVCC_DRAM 200mA Requirement for MX6Sololite SoC only does not include DRAM IC 5 0V gt USB VBUS 60mA Requirement for MX6Sololite SoC only does not include additional external USB loads 7 1 3 Internal LDO description The 1 MX6Sololite internal power system consists of 7 LDOs Ea
31. AP VDD_SNVS_IN domain may pull higher current In order to prevent in rush current slow ramp rate is recommended for VDD _SNVS_IN Assuming 0 22 uF attached to VDD_ SNVS_CAP with low trace capacitance and load capacitance 0 5 V ms ramp rate or slower is recommended 7 2 3 Power down sequence Before powering down the power rails the PMIC should assert POR_B When powering down the power rails the power down sequence order in table 3 4 should be followed The POR_B signal power rails and 32K external clock power down sequence should be done in the reverse order of figure 2 Each power rail should be turned off and discharged to ground by the PMIC with an impedance of approximately 50 100 ohms Each power rail should be turned off and discharged to at least 10 of its initial value until before turning off and discharging the next power rail The PMIC should also ensure the external 32 768kHz clock is turned off before turning off the VDD_SNVS_IN supply 7 2 4 Power up sequence in low voltage system design Oni MX6SL NVCC33_IO voltage rail is selected as the default logic level for all dual voltage GPIO pads If the pads are connected to 3V logic level external peripheral this poses no issue However some systems are designed to operate with external ICs and components at 1 8V logic levels If the majority of the dual voltage I Os are connected to ICs powers up to 1 8V logic level operation following power up sequence should be considered Ha
32. DDR PHY and associated jack Jack and CODEC input Bluetooth or other RF and antenna Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 25 i MX 6 Series Layout Recommendations 2 12 Reducing skew and phase problems in deferential pairs traces Differential pair technology has evolved to require more stringent checking in the area of phase control This is evident on the higher data rates associated with parallel buses such as DDR or Ethernet In the simplest of terms Diff Pair technology sends opposite and equal signals down a pair of traces Keeping these opposite signals in phase is essential to assuring that they function as intended Figure 2 31 and Figure 2 32 show two examples of static routing where a match is achieved without needing to tune one element of the differential pair Figure 2 31 Yellow traces diff pairs 1 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 26 Freescale Semiconductor i MX 6 Series Layout Recommendations The following figure shows the addition of a delay trace to one element of the differential pair to avoid length mismatch which reduces skew and phase problems The green box marks the detail Figure 2 32 Small bumps added to the shorter differential pair Having this delay reduces skew and phase problems Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1
33. DP USB_OTG2_DN NOTE In rev3 of the i MX6 IBIS some of the above unsupported pins are described as GPIO cells These are no more than placeholders and cannot be used for signal modeling 8 6 Quality assurance for the IBIS models The IBIS models are validated against the IBIS specification which provides a way to objectively measure the correlation of model simulation results with reference transistor level spice simulation or measurements Correlation The process of making a quantitative comparison between two sets of I O buffer characterization data such as lab measurement vs structural simulation or behavioral simulation vs structural simulation Correlation Level A means for categorizing I O buffer characterization data based on how much the modeling engineer knows about the processing conditions of a sample component and which correlation metric he or she used All models GPIO DDR MLB have passed the following checks e IBISCHK without errors or unexplained warnings e Data for basic simulation checked Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 11 Understanding the IBIS Model e Data for timing analysis checked e Data for power analysis checked e Correlated against Spice simulations Validation reports can be provided upon demand 8 7 IBIS usage Freescale board designers used the 1i MX6SL IBIS model with the Hyperlynx tool by Me
34. DRAM_D 31 0 efo Q 3 1 0 DRAM_CS 1 0 px CS DRAM_SDCLK 1 0 DRAM CKIC CKW1 SDCLK_1 SDCLK_1_B DRAM_SDWE lt cimm gt WE Figure 2 6 Connection between i MX 6SoloLite and DDR3 i MX6SL LPDDR2 JEDEC PoP DRAM_A 9 0 tt 9 0 DRAM_D 31 0 1 Q 3 1 0 DRAM_CS 1 0 p CS DRAM_SDCLK 1 0 DRAM gt CKIC CKW1 SDCLK_1 SDCLK_1_B Figure 2 7 i MX 6SoloLite and LPDDR2 The LPDDR2 interface is one of the most critical interfaces for chip routing It must have the controlled impedance for the single ended traces be equal to 50 Q and for the differential pairs be equal to 100 Q The following figure shows the physical connection scheme for both top and bottom placement of the DDR chips showing the final placement of the LPDDR2 memory and the decoupling capacitors The red elements show the top layer and the blue elements show the bottom layer It is very important to place the Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 6 Freescale Semiconductor i MX 6 Series Layout Recommendations memory as close to the processor as possible to reduce trace capacitance and keep the propagation delay to the minimum Follow the reference board layout as a guideline for memory placement and routing Figure 2 8 Final placement of memories and decoupling capacitors 2 4 DDR routing rules DDR3 LPDDR2 routing can be accomplished in two different ways routing all signal
35. Hardware Development Guide for i MX 6SoloLite Applications Processors IMX6SLHDG Rev 1 06 2013 e Po ose Ps freescale Contents Paragraph Number Title Chapter 1 Design Checklist 1 1 Design checklist Ovenvie Wiacuse saccade acatesciedieonceaataaceantuanaemanemauaimaes 1 2 Design check list tables 2 4014 cco Ws aeventp aon hacer teen eee eee 1 3 BUS is lation CITOUIE e cascaviscctandaearsdeiacdidsrsducheasediaghiaateagshelaceasseoriceo R ARE E 1 4 DDR reference citctit sessen datas aad sind Mani aiak 1 5 PC clock speed and division factors IFDR c ccesceeseeeseeesseeeteceteeeeeeeeseeees 1 6 JTAG signal termination seis coc aeenests seeks oduaae sti aseas Vavancast oiaceoucteeys obese ean 1 7 Oscillatet tolerates issiro aren n E tier ernst ana a a ahgaes 1 8 Un sed analog mterface Snir ernaria niia Eiaa E E iE Ai mates Chapter 2 i MX 6 Series Layout Recommendations 2 1 Basic design FECOMMICHOAONS 1 sccncoecerssasyec eosdovetesnse deeeeesaedetessursundasvnceooenees 2 1 1 Fanout ill str tions esner aro eiri iia a date tangy trios nee aks 2 1 2 Placing decoupling capacitors s sesssseseeseesseesseseessressessessrssessessessresseesees 22 Stackup recommendations ss csseissfesedeccuasdecavs tested eathe segue senrdacteasesouonteguess 2 3 DDR connection information sessessesessseessesesseessessresresseesesressteseesersseesseserst 2 4 DDR TOUN TES i e A e N a ease N 2 5 Routing considerations sssses
36. MUX tool sessessssessesesssesseserssressessesrrssressessrssressessrssresseeseeseessee 5 2 Chapter 6 Configuring JTAG Tools 6 1 JIA G tool r g irements isi nsan oaan one cate aa A AR anata E R R 6 1 6 2 Extr JTAG f ctonalityo ie enni a a e E EE EARE E E RE EE eae 6 1 6 3 Updating your RealView ICE tcc scvsec si avn dckeca benders unaed tnge dcaaas anes ous eubectunenanausateamauees 6 2 6 4 Defining th JTAG chaf Fst yess oes a a ds caesavanscnesneblv ot wad ems R Seeeevelaarss 6 3 6 5 Reading a register with Real View Debugger V4 1 0 0 cceececcceeseceseceeeceeseecsseceseeneeeeeseeens 6 6 6 6 CoreSight Base address references 0233 5 sesseass tescielessexteauseai eas cask nseahoectaatimm detest 6 8 Chapter 7 Avoiding Board Bring up Problems 7 1 Power SYStEM OVERVIEW indiat a a o a aaa a a ea 7 1 7 1 1 Block di graMeeeoi tan SO pa a a e e EY a a a a Ee a h 7 1 7 1 2 Maximum supply requirements cccecscccsseceseceesceeseecseceeeeesseecsuecnseeneeeeeseeeaecneenaes 7 2 Hardware Development Guide for i MX 6SoloLite Applications Processors Rev 1 2 Freescale Semiconductor Paragraph Number 7 1 3 7 2 7 2 1 7 2 2 1 2 3 7 2 4 7 3 7 4 TS 7 6 e 7 8 7 9 7 10 7 11 8 1 8 2 8 3 8 4 8 4 1 8 4 2 8 4 3 8 5 8 5 1 8 5 1 1 8 5 2 8 5 3 8 5 4 8 6 8 7 8 8 9 1 9 2 Contents Page Title Number Internal DO deseription enire anna a a Condes Aa Ra aa 7 3 Power SEQUCI CIN sss praan aanta oaea E bend
37. MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Avoiding Board Bring up Problems Tek Single Seq op OOKS S SW1A B VDDARM_IN 43 SW1C VDDSOC_IN SW2 VGEN2 System 1 5V Jalap a Soos cht te Figure 7 6 Power up sequence example 2 7 11 Sample board bring up checklist 15 53 03 800mV 17 Feb 2012 Table 7 14 provides a sample board bring up checklist Note that the checklist incorporates the recommendations described in the previous sections Blank cells should be filled in during bring up as appropriate Table 7 14 Board bring up checklist Checklist Item Details Owner Findings amp status Note The following items must be completed serially 1 Perform a visual inspection Check major components to make sure nothing has been misplaced or rotated before applying power 2 Verify all i MX6 voltage rails Confirm that the voltages match the data sheet s requirements Be sure to check voltages not only at the voltage source but also as close to the i MX6 as possible like on a bypass capacitor This reveals any IR drops on the board that will cause issues later Note Ideally all of the i MX6 voltage rails should be checked but VDD_ARM_IN and VDD_SOC_INare particularly important voltages These are the core logic voltages and must fall within the parameters provided in the i MX6 data sheet VDD_SNVS_IN NVCC_JTAG a
38. NCES Aires avisuriea steed ude Aue wteans wand ner ee a Aaa Ae 9 2 Chapter 10 Using BSDL for Board level Testing 10 1 S td 0 Bean a5 Gd on eee NERC Pree tro eN eT eRe A Cre etn aera ee re reer 10 1 10 2 How BS DE functions sssini a cs datos a aa a a aatia aat 10 1 10 3 Downloading the BSDL Mle scicnissiedscycshs wuladcucstianlinaraaharauiedduciieaine 10 1 10 4 Pin coverage Of BS Dic chisel iiaa state ine nie emt de E a anon E OS 10 1 10 5 Boundary scan operation ator scence tes ctset ce seaeush ce aan odcatsa ns Shae ae sesech cece tay deaaos aad aaa 10 2 10 6 O pin power Considerations ieceis 2 cease tics cele eis eateue etter eta 10 2 Chapter 11 Using the FEC Interface 11 1 VEIT Waen Sciacca a ec Nia ie a else ca 11 1 11 2 Configuring the FEC signal connections ccccceseceseceesceescecseeceeceeeeenseecaecneeeeeeensees 11 1 11 3 Generating the reference ClOC kg caeden cies sass cheanauee cadin iuaiuuad amass nchatee lecedauvseecacsneiteas 11 3 11 4 Generating the reference clock on chip vis5 c2 se2hsasebcansxadoasiacessaedluctonsapacessaeiacasarataatetancds 11 3 11 5 Using ancexternal Clock csicasty citesactest tects ch suit isahuctasdvawsdiiactavieds Gash a a 11 3 Appendix A Development Platforms Appendix B Revision History Hardware Development Guide for i MX 6SoloLite Applications Processors Rev 1 4 Freescale Semiconductor Chapter 1 Design Checklist 1 1 Design checklist overview This chapter provides a desi
39. PIO 24 ALT3 CSIODAT10 M1 RI F23 EIM_EB3 ALT3 3 300V WEIM_SEC gpio2_GP1O 31 ALT1 SD3DAT7 F13 RTS G20 EIM_D20 ALT4 3 300V WEIM_SEC gpio3_GPIO 20 F uart2 4 of 4 RXD_MUX M3 CSIO_DAT11 ALT3 3 300V IPU_CSI gpioS_GPIO 29 gt M cts ALT4 EIM_D TXD_MUX M1 CSIO_DAT10 ALT3 3 300V IPU_CSI io5_GPIO 28 E RTS AT DSa A 7 RXD_MUX ALT4 EIM_D CTS G23 EIM_D28 ALT4 3 300V WEIM_SEC gpio3_GPIO 28 4 RTS J19 EIM_D29 ALT4 3 300V WEIM_SEC gpio3_GPIO 29 ALT4 EIMD26 E24 RXD_MUX E25 EIM_D27 ALT4 3 300V WEIM_SEC gpio3_GPIO 27 2 Signal E TXD_MUX E24 EIM_D26 ALT4 3 300V WEIM_SEC io3_GPIO 26 Connected to U12 auxiliary console O soler 13 MiMi A a a Selection 519 Y unz _ Pane CTS J20 EIM_D30 ALT4 3 300V WEIM_SEC gpio3_GPIO 30 gt CTs Aira cdi RTS H21 EIM_D31 ALT4 3 300V WEIM_SEC gpio3_GPIO 31 gt BITS aac RXD_MUX E16 SD4_CLK ALT2 1 800V NANDF gpio7 _GPIO 10 gt iBT XD MUN ALT2 spaci TXD_MUX B17 SD4_CMD ALT2 1 800V NANDF apio POPI O CTS 13 CSIO_DAT17 ALT3 3 300V IPU_CSI gpio6_GPIO 3 ALT2 SDACMD 817 RTS L4 CSIO_DAT16 ALT3 3 300V IPU_CSI gpio6 _GPIO 2 7 uart4 4 of 4 RXD_MUX V6 KEY ROWO ALTA 0 000V GPIO gpio4_GPIO 7 F CTS ALT3 CSI0 0 TXD_MUX WS KEY_COLO ALTA 0 000V GPIO gpio4_GPIO 6 7 RTS ALT3 CSIO_D b Z RXD_MUX ALTA KEY RG F ALT4 KEYCOLO W5 ALT3 CSIODAT12 M2 E uart5 gt E cTs ALTA KEY RC gt E RTS ALT4
40. Package variable typ min max R_pkg 0 1820888 0 0062144 0 424531 L pkg 2 33166nH 0 07436nH 4 98212nH C_ pkg 4 85350pF 0 58625pF 52 4327pF Pin signal name model name R_pin L pin Cipin Al GND GND NA NA NA A2 DRAM SDQS3_B ddr 0 274507 2 93233nH 0 87287pF A3 DRAM D24 ddr 0 308072 3 38497nH 0 82353pF Pin Mapping pulldown_ref pullup_ref Al GND NC A2 GND NC A3 GND NC Diff Pin inv_pin vdiff tdelay typ tdelay min tdelay max B3 A2 NA NA NA NA F1 F2 NA NA NA NA L1 M1 NA NA NA NA Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 3 Understanding the IBIS Model 8 4 Model information The Model keyword starts the description of the data for a particular buffer Table 8 3 shows the main sets of parameters and keywords composing the model definition Table 8 3 Model information Keyword Comment Model Spec General set of parameters for the model simulation Receiver Thresholds Threshold information for the different simulation cases Temperature Range The temperature range over which the min typ and max IV and switching data have been gathered Voltage Range Pulldown Pullup GND_clamp POWER_clamp The range over which Vcc is varied to obtain the min typ and max pullup and power clamp data IV information For more details see Section 8 4 1 IV information Ramp Rising Waveform Falling Waveform
41. R1 14 ENET_CLK_SEL 1 FEC_TX_CLK ANATOP REF_CLK Figure 11 5 Clock supplied by Ethernet PHY Input at FEC_TX_CLK pin Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 11 4 Freescale Semiconductor Appendix A Development Platforms This appendix provides a complete list of the development platforms that are available from Freescale to support the i MX 6SoloLite processor You can use these tables as a quick guide for finding the best development platform for your needs Note that although these development platforms are based on a specific product family they will work with any of the 1 MX product families listed above Table A 1 EVK Board for Smart Devices Version i MX used i MX 6SoloLite Schematic PN and Rev 170 27452 e 1 Gbyte LPDDR2 e SPI Nor e eMMC Socket SD Card Socket e Port of CSI CMOS Sensor camera e Parallel Display Port e TouchScreen Audio CODEC e Ethernet 3 Axis Accelerometer e Aux SDIO Socket e Mini PCle only USB port connection supported e EPDC support via EPD daughter board Dual display support via EPD daughter board and LCD daughter board Features Quick Start Guide Available at www freescale com 6SLEVK on the Freescale website Schematic Available at www freescale com 6SLEVK on the Freescale website Layout Available at www freescale com 6SLEVK on the Freescale website Hardware Development Guide for i MX 6SoloLit
42. S power domains proportional to the voltage difference Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Design Checklist Table 1 7 Oscillator and clock recommendations Checkbox Recommendation Explanation supplemental recommendation 1 Precision 32 768 kHz oscillator Connect a crystal between RTC_XTALI and RTC_XTALO Choose a crystal with a maximum of 100 kQ ESR equivalent series resistance and follow the manufacturer s recommendation for loading capacitance Do not use an external biasing resistor because the bias circuit is on chip The capacitors implemented on either side of the crystal are about twice the crystal load capacitance To hit the target oscillation frequency board capacitors need to be reduced to compensate for board and chip parasitic capacitance typically 15 16 pF is employed The integrated oscillation amplifier has an on chip self biasing scheme but is high impedance relatively weak to minimize power consumption Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground gt 100 MQ as this negatively affects the amplifier bias and causes a reduction of startup margin Use short traces between the crystal and the processor with a ground plane under the crystal load capacitors and associated traces 2 External kilohertz source If feeding an external clock into the device
43. SCII format The basic IBIS file contains the following data e Header information regarding the model file e Information about the component the package s electrical characteristics and the pin to buffer model mapping in other words which pins are connected to which buffer models e The data required to model each unique input output and I O buffer design on the component IBIS models are component centric meaning they allow users to model an entire component rather than only a particular buffer Therefore in addition to the electrical characteristics of a component s buffers an IBIS file includes the component s pin to buffer mapping and the electrical parameters of the component s package Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 1 Understanding the IBIS Model 8 2 Header Information The first section of an IBIS file provides the basic information about the file and its data The following table explains the header information notation Example 8 1 shows what header information looks like in an IBIS file Table 8 1 Header Information Keyword Required Description IBIS Ver Yes Version of IBIS Specification this file uses Comment char No Change the comment character Defaults to the pipe character File Name Yes Name of this file All file names must be lower case The file name extension for an IBIS file is ibs File
44. See the engineering bulletin EB830 for additional options Freescale BSP software requires 24 MHz on this clock This clock is used as a reference for USB so there are strict frequency tolerance and jitter requirements See Table 1 14 for guidelines See the crystal oscillator XTALOSC reference manual chapter and relevant interface specification chapters for details To access a calculator for the 24 MHz crystal drive level see EB830 on the i MX Community 5 External megahertz source If feeding an external clock into the device XTALI can be driven DC coupled with XTALO floated For XTALI VIL and VIH voltage levels see the latest i MX 6 series datasheet This clock is used as a reference for USB PCle and SATA so there are strict frequency tolerance and jitter requirements See Table 1 14 for guidelines See the crystal oscillator CTALOSC reference manual chapter and relevant interface specification chapters for details Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 7 Design Checklist Table 1 7 Oscillator and clock recommendations continued Checkbox Recommendation Explanation supplemental recommendation 6 CLK1_P CLK1_N is LVDS input output differential pair compatible with TIA EIA 644 standard The frequency range is 0 to 600 MHz Alternatively a single ended signal can be used to drive a CLK1_P input In this case t
45. U_IN DD_SOC_IN POR_B TIME SLOT Ai Blt A Al cl Al cl AL CI A CI A C A CI A Di Figure 7 2 Startup Timing Diagram LDO Bypass NOTE VDD_ARM_IN VDD_PU_IN add VDD_SOC_IN can startup at the same However VDD_ARM_IN and VDD_PU_IN must be at their target values within Ims of VDD_SOC_IN Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 4 Startup timing diagram parameters Time Slot Description Timing Requirement A Ramp time for each rail from OV to the target voltage Max total ramp time 1ms B The 32k clock from the PMIC can begin clocking the processor as soon At least one 32k clock cycle as VDD_SNVS_IN reaches its target voltage The PMIC should then wait until at least one 32k clock cycle has completed before ramping the remaining rails C Time between previous rail reaching its target value and next rail The next power rail can begin ramping beginning to ramp as soon as the previous rail reaches its target value No max time requirement D Time between last rail reaching target value and de asserting POR_B POR_B can be de asserted as soon as power on reset the final rail reaches its target value No max time requirement 7 2 2 VDD_SNVS_IN power up ramp rate During power up if VDD_SNVS_IN s ramp rate is significantly faster than the ramp rate seen at VDD_SNVS_C
46. _STBY_ REQ PMIC_ON_ REQ PMIC_RDY WDOG_B and WDOG_RST_B_ DEB Table 7 6 provides a description of each of the signals Table 7 6 PMIC handshaking signal descriptions Signal Name Signal Description POR_B This signal is an input only pin and is active low When asserted it will reset the processor The processor will remain in reset until the POR_B is de asserted The pads for this signal are powered from VDD_SNVS_IN so VDD_SNVS_IN must be present for this pin to function POR_B must be asserted for a least one 32k clock cycle 30us for the processor to qualify it as valid PMIC_STBY_REQ This output signal is active high When asserted the processor is requesting the PMIC to configure the power rails to place the system into a low power standby mode When de asserted the PMIC should exit low power standby mode The pads for this signal are powered from VDD_SNVS_IN so VDD_SNVS_IN must be present for this pin to function PMIC_ON_REQ This output signal is active high When de asserted the processor is requesting the PMIC to turn the system off When asserted the PMIC should bring the system out of off mode The pads for this signal are powered from VDD_SNVS_IN so VDD_SNVS_IN must be enabled for this pin to function WDOG_B This is one of the watchdog output signals from the processor This signal gets asserted low for either of the following two conditions 1 Software write to WDA bit of Watchdog Contro
47. ains the rules for routing the signals by byte group Table 2 3 DDR3 LPDDR2 routing by byte group Length Chip signals Group Recommendations Min Max DRAM_SDCLK 1 0 Clock Short as possible 2 25 inches Match the signals 5 mils DRAM_SDCLK_B 1 0 2 25 inches is recommended DRAM_A 15 0 Address Clock min 200 Clock min Match the signals 25 mils DRAM_SDBA 2 0 and Command DRAM_RAS DRAM_CAS DRAM_SDWE DRAM_D 7 0 Byte Group 1 Clock min Match the signals of each byte group 25 DRAM_DQMO mils DRAM_SDQS0 Match the differential signals of DQS 10 DRAM_SDQS0_B mils DRAM_D 15 8 Byte Group 2 Clock min DRAM_DQM1 DRAM_SDQS1 DRAM_SDQS1_B DRAM_D 23 16 Byte Group 3 Clock min DRAM_DQM2 DRAM_SDQS2 DRAM_SDQS2_B DRAM_D 31 24 Byte Group 4 Clock min DRAM_DQM3 DRAM_SDQS 3 0 DRAM_SDQSJ3 0 _B DRAM_CS 1 0 Control signals Clock min 200 Clock min Match the signals 50 mils DRAM_SDCKE 1 0 DRAM_SDODT 1 0 1 Clock min The shortest length of the clock group signals because this group has a 5 mil matching tolerance Finally the impedance for the signals should be 50 Q for single ended and 100 Q for differential pairs Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 8 Freescale Semiconductor i MX 6 Series Layout Recommendations 2 5 Routing considerations The chip can handle u
48. ale Semiconductor Chapter 11 Using the FEC Interface 11 1 Overview This chapter provides supporting instructions for the use of the i MX 6 series SLFast Ethernet Controller FEC interface NOTE This chapter only covers the required hardware and register settings Modifications to the Ethernet driver or its initialization code are beyond its scope For this information see your BSP documentation 11 2 Configuring the FEC signal connections Audio UART FEC U1D ECSPI1_SCLK ECSPI1_MOS ECSPI1_MISO ECSPI1_SSO ECSPI2_SCLK ECSPI2_MOSI ECSPI2_MISO ECSPI2_SS0 FEC_MDIO FEC_TX CLK FEC_RX_ER FEC_CRS_DV FEC_RXD1 FEC_TXDO FEC_MDC FEC_RXDO FEC_TX EN FEC_TXD1 FEC_REF_CLK Primary Use 12 12 10 10 10 10 10 3G Card Enable 3G Card Reset 14 14 4 6 11 4 6 11 6 10 11 6 10 11 8 8 8 8 8 9 11USB_5V_HOST Over current Flag 3 11 Charger Ok Status 3 11 Charger fault status 3 11 Charging status 15 15 10 15 15 1 15 15 15 15 15 Ethernet power enable Headphone detect Figure 11 1 Reference schematic part 1 of 2 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Using the FEC Interface ND OND aTnezep maa oxo uddw AHa aco ast rer ied 20 Zoro Soo a x K noa o 9
49. banaeetents 8 2 Component and pin information sssesseessessesseeseessessesstesresstesessresseeseesersseessesressresseser 8 2 Mod l mformatigt orero a ER E E T TAE 8 4 IV information ser e a a a vi aces r ada fe tees aE 8 5 VT information esearon ts eip eE E EEE A AAE 8 5 Golden Model VT information ss seseseesseseeseeeseessessrsseessessrssressessrssresseestesresresseesess 8 7 Freescale naming conventions for model names and usage in i MX6 IBIS file 8 8 Model Selector ddr nn E E EE EEE E E E O 8 8 DDR Model Sle Clan lt 2 catcsccccoteescasgiticatatcedetdueacrace cass aadestacavinscarseneaeeoete seas 8 8 MIGdel Selector O16 acess soinck esa a ah earl ee tak nema etna 8 10 Model Selecter WIS a cook eens deunateadseon acid aeieaa A aN AS 8 10 List of pins not modeled in the i MX6 IBIS file eee ceeceeeteeeeteeeteeeeeeeeseees 8 11 Quality assurance for the IBIS models pci cssaddcvacsdvewadealsaessienssabensvinreatinasacdiavndend 8 11 MESS BS AS aia cca E aac oa ay sec os aise ge Saino N as oe wa Bo as Cen AE A 8 12 ReferehceS ann ee AE ee ns eo a A a Ge Ne Deans aes he 8 12 Chapter 9 Using the Manufacturing Tool CVT LC Woy seo aes ea g a ge oe ia ea Oi eit cea ek hat ne aa 9 1 Feature s mmary eea eiea ata ae dace a E a sec a aaen 9 1 Hardware Development Guide for i MX 6SoloLite Applications Processors Rev 1 Freescale Semiconductor 3 Contents Paragraph Page Number Title Number 9 3 Other TEHCTE
50. cent Connections Cortex A9 O RVI connected 5 0x020E0220 Cortex A9 O RVI_1 0 4 8 0x00000005 DPx00000005 0x00000005 S 0x020E022c 0x00000005 0x00000005 Ox00000005 S 0x020E0238 0x00000005 0x00000005 Ox00000005 S 0x020E0244 9x00000005 0x00000005 0x00000005 S 0x020E0250 9x00000005 0x00000005 Ox00000005 S 0x020E025c 0x00000005 0x00000005 0x00000005 S 0x020E0268 9x00000005 0x00000005 Ox00000005 S 0x020E0274 0x00000005 0x00000005 0x00000005 5 0x020E0280 9x00000005 0x00000005 0x00000005 S 0x020E028C 9x00000005 0x00000005 Ox00000005 S 0x020E0298 9x00000005 0x00000005 Ox00000005 S 0x020E02A4 9x00000005 0x00000005 0x00000005 S 0x020E02BO 0x00000005 0x00000005 0x00000010 S 0x020E02BC 9x00000000 0x00000000 0x00000000 S 0x020E02C8 9x00000000 0x00000000 Ox00000005 S 0x020E02D4 9x00000005 0x00000005 Ox00000005 S 0x020E02E0 9x00000005 0x00000005 0x00000005 S 0x020E02EC 9x00000005 0x00000005 Ox00000005 anannanmnn O2D000000 O220D 000000 Ds DDO0000 lt 5 O0x00000EEE gt lt Unknown Location gt lt 5 0x00000C30 gt lt Unknown Location gt Figure 6 8 Accessing a register Figure 6 8 shows an example of using the Real View Debugger to access the IOMUX register IOMUXC SW MUX CTL PAD GPIO 0 whose address is 0x020E0220 and whose default value after reset is 0x5 6 6 CoreSight Base address references The CoreSight base address is as fo
51. ch LDO is described in Table 7 2 Table 7 2 Internal LDO descriptions LDO Name Description LDO_ARM Sources the power to the ARM core LDO_PU Sources the power to the graphics processor blocks LDO_SOC Sources power to the rest of the SoC gates LDO_2P5 Provides 2 5V power to the chip serial interfaces PLLs and DRAM pre drivers LDO_1P1 Provides power to the PLL digital circuitry LDO_SNVS This is a low power LDO which supplies the low power 1 1V to the 32kHz RTC and other SNVS circuitry LDO_USB Powers the on chip USB blocks Also handles the 5V power muxing when two 5V sources are present Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 3 Avoiding Board Bring up Problems 7 2 Power sequencing Table 7 3 shows the power up and power down sequence orders Two cases are shown Using the i MX6Sololite internal supplies non bypass and bypassing the internal LDO Low Drop Out linear regulator supplies Table 7 3 Power sequence Power Rail Name Using all internal LDOs Internal LDOs Bypassed Comments Power Up Power Down Power Up Power Down VDD_SNVS_IN 1 6 1 9 VDD_HIGH_IN 4 3 2 8 NVCC33_10 NVCC_HIGH VDD_HIGH_CAP_ Powered internally Powered internally 3 7 NVCC18_10 5 2 4 6 NVCC_LOW NVCC_PLL Powered internally Powered internally 5 5 NVCC_DRAM_IN 6 1 6 4 VDD_ARM_IN 2 5 7 3 For bypass mode DC
52. connectors make sure the ground plane clearouts around each pin have ground continuity between all pins e Maintain the parallelism skew matched between DP and DM these traces should be the same overall length e Do not route DP and DM traces under oscillators or parallel to clock traces and or data buses e Minimize the lengths of high speed signals that run parallel to the DP and DM pair e Keep DP and DM traces as short as possible e Route DP and DM signals with a minimum amount of corners Use 45 degree turns instead of 90 degree turns e Avoid layer changes vias on DP and DM signals Do not create stubs or branches 2 8 Impedance signal recommendations Use the following table as a reference when you are updating or creating constraints in your software PCB tool to set up the impedance and the correct trace width Table 2 7 Impedance signal recommendations Layout Signal Group Impedance Tolerance All signals unless specified 50 Q SE 10 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 23 i MX 6 Series Layout Recommendations Table 2 7 Impedance signal recommendations continued E p Seje Ja se e i 46 e et o S t 6 Q la gis g 2 o E gt Qa Ss o o T g c O 2 a a a D cC pom oO p 3 h W E 2 nO gt 25 5 Sa m G 7 tQ D NAO The following figure shows the dimen
53. ctance cancels out capacitance e Tie caps to GND plane directly with a via e Place capacitors close to the power contact of the associate package designed from the schematic The MCIMX6SLEVK CPU uses the preferred BGA power decoupling design Note that the layout is available through www freescale com Customers should use the reference design strategy for power and decoupling 2 2 Stackup recommendations High speed design requires a good stackup in order have the right impedance for the critical traces The constraints for the trace width may depend on a number of factors such as the board stackup and associated dielectric and copper thickness required impedance and required current for power traces The Freescale reference design uses a minimum trace width of 3 mils for the DDR routing The stackup also determines the constraints for routing and spacing Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 4 Freescale Semiconductor i MX 6 Series Layout Recommendations Consider the following when designing the stackup and selecting the material for your board Board stack up is critical for high speed signal quality You must preplan impedance of critical traces High speed signals must have reference planes on adjacent layers to minimize cross talk FSL reference design equals Isola 370HR FSL validation boards equals Isola FR408 The recommended stackup is 6 layers with the layer stack as sh
54. d on each signal line connecting to an external cable These ferrite beads must be placed as close to the PCB jack as possible NOTE Ferrite beads should have a minimum impedance of 500 Q at 100 MHz with the exception of the ferrite on USB_5V Ferrite beads should NOT be placed on the USB D D signal lines as this can cause USB signal integrity problems For radiated emissions problems due to USB a common mode choke may be placed on the D D signal lines However in most cases it should not be required if the PCB layout is satisfactory Ideally the common mode choke should be approved for high speed USB use or tested thoroughly to verify there are no signal integrity issues created It is highly recommended that ESD protection devices be used on ports connecting to external connectors See the IMX6SLEVK available on the Freescale website for detailed information about ESD protection implementation on the USB interfaces If possible stitch all around the board with vias with 100 mils spacing between them connected to GND planes with exposed solder mask to improve EMI Component placement recommendations Adhere to the following recommendations when placing components Place components such that short and or critical routes can be easily laid out Critical routes determine component location Orient devices to facilitate routes minimize length and crossovers Consider placing the following pairings adjacent i MX and
55. d resulting PC CLK frequencies are indicated in the table below Resulting frequencies will vary according to the PERCLK CLK ROOT frequencies selected Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 11 Design Checklist Table 1 12 assumes PERCLK CLK ROOT 49 5MHz Table 1 12 IFDR IFDR Division factor Frequency kHz 0 30 1650 1 32 1546 875 2 36 1375 3 42 1178 571 4 48 1031 25 5 52 951 9231 6 60 825 7 72 687 5 8 80 618 75 9 88 562 5 A 104 475 9615 B 128 386 7188 C 144 343 75 D 160 309 375 E 192 257 8125 F 240 206 25 10 288 171 875 11 320 154 6875 12 384 128 9063 13 480 103 125 14 576 85 9375 15 640 77 34375 16 768 64 45313 17 960 51 5625 18 1152 42 96875 19 1280 38 67188 1A 1536 32 22656 1B 1920 25 78125 1C 2304 21 48438 1D 2560 19 33594 1E 3072 16 11328 1F 3840 12 89063 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Table 1 12 IFDR continued Design Checklist 20 22 2250 21 24 2062 5 22 26 1903 846 23 28 1767 857 24 32 1546 875 25 36 1375 26 40 1237 5 27 44 1125 28 48 1031 25 29 56 883 9286 2A 64 173 4375 2B 72 687 5 2C 80 618 75 2D 96 515 625 2E 112 441 9
56. de for i MX 6SoloLite Applications Processor Rev 1 6 2 Freescale Semiconductor Configuring JTAG Tools 2 Install update You are going to install release 4 3 0 build 1 The release currently installed is 4 3 0 build 1 RealView ICE DSTREAM Fimware v4 3 This firmware update adds functionality for Preliminary support for Cortex A15 Support for debug of SMP Cortex platforms Extended platform support Figure 6 2 Install update window 6 RVI automatically reboots 7 Upon reconnecting to the RVI you should see version number 4 3 0 build 1 or a later version number The exact version name should match with the version number installed in step 4 see the following figure 2 RVI Update RVI1 RealView ICE 4 3 Templates Description RealView ICE Firmware Figure 6 3 RVI window after reconnecting 6 4 Defining the JTAG chain To define the JTAG chain for an ARM Cortex A9 based chip perform the following steps 1 Find Freescale imx6 SL rvs at the following location my Documents ARM rvconfig platformFiles NOTE Be sure to use this path exactly or the tool chain configuration will not be available from the Debugger Connect to Target Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 6 3 Configuring JTAG Tools ee soy Contact your sales representative or go to www freescale com to obtain your copy of the Freescale imx6 su rv
57. de for i MX 6SoloLite Applications Processor Rev 1 8 8 Freescale Semiconductor Understanding the IBIS Model DDR write models _ mio suffix have no simulated ODT as ODT is disabled during write Write models DS parameter is meaningful and changes to describe the different levels of drive strength DDR read models _mi suffix have no meaningful DS parameter as no driving happens during read Read models ODT parameter is meaningful and changes to describe different levels of ODT impedance Selected according to the used DDR DDR IO voltage level is selected accordingly Controlled by the IOMUXC_SW_ PAD CTL GRP DDR_TYPE 19 18 register in IOMUXC IOMUX controller DDR_SEL bits to select between DDR3 amp DDR Protocol DDR IO Type Drive strength ODT value LPDDR2 Controlled by bits 5 3 DSE of the following registers in IOMUXC IOMUX controller IOMUXC_SW_PAD CTL PAD DRAM SDCLK x 2 registers IOMUXC_SW_ PAD CTL PAD DRAM CAS IOMUXC_SW PAD CTL PAD DRAM RAS IOMUXC_SW_ PAD CTL PAD GRP ADDDS IOMUXC_SW_PAD CTL PAD DRAM RESET IOMUXC_SW_ PAD CTL PAD DRAM SDCKEx 2 registers IOMUXC_SW_ PAD CTL PAD DRAM SDODTx 2 registers IOMUXC_ SW _ PAD CTL PAD GRP CTLDS IOMUXC_SW_ PAD CTL PAD DRAM SDQSx 8 registers IOMUXC_SW PAD CTL PAD DRAM BxDS 8 registers IOMUXC_SW_ PAD CTL PAD DRAM DQM x 8 registers Controlled by bits 18 16 14 12 10 8 and 6 4 in MPODTCTRL register o
58. e Applications Processor Rev 1 Freescale Semiconductor A 1 Development Platforms Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 A 2 Freescale Semiconductor Appendix B Revision History Table B provides a revision history for this document Table B 1 Document Revision History Rev f Number Date Substantive Change s 1 6 2013 Update to comments in Table 7 3 regarding bypass mode 0 4 2013 Initial release Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor BB 1 How to Reach Us Home Page freescale com Web Support freescale com support Document Number IMX6SLHDG Rev 1 06 2013 Information in this document is provided solely to enable system and software implementers to use Freescale products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document Freescale reserves the right to make changes without further notice to any products herein Freescale makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical
59. e at their working voltage A reset switch may be wired to the chip s POR_B which is a cold reset negative logic input that resets all modules and logic in the IC POR_B may be used in addition to internally generated power on reset signal logical AND both internal and external signals are considered active low 2 For portable applications the ONOFF input may be connected to an ON OFF SPST push button switch On chip debouncing is provided and this input has an on chip pullup If not used ONOFF should be a no connect A brief connection to GND in OFF mode causes the internal power management state machine to change state to ON In ON mode a brief connection to GND generates an interrupt intended to be a software controllable power down An approximate 5 second or more connection to GND causes a forced OFF Table 1 9 USB recommendations Checkbox Recommendation Explanation supplemental recommendation 1 USB OTG To comply with the USB OTG specification the VBUS supply on the OTG connector should default to off when the boards power up The processor should turn VBUS on as required 2 USB Host USB_H1_VBUS should be directly connected to a 5 V supply Tie USB_H1_VBUS to an unswitched 5 V supply for the typical use case However if the your system is a USB device then USB_H1_VBUS may be a no connect Hardware Development Guide for i MX 6SoloLite Applications Processo
60. eesesseesseseesseessessessessessrestesseeseesresseesesrrssesseseest 2 5 1 Swapping data lines 2 5 onus suas pal ne nideu a a a a a a a a 2 5 2 DDR3 32 bits T topology considerations ccccccesceseeseeceteeeteeeeeeeeseees 2 5 3 DDR3 32 bits Fly by topology considerations ceceeseeeteceteeeeeeeeeees 2 5 4 2 Gigabyte recommendations ccceccescesecessceeseeeeceeescecsaeceeeeeeeenseeesaeeues 2 5 5 l Gigabyte Tecomimendatlons lt s2 a5 cats cassis owe cme eevee Mioataaey 2 5 6 Four chips T topology routing examples cccecceecceeseeeseeeeeceeeeeeeenseenes 2 5 7 LPDDR2 FBGA 168 routing example cecceecceceseceseeeeeeeeeeeteeeeeeeeaeees 2 5 8 High speed signal routing recommendations sssssessessseseesseeseeseesseeseeseeee 2 5 9 Ground plane recommendations ssssessseesseseesseesreseessesseeseseesseesseseesseesse 2 6 DDR power recommendations for DDR3 only s sssssssseessssesssesessessresseesese 2 7 USB recommendations ss sessseessessesseosseesesetsstesesressesstesesresseesseserssressessessres 2 8 Impedance signal recommendations s ss ssesessseesseseeseessesseesrssressessessresseeseese 2 9 Reference TESistOrS ioes isen ninae e aE aa Eaa EE e ANa aa a tAE 2 10 ESD and radiated emissions recommendations c ccccccceeeeeseeeseeeeteceteeeees 2 11 Component placement recommendations s ss ssessssseessessresressesseseesseesresressee 2 12 Reducing skew and pha
61. el Selector gpio in IBIS file Model Selector gpio gpiohv_dsii1l1_sri1l1_mio GPIO gpiohv ds111 sr110 mio GPIO gpiohv ds111 sr101 mio GPIO GPIO 3 3V extra drive fast sr maxfsel gpiohv ds111 sr110 mio GPIO gpiohv ds111 sr101 mio GPIO gpiohv_ds111_sr100_mio GPIO piohv ds111 sro GPIO Q m 8V extra drive fast 8V extra drive fast 1 8V extra drive fast W www 3V extra drive fast 3V extra drive fast 3V extra drive fast 3V extra drive slow sr max fsel sr fast fsel sr medium fsel sr fast fsel sr medium fsel sr slow fsel sr max fsel See the register description in the IOMUXC chapter in the chip reference manual for further details about this model 8 5 3 Model Selector USB At the time of publication i MX6 IBIS rev 3 does not contain the USB model It is expected to be published in a future revision Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 8 10 Freescale Semiconductor Understanding the IBIS Model 8 5 4 List of pins not modeled in the i MX6 IBIS file The following table provides a list of analog or special interface pins that are not modeled in the 1 MX6 IBIS file Table 8 6 i MX6 pins not supported by IBIS Domain Pins Analog RTC_XTALI RTC_XTALO XTALI XTALO ZQPAD Analog USB USB_OTG1_VBUS USB_OTG1_DP USB_OTG1_DN USB_OTG1_CHD B USB_OTG2_VBUS USB_OTG2_
62. enshot Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 6 6 Freescale Semiconductor Configuring JTAG Tools 7 rvdebug brd Connect to Target DER File View Connection Help 20 2 mp Ba sf Grouped By Ee Name Configuration RealView Instruction Set Simulator RVISS Model Library Model Process Instruction Set System Model ISSM Real Time System Model RTSM RealView ICE Cortex A9_0 Cortex A3_1 Cortex A9_2 Cortex A9_3 SoC Designer ARM Ltd Direct Connection DSTREAM VSTREAM Connection Modes Connect Use Default v Disconnect As Is Without Debug Figure 6 7 Establishing a connection to the core 3 Establish the connection to the core of your choice by using the Connect icon or the shortcut CTRL N You now have a new RVI configuration with four Cortex A9 targets and the RealView Debugger up and running You can now use the RealView Debugger window to access a register as shown in the following figure Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 6 7 Configuring JTAG Tools f2 Cortex A9_O RVI RealView Debugger File Edit View Target Debug Tools Help E ED ab ld baM BOC OB be Ww ia f E P Hy Fie Home Page Disassembly Welcome to RealView Debugger v4 1 2 Memory Start address 0 Display sizes Load Image S 0x020E0220 wv Autd column wv 4 bytes Re
63. ent Output voltage ripple 10mVpp maximum Load regulation 1mA lt ILoap lt ILoapmax for any operational 10mV maximum Line regulation for any li gap 1MA lt lLoan lt ILoapmax for any operational Viy 10mV maximum Transient Load Response Vout overshoot and undershoot when Vjy steps from 10mA to 0 75 x lLoapmax and back 20mV maximum transient response less than 30us Transient Line Response VOUT overshoot and undershoot for a Vy step of 1V up or down within the operating range for any Vout and for any I_oap 1MA lt ILoap lt ILoADMAx 20mV maximum transient response less than 30us Output resistance to GND when OFF 50 1000hms Startup Voltage ramp up time Min ramp rate 0 1V us Max total ramp time 1ms Table 7 12 lists the key general purpose LDO specifications and requirements Table 7 12 General purpose LDO requirements Specification Parameter Recommended Requirement Operating Input Voltage Vin System Application input power supply dependent Output voltage accuracy including bandgap variation 1mA lt ILoab lt ILoapMax for any operational Viy VNoM 3 Load regulation 1mA lt lLoapn lt Loapmax for any operational 0 25mV mA maximum Line regulation for any 9ap 1MA lt ltLoan lt ILoapmax for any operational Vy 10mV maximum Transient load regulation Voyr undershoot and overshoot whe
64. erence circuit The following table is a resistor chart see Table 1 1 recommendation 2 The recommendations are appropriate for designs with DDR memory chips with a maximum Vref input current of 2uA each Table 1 11 DDR Vref resistor sizing guideline Number of DRAM with 2 A Vref Resistor divider value input current 2 resistors 2 lt 1 21 KQ 1 2 lt 1 54 KQ 0 5 2 lt 2 32 KQ 0 1 4 lt 768 Q 1 4 lt 1 KQ 0 5 4 lt 1 5 KQ 0 1 1 5 I C clock speed and division factors IFDR The I C clock is sourced from PERCLK_CLK_ROOT which is routed from IPG_CLK_ROOT The PC clock frequency can be easily obtained using the following formula PC clock Frequency PERCLK_ROOT frequency division factor corresponding to IFDR By default the IPG_CLK_ ROOT and PERCLK CLK ROOT frequencies are set to 49 5MHz where the root clock is sourced from PLL2 s PFD2 Obtaining the frequencies can be accomplished using the following PLL2 528MHz PLL2_PFD2 528MHz 18 24 396MHz IPG_CLK_ ROOT PLL2_PFD2 ahb_podf ipg_podf 396MHz 4 2 49 5MHz PER_CLK_ROOT IPG_CLK_ROOT perclk_podf 49 5MHz 1 49 5MHz NOTE The above calculation assumes that the default CCM register settings routing and division factors are used If different routing PFD values and or division factors are used the user must adjust the parameters accordingly to calculate the correct clock frequency IFDR division factor an
65. ex 2 Device Index 3 ICE USB 119070379 Cortex A9 Cortex A9_3 Device Index 3 Auto Configure Clock Speed 10 000 MHz x Auto Configure Clear Platform Use adaptive clock if detected Trace Associations Read CoreSight ROM tables Move Left Properties Remove Move Right Configure Add the correct amount of Cortex A 9 cores desired to access your CPUs Figure 6 5 RealView debugger screenshot Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Configuring JTAG Tools 6 5 Reading a register with RealView Debugger v4 1 To read a register perform the following steps 1 Open the RealView Debugger 4 1 and connect to the target as shown in the following figure f8 RealView Debugger File Edit View RECAS Debug Tools Help I i D ce OR ee et as ee Disconnect Defining Mode 2 Disconnect Ctrl D Reset Target Processor Welcome lt Connection Properties Recent Cd Synchronization Control Cortes Attach Window to a Connection ARM92 REE N ARM Cd Connections Cortes Recent Connections gt E Load Image Ctrl Shift 0 g Reload Image to Target Ctri F5 Refresh Symbols E Unload Image Load Binary Recent Images gt Recent Binaries gt Figure 6 6 Connecting to the target 2 You are now at rvdebug bra if you have successfully completed your setup it looks like the following scre
66. f MMDC Example 8 4 Model Selector DDR in IBIS file ddr3_sell11_ds111_ mio lpddr2_sel10_ ds111 mio lpddr2_sel10_ ds110 mio DDR LPDDR LPDDR 1 5V ddr3 mode AON 5 Le 2V 34 Ohm driver impedance lpddr2 mode 34 Ohm driver impedance lpddr2 mode 40 Ohm driver impedance See the register description in the IOMUXC chapter in the chip reference manual for further details about this model Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 9 Understanding the IBIS Model 8 5 2 Model Selector gpio This model has the following parameters e Voltage level e Drive strength e Slew rate e Speed The IBIS model name is composed from parameters values as follows gpio lt voltage level gt ds lt drive_strength gt _sr lt slew_rate l bit gt lt speed 2 bits gt mio Voltage level For 1 MX 6SoloLite unlike other i MX 6 series chips each dual voltage level GPIO pad can be assigned to high or low voltage via the LVE bit IBIS users can choose between high and low voltage by selecting a different model at Model Selector Drive strength Controlled by the DSE bits bits 5 3 in the IOMUXC_SW_PAD CTL PAD lt pad name gt Slew rate Controlled by the SRE bit bit 0 in the IOMUXC_SW_ PAD CTL PAD lt pad name gt Speed Controlled by the SPEED bits bits 7 6 in the IOMUXC_SW_PAD CTL PAD lt pad name gt Example 8 5 Mod
67. facilitates the assignment of internal signals to external device balls pins by helping users e Record signal assignments for the supported i MX device e Identify conflicts allowing them to be resolved in real time e Add notes or comments for each signal to the list of recorded assignments e Generate C code to configure the IOMUXC registers according to the user s design e Move signals to different modules to order configuration code into logical functions Users can save design configurations for future use and or export them for use in schematics or software source code as supplementary documentation of a system The following figure shows a screenshot of the IOMUX application window with various areas labeled Device Code View Hel P no Dco ALT3 EIM_D Signals Ball Diagram Pads Registers Power General DSR ALT EIM_D 7 DTR ALT EIM_D F RI ALT3 EIM_EE a Z RTS ALT4 EIM_D Peripheral Signal Ball Pad Name AltMode Power Group Signal Notes ALT4 EIMD20 G20 ALT1 SD3DAT1 F14 a Z RXD_MUX ALT3 CSIO_C CTS G21 EIM_D19 ALT4 3 300V WEIM_SEC gpio3_GPIO 19 ALT3 CSIODAT11 M3 DCD D25 EIM_D23 ALT3 3 300V WEIM_SEC gpio3_GPIO 23 ALT1 SD3DATE E13 DSR G22 EIM_D25 ALT7 3 300V WEIM_SEC gpio3_GPIO 25 4 DTR F22 EIM_D24 ALT7 3 300V WEIM_SEC gpio3_G
68. for using RVDS at its version at time of publication 4 1 because it does not support PTM i MX 6 series trade module Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 6 1 D Configuring JTAG Tools 6 3 Updating your RealView ICE Before using the RealView ICE for JTAG debugging ensure you have the most up to date version available To update your RealView ICE perform the following steps 1 Launch the RVI Update utility by using the following path Start Programs ARM RealView ICE v4 1 RealView ICE Update 2 Connect to the ICE by selecting it from the list as shown in the following figure RVI Update lt Unconnected gt File View RVI Help wv Connect to Debug Hardware to continue Debug Hardware browser Stopped Access Host Name IP Address Ethemet Address Debug Hardware use VII 127 0 0 2 00 02 F7 00 15 94 RealView ICE Other TCP IP Devices IP Address Host Name Figure 6 1 Connecting to ICE NOTE The ICE must be disconnected from any other target at this step 3 Select the firmware update from the upside menu RVI gt Install Firmware Update 4 Select the following file or an equivalent more recent version C Program Files ARM RVI Firmware 4 2 23 ARM RVI 4 3 0 l base rvi 5 Select Continue from the install update window and wait until the update is complete Hardware Development Gui
69. formation Golden waveforms are a set of waveforms simulated using known ideal test loads They are useful for verifying the accuracy of behavioral simulation results against the transistor level circuit model from which the IBIS model parameters originated The following figure shows a generic test load network Re ee NEAR Rpl_near Rs_ near Ls near 0 0 0 0 V_terml FAR IN Ls_far Rs_far 0 0 0 Td Cl_near Zo C2 far 7 C2_near Cl far Viterm2 OH SsSSSsssssse5 o o n a o o 2sSs sss o Rp2_near Rp2_far GND GND Figure 8 3 Generic test load network Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 8 7 Understanding the IBIS Model The following table explains the golden waveform keywords Table 8 5 Golden waveform keywords Keyword Required Comment Test Data No e Provides a set of golden waveforms and references the conditions under which they were derived e Useful for verifying the accuracy of behavioral simulation results against the transistor level circuit model from which the IBIS model parameters originated Rising Waveform Near Yes Current Over Voltage tables for far and near portions of the golden model as Rising Waveform Far described by Figure 8 3 Falling Waveform Near
70. g regulator is recommended as a reference for memory configurations of more than four devices Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 1 Design Checklist Table 1 1 DDR recommendations continued Checkbox Recommendation Explanation supplemental recommendation 3 Connect DRAM_RESET to a 10 KQ 5 pulldown DDR3 DRAM_RESET should be pulled down to resistor to GND meet the JEDEC sequence until the controller is configured and starts driving DRAM_RESET should be kept high when DDR3 enters self refresh mode e LPDDR2 DRAM_RESET should be left unconnected Some Freescale reference designs use a 1 resistor simply to consolidate the BOM DRAM_RESET is an active low signal 4 DRAM_SDCKE0 and DRAM_SDCKE1 should be To minimize current drain the Freescale BSP connected to individual 10 KQ 5 resistors to GND board support package disables the EMI I O during DSM deep sleep mode A pull down resistor ensures that the DRAM is in the proper state during DSM e For LPDDR2 SDCKE 1 0 must be pulled down to meet the JEDEC sequence until the controller is configured and starts driving e For DDR3 SDCKE 1 0 pull down is not required to meet JEDEC Table 1 2 EIM recommendations for developer s boot modes Checkbox Recommendation Explanation supplemental recommendation 1 Use isolation buffers and series resistor
71. g the Clock Connectivity Table This chapter provides a reference table of the root clock default speed and a list of the i MX modules available to exit stop mode 4 1 Root clocks Clock connectivity is described in the System Clocks Connectivity section in the CCM chapter of the chip reference manual This section contains a series of tables that describe the clock inputs of each module and which clock is connected to it NOTE In some cases a clock is associated with an external interface and is sourced from a pad mainly through IOMUX and not from the CCM Such clocks do not appear in the clock connectivity table They are found in the External Signals and Pin Multiplexing chapter Clock gating is done with the low power clock gating LPCG module based on a combination of the clock enable signals For information about how the clock gating signals are logically combined see the LPCG section in the CCM chapter of the chip reference manual Table 4 1 lists the available clock sources and the default frequencies that are configured by design In some cases users need to divide the clock inside the module when the maximum frequency is used in order to meet the protocol requirements CCM the clock controller module generates and drives the clock sources For information about how the root clocks are generated see the clock generation diagrams in the CCM chapter of the chip reference manual Table 4 1 Clock roots
72. gn checklist for the 1 MX 6SoloLite For information on the i MX 6Quad 6Dual 6DualLite and 6Solo processors see the Hardware Development Guide for i MX 6Quad 6Dual 6DualLite 6Solo Families of Applications Processors IMX6DQ6SDLHDG The design checklist tables Table 1 1 Table 1 10 contain recommendations for optimal design Where appropriate the checklist tables also provide an explanation of the recommendation so that users have a greater understanding of why certain techniques are recommended All supplemental tables referenced by the checklist appear in sections following the design checklist tables See also the application note Common Hardware Design for i MX 6Dual 6Quad and i MX 6Solo 6DualLite AN4397 1 2 Design checklist tables Table 1 1 DDR recommendations Checkbox Recommendation Explanation supplemental recommendation 1 Connect ZQPAD to an external 240 Q 1 resistor This is a reference used during DRAM output buffer to GND driver calibration 2 Connect DRAM_VREF to a source that is 50 of The user may tie DDR_VREF to a precision external the voltage value of NVCC_DRAM resistor divider Shunt each resistor with a closely mounted 0 1 uF capacitor See Table 1 11 for resistor values Using resistors with recommended tolerances ensures the 2 DDR_VREF tolerance per the LPDDR2 and DDR3 specifications The user can use a PMIC s tracking regulator as used on Freescale reference designs A trackin
73. he corresponding CLK1_N input should be tied to a constant voltage level equal to 50 of VDD_HIGH_CAP Termination should be provided with high frequency signals See the LVDS pad electrical specification in the data sheet for further details After initialization the CLK1 inputs outputs can be disabled if not used by the PMU_MISC 1 register If unused any or both of the CLK1_N P pairs may be left floating The clock inputs outputs are general purpose differential high speed clock Input outputs Any or both of them can be configured As inputs to feed external reference clocks to the on chip PLLs and or modules for example as alternate reference clock for PCle or and SATA or video audio interfaces e As outputs to be used as either a reference clock or as a functional clock for peripherals for example an output of the PCle master clock root complex use See the chip reference manual for details on the respective clock trees 7 Bias XTALI with a 2 2 MQ resistor to GND Mount the resistor close to the XTALI ball The XTALI bias must be adjusted externally to ensure reasonable start up time Without the resistor start up time may be 200 ms or more Table 1 8 Reset and ONOFF recommendations Checkbox Recommendation Explanation supplemental recommendation 1 The POR_B input must be asserted at power up and remain asserted until after the last power rail for devices required for system boot ar
74. high speed signals Note that the propagation delay and the impedance control should match in order to have the correct communication with the devices 2 5 9 High speed signals DDR FEC display must not cross gaps in the reference plane Avoid creating slots voids and splits in reference planes Review via voids to ensure they do not create splits space out vias A solid GND plane must be directly under crystal associated components and traces Clocks or strobes that are on the same layer need at least 2 5x spacing from an adjacent trace 2 5 height from reference plane to reduce cross talk All synchronous modules should have bus length matching and relative clock length control For SD module interfaces Match data and CMD trace lengths length delta depends on bus rates CLK should be longer than the longest signal in the Data CMD group 5 mils Similar DDR rules must be followed for data address and control as for SD module interfaces Ground plane recommendations This section provides examples of good practices and how to avoid common user mistakes when flowing the ground planes layers The following two figures show common examples of poor GND planes The copper plane is represented by the color gray in Figure 2 23 and by the horizontal green lines in Figure 2 24 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 19 i MX 6 Series
75. ion 3 Only one 22 uF bulk capacitor should be connected to each of these on chip LDO regulator outputs e VDD_ARM_CAP e VDD_SOC_CAP e VDD_PU_CAP A 22 uF bulk capacitor must be placed as near as possible with pins vias The distance should be less than 50mil between bulk cap and VDD_xx_CAP pins Decoupling capacitors such as 0 1 uF or 0 22 uF should also be used If the nominal capacitance value is larger than recommended power up ramp time is excessive and operation cannot be guaranteed Note that the ramp up time is constant Larger capacitors mean more inrush current Select small capacitors with low ESR equivalent series resistance The 22 uF bulk capacitors should be placed as close as possible to the associated VDD_xx_CAP ball with trace widths and via sizes appropriate to the expected current draw A trace length of less than 50 mil is recommended Do not connect any loads to these LDO outputs VDDARM_CAP VDDARM23_CAP or VDDPU_CAP VDDSOC_CAP is restricted to MX6 loads 4 Only one 10 uF bulk capacitor should be connected to each of these on chip LDO regulator outputs e VDD_HIGH_CAP e NVCC_PLL e VDD_USB_CAP Decoupling capacitors such as 0 1 uF or 0 22 uF should also be used If the nominal capacitance value is larger than recommended power up ramp time is excessive and operation cannot be guaranteed Select small capacitors with low ESR These LDOs should only be used to power the loads as described i
76. ions Processor Rev 1 Freescale Semiconductor 7 11 Avoiding Board Bring up Problems Table 7 9 Capacitance required for each processor rail continued NVCC33_10 0 22uF for each pin 10uF 10uF The recommended bulk capacitance is shown External PMIC and However the recommended value can be reduced PCB design dependent upon the external PMIC and PCB design dependent impedances as long as the specification parameters and requirements in table 10 15 are met when measured at the processor pins VDD_HIGH_IN 0 22uF for each pin 10uF The recommended bulk capacitance is shown External PMIC and However the recommended value can be reduced PCB design dependent upon the external PMIC and PCB design dependent impedances as long as the specification parameters and requirements in table 10 15 are met when measured at the processor pins VDD_HIGH_CAP 0 22uF for each pin 2 2uF min Place close to processor pins 10uF max NVCC_PLL 0 22uF single pin 2 2uF min Place close to processor pins 10uF max VDD_SNVS_IN 0 22uF single pin Place close to processor pins VDD_SNVS_CAP 0 22uF single pin Place close to processor pins USB_OTG1_VBUS 0 22uF single pin 4 7uF This pin provides close to the max allowable capacitance according to the USB specification to compensate for any USB cable voltage droop Place close to processor pins USB_OTG2_VBUS 0 22uF single pin 4 7uF This pin
77. ired to use the FEC interface These signal connections are generally self explanatory or explained in the chip reference manual However there are some required modifications 11 3 Generating the reference clock The Ethernet MAC needs to have a reference clock which can be generated in one of the following three ways e On chip clock generator e By an external oscillator e By the FEC PHY 11 4 Generating the reference clock on chip The reference clock can be generated internally and output to the PHY on the FEC_REF_ CLK pin In this case it can also be fed back to the FEC_TX_CLK by clearing the GPR1 14 ENET_CLK_SEL bit T Ea _ GPR1 14 ENET_CLK_SEL 0 FEC_REF_CLK ANATOP REF_CLK Figure 11 3 Internal reference clock ENET_CLK_SEL 0 11 5 Using an external clock The reference clock can be generated externally by the Ethernet PHY or an external oscillator It can be input to the i MX6SL through the FEC_TX_CLK pin The following figures show the possible configurations Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 11 3 Using the FEC Interface GPR1 14 ENET_CLK_SEL 1 FEC_TX_CLK FEC 2 Oscillator ANATOP REF_CLK Figure 11 4 External oscillator Input at FEC_TX_CLK pin Figure 11 4 shows how to use an external clock This configuration is almost identical when using an external oscillator or the Ethernet PHY to supply a clock GP
78. is section show examples for the routing of 1 Gbyte LPDDR2 memory These figures are a guideline of the routing by layer used on 1 MX6SLEVK They use the same color code shown in Table 2 4 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 16 Freescale Semiconductor i MX 6 Series Layout Recommen dations Figure 2 22 Bottom LPDDR2 routing Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freesca le Semiconductor 2 17 i MX 6 Series Layout Recommendations The following table shows the total etch of the signals for the byte 0 and byte groups Table 2 6 Total signal etch LPDDR2 Signals Length Mils DRAM_DO 342 03 DRAM_D1 347 02 DRAM_D2 348 47 DRAM_D3 346 29 DRAM_D4 341 84 DRAM_D5 349 40 DRAM_D6 342 90 DRAM_D7 346 38 DRAM_DQMO 344 57 DRAM_SDQSO 349 30 DRAM_SDQS0_B 350 30 DRAM_D8 342 18 DRAM_D9 343 85 DRAM_D10 349 73 DRAM_D11 350 18 DRAM_D12 349 90 DRAM_D13 346 66 DRAM_D14 345 09 DRAM_D15 343 37 DRAM_DQM1 345 93 DRAM_SDQS 1 350 18 DRAM_SDQS1_B 350 45 DRAM_SDCLKO 842 84 DRAM_SDCLKO_B 842 12 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 18 Freescale Semiconductor 2 5 8 i MX 6 Series Layout Recommendations High speed signal routing recommendations The following list provides recommendations for routing traces for
79. ith an on chip keeper circuit such that the floating condition is actively eliminated if an external pull resistor is not present An external pull resistor on JTAG_TDO is detrimental See Table 1 13 for a summary of the JTAG interface Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 3 Design Checklist Table 1 5 JTAG recommendations continued Checkbox Recommendation Explanation supplemental recommendation 2 Ensure that the on chip pullup pulldown configuration is followed If external resistors are used with JTAG signals with the exception of JTAG_TDO For example do not use an external pulldown on an input that has an on chip pullup External resistors can be used with all JTAG signals except JTAG_TDO but they are not required See Table 1 13 for a summary of the JTAG interface 3 JTAG_MOD may be referred to as SJC_MOD in some documents Both names refer to the same signal JTAG_MOD should be externally connected to GND for normal operation in a system Termination to GND through an external pulldown resistor is allowed Use lt 4 7 kQ When JTAG_MOD is low the JTAG interface is configured for common software debug adding all the system taps to the chain When JTAG_MOD is high the JTAG interface is configured to a mode compliant with the IEEE 1149 1 standard Hardware Development Guide for i MX 6SoloLite Applications
80. l Register WDOG_WCR This signal remains asserted as long as the WDA bit is 0 2 Watchdog time out event WDT bit of Watchdog Control Register WDOG_WCR must be set for this scenario WDOG_B signal remains asserted until a Power on Reset POR occurs It gets cleared after the POR occurs and not due to any other system reset The POR_B PMIC_STBY_REQ and PMIC_ON_ REQ pins are powered by the VDD_SNVS_IN domain The specifications for these signals are shown in Table 7 7 Table 7 7 VDD_SNVS_IN domain signals Parameter POR_B PMIC_STBY_REQ PMIC_ON_REQ Supply Domain Power VDD_SNVS_IN VDD_SNVS_IN VDD_SNVS_IN I O Voltage Range V 0 3 to VDD_SNVS_IN 0 3 0 3 to VDD_SNVS_IN 0 3 0 3 to VDD_SNVS_IN 0 3 Min High level Input Voltage 0 7 x VDD_SNVS_IN N A N A VIH MIN Max Low level Input Voltage 0 3 x VDD_SNVS_IN N A N A VIL MAX High level Output Driver N A 50 250 ohms drive strength 50 250 ohms drive strength Impedance setting dependent setting dependent Low level Output Driver N A 50 250 ohms drive strength 50 250 ohms drive strength Impedance setting dependent setting dependent Active State Low High High Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 7 VDD_SNVS_IN domain signals continued I O type CMOS input CMOS output open drain Internal Pull device 10
81. l grid array contains 24 rows and 24 columns making it a 576 ball BGA package For detailed information about the package see the 1 MX 6SL series Consumer datasheets The following figure shows the ball grid array Figure 2 2 shows additional package information 4 6 10 12 14 16 16 20 22 24 1 3 4 F 9 W 43 15 17 19 2 23 AD AG 48 AA Y W Yy u T R P N M L K d H G F E D c B A A1 CORNER INDEX AREA BOTTOM VIEW Figure 2 1 i MX 6SL ball grid array Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 1 i MX 6 Series Layout Recommendations Figure 2 2 i MX 6SoloLite package information It is critical to maintain the recommended footprint of a 10 mil pad with a 14 mil open solder mask for ease of fanout In this case the solder paste is the same as the pad with 10 mils When using the Allegro tool optimal practice is to use the footprint as created by Freescale When not using the Allegro tool use the Allegro footprint export feature supported by many tools If export is not possible create the footprint as per the package mechanical dimensions outlined in the product data sheet Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 2 Freescale Semiconductor i MX 6 Series Layout Recommendations 2 1 1 Fanout illustrations The following figures show the top and bottom layer fanouts for the i MX SL chip
82. led by BOOT MODEO0 BOOT MODEL and JTAG MOD pins e On chip Fuse bits The JTAG_ MOD pin state controls the selection of JTAG to the core logic or boundary scan operation See the following references for further information e The System JTAG Controller SJC chapter in the chip reference manual for the definitions of the JTAG interface operations e The JTAG Security Modes section in the same chapter for an explanation of the operation of the e Fuse bit definitions in the following table e The Fusemap chapter in the chip reference manual the fusemap tables Table 10 1 System considerations for BSDL Pin name Logic state Description JTAG_MOD 1 IEEE 1149 1 JTAG compliant mode BOOT_MODE 1 0 0 0 Boot From Fuses 0 1 Serial Downloader 1 0 Internal Boot Development POR_B 1 Power On Reset for the device e Fuse bits JTAG_SMODE 1 0 0 0 JTAG enable mode 0 1 Secure JTAG mode SJC_DISABLE 0 Secure JTAG Controller is enabled 10 6 I O pin power considerations The boundary scan operation uses each of the available device pins to drive or read values within a given system Therefore the power supply pin for each specific module must be powered in order for the IO buffers to operate This is straightforward for the digital pins within the system NOTE BSDL was only tested at 1 8 V Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 10 2 Freesc
83. levels must be kept within 25mV of the nominal voltage level Maximum noise level shall be kept within 25mVp p of the supply voltage for corresponding operating frequency VDD_PU_IN 3 4 8 2 For bypass mode DC levels must be kept within 25mV of the nominal voltage level Maximum noise level shall be kept within 25mVp p of the supply voltage for corresponding operating frequency VDD_SOC_IN 3 4 9 1 For bypass mode DC levels must be kept within 25mV of the nominal voltage level Maximum noise level shall be kept within 25mVp p of the supply voltage for corresponding operating frequency USB_OTG1_VBUS N A N A N A N A Off by default Software must turn USB_OTG2_VBU it on S Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 4 Freescale Semiconductor Avoiding Board Bring up Problems 1 Internally controlled by processor NOTE VDD_ARM_IN VDD_PU_IN and VDD_SOC _IN can startup at the same However VDD_ARM_IN and VDD _PU_IN must be at their target values within Ims of VDD_SOC_IN There are no special timing requirements for USB_OTG1_VBUS USB_OTG2_VBUS 7 2 1 Detailed power up sequence The power up sequence timing diagram is shown in Figure 7 2 DD_SN S_IN 4 32K_CLOCK it DD_HIGH_IN N CC_HIGH DD_HIGH_CAP N CC_LOW N CC_PLL_OUT N CC_DRAM_IN DD_ARM_IN DD_P
84. llows CPU 0 0x82150000 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor Chapter 7 Avoiding Board Bring up Problems This chapter provides recommendations for avoiding typical mistakes when bringing up a board for the first time These recommendations consist of basic techniques that have proven useful in the past for detecting board issues and addressing the three most typical bring up pitfalls power clocks and reset A sample bring up checklist is provided at the end of the chapter 7 1 Power system overview 7 1 1 Block diagram The block diagram in Figure 7 1 shows major power systems blocks and internal external connections for the i MX 6SoloLite processor Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 1 Avoiding Board Bring up Problems External Supplies i MX 6SL Chip VDDPU_IN VDDPU_CAP LDO_PU DCDC Low enn T GPU2D OpenVG GND VDDARM_IN E LDO ARM VDPARM_CAP a g ARM Core GND L2 Cache L1 Cache Switch VDDSOC_IN LDO_SoC VDDSOC_CAP SoC VDDHIGH_CAP DCDC High LDO_2P5 VDDHIGH_IN TGND usB PLLs Lvps 24M OSC LDO_1P1 NVCC PLL_OUT _L TenD VDDSNVS_CAP LDO_SNVS GND VDDUSB_C
85. mal operation using MX6Sololoite internal LDOs These caps should be placed close to the processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances VDD_PU_IN 0 22uF for each pin 22uF For normal operation using MX6Sololoite internal LDOs These caps should be placed close to the processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances VDD_PU_CAP 0 22uF for each pin 22uF For normal operation using MX6Sololoite internal LDOs These caps should be placed close to the processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances NVCC_DRAM 0 22uF for each pin 22uF External PMIC and PCB design dependent The recommended bulk capacitance is shown However the recommended value can be reduced dependent upon the external PMIC and PCB design impedances as long as the specification parameters and requirements in table 10 15 are met when measured at the processor pins NVCC18_I1O 0 22uF for each pin 10uF 10uF External PMIC and PCB design dependent The recommended bulk capacitance is shown However the recommended value can be reduced dependent upon the external PMIC and PCB design impedances as long as the specification parameters and requirements in table 10 15 are met when measured at the processor pins Hardware Development Guide for i MX 6SoloLite Applicat
86. n li oap steps from 1 mA to 0 75 x li oapmax and back in 5us 1us rise and 1us fall 20mV maximum Transient Line regulation Vgyt overshoot and undershoot when Viy steps from Voytt0 3V to Vour 1 0V and back 10us rise and 10us fall for any Voyy and for any I gap IMA lt lLoan lt lLoapMax 10mV maximum Output noise 10Hz 10MHz 10mV maximum Startup Voltage ramp up time Min ramp rate 0 1V us Max total ramp time 1ms Table 7 13 lists the key low noise LDO specifications and requirements Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 15 Avoiding Board Bring up Problems Table 7 13 Low noise LDO requirements Specification Parameter Recommended Requirement Operating Input Voltage Viy System Application input power supply dependent Output voltage accuracy including bandgap variation 1MA lt Vom 3 ILoap lt ILoapMax for any operational Viy Load regulation 1MA lt I gap lt lLoapmax for any operational 0 25mV mA maximum Line regulation for any lLoap 1MA lt ILoap lt ILoaDMax for 10mV maximum any operational Viy Transient load regulation Vgyz undershoot and overshoot 5mV maximum when lLoap Steps from 1 mA to 0 75 x lLoapmax and back in 5us 1us rise and 1us fall Transient Line regulation Vgyt overshoot and undershoot 10mV maximum when Vy steps from Voytt 0
87. n the reference manual or data sheet Do not connect any loads to these LDO outputs NVCC_PLL_OUT or VDDUSB_CAP VDDHIGH_CAP is restricted to MX6 loads 5 One 22 uF decoupling capacitor should be connected to VDD_SNVS_CAP an on chip LDO regulator output A bulk capacitor is not necessary If the nominal value is larger than recommended power up down ramp time is excessive and suspend resume operation cannot be guaranteed Select a small capacitor with low ESR Do not connect an external load to this LDO output Note Larger cap values on VDD_SNVS_CAP slow the ramp rate If the VDD_SNVS_IN s ramp rate is significantly faster than VDD_SNVS_CAP s ramp rate excess current consumption may result in SNVS_IN 6 Maximum ripple voltage requirements 7 If VDD_SNVS_IN is directly supplied by a coin cell a schottky diode is required between VDD_HIGH_IN and VDD_SNVS_IN The cathode is connected to VDD_SNVS_IN Alternately VDD_HIGH_IN and VDD_SNVS_IN can be tied together if the real time clock function is not needed during system power down Common requirement for ripple noise should be less than 5 Vp p of supply voltage average value Related power rails affected all VDD_xxx_IN and VDD_xxx_CAP When no power is supplied to VDD_VSNVS_IN the diode limits the voltage difference between the two on chip SNVS power domains to approximately 0 3 V The processor is designed to allow current flow between the two SNV
88. nd NVCC_DRAM are also critical to the i MX6 boot up Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 18 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 14 Board bring up checklist continued Checklist Item 3 Verify power up sequence Details after all power rails have come up and are stable See the i MX6 data sheet for details about power up sequencing Owner Findings amp status Verify that power on reset POR_B is de asserted high 4 Measure probe input clocks 32 kHz 24MHz others 5 Check JTAG connectivity RV ICE Without a properly running clock the i MX6 will not function properly The 24MHz clock must be running before POR_B is released high to the i MX6 to allow the debug and execution of low level code This is one of the most fundamental and basic access points Note The following items may be worked on in parallel with other bring up tasks Access internal RAM Verify basic operation of the i MX6 in system The on chip internal RAM starts at address 0090_0000h and is 128 Kbytes in density Perform a basic test by performing a write read verify to the internal RAM No software initialization is necessary to access internal RAM Verify CLKO outputs measure and verify default clock frequencies for desired clock output options if the board design supports probing of the CLKO pin N
89. ntor Graphics The HyperLynx version used was HyperLynx v8 1 1 Update 3 Effective board design results achieved after loading e i MX6SL IBIS model e Companion IC IBIS models e Board model in HyperLynx format Board simulations for various GPIO and DDR signals were then run 8 8 References Consult the following references for more information about the IBIS model IBIS Open Forum http www eda org ibis The IBIS Open Forum consists of EDA vendors computer manufacturers semiconductor vendors universities and end users It proposes updates and reviews revises standards and organizes summits It promotes IBIS models and provides useful documentation and tools e IBIS specification http eda org pub ibis ver5 0 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 8 12 Freescale Semiconductor Chapter 9 Using the Manufacturing Tool 9 1 Overview The 1 MX manufacturing tool is designed to program firmware onto storage devices such as NAND or eMMC through the EVK and preload the data area with media files in an efficient and convenient manner It is intended for Freescale Semiconductor customers or their OEMs who plan to mass manufacture i MX based products The application is not designed to test the devices or to diagnose manufacturing problems Devices initialized with this application still need to be functionally verified 9 2 Feature summary The tool includes the following feat
90. om VDDSOC_IN with the LDO_SOC operating in internal bypass mode OFF There is no power to either VDDSOC_IN or VDD_SOC_CAP GPU2D OpenVG ON Power Power OFF OFF Power Gated Power is still supplied to Gated Gated VDDPU_IN but there is no power to VDD_PU_CAP because the LDO_PU is off OFF There is no power to either VDDPU_IN or VDD_PU_CAP 24MHz XTAL ON OFF OFF OFF OFF 24MHz RC OSC OFF ON OFF OFF OFF 32kHz OSC Clock ON ON ON ON OFF _ This is the 32kHz clock either being generated by the processor or being provided to the processor by the PMIC PLL ON OFF OFF OFF OFF USB PHY ON OFF OFF OFF OFF DRAM I O ON ON ON OFF OFF The DRAM I O Pre drivers are powered by the Pre Driver DRAM_2P5 input pin This pin should be connected to the VDD_HIGH_CAP pin of the processor LDO ARM ON OFF OFF OFF OFF OFF Internal ARM LDO turned off and power to the core is gated has no power LDO SOC ON ON BYPASS OFF OFF BYPASS MODE Internal SoC LDO is turned MODE off but placed into internal bypass mode External PMIC low voltage 0 9V power is supplied to the SoC domain via the VDDSOC_IN pins LDO PU ON OFF OFF OFF OFF OFF Internal PU LDO turned off and power to the PU domain is gated has no power LDO 1P1 ON ON OFF OFF OFF OFF 1 1V internal LDO turned off LDO 2P5 ON ON MICRO OFF OFF Whenthe LDO_2P5 is placed into micro power POWER mode the main LDO is turned off and a low MODE current bias reg
91. or assistance obtaining documents if needed e For detailed information about how to use the manufacturing tool see Manufacturing Tool V2 Quick Start Guide e For detailed information about how to script the processing operations of the manufacturing tool see the Manufacturing Tool V2 UCL User Manual e For information about how to generate the manufacturing tool firmware for Linux and Android see Manufacturing Tool V2 Linux or Android Firmware Development Guide e For the change list and known issues see Manufacturing Tool V2 Release Notes Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 9 2 Freescale Semiconductor Chapter 10 Using BSDL for Board level Testing 10 1 BSDL overview Boundary scan description language BSDL is used for board level testing after components have been assembled The interface for this test uses the JTAG pins The definition is contained within IEEE Std 1149 1 10 2 How BSDL functions A BSDL file defines the internal scan chain which is the serial linkage of the IO cells within a particular device The scan chain looks like a large shift register which provides a means to read the logic level applied to a pin or to output a logic state on that pin Using JTAG commands a test tool uses the BSDL file to control the scan chain so that device board connectivity can be tested For example when using an external ROM test interface the test tool would do the following
92. ote Test ports must be provided in order to monitor signals assigned to these pins This ensures that the corresponding clock is working and that the PLLs are working Note that this step requires chip initialization for example via the JTAG debugger to properly set up the IOMUX to output CLKO and to set up the clock control module to output the desired clock See the reference manual for more details Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 19 Avoiding Board Bring up Problems Table 7 14 Board bring up checklist continued Checklist Item Measure boot mode frequencies Set the boot mode switch for each boot mode and measure the following depending on system availability e NAND probe CE to verify boot measure RE frequency SPI NOR probe slave select and measure clock frequency e MMC SD measure clock frequency Details This verifies the specified signals connectivity between the i MX6 and boot device and that the boot mode signals are properly set See the System Boot chapter in the reference manual for details about configuring the various boot modes Findings amp Owner Status Run basic DDR initialization and test memory 1 Assuming the use of a JTAG debugger run the DDR initialization and open a debugger memory window pointing to the DDR memory map starting address 2 Try writing
93. own in the following figure The lefthand image shows the detail provided by Freescale inside the fabrication detail as a part of the Gerber files The righthand side shows the solution suggested by the PCB fabrication company for our requirements Additional power planes to support i MX 6Dual 6Quad and i MX 6Solo power options only AYER 1 TOP SID 3 8 02 VL LL LAYER 2 OND PLANE 1 1 2 02 AYER 3 POWER PLANE 2 01 AYER 4 INTERNAL L 2 07 LAYER 5 GND PLANE 2 2 02 AYER 6 BOTTOM SIDE 3 8 02 Figure 2 5 Layer stack EVK board The following table shows a working stack up implementation Table 2 1 Stackup implementation Single ended Differential Layers Trace width Impedance Trace width Trace spacing Impedance Trace width Trace spacing Impedance Mils Qs Mils Airgap Mils Qs Mils Airgap Mils Qs TOP 4 75 50 4 2 4 8 90 3 5 5 5 100 INT1 5 5 50 BOT 4 75 50 4 2 4 8 90 3 5 5 5 100 Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 5 i MX 6 Series Layout Recommendations 2 3 DDR connection information The following figures show the block diagrams from the reference design boards for the DDR3 interface and the LPDDR2 interface respectively with the 1 MX6SL i MX6SL DDR3 DRAM_A 15 0 mxx A 5 0
94. p to 2 Gbytes of DRAM memory i MX6SL DDR routing needs to be separated into three groups data address and control Each group has its own method of routing from an 1 MX 6SL chip to DDR memory The DDR layout has 2 Gbytes 2 5 1 Swapping data lines The DDR3 pin swapping technique for the data bus lines within bytes makes it easier to e Route direct lines e Avoid changes between layers The rules are as follows e Hardware write leveling lowest order bit within byte lane must remain on lowest order bit of lane by JEDEC compliance see the Write Leveling section in JESD79 3E DO D8 D16 D24 D32 D40 D48 and D56 are fixed Other data lines free to swap within byte lane e JEDEC DDR3 memory restrictions are No restrictions for complete byte lane swapping DQS and DQM must follow lanes NOTE If byte lane swapping was done target DDR IC register read value must be transposed according to the data line swapping 2 5 2 DDR3 32 bits T topology considerations Be sure to take into account the following when designing a T topology system e Follow the routing rules described in Table 2 3 e Termination resistors not required e Short routing lengths and on chip drive strength control e Your design is limited to 4 DDR chips e DDR3 2 GBytes using latest memories 4 GBytes coming 2 5 3 DDR3 32 bits Fly by topology considerations Pay attention to the following recommendations when the Fly by topology and
95. ply to the GPU must be designed to handle relatively large surges Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 3 5 Requirements for Power Management of current at high frequencies from the original source to the processor input for power VDD_SOC_IN and at the output of the internal regulator for GPU operations VDD_PU_CAP The following list provides recommendations for each specific point along the current supply path It may be necessary to implement all of these recommendations to ensure that one particular point along the supply path does not become a current choke point e The voltage with which VDD_SOC_IN will be fed must have a maximum tolerance of 25 mV PF0100 s SWIC is already designed with this tolerance Care must be taken if the design uses a different regulator e VDD_SOC_CAP and VDD _PU_CAP bulk capacitance must be equal to 22 uF so that start up current through the on board LDOs is reduced e These bulk capacitors must be very close to the VDD_SOC_CAP and VDD PU CAP pins respectively and the connecting traces must be as thick as the design allows so the ability of being a bulk capacitor for high speed operations is not limited e VDD SOC _IN requires 66 uF of bulk capacitance because it supplies power for both VDD_SOC_CAP and VDD_PU_CAP Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 3 6 Freescale Semiconductor Chapter 4 Usin
96. pplied to the processor it should be connected to the RTC_XTALI pin The RTC_XTALO pin should remain floating Figure 7 4 is an example circuit Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 7 Avoiding Board Bring up Problems 32kKH Clack fZenerator Figure 7 4 External 32k clock connection diagram LLELLL ETT YTA AT _ TAI LMx Salolite Prosessor Table 7 5 provides a list of specifications for the 32kHz input clock and RTC_XTALI Table 7 5 RTC_XTALI and 32kHz clock specifications Parameter Description Min Typ Max Units RTC_XTALI input source sink current 1 LA RTC_XTALI Input Voltage 0 VDD_SNVS_CAP 1 1V RTC_XTALI High level input voltage 0 8 x VDD_SNVS_CAP 1 1V ViH MIN RTC_XTALI Low level input voltage 0 2 V 1 1V V ViL max 32kHz Clock Nominal Frequency 32 768 kHz 32kHz Clock Frequency Accuracy 10 30 200 ppm 1 Note The 32kHz Clock accuracy needed will be dependent upon the overall RTC time keeping accuracy required A typical 32kHz crystal used for RTC time keeping has an accuracy of around 10 30ppm Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 4 Avoiding Board Bring up Problems PMIC Handshaking Signals The 1 MX6Sololite PMIC handshaking signals that will be considered in this section are POR_B PMIC
97. provides close to the max allowable capacitance according to the USB specification to compensate for any USB cable voltage droop Place close to processor pins VDD_USB_CAP 0 22uF single pin 2 2uF min Place close to processor pins 10uF max 7 7 Power Modes Table 7 10 defines the processor power modes and indicates the on off state of the power supplies and different processor modules in each of the power modes Table 7 10 Power Mode Table Power Supply or Power Mode Processor Modals Comments Active Idle Suspend SNvs OFF POR_B HIGH HIGH HIGH LOW LOW _ This is the logic state of the POR_B signal PMIC_STBY_REQ LOW LOW HIGH LOW Low PMIC_ON_REQ HIGH HIGH HIGH LOW Low WDOG_B HIGH HIGH HIGH LOW LOw These logic states assume a watchdog event has NOT triggered Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 12 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 10 Power Mode Table continued Power Mode processor Module Comments Active Idle Suspend SNvs OFF ARM Core ON Power Power OFF OFF Power Gated Power is still supplied to L1Cache Gated Gated VDDARM_IN but there is no power to VDD_ARM_CAP because the LDO_ARM is off OFF There is no power to either VDDARM_IN or VDD_ARM_CAP SoC L2 Cache ON ON Low OFF OFF Low Voltage The SoC and L2 cache are Voltage provided a low voltage source 0 9V fr
98. quency sources e CLK1_ P N is optional In addition to probing the external input clocks you can check internal clocks by outputting them at the debug signals CLKO1 and CLKO2 iomuxed signals See the CCM chapter in the chip reference manual for more details about which clock sources can be output to those debug signals JTAG tools see Chapter 6 Configuring JTAG Tools can be used to configure the necessary registers to do this Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 16 Freescale Semiconductor 7 10 Avoiding reset pitfalls Follow these guidelines to ensure that you are booting using the correct boot mode Avoiding Board Bring up Problems During initial power on while asserting the POR_B reset signal ensure that 24 MHz clock is active before releasing POR_B Follow the recommended power up sequence specified in the i MX6SL data sheet Ensure the POR_B signal remains asserted low until all voltage rails associated with bootup are The GPIOs and internal fuses control how the 1 MX6SL boots For a more detailed description about the different boot modes see the system boot chapter of the chip reference manual The following figures show two examples of the power up sequence 5V_MAIN Feeds 3 3 V Reg ae ut SNVS SW1A B Tek Single seq i 0 0kS s 2 0 V 20 Feb 2012 14 07 48 Figure 7 5 Power up sequence example 1 Hardware Development Guide for i
99. r Rev 1 1 8 Freescale Semiconductor Design Checklist Table 1 10 Miscellaneous recommendations Checkbox Recommendation Explanation supplemental recommendation 1 The TEST_MODE input is internally connected to an This input is reserved for Freescale manufacturing use on chip pulldown device The user can either float this signal or tie it to GND 2 For termination of unused analog interfaces see Table 1 15 3 GPANAIO must be a no connect This output is reserved for Freescale manufacturing use 4 NC contacts are no connect and should be floated Depending on the feature set some versions of the IC may have NC contacts connected inside the BGA Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 1 9 Design Checklist 1 3 The following figure provides supporting information for Table 1 2 recommendation 1 4 6 8 11 Bus isolation circuit P3V15_VDDHIGH_SW2 Boot Strap Power Control GND POR B VCC_BT_CFG_OE gt BRE gah VCC_BT_CFG_OE VGC_BT_CFG_OE o e VCC_BT_CFG_OE R722 47K 0402_CC 6 BT CFG EN C218 1 0UF VCC_BootStrap 0402_CC 10V 5 3 output pulse R41 o GND RT BT CFG EN 7 SN7aLvC2 125 pS GND
100. rdware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 6 Freescale Semiconductor Avoiding Board Bring up Problems nitially ramp to 1 8V Begin ramp before NVCC18_I0 VDD_SNVS_IN VDD_HIGH_IN NVCC33_IO NVCC18_1O NVCC_DRAM Ramp voltage to 3 2V after VDD_ARM_IN I LVE settings completed VDD_SOC_IN POR_B I Approximate timing Figure 7 3 Ramp up recommendation for low voltage design systems power up LDO bypass mode Step1 Follow the proper power up sequence up to NVCC33_IO rail power up point Step2 Power up NVCC33_IO to 1 8V instead of 3Vnominal Step3 Complete the rest of the power up sequence Step4 Set up each of the dual voltage pad s operating voltage to NVCC18_IO by setting LVE bit located in corresponding IOMUX control register Step5 Change bump NVCC33_IO s voltage to nominal 3V Above step will require additional steps but will avoid possible electrical issues to 1 8V logic level lines or having to add external glue logic which could be cost prohibitive CAUTION When ramping NVCC33_IO to 1 8V make sure to have NVCC33_IO is powered up before NVCC18 IO Also NVCC33_IO must be ramped up after VDD_HIGH_IN is powered up If these sequences were not followed it may result in unreliable boot or possibly cause IC failure 7 3 External 32 kHz clock requirements If an external 32kHz crystal output is su
101. rocessors power requirements see the product data sheet The following table shows the i MX6SL chip specific interface Table 3 1 Interface between i MX6SL and PF0100 A Voltage Current Generated Power up Voltage rail Supply reg V A by sequence Notes VDD_ARM_IN SW1A B 1 375 2 5 PF0100 1 VDD_ARM_CAP Note 1 i MX Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 3 1 Requirements for Power Management Table 3 1 Interface between i MX6SL and PF0100 continued Voltage rail Supply reg aea ers ree isin Notes VDD_SOC_IN SW1C 1 375 1 75 PF0100 1 VDD_PU_IN VDD_SOC_CAP Note 1 i MX VDD_PU_CAP Note 1 i MX VDD_HIGH_IN SW2 3 15 2 PF0100 2 VDD_HIGH_CAP Note 1 i MX VDD_SNVS_IN VSNVS 3 400 uA PF0100 0 VDD_SNVS_CAP Note 1 1 1 i MX NVCC_PLL Note 1 i MX USB_OTG1_VBUS Connect to VBUS pin of USB plug USB_OTG2_VBUS Connect to VBUS pin of USB plug VDD_USB_CAP Note 1 i MX NVCC_DRAM SW3A B 1 2 2 5 PF0100 4 SW3 can be configured from 0 4 to 3 3V so the right voltage is chosen for the respective DDR technology NVCC_DRAM_2P5 VDDHIGH_ 2 5 0 1 i MX or 5 CAP or PF0100 VGEN5 DRAM_VREF VREFDDR 0 6 0 01 PF01
102. s Processor Rev 1 2 10 Freescale Semiconductor i MX 6 Series Layout Recommendations Route the ADDR CMD signals as shown in the following figure Address Command Figure 2 11 ADDR CMD signal topology Control Net Structures DRAM_SDCKE 1 0 DRAM_SDODT 1 0 CTRL Rtt Figure 2 12 CTRL signal topology Net Structure Routing for DRAM_D 31 0 DRAM_DQM 3 0 DRAM_SDQS 3 0 DRAM_SDQS 3 0 Data DRAM_SDCLK 1 0 DRAM_SDCLK 1 0 Figure 2 14 Clock routing topology Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 11 i MX 6 Series Layout Recommendations 2 5 6 Four chips T topology routing examples The figures in this section show examples for the routing of the 2 GByte DDR3 memories Figure 2 15 through Figure 2 20 are guidelines of the T configuration routing with 12 layers PCB Table 2 4 shows the color coding used in the figures Table 2 4 Color code Color Meaning Soft Green ADD amp CMD Signals Yellow Clocks Soft Pink Data Byte Group 0 Purple Data Byte Group 1 Blue Data Byte Group 2 Brown Data Byte Group 3 Gray DDR_1V5 amp DDR_VREF Soft Red Control Signals os 1a gga Figure 2 15 Top layer DDR3 routing Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 12 Freescale Semiconductor FHEA ee A e ae AN OF z gt combs PA OCE ar
103. s Processor Rev 1 8 2 Freescale Semiconductor Understanding the IBIS Model Table 8 2 Component and Pin Information continued Keyword Required Comment Package Yes This keyword contains the range minimum typical and maximum values over which the packages lead resistance inductance and capacitance vary the R_pkg L_pkg and C_pkg parameters Pin Yes This keyword contains the pin to buffer mapping information In addition the model creator can use this keyword to list the package information R L and C data for each individual pin R_pin L_pin and C_pin parameters Package No If the component model includes an external package model or uses the Define Package Model Model keyword within the IBIS file itself this keyword indicates the name of that package model Pin Mapping No This keyword is used if the model creator wishes to include information on buffer power and ground connections This information may be used for simulations involving multiple outputs switching Diff Pin No This keyword is used to associate buffers that should be driven in a complementary fashion as a differential pair Model This keyword provides a simple means by which several buffers can be made optionally available Selector for simulation at the same physical pin of the component Example 8 2 Component and pin information Component mx6sl_ 416mapbgal3x13 Manufacturer FREESCALE
104. s at the same length or routing by byte group Ideally we could route all the signals at the same length However it could be difficult because of the large number of connections in the tight space between the DDR and the processor The following table explains the rules for routing the signals by the same length Table 2 2 DDR3 LPDDR2 routing by the same length Signals Total length Recommendations Address and Bank Clock length Match the signals 25 mils of the value specified in the length column Data Clock length Control signals Clock length Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 7 i MX 6 Series Layout Recommendations Table 2 2 DDR3 LPDDR2 routing by the same length continued Signals Total length Recommendations Clock Longest trace lt 3 inches Match the signals of clocks signals DRAM_SDCLK 1 0 5 mils Each differential clock pair DRAM_SDQSJ 3 0 and Clock length Match the signals of DQS signals DRAM_SDQSJ 3 0 _B 10 mils of the value specified in the length column Routing by byte group requires better control of the signals of each group It is also more difficult for analysis and constraint settings However its advantage is that the constraint to match lengths can be applied to a smaller group of signals This is often more achievable once the constraints are properly set The following table expl
105. s file Run RealView Debugger by using the following path start gt Programs ARM gt RealView Development Suite v4 1 RealViewDebugger v4 1 Select Connect to Target in the RealView Debugger upside menu Target gt Connect To Target Press Add near RealView ICE 7 rvdebug brd Connect to Target DEAR File View Connection Help 0 2 mp Ba Ge Grouped By Target v Name Configuration State RealView Instruction Set Simulator RVISS Model Library Model Process Instruction Set System Model ISSM C Add Add j H Add a chain Hardware targets connected to an ARM RealView ICE unit Figure 6 4 Adding your ICE Select your ICE from the list and press Connect see Figure 6 1 In the new window choose Select Platform Expand the Freescale list and select imx6 o Save the file File gt Save Close the window Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor After finishing this procedure you should see the following screen RVConfig D Profiles b38883 Application Data ARM rvdebug 4 1 2 RVI_O rvc File View Help Configuring JTAG Tools E Connected to USB 119070379 o Baie SJC SDMA ARMCS DP Cortex A9 Cortex A9 Cortex A9 Cortex A9 Advanced Trace Platform iMX6 Q SJC SDMA ARMCS DP Ti SJC_O SDMA_O ARMCS DP_O IR Length 5 IR Length 4 IR Length 4 Device Index 1 Device Ind
106. s on the Isolation buffers are required because 6SoloLite pads development board design if the boot configuration can be set to 1 8V or 3V logic levels while boot signals bus signals muxed with the EIM bus are used as the require 3V logic level to latch the boot settings system s EIM signals GPIO or other functions after Any pull ups for boot configuration line must be properly boot isolated because there is a chance that the system may use 1 8V logic levels See Figure 1 1 for an example circuit 2 To reduce incorrect boot up mode selections do Using EIM boot interface lines as inputs may result in a one of the following wrong boot up due to the source overcoming the pull e Use EIM boot interface lines only as processor resistor value A peripheral device may require the EIM outputs Ensure EIM boot interface lines are not signal to have an external or on chip resistor to minimize loaded down such that the level is interpreted as signal floating low during power up when the intent is to be a If the usage of the EIM boot signal affects the peripheral high level or vice versa device then an analog switch open collector buffer or If an EIM boot signal must be configured as an equivalent should isolate the path A pullup or pulldown input isolate the EIM signal from the target driving resistor at the peripheral device may be required to source with one analog switch and apply the logic maintain the desired logic level
107. se a wide island trace for current capacity Place the VTT generator as close to termination resistors as possible to minimize impedance inductance Place one or two 0 1 uF decoupling capacitors by each termination RPACK on the VTT island to minimize the noise on VTT Other bulk 10 22 pF decoupling is also recommended to be placed on the VTT island DDR_VTT pA ong e C421 C152 Figure 2 27 DDR_VTT evaluation board example Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 2 22 Freescale Semiconductor i MX 6 Series Layout Recommendations DDR_VIT DDR_VTT DRAM_SDBAO 47 R681 C155 DRAM_SDBA1 47 R683 DRAM_SDBA2 47 R623 0 1UF DRAM RAS B 47 R677 E C454 DRAM CAS B 474 R680 0450 DRAM CS0 B 47 DRAM WEB 47 R286 DRAM_CS1_B 47 0 1UF DRAM _SDCKEO 47 R287 To 1UF DRAM SDODTO 47 DRAM_SDCKE1 47 R622 DRAM_SDODT1 47 C423 C451 0 1UF _ o 1uF Figure 2 28 DDR_VTT evaluation board examples 2 7 USB recommendations Use the following recommendations for the USB e Route the DP and DM differential pair first e Route DP and DM signals on the top or bottom layer of the board e The trace width and spacing of the DP and DM signals should be such that the differential impedance is 90 Q e Route traces over continuous planes power and ground They should not pass over any power GND plane slots or anti etch When placing
108. se problems in deferential pairs traces cesses Hardware Development Guide for i MX 6SoloLite Applications Processors Rev 1 Page Number Freescale Semiconductor Contents Paragraph Page Number Title Number Chapter 3 Requirements for Power Management 3 1 Power management requirements OVervieW s essessssssessesseeerssressessresressesstssresseeseesressee 3 1 3 1 1 Voltage domains OVervieW sessssesseseseseessessssressesstesressesstesressteseesresstessesressressesresee 3 1 Si be PEOLOO OVE Wy saci ae ceased aie he ae hae ot ala cons tena aka te Aas bn ahaa 3 1 3 2 Requirements for a generic interface between chip and PFO100 cc ceeseeseeseeneeeeeees 3 1 3 3 LM XG internal regulators sicn sists chek aana n cae kien a a a a 3 3 3 4 Connection diagram Se aeii ai ea a E E E EE E E EE E wanna 3 4 3 5 Video power recommendations s ssssssessessreseessesersrtssesreserssessesstsstessesstssresseeseesressee 3 5 Chapter 4 Using the Clock Connectivity Table 4 1 Root CLOCKS css scscosescns asia va teaeks Aiatacota end Naas ee ead Anda E E a ane Ae as 4 4 2 Waking the Core up from stop MOE 4 0 sx5 gsser dccsdssdotissazeasasbaadesatinaadans ibis ti dbeodviandeniede 4 2 Chapter 5 Using the IOMUX Design Aid 5 1 Application regj irementSiinesninotnneniai niii ata ari easi arii 5 2 5 2 TIOMUX tool Versi fisnen ianua a a a i 5 2 5 3 TOME tool loc tioi aserrean aa r a a ia e alae E E 5 2 5 4 Learning to use the IO
109. sions of a stripline and microstrip pair Figure 2 30 shows the differential pair routing gt lt gt lt lt je Stripline Microstrip 2S where For better coupling within a differential pair make S lt 2W S lt B and D pair space between two traces of a differential pair width of a single trace in a differential w S space between two adjacent differential pairs thickness of the board D B Figure 2 29 Microstrip and stripline differential pair dimensions Figure 2 30 Differential pair routing The space between two adjacent differential pairs should be greater than or equal to twice the space between the two individual conductors Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 2 24 2 9 i MX 6 Series Layout Recommendations Reference resistors NOTE The reference resistor and the connection should be placed away from noisy regions Noise induced on it may impact the internal circuit and degrade the interface signals 2 10 ESD and radiated emissions recommendations The PCB design should use six or more layers with solid power and ground planes The recommendations for ESD immunity and radiated emissions performance are as follows 2 11 All components with ground chassis shields USB jack buttons and so forth should connect the shield to the PCB chassis ground ring Ferrite beads should be place
110. tchdog reset event occurs In this case the POR_B must be asserted for at least one 32k clock cycle 30us for the processor to qualify it as valid 7 6 Processor Rail Capacitance Table 7 9 lists the capacitance high frequency and bulk required on each processor rail Ceramic capacitors should be used and should be rated for the maximum voltage specified for each rail Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 10 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 9 Capacitance required for each processor rail Processor Rail High Frequency Caps Recommended Bulk Caps Comments VDD_ARM_IN 0 22uF for each pin 22uF For normal operation using MX6SoloLite internal LDOs These caps should be placed close to the processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances VDD_ARM_CAP 0 22uF for each pin 22uF For normal operation using MX6Sololoite internal LDOs These caps should be placed close to the processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances Direct through via to caps VDD_SOC_IN 0 22uF for each pin 66uF For normal operation using MX6Sololoite internal LDOs Should be placed close to processor pins Values may vary dependent upon the PMIC regulator requirements and PCB impedances VDD_SOC_CAP 0 22uF for each pin 22uF For nor
111. this signal will not have any power applied to its pad since it is powered from the VDDSNVS_IN domain which will be powered off As a result this signal should be at OV Care should be taken so that the PMIC does not drive or inject current into this signal when the system is placed in the OFF state When in the SNVS and OFF states this signal will not have any power applied to its pad since it is powered from the VDDHIGH_IN domain which will be powered off As a result this signal should be at OV Care should be taken so that the PMIC does not drive or inject current into this signal when the system is placed in the SVNS and OFF states 7 8 Regulator Requirements The tables in this section list the requirements for the step down DCDC converters general purpose LDOs and low noise LDOs and low noise LDOs The PMIC should meet the specification parameters and requirements for the applicable regulators in this section While there are no specific requirements for the transient slew rate of the regulators a 1uA s should be acceptable Table 7 11 lists the key DCDC converter specifications and requirements Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 7 14 Freescale Semiconductor Avoiding Board Bring up Problems Table 7 11 Step down DCDC converter requirements Specification Parameter Recommended Requirement Operating Input Voltage Viy System Application input power supply depend
112. ulation circuit is used to supply 2 5V to the DRAM I O pre drivers require about 10uA from the VDD_HIGH_CAP pin Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 7 13 Avoiding Board Bring up Problems Table 7 10 Power Mode Table continued Power Supply or Power Mode Praca sear Node Comments Active Idle Suspend SNvs OFF LDO USB 3 0V ON OFF OFF OFF OFF OFF Internal USB LDO is turned off Bandgap ON OFF OFF OFF OFF Low Power ON ON OFF OFF OFF Bandgap Charge Pump OFF OFF ON OFF OFF NVCC HIGH I O ON ON ON OFF OFF 3 3V NVCC LOW I O ON ON ON OFF OFF I 8V NVCC DRAM I O ON ON ON OFF OFF LPDDR2 1 2V VDDSNVS_IN ON ON ON ON OFF Power to VDDSNVS_IN is provided either by LDO_SNVS the PMIC or external coin cell When VDDSNVS_IN is present ON the LDO_SNVS automatically turns on and will provide power to the VDD_SNVS_CAP pin When OFF neither the coin cell or PMIC power into the VDDSNVS_IN pin is present 1 SVNS Secure Non volatile State When in the OFF state this signal will not have any power applied to its pad since it is powered from the VDDSNVS_IN domain which will be powered off As a result this signal should be at OV Care should be taken so that the PMIC does not drive or inject current into this signal when the system is placed in the OFF state When in the OFF state
113. ures e Continuous operation operations automatically begin with the connection of a new device and multiple operations such as update and copy can be linked together seamlessly e Enumeration static ID firmware loaded into RAM in recovery mode prevents Windows from enumerating every device e AutoPlay various Windows pop up application and status messages such as Explorer in Windows XP and Windows 7 In addition the following characteristics improve the tool s ease of use e An independent process bar is set up for each physical USB port e The tool begins processing with the connection of the first device detected and allows users to replace each device after completion instead of needing to wait for all devices to complete e The tool uses color based indicators to indicate the work status on each of the ports Blue indicates the device is being processed Green indicates the device was successfully processed and that the programmed device can be replaced with a new one independent of the of the device s progress Red indicates the device failed to process Hardware Development Guide for i MX 6SoloLite Applications Processor Rev 1 Freescale Semiconductor 9 1 Using the Manufacturing Tool 9 3 Other references For more detailed information about the manufacturing tool see the following documents included in the manufacturing tool release package Contact your local Freescale sales office f
114. y RTA ERE AaS a ERA iR 7 4 Detailed power up sequence iets cise dapiauestedoadexcessesins cieavateaucavenessadalleeadeatvncoumapaeaseanace 7 5 VDD SNV SUN power up ramp Tate tachhe sel recat a ota ite te dene cleat ralan 7 6 POWET COW SEQUETICE wit cc orc di anccrdys oases fcoccaays edadedhigs bedtden wound edureslan due ccaran iiia alates 7 6 Power up sequence in low voltage system design cceecceessecsseceeeeeeeeeeteeeeseeeteeeees 7 6 External 32 kHz clock Pequin ener a3 yiesa ua ininets asvsd easctesased sacha tation sean deeasaan dveabe eaereneeed ox 7 7 PMIC Handshaking Signals scc20 sa scvccueveattesvs eve ccctecsdele tabi aiesvintactie aasticl edie aaeeieutts 7 9 Watchdog Reset Behavior acrenarunnsuris onire e a Steins 7 10 Processor Rail CAPACI ANC Ssh contirs alia acess sl aatas Gameia setaea dh an tector andacc utes ancdunianiastagetnn 7 10 Power WIGS 62a asso aaah Ua eh oki alae cera UN aes ena nea Ci aa 2s 7 12 Reg lat r Requirements arisna eiaa aR E AEAT 7 14 Checking for clock pittalls acs isusvieisiacts athatg tahoe eae eno heated 7 16 Ayoiding reset pitfalls rsisi has hse a E saad rica vaca EE E E A A O EE 7 17 Sample board bring up checklist ysancicssd ees scCacasiecssacesateganesessedsadeesteseccosceceacPastieae davatesen 7 18 Chapter 8 Understanding the IBIS Model IBIS structure and content cnsceineiiitiieiiriisi Gotta ease ei tans Aba iae 8 1 Header Infornatioi estian ea a ahbeaneoanedseiayaedanlasapebodsiabsexassanltcad

Hardware Development Guide for i.MX 6SoloLite

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