Home

(TI)

1. GND jf J2 SDO ZDIFF100 P Z50 1 SMA_R_EDGE ATUR if i J3 SDO ZDIFF100 N Z50 2 SM R EDGE 4 7uF GND LAYOUT NOTE ZDIFF100_P ZDIFF100_N DIFFERENTIAL 1000HM IMPEDANCE Z250_1 Z50_2 W 40MIL ZO 50 5 SMA 3 4 inch spacing center to center Pin Mode V V HDR_3 GND HDR_3 HDRES GND SPI_EN Company Confidential Title SD384 Evaluation Board for LMH0384 National Semiconductor Size B Doc No Rev A Print Date 3 4 2009 Sheet 1 of 1 File C SD384 LMH0344 SchDoc 1 2 3 4 5 6
2. Connectors The VCC and GND power connectors should be powered with a DC input voltage of 3 3V 5 3 6V maximum SPI Mode Pin Mode Select JP1 JP4 JP1 JP2 JP3 and JP4 are used to select between SPI Mode or Pin mode To select Pin Mode set four jumpers as shown in Figure 2 and to select SPI Mode set four jumpers as shown in Figure 3 Either Pin Mode or SPI mode must be selected for proper operation do not leave JP1 JP4 open SPI MODE SPI MODE JP1 JP4 JP1 JP4 PIN MODE PIN MODE JP1 JP4 JP1 JP4 Figure 2 Pin Mode Select Figure 3 SPI Mode Select MUTErer JP5 JP5 allows control of the MUTErer function and may be used in either Pin Mode or SPI Mode MUTEger is an input voltage used to set the threshold for CD The MUTErer DC input voltage should be between OV and 3 3V Refer to the LMH0384 datasheet for details Leave JP5 unconnected for normal operation Pin Mode Controls JP6 JP8 JP6 JP7 and JP8 are used to control LMH0384 features while the device is configured for Pin Mode Jumpers should not be placed on JP6 JP7 or JP8 while the device is configured for SPI Mode CD and MUTE JP6 JP6 allows Carrier Detect CD monitoring and MUTE control CD is high when no input signal is present MUTE may be used to force the outputs on or off or tied to CD to allow automatic mute operation based on the input signal To activate mute and force the outputs into a muted condition set the jumper to pull MUTE to VCC To t
3. National Semiconduct oe sige anal N j Gary Melchior a Board September 11 2009 ser Guide Overview The SD384 Evaluation Kit EVK enables evaluation of the LMH0384 3G HD SD SDI Adaptive Cable Equalizer Evaluation Kit SD384EVK Contents The EVK contains the following parts e SD384EVK board assembly with the LMH0384 cable equalizer e SD884EVK User Guide Evaluation Board Description Figure 1 shows the SD384 evaluation board and highlights some of its features SPI Header SAI a la Carrier Detect ELE a 1 Pin Mode Controls DO NOT PLACE JP6 JPB FOR SPI MODE Bypass Auto Sleep CERAM VCE JE CD Mute LMHo3e4so vena UTOSLP CD Dials 75Q BNC we uci h US IE o i i SDI Input J ia eine f rir Connector ie er ea tee FES er N om 1 e wje Output Connectors a T 33 pa SPI Mode p Eee Pin Mode Select a se a3 JP1 JP4 JPi JP4 MUTErer DC Power Connectors Figure 1 SD384 Evaluation Board SD384 EVK User Guide 1 of 5 Rev 1 2 2009 National Semiconductor Corp SDI Input and SDO Output The SDI input connector J1 is a 75Q BNC connector The SDI input should conform to the SMPTE 424M SMPTE 292M or SMPTE 259M standards The SDO output connectors J2 and J3 are 50Q SMA connectors When using only one side of the output pair the other side should be terminated with a 50Q SMA termination For example when only using the SDO output SDO should be terminated with a 50Q SMA termination DC Power
4. ls Carrier Detect LED D1 D1 shows the status of Carrier Detect This LED is GREEN when an input signal has been detected and OFF when no input is detected D1 shows the status of Carrier Detect while in Pin Mode or SPI Mode Typical Performance Figures 4 and 5 show typical output waveforms of the SD384 with the 1m of Belden 1694A cable on the input and 110m of Belden 1694A cable on the input respectively The input signal is a 2 97 Gbps PRBS10 and the output signal is measured on the Agilent DCA J 86100C Oscilloscope lt gt File Control Setup Measure Calibrate Utilities Help 04 Jun 2009 11 29 _ 3 of 3 TP Ea gay gas E E A Maa Seale Figure 4 SD384 Output Waveform at 2 97 Gbps with 1m Belden 1694A Cable SD384 EVK User Guide 3 0f 5 Rev 1 2 2009 National Semiconductor Corp control Setup Measure Calibrate Utilities Help 04 Jun 2009 1132 158 HSI hepepebeteiepebe pelei BB mvc g 664 mwai gy 10 0 mwai gy 100mwoi Time 56 1 psz 9 Tho Patem pattem y 75 mi j 2 EELV F oov 3 oov Delay 40 5438 ns l Bit 140 l Aik Figure 5 SD384 Output Waveform at 2 97 Gbps with 110m Belden 1694A Cable Bill of Materials C2 C3 C4 Dt BNC Amphenol 75 ohm edge launch Amphenol 31 6009 Em TUF D1 zs Ao S S ea op i annam eneare O Een eoma J2 J3 2 SMA 50 ohm edge launch Components 142 0701 851 6 0 i 0 Ct 0 ze Reference Designator Qty Desc
5. ription Manufacturer Manufacturer Part No PCB Quick Fit Male Terminal 052 Keystone diameter 250 tab size Electronics 1287 ST PS1 PS2 2 R1 R2 2i a aT R4 CCCs 1 Resistor 300 ohm 1 10W 5 0402 ERJ 2GEJ301X 2 rf Resistor 75 ohm 1 16W 1 0402 RC0402FR 0775RL Capacitor 0 1uF 16V X5R 0402 Panasonic ECG ECJ 0EB1C104K Resistor 37 4 ohm 1 16W 1 0402 Vishay Dale CRCW040237R4FKED 3 5 1 1 1 1 1 2 1 1 1 National U LMH0384 Cable Equalizer LLP 16 Semiconductor LMH0384SQ Schematic SD384 EVK User Guide 4of5 Rev 1 2 2009 National Semiconductor Corp GND PS2 R4 PS1 VCC 300 vcc VCC C5 0 1uF GND SDI C2 275 3 BNC_EDGE 1uF Gs 275 4 GND 1uF LAYOUT NOTE Z75_1 W 20MIL ZO 75 5 Z75_2 W 20MIL ZO 75 5 SPI Mode Pin Mode Select JP1 JP4 JP1 VCC JP2 SPI Mode BYPASS CD D1 Kt LED HDR_ 3x2 VCC Pin Mode Controls do not place Jumpers JP6 8 for SPI Mode VCC CD MUTE MOSI CD MOSI CD V GND x D P Q D 2 E Aa S ORS BYPASS CD MUTEREF V GND BYPASS VCC JP7 GND HDR 3 BYPASS VCC C6 0 1uF GND eh LMH0384 VEE SS JP5 O O HDR_2 MUTEREF AUTOSLP MISO VCC JP8 91 E g GND HDR_3 SPI Header AUTO SLEEP JP9 GND SCK MUTE SCK MOSI MOSI MISO AUTOSLP MISO SS VEE SS GND HDR_6
6. urn off mute so that the outputs will never mute set the jumper to tie MUTE to GND For normal operation set the jumper to tie CD to MUTE for automatic mute control The LMH0384 MUTE pin has an internal pulldown to disable mute so JP6 may be left unconnected and the LMH0384 will never mute SD384 EVK User Guide 20f5 Rev 1 2 2009 National Semiconductor Corp BYPASS JP7 JP7 allows control of the equalization BYPASS function To put the device into bypass mode set the jumper to pull BYPASS to VCC To turn off bypass for normal operation set the jumper to pull BYPASS to GND The LMH0384 BYPASS pin has an internal pulldown to disable bypass so JP7 may be left unconnected for normal operation AUTO SLEEP JP8 JP8 allows control of the AUTO SLEEP function To put the device into auto sleep mode in which it will power down when no input is detected set the jumper to pull AUTO SLEEP to VCC To turn off auto sleep and prevent the LMH0384 from automatically powering down set the jumper to pull AUTO SLEEP to GND The LMH0384 AUTO SLEEP pin has an internal pullup to enable auto sleep so JP8 may be left unconnected to enable auto sleep mode SPI Header JP9 JP9 is the SPI Serial Peripheral Interface header It allows access to the SPI pins SS MISO MOSI and SCK while the LMH0384 is in SPI mode These pins may be connected to a standard SPI controller to access the LMH0384 SPI registers Refer to the LMH0384 datasheet for detai

(TI)

Contents

Download Pdf Manuals

Related Search

Related Contents