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Altera SoC Embedded Design Suite User Guide

1. Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty 8 B Fe Name Altera SocFPGA Hardwarelib FPGA CV GNU Debug type filter text E C C Application fe C C Attach to A fe C C Postmorter Select the manufacturer board project type and debug operation to use Currently selected lone V Metal E C C Remote Ap Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 4 7 DS 5 Debugger Jh Altera SoCFPG Iron Python Run a Cyclone V SoC Dual Core g Iron Python unittes 4 Bare Metal Debug E5 Java Applet Debug Cortex A9_0 O Java Application Debug Cortex A9 1 Ju JUnit Debug Cortex A9x2 SMP Jython run 2 Jython unittest Target Connection USB Blaster v amp Launch Group DTSL Options Configure USB Blaster trace or other target options Using default configurati C PyDev Django 23 PyDev Google App DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Python Run g Python unittest Connections T Remote Java Applic 5 Connection N Files 79 Debugger OS Awareness 6 Arguments PG Environment Bare Metal Debug Connection 4 m1 i Filter matched 19 of 19 iten 4 In the Select Debug Hardware dialog box select the desired USB Blaster and click OK Getting Started Guides Altera Corporation C Send Feedback 1137 4 64 Running the Hardware Library Sample Application D
2. Configure the on chip trace buffer Size 01000 The following options are available e Configure the on chip trace buffer check this if ETF is selected for trace destination on the Trace Buffer tab e Size define the ETF size By default it is set up to 0x1000 4KB but it can be set to 0x8000 32KB to match the actual buffer size ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback Embedded Command Shell 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The purpose of the embedded command shell is to provide an option for you to invoke the SoC EDS tools It enables you to invoke the SoC EDS tools without qualifying them with the full path Commands like eclipse bsp editor or arm altera eabi gcc can be executed directly On Windows the embedded command shell is started by running lt SoC EDS installation directory gt Embedded_Command_Shell bat On Linux the embedded command shell is started from the Start menu or by running lt SoC EDS installa tion directory gt embedded_command_shell sh 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera co
3. File name scatter scat 4 Click OK to close the Project Properties window Write Application Source Code 1 Go to File gt New gt Source File Getting Started Guides GJ Send Feedback Write Application Source Code 4 37 EERTE Search TestProject P File folder CPROJECT File PROJECT File SCAT Fil Altera Corporation 4 38 Write Application Source Code Figure 4 16 New Source File File Edit Source Refactor Navigate Search Project Run Window Help New Open File Close Close All Save Save As Save All Revert Move Rename Refresh Convert Line Delimiters To Print Switch Workspace Restart Alt Shift N gt Ctrl W Ctri Shift W Ctri S Ctri Shift S Ctri P 2 UBe R20 ZOMM Makefile Project with Existing Code C Project C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Template Class Other 4 Tasks E Console Properties Resource 2 Edit the file name to be test c and click Finish Altera Corporation ug 1137 2014 12 15 sm S 1 gt utline is not able Getting Started Guides GJ Send Feedback ug 1137 a1 4 12 15 Write Application Source Code 4 39 Figure 4 17 New Source File Source File Create a new source file Source folder TestProject Source file test c Template Default C source template Configu
4. Non A W N 8 9 Configure the Preloader load the next boot stage from SD MMC check BooT_FRoM_spDMMc and uncheck the other BooT_FROM options Enable Preloader FAT Support check FAT_SUPPORT Edit FAT_BOOT_PARTITION if necessary default is 1 Edit the FAT_LOAD_PAYLOAD_NAME if necessary default is u boot img Compile Preloader to make sure all the source code is available Modify file lt bsp directory gt uboot socfpga include configs socfpga_common h to have the macro CONFIG_SPL_FPGA_LOAD defined It is undefined by default If needed modify file lt bsp directory gt uboot socfpga include configs socfpga_common h to change the macro CONFIG_SPL_FPGA_FAT_NAME the default is fpga rbf Re compile the Preloader and write it to the SD card Write the RBF file to the selected FAT partition on the SD Card and using the selected file name 10 Set up MSEL accordingly and boot board Preloader Image Tool The preloader image tool creates an Altera boot ROM compatible image of the preloader The tool can also decode the header of previously generated images Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Operation of the Preloader Image Tool 7 17 The preloader image tool makes the following assumptions 1 The input file format is raw binary You must use the objcopy utility provided with the GNU Compiler Collection GCC tool chain from the Mentor Graphics
5. Create a new C project Wizards type filter text gt General Makefile Project with Existing Code E j g b E CVS b E Java gt amp PyDev 4 Continue with one of the following options 1 Select Project Type as Executable gt Empty Project and then for Toolchains select Altera Baremetal GCC Click Finish ARM DS 5 Altera Edition Altera Corporation C Send Feedback ug 1137 5 14 Creating a Project Sits Figure 5 12 Create an Empty Project with a Toolchain Selected C Project Create C project of selected type Project name TestProject Use default location Location C Workspace T estProject l CEE Choose file system default 7 Project type Toolchains a Executable RM C Empty Project ARM Compiler 6 DS 5 built in Hello World ANSI C Project Altera Baremetal GCC gt Shared Library Cygwin GCC gt amp Static Library gt Makefile project GCC for ARM Bare metal GCC 4 x arm linux gnueabihf MinGW GCC i JM 2 Select Static Library gt Empty Project and click Finish Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 201 4 12 15 Linker Script 5 15 Figure 5 13 Create an Empty Project Without a Toolchain pm E il i T a ee FPS tol bs C Project Create C project of selected type Project name TestLibrary V Use default location Location C Workspac
6. Note Starting with version 14 1 the HPS Flash Programmer supports all ONFI compliant NAND flash devices that are supported by the HPS QSPI Flash Controller HPS Flash Programmer User Guide Altera Corporation GJ Send Feedback Bare Metal Compiler 1 O 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The bare metal compiler that is shipped with the SoC EDS is the Mentor Graphics Sourcery CodeBench Lite Edition version 4 9 1 For more information on the Sourcery CodeBench Lite Edition and for downloading the latest version of the tools refer to the Mentor Graphics website www mentor com The compiler is a GCC based arm altera eabi port It targets the ARM processor it assumes bare metal operation and it uses the standard ARM embedded application binary interface EABI conventions The bare metal compiler is installed as part of the SoC EDS installation in the following folder lt Soc EDS installation directory gt host_tools mentor gnu arm baremetal The Embedded Command Shell opened by running the script from the SoC EDS installation folder sets the correct environment PATH variables for the bare metal compilation tools to be invoked After starting the shell commands like arm altera eabi gcc can be invoked directly When the Eclipse environ ment is started from the embedded command shell it inherits the environment settings and it can call these compilation tools directly Alternatively the full path to the compilatio
7. hps_isw_handoff lt hps_entity_name gt bsp Generate Libes Sseltlangs sectings bsp bsp dir Example 7 6 Generating Files After BSP Updates bsp update settings settings settings bsp set spl debug SEMIHOSTING 1 bsp generate files settings settings bsp bsp dir Use the bsp generate files tool when BSP files need to be regenerated under one of the following conditions e bsp create settings creates the PSP but the bsp dir parameter was not specified so PSP files were not generated e bsp update settings updates the PSP but the bsp dir parameter was not specified so the files were not updated e You want to ensure the BSP files are up to date Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 BSP Settings 7 9 Table 7 4 User Parameters bsp generate files opon T Rearea scription settings lt settings file gt Yes This option specifies the path to an existing BSP settings file bsp dir lt bsp dir gt Yes This option specifies the path where the BSP files are generated BSP Settings The preloader support package generator includes BSP settings for the following command options Related Information e bsp create settings on page 7 5 e bsp update settings on page 7 6 e bsp query settings on page 7 7 Command Options Table 7 5 Command Options mmaa T on bsp create settings set bsp update settings set Note When using bsp create settings or b
8. Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Debug Configuration Options 5 25 Figure 5 23 Rename Debug Configuration Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty pex eer type filter text fc C C Application fe C C Attach to Applic fc C C Postmortem Det fE C C Remote Applicat 4 7 DS 5 Debugger Ze Altera SoCFPGA Hel Je New_configuration 2 Iron Python Run Iron Python unittest E Java Applet Python Run Name AEDES A eile Select target Select the manufacturer board project type and debug operation to use Currently sele Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 4 Altera gt Arria V SoC b Cyclone V SoC Dual Core Cyclone V SoC Single Core mt q HT j Filter matched 20 of 20 items Debug Configuration Options This section lists the Debug Configuration options which allows you to specify the desired debugging options for a project e Connection Options e File Options e Debugger Options e RTOS Awareness e Arguments e Environment e Event Viewer Related Information e Getting Started Guides on page 4 1 For examples on how to use the ARM DS 5 AE debugging features e Online ARM DS 5 Documentation Refer to the DS 5 reference documentation for the complete details ARM
9. Properties Exit Getting Started Guides GJ Send Feedback Ctri W Ctri Shift W Ctri S Ctrl Shift S Makefile Project with Existing Code c Poe Pf esi C Project PS Project E Convert to a C C Project Adds C C Nature is 68 Source Folder able xX 1 ai C3 Folder E Source File ke Header File File from Template Class ry Other Yj Tasks EJ Console Properties 2 Edit the filename in Source File to be test c and click Finish Altera Corporation ug 1137 4 14 Write Application Source Code re 2 15 Source File Create a new source file Source folder TestProject Source file test c Template Default C source template 3 Edit the test c file to contain the text shown in the following image Note The __auto_semihosting symbol is a convenient way to let Debugger know that the current executable image requires semihosting services Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 XA Str O B teste x a amp 1 include lt stdio h gt 2 39 Notify debugger that gt SY Includes 4 semihosting is required gt Q test c 5 int _auto semihosting 6 7 gt int main void 8 9 printf Hello Word n 10 return 0 11 12 4 B Problems X 2 Tasks E Console Properties 0 items Description Resource A Build Application 4 15 BZV z7 3I stdio h _auto_semih main void i
10. Related Information e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Cyclone V Coresight Debug and Trace For more information about Cross Triggering refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook Cross triggering Prerequisites This section presents the preparation steps that are required in order to perform the cross triggering scenarios We boot the HPS start Signal Tap II and program the FPGA Note Any debugging scenario on HPS can be running as long as it uses a JTAG connection It does not necessarily have to be Linux It could be a bare metal program for example 1 Boot the board using the Linux SD card as shown in the Getting Started with Running Linux section 2 Connect USB cable from the USB Blaster II connection to the host PC 3 Open the Quartus SignalTap II program by running the command lt Quartus installation directory gt bin quartus_stpw This assumes you have accepted the default settings when installing SoC EDS 4 In Signal Tap II select File gt Open browse to lt SoC EDS Installation directory gt examples hardware cv_ soc_devkit_ghrd cti_tapping stp and click Open 5 In Signal Tap II on the JTAG Chain Configuration gt Hardware select the USB Blaster II Ins
11. Starting Eclipse with the Embedded Command Shell eeeseeeeeeeeeeeeeeeeeeaeeeeeeeeeees 4 73 Deb ussing the Kernel eosina ene etre ren ee rene er ee eee eee 4 73 Getting Started with Linux Application Debugging ee eeeeeeeeeseeceeeeeeeeseneeacseeasaeseeaseeeetseeees 4 78 Conr uroa Bi on ib ona N E error state rr rey Te yaar ae rere errr entre 4 78 Starting Eclipse with the Embedded Command Shell eeseseeeeeeeeeeeeeeeeeeaeeeeseeeeees 4 79 Importing the Linux Application Debugging Sample Application eeeeeeeeseeeeeees 4 79 Compiling the Linux Application Debugging Sample Application eeeeeeeeeeees 4 82 Seting p Remote System EXPlOrEY Een etre nary annT meer rs mre Ani nner errr EE verre 4 82 Running the Linux Application Debugging Sample Application ee eeeeeeeeeeeeeeeeees 4 88 Getting Started with Tracing acca artes ete cd anette aces se enn scaiep ii cous eta duces enone ee ets esteem eres 4 92 Getting Started with Cross Triggering cha a asec ie ca cstv sets iieiaeie oaiit 4 96 Cross mie eT Pre COG ICG sence tar ance eE n E R toc secvacousstenocesaesasnteeeneenasouaeetaee 4 96 Epabling Cross trie Sere on TIPS sess tice seca tact ctsceceseecgezgnctec e iaeio aea aieiaa 4 98 FPGA Triggering HPS wp 14 6 0 eee nner er ener t more Cee nit career ia aa renner 4 100 Enabling Cross triggering on FPG Pes iiscseausetecees setae teed sceuecacucssenees se ceneesee tac caseeeivenatetcnnr 4 103 HPS Tigeerng PPGA Example eeprom enmnee ny ere eet e
12. TestConfiguration type filter text aom E C C Application fe C C Attach to Application Target Configuration fe C C Postmortem Debugge Anpication on host so downloud fe C C Remote Application 4 2 DS 5 Debugger S workspace_loc TestProject Debug TestProject axf f New_configuration File System Workspace 7 Load symbols PP ees oad sym Iron Python unittest Files Java Applet T Java Application Ju JUnit 2 Jython run 2 Jython unittest Workspace Launch Group C PyDev Django 23 PyDev Google App Run Python Run Python unittest eag Remote Java Application i Filter matched 19 of 19 items This launch is associated with the DS 5 Debug perspective Do you want to open this perspective now Remember my decision 11 Application will be downloaded and stopped at entry to main function Getting Started Guides Altera Corporation C Send Feedback ug 1137 4 24 Debug Application 2014 12 15 Ble Eat Souce Relator Novigmte Seach Project Run Window Hep Deb X Pro HRe o H Com X i History Scripts BRER a es E Ex Sr amp Linked TestConfiguration B Linked TestConfiguration Continue F8 F8 a 4 R TestConfiguration connected Continuen stopped at breakpoint 1 7 wens 7 vere In test c Loca vananre S xFFFF 2 C 8 0 E File Statics current _cs3_premain 0 80 atts peted temporary breakpoint 1 r amp Globals TestConfiguration connected bio Command
13. as shown in the following example Setting values are sent to courier Example 7 4 Querying a PSP The following command will retrieve all the settings from settings bsp and displays the setting names and values bsp query settings settings settings bsp get all show names Table 7 3 User Parameters bsp query settings opn Daea Deepon See oe Yes This option specifies the path to an existing BSP settings file Do a No This option instructs bsp query settings to return the value of the BSP setting lt name gt HPS Preloader User Guide Altera Corporation C Send Feedback 7 8 bsp generate files 20 i o opon T eaea T Deerin A a No This option shows all the BSP settings values When using get a11 you must also use show names show names No This option only takes effect when used together with get lt name gt or get all When used with one of these options names and values of the BSP settings are shown side by side Related Information BSP Settings on page 7 9 bsp generate files The bsp generate files tool generates the files and settings stored in BSP settings file as shown in the following examples Example 7 5 Generating Files After BSP Creation The following command creates a settings file based on the handoff folder then generates the Preloader source files based on those settings bsp create settings type spl bsp dir settings settings bsp preloader settings dir
14. browse button b Edit the Target download directory to be home root the root folder c Edit the Target working directory to be home root the root folder Getting Started Guides Altera Corporation GJ Send Feedback TEE a ug 1137 4 90 Running the Linux Application Debugging Sample Application 2014 12 15 Figure 4 63 Target Configuration Target Configuration Application on host to download workspace loc Altera SoCFPGA HelloWorld Linux GNU hello File System Workspace Load symbols Target download directory Target working directory l 7 Click the Debug button A dialog window appears asking to switch to Debug perspective Click Yes 8 Eclipse downloads the application to the board and stops at main function entry Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 f ee Bee 2014 12 15 Running the Linux Application Debugging Sample Application 4 91 Figure 4 64 Program Downloaded DS 5 Debug Altera SoCFPGA HelloWorld Linux GNU hello c Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window HER a a AN R T aa ey GB aa Debug X Projec H Remot OB MckxX MH 6s p OVS P S Ma MMe Oly DlM Sie GD y v R Linked LinuxAppDebug_ DevKi ked LinuxAppDebug_D Working directory hom Name LinuxAppDebug_DevKit connectec DevKit ee oea set debug from main 3 amp Locals g start v Active Threads argc wai
15. gt Host working directory Use default Paths Source search directory iJ home radu altera 14 0 embedded embeddedsw soctfpga sources linux soctpga 5 Click the Debug button The debugger connects to the board stops the cores as instructed and loads the kernel symbols It determines where the cores are stopped and highlights it in the source code The following figure shows the debugger stopped in the idle instruction Getting Started Guides Altera Corporation GJ Send Feedback 4 76 Debugging the Kernel Figure 4 50 Linux Kernel Stopped ug 1137 2014 12 15 amp DS 5 Debug home radu altera 14 0 embedded embeddedsw socfpga sources linux socfpge File Edit Navigate Search Project Run Window Help cay hv EZ P a R h s a R amp Be E K A comm 2 W Histor Scripts Ex fal 7 a G Linked DebugLinux_DevKit rs Ge a Bar PE OF O Linked DebugLinux_Devkit add symbol file home radu altera 1 2 Name Vali W DebugLinux_ connected DebugLinux Devkit a E Linux Kernel Enabled Command Press S proc v7 5 3 7LENTRY cpu_v7_do idle 72 dsb 73 wi 74 mov pc Ir 75 ENDPROC cpu v7 do idle 76 77 ENTRY cpu v7 dcache clean area 78 ifndef TLB CAN READ FROM L1 CACHE dcache Line size r2 r3 mer p15 0 rO c7 c10 1 add ro r r2 subs ri rl r2 bhi 1b clean D ov karnal cunnart far wai ce for submit WFI may enter
16. wv Cyclone V SoC Dual Core gt Bare Metal Debug gt Linux Application Debug Linux Kerel and or Device Driver Debug Debug Cortex A9 0 Debug Cortex A9 1 Debug Cortex A9x2 SMP Target Connection USB Blaster DTSL Options Configure USB Blaster trace or other target options Using default configurat DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kemel 5 In the DTSL windowDTSL dialog box click Trace Buffer tab and select On Chip Trace Buffer ETF for the Trace capture method Figure 4 67 Trace Into ETF Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Trace capture method On Chip Trace Buffer ETF om Timestamp frequency 25000000 6 In the DTSL dialog box click the Cortex A9 tab and enable tracing for both cores Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 94 Getting Started with Tracing ree 2 15 Figure 4 68 Enable PTM Tracing Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Enable Cortex A9 0 trace Enable Cortex A9 1 trace O PTM Triggers halt execution Enable PTM Timestamps Timestamp period 4000 Enable PTM Context IDs Context ID Size 32 bit A O Cycle Accurate Trace capture range 7 Inthe ETF tab select the ETF to be enabled and a buffer size of 0x8000 to match the ETF size on the Cyclone V SoC which is 32 KB Figure 4 69 Configure ETF Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Confi
17. 128 KB HPS Preloader User Guide Altera Corporation GJ Send Feedback 1137 Serial NOR Flash Each QSPI boot image occupies an integer number of sectors unless subsector erase is supported this ensures that updating one image does not affect other images SD MMC The master boot record located at the first 512 bytes of the device memory contains partition address and size information The preloader and U boot images are stored in partitions of type 0xA2 Other images are stored in partition types according to the target file system format You can use the fdisk tool to set up and manage the master boot record When the fdisk tool partitions an SD MMC device the tool creates the master boot record at the first sector with partition address and size information for each partition on the SD MMC Padding The preloader image tool inserts a CRC checksum in the unused region of the image Padding fills the remaining unused regions The contents of the padded and unused regions of the image are undefined Related Information e Cyclone V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook e Arria V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook mkimage Tool The preloader verifies the mkimage header a
18. 4 12 15 Running the Bare Metal Debugging Sample Application 4 57 Figure 4 35 Program Downloaded WVZ 8 EE AE d Altera SoCFPGA HelloWorld Baremeti Altera SoCFPGA HelloWorld Bareme D C a Name A 20eC 13 0 int ma eS Locals 2vi a Deleted temporary breakpoint __cs3_premain 0x30 core 1 E argc Ui _cs3 start_c 0x8C Current core is 1 ID 1 s7 argv 7 amp File Statics current R Altera SoCFPGA G Globals gm r hello c x Ea SBT Qe CA 12 QR ee Y int main int argc char argv gt 139 d Altera SoCFPGA HelloWorld B et 14 printf Hello Tim n amaina elloWorld Baremeta 15 return T Altera SoCFPGA HelloWorld Baremetal De Altera Cyclone V SoC Dual Core 7 Click Continue green button or press F8 to run the application It displays the hello message in the Application Console Getting Started Guides GJ Send Feedback Altera Corporation l l ug 1137 4 58 Getting Started with the Hardware Library 2014 12 15 Figure 4 36 Debugging Session window DS 5 Debug Altera SoCFPGA HelloWorld Baremetal GNU hello c Eclipse Platform o een File Edit Source Refactor Navigate Search Project Run Window Help wy pr eee vi GyrQ s ae gt ad v m Quick Access FY Fie 2 x 0 FRC lt gt VX B 3 E 2 x lA I Six Sr yY w F d Altera SoCFPGA HelloWorld Baremet Altera SoCFPGA HelloWorld Bareme WARNING TAB186 Unknown sem a Name Valu
19. 8 Toggle Line Breakpoint Toggle Method Breakpoint CDT Build Console Tes lt i scatter scat aeea E A Watchpoint Skip All Breakpoints Remove All Breakpoints Breakpoint Types Manage Python Exception Breakpoints Finished building 16 32 43 Build Fi lt gt Disable Step into properties E TestProj tad TestProject Det External Tools 3 Right click DS 5 Debugger and click New Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 44 Debug Application 2014 1 2 15 Figure 4 22 New DS 5 Debugger a ee 1 a a U EA OEE S E E 7 Ta a m Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session Configure launch settings from this dialog Press the New button to create a configuration of the selected type 5 Press the Duplicate button to copy the selected configuration fe C C Attach to oe E C C Postmorte I Press the Delete button to remove the selected configuration E C C Remote A gt Press the Filter button to configure filtering options Zk DS 5 Debugger r E E Sa 2 Iron Python Ru New existing configuration by selecting it 2 Iron Python un Duplicate E Java Applet _ spective settings from the Perspectives preference page G Java Applicatio Ju JUnit 2 Jython run 2 Jython unittest k 4 Select the Target t
20. C altera 14 embedded host_tools mentor gnu arm bare Finished building target TestProject axf 13 25 12 Build Finished took 783ms he Writable 2 Go to Run gt Debug Configurations Getting Started Guides GJ Send Feedback Altera Corporation 4 18 Debug Application oS amp Str 4 E TestProject gt K Includes 4 Debug _ makefile objects mk sources mk subdir mk gt test d Fr test o TestProject axf b Q test c t es y a Writable or A test c 22 1 include lt st 2 38 Notify de 1 eA ROR Ms int _auto_s 6 7 gt int main voi 8 9 printf t 18 return 11 12 i Problems s Tasks CDT Build Console Tes DULLULNE Lar eee Invoking GCC C L E un 4 Q amp arm altera eabi ge 3 Finished building Window Help Set Next Statement Run Debug Run History Run As Run Configurations Debug History Debug As Debug Configurations Toggle Breakpoint Ctri Shift B Toggle Line Breakpoint Toggle Method Breakpoint Toggle Watchpoint Skip All Breakpoints Remove All Breakpoints Breakpoint Types Manage Python Exception Breakpoints Disable Step into properties External Tools 13 25 12 Build Finished took 783ms 4 Smart Insert 12 1 3 Right click DS 5 Debugger and click New Altera Corporation ug 1137 2014 12 15 Getting Started Guides GJ Send Feedback ug 1137 1 4 12
21. DS 5 Altera Edition GJ Send Feedback Altera Corporation ug 1137 5 26 Connection Options eee Connection Options The Connection tab allows the user to select the desired target The following targets are available for the Altera platforms Arria V SoC e Bare Metal Debug e Debug Cortex A9_0 e Debug Cortex A9_1 e Debug Cortex A9x2_SMP e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9_0 e Debug Cortex A9_1 e Debug Cortex A9x2_SMP Cyclone V SoC Single Core e Bare Metal Debug e Debug Cortex A9_0 e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9_0 Cyclone V SoC Dual Core e Bare Metal Debug e Debug Cortex A9_0 e Debug Cortex A9_1 e Debug Cortex A9x2_SMP e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9_0 e Debug Cortex A9_1 e Debug Cortex A9x2_SMP Dual Arria V SoC Two Dual Core SoCs Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Connection Options 5 27 e Bar
22. FPGA before asserting a warm reset This setting enables the reset manager to request that the Embedded Trace Router ETR stalls the Advanced eXtensible Interface AXI master and waits for the ETR to finish any outstanding AXI transactions before asserting a warm reset of the L3 interconnect or a debug reset of the ETR Altera Corporation ug 1137 7 14 Reset Assert Settings 2013 05 03 spl warm_reset_handshake SDRAM Boolean True This setting enables the reset manager to request that the SDRAM controller puts the SDRAM device into self refresh mode before asserting warm reset spl boot FPGA_MAX_SIZE Hexadec 0x10000 This setting specifies the imal maximum code text and rodata size that can fit within the FPGA If the code build is bigger than the specified size a build error is triggered OxFFFFO000 This setting specifies the base location for the data region data bss heap and stack when execute on FPGA is enabled spl boot FPGA_DATA BASE Hexadec imal spl boot FPGA_DATA MAX S1zE Hexadec imal 0x10000 This setting specifies the maximum data data bss heap and stack size that can fit within FPGA If the code build is bigger than the specified size a build error is triggered OxFFFFFD00 This setting specifies the base address for storing preloader debug information enabled with the spl debug DEBUG_MEMORY_ WRITE setting spl debug DEBUG_MEMORY_ADDR Hexadec imal spl debug
23. Figure 3 6 Add License Developer Account Details Developer account details Enter the ARM developer Silver account details Enter account details Email iD Password eeeseseseese Forgot password Click here to reset your password Don t have an account Click here to create one Caras Note The License Manager needs to be able to connect to the Internet in order to activate the license If you do not have an Internet connection you will need to write down your Ethernet MAC Altera Corporation Licensing GJ Send Feedback ug 1137 2014 12 15 Activating the License 3 7 address and generate the license directly from the ARM Self Service web page on the ARM website silver arm com then select the Already have a license option in the License Manger Note Only the Subscription Edition with an associated license number can be activated this way The Web Edition and Evaluation edition are based on activation codes and these codes cannot be used on the ARM Self Service web page on the ARM website silver arm com They need to be entered directly in the License Manager which means an Internet connection is a requirement for licensing The ARM License Manager uses the Eclipse settings to connect to the Internet The default Eclipse settings is to use the system wide configuration for accessing the Internet In case the License Manager cannot connect to the Internet you can try to change the Proxy settings by going to
24. HPS Flash Programmer Command Line Examples 2014 12 15 Short Required Description Option operation This option specifies the operation to be performed The following operations are supported e J Read IDCODE of SOC device and discover Access Port e S Read Silicon ID of the flash e E Erase flash e B Blank check flash e P Program flash e V Verify flash e EB Erase and blank check flash e BP Program lt BlankCheck gt flash e PV Program and verify flash e BPV Program blank check and verify flash e X Examine flash Note The program begins with erasing the flash operation before programming the flash by default e Yes if the start This option specifies the start address of the address isnot0 operation to be performed oR nZe B No This option specifies the number of bytes of data to be performed by the operation size is optional B ae These options must be used together The EE TE HPS BOOT flow supports up to four images where each image is identical and these options duplicate the operation data therefore you do not need eSW to create a large file containing duplicate images No repeat specifies the number of duplicate images for the operation to perform interval specifies the repeated address The default value is 64 kilobytes KB repeatand intervalare optional HPS Flash Programmer Command Line Examples Type quartus_hps help to obtain information about usage You can also type quar
25. HWLIB are expected to evolve and expand over time particularly as common use case patterns become apparent from practical application in actual systems 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN Oe RYA 101 Innovation Drive San Jose CA 95134 ug 1137 8 2 Feature Description 2014 12 15 In general the HWLIB assumes to be part of the system software that is executing on the Hard Processor System HPS in privileged supervisor mode and in the secure state
26. Help menu 2 If at any time it is required to change the license select Help gt ARM License Manager to open the License Manager Altera Corporation Licensing GJ Send Feedback ug 1137 2014 12 15 Activating the License 33 Figure 3 2 Accessing ARM License Manager Welcome to DS 5 Help Contents aP Search Dynamic Help Key Assist Ctri Shift L Tips and Tricks Cheat Sheets j a ARM License Manager ARM Extras Check for Updates Install New Software a Problems 53 J Tasks El 0 items About ARM DS 5 About Eclipse Platform 3 The License Manager View and edit licenses dialog box opens and shows that a license is not available Click the Add License button Licensing Altera Corporation GJ Send Feedback oe l ug 1137 3 4 Activating the License 2014 12 15 Figure 3 3 ARM License Manager niai e E n ell PE 7 T an TF F Cense viahnade View and edit licenses Configure licenses and diagnose licensing problems Configuration Diagnostics Delete License Select the toolkit that you intend to use Ne toolkits available 4 In the Add License Obtain a new licenses dialog box select the type of license to enter In this example select the radio button Enter a serial number or activation code to obtain a license to enter the choices listed below When done click Enter a ARM License Number for Subscription Edition b ARM License Activat
27. Line Delimiters To Print Switch Workspace Create New Project 4 7 E Convert to a C C Project Adds C C Nature GS Source Folder CS Folder amp Source File in Header File File from Template Class F Other a i Tasks El Console E A 2 Select C C gt C Project and click Next Getting Started Guides GJ Send Feedback Properties Resource butline is not able Altera Corporation ug 1137 4 8 Create New Project ve 2 15 j U ii f F u m 7 EW Frojec 4 a Be 1 Bria Peas tes EEN Select a wizard Create a new C project Wizards type filter text bp amp General a fe C C iC Project C Makefile Project with Existing Code gt amp VS b C Java gt amp PyDev Next gt Finish 3 Edit Project Name to be Test Project select Project Type to be Bare metal Executable gt Empty Project and select Toolchains to be Altera Baremetal GCC Click Finish Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Set the Linker Script 4 9 C Project Create C project of selected type V Use default location Location C Workspace TestProject Choose file system default v Project type Toolchains 4 Bare metal Executable ARM Compiler 5 Empty Project ARM Compiler 6 Hello World Project Altera Baremetal GCC b E Bare metal Library DS 5 GCC gt Execu
28. Linux Kemel and or Device Driver Debug Debug Cortex A9x2 SMP filter platforms o E vy Altera gt Aria V SoC v Cyclone V SoC Dual Core gt Bare Metal Debug gt Linux Application Debug vo Linux Kemel and or Device Driver Debug Debug Cortex A9 0 Debug Cortex A9 1 Debug Cortex A9x2 SMP gt Cyclone V Soc Single Core Target Connection USB Blaster DTSL Options Edit Configure USB Blaster trace or other target options Using default configurat DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kernel Connections 4 Click on the Debugger and perform the following steps a Select option Connect Only for Run Control b Check Execute debugger commands check box c Add the debugger commands to stop cores and load image symbols for the Linux executable as shown in the following figure d Add the path to the Linux source files on the host machine to allow the debugger to locate them Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 2014 12 15 Debugging the Kernel 4 75 Figure 4 49 Debugger Settings Run control Connect only Debug from entry point Debug from symbol O Run target initialization debugger script ds py O Run debug initialization debugger script ds py Execute debugger commands interrupt add symbol file nome radu altera 14 0 embedded embeddedsw soctpga prebuilt_images vmlinux a
29. The anticipated HWLIB clients include e Bare Metal application developers e Custom preloader and boot loader software developers e Board support package developers e Diagnostic tool developers e Software driver developers e Debug agent developers e Board bring up engineers e Other developers requiring full access to SoC FPGA hardware capabilities Feature Description This section provides a description of the operational features and functional capabilities present in the HWLIB An overview and brief description of the HWLIB architecture is also presented The HWLIB is a software library architecturally comprised of two major functional components e SoC Abstraction Layer SoCAL e Hardware Manager HW Manager SoC Abstraction Layer SoCAL The SoC Abstraction Layer SoCAL presents the software API closest to the actual HPS hardware Its purpose is to provide a logical interface abstraction and decoupling layer to the physical devices and registers that comprise the hardware interface of the HPS The SoCAL provides the benefits of e A logical interface abstraction to the HPS physical devices and registers including the bit fields comprising them e A loosely coupled software interface to the underlying hardware that promotes software isolation from hardware changes in the system address map and device register bit field layouts Hardware Manager HW Manager The Hardware Manager HW Manager component provides a group
30. Window gt Preferences gt General gt Network Connections Ensure that HTTPS proxy entry is configured and enabled 8 After a few moments the ARM Ds 5 will activate the license and display it in the License Manager Click Close Figure 3 7 ARM License Manager 6 ARM License Manager View and edit licenses Configure licenses and diagnose licensing problems Configuration Diagnostics f D i Select the toolkit that you intend to use Add License Delete License DS 5 Altera Edition Related Information e ARM website e Getting the License on page 3 1 Licensing GJ Send Feedback Altera Corporation Getting Started Guides 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback This chapter presents a series of getting started guides aimed at enabling you to quickly get accustomed to doing the basic SoC software development tasks The following items are covered e Preloader e Bare Metal debugging e SoC Hardware library HWLIB e Peripheral register visibility e Linux application debugging e Linux Kernel and driver debugging e Tracing e Cross Triggering The following additional topics are covered to support the above scenarios e Board setup needed for all the scenarios e Running Linux needed for the scenarios that use Linux The guides presented in this chapter are intedned to be run on a Cyclone V SoC Development board Getting Started with Board
31. a low poi gt SG Locals 0 var File Statics current _ y k gt O 33 Di xN E Me E Mo 5 Ev 0u 55 F Linked DebugLinux_Devkit lt Next Instru 100 Opcode Disassembly cpu v7 dcache a o l P E App Co W Target 2 SemorL O fl Ex BP B Linked DebugLinux DevKit Walting TOr Geoug server TO Start atc Debug server started successfully RA 6 To view the running threads maximize the top left panel It shows Active Threads with the two currently executing threads Also the All Threads can be expanded to show all threads in the system Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 seis Debugging the Kernel 4 77 Figure 4 51 Linux Threads 24 Debug Control a D Project Explorer w Remote Systems pe Sy 7 DebugLinux DevKit connected v 2 Active Threads v amp swapper 0 2 stopped PID 0 was running cpu _ v7 _do idle 0x gt Se swapper 1 3 stopped PID 0 was running v All Threads gt amp swapper 0 2 stopped PID 0 was running gt Ke swapper 1 3 stopped PID 0 was running gt Ke kthreadd 4 PID 2 gt a ksoftirgd O 5 PID 3 gt Ke kworker 0 0 6 PID 4 gt Ke kworker 0 0H 7 PID 5 gt te kworker u 0 8 PID 6 gt Re kworker u OH 9 PID 7 gt Ke migration O 10 PID 8 gt grcu bh 11 PID 9 gt rcu sched 12 PID 10 DebugLinux DevkKit connected
32. addr e ep n name d data_file data_file image A gt set architecture to arch 0 gt set operating system to os T gt set image type to type C gt set compression type comp a gt set load address to addr hex e gt set entry point to ep hex n gt set image name to name d gt use image data from datafile x gt set XIP execute in place mkimage D dtc_options f fit image its fit image mkimage V gt print version information and exit mkimage Tool Image Creation Example 7 7 Creating a U boot Image mkimage A arm T firmware C none 0 u boot a 0x08000040 e 0 n U Boot 2011412 for SOCFGPA board d u booct bin u boot img HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 22 mkimage Tool Image Creation 2013 05 03 Example 7 8 Creating a Bare metal Application Image mkimage A arm 0 u boot T standalone C none a 0x02100000 e 0 n baremetal image d hello_world bin hello_world img Altera Corporation HPS Preloader User Guide GJ Send Feedback Hardware Library 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The Altera SoC FPGA Hardware Library HWLIB was created to address the needs of low level software programmers who require full access to the configuration and control facilities of SoC FPGA hardware An additional purpose of the HWLIB is to mitigate the complexities of managing the operati
33. and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN Oe RYA 101 Innovation Drive San Jose CA 95134 ay ug 1137 12 2 SD Card Boot Utility 2014 12 15 SD Card Boot Utility The SoC EDS SD card boot utility is a tool for updating the boot software on an SD card The Preloader is typically stored in a custom partition with type 0xA2 on the SD card Optionally the next boot stage usually the Bootloader can also be stored on the same custom partition Since it is a custom partition without a file system the Preloader and or Bootloader cannot be updated by copying the new file to the card
34. be used directly from the makefiles without the full path 1 At the command line type eclipse amp to start Eclipse IDE used by ARM DS 5 Altera Edition See Embedded Command Shell section for more details about the shell 2 On Windows Eclipse can be started by selecting Start gt All Programs gt ARM DS 5 gt Eclipse for DS 5 On different Linux machines shortcuts may be created for starting Eclipse in a similar manner Bare metal Project Management ARM DS 5 Altera Edition enables convenient project management for bare metal projects using two different methods e Using Makefiles e Using the ARM DS 5 AE graphical interface Some users prefer Makefiles because they allow the option for the project compilation to be performed from scripts Other users prefer to use a GUI to manage the project and this is available for both GCC and ARM Compiler bare metal projects Bare metal Project Management using Makefiles ARM DS 5 Altera Edition enables convenient project management using makefiles The sample projects that are provided with SoC EDS use makefiles to manage the build process In order to allow Eclipse to manage a makefile based project a project needs to be created 1 Create a folder on the disk For example we have created the folder c sample_project 2 Create the project by selecting File gt New gt Makefile Project with Existing Code Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014
35. download Files 4 Click the Debug button to download the application to the target board 5 Select the Registers view and maximize it It shows the Core Coprocessor VFP NEON and Peripheral Registers Under the Peripherals group the DS 5 displays both the HPS peripheral registers and the Soft IP registers The figure below shows some of the HPS modules with the EMAC one expanded Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 2014 12 15 Getting Started with Peripheral Register Visibility 4 69 Figure 4 45 Peripheral Registers Peripherals acpidmap gt cand amp cani H clkmgr dap dmanonsecure H gt dmasecure gt emacd emac0_gmacgrp_MAC_Configuration emacd gmacgrp MAC Frame Filter 6 Put a breakpoint in the source code file named hwlib c at the line where the soft IP GPIO module data register is written to turn LEDs ON or OFF The breakpoint is added by simply double clicking to the left of the line number in the dialog box Getting Started Guides Altera Corporation GJ Send Feedback P kay aes ug 1137 4 70 Getting Started with Peripheral Register Visibility 2014 12 15 Figure 4 46 Breakpoint Added DS 5 Debug Altera SoCFPGA HardwareLib FPGA CV GNU hwlib c Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window Help ten a ae ne eae ee Quick Access 0 x OP 4 gt 0 Ecx EH
36. gt Linux Application Debug gt Download and Debug Application b For the Subscription Edition or 30 day Evaluation Edition select Altera gt Cyclone 5 SoC gt Linux Application Debug gt Download and Debug Application 5 In the Connection tab select the newly created RSE connection and keep the default values Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 ee a 2014 12 15 Running the Linux Application Debugging Sample Application 4 89 Figure 4 62 Connection Settings Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Application Debug Download and debug application Fiter platforms oo v Altera b Arria V SoC v Cyclone V SoC Dual Core Bare Metal Debug v Linux Application Debug Connect to already running gdbserver Download and debug application Start qdbserver and debug target resident application v DS 5 Debugger will download your application to the target system and then start a new gdbserver session to debug the application This configuration requires ssh and gdbserver on the target platform Connections RSE connection 192 168 10 119 s Address Use RSE Host gdbserver TCP port Use Extended Mode 6 Go to Files tab and set the Target Configuration parameters a Select the Application on host to download to be the hello executable file Use the Workspace
37. kernel executable file is accessible on the host computer The kernel executable for the pre built Linux image is located at lt SoC EDS installation directory gt embeddedsw socfpga prebuilt_ images vmlinux e Make sure the source code corresponding to the kernel running on the board are accessible on the host computer The sources for the pre built Linux image can be obtained by Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 4 Starting Eclipse with the Embedded Command Shell 4 73 Start Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command_ shell sh Run the following command cd lt SoC EDS installation directory gt embeddedsw socfpga sources If your computer connects to the Internet using a proxy you may need to use the following command to tell the Git utility about the proxy git config global http proxy lt proxy_name gt Run the following command git_clone sh Related Information Getting Started with Running Linux on page 4 2 For more information refer to the Getting Started with Running Linux section in this document Rocket Boards For more information about Linux and the latest source releases refer to the Rocketboards website Starting Eclipse with the Embedded Command Shell l Start an Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command_ shell sh 2 Start Eclipse by running the eclipse comman
38. lt 3 Existing Projects into Workspace O3 File System E9 Preferences lt Back Finish 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS installation directory gt embedded examples software select the file Altera SoCFPGA HelloWorld Baremetal GNU tar gz and click Open 5 Click Finish The project is imported The project files are displayed in the Project Explorer panel The following files are part of the project Table 4 1 Project Files hello c Sample application source code Altera SoCFPGA HelloWorld Baremetal GNU Launcher file used to run or debug the sample Debug launch application from within Eclipse altera socfpga hosted ld Linker script semihost_setup ds Debugger script use to load the sample application makefile Makefile used to compile the sample application Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 54 Compiling the Bare Metal Debugging Sample Application 2014 12 15 Compiling the Bare Metal Debugging Sample Application The sample application is compiled using the Mentor bare metal GCC tool chain invoked by the Makefile 1 To compile the application select the project in Project Explorer 2 Select Project gt Build Project Figure 4 32 Project Compiled C C Eclipse Platform o fee File Edit Source Refactor Navigate Search Project Run Window Help ms Eaa N HN EO adl
39. of the application to be downloaded to the target It can be entered directly in the edit box or it can be browsed for in the Workspace or on the File System e Files contains a set of files A file can be added to the set using the button and files can be removed from the set using the button Each file can be one of the following two types e Load symbols from file the debugger will use that file to load symbols from it e Add peripheral description files from directory the debugger to load peripheral register descrip tions from the SVD files stored in that directory The SVD file is a result of the compilation of the hardware project Figure 5 27 Files Settings J Connection Files gt Hi Debugger 3 OS Awareness 09 Arguments PE Environment Target Configuration Application on host to download Load symbols Debugger Options The Debugger tab offers the following configurable options e Run Control Options e Option to connect only debug from entry point or debug from user defined symbol e Option to run user specified target initialization script e Option to run user specified debug initialization script e Option to execute user defined debugger commands e Host working directory used by semihosting e Paths allows the user to enter multiple paths for the debugger to search for sources Paths can be added with button and removed with button ARM DS 5 Altera Edition Altera Corpor
40. programming and bridge releasing are not required before Linux starts running using this DTB This DTB file is intended for customers interested in bringing up a new board or just wanting to simplify their boot flow until they get to the Linux prompt If what is being developed or debugged does not involve the FPGA it is better to remove the FPGA complexities e The soc_system dtb file is based on the GHRD design which is part of the GSRD Since the GHRD does contain soft IPs this DTB notifies Linux to load the soft IP drivers Therefore the FPGA needs to be programmed and the bridges released before booting Linux Hardware and Software Development Roles Depending on your role in hardware or software development you need a different subset of the SoC EDS toolkit The following table lists some typical engineering development roles and indicates which tools each role typically requires Table 1 1 Hardware and Software Development Roles Tool Hardware Bare Metal RTOS Developer Linux Kernel and Linux Application Engineer Developer DIAA DIAO of 1e Developer y y y y y ARM DS 5 Debugging ARM DS 5 V Tracing ARM DS 5 Cross Triggering Hardware Libraries Preloader Generator Flash Programmer Bare Metal Compiler Linux Compiler Yocto Plugin Device Tree Generator lt a Introduction to SoC Embedded Design Suite Altera Corporation GJ Send Feedback ug 1137 1 4 Hardware and Software Development Role
41. source files and board specific SoC FPGA files The generator consolidates required hardware settings and your inputs to create the preloader support package The support package files include a makefile to create the preloader image you can download the preloader image to a flash device or FPGA RAM The preloader support package generator allows you to perform the following tasks e Create a new preloader support package e Report preloader support package settings e Modify preloader support package settings e Generate preloader support package files Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Hardware Handoff Files 7 3 Figure 7 2 Preloader Support Package Generator Flow User Inputs Qsys Settings e g Pin Multiplexer User Inputs Quartus Settings e g Pin Assignments Hardware Handoff Files Preloader Support Package Generator User Inputs Preloader support package settings Generate Preloader Preloader Source Support Code Package Preloader Image Related Information e BSP Settings on page 7 9 e Preloader Image Tool on page 7 16 Hardware Handoff Files Use the Qsys system integration tool in the Quartus II software to generate a set of handoff files containing the hardware information required by the preloader The handoff files from the Qsys compilation are located in the lt quartus project directory gt hps_isw_handoff lt hps entity nam
42. trees for SoC systems that contain FPGA designs created using Qsys The generated Device Tree describes the HPS peripherals selected FPGA Soft IP and peripherals that are board dependent Related Information e Altera Wiki For more information about DTG refer to the Altera Wiki website e Device Tree Generator User Guide For more details navigate to the Device Tree Generator User Guide located on the Device Tree Generator Documentation page on the Rocketboards website Altera Corporation Linux Software Development Tools GJ Send Feedback ug 1137 l 2014 12 15 Yocto Plugin 12 5 Yocto Plugin The Yocto Linux Source Package available on the Yocto Project website allows the entire Linux software stack kernel drivers device tree and root file system targeting the SoC to be built in a very simple and convenient way The Yocto Eclipse plugin fulfills the need of the application developers to be able to target the Linux software stack without requiring them to learn the details on how to build the system This enables the developers to focus on what they know best developing applications The Yocto Eclipse plugin is installed on top of the ARM DS 5 Altera Edition Documentation on how to install and use the Yocto Plugin is located on the Rocketboards website Related Information e Yocto Project For more information about the Yocto Linux source project refer to the Yocto Project website e Yocto Eclipse Plugin For more informa
43. writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN Oe RYA 101 Innovation Drive San Jose CA 95134 1137 4 2 Dual in line package DIP Switch Settings 9014 12 15 Dual in line package DIP Switch Settings e SW1 all switches OFF e SW2 all switches OFF e SW3 ON OFF OFF OFF ON ON This selects the proper FPGA configuration option MSEL e SW4 OFF OFF ON ON This selects both HPS and FPGA to be in the JTAG scan chain Jumper Settings ee ee J5 9V Open Getting Started with Running Linux This section presents how to run the provided Linux image on the board to be able to run the Getting Started sections related to Linux Note The provided Linux image is an example only use the latest version from the Rocketboards website for your development Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 l l E 2014 12 15 Getting Started with Preloader E The steps are 1 Setup the board as described in Board Setup section 2 Extract the SD card image from the archive lt SoC EDS installation directory gt embeddedsw socfpga prebuilt_images sd_card_linux_boot_image tar gz The file is named sd_card_linux_boot_image img The command tar xzf lt filename gt can be used from Embedded Command Shell to achieve this 3 Write the SD card image to a micro
44. 0 This setting specifies the location imal of the subsequent boot image in NAND spl boot FAT_ SUPPORT Boolean False Enable FAT partition support when booting from SDMMC D e When using bsp create settings or bsp update settings you must turn off the boot option that is currently turned on before you can turn on a different boot option e When using bsp editor only one of these options can be turned on at a time sp1 boot BOOT_FROM_ OSPL spl boot BOOT FROM SDMMC Or spl boot BOOT FROM RAM 2 e When using bsp create settings or bsp update settings you must turn off the boot option that is currently turned on before you can turn on a different boot option e When using bsp editor only one of these options can be turned on at a time sp1 boot BOOT_FROM_ QOSPI spl boot BOOT_FROM_SDMMC Or spl boot BOOT_FROM_RAM 3 e When using bsp create settings or bsp update settings you must turn off the boot option that is currently turned on before you can turn on a different boot option e When using bsp editor only one of these options can be turned on at a time spl boot BOOT_FROM_ QSPI spl boot BOOT_FROM_SDMMC Or spl boot BOOT_FROM_RAM Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Available BSP Settings 7 11 spl boot FAT_BOOT_PARTITION spl spl So spl SPL spl boot boot boot boot Doot boot FAT_LOAD_PAYLOAD_NAME WATCHDOG_ENABLE o CHE
45. 013 05 03 Note The options for generating the RBF file need to match the MSEL settings on the board RBF File Stored in QSPI Flash Memory The following steps are required to enable the Preloader to configure the FPGA from an RBF file stored in QSPI Flash memory l Wo Configure the Preloader load the next boot stage from QSPI Check BOOT_FROM_QSPI and uncheck the other BOOT_FROM options Generate Preloader Compile Preloader to make sure all the source code is available Modify file lt bsp directory gt uboot socfpga include configs socfpga_common h to have the macro CONFIG_SPL_FPGA_LOAD defined It is undefined by default If needed edit the file lt bsp directory gt uboot socfpga include configs socfpga_common h to modify the CONFIG SPL FPGA QSPI ADDR macro to select a different location for the RBF data in flash Re compile the Preloader and flash it to QSPI Wrap the RBF file with the mk image header This is used by the Preloader to determine the RBF file size This can be achieved by using a command similar with the following mkimage A arm T standalone C none a 0 e 0 n foga image d lt file rbf gt lt file img gt Program the wrapped RBF file to QSPI at the address CONFIG_SPL_FPGA_QSPI_ADDR Set up MSEL accordingly and boot board RBF File Stored on SD MMC Card The following steps are required to enable the Preloader to configure the FPGA from an RBF file stored on SD MMC card 1 1
46. 12 15 Open File Close Close All Save Save As Save All Revert Move Rename Refresh Convert Line Delimiters To Print Switch Workspace Restart Import Export ARM DS 5 Altera Edition C Send Feedback Alt Shift N gt Ctri W Ctri Shift W Ctri S Ctri Shift S Ctri P 2 QAOURARZA AAR Bare metal Project Management using Makefiles 33 Figure 5 1 Creating a Project with Existing Code _ Makefile Project with Existing Code C Project C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Template Class m XK i A gt utline is not able 3 Type the folder name in the Existing Code Location edit box and then click Finish Altera Corporation 5 4 Bare metal Project Management using Makefiles Figure 5 2 Import Existing Code window i j Kia g PA A _ 7 i T Mm E Import Existing Code Create a new Makefile project from existing code in that same directory Project Name sample_project Existing Code Location c sample_project Languages VIC WV C Toolchain for Indexer Settings lt none gt ARM Compiler 5 ARM Compiler 6 Altera Baremetal GCC Cygwin GCC DS 5 GCC MinGW GCC V Show only available toolchains that support this platform ug 1137 2014 12 15 4 Create a Makefile in that folder and define the rules required for c
47. 15 Debug Application 4 19 T p Y rier re r E Lt keh lean n E Hud Lor JUrAatiIons ee ee ee f Create manage and run configurations Create edit or choose a configuration to launch a D5 5 debugging session Configure launch settings from this dialog _ Press the New button to create a configuration of the selected type Press the Duplicate button to copy the selected configuration I Press the Delete button to remove the selected configuration gt Press the Filter button to configure filtering options existing configuration by selecting it Duplicate X Delet spective settings from the Perspectives preference page Eliete Java Applet GJ Java Applicatio Ju JUnit 2 Jython unittest Filter matched 18 of 18 ite 4 Select target to be Altera gt Cyclone V SoC Dual Core gt Bare Metal Debug gt Debug Cortex A9_0 and Target Connection to be USB Blaster Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 20 Debug Application re 2 15 Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty i Ral B 3 X o Name TestConfiguration r g LJ U Se Connection gt ii Files Bs Debugger i OS Awareness Arguments 9 Environment fe C C Application sana a i fe C C Attach to Application fe C C Postmortem D
48. 2 Then in the Project Properties window the Compilation settings can be accessed by selecting C C Build gt Settings ARM DS 5 Altera Edition C Send Feedback Altera Corporation 5 22 Debugging Figure 5 20 Project Settings i 7 o e E ee S Propert es for stProject lt type filter text gt Resource Builders 4 C C Build Build Variables Environment Logging Settings Tool Chain Editor C C General Project References Refactoring History Run Debug Settings Settings Configuration Debug Active v Manage Configuratio ug 1137 2014 12 15 Tool Settings Build Steps I Build Artifact n Binary Parsers Error Parsers a ARM C Compiler 5 Target Preprocessor Includes Source Language Command armcc All options 00 g Optimizations G8 Debugging Warnings and Errors Miscellaneous a ARM Assembler 5 GS Target 3 Preprocessor G8 Debugging Warnings and Errors Miscellaneous 4 ARM Linker 5 3 Target Image Layout Expert settings Command line pattern COMMAND S FLAGS S OUTPUT_FLAG S OUTF The build settings include detailed settings for all tools e Compiler e Assembler e Linker The Getting Started with ARM Compiler Bare Metal Project Management contains complete instruc tions on how to create a project from scratch compile it and run it on an Altera SoC devel
49. 37 Introduction to SoC Embedded Design Suite lt Subscribe GJ Send Feedback The Altera system on a chip SoC Embedded Design Suite EDS provides the tools needed to develop embedded software for Altera s SoC devices The Altera SoC EDS is a comprehensive tool suite for embedded software development on Altera SoC devices The Altera SoC EDS contains development tools utility programs run time software and application examples that enable firmware and application software development on the Altera SoC hardware platform Overview The Altera SoC EDS enables you to perform all required software development tasks targeting the Altera SoCs including Board bring up Device driver development Operating system OS porting Bare metal application development and debugging OS and Linux based application development and debugging Debug systems running symmetric multiprocessing SMP Debug software targeting soft IP residing on the FPGA portion of the device 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to
50. 37 4 42 Debug Application 2014 1 2 15 Figure 4 20 Console and Project Views Created Refactor Navigate Search Project Run Window Help y A la cy amp la scatter scat test c 53 oz Oo X M FF E amp x include lt stdio h gt RLR EV a amp TestProject 30 int main void s gt K Includes 4 4 Debug 5 _ makefile 6 _ objects mk A i sources mk 5 _ subdir mk 7 gt test d m stdio h a Monahan 3 main void int 2 i Problems g Tasks Console X E Properties Es fe TestProject ax 2 0l aa E Rl r gt Le test c CDT Build Console TestProject scatter scat SESSSSSSSSSSSS eS ese SSeS SSS SSSSSSSSSSs SSS SSeS SSeS SssSsssssssesseseeseseessse z Finished building target TestProject axf 16 32 43 Build Finished took 2s 172ms Debug Application 1 Setup board 2 Go to Run gt Debug Configurations Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 boas 2014 12 15 Debug Application 4 43 Figure 4 21 Debug Configurations Set Next Statement Ctri Alt R Run Ctrl Fll G i Debug F11 l scatter scat M ot a 1 include lt st Run History So 2 4 cS TestProject 30 int main voi Run As gt fay Includes 4 Run Configurations h 4 Debug printf t void int objects mk Debug As ara Debug Configurations subar gt test d Toggle Breakpoint Ctri Shift B i Problems 3 Tasks 5 _ makefile 6 return Debug History 7
51. 4 Executable Empty Project Hello World ANSI C Project b amp Shared Library b amp Static Library b Makefile project Create a Linker Script 4 29 Browse _ Choose file System default ool j Toolchains M Compiler 5 DS 5 built in ARM Compiler 6 DS 5 built in Altera Barernetal GCC Cygwin GCC GCC 4 x arm linux gnueabihf _ GCC for ARM Bare metal MinGW GCC Create a Linker Script 1 Go to File gt New gt Other Getting Started Guides GJ Send Feedback Altera Corporation 4 30 Create a Linker Script ug 1137 2014 12 15 File Edit Source Refactor Navigate Search Project Run Window Help New Alt Shift N gt Open File Close Ctri W Close All Ctri Shift W Save Ctri S Save As Save All Ctrl Shift S Revert Move Rename Refresh Convert Line Delimiters To Print Switch Workspace Restart Import Properties 1 scatter scat altera 14 1 embedded Exit Makefile Project with Existing Code C Project C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Template Class Other 5 Console E Properties A 2 Select Scatter File Editor gt Scatter File and press Next Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 201 4 12 15 Create a Linker Script 4 31 Figure 4 9 Create a Scatt
52. 4 36 Set the Linker Script mre 2 15 Figure 4 14 Settings nm he x type filter text Settings PvyaQovyv Resource Builders a C C Build Configuration Debug Active 7j Me Build Variables Environment Logging Tool Settings Build Steps I Build Artifact Settings Tool Chain Editor a X ARM C Compiler 5 Image entry point entry one reine Target RO base address ro_base Project References Preprocessor Refactoring History Includes RW base address rw_base Run Debug Settings Source Language ee ee ee Optimizations B Debugging Scatter file scatter Warnings and Errors 3 Miscellaneous a ARM Assembler 5 Target 3 Preprocessor Debugging 3 Warnings and Errors Miscellaneous 4 ARM Linker5 Target Image Layout Libraries Loe cancel 3 Select the newly created file scatter scat and click Open Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 15 Opening the Newly Created File Vl jel Ai OSDisk C Workspace TestProject gt bes Organize New folder d Downloads Name Date modified S Recent Places n Ji Debug 11 10 2014 4 10 PM cproject 11 10 2014 3 53 PM a Libraries za Libraries 11 10 2014 3 05 PM 5 Documents a Music Pictures F Videos jE Computer amp OSDisk C ca Second Drive D
53. 5 connecting to the target system The system clocks are typically set up by running the Altera preloader script Assume Cross Triggers can be accessed Trace Buffer Settings The Trace Buffer tab allows the selection of the destination of the trace information As mentioned in the introduction the destination can be one of the following e None meaning the tracing is disabled e ETR using any memory buffer accessible by HPS e ETF using the 32KB on chip trace buffer e DSTREAM using the 4GB buffer located in the DSTREAM The DSTREAM option is available only if the Target connection is selected as DSTREAM in the Debug Configuration Figure 5 34 DTSL Configuration Editor Trace Buffer gt Trace Capture Method Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Trace capture method Timestamp frequency System Memory Trace Buffer ETR On Chip Trace Buffer ETF The Trace Buffer tab provides the option of selecting the timestamp frequency Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 3014 12 15 Cortex A9 Settings 5 37 Figure 5 35 DTSL Configuration Editor Trace Buffer gt Timestamp Frequency Cross Trigger Trace Buffer gt Cortex A9 STM ETR ETF Trace capture method Timestamp frequency 25000000 Cortex A9 Settings The Cortex A9 tab allows the selection of the desired core tracing options Figure 5 36 DTSL Configuration Editor Cortex A9 Cross Trig
54. 8 aren B a kQ ws Gl Ek Sr ra SoCFPGA HardwareLib FPGA C eS ee A ih s Fi Cortex A9_0 1 stopp _ aioe T ered oo eve emporary Oreark G G gt CP15 H G VFP 4 m 3 SoCFPGA HardwareLib FPGA main W Altera SoCFP connected No OS Support Command mAs uint32_t gray i gt gt 1 i a Ene A alt write word ALT_LWFPGA BASE ALT_LWF See eee printf INFO Gray code i x x gt Ox x ii F Writable Smart Insert 298 13 7 Let the program run by clicking the green Continue button or by pressing F8 The code will stop at the breakpoint Note This ensures that when you try to access the soft IP registers they are already available If you try to access the soft IP registers before the FPGA is programmed or before the bridges are open the debugger generates a memory access abort and the debugging session fails 8 Maximize the Registers dialog box and expand the Peripherals register group 9 Scroll to the end of the list and expand the altera_avalon_pio_led_pio_s1 group It corresponds to the soft IP GPIO module that controls the FPGA LEDs on the board 10 Expand the DATA register This register contains the values that are driven on the GPIO pins to control the LEDs Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Getting Started with Peripheral Register Visibility 4 71 Figure 4 47 Soft IP Registers S DS 5 Debug Altera SoCFPGA HardwareLib FPGA CV GNU hw
55. Altera SoC Embedded Design Suite User Guide lt Subscribe ug 1137 2014 12 15 GJ Send Feedback 101 Innovation Drive San Jose CA 95134 A DTE RYa www altera com TOC 2 Contents Introduction to SoC Embedded Design Suite osoossssosssssssssssssssssssssesessssssses 1 1 ODN A cscs esac A A cre een eee ce l 1 Dere TEPA a a E E E E 1 2 Hardware and Software Development Roles ccccscessssesseseeseeseseeseeseeecsecsesseeseecsecseeaeeeeeeeseeseeaeeeesees 1 3 Hardware Software Development FIOW cccsssssssseeseesessesceseeceseesesseeecsecseeseeseseeeesseeeeeeeeesesaeeaeeneeees 1 5 Installing the Altera SoC Embedded Design Suite ccccssssssssssseeeeeeeeeeees 2 1 Tasta laton Fon cee eee ee oe een eC ee ee ee 2 1 a ecw Uh oveag de ce oye Sil Sc TO E are Ons E P E E eae meron errs 2 1 Installing the ARM DS 5 Altera Edition Toolkit eseseeeseeceeeeeecseeeeseeeseseeaeseeeeseeeeeseeeeseseeeees 2 2 BTC OTIS PING soso acetate ass vena aes ceniseiegact E E E E 3 1 ES a Yad E e 0s eer er rere E TE E N E E ern oer ere rere reer errr 3 1 aCe MM a ol Bile oy E ANEA E E ee 3 2 Geno Saared GUTES snn E E E E 4 1 Getting Started with Board SCE fs fata cares hae cst cana cet at paca ainn oep i rienda ioiei arie ee coania 4 1 External Connections sussies oraa aeaa ana aae ena ein aaas 4 1 Dwalan line package DIP Switch SettingS annserciisianieiens seien 4 2 Tiap e E A E E E E E OE scene N 4 2 Getting Starte
56. Build Application 1 Build the application by going to Project gt Build Project Getting Started Guides GJ Send Feedback Altera Corporation 4 16 Build Application B Problems X Tasks EJ Console Properties 0 items Open Project Close Project Build All Build Configurations Build Project Build Working Set Clean V Build Automatically Make Target C C Index Properties wo Description s _ Resource a FT on A ug 1137 2014 12 15 ET BE Ri BILN O vv YJ stdio h _auto_semih main void i 2 After the project is built the Console shows the commands and the Project shows the created Altera Corporation TestProject axf executable Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 eS y 4 cS TestProject gt fay Includes 4 Debug _ makefile objects mk sources mk subdir mk test d lor test o a TestProject axf gt e test c Debug Application 1 Setup board Debug Application 4 17 test c 53 EMET x gt Peno 1 include lt stdio h gt ARVO 3 Notify debugger that a 4 semihosting is required 5 stdio h 72 int main void meow 8 4 printf Hello Word n return i Problems s Tasks Console X E Properties ni m TE n n a E A a ba CDT Build Console TestProject DULLULIIB target eSLi Ujel axi a Invoking GCC C Linker arm altera eabi gcc T
57. CKSUM NZXT LTMAGE EXE_ON_FPGA o S TATH REG _ ENABLE BOOTROM_HANDSHAKE_CFGIO HPS Preloader User Guide GJ Send Feedback Decimal String Boolean Boolean Boolean Boolean Boolean l u boot img True True False True True When FAT partition support is enabled this specifies the FAT partition where the boot image is located When FAT partition supported is enabled this specifies the boot image filename to be used This setting enables the watchdog during the preloader execution phase The watchdog remains enabled after the preloader exits This setting enables the preloader to validate the checksum in the subsequent boot image header information This setting executes the preloader on the FPGA Select spl boot EXE_ON_FPGA when the preloader is configured to boot from the FPGA This setting enables writing the magic value to the INITSWSTATE register in the system manager when the preloader exists this indicates to the boot ROM that the preloader has run successfully This setting enables handshake with boot ROM when configuring the IOCSR and pin multiplexing If spl boot BOOTROM_HANDSHAKE_ CFGIO is enabled and warm reset occurs when the preloader is configuring IOCSR and pin multiplexing the boot ROM will reconfigure IOCSR and pin multiplexing again This option is enabled by default Altera Corporation 7 12 Available BSP Settings ug 1137 2013 05 03
58. Command Press Ctrl Space for Con Submit Command Press Ctrl Space for Con Submit IDS NIA M 8M BE Bo 7 70 1 include lt stdio h gt ea 2 A 30 Notify debugger that Linked TestConfiguration 4 spies tO i is aa J B lt Next Instruction gt 100 5 int _ auto 6 si main void BB App Co X W Taget Erorlog OB a printf Hello Word n B Rae Y E 7 ae Linked TestConfiguration 12 nr sf 12 Click the Continue button or press F8 The application runs to completion and exits The Application console shows the message printed by application Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Getting Started with ARM Compiler Bare Metal Project Management file Edt Source Refactor Novigte Search Pojet Bun Window Help a Deb x R5Prom ff Rew B x o z 4 Tes na y gt exi Cortex A9_0 1 application ex g No Stack R TestConf application exit code 0 No OS Support Le test c 53 1 include lt stdio h gt 2 32 Notify debugger that semihosting is required 5 int 6 72 int __auto_semihosting main void printf Hello Word n return H Micon X i Histo 4 25 me eee E 6 am gS y amp Linked TestConfiguration WARNING TAB186 Unknown semihostin Execution stopped at S xFFFF2F8 In _exit no debug info S OxFFFF2F8 SVC 0x123456 _ Application exited w
59. Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered JANOS RYAN 101 Innovation Drive San Jose CA 95134 ug 1137 9 2 Using the Flash Programmer from the Command Line 2014 12 15 The target portion is the HPS in the SoC The target accepts the programming data flash content and required information about the target flash memory device sent by the host The target writes the data to the flash memory device Figure 9 1 HPS Flash Programmer Download Cable e g USB Blaster The HPS flash programmer determines the type of flash to program by sampling the boot select BSEL pins during cold reset you do not need to specify the typ
60. D that is provided with SoC EDS Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 4 Getting Started with Preloader 2014 12 15 The Preloader is an essential tool for SoC software It performs the low level initialization brings up SDRAM memory loads the next boot stage from flash to SDRAM and executes it The Preloader is already delivered as part of the GHRD in the lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software preloader folder In this example you will re create the Preloader in the folder lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software spl_bsp The screen snapshots presented in this section were created using the Windows version of SoC EDS but the example can be run in a very similar way on a Linux host PC The steps to create the Preloader are 1 Start an Embedded Command Shell by executing lt SoC EDS installation directory gt Embedded_Command_ Shell bat 2 Run the command bsp editor The BSP Editor dialog box appears Note The tool that generates a preloader support package is the BSP Editor also used to generate BSPs for other Altera products 3 Select File gt New BSP The New BSP dialog opens 4 Click the button to browse for the Preloader settings directory in the New BSP dialog box 5 Browse lt SoCEDS folder gt examples hardware cv_soc_devkit_ghrd hps_isw_handoff soc_system_hps_0 for the hardware ha
61. DEBUG_MEMORY_SIZE Hexadec imal 0x200 This setting specifies the maximum size used for storing preloader debug information Related Information Reset Assert Settings on page 7 14 Reset Assert Settings Table 7 7 spl reset_assert lt peripheral_name gt BSP Setting Default Value spl reset_assert DMA False spl reset_assert GPIOO False text and rodata are default memory sections defined by the linker tool in the GCC tool chain data and bss are default memory sections defined by the linker tool in the GCC tool chain data and bss are default memory sections defined by the linker tool in the GCC tool chain Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Preloader Compilation 7 15 BSP Setting Default Value spl spl spl spl spl spl spl reset_assert GPIOl False reset_assert GPIO2 False reset_assert L4wDl False reset_assert OSCLTIMER1 False reset_assert SDR False reset_assert SPTIMERO False reset_assert SPTIMER1 False Preloader Compilation The makefile created by the PSP generator compiles the preloader sources and generates a preloader image The makefile performs the following tasks e Copies the generic preloader source code into lt bsp directory gt uboot socfpga e Copies the generated BSP files and hardware handoff files to the source directory in lt bsp_directory gt uboot socfpga board altera socfpga_ lt device gt e Configures the c
62. Documentation Starting Eclipse Eclipse is the IDE used by ARM DS 5 Altera Edition and it can be started from the Embedded Command Shell or from the windows file menu selection trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are ISO 9001 2008 Registered JA DTE RYA ug 1137 5 2 Bare metal Project Management 2014 12 15 The advantage of starting Eclipse from the Embedded Command Shell is that all the utilities are added to the search path and they can
63. ETR settings allow the configuration of the Embedded Trace Router ETR settings The Embedded Trace Router is used to direct the tracing information to a memory buffer accessible by HPS Figure 5 38 DTSL Configuration Editor ETR Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Configure the system memory trace buffer Start address Ox100000 Size Ox8000 M Enable scatter gather mode The following options are available e Configure the system memory trace buffer check this if the ETR is selected for trace destination on the Trace Buffer tab e Start Address Size define the trace buffer location in system memory and its size e Enable scatter gather mode use when the OS cannot guarantee a contiguous piece of physical memory The scatter gather table is setup by the operating system using a device driver and is read automatically by the ETR Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 ETF Settings 5 39 ETF Settings The ETF tab allows the configuration of the Embedded Trace FIFO ETF settings The Embedded Trace FIFO is a 32KB buffer residing on HPS that can be used to store tracing data to be retrieved by the debugger but also as an elastic buffer for the scenarios where the tracing data is stored in memory through ETR or on the external DSTREAM device using TPIU Figure 5 39 DTSL Configuration Editor ETF Cross Trigger Trace Buffer Cortex A9 STM ETR ETF
64. FPGA is programmed the SignalTap II will be ready to acquire Getting Started Guides Altera Corporation GJ Send Feedback 1137 4 98 Enabling Cross triggering on HPS 9014 12 15 Figure 4 75 Signal Tap Ready to Acquire SignalTap II Logic Analyzer home radu altera 14 0 embedded examples hardware cv_soc devkit_ ghrd sc O x File Edit View Project Processing Tools Window Help wild 9e l s Hi r gt e Instance Manager a Ready to acquire x JTAG Chain Configuration JTAG ready E etaa Sad Enabled LEs 587 4 Hardware USB Blasterll 1 1 3 3 auto signaltap 0 Not running 587 cells 1 Device 2 5CSEBAG ES S5CSEMA6 SOF Manager but_files soc_system sof cal Search altera com ET trigger 2013 08 29 10 20 24 1 Lock mode Allow all changes signal Configuration Node Data Enable rigger Enabi Trigger Conditions o o tMBasicANe oo ipga ipsw pif V ipga psw po VO Ea pga _aipsw poz S gger position S maap TS moa ter pitt v v amp Trigger conditions poa ted po aes monea M E nce instjaata out A Opi nce instaat outs I bata a setup 8 auto signaltap 0 Nodes Allocated Auto O Manual Trigger flow control Al RD S A 0 00 00 00 Related Information Getting Started with Running Linux on page 4 2 For more information refer to the Getting Started with Running Linux section in this document E
65. IB_STACKHEAP 0 EMPTY 6x4000 td _Regions Sections scatter scat 5 The file can also be edited by using the tools on the Outline view for the file ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback ug 1137 5 20 Build Settings aie Figure 5 18 Editing Scatter scat File Using Tools on the Outline View Ss o scatter scat c test c 4 y 4 cS TestProject gt EP Includes 3 a oE APP_CODE J amp Debug RO RW ZI oO RO RW ZI _ makefile ARM IIR STACKHEAP _ objects n Add load region D sources r lication a e AeL de Add execution region subdir m B test d Add section or test o Rename oi TestProje gt Le test c scatter scat Delete i Problems Tasks EJ Console Properties J Commands X B Linked no current context v No debugger is currently connected Build Settings 1 Once the project is created the project properties can be accessed by going to Project gt Properties Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Figure 5 19 Project Properties a TestProject gt K Includes Open Project Close Project Build All Build Configurations Build Project Build Working Set Clean Build Automatically Make Target C C Index Properties 2 Problems X Tasks EJ Console Properties 0 items Description Resource Build Settings An outline is not available 5 21
66. Installing the ARM DS 5 Altera Edition Toolkit 2014 12 15 5 Select All the components to be installed and click Next The installer displays a summary of the installation Click Next to start the installation process The installer displays a separate dialog box with the installation progress of the component installation When the installation is complete turn on Launch DS 5 Installation to start the ARM DS 5 installa tion and click Finish Note On some Linux based machines you can install the SoC EDS with a setup GUI similar to the Windows based setup GUI Because of the variety of Linux distributions and package require ments not all Linux machines can use the setup GUI If the GUI is not available use an equivalent command line process Download the Linux installation program from the SoC Embedded Design Suite page on the Altera website Installing the ARM DS 5 Altera Edition Toolkit For the last step of the SoC EDS installation process start the ARM DS 5 AE Toolkit installer Note Make sure you have the proper setting to access the internet i Z 3 ON A up Altera Corporation When the Welcome message is displayed click Next Accept the license agreement and click Next Accept the default installation path to ensure proper interoperability between SoC EDS and ARM DS 5 AE and click Next Click Install to start the installation process The progress bar is displayed When a driver installati
67. J Send Feedback Altera Corporation ug 1137 2014 12 15 Figure 4 58 Enter Target IP Address Setting up Remote System Explorer 4 85 New Connection Remote SSH Only System Connection Define connection information Parent profile radu Host name 192 168 10 119 Connection name 192 168 10 119 Description W Verify host name Configure proxy settings Cancel Finish 6 In the Remote Systems panel click the Target IP gt Sftp Files gt Root This opens a dialog box to enter the username and password Getting Started Guides Altera Corporation GJ Send Feedback l ug 1137 4 86 Setting up Remote System Explorer 2014 12 15 Figure 4 59 Browse Target Remote System Explorer Eclipse Platform File Edit Navigate Search Project Run Window Help ja soe es dh Quick Access Jt ag m El 28 Remote Systems 8 amp Team z D 7 o 7 p An outline is H gt n not available 2 lt v Fy 192 168 10 119 v Sftp Files gt gt My Home Ex Ssh Shells 2 Ssh Terminals Remote System X JY Tasks B Properties X Remote Scra gt L File filter Root 7 Assign root to User ID and assign the password you selected in the Configuring Linux section to Password Select the Save User ID and Save password check boxes Click OK Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 l TE 2014 12 15 Setting up Remote System Explorer Fi
68. Linux Kemel Enabled 7 Minimize the Debug Control panel and maximize the Functions panel from top right All of the functions in the kernel are displayed The Functions panel supports the following operations for each function Run up to the function Set PC to function Locate in source code memory or disassembly Set breakpoints to software or hardware Set trace points to enable disable or toggle 8 Select Modules panel to view the currently loaded modules In the example below only the ipv6 module is loaded 9 Add breakpoints at the module load and module unload functions As modules are loaded with insmod and removed with rmmod the DS 5 AE will reflect the changes cao oT Getting Started Guides Altera Corporation GJ Send Feedback PE ug 1137 4 78 Getting Started with Linux Application Debugging 2014 12 15 Figure 4 52 Kernel Debugger Breakpoints Var e Br amp m Re Ex f Fu 2 Linked DebugLinux DevkKit S 0x8007F3F4 SyS delete module Debug 5 0 60081490 Sy5S_init_module Debugger gt Getting Started with Linux Application Debugging The ARM DS 5 Altera Edition provides very powerful Linux application debugging capabilities This section presents running the ARM DS 5 Altera Edition for the first time importing compiling and running the Hello World Linux example application provided as part of SoC EDS Note This section uses a Linux host computer as can b
69. RD including e FPGA hardware project e FPGA hardware SOF file e Precompiled preloader Embedded command shell allowing easy invocation of the included tools e SD Card Boot Utility e Yocto Eclipse plugin Quartus II Programmer and SignalTap II Note The Linux package included in the SoC EDS is not an official release and is intended to be used only as an example Use the official Linux release described in the Golden System Reference Design GSRD User Manual available on the Rocketboards website or a specific release from the Git trees located on the Gitweb page of the Rocketboards website for development Note The SoC EDS is tested only with the Linux release that comes with it Newer Linux releases may not be fully compatible with this release of SoC EDS Note The Golden Hardware Reference Design GHRD included with the SoC EDS is not an official release and is intended to be used only as an example For development purposes use the official GHRD release described in the GSRD User Manual available on the Rocketboards website Related Information RocketBoards Website Device Tree Binary There are two device tree binary DTB files delivered as part of the SoC EDS Altera Corporation Introduction to SoC Embedded Design Suite GJ Send Feedback ug 1137 ae 2014 12 15 Hardware and Software Development Roles 5 e The socfpga_cyclone5 dtb file is a generic DTB file which does not have any dependency on soft IP FPGA
70. ROM_RAM BOOT_FROM_NAND QSPI_NEXT_BOOT_IMAGE BOOT_FROM_RAM QSPI_NEXT_BOOT_II SDMMC_NEXT_BOOT_IMAGE SDMMC_NEXT_BOOT NAND_NEXT_BOOT_ NAND_NEXT_BOOT_IMAGE FAT_SUPPORT FAT_BOOT_PARTITII E FAT_SUPPORT FAT_LOAD_PAYLOAL EAT BOOT PARTITION Advanced a FAT_LOAD_PAYLOAD_NAME 0x60000 0x40000 0xc0000 4 u bootimg Information Problems Processing Searching for BSP components with category driver_element Searching for BSP components with category software_package_element Added operating system component spl 1 0 7 Click Generate in the BSP Editor dialog box to generate the Preloader files 8 Click Exit in the BSP Editor dialog box to exit the application 9 In the Embedded Command Shell execute the following commands e cd lt SoC EDS installation directory gt examples hardware cv_soc_devkit_ghrd software spl_bsp e make 10 The Preloader is ready to be used in the above folder Some of the more relevant files that are created e preloader mkpimage bin Preloader with the proper header to be loaded by BootROM e uboot socfpga spl u boot spl Preloader ELF file to be used for debugging purposes e uboot socfpga tools mkimage exe Utility to add the header needed by the Preloader to recognize the next boot stage Related Information e Preloader For more information about the Preloader refer to the Preloader section Getting Started Guides GJ Send Fee
71. SD card using the free tool Win32DiskImager from the Sourceforge Projects website sourceforge net on Windows or the dd utility on Linux 4 Power up the board using the PWR switch 5 Connect a serial terminal from the host PC to the serial port corresponding to the UART USB connection and use 115 200 baud no parity 1 stop bit no flow control settings 6 After successful boot Linux will ask for the login name Enter root and click Enter Figure 4 1 Linux Booted a radu sudo File Edit View Scrollback Bookmarks Settings Help itc udncpc d ult Adding DNS 192 168 10 1 Starting portmap daemon Wed Apr 16 05 33 00 UTC 2014 INIT Entering runleve starting OpenBSD Secure e j al JI s Pi CECE aftafa F 7 m Fe Fi E Y n i F LJ i Fh a E B E a r 1 k j a gt thi or Lat ca Lor i L of LI Ph he LJ B ME h 1 hlinkinoa LED cerve d er ho oe a r am Fh F j pa a Bootloa daemon Project socfpga login root mn eS Fp root socTpga radu sudo Related Information e Rocket Boards For more information about the latest Linux version refer to the Rocketboards website e Sourceforge Projects To obtain the free tool Win32DiskImager refer to the Projects section of the Sourceforge website Getting Started with Preloader This section presents an example of how to generate and compile the Preloader for the Cyclone V SoC Golden Hardware Reference Design GHR
72. SP DOO WARMRST SKIPT EFGTO spl boot SDRAM_SCRUBBING S SOOr oD RAM cer UE me OO TAREGIONS gt TART spl boot SDRAM SCRUB_BOOT_REGION_ END spl boot SDRAM SCRUB_REMAIN_ REGION spl debug DEBUG_MEMORY_WRITE spl debug SEMIHOSTING Boolean Boolean Hexadec imal Hexadec imal Boolean Boolean Boolean True False 0x 1000000 0x2000000 True False False This setting enables the preloader to skip IOCSR and pin multiplexing configuration during warm reset spl boot WARMRST_SKIP_CFGIO is only applicable if the boot ROM has skipped IOCSR and pin multiplexing configuration Scrub SDRAM to initialize ECC bits The start address of the memory region within SDRAM to be scrubbed The end address of the memory region within SDRAM to be scrubbed Scrub the remaining SDRAM during the flash accesses to load the image This setting enables the preloader to write debug information to memory for debugging useful when UART is not available The address is specified by spl debug DEBUG_ MEMORY_ADDR This setting enables semihosting support in the preloader for use with a debugger tool spl debug SEMIHOSTING is useful when UART is unavail able Refer to the ARM Infocenter for more information on semihosting 4 SDRAM Scrubbing must be enabled in the Preloader Support Package Generator whenever the SDRAM ECC is enabled for the hardware project in Qsys Alternatively the user so
73. Select Scatter File Editor gt Scatter File and press Next Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Linker Script 5 17 Figure 5 15 Creating a Scatter File ae kh Select a wizard Create a scatter file Wizards He gt gt General gt gt C C gt G CVS b amp DS 5 Configuration Database b DS 5 Debugger 4 gt DS 5 Platform Configuration Editor Platform Configuration File b amp Java gt amp PyDev gt Remote System Explorer 4 amp Scatter File Editor Scatter File b amp Target Configuration Editor 3 Select the location of the new file type in the file name and press Finish ARM DS 5 Altera Edition C Send Feedback Altera Corporation Altera Corporation 5 18 Linker Script Figure 5 16 Create a New Scatter File Resource rN Scatter File Create a new scatter file resource TestProject i Es G Enter or select the parent folder 5 i gt RemoteSystemsTempFiles 4 cS TestProject 2 Debug 4 The linker script file can be edited directly as shown in the example below File name _ scatter scat ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 ug 1137 9014 12 15 Linker Script 5 19 Figure 5 17 Linker Script Example E scatter scat 3 o p 1S OCRAM OxFFFF0000 0x10000 APP_CODE 0 RO RW ZI Application heap and stack ARM_L
74. Setup This section presents the necessary Altera Cyclone V Development Kit board settings in order to run Linux and the Getting Started examples External Connections e External 19V power supply connected to J22 DC Input e Mini USB cable connected from host PC to J37 Altera USB Blaster II connector This is used for connecting the host PC to the board for debugging purposes e Mini USB cable connected from host PC to J8 UART USB connector This is used for exporting the UART interface to the host PC e Ethernet cable from connector J3 to local network This is used if Linux network connectivity is desired 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in
75. These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Linux Kernel and Driver Developer As a Linux kernel or driver developer you may use the same tools the RTOS developers use because you need low level access and visibility into the system However you must use the Linux compiler instead of the bare metal compiler You can use the Yocto plugin to manage the project and the device tree generator to generate device trees These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Linux Application Developer As a Linux application developer you write code that targets the Linux OS running on the board Because the OS provides drivers for all the hardware you do not need low level visibility over JTAG DS 5 offers a very detailed view of the OS showing information such as which threads are running and which drivers are loaded You can use the Yocto plugin to manage the application build These tasks do not require JTAG debugging You can perform them both in the Web and Subscription editions For more information see the Licensing section Related Information Licensing on page 3 1 For more information about svd files refer to the Hardware Software Development Flow section Altera Corporation Introduction to SoC Embedded Design Suite GJ Send Feedback ug 1137 Sree Hard
76. UL eeeseeseseeeeseceeeseeeseeeeeeseeeseeeeeees 7 3 Preloader Support Package Files and Folders eesssseesseceseeeesceceecseeeesceeeeeseeesseeeeeseeeeseeees 7 4 Command Line Tools for the Preloader Support Package Generatol eeseeseeeeeeseeeeeees 7 5 Be NS E AA A I sand en sate A T EA A E T T 7 9 Preloader Comp ua O eera ner E E E E E E Waseeeene 7 15 Conligurne FPGA froi Preloader semiasi oiiaaie Eae REE 7 15 RBF File Stored 1m OSPI Flash MemO ry sccsesececcacaesectaxepcacsteserceidverneteteceundetencniacnesrecasasesetateacs 7 16 RBF Tie Stored oni SD MMC Caid sesiis een Tar ene mee reer eee reer errs er eens ree 7 16 Picloader Image TOO lorera a E E ere eee eee eee eee eee 7 16 Operation of the Preloader Image TOOL esisciiisopirtiinscnneenreaniiannn nienean ieina ieaiai 7 17 UE SA E E A EA T P A E E A T ees 7 18 OUT DUC igge Layo cessarono a a a E E AERE a A R Ra 7 19 ON alia Baroda Eo PPE E N A T E A EAE 7 20 mmage Tool Opio NS aiseee aE E E E er are ae E E 7 21 Hkimage Lool Image Cred Olaann uii iai Neia EEA a Ea RN 7 21 Hardware LID ANY eenen EE E EE E TE EE 8 1 ae AD E e U0 a E E E A N E A E E T E E emer e 8 2 S0C AbDsifaction Layer SOCAL sscrsreiesireiesir erered ceaneieen diiran raie e naei Erer ei seara eieiei E Ri 8 2 Hardware Manager HW Manager ssssssssssssceseseesesceeessececesceeescseeeesceceesscaeseeeeacseeaseeseeaeeeeas 8 2 Hardware Library Reference Documentation eceieesssssssesseceseecessesesceseeeesecese
77. a Debug launch tion from within Eclipse Getting Started Guides Altera Corporation GJ Send Feedback 4 62 Compiling the Hardware Library Sample Application ee ey altera socfpga hosted ld Linker script debug hosted ds Debugger script use to load the sample application Makefile Makefile used to compile the sample application Compiling the Hardware Library Sample Application 1 To compile the application select the project in Project Explorer 2 Select Project gt Build Project 3 The project compiles and the Project Explorer shows the newly created hwlib axf executable file as shown in the above figure The Console dialog box shows the commands and responses that were executed Figure 4 39 Project Compiled E i C C us Eclipse Platt or mn go as File Edit Source Refactor Navigate Search Project Run Window Help Tor E eh GM ay B Or rH OKA Vie yr a gt ie x S Quick Access i m Ea a a oo gt A oOo 2 F BS Y 4 gt Altera SoCFPGA Hardw An outline is not gt K Includes available gt alt_address_space c A alt_bridge_manager gt alt_cache c y oe niini pinin Problems 5 Tasks EJ Console 53 E Properties a X alt_dma_program c L S PERE E Blee Bri alt_dma c CDT Build Console Altera SoCFPGA HardwareLib FPGA CV GNU gt alt_fpga_manager c arm altera eabi objcopy treating that number as an absolute e machi g g 8 2 A hwlib c arm altera eabi objdump d hwlib axf gt h
78. al Debug Files 7 Debugger fs OS Awareness Arguments PG Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 a Cyclone V SoC Dual Core 4 Bare Metal Debug Debug Cortex A9_0 Debug Cortex A9_1 Debug Cortex A9x2 SMP Target Connection DTSL Options DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections Bare Metal Debug Connection Configure USB Blaster trace or other target options Using default configurati 4 Altera Corporation l ug 1137 4 56 Running the Bare Metal Debugging Sample Application 2014 12 15 Figure 4 34 Select Debug Hardware Connection Browser Select a target connection US6 Blasterll USB 1 USB Blasterll on localhost USB 1 5 Click the Debug button from the bottom of the Debug Configurations dialog box 6 Eclipse ask whether to switch to Debug Perspective Click Yes to accept it The debugger downloads the application on the board through JTAG enables semi hosting using the provided script and runs the application until the PC reaches the main function At this stage all the debugging features of DS 5 can be used viewing and editing registers and variables looking at the disassembly code Getting Started Guides GJ Send Feedback Altera Corporation 1137 E
79. alization then the target may lock up The folllowing option should only be set if you are sure that the system clocks have been initialized prior to DS 5 connecting to the target system The system clocks are typically set up by running the Altera preloader script Assume Cross Triggers can be accessed In order to allow FPGA cross triggers to trigger HPS you need to e Check the Enable FPGA gt HPS Cross Triggering check box e Check the Assume Cross Triggers can be accessed check box Getting Started Guides GJ Send Feedback Altera Corporation 1137 4 100 FPGA Triggering HPS Example 9014 12 15 In order to allow HPS cross triggers to trigger FPGA you need to e Check the Enable HPS gt FPGA Cross Triggering check box e Check the Assume Cross Triggers can be accessed check box Note In order to enable bi directional triggering you can check all three checkboxes FPGA Triggering HPS Example This section presents an example on how FPGA can trigger HPS to stop the execution This can be useful if you want to see what the HPS is doing at the moment the trigger comes from FPGA The required steps are to reproduce this scenario are 1 Perform the steps from the Cross triggering Prerequisites section 2 Open the Debugger configuration and edit DTSL options to enable FPGA cross triggering HPS as shown in the Enabling Cross triggering on HPS section a Check the Enable FPGA gt HPS Cross Triggering check box b Un check t
80. and a software tool is needed The SD card boot utility allows the user to update the Preloader and or Bootloader on a physical SD card or a disk image file The utility is not intended to create a new bootable SD card or disk image file from scratch In order to do that it is recommended to use fdisk on a Linux host OS Usage Scenarios This utility is intended to update boot software on that resides on an existing e Existing SD card e Existing disk image file You can choose from these three usage scenarios e Update just the Preloader software e Update just the Bootloader software e Update both Preloader and Bootloader software In the context of this tool the term Bootloader simply means the next boot stage from Preloader In some usage scenarios it can be a bootloader while in other scenarios it could be a bare metal application or even an OS Note The Preloader file needs to have the mkpimage header as required by the BootROM and the Bootloader file needs to have the mkimage header as required by the Preloader Both mkpimage and mkimage tools are delivered as part of SoC EDS The tool only updates the custom partition that stores the Altera SoC boot code The rest of the SD card or disk image file is not touched This includes the Master Boot Record MBR and any other partitions FAT EXT3 etc and free space Warning The users of this tool need administrative or root access to their computer to use this tool to wri
81. andbook Appendix A Booting and Configuration For information about how the boot ROM loads preloader images refer to Boot ROM Flow in the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook e Arria V Device Handbook Appendix A Booting and Configuration For information about how the boot ROM loads preloader images refer to Boot ROM Flow in the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook Address Alignment Every preloader image aligns to a 64 KB boundary at offsets 0x0 0x10000 0x20000 and 0x30000 except for the NAND flash Version 0 of the boot ROM assumes that all preloader images in flash memory align to 64 KB boundaries except in the case of NAND flash If the preloader images are stored in NAND flash with an erasable block size larger than 64 KB preloader images are aligned to the block size The preloader image tool is unaware of the target flash memory type If you do not specify the block size the default is 64 KB NAND Flash Each preloader image occupies an integer number of blocks A block is the smallest entity that can be erased so updates to a particular boot image does not impact the other images The size of a single preloader image sizing is either 64 KB or the NAND flash block size whichever is larger For example if a NAND block is 32 KB or 64 KB a single preloader image size is 64 KB if a NAND block is 128 KB a single preloader image size is
82. argv status 4 mA zE Qe p G Ex BBY tera SoCFPGA HardwareLib FPGA CY 7 Click Continue green button or press F8 to run the application It displays a log of activities it performs in the Application Console Getting Started Guides GJ Send Feedback Altera Corporation 4 66 Running the Hardware Library Sample Application ug 1137 2014 12 15 Figure 4 43 Application Completed INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO INFO Gray Gray Gray Gray Gray Gray Gray Gray Gray Gray G ray aray Gray LEDs T sole fi o Target Console Error Log al Ek BE og Linked Altera 50CFPGA HardwareLib FPGA CV GNU Debug code i x3 gt code i x4 gt code i x5 gt code i x6 gt code i x7 gt code i x8 gt code i x9 gt code i xa gt code i xb gt code i xc gt code i xd gt code i xe gt code i xT gt x Ox 6x5 bx xc xd Oxf exe Axa xb Ax 6010 0110 0111 0101 0106 1160 1161 1111 1116 1010 1011 1601 1006 should have blinked Cleanup of Bridge 2 Cleanup of FPGA Cleaning up DMA System RESULT Example completed successfully 8 Click Disconnect from Target button to close the debugging session Sequence Sample Application Function 2 Altera Corporation Used Hardware Descriptio
83. ating a New Debug Configuration A Debug Configuration is created in the Debug Configurations window by selecting DS 5 Debugger as the type of configuration in the left panel and then right clicking with the mouse and selecting the New menu option ARM DS 5 Altera Edition Altera Corporation C Send Feedback ug 1137 5 24 Creating a New Debug Configuration ree 2 15 Figure 5 22 Create New Debug Configuration A Tia ARR a MEN main ai e EEn 1 Vebpug Lontigurations Ta ee ie icaiietllaldh gies haat heen bee eatin Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session Configure launch settings from this dialog type filter text C Press the New button to create a configuration of the selected type E C C Applicatic Press the Duplicate button to copy the selected configuration fe C C Attach to C C Postmorte fe C C Remote A gt Press the Filter button to configure filtering options New or view an existing configuration by selecting it ca Iron Duplicate Javad X Delete launch perspective settings from the Perspectives preference page D Java Appreecronre Ju JUnit a Jython run Jython unittest i Filter matched 19 of 19 ite I Press the Delete button to remove the selected configuration The Eclipse IDE will assign a default name to the configuration which can then be edited by you
84. ation GJ Send Feedback ug 1137 5 32 RTOS Awareness sai Figure 5 28 Debugger Settings E Connection ie Files Bi Vebugg Tiia OS Cree ess x Arguments PS teen Run control O Connect only Debug from entry point Debug from symbol main Run target initialization debugger script ds py File System Workspace C Run debug initialization debugger script ds py File System Workspace Execute debugger commands Host working directory Use default S workspace_loc File System Workspace Paths Source search directory 5 RTOS Awareness The RTOS Awareness tab allows the user to enable Keil CMSIS RTOS RTX awareness for the debugger in case that specific RTOS is used Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Arguments 5 33 Figure 5 29 RTOS Awareness Settings Name Sample Configuration I Connection T Files i Debugger fap OS Awareness k Arguments Environment Select OS awareness f FreeR TOS Keil CMSIS RTOS RTX ThreadX embOS pC OS 1 uC OS H Related Information Keil Website For more information about RTOS Awareness refer to the Embedded Development Tools page on the KeilTM website Arguments The Arguments tab allows the user to enter program arguments as text Figure 5 30 Arguments Settings Name Sample Configuration 4
85. ava Applet OJ Java Application Ju JUnit 2 Jython run E Jython unittest Launch Group idj PyDev Django Files Load symbols from file v kinisas 23 PyDev Google App Run e Python Run g Python unittest ral Remote Java Application lt w Filter matched 19 of 19 items 10 Eclipse will ask whether to switch to the Debug perspective Accept by clicking Yes Figure 4 28 Confirm Perspective Switch This launch ts associated with the D5 5 Debug perspective Do you want to open this perspective now Remember my decision 11 The application will be downloaded and stopped at entry to main function Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 4 50 Debug Application re 2 15 Figure 4 29 DS 5 Debug Window cn OL a SS BB Hist Sci D V 5 B ix Sr ay Linked TestConfiguration amp Linked TestConfiguration er Name Vi r g a Locals 0 vai Command Press Ctri Space for C Fe a e S WD X SM A E scatter scat test c 3 1 include lt stdio h gt 2 39 H main void 4 printf Hello World n B App X ETa O Ero E Con P 5 return g B bE amp Linked TestConfiguration Linked TestConfiquration 4 R TestConfiguration connected Altera Cyclone V SoC Dual Core 12 Click the Continue button or press F8 The application will run to completion and exit T
86. back l ug 1137 4 60 Importing the Hardware Library Sample Application 2014 12 15 Figure 4 37 Import Existing Project Create new projects from an archive file or directory Select an import source type filter text gt General JIE Archive File G Existing Projects into Workspace G File System ES Preferences 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS installation directory gt embedded examples software select the file Altera SoCFPGA HardwareLib FPGA CV GNU tar gz and click Open Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 E 4 12 15 Importing the Hardware Library Sample Application 4 61 Figure 4 38 Select Imported File Select a directory to search for existing Eclipse projects O Select root directory q Select archive file C altera 14 0 embedded examples softwar Projects Altera SoCFPGA HardwareLib FPGA CV GNU Altera SoCFPGA F Options v Search for nested projects v Copy projects into workspace Working sets Add project to working sets AJF j Working sets 5 Click Finish The project will be imported The project files will be displayed in the Project Explorer panel The following files are part of the project Table 4 2 Project Files hwlib c Sample application source code Altera SoCFPGA HardwareLib GNU Launcher file used to run debug the sample applic
87. baremetal arm altera eabi lib cycloneV dk oc ram hosted ld select cycloneV dk oc ram hosted 1d and click on the Open button This will instruct the Linker to use a linker script that targets the 64 KB Internal RAM and also to use semihosting operations Getting Started Guides GJ Send Feedback Altera Corporation 4 12 Write Application Source Code ug 1137 2014 12 15 Organize New folder wx Favorites a horoi E Desktop d Idscripts pg Downloads L thumb T Recent Places J thumb2 3 arm names inc Libraries _ armulator ram ld Documents C armulator ram hosted ld a Music B 2 sila om Pictures Ikac 7 H Videos D a ET id a cycloneV dk ram hosted ld E Computer _ generic ld amp OSDisk C Filename cycloneV dk oc ram hosted Id 4 Click OK to close the Project Properties window Write Application Source Code 1 Go to File gt New gt Source File Altera Corporation 5 5 2014 2 21 PI 5 5 2014 2 22 Pr 5 5 2014 2 22 Ph 5 1 2014 10 52 5 1 2014 10 52 5 1 2014 10 52 5 1 2014 10 52 Z 5 1 2014 10 52 r 5 1 2014 10 52 Z 5 1 2014 10 52 Z _ Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 File Edit Source Refactor Navigate Search Project Run Window Help Write Application Source Code 4 13 New Open File Close Close All Save Save As Save All Convert Line Delimiters To Print Switch Workspace Restart Import Export
88. bsite Altera Corporation Getting Started Guides GJ Send Feedback ARM DS 5 Altera Edition 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The ARM DS 5 AF is based on the ARM Development Studio 5 DS 5 Toolkit and is a device specific exclusive offering from Altera The ARM DS 5 Altera Edition is a powerful Eclipse based comprehensive Integrated Development Environment IDE Some of the most important provided features are e File editing supporting syntax highlighting and source code indexing e Build support based on makefiles e Bare metal debugging e Linux application debugging e Linux kernel and driver debugging e Multicore debugging e Access to HPS peripheral registers e Access to FPGA soft IP peripheral registers e Tracing of program execution through PTM e Tracing of system events through STM e Cross triggering between HPS and FPGA e Connecting to the target using Altera USB Blaster II The ARM DS 5 Altera Edition is a complex tool with a vast amount of features and options The Altera SoC EDS User Guide only describes some of the most common features and options and provides getting started scenarios to allow you to start being productive quickly Related Information Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5
89. cation Name TestConfiguration Target Configuration Application on host to download Files Bs Debugger OS Awareness 60 Arguments Environment pace 7 Load symbols 8 Browse to the executable and click OK Getting Started Guides GJ Send Feedback 4 47 Altera Corporation ug 1137 4 48 Debug Application 2014 12 15 Figure 4 26 Open TestProject axf Select a file RemoteSystemsTempFiles 4 gt TestProject cproject project a amp Debug a TestPro _ makefile _ objects mk _ sources mk subdir mk test d test o scatter scat test c 9 Click the Debug button to download the application and start the debug session Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Debug Application 4 49 Figure 4 27 Debug Session Started Create manage and run configurations _ Create edit or choose a configuration to launch a DS 5 debugging session pex Ep type filter text fe C C Application fe C C Attach to Application fc C C Postmortem Debugge E C C Remote Application 4 2 DS 5 Debugger 2 New_configuration Iron Python Run Name TestConfiguration es Connection E Files gt 4 Debugger OS Awareness 0 Arguments PB Environment Target Configuration Application on host to download S workspace_loc TestProject Debug TestProject axf Lond amet Iron Python unittest J
90. cess the launch configurations The sample project comes with a pre configured launcher that allows the application to be run on the board 2 In the Debug Configurations dialog box on the left panel select DS 5 Debugger gt Altera SoCFPGA HelloWorld Baremetal Debug Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Running the Bare Metal Debugging Sample Application 4 55 The Target is already pre configured to be Altera gt Cyclone VSoC gt Bare Metal Debug gt Debug Cortex A9_0 via Altera USB Blaster 3 Click Browse to select the USB Blaster connection Figure 4 33 Debug Configuration Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty type filter text C C Application E C C Attach to A E C C Postmorter E C C Remote Ap 4 7 DS 5 Debugger Jh Altera SoCFPG Iron Python Run g Iron Python unittes Java Applet D Java Application Ju JUnit a Jython run E Jython unittest gt Launch Group C PyDev Django 23 PyDev Google App 2 Python Run Python unittest ral Remote Java Applic pr soca i 4 In the Select Debug Hardware dialog box select the desired USB Blaster and click OK Getting Started Guides GJ Send Feedback Filter matched 19 of 19 iten f ma O BX E F7 Name Altera SoCFPGA HelloWorid Baremet
91. ck The following list contains the Linux software development tools e Linux compiler e Device tree generator e Yocto plugin Linux Compiler on page 12 1 SD Card Boot Utility on page 11 1 The SoC EDS SD card boot utility is a tool for updating the boot software on an SD card Device Tree Generator on page 12 4 Yocto Plugin on page 12 5 Linux Compiler The Linaro Linux compiler version 4 8 3 is shipped with the SoC EDS For more information about the Linux compiler and for downloading the latest version of the tools refer to the download page at the Linaro website www linaro org The compiler is a GCC based arm linux gnueabihf port It targets the ARM processor it assumes the target platform is running Linux and it uses the GNU embedded application binary interface EABI hard float HF conventions The Linux compiler is installed as part of the ARM DS 5 AE which is installed as part of the SoC EDS The compilation tools are located at lt SoC EDS installation directory gt ds 5 bin The Linux compiler comes with full documentation located at lt SoC EDS installation directory gt ds 5 documents gcc The documents are provided as HTML files Some of the provided documents are e Compiler manual e Assembler manual e Linker manual e Binutils manual e GDB manual e Getting Started Guide 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words
92. current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 NOS RYA ug 1137 1 2 Device Tree Binary 2014 12 15 The major components of the SoC EDS include ARM Development Studio 5 DS 5 Altera Edition AE Toolkit Compiler tool chains e Bare metal GNU Compiler Collection GCC tool chain from Mentor Graphics e ARM Bare metal compiler tool chain e Linux GCC compiler tool chain from Linaro Pre built Linux package including e Linux kernel executable e Linux kernel U boot image e Device tree blob e Secure Digital SD card image e Script to download Linux source code from the Git tree on the Rocketboards website www rocketboards org The script downloads the sources corresponding to the pre built Linux package SoC Hardware Library HWLIB Hardware to software interface utilities e Preloader generator e Device tree generator Sample applications Golden Hardware Reference Design GH
93. cycles Getting Started Guides Altera Corporation GJ Send Feedback 1137 4 104 HPS Triggering FPGA Example 2014 12 15 Quartus SignalTap II GUI has the above depicted Trigger panel that controls cross triggering e The Trigger In panel determines whether HPS can trigger FPGA Trigger In can be enabled and the Pattern can be selected with Don t care Low High Rising Edge for instance e The Trigger out panel determines whether FPGA can trigger HPS Trigger out can be enabled and the Level can be selected Active High and Active Low Note Changing some of the settings requires recompiling the FPGA design For this getting started scenario you will change only options that do not require recompilation The SignalTap II file that is provided with the Cyclone V GHRD has only the options that do not require compilation enabled to be edited If you recompile the design you can enable all options to be edited by selecting the Lock Mode to be Allow all changes Figure 4 85 SignalTap Lock Mode Lock mode f Allow all changes HPS Triggering FPGA Example This section presents an example on how stopping HPS execution in the debugger can trigger FPGA to perform a SignalTap II acquisition This can be useful for example if we want to see the state of some FPGA signals at the time the HPS is stopped in the debugger The required steps are to reproduce this scenario 1 Perform the steps from the Cross triggering Prerequisites
94. d from the Embedded Command Shell The Eclipse tool part of the ARM DS 5 AE prompts for the workspace folder to be used Accept the suggested folder and click OK The ARM DS 5 AE Welcome screen appears It can be used to access documentation tutorials and videos Select Window gt Open Perspective gt DS 5 Debug to open the Workbench Alternatively you can Click on the link Go to the Workbench located under the list of DS 5 Resources Debugging the Kernel This section presents how to create a Debug Configuration that is then used to debug the Linux kernel 1 Select Run gt Debug Configurations to open the Debug Configurations dialog box 2 In the Debug Configurations dialog box right click DS 5 Debugger on the left panel and select New 3 In the Debug Configurations dialog box perform the following a Rename the configuration to DebugLinux_DevKit using the Name edit box b Select the Target to be Altera gt CycloneVSoC gt Linux Kernel and or Device Driver Debug gt Debug Cortex A9x2 SMP via Altera USB Blaster c Click the Browse button near the Connection edit box and select the desired USB Blaster instance Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 74 Debugging the Kernel 9014 12 15 Figure 4 48 Configure Connection Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core
95. d with R nning LiN UX sssissisisessieisoersencriirorerocoiisi ecaecesonsastiucdeastycatentecedescsteoeteccesadBeesattees 4 2 Getting Started with Preloader sesesessesesessesesesessssesesessssesestssesesestssesesestssesesesteseseseseesesesesrseseseseseeseses 4 3 Getting Started with GCC Bare Metal Project Management s ssssseesessssssesesessrsesessesesesessesesesesseseses 4 6 GLE wl E e lt a ae T E IE T S ree er ae ene ee ener re ere 4 6 Create NOW PTO cl Denese errr ae Crore Ten Tener enor er rere nerve nnn were ere nT tre er rte era arty 4 6 St ES Linker SC OU aise stese tedynerenesd dostieesdeassdesahabevendevensol tun Nia ESE EE E TT OEO NiNa 4 9 Write AP PCat OM SOU COC OCC nuceria ninn aE e eii i ieS 4 12 PALA OO AC AU iae A E EEA E E EAE ESEE OSIE 4 15 Pebr AP PAU Oea EEEE EE EE EE E E E ee 4 17 Getting Started with ARM Compiler Bare Metal Project Management ssssssssssessssssssessesssseseeses 4 25 STS E SC O E EE E A A E A EEE A E 4 25 E E al op 0 lt 1 A E E E A A E TS 4 26 O OE ae oai A E E A E T E A A E 4 29 Set the Linker Stipi dec heoca ss ccs ce test cc sccuendshecat nnen nace iaiaaeaia ieena 4 34 Write Applicaton SOU COC OS a cassas caccsscacatescndontnedeaductetecuntau ects tadcateececasanseedeucbiocedestacedendaosieceates 4 37 Bada OO a OM ecco scence E A EE E AEN cn ecto 4 40 DRaa a0 9 E N A O O A O ee Te 4 42 Getting Started with Bare Metal Debugging eeessssssssssesssssrssesssse
96. dback Altera Corporation 4 6 Getting Started with GCC Bare Metal Project Management e Cyclone V Device Handbook Booting and Configuration For more information about Booting and Configuration with regards to Preloader refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook e Arria V Device Handbook Booting and Configuration For more information about Booting and Configuration with regards to Preloader refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook Getting Started with GCC Bare Metal Project Management This section presents a complete bare metal example demonstrating the GCC bare metal project management features of the ARM DS 5 Altera Edition Start Eclipse 1 Start Eclipse The Workspace Launcher dialog box appears Figure 4 4 Select a Workspace Workspace Launcher Sc Select a workspace Eclipse Platform stores your projects in a folder called a workspace Choose a workspace folder to use for this session Workspace v Browse l Use this as the default and do not ask again ey a l Cancel 2 Select a new workspace to use For example you can enter c Workspace and click OK Create New Project 1 Go to File gt New gt Project Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Close Close All Save Save As Save All Revert Move Rename Refresh Convert
97. ders for products or services JNO TS RYAN 101 Innovation Drive San Jose CA 95134
98. e Figure 4 41 Select USB Blaster Connection Browser Select a target connection US6 Blasterll USB 1 USB Blasterll on localhost USB 1 5 Click the Debug button from the bottom of the Debug Configurations dialog box 6 Eclipse ask whether to switch to Debug Perspective Click Yes to accept it The debugger downloads the application on the board through JTAG enables semi hosting using the provided script and runs the application until the PC reaches the main function At this stage all the debugging features of DS 5 can be used such as viewing and editing registers and variables looking at the disassembly code Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 2014 12 15 Figure 4 42 Application Downloaded Running the Hardware Library Sample Application 4 65 E De X Pr gre O AC x BH Bs D Blux G Gr v Qltera SoCFPGA HardwareLib FPGA CV a W amp Altera SoCFPGA Hardwarelib F Running from entry point j Execution stopped at break a 98 Cortex A9_0 1stoppedoni In kolibe r Pe main S AXAMITANAAR 4 Command Press Ctri Spac 319 40 E BB hwlib c 3 318 gt int main int argc char argv 319 320 ALT_STATUS_CODE status ALT_E_SUCCESS 321 ALT_DMA CHANNEL _t channel 322 f etatuece AIT E CiIrreccy fe a 292 Writable SmartInset 3 1 C VX 8B tera SoCFPGA HardwareLib FPGA C Name Locals argc
99. e Execution stopped at S xFF Locals 0 variable amp No Stack S xFFFF2F88 SVC 0x1 Bh nr ae Application exited with stat gt Globals 4 we gt 4 R Altera SoCFPGA HelloWorld Ba E Cortex A9_0 1 application In _exit no debug info R Altera S application exit code 0 No OS Support Command Submit z z hello c 3 Ba xe Ojien So 5 F Gl Ex Bi Y int main int argc char argv printf Hello Tim n return 0 d Altera SoCFPGA HelloWorld Baremeta Hello Tim m 8 Click Disconnect from Target button to close the debugging session Getting Started with the Hardware Library The SoC Hardware Libraries example program is part of the Altera SoC Embedded Design Suite EDS You can run the sample program on a Cyclone V SoC development kit board The example program demonstrates using the Hardware Library to programmatically configure the FPGA and exercise soft IP control from the hard processor system HPS Hardware Library Sample Application Overview The Bare Metal sample application uses the HWLIB API to e Programmatically configure the FPGA from the HPS e Initialize and bring up the Advanced eXtensible Interface AXI bridge interfaces between the HPS and the FPGA e Exercise the FPGA soft IP parallel I O PIO core from the HPS to toggle the development board LEDs The sample application uses the development kit Golden System Reference Design GSRD FPGA configuration The samp
100. e Connection Ta Files e Debugger te OS Awareness 6 Arguments Mg Environment Program Arguments Environment The Environment tab allows the user to enter environment variables for the program to be executed ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback 1137 5 34 DTSL Options ai Figure 5 31 Environment Settings Name Sample Configuration i Connection Ta Files e Debugger te OS Awareness 6 Arguments B Environment Target environment variables to set Variable Value Edit Remove DTSL Options The Debug and Trace Services Layer DTSL provides tracing features To configure trace options in your project s Debug Configuration window in the Connection tab click the Edit button to open the DTSL Configuration window Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 9014 12 15 Cross Trigger Settings 5 35 Figure 5 32 Debug Configurations DTSL Options Edit Name Sample Configuration Ei Connection Files 4 Debugger ii OS Awareness I Arguments P Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 4 Altera Arria V SoC a Cyclone V SoC Dual Core 4 Bare Metal Debug Debug Cortex A9 0 Debug Cortex A9 1 Debug Cortex A9x SMP Zz gt Linux Application Debug gt Linux Kernel and or Device Dr
101. e Metal Debug e Debug HPSO Cortex A9_0 e Debug HPSO Cortex A9_1 e Debug HPSO Cortex A9x2_SMP e Debug HPS1 Cortex A9_0 e Debug HPS1 Cortex A9_1 e Debug HPS1 Cortex A9x2_SMP e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug HPSO Cortex A9_0 e Debug HPSO Cortex A9_1 e Debug HPSO Cortex A9x2_SMP e Debug HPS1 Cortex A9_0 e Debug HPS1 Cortex A9_1 e Debug HPS1 Cortex A9x2_SMP Dual Cyclone V SoC Two Dual Core SoCs e Bare Metal Debug e Debug HPSO Cortex A9_0 e Debug HPSO Cortex A9_1 e Debug HPSO Cortex A9x2_SMP e Debug HPS1 Cortex A9_0 e Debug HPS1 Cortex A9_1 e Debug HPS1 Cortex A9x2_SMP e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug HPSO Cortex A9_0 e Debug HPSO Cortex A9_1 e Debug HPSO Cortex A9x2_SMP e Debug HPS1 Cortex A9_0 e Debug HPS1 Cortex A9_1 e Debug HPS1 Cortex A9x2_SMP Android Application Debug e Native Application Library Debug e APK Native Library Debug via gdbserver e Attach to a running Android application e Download and debug an Android application Linux Application Debug ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback ug 1137 5 28 Connection Options w e App
102. e TestLibrary Browse Choose file system default Project type Toolchains b Executable ARM Compiler 5 DS 5 built in gt amp Shared Library ARM Compiler 6 DS 5 built in 4 amp Static Library Altera Baremetal GCC Empty Project Cygwin GCC b Makefile project GCC 4 x arm linux gnueabihf GCC for ARM Bare metal MinGW GCC ay ae t V Show project types and toolchains only if they are supported on the platform project types ey PP P Linker Script ARM DS 5 AE offers a visual tool to help create linker scripts 1 Go to File gt New gt Other ARM DS 5 Altera Edition Altera Corporation C Send Feedback 5 16 Linker Script Figure 5 14 Creating a Linker Script File Edi rce Open File Close Close All Move Save Save As Save All Revert Rename Refresh Convert Line Delimiters To Print Refactor Navigate Search Project Run Alt Shift N gt Ctrl W Ctri Shift W Ctri Ctri Shift S Switch Workspace Restart Import Export Properties Alt Enter 1 scatter scat altera 14 1 embedded Exit items selected l 7 AGRRERAM ZAMM Makefile Project with Existing Code C Project C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Ternplate Class Other E Properties a ug 1137 2014 12 15 2
103. e gt directory where hps entity name is the HPS component name in Qsys Note You must update the hardware handoff files and regenerate the preloader support package each time a hardeare change impacts the HPS such as after pin multiplexing or pin assignment Using the Preloader Support Package Generator GUI You must perform the following steps to use the preloader support package generator GUI bsp editor 1 Start an embedded command shell as follows HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 4 Using tcl Scripts 201 3 05 03 e Ona Windows based system run the batch file lt SoC EDS installation directory gt Embedded_Command_Shell bat e Ona Linux based system run the shell script lt SoC EDS installation directory gt embedded_command_shell sh 2 Run the bsp editor command in the embedded command shell to launch the preloader support package generator 3 To open and modify an existing preloader support package PSP project in the preloader support package generator click File gt Open and browse to an existing bsp file 4 To create a new PSP project click File gt New BSP to open the New BSP dialog box The New BSP dialog box includes the following settings and parameters e Preloader settings directory the path to the hardware handoff files The generator inspects the handoff files to verify the validity of this path e Operating system and Version Not applicable to preloader gen
104. e next boot stage from Preloader In some usage scenarios it can be a bootloader while in other scenarios it could be a bare metal application or even an OS Note The Preloader file needs to have the mkpimage header as required by the BootROM and the Bootloader file needs to have the mkimage header as required by the Preloader Both mkpimage and mkimage tools are delivered as part of SoC EDS The tool only updates the custom partition that stores the Altera SoC boot code The rest of the SD card or disk image file is not touched This includes the Master Boot Record MBR and any other partitions FAT EXT3 etc and free space 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agr
105. e of flash to program Using the Flash Programmer from the Command Line HPS Flash Programmer The HPS flash programmer utility can erase blank check program verify and examine the flash The utility accepts a Binary File with a required bin extension The HPS flash programmer command line syntax is guartus_hps lt options gt lt file bin gt Note The HPS flash programmer uses byte addressing HPS Flash Programmer User Guide GJ Send Feedback Altera Corporation ug 1137 2014 12 15 HPS Flash Programmer 9 3 Table 9 1 HPS Flash Programmer Parameters Short Required Description Option cable This option specifies what download cable to use To obtain the list of programming cables run the command jtagconfig It will list the available cables like in the following example jtagconfig 1 USB Blaster USB 0 2 USB Blaster USB 1 3 USB Blaster USB 2 The c parameter can be the number of the programming cable or its name The following are valid examples for the above case c 1l c USB Blaster USB 2 SHORTI ee Yes if there are This option specifies the index of the HPS multiple HPS device The tool will automatically detect the devices in the chain and determine the position of the HPS chain device however if there are multiple HPS devices in the chain the targeted device index must be specified HPS Flash Programmer User Guide Altera Corporation GJ Send Feedback ug 1137
106. e seen from the screen shots and the issued commands However the scenario can also be run on a Windows machine although it is not usual for Linux development to be done on Windows Related Information e ARM DS 5 Altera Edition on page 5 1 For more information refer to the ARM DS 5 Altera Edition section e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Configuring Linux For this getting started scenario we need Linux to be running on the target board and be connected to the local network The local network has to have a DHCP server that will allocate an IP address to the board Eclipse needs an account with a password to be able to connect to the target board The root account does not have a password by default so one needs to be set up Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 ame 2014 12 15 Starting Eclipse with the Embedded Command Shell 3 The required steps are 1 Setup the board as described in the Getting Started with Board Setup section and connect the HPS Ethernet Connector J2 to the local network 2 Start Linux on the target board as described in the Getting Started with Running Linux section On the Li
107. eacseeacseeseeesseeaceeeaeeeees 8 3 HPS Flash Programmer User Guide csccscssssssssssssosssssnsssssssssscsssssvorsoessesseeees 9 1 HPS Flash Programmer Command Line Utility eee seeeeseeeeseeeeeeeeecseeeeseseeaeseeeseseeessesesseeeeaeees 9 1 How the HPS Flash Programiner WOT Sse cece ece aces c cai eect ctste weet atch cae asa E ea e iiaeiai 9 1 Using the Flash Programmer from the Command Line ee eseeeeseseeeeseeeeeeeceseeceeeaceeeacseseeseeeeaees 9 2 Iie ro a EE 018 cs ey ATO 2 canner ene NA ae ener T N peer ener ean ere een eee ee 9 2 HPS Flash Programmer Command Line Examples esessseeeeeeeeeeececeeeeeeseeeeeseeeeaceeeaes 9 4 SUPporecd Memory DEVICES ene ne pe et er rte Or AE E reer eee ore ee err eee 9 6 B re Metal CO iC le aioe coe nena na ocecaestaceuaeseecansssasiesentccavesipsheesncavesenoneecysaieeancouets 10 1 a Boor U abana toes cectvace E E ET 11 1 OE E a S E E EE E E E E EE E A E E 11 1 EO E sees A E A T E AE E E E E E E E T ER 11 2 Linux Software Development Tools sssssseescececccecsossssssesecececcccoosssssseseseseeeeoo 12 1 EAO oct oy E E A E AT EI A AA E E E N E E 12 1 SDE Nae we 1b a E E ten E A E T E E E E A te ee 12 2 OG E A A car on E AT T A E E TT T 12 2 To Op MOINS e ATE E E T E E E E 12 2 Dee CC e a E A A E E A E A E A T 12 4 DCR ad Lb 25 a OA E EEEE E E E N E E T 12 5 Altera Corporation TOC 5 SU POL AMG Feed Dac Roera E E E EE ETS 13 1 Altera Corporation 2014 12 15 ug 11
108. eakpoints Note In the scenario presented here the Linux kernel is already running on the board but it can also be downloaded through the debugger Note This scenario uses the pre built Linux images and Linux source code included in the SoC EDS These are examples only use the latest sources from the Rocketboards website for development Note This section uses a Linux host computer as can be seen from the screenshots and the issued commands However the scenario can also be run on a Windows machine although it is not usual for Linux development to be done on Windows Note The paths presented in this section assume the default installation paths were used Adjust accordingly if non standard location is used Related Information e ARM DS 5 Altera Edition on page 5 1 For more information refer to the ARM DS 5 Altera Edition section e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Linux Kernel and Driver Debugging Prerequisites e Make sure the desired Linux kernel version is already running on the board See the Getting Started with Running Linux section for instructions on how to run the provided Linux binaries on the board e Make sure the Linux
109. ebugge E C C Remote Application 4 2 DS 5 Debugger 2 New_configuration Iron Python Run 4 Altera 2 Iron Python unittest gt Arria V SoC Java Applet a Cyclone V SoC Dual Core G Java Application 4 Bare Metal Debug Ju JUnit Debug Cortex A9 0 2 Jython run Debug Cortex A9_1 2 Jython unittest Debug Cortex A9x2 SMP Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 Launch Group C PyDev Django Target Connection 23 PyDev Google App Run cm oars om DTSL Options Configure USB Blaster trace or other target options Using default configuration F Python unittest S DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application ea Remote Java Application Connections Bare Metal Debug Connection 4 m Apy Revert e Filter matched 19 of 19 items ay Debug 5 Click the Connection gt Browse Button to select the connection to the target board 6 Select the desired target and click Select Select a target connection USB Blasterll USB 1 JSB Blasterll on localhost USB 1 Altera Corporation Getting Started Guides GJ Send Feedback 1137 E 4 12 15 Debug Application 4 21 7 Go to Files tab gt Target Configuration gt Application on host to download and click the Workspace button to browse for the executab
110. eed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN Oe RYA 101 Innovation Drive San Jose CA 95134 ug 1137 112 Tool Options sins Warning The users of this tool need administrative or root access to their computer to use this tool to write to physical SD cards These rights are not required when only working with disk image files Please contact the IT department if you do not have the proper rights on your PC Tool Options The utility is a command line program The table describes all the command line options and the figure shows the he 1p output from the tool Table 11 1 Command Line Options p filename Required Specifies Preloader file to write b filename Specifies Bootloader file to write a write Required Specifies action to take Only write action is supported Example a write disk_file Required unless d optionis Specifies disk image file or physical disk to used write to A disk image file is a file that contains all the data for a storage volume including the partition table This can be written to a physical disk later with another tool For physical disks in Linux just specify the device file For example dev mmcblko For physical disks in Windows specify the physical drive path such as physicaldrive2 or use the drive letter opt
111. er File Select a wizard Create a scatter file Wizards p E General b amp C C gt Ge CVS b amp DS 5 Configuration Database gt amp DS 5 Debugger a DS 5 Platform Configuration Editor Platform Configuration File gt 6 Java gt amp PyDev gt gt Remote System Explorer 4 Scatter File Editor Scatter File gt amp Target Configuration Editor 3 Select the Test Project edit the file name to be scatter scat and click Finish Getting Started Guides Altera Corporation GJ Send Feedback 4 32 Create a Linker Script ug 1137 2014 12 15 Figure 4 10 Scatter File Resource r T WEW 2C Scatter File Create a new scatter file resource Enter or select the parent folder TestProject tes i RemoteSystemsTempFiles 4 E TestProject Debug File name scatter scat 4 Edit the file scatter scat to contain the following Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 11 Contents of scatter scat Cy scatter scat 23 OCRAM xFFFF x16000 2 3 APP_CODE 0 5 RO RW ZI Application heap and stack ARM_LIB_STACKHEAP 0 EMPTY 0x4000 ie 12 ri Regions Sections scatter scat Create a Linker Script 4 33 The above linker script instructs the linker on how to link the application e Defines OCRAM base address OxFFFFO000 and size 0x10000 e Loads all application section
112. er trace or other target options Using default configuration DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections Bare Metal Debug Connection Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 errr ne Connection Options 5 29 For the Linux Application Debug targets the connection parameters will be different depending on which type of connection was selected The following two pictures illustrate the options Figure 5 25 Linux Application Debugging Connect to a Running GDB Server Name Sample Configuration Be Connection i Files ns Debugger gs OS Awareness 69 Arguments a Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Application Debug Connect to already running gdb 4 Altera t Arria V Sot 4 Cyclone V SoC Dual Core t Bare Metal Debug 4 Linux Application Debug Connect to already running gdbserver Download and debug application Start gdbserver and debug target resident application DS 5 Debugger will connect to an already running gdbserver on the target system Connections gdbserver TCP p 5000 Use Extended Mode Terminate gdbserver on disconnect ARM DS 5 Altera Edition Altera Corporation C Send Feedback ug 1137 5 30 Connection Options Dra Figure 5 26 Linux Application Debugging Down
113. era customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN D fe RYA 101 Innovation Drive San Jose CA 95134 SD Card Boot Utility 1 1 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The SoC EDS SD card boot utility is a tool for updating the boot software on an SD card The Preloader is typically stored in a custom partition with type 0xA2 on the SD card Optionally the next boot stage usually the Bootloader can also be stored on the same custom partition Since it is a custom partition without a file system the Preloader and or Bootloader cannot be updated by copying the new file to the card and a software tool is needed The SD card boot utility allows the user to update the Preloader and or Bootloader on a physical SD card or a disk image file The utility is not intended to create a new bootable SD card or disk image file from scratch In order to do that it is recommended to use fdisk on a Linux host OS Usage Scenarios This utility is intended to update boot software on that resides on an existing e Existing SD card e Existing disk image file You can choose from these three usage scenarios e Update just the Preloader software e Update just the Bootloader software e Update both Preloader and Bootloader software In the context of this tool the term Bootloader simply means th
114. eration e BSP target directory the destination folder for new PSP files created by the generator This document refers to the preloader BSP directory as lt bsp directory gt The default directory name is spl_bsp You can modify the directory name e BSP settings file name the location and filename of the bsp file e Additional tcl scripting the location and filename of a tcl script for overriding the default BSP settings 5 You can customize the PSP After creating or opening a bsp file access the Settings in the BSP Editor dialogue box The Settings are divided into Common and Advanced settings When you select a group of settings the controls for the selected settings appear on the right side of the dialogue box When you select a single setting the setting name description and value are displayed You can edit these settings in the BSP Editor dialogue box 6 Click Generate to generate the preloader support package 7 Click Exit to exit the preloader support package generator Using tcl Scripts Instead of using the default settings you can create a tcl script file tcl to define custom settings during BSP creation set_setting is the only available tel command Refer to BSP Settings for a list of available settings Example 7 1 Valid tcl Scripting Commands for Changing BSP Settings The following commands are used to set parameters n the BSP setings file set_setting spl boot BOOT_FROM_QSPI true set_setting s
115. f the online SoC FPGA Hardware Library HWLIB Reference Documentation are e SoC Abstraction Layer SoCAL API Reference Documentation lt SoC EDS installation directory gt ip altera hps altera_hps doc socal html index html e Hardware Manager HW Manager API Reference Documentation lt SoC EDS installation directory gt ip altera hps altera_hps doc hwmgr html index html Hardware Library Altera Corporation GJ Send Feedback HPS Flash Programmer User Guide 2014 12 15 ug 1137 lt Subscribe GJ Send Feedback The Altera Quartus II software and Quartus II Programmer include the HPS flash programmer 9 Hardware designs such as HPS incorporate flash memory on the board to store FPGA configuration data or HPS program data The HPS flash programmer programs the data into a flash memory device connected to an Altera SoC The programmer sends file contents over an Altera download cable such as the USB Blaster II to the HPS and instructs the HPS to write the data to the flash memory The HPS flash programmer programs the following content types to flash memory e HPS software executable files Many systems use flash memory to store non volatile program code or firmware HPS systems can boot from flash memory Note The HPS Flash Programmer is mainly intended to be used for programming the Preloader image to QSPI or NAND flash Because of the low speed of operation it is not recommended to be used for programming la
116. factor Navigate Search Project Run Window Help Makefile Project with Existing Code C Project C Project Project ea New Open File Close Ctri W Close All Ctri Shift W Save Ctrl S Convert to a C C Project Adds C C Nature Save As Save All Ctri Shift S Revert gt utline is not Source Folder able Folder Source File Header File File from Template Rename Cian Move Cea Re ZAR Refresh Convert Line Delimiters To Other Print Tasks Console Properties Switch Workspace Restart A Resource Import Export 2 Select C C gt C Project and click Next Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 28 Create a New Project re 2 15 Figure 4 7 Create a New C Project Select a wizard Create a new C project Wizards ae type filter text b amp General a C C E C Project fe C Project Makefile Project with Existing Code b amp Cvs gt gt Java gt S amp S PyDev 3 Edit Project Name to be Test Project Select Project Type to be Executable gt Empty Project then Toolchains to be ARM Compiler 5 DS 5 built in then click Finish Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 8 Create C Project C Project Create C project of selected type Project name TestProject Use default location Location C Workspace TestProject Project type
117. from the embedded command shell To display help type the following command lt name Of tool gt help Related Information Preloader Support Package Generator on page 7 2 bsp create settings The bsp create settings tool creates a new PSP settings file with default settings You have the option to modify the BSP settings or generate the PSP files as shown in the following example Example 7 2 Creating a New PSP Settings File bsp create settings type spl bsp dir settings settings bsp preloader settings dir hps_isw_handoff lt hps_entity_name gt HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 6 bsp update settings 2013 05 03 Table 7 1 User Parameters bsp create settings oen Treure Descon type lt bsp type gt Yes This option specifies the type of BSP spl is the only allowed PSP type for a SoC EDS PSP SSSEE LUGS SSSI sings wa Le Yes This option specifies the path to a BSP settings file The file is created with default settings Altera recommends that you name the BSP settings file settings bsp ae Yes This option specifies the path to the hardware lt preloader settings dir gt handoff files ae ec Yes This option specifies the path where the BSP files are generated When specified bsp create settings generates the files after the settings file has been created Altera recommends that you always specify this parameter with bsp create settin
118. ftware may be designed in such a way that no SDRAM location is read before it is first written Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Available BSP Settings 7 13 spl debug HARDWARE_DIAGNOSTIC spl debug SKIP_SDRAM spl performance SHRIAL SUPPORT spl reset_assert lt peripheral_name gt spl warm_reset_handshake FPGA spl warm_reset_handshake ETR HPS Preloader User Guide GJ Send Feedback Boolean Boolean False False True Refer to Reset Assert Settings on page 7 14 True True This setting enables hardware diagnostic support enabling hardware to read from and write to the SDRAM to ensure hardware is working the status is reported in the console The preloader skips SDRAM initialization and calibration when this setting is enabled This setting enables UART print out support enabling preloader code to call printf at runtime with debugging information stdout output from printf is directed to the UART You can view this debugging information by connecting a terminal program to the UART specified peripheral This setting forces the device to remain under reset state You can include multiple instances of spl reset_ assert lt peripheral_name gt to hold multiple peripherals in reset You must ensure the debugger does not read registers from these components This setting enables the reset manager to perform handshake with the
119. g on port 5000 Debug session has been started connecting to gdbserver Remote debugging from host 137 57 188 107 Hello SoC FPGA lt Getting Started with Tracing ARM DS 5 provides powerful tracing features allowing PTM and STM tracing It allows different tracing data destination types This section presents an example of Program Tracing using PTM and storing the tracing information in memory using ETF The tracing scenario presented here uses Linux kernel debugging as an example but any application can be traced in the same way As shown the tracing can be selected to show current core a particular core or follow the currently executing thread The following steps are necessary in order to enable PTM tracing 1 Execute the steps described in the Getting Started with Linux Kernel and Driver Debugging section to perform Linux kernel debugging Select Run gt Debug Configurations and select the Debug Linux_DevKit configuration created at the previous step 3 Select the Connection tab 4 Click the Edit DTSL Options button Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 1 2 15 Getting Started with Tracing 4 93 Figure 4 66 Edit DTSL Options Button Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Kernel and or Device Driver Debug Debug Cortex A9x2 SMP v Altera gt Aria V SoC
120. g the tool with the nelp option provides a tool description and tool usage and option information S mkpimage help mkpimage version 14 1 build 182 Description This tool creates an Altera BootROM compatible image of Second Stage Boot Loader SSBL The input and output files are in binary format It can also decode and check the validity of previously generated image Usage Create quad image mkpimage options hv lt num gt o lt outfile gt lt infile gt lt infile gt lt infile gt lt infile gt Create single image mkpimage options hv lt num gt o lt outfile gt lt infile gt Decode single quad image mkpimage d a lt num gt lt infile gt Options a alignment lt num gt Address alignment in kilobytes valid value Starts from 64 128 256 etc default to 64 for header version 0 and 256 for header version 1 override if the NAND flash has a larger block size d decode Flag to decode the header information from input file and display it f orce Flag to force decoding even if the input file is an unpadded image h help Display this help message and exit hv header version lt num gt Header version to be created Arria Cyclone V 0 Arria 10 1 O OuTpUL lt outfile gt Output file relative and absolute path supported off offset lt num gt Program entry offset relative to start of header 0x40 default to 0x14 Used for header version 1 only v vers
121. ger Trace Buffer Cortex A9 STM ETR ETF Enable Cortex A9 core trace Enable Cortex A9 0 trace Enable Cortex A9 1 trace PTM Triggers halt execution Enable PTM Timestamps Timestamp period 4000 Enable PTM Context IDs Context ID Size Cycle Accurate Trace capture range Ox OxFFFFFFFF The following Core Tracing Options are available e Enable Cortex A9 0 core trace check to enable tracing for core 0 e Enable Cortex A9 1 core trace check to enable tracing for core 1 e PTM Triggers halt execution check to cause the execution to halt when tracing e Enable PTM Timestamps check to enable time stamping e Enable PMT Context IDs check to enable the context IDs to be traced e Context ID Size select 8 16 or 32 bit context IDs Used only if Context IDs are enabled ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback ug 1137 5 38 STM Settings revere e Cycle Accurate check to create cycle accurate tracing e Trace capture range check to enable tracing only a certain address interval e Start Address End Address define the tracing address interval Used only if the Trace Capture Range is enabled STM Settings The STM tab allows you to configure the System Trace Macrocell STM Figure 5 37 DTSL Configuration Editor STM Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Enable STM trace Only one option is available e Enable STM Trace check to enable STM tracing ETR Settings The
122. gs Se ee Seeder j This option sets the BSP setting name to name and and sets value to value E Related Information BSP Settings on page 7 9 A complete list of available setting names and descriptions bsp update settings The bsp update settings tool updates the settings stored in the BSP settings file as shown in the following example Example 7 3 Updating a PSP The following command changes the value of a parameter inside the file settings bsp bsp update settings settings settings bsp set spl debug SEMIHOSTING 1 Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 l 2013 05 03 bsp query settings 7 7 Table 7 2 User Parameters bsp update settings Os T Destan settings lt settings file gt Yes This option specifies the path to an existing BSP settings file to update E o en cae No This option specifies the path where the BSP files are generated When this option is specified bsp create settings generates the BSP files after the settings file has been created Altera recommends that you specify this parameter with bsp create settings set lt name gt lt value gt No This option sets the BSP setting lt name gt to the value lt value gt Refer to BSP Settings for a complete list of available setting names and descriptions Related Information BSP Settings on page 7 9 bsp query settings The bsp query settings tool queries the settings stored in BSP settings file
123. gure 4 60 Target Username and Password Enter Password System type SSH Only Host name 192 168 10 119 Connection name 192 168 10 119 User ID root Password optional eae Save user ID W Save password Cancel 8 Eclipse asks for confirmation of authenticity of the board Click Yes 9 Remote System Explorer shows the files on the DevKit board on the left panel Getting Started Guides GJ Send Feedback Altera Corporation f PO me ug 1137 4 88 Running the Linux Application Debugging Sample Application 2014 12 15 Figure 4 61 Target Files wi Remote Systems X Team ae amp kiTa i Z T v f 192 168 10 119 b My Home v7 oy v bin addgroup gt adduser E arping ash bash OE E gg piP a m i gt LE Running the Linux Application Debugging Sample Application At this stage we have a compiled Linux application and a properly configured Remote Systems Connection This section shows how to create a Debugger Configuration and use it to run and debug the application 1 Select Run gt Debug Configurations to open the Debug Configurations dialog box 2 Right click the DS 5 Debugger and click New to create a new debug configuration 3 Name the newly created debugger configuration LinuxAppDebug_DevKit by editing its name in the Connection tab 4 In the Connection tab select a For the Free Web Edition license select Generic gt gdb server
124. gure the on chip trace buffer Size Ox8000 8 Click OK to exit the DSTL Configuration Editor 9 Start a debugging session by starting the Debug Linux_DevKit debug configuration The debugger stops the Linux kernel and configure tracing 10 Let the kernel run by clicking the Continue green button or pressing F8 11 After executing some commands from the Linux serial terminal click Interrupt button or press F9 The Debugger shows the captured trace information Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Getting Started with Tracing 4 95 Figure 4 70 Trace Window wi Disassembly 4 Memory Trace amp Modules H Events g Outline g Ek M Linked DebugLinux_DevKit swapper 0 Trace Capture Device Source Ranges gic_handle_irg i irg sve lt Unknown gt __gnu_mcount_nec scheduler_tick update_rq_clock task_tick_idle 6 59 update_cpu_load_active update _rq_clock_ task arch_local_irq_enable oT Index Address Opcode Cycles Detail a update cpu load active S 0x80051604 MOV rl2z sp 5 6x86051668 PUSH r4 r7 ri1 r12 lr pc S 0x8005160C SUB rll rl2 4 5 6x66051616 PUSH ir 5 6x80651614 BL gnu mcount nc OxSQ00EBBO gnu mcount nc 5 0xX8000EBBO MOV r12 Ur _S Ox8009EBB4 C2804000 p DM so irl I ee miaa at oe G Pa te Li 5 Te T Fi m Hi gt The tracing window shows e Core instructions as they were executed e Percentage occu
125. he Enable HPS gt FPGA Cross Triggering check box if checked c Check the Assume Cross Triggers can be accessed check box 3 Start the debug session by clicking Debug in the Debug Configuration dialog box The debugger will stop the Linux kernel and display the current HPS state 4 In Signal Tap II configure a trigger on the fpga_dispw_pio 0 signal to trigger at any edge by right clicking the corresponding cell in the Trigger Condition column Figure 4 78 Trigger on Dip Switch trigger 2013 09 06 17 49 21 0 Lock mode Allow trigger cc Data Enable ae Enable jgger Conditio fpga_ dipsw_piofO fpga_dipsw_pio 1 Don t Care fpga_dipsw_pio Low ipga_dipsw_plo s Falling Edge pga_ted_pio Rising Edge fpga_led_ pio 1 fpga_led_pio 2 1 High fpga_led_pio 3 Either Edge Inst data_ ourt O 1nst data_ourt 1 eevee 5 In Signal Tap II configure the Trigger out to be sent to HPS so that the SignalTap II sends the trigger to HPS whenever it performs an acquisition Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 79 Enable Trigger Out to HPS FPGA Triggering HPS Example 4 101 Instance Hard Processor System HPS trigger in qF Hard Processor System HPS event Level Active High Latency delay 5 cycles 6 In Signal Tap II configure the Trigger in to be disabled by setting its pattern to Don t Care In thi
126. he applica tion console will show the message printed by the application Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 l l l re 2014 12 15 Getting Started with Bare Metal Debugging Figure 4 30 Application Console DS 5 Debug TestProject test c Eclipse Platform re f Ea File Edit Source Refactor Navigate Search Project Run Window Help a WE prea insted 3 in ines die Gene eo ac tienen Tact te a Quick Access ES Fa 2 Zk Debu 53 Proje ga Rem O E co x2 B gt 6 WVR 3 E ao Be o2 M a y g 2 gt die 2 x Hl Oly cov Pm o i a Ex ab Dy i v B Linked TestConfiguration B Linked TestConfiguration 7 4 R TestConfiguration application exit code continue 7 Name Value 4 q Cortex A9_0 1 application exit Execution stopped at S 0xFFFF107 amp amp Locals 0 variab erp In _sys_exit no debug info File Statics current on i S 0xFFFF1078 SVC 0x123456 sed a Se ee 3 gt Globals 4 m p R TestConfigura application exit code 0 No OS Support Command Submit Lc test c 52 1 include lt stdio h gt 3 gt int main void ae App amp printf Hello World n CAN A B Linked TestConfiguration Hello World p R TestConfiguration application exit code 0 Altera Cyclone V SoC Dual Core Getting Started with Bare Metal Debugging The ARM DS 5 Altera Edition provides very powerful bare metal debugging capabilit
127. ia V Device Handbook Booting and Configuration For more information about the four stages of the HPS booting process refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook e Cyclone V Device Handbook Booting and Configuration For more information about the four stages of the HPS booting process refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook HPS Configuration The preloader performs the following steps to configure the HPS and load the next image in the boot process 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest ver
128. idges are open Otherwise the debugger will generate a memory access abort and the debugging session will fail This includes having any soft IP registers groups expanded in the Registers dialog box The debugger will try to access them in order to refresh the view and it will generate a memory access abort if they are not accessible Always collapse the soft IP register view after usage if there is any chance they will not be available to the debugger Related Information e Getting Started with the Hardware Library on page 4 58 For more information refer to the Getting Started with the Hardware Library section Getting Started Guides Altera Corporation GJ Send Feedback Sie l ug 1137 4 72 Getting Started with Linux Kernel and Driver Debugging 2014 12 15 e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Getting Started with Linux Kernel and Driver Debugging The ARM DS 5 Altera Edition provides very powerful Linux Kernel and Driver debugging capabilities This section presents an example on of how to debug the Linux kernel and drivers using DS 5 The software engineers can use the dedicated Linux debugging features presented in this section together with the basic debugging features such as viewing registers inspecting variables and setting br
129. ies This section presents running the ARM DS 5 Altera Edition for the first time importing compiling and running the Hello World bare metal example application provided as part of SoC EDS Sample Application Overview Related Information e ARM DS 5 Altera Edition on page 5 1 For more information refer to the ARM DS 5 Altera Edition section e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Bare Metal Debugging Sample Application Overview Getting Started Guides GJ Send Feedback Altera Corporation 1137 4 52 Starting the Eclipse IDE ee 215 The provided sample application prints a Hello message on the debugger console by using semihosting This way no pins are used and all communication happens through JTAG The application is located in the 64 KB On Chip RAM and therefore does not require the SDRAM memory on the board to be configured This application can run on any board supporting the SoC device because of its simplicity and it does not require pins or external resources to be configured Note Make sure that Linux or another OS is not running on the board prior to doing this example An OS can interfere with the feature of downloading and debugging bare metal applications Note The screen snapshots and command
130. ion Display version and exit Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 2013 05 03 Output Image Layout 7 19 Output Image Layout Base Address Size You must place the preloader image at 0x0 for NAND and QSPI flash The SD MMC flash has a MBR that points to a specific offset at the start of the partition The partition is of type 0xA2 a custom raw partition type without any file system The preloader image tool always places the output image at the start of the output binary file regardless of the target flash memory type The flash programming tool is responsible for placing the image at the desired location on the flash memory device Related Information e Cyclone V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook e Arria V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook A single preloader has a 60 KB image size You can store up to four preloader images in flash If the boot ROM does not find a valid preloader image at the first location it attempts to read an image from the next location 64 KB above the first To take advantage of this feature program four preloader images in flash at consecutive 64 KB intervals Related Information e Cyclone V Device H
131. ion d to specify a drive letter The drive letter option is the easiest method in Windows d Optional specify disk drive letter to write to Example d E When using this option the disk_file option cannot be specified h Displays help message and exits version Displays script version number and exits Altera Corporation SD Card Boot Utility GJ Send Feedback ug 1137 2014 12 15 Tool Options 11 3 Figure 11 1 Sample Output from Utility alt boot disk util Altera Boot Disk Utility Copyright C 1991 2014 Altera Corporation Usage write preloader to disk alt boot disk util p preloader a write disk file write bootloader to disk alt boot disk util b bootloader a write disk file write BOOTloader and PREloader to disk alt boot disk util p preloader b bootloader a write disk file f write BOOTloader and PREloader to disk drive E alt boot disk util p preloader b bootloader a write d E Options version show program s version number and exit h help show this help message and exit b FILE bootloader FILE bootloader image file p FILE preloader FILE preloader image file a ACTION action ACTION only supports write action d DRIVE drive DRIVE specify disk drive letter to write to options error disk not specified SD Card Boot Utility Altera Corporation GJ Send Feedback Linux Software Development Tools 2014 12 15 ug 1137 lt Subscribe GJ Send Feedba
132. ion Code for Web Edition and 30 Day Evaluation Altera Corporation Licensing G send Feedback ug 1137 Eas l z 2014 12 15 Activating the License Figure 3 4 Add License Obtain a New License r aA TA i ae ye f m p ee ALTI ra Le k w Obtain a new license Select the type of license to create for this computer Enter a serial number or activation code O Use an existing license file or license server address _ Generate a 30 day evaluation license D Manually obtain a license via www arm com website Finish Cancel 5 Click Next 6 In the Add License Choose Host ID dialog box select the Host ID Network Adapter MAC address to tie the license to If there are more than one option select the one you desire to lock the license to and click Next Licensing Altera Corporation GJ Send Feedback oe l ug 1137 3 6 Activating the License 2014 12 15 Figure 3 5 Add License Choose host ID Choose host ID Choose a host ID that the license will be locked to al ae dd License ho riit piei era oe i The license is locked to the selected host ID ARM recommends selecting the host ID of a physical device If a virtual device is selected the license will stop working 7 In the Add License Developer account details dialog box enter an ARM developer Silver account If you do not have an account it can be created easily by clicking the provided link After entering the account information click Finish
133. ion number and exits Linux Software Development Tools Altera Corporation GJ Send Feedback ug 1137 12 4 Device Tree Generator 2014 12 15 Figure 12 1 Sample Output from Utility alt boot disk util Altera Boot Disk Utility Copyright C 1991 2014 Altera Corporation Usage write preloader to disk alt boot disk util p preloader a write disk file fwrite bootloader to disk alt boot disk util b bootloader a write disk file write BOOTloader and PREloader to disk alt boot disk util p preloader b bootloader a write disk file write BOOTloader and PREloader to disk drive E alt boot disk util p preloader b bootloader a write d E Options version show program s version number and exit h help show this help message and exit b FILE bootloader FILE bootloader image file p FILE preloader FILE preloader image file a ACTION action ACTION only supports write action d DRIVE drive DRIVE specify disk drive letter to write to options error disk not specified Device Tree Generator A Device Tree is a data structure that describes the underlying hardware to an operating system primarily Linux By passing this data structure to the OS kernel a single OS binary may be able to support many variations of hardware This flexibility is particularly important when the hardware includes an FPGA The Device Tree Generator tool is part of Altera SoC EDS and is used to create device
134. ith status v gt 0 A Command ress amp a amp Locals yf D X M OV 3 B 3 Name Value 0 variable File Statics current E Globals Linked ne A Linked TestConfiguration 7 B lt Net Instruction gt MM App Co 58 S Hello Word p R TestConfiguration application exit code 0 Altera Cyclone V SoC Dual Core 100 be Gl Ex Ob Target Error Log Linked TestConfiguration Getting Started with ARM Compiler Bare Metal Project Management This section presents a complete bare metal example demonstrating the ARM Compiler bare metal project management features of the ARM DS 5 Altera Edition Start Eclipse 1 Start Eclipse 2 Select a new workspace to use for example c Workspace and press OK Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 4 26 Create a New Project ve 2 15 Figure 4 5 Select a Workspace F E LAT s PE appmeRer W WOrkspace Launcher Select a workspace Eclipse Platform stores your projects in a folder called a workspace Choose a workspace folder to use for this session Workspace Use this as the default and do not ask again Create a New Project 1 Go to File gt New gt Project Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 201 4 12 15 Create a New Project 4 27 Figure 4 6 New Project File Edit Source Re
135. ith the help of the Remote System Explorer RSE Before this feature can be used the RSE needs to be configured to connect to the target board running Linux 1 In your Eclipse workspace select Window gt Open Perspective gt Other This will open the Open Perspective dialog box 2 In the Open Perspective dialog box click the Remote System Explorer and click OK 3 In the Remote System Explorer view right click Local and select New gt Connection This will open the New Connection wizard Note Clicking the sign achieves the same result Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 56 Create New Connection 1 Remote Sy X Team 70O wt 2 A Define a connection to remote system gt 74 Local Files fy Local Shells Setting up Remote System Explorer 4 83 4 In the first page of the New Connection wizard named Remote System Type view select SSH only and click Next Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 4 84 Setting up Remote System Explorer 2014 12 15 Figure 4 57 New Connection window New Connection Select Remote System Type Connection for SSH access to remote systems system type v General ty FTP Only A Linux El Local SSH Only unix UNIX ii Windows Cancel 5 Enter the IP address of the board in the Host Name field Click Finish to create the connection Getting Started Guides G
136. iver Debug m Target Connection DTSL Options Configure USB Blaster trace or other target options Using default configuration DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections Bare Metal Debug Connection Cross Trigger Settings The Cross Trigger tab allows the configuration of the cross triggering option of the SoC FPGA The following options are available e Enable FPGA gt HPS Cross Trigger for enabling triggers coming from FPGA to HPS e Enable HPS gt FPGA Cross Trigger for enabling triggers coming from HPS to FPGA e Assume Cross Triggers can be accessed the user needs to select this option as a confirmation that the Preloader was already loaded so the DS 5 can access the cross triggering interface ARM DS 5 Altera Edition GJ Send Feedback Altera Corporation ug 1137 5 36 Trace Buffer Settings Dra Figure 5 33 DTSL Configuration Editor Cross Trigger Cross Trigger Trace Buffer Cortex A9 STM ETR ETF Enable FPGA gt HPS Cross Trigger C Enable HPS gt FPGA Cross Trigger Cross Trigger initialization The Cross Trigger interface can only be accessed if the system clocks have been initialized If the Cross Trigger interface is accessed prior to the clock initialization then the target may lock up The folllowing option should only be set if you are sure that the system clocks have been initialized prior to DS
137. kefile Makefile used to compile the sample application Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 82 Compiling the Linux Application Debugging Sample Application 2014 12 15 Compiling the Linux Application Debugging Sample Application 1 To compile the application select the project in Project Explorer 2 Select Project gt Build Project 3 The project compiles and the Project Explorer shows the newly created helloexecutable file as shown in the figure below The Console dialog box shows the commands and responses that were executed Figure 4 55 Project Compiled C C Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window Help Eas SQ GIP Sa e amp eet o ag x ew ww Fas P 52 A e Y An outline is not available v W Altera SoCFPGA I b 4 Binaries gt iy Includes B gt 9 hello c E 2a hl S a Ss ee CDT Build Console Altera SoCFPGA HelloWorld Linux GNU gt B hello o arm En Build of configuration Default for project AlL hello map arm Linux gnueabihf gcc g 00 Werror Wall c hello c o gt Makefile arm linux gnueabihf gcc g 00 Werror wall hello o o hel arm linux gnueabihf nm hello gt hello map Problems Tasks Console X Properties B p gt 5 Altera SoCFPGA HelloWorld Linux GNU hello Setting up Remote System Explorer The ARM DS 5 AE can run and debug programs directly on the target w
138. le application uses the following files e FPGA configuration SRAM Object File sof e Preloader executable file for proper initialization of the GSRD HPS component Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Starting the Eclipse IDE 4 59 The sample application is built with a makefile that performs the following steps l 2 Copies Hardware Libraries source code from installation folder to the current project folder Compiles the example C source code files with the GNU Compiler Collection GCC tool chain from Mentor Graphics Copies the sof file from the GSRD folder Converts the sof file to a compressed Raw Binary File rbf format with the quartus_cpf utility available in the Altera Complete Design Suite or the Quartus II software programmer Converts the rbf to an equivalent Executable and Linking Format File elf object file with the GCC objcopy utility Links the example program and the FPGA configuration resource object files into the HWLIB example executable file A debugger script performs the following steps to help execute the sample application l Zi 3 Loads the preloader image and places a breakpoint at the end of the image Runs the preloader image until it reaches the breakpoint This properly configures the HPS component according to the GSRD Loads the HWLIB sample application Related Information Hardware Library on page 8 1 For more i
139. le in the current Workspace Create manage and run configurations Debugger Debugging from a symbol but no symbol files defined in the Files tab type filter text ion lis Files amp OS Awareness 60 Arguments PG Environment fe C C Application fe C C Attach to Application Target Configuration Application on host to download E C C Postmortem Debugge fe C C Remote Application 4 2 DS 5 Debugger Jk New_configuration 7 meree e Ree Iron Python Run o A onnaa Files Java Applet FJ Java Application Load symbols from file v Ju JUnit a Jython run 2 Jython unittest File System Launch Group CI PyDev Django PyDev Google App Run e Python Run g Python unittest Z Remote Java Application gy E Filter matched 19 of 19 items 8 Browse to the executable and click OK Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 22 Debug Application re 2 15 i ae ee Select a file gt Z RemoteSystemsTempFiles 4 W TestProject E cproject project _ subdir mk test d lor test o test c 9 Click the Debug button to download the application and start the debug session Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 E 4 12 15 Debug Application 4 23 Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session 3 x Y Name
140. lib c Eclipse Platform File Edit Source Refactor Navigate Search Project Run Window Help in aE THY Q ia gt eS i i otm Quick Access I Variables Breakpoints mo Registers 3 25 Expressions fO Functions 4 Linked Altera SoCFPGA HardwareLib FPGA CV GNU Debug Name Value Size Access 6 usb0 i More gt usbl h altera_avalon_sysid_sysid_qsys_control_slave altera_avalon_pio_led_pio_sl altera_avalon_pio_led_pio_sl1_DATA exeeeeeece 32 R W data 32 R W altera_avalon_pio_led_pio_sl_DIRECTION exeeceeeeee 32 R W q Peripherals Saltera_avalon_pio_led_pio_sl Saltera_avalon_pio_led_pio_sl_DATA data cs q Reads Data value currently on PIO inputs Writes New value to drive on PIO outputs altera_avalon_pio_led_pio_sl_SET_BIT altera_avalon_pio_led_pio_sl1_CLEAR_BITS altera_avalon_pio_dipsw_pio_sl altera_avalon_pio_button_pio_sl 11 You can resume the code several times by pressing F8 and you will see how the DATA register changes and the HPS LEDs on the board are lighted accordingly 12 You can also change the DATA register manually and see the LEDs being lighted accordingly 13 Collapse the soft IP register group to avoid the debugger accessing them on the next debugging session before they are accessible 14 Click Disconnect from Target button to close the debugging session Note Do not try to access the soft IP registers before the FPGA is programmed or before the br
141. lication Debug e Connections via gdbserver e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application Depending on the selected Target the Connections panel will look different For Bare Metal Debug and Linux Kernel and or Device Driver Debug target types e A Target Connection option appears and it allows the user to select the type of connection to the target Altera USB Blaster and DSTREAM are two of the most common options e A DTSL option appears allowing the user to configure the Debug and Traces Services Layer detailed later e A Connections Browse button appears allowing the user to browse and select either the specific instance for the connection i e Altera USB Blaster or the DSTREAM instance Figure 5 24 Connection Options for Bare metal and Linux Kernel and or Device Driver Debug Name Sample Configuration Ei Connection Files Ss Debugger abs OS Awareness Arguments B Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 4 Altera Arria V SoC Cyclone V SoC Dual Core 4 Bare Metal Debug Debug Cortex A9 0 Debug Cortex A9 1 Debug Cortex A9x SMP gt Linux Application Debug m gt Linux Kernel and or Device Driver Debug Me Target Connection DTSL Options Configure USB Blast
142. load And Debug Application Name Sample Configuration A Connection gt Lin Files H Debugger i OS Awareness 69 Arguments PS Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Application Debug Download and debug application Cyclone V SoC Dual Core gt Bare Metal Debug 4 Linux Application Debug Connect to already running qdbserver Download and debug application te ae I ee S E ce E Oe Se Ee H am DS 5 Debugger will download your application to the target system and then start a new gdbserver sessioouq the application This configuration requires ssh and gdbserver on the target platform Connections RSE connection Use RSE Host 5000 Use Extended Mode Note For the Linux Application Debug the Connection needs to be configured in the Remote System Explorer view as shown in Getting Started with Linux Application Debugging Related Information e DTSL Options on page 5 34 For more information about the option on the Connections tab refer to the DTSL Options section e Debugger Options on page 5 31 e Getting Started with Linux Application Debugging on page 4 78 Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 spas Files Options 5 31 Files Options The Files tab allows the following settings to be configured e Application on host to download the file name
143. m operation the tool verifies the data programmed Example 9 5 Erase Flash on the Flash Addresses quartus_hps c 1 o EB input bin erases the flash on the flash addresses where the input file input bin resides followed by a blank check using a cable M Example 9 6 Erase Full Chip quartus_hps c 1 o E erases the full chip using a cable M When no input file input bin is specified it will erase all the flash contents Example 9 7 Erase Specified Memory Contens of Flash quartus_hps c 1 o E a 0x100000 s 0x400000 erases specified memory contents of the flash For example 4 MB worth of memory content residing in the flash address starting at 1 MB are erased using a cable M Example 9 8 Examine Data from Flash quartus_hps c 1 o X a 0x98679 s 56789 output bin examines 56789 bytes of data from the flash with a 0x98679 flash start address using a cable M HPS Flash Programmer User Guide Altera Corporation GJ Send Feedback l ug 1137 9 6 Supported Memory Devices 2014 12 15 Supported Memory Devices Table 9 2 QSPI Flash Micron 0x18BA20 Spansion 0x182001 l 128 Sector size of 64 KB Spansion 0x182001 1 128 Sector size of 256 KB Spansion 0x190201 256 Sector size of 64 KB Spansion 0x190201 l 256 Sector size of 256 KB Table 9 3 ONFI Compliant NAND Flash Micron 0x2C 0x68 Altera Corporation HPS Flash Programmer User Guide GJ Send Feedback ug 1137 2014 12 15 Supported Memory Devices 9 7
144. m common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYAN 101 Innovation Drive San Jose CA 95134 HPS Preloader User Guide 2013 05 03 ug 1137 o lt Subscribe GJ Send Feedback There are four stages of the hard processor system HPS booting process the preloader is the second stage Figure 7 1 Typical Boot Flow Boot ROM Operating System The Preloader configures the HPS component based on the information from the handoff folder initial izes the SDRAM and then loads the next stage of the boot process into SDRAM and passes control to it The preloader can directly load your final application for Bare Metal applications and simple RTOSes Typically a boot ROM loads the preloader from a flash device into the on chip RAM and executes the preloader The preloader can also be executed directly from the FPGA memory Related Information e Arr
145. mation Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JN Oe RYA 101 Innovation Drive San Jose CA 95134 St l ug 1137 3 2 Activating the License 2014 12 15 the Altera website http dl altera com soceds and then activate your license in DS 5 as shown in the Activating the License section Related Information e SoC EDS Download Page e Activating the License on page 3 2 Activating the License This section presents the steps required for activating the license in DS 5 Altera Edition by using the serial license number or activation code that were mentioned in the Getting the License section Note An active user account is required to activate the DS 5 Altera Edition license If you do not have an active user account it can be created on the ARM Self Service page available on the ARM website silver arm com 1 The first time the Eclipse IDE from the ARM DS 5 is run it notifies you that it requires a license Click the Open License Manager button Figure 3 1 No License Found S No Licenses Found i ARM D5 5 is license managed but there are no registered licenses Use the ARM License Manager to obtain and add licenses You can open the ARM License Manager at any time from the Eclipse
146. metal application eal Remote Java Application Connections Bare Metal Debug Connection i lt Filter matched 19 of 19 items 5 Click the Connection gt Browse button to select the connection to the target board 6 Select the desired target and click Select Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 46 Debug Application 2014 12 15 Figure 4 24 Target Connection Connection Browser Select a target connection USB Blasterll USB 1 USB Blasterll on localhost USE 1 7 Go to Files tab gt Target Configuration gt Application on the host to download and click the Workspace buton to browse for the executable in the current workspace Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Temxlex type filter text fe C C Application fe C C Attach to Application E C C Postmortem Debugge fe C C Remote Application 4 7 DS 5 Debugger 2 New_configuration Iron Python Run 2 Iron Python unittest Java Applet O Java Application Ju JUnit 2 Jython run 2 Jython unittest Launch Group ij PyDev Django 23 PyDev Google App Run 2 Python Run Python unittest eal Remote Java Application Filter matched 19 of 19 items Figure 4 25 Target Configuration Create manage and run configurations _ Debugger Debugging from a symbol but no symbol files defined in the Files tab Debug Appli
147. n Libraries APIs alt_dma_init Init DMA module driver alt_dma_channel_ Allocate DMA channel socfpga_dma_setup alloc_any socfpga_fpga_setup socfpga_bridge_ setup socfpga_bridge_io alt_dma_channel_ Check state of DMA channel state_get alt_fpga_init Init FPGA manager driver Query the FPGA state Enable controlling the FPGA alt_fpga_state_get alt_fpga_control_ enable alt_fpga_cfg_mode_ get Query the configuration mode alt_fpga_configure_ Configure the FPGA using the DMA alt_bridge_init Initialize bridges O rab alt_addr_space_remap Remap address space N A Application accesses Soft IP directly Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Getting Started with Peripheral Register Visibility 4 67 Sequence Sample Application Used Hardware Description Function Libraries APIs 12 socfpga_bridge_ alt_bridge_uninit Deinitialize bridges cleanup 13 alt_fpga_control_ Disable control of FPGA socfpga_fpga_ disable cleanup 14 alt_fpga_uninit Close the FPGA driver 15 socfpga_dma_ alt_dma_channel free Deallocate the DMA channel 16 cleanup Close the DMA driver Getting Started with Peripheral Register Visibility The ARM DS 5 Altera Edition allows you to specify the peripheral IP register descriptions using svd files The svd files are resulted from the hardware project compilation using ACDS The svd files contain the description of both HPS peripheral registers such a
148. n tools can be used lt SoC EDS installation directory gt host_tools mentor gnu arm baremetal bin The bare metal compiler comes with full documentation located at lt SoC EDS installation directory gt host_ tools mentor gnu arm baremetal share doc sourceryg arm altera eabi The documentation is offered in four different formats to accommodate various user preferences e Html files e Info files e Man pages e PDF files Among the provided documents are e Compiler manual e Assembler manual e Linker manual e Binutils manual e GDB manual e Getting Started Guide e Libraries Manual 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Alt
149. nabling Cross triggering on HPS 1 Cross triggering can be enabled in the DTSL dialog box which can be accessed from the Connection tab of the Debug Configuration Altera Corporation Getting Started Guides GJ Send Feedback 1137 ET Enabling Cross triggering on HPS 4 99 Figure 4 76 Debug Configuration Connection Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Kernel and or Device Driver Debug Debug Cortex A9x2 SMP v Altera gt Aria V SoC wv Cyclone V SoC Dual Core gt Bare Metal Debug gt Linux Application Debug Linux Kerel and or Device Driver Debug Debug Cortex A9 0 Debug Cortex A9_ 1 Debug Cortex A9x2 SMP Target Connection USB Blaster H DTSL Options Configure USB Blaster trace or other target options Using default configurat DS 5 Debugger will connect to an Altera USB Blaster to debug a SMP Linux kemel 2 The Cross Trigger tab of the DTSL Configuration Editor allows Cross trigger configuration Figure 4 77 HPS Cross Trigger Configuration Cross Trigger Trace Buffer Cortex A9 STM ETR ETF O Enable FPGA gt HPS Cross Trigger O Enable HPS gt FPGA Cross Trigger Cross Trigger initializatio 7 The Cross Trigger interface can only be accessed if the system clocks have been initialized If the Cross Trigger interface is accessed prior to the clock initi
150. ndoff folder The rest of the Preloader settings are populated automatically Figure 4 2 Populated Options in the New BSP Window New BSP Hardware Preloader settings directory examples hardware cv_soc_devkit_ghrd hps_isw_handoff soc_system_hps_0 a Software Operating system Preloader Version default V Use default locations BSP target directory 2ra 14 0 embedded examples hardware cv_soc_devkit_ghrd software spl_bsp BSP Settings Filename sedded examples hardware cv_soc_devkit_ghrd software spl_bsp settings bsp Enable Settings File relative paths Enable Additional Td script 6 Click OK to close the New BSP dialog box This will populate the BSP Editor dialog box with the default settings Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Figure 4 3 Default Options in the BSP Editor window ncn a ae lt a a A c a yl v Arr AN Yaca EAEAN ya Ad of pce L a m T prap ta U are ek NT AA es oe re 3SP Edito 0 1 alte a Q mbedded lt fi ples vare ar YV SO vkit_ g d sc we cn ssp settinas bsr es N o a rr oO _ z gt gt File Help Getting Started with Preloader 4 5 SOPC Information file CPU name Operating system BSP target directory Settings Sika S spl F BOOT_FROM_QSPI PRELOADER_TGZ a CROSS_ COMPILE F BOOT_FROM_SDMMC wag F BOOT_FROM_NAND BOOT_FROM_QSPI BOOT_FROM_SDMMC BOOT_F
151. nformation refer to the Hardware Libs Overview section in this document Mentor Code Sourcery For more information about the Sourcery CodeBench Lite Edition including ARM GCC IDE refer to the Embedded Software page on the Mentor Graphics website Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation Starting the Eclipse IDE l Select Start Menu gt Programs gt ARM DS 5 gt Eclipse for DS 5 to start Eclipse Alternatively you can run eclipse command from the Embedded Command Shell The Eclipse tool part of ARM DS 5 AE prompts for the workspace folder to be used Use the suggested folder and click OK The ARM DS 5 AE Welcome screen appears It is instructive and can be used to access documenta tion tutorials and videos Select Window gt Open Perspective gt DS 5 Debug to open the Workbench Alternatively you can Click on the link Go to the Workbench located under the list of DS 5 Resources Importing the Hardware Library Sample Application l In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Getting Started Guides Altera Corporation GJ Send Feed
152. nux console run the command ifconfig to determine the IP address of the board A U On the Linux console change the root password by running the passwd command Ignore the warnings about a weak password Related Information e Getting Started with Board Setup on page 4 1 For more information refer to the Getting Started with Board Setup section e Getting Started with Running Linux on page 4 2 For more information refer to the Getting Started with Running Linux section Starting Eclipse with the Embedded Command Shell 1 Start an Embedded Command Shell by running lt SoC EDS installation directory gt embedded_command_ shell sh 2 Start Eclipse by running the eclipse command from the Embedded Command Shell 3 The Eclipse tool part of the ARM DS 5 AE prompts for the workspace folder to be used Accept the suggested folder and click OK 4 The ARM DS 5 AE Welcome screen appears It can be used to access documentation tutorials and videos 5 Select Window gt Open Perspective gt DS 5 Debug to open the Workbench Alternatively you can Click on the link Go to the Workbench located under the list of DS 5 Resources Importing the Linux Application Debugging Sample Application 1 In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Getting Started Guides Al
153. o adl gry oer O7 QFN Vir p v K Quick Access FY Ea 2 If Pro 53 i e a7 31 o am B 7 4 gt gt Altera SoCFPGA Hardu An outline is not K Includes available alt_address_space c alt_bridge_manager alt_cache c alt_clock_manager alt_dma_program c ab S ue e cei rf rr alt_dma c CDT Build Console Altera SoCFPGA HardwareLib FPGA CV GNU alt_fpga_manager c arm altera eabi objcopy treating that number as an absolute e machi hwlib c arm altera eabi objdump d oo gt meS aoe rm ra nm hwlib axf gt hwlib axf m EPE es p po Baa 14 0 pect ds 5 i een hardware cv_soc_devk fer arm altera eabi objdump d u boot spl axf gt u boot spl axf objdump alt_cache o arm alt_clock_manager 15 57 42 Build Finished took 13s 769ms 4 m gt mm Problems Yj Tasks EJ Console 52 E Properties m 3 The project compiles and the Project Explorer shows the newly created hello axf executable file as shown in the above figure The Console dialog box shows the commands and responses that were executed Running the Bare Metal Debugging Sample Application Before running the sample application perform the following setup e Setup the board as described in Getting Started with Board Setup e Connect mini USB cable from DevKit board connector J37 to PC e Connect 19V power supply to the DevKit e Turn on the board using the PWR switch 1 Select Run gt Debug Configurations to ac
154. o be Altera gt Cyclone V SoC Dual Core gt Bare Metal Debug gt Debug Cortex A9_0 and Target Connection to be USB Blaster Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 1 4 12 15 Debug Application 4 45 Figure 4 23 Debug Configuration Connection Tab Vet Create manage and run configurations Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty Sexl ex type filter text Be Connection gt B Debugger OS Awareness 6 Arguments P Environment E C C Application E C C Attach to Application Select target E C C Postmortem Debuggs Select the manufacturer board project type and debug operation to use Currently selected E C C Remote Application Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 4 4 DS 5 Debugger 2 New_configuration Iron Python Run a Altera Iron Python unittest b Arria V SoC Java Applet a Cyclone V SoC Dual Core O Java Application a Bare Metal Debug Ju JUnit Debug Cortex A9_0 2 Jython run Debug Cortex A9_1 2 Jython unittest Debug Cortex A9x2 SMP gt Launch Group i CI PyDev Django Target Connection USB Blaster v 23 PyDev Google App Run Python ig DTSL Options Configure USB Blaster trace or other target options Using default configuration Python unittest DS 5 Debugger will connect to an Altera USB Blaster to debug a bare
155. of functional APIs that address more complex configuration and operational control aspects of selected HPS resources The HW Manager functions have the following characteristics e Functions employ a combination of low level device operations provided by the SoCAL executed in a specific sequence to effect a desired operation e Functions may employ cross functional such as from different IP blocks device operations to implement a desired effect e Functions may have to satisfy specific timing constraints for the application of operations and validation of expected device responses e Functions provide a level of user protection and error diagnostics through parameter constraint and validation checks The HW Manager functions are implemented using elemental operations provided by the SoCAL API to implement more complex functional capabilities and services The HW Manager functions may also be Altera Corporation Hardware Library GJ Send Feedback ug 1137 2014 12 15 Hardware Library Reference Documentation z implemented by the compound application of other functions in the HW Manager API to build more complex operations for example software controlled configuration of the FPGA Hardware Library Reference Documentation Reference documentation for the SoCAL API and HW Manager API is distributed as part of the SoCEDS Toolkit This reference documentation is provided as online HTML accessible from any web browser The locations o
156. ompiler tools to target an SoC FPGA e Compiles the source files in lt bsp directory gt uboot socfpga with the user specified cross compiler specified in the BSP settings and stores the generated preloader binary files in lt bsp_directory gt uboot socfpga spl e Converts the preloader binary file to a preloader image lt bsp_directory gt preloader mkpimage bin with the mkpimage tool The mkpimage tool is part of the SoC EDS It inserts the correct header information and creates an Altera boot ROM compatible image of the preloader You can run the make utility in the command shell to compile the preloader in the BSP directory The makefile contains the following targets e make all compiles the preloader e make clean deletes preloader mkpimage bin from the lt bsp directory gt e make clean all deletes lt bsp directory gt including the source files in the directory Related Information Preloader Image Tool on page 7 16 Configuring FPGA from Preloader The Preloader has the ability to configure the FPGA by using configuration data stored in one of the following two locations e specific address in QSPI Flash e specific file name on a SD MMC FAT Partition In order to configure the FPGA an RBF file needs to be used The RBF file is obtained by converting a SOF file to RBF by using the Quartus II Programmer HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 16 RBF File Stored in QSPI Flash Memory 2
157. ompiling the code Make sure it has the all and the clean targets 5 Eclipse now offers the possibility of invoking the build process from the IDE Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 BE 2014 12 15 GCC Based Bare Metal Project Management z Figure 5 3 Eclipse IDE build process invoked Bie Edit Source Refactor Navigate Search Project Run Window Help ir ES cj Open ope Bieter es cle ret Ry Pr x Ia A Str 8 Build All 2 5 Build Configurations 4 cs sample project ae ye An outline is not gay gae Build Worki Set i gt fap Includes ul ng available gt alt_pt c Clean gt in alt_pt h Build Automatically gt A qspi_demo_blockio c gt A qspi_demo_dma c Make Target A qspi_demo_erase c gt Le qspi_demo_indirect c gt Le qspi_demo c R qspi_demo h gt Altera SoCFPGA Har gt altera socfpga hoste debug hosted ds 2 Problems X Tasks EJ Console Makefile 0 items Description oz x4 i Properties 6 Ifthe compilation tools issue errors Eclipse parses and formats them for you GCC Based Bare Metal Project Management This section shows how the Bare metal toolchain plugin can be used to manage GCC based projects in a GUI environment Creating Project 1 Go to File gt New gt Project ARM DS 5 Altera Edition Altera Corporation C Send Feedback ug 1137 5 6 Creating Project sins Figu
158. on of a sophisticated multi core application processor and its integration with hardened IP peripheral blocks and programmable logic in a SoC architecture Figure 8 1 HW Library User Software SoC FPGA Hardware Hardware Library Within the context of the Soc HW SW ecosystem the HWLIB is capable of supporting software develop ment in conjunction with full featured operating systems or standalone bare metal programming environments The relationship of the HWLIB within a complete SoC HW SW environment is illustrated in the above figure The HWLIB provides a symbolic register abstraction layer known as the SoC Abstraction Layer SoCAL that enables direct access and control of HPS device registers within the address space This layer is necessary for enabling several key stakeholders boot loader developers driver developers board support package developers debug agent developers and board bring up engineers requiring a precise degree of access and control of the hardware resources The HWLIB also deploys a set of Hardware Manager HW Manager APIs that provides more complex functionality and drivers for higher level use case scenarios The HWLIB has been developed as a source code distribution The intent of this model is to provide a useful set of out of the box functionality and to serve as a source code reference implementation that a user can tailor accordingly to meet their target system requirements The capabilities of the
159. on window appears click Next Accept the driver installation and click Install After successful installation click Finish ARM DS 5 AE installation is complete Click Finish Installing the Altera SoC Embedded Design Suite GJ Send Feedback Licensing 3 2014 12 15 ug 1137 gt lt subscribe GJ Send Feedback The SoC EDS is available with three different licensing options e Subscription edition e Free web edition e 30 day evaluation of subscription edition The only tool impacted by the selected licensing option is the ARM DS 5 Altera Edition All the other tools offer the same level of features in all licensing options for example the preloader generator and the bare metal compiler offer the same features no matter which licensing option is used The main difference between the licensing options depends on which types of debugging scenarios are enabled Web edition e Linux application debugging over ethernet Subscription edition e JTAG based Bare Metal Debugging 30 day evaluation of the subscription edition E TAG based Linux Kernel and Driver Debugging e Linux Application Debugging over Ethernet Getting the License Depending on the licensing option it is necessary to follow the steps detailed for each option to obtain the license Subscription Edition If you have purchased the SoC EDS Subscription Edition then you have already received an ARM license serial number This is a 15 digit alphanumeric string
160. opment board Related Information Getting Started with ARM Compiler Bare Metal Project Management on page 4 25 Debugging ARM DS 5 AE offers you a variety of debugging features Accessing Debug Configurations Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 201 4 12 15 Creating a New Debug Configuration 5 23 The settings for a debugging session are stored in a Debug Configuration The Debug Configurations window is accessible from the Run gt Debug Configurations menu Figure 5 21 Accessing Debug Configurations File oes FA 7 WY oo B te vy G gt Set Next Statement Ctrl Alt R Run Ctri F11 i E Debug Fil gt p Run History gt 4 Y5 Altera SoCFPGA HelloW Run As gt Bisnot gt K Includes Run Configurations gt e hello c gt e hello o arm le Debug History Altera SoCFPGA Hell Debug As ea hello axf Debug Configurations hello axf map l gt hello axf objdump Makefile gt semihost_setup ds F E ri CDT Build Console Alte Toggle Method Breakpoint arm aitera ap1 g Toggle Watchpoint y marci arm altera eabi g mtune arm altera eabi ot X Skip All Breakpoints arm altera eabi n Remove All Breakpoints 12 50 07 Build Fi Breakpoint Types Manage Python Exception Breakpoints Toggle Breakpoint Ctri Shift B fi Problems Tasks Toggle Line Breakpoint Disable Step into properties External Tools Cre
161. ot generated for all soft IP cores Related Information e HPS Preloader User Guide on page 7 1 e Device Tree Generator Introduction to SoC Embedded Design Suite Altera Corporation GJ Send Feedback Installing the Altera SoC Embedded Design Suite 2 2014 12 15 ug 1137 o lt Subscribe GJ Send Feedback You must install the Altera SoC Embedded Design Suite EDS and the ARM Development Studio 5 DS 5 Altera Edition AE Toolkit to run the SoC EDS on an Altera SoC hardware platform Installation Folders The default installation folder for SoC EDS is e lt SoC EDS installation directory gt e c altera 14 1 embedded on Windows e altera 14 1 embedded on Linux The default installation folder for Quartus Programmer is e lt Quartus installation directory gt e c altera 14 1 qprogrammer on Windows e altera 14 1 qprogrammer on Linux Note The installation directories are defined as follows e lt Altera installation directory gt to denote the location where Altera tools are installed e lt SoC EDS installation directory gt to denote the location where SoC EDS is installed Installing the SoC EDS Perform the following steps to install the SoC EDS Tool Suite in a Windows based system 1 Download the latest installation program from the SoC Embedded Design Suite page of the Altera website 2 Run the installer to open the Installing SoC Embedded Design Suite EDS dialog box and click Next to start the Setup Wi
162. pied by each function e Histogram with function allocation Related Information e ARM DS 5 Altera Edition on page 5 1 For more information refer to the ARM DS 5 Altera Edition section e Cyclone V Coresight Debug and Trace For more information about Tracing refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards website Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 96 Getting Started with Cross Triggering 2014 12 15 Getting Started with Cross Triggering The Altera SoC offers powerful cross triggering capability between the HPS and the FPGA fabric The HPS can trigger the FPGA and also the FPGA can trigger the HPS ARM has updated the DS 5 tool specifically for Altera to enable this SoC capability to be easily used This section presents an example of how cross triggering can be used The Golden Hardware Reference Design GHRD contains the necessary instrumentation to be able to use Quartus Signal Tap II tool to demonstrate cross triggering The Quartus Signal Tap II utility is an optional component of the SoC EDS installation and is selected by default
163. pio 3 fpga_led_pio o EIE fpga_led_pio 1 Ee ipga_led_pio 2 __ tpga_ted_pio 3 et nstjdata out 0 s instjdata_out Data 2a Setup 11 Go back to the Eclipse debugger you will notice the execution has stopped When SignalTap II is triggered caused by a state change of the DIP switch it sends the trigger to HPS which in turn stops the cores as instructed Related Information e Cross triggering Prerequisites on page 4 96 For more information refer to the Cross triggering Prerequisites section in this document e Enabling Cross triggering on HPS on page 4 98 For more information refer to the Enabling Cross triggering on HPS section in this document Altera Corporation Getting Started Guides GJ Send Feedback 1137 err ee Enabling Cross triggering on FPGA 4 103 Enabling Cross triggering on FPGA For this getting started scenario we are using Quartus SignalTap II utility to control FPGA cross triggering Figure 4 84 SignalTap Cross Trigger Options Trigger Nodes Allocated Auto O Manual Zs Trigger flow control Sequential Trigger position Pre trigger position Trigger conditions 1 Trigger in opm fe O node sid t O Instance a Hard Processor System HPS trigger out Pattern q High Trigger out Pin Instance s Hard Processor System HPS trigger in Hard Processor System HPS event Level Active High Latency delay 5
164. pl boot QSPI_NEXT_BOOT_IMAGE 0x50000 Related Information BSP Settings on page 7 9 Preloader Support Package Files and Folders The files and folders created with the preloader support package are stored in the location you specified in BSP target directory in the New BSP dialog box Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 a 3 05 03 Command Line Tools for the Preloader Support Package Generator 7 5 Figure 7 3 PSP Directory bsp_ directory Settings bsp Makefile generated The BSP files include e settings bsp the settings file containing all BSP settings e Makefile the makefile to create the preloader image for more information refer to Preloader Compilation e generated this folder contains files generated from the hardware handoff files from the Qsys system integration tool Related Information Preloader Compilation on page 7 15 Command Line Tools for the Preloader Support Package Generator The BSP command line tools can be invoked from the embedded command shell and provide all the features available in the preloader support package generator e The bsp create settings tool creates a new BSP settings file e The bsp update settings tool updates an existing BSP settings file e The bsp query settings tool reports the setting values in an existing BSP settings file e The bsp generate files tool generates a BSP from the BSP settings file Note Help for each tool is available
165. ppended to the boot image before the preloader loads the next stage boot image in the HPS booting process The next stage boot image is a U boot image an RTOS or a bare metal application The mkimage utility is delivered with SoC EDS The mkimage tool appends the mkimage header to the next image Figure 7 6 mkimage Header from mkimage Tools Next Stage Boot Image mkimage Signature Header 0x0000 Altera Corporation HPS Preloader User Guide GJ Send Feedback ug 1137 9013 05 03 mkimage Tool Options 7 21 The preloader reads the following information from mkimage header Image magic number determines if the image is a valid boot image Image data size the length of the boot image to be copied Data load address the entry point of the boot image Operating system determines if the image is a U boot image or another type of image Image name the name of the boot image 6 Image CRC the checksum value of the boot image a ee Figure 7 7 mkimage Header Layout from mkimage Tools 0x0040 0x0030 Image name 0x4 0x8 OxC OxD OxE OxF 0x0020 0x0010 0x0000 mk image invokes the mkimage tool and the ne1p option provides the tool description and option information mkimage Tool Options The help option of the mkimage tool provides the tool description and option information S mkimage Usage mkimage 1 image l gt list image header information mkimage x A arch O os T type C comp a
166. ption e Resource Open Project Close Project Build All Build Configurations Build Project Build Working Set Clean V Build Automatically Make Target C C Index Properties ug 1137 2014 12 15 An outline is not available Then in the Project Properites window the Compilation settings can be accessed by selecting C C Build gt Settings Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 l l ae 2014 12 15 ARM Compiler Bare Metal Project Management 5 Figure 5 9 Project Settings Coia type filter text Settings Resource Builders oo a a C C Build Configuration Debug Active Manage Configuratio Build Vanables Environment Logging Tool Settings Build Steps Build Artifact e Binary Parsers Error Parsers settings Tool Chain Editor a amp 3 GCC C Compiler Command arm altera eabi gec C C General get Target Project References 22 Preprocessor Run Debug Settings 3 Symbols ce Includes 3 Optimization ce Debugging g Warnings Expert settings 3 Miscellaneous Command a 3 GCC Assembler line pattern 22 Target 3 Symbols Includes 3 Debugging 3 Wamings All options 00 g Wall HCOMMANDI S FLAGS HOUTPUT_FLAG S OUTPUT_PREI 2 Miscellaneous a 3 GCC C Linker 3 Image Ge Libraries et Objects Ge Warnings Miscellaneous The Build Settings incldue detailed settings for all tools e Compiler e Assemble
167. r e Linker The Getting Started Guides chapter in this document contains complete instructions on how to create a project from scratch compile it and run it on an Altera SoC development board ARM Compiler Bare Metal Project Management This section shows ARM DS 5 can be used to manage ARM compiler projects in a GUI environment Creating a Project 1 Start Eclipse 2 Go to File gt New gt Project ARM DS 5 Altera Edition GJ Send Feedback Altera Corporation 5 12 Creating a Project Figure 5 10 New Project File Edit Source Refactor Navigate Search Project Run Window Help Alt Shift N gt Makefile Project with Existing Code New Open File Close Close All Save Save As Save All Revert Move Rename Refresh Convert Line Delimiters To Print Switch Workspace Ctri W Ctri Shift W Ctri S Ctri Shift S f a G ef E 68 cs in Bi GS cs C Project C Project Project Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Template Class Other 7 Tasks E Console Properties A Resource 3 Select C C gt C Project and click Next Altera Corporation ug 1137 2014 12 15 em s HES yutline is not able ARM DS 5 Altera Edition GJ Send Feedback ug 1137 201 4 12 15 Creating a Project 5 13 Figure 5 11 Create a New C Project Select a wizard lt gt
168. re 3 Edit the test c file to contain the text shown in the following image Getting Started Guides Altera Corporation GJ Send Feedback 4 40 Build Application Figure 4 18 Text for Test c STEE Ao n yi Pr A A Str P O eg Y 4 iS TestProject gt fap Includes gt Debug gt Q test c E scatter scat Build Application test c 5S 1 include lt stdio h gt 2 35 int main void printf Hello World n return 0 E Problems X Tasks E Console Properties 0 items 1 Build the application by going to Project gt Build Project Altera Corporation ug 1137 2014 12 15 E am Ay i E T QuickAccess i eg Ei 48 S an D5 9 X M es BlZ Rw OK Vv zI stdio h main void int Getting Started Guides GJ Send Feedback ug 1137 Build Application 4 41 e AY 4 pi Baxe joas 2 oe x M 8 BIZ RwWw X 3I stdio h main void int 2014 12 15 Figure 4 19 Build Project Open Project Close Project Build All Build Configurations a cS TestProject i uke rojet K Includes j Build Working Set gt Debug Clean gt test c Build Automatically scatter scat i Make Target C C Index Properties A Problems X 4A Tasks EJ Console Properties 0 items 2 The project is built The console shows the commands and the project shows the TestProject axf executable that was created Getting Started Guides GJ Send Feedback Altera Corporation ug 11
169. re 5 4 Create a New Project l Alt ShifteN Makefile Project with Existing Code ix C Project Ctriew El CProject Close All Ctrl Shift W C2 Erste Convert to a C C Project Adds C C Nature boma Source Folder able Folder Source File Header File peta File from Template Rename Refresh Convert Line Delimiters To Save Ctri 5 Save As Save All Ctrl Shift S Revert Class Print Switch Workspace Restart Import 2 Select C C gt C Project and click Next Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 2014 12 15 Figure 5 5 New C Project Created af 7 R j i P APA em pee a ey NEW Froyect a h a iim a at eat aA Fi Select a wizard Create a new C project Wizards type filter text b amp General 4 t C C E C Proje E C Project Makefile Project with Existing Code p GC CVS gt Java b amp PyDev Creating Project 3 7 3 Determine if you want to create a Bare metal executable empty project or a Bare metal library empty project a Bare metal executable Select Project Type to be Bare metal Executable gt Empty Project then Toolchain to be Altera Baremetal GCC then click Finish ARM DS 5 Altera Edition C Send Feedback Altera Corporation 5 8 Creating Project c i a a ee an ee Figure 5 6 Bare metal Executable Project Type Create C project of selected t
170. rge files e FPGA configuration data At system power up the FPGA configuration controller on the board or HPS read FPGA configuration data from the flash memory to program the FPGA The configuration controller or HPS may be able to choose between multiple FPGA configuration files stored in flash memory e Other arbitrary data files The HPS flash programmer programs a binary file to any location in a flash memory for any purpose For example a HPS program can use this data as a coefficient table or a sine lookup table The HPS flash programmer programs the following memory types e Quad serial peripheral interface QSPI Flash e Open NAND Flash Interface ONFI compliant NAND Flash HPS Flash Programmer Command Line Utility You can run the HPS flash programmer directly from the command line For the Quartus II software the HPS flash programmer is located in lt Altera installation directory gt quartus bin For the Quartus II Programmer the HPS flash programmer is located in lt Altera installation directory gt qprogrammer bin How the HPS Flash Programmer Works The HPS flash programmer is divided into a host and a target The host portion runs on your computer and sends flash programming files and programming instructions over a download cable to the target 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera
171. rogram CRC Checksum Preloader Program impty Preloader Exception Vector Header Preloader Exception Vector 0x0000 As illustrated the binary preloader image is an input to the preloader image tool The compiler leaves an empty space between the preloader exception vector and the program The preloader image tool overwrites this empty region with header information and calculates a checksum for the whole image When necessary the preloader image tool appends the padding data to the output image The header includes e Validation word e Version field set to 0x0 e Flags field set to 0x0 e Program length measured by the number of 32 bit words in the preloader program e 16 bit checksum of the header contents 0x40 0x49 HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 18 Tool Usage 201 3 05 03 Figure 7 5 Header Format 048 Simple Checksum Reserved 0x0 X Program Length Flags Version ox44 A Validation Word 0x31305341 0x40 Tool Usage The preloader image tool has three usage models 1 Single image creation 2 Quad image creation 3 Single or quad image decoding If an error is found during the make image process the tool stops and reports the error Possible error conditions include e The input image size is equal to or less than 80 bytes e The input image size is equal to or greater than 60 kilobytes KB mkpimage invokes the preloader image tool invokin
172. s scenario we do not want the HPS to trigger FPGA Figure 4 80 Disable SignalTap Trigger in O Pin O Node _ O Instance Hard Processor System HPS trigger out Pattern Don t Care 7 In Eclipse debugger let the Linux kernel continue running by pressing the green Continue button or pressing F8 8 In SignalTap II press the Run Analysis button to arm Signal Tap Figure 4 81 Run Analysis Instance Manager gt a m atarra __ Ready to acquire O x Instance status Ryn Analysis P87 7 Memory 102 Small NA Medium NA auto Not running sey cells 10240 bits NA NA Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 102 FPGA Triggering HPS Example 2014 12 15 9 SignalTap II will run the analysis and wait for the trigger from the DIP switch Figure 4 82 Acquisition in Progress Instance Status LEs 587 Memory 102 Small NA Medium NA auto Waitingfor 587 cells 10240bits NA NA 10 Change the state of the FPGA DIP switch 0 SWL 5 on the board This will trigger a Signal Tap II acquisition and stop Signal Tap II This will be indicated by the status changing back to Ready to acquire Note On the Data tab you will be able to see the change on the DIP switch signal Figure 4 83 DIP switch Toggled log 20130906 18 05 21 0 Name re O a e 178 256 et ipga_dipsw_pio 0 a fga dpsw pog O OoOO O O _ tpga_dipsw_pio 2 al fpga_dipsw_
173. s 2014 12 15 This table lists typical tool usage but your actual requirements depend on your specific project and organization Hardware Engineer As a hardware engineer you typically design the FPGA hardware in Qsys You can use the debugger of the ARM DS 5 Altera Edition to connect to the ARM cores and test the hardware A convenient feature of the DS 5 debugger is the soft IP register visibility using Cortex Microcontroller Software Interface Standard CMSIS System View Description svd files With this feature you can easily read and modify the soft IP registers from the ARM side As a hardware engineer you may generate the Preloader for your hardware configuration The Preloader is a piece of software that configures the HPS component according to the hardware design As a hardware engineer you may also perform the board bring up You can use the ARM DS 5 debugger to verify that they can connect to the ARM and the board is working correctly These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Bare Metal and RTOS Developer As either a bare metal or a RTOS developer you need JTAG debugging and low level visibility into the system Use the bare metal compiler to compile your code and the SoC Hardware Library to control the hardware in a convenient and consistent way Use the Flash Programmer to program the flash memory on the target board
174. s UART EMAC and timers and the Soft IP peripheral registers residing on FPGA side This section presents the necessary steps in order to view the HPS registers and the Soft IP registers using the Getting Started with Hardware Library example Note The soft IP register descriptions are not generated for all soft IP cores Do not expect to have registers for all the cores they use on FPGA Some may have it some may not 1 Perform the steps described in the Getting Started with Hardware Library section up to and including configuring the USB Blaster connection 2 In the Eclipse IDE click Run gt Debug Configurations to open the Debug Configurations dialog box 3 In the Debug Configurations dialog box go to the Files panel and under the Files panel a Select Add peripheral description files from directory from the drop down box b Use the browse File System button to browse to the folder lt SoC EDS Folder gt examples hardware cv_soc_devkit_ghrd soc_system synthesis This is where the svd file generated by Quartus II is located Getting Started Guides Altera Corporation GJ Send Feedback P kay aes ug 1137 4 68 Getting Started with Peripheral Register Visibility 2014 12 15 Figure 4 44 Configue Peripheral Register Visibility Name Altera SoCFPGA HardwareLib FPGA CV GNU Debug i Connection cr Files gt 4 Debugger ii OS Awareness Arguments PS Environment Target Configuration Application on host to
175. s in the OCRAM e Allocates a maximum of 16K 0x4000 for stack an heap 5 If desired click on the Regions Section tab and you will see a graphical view of the linker script Getting Started Guides GJ Send Feedback Altera Corporation ug 1137 4 34 Set the Linker Script ie Figure 4 12 Graphical View of the Linker Script E scatter scat 52 Eai OxFFFFFFFF OxFFFFFFFF i I i End C APP_CODE RO RW Z OxFFFFOOOO OxFFFFOO00 000000000 000000000 Load Regions Execution Regions as i TT gt Regions Sections scatter scat Set the Linker Script 1 Go to Project gt Properties Altera Corporation Getting Started Guides GJ Send Feedback 1137 201 4 12 15 Set the Linker Script 4 35 Figure 4 13 Test Project Properties A Open Project A a v2 ia i Close Project Quccscces SB M Str D scatter sca 6 eo Po Build Configurations gt i hn wn x eS y eye 4 cS TestProject poet gt OCRAM gt K Includes 2 Build Working Set gt Debug Clean E scatter scat Build Automatically Make Target C C Index Properties Regions Sections scatter scat ai Problems X A Tasks EJ Console Properties 0 items Description Resor Writable Insert 7 1 2 Go to C C Build gt Settings gt ARM Linker 5 gt Image Layout and then click Browse Getting Started Guides Altera Corporation GJ Send Feedback ug 1137
176. s presented in this section were created using the Windows version of SoC EDS but the example can be run in a very similar way on a Linux host PC Starting the Eclipse IDE 1 Select Start Menu gt Programs gt ARM DS 5 gt Eclipse for DS 5 to start Eclipse Alternatively you can run eclipse command from the Embedded Command Shell 2 The Eclipse tool part of ARM DS 5 AE prompts for the workspace folder to be used Use the suggested folder and click OK 3 The ARM DS 5 AE Welcome screen appears It is instructive and can be used to access documenta tion tutorials and videos 4 Select Window gt Open Perspective gt DS 5 Debug to open the Workbench Alternatively you can Click on the link Go to the Workbench located under the list of DS 5 Resources Importing the Bare Metal Debugging Sample Application 1 In Eclipse select File gt Import The Import dialog box displays 2 In the Import dialog box select General gt Existing Projects into Workspace and click Next This will open the Import Projects dialog box Altera Corporation Getting Started Guides GJ Send Feedback ug 1 137 r 4 3 2014 12 15 Importing the Bare Metal Debugging Sample Application 5 Figure 4 31 Import Existing Project Create new projects from an archiwe file or directory Select an import source type filter text gt General IE Archive File
177. section 2 Open the Debugger configuration and edit DTSL options to enable FPGA cross triggering HPS as shown in the Enabling Cross triggering on HPS section a Un check the Enable FPGA gt HPS Cross Triggering check box b Check the Enable HPS gt FPGA Cross Triggering check box if checked c Check the Assume Cross Triggers can be accessed check box 3 Start the debug session by clicking Debug in the Debug Configuration dialog box The debugger will stop the Linux kernel and display the current HPS state 4 In Signal Tap II make sure all trigger signals are disabled by setting their condition to Don t care Altera Corporation Getting Started Guides GJ Send Feedback 1137 seis HPS Triggering FPGA Example 4 105 Figure 4 86 Trigger Signals Disabled trigger 2013 09 06 17 49 21 0 Lock mode amp Allow trigger ct gt ah F mi i E g T a i 3 10 4 ga_ 1nst data_ ourt 0 5 In Signal Tap II configure the Trigger in to be sensitive to both edges so that the SignalTap II sends the trigger to HPS whenever it performs an acquisition Figure 4 87 Configure Trigger in O Pin O Node Instance Hard Processor System HPS trigger out Pattern x Either Edge lt 6 In Eclipsedebugger let the Linux kernel continue running by pressing the green Continue button or pressing F8 7 In SignalTap II press the Run Analysis button to arm Signal Tap Ge
178. sion of device specifications before relying on any published information and before placing orders for products or services JANOS RYAN 101 Innovation Drive San Jose CA 95134 ug 1137 7 2 Preloader Support Package Generator 2013 05 03 1 Configures the HPS pins I O configuration shift register IOCSR and pin multiplexing 2 Configures the HPS phase locked loops PLLs and clocking 3 Configures the external SDRAM 4 Loads the next image in the boot process typically stored in a flash device such as the NAND flash memory Secure Digital MultiMedia Card SD MMC flash memory or the quad serial peripheral interface QSPI flash memory 5 Jumps to the next loaded boot image Related Information e Cyclone V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook e Arria V Device Handbook Appendix A Booting and Configuration For more information refer to the Booting and Configuration appendix in volume 3 of the Arria V Device Handbook e Importing Sample Application Preloader Support Package Generator The preloader support package generator provides you with an easy safe and reliable way to customize the preloader The preloader image tool creates an Altera boot ROM compatible image of the preloader The preloader support package generator creates a customized preloader support package with preloader generic
179. sp update settings you must turn off the boot option that is currently turned on before you can turn on a different boot option Sale bsp query settings get all show names Available BSP Settings Table 7 6 Available BSP Settings spl PRELOADER_TGZ String lt SoC EDS installation directory gt host_ tools altera preloader uboot socfpga tar gz This setting specifies the path to archive file containing the preloader source files HPS Preloader User Guide Altera Corporation GJ Send Feedback ug 1137 7 10 Available BSP Settings 2013 05 03 spl CROSS_COMPILE String arm This setting specifies the cross alice compilation tool chain for use eabl spl boot BOOT_FROM_QSPI P Boolean False This setting loads the boot loader image from QSPI spl boot BOOT_FROM_spMmc Boolean True This setting loads the subsequent boot image from Secure Digital MultiMediaCard SD MMC spl boot BOOT_FROM_RAM Boolean False This setting loads the subsequent boot image from RAM spl boot BOOT_ FROM NAND Boolean False This setting loads the subsequent boot image from NAND spl boot QSPI_NEXT_BOOT_IMAGE Hexadec 0x60000 This setting specifies the location imal of the subsequent boot image in QSPI spl boot SDMMC_NEXT_BOOT_IMAGE Hexadec 0x40000 This setting specifies the location imal of the subsequent boot image in SD MMC spl boot NAND_NEXT_BOOT_IMAGE Hexadec 0xC000
180. sssesessesesesessesesesessesesesessesesesesreresess 4 5 Bare Metal Debugging Sample Application Overview eeseesssseceseeceeseeesseeeeesceeeseeeeeseees 4 5 SoH g OU OT e Eei pse aya ene ers ee E E ee ret E eer ea neon eee 4 52 Altera Corporation Importing the Bare Metal Debugging Sample Application eee eeseeeeeeeeeeeeeeeeeeeeens 4 52 Compiling the Bare Metal Debugging Sample Application eeeseeeeseeeeeeeeeeeeeeeeeeees 4 54 Running the Bare Metal Debugging Sample Application eeeeeeeseeeeseteeeeseeeeeeeeeeees 4 54 Getting Started with the Hardware VA DC Ary aiceecsfscsscasserscsensscescacnctecsstessarbeapectonsscteet esta teeetteaeetteesees 4 58 Hardware Library Sample Application Overview cccesssseseesseeeteeeeeeseeeesceeeseeeeseeaeeaeaeeeeees 4 58 Starting the Edipse ID eee tr ene etree erate renee ere eran eer E eer eee E O 4 59 Importing the Hardware Library Sample Application eeeeeeeseeeeeceeeeeeeeeeaceeeeeseeeaees 4 59 Compiling the Hardware Library Sample Application eeeseeseeeeeeseeeeseeteeseeeeseeeeeees 4 62 Running the Hardware Library Sample Application eeeseeeeseeeeseeeceeeeeeeeeeeeeseeeaeees 4 62 Getting Started with Peripheral Register Visibility eee eeseeeescseeseseeeesceeeeeseeeeseeeeecseeecseeeeaeees 4 67 Getting Started with Linux Kernel and Driver Debugging eeeeeeeseeeeseeseeeeeeeeeceeeesseeeteeees 4 72 Linux Kernel and Driver Debugging Prerequisites cess eseeseeeeseeeeseceeeseeeeaceeeeeseeeeeees 4 72
181. t f argv V amp Thread 201 1 stopped on br main 0x76F14FDA Execution stopped at bri 1 In hello c amp File Statics currer 0x000083CC 30 0 int v Globals 0 ED R TekDebun DEAR connected No OS Support Command Submit a hello c amp B E App Co X W Target Error Lo 2 a i f f 28 include lt stdio h gt G En Gb 29 P amp Linked LinuxAppDebug_ Devkit D 30 j t NA S j in 0 sy f wn wr Lt et Aeviw urte sree ee ee w y a gdbserver 5000 Zhome root hello ajs aiea a Sk PERRIN Ds Process home root hello created pid Listening on port 5000 3 g on p i a Debug session has been started connecti R emote debugging from host 137 57 188 a a eee gt Note At this stage all the usual debugging features of DS 5 can be used such as breakpoints view variables registers tracing and threads 9 Click the Continue green button or press F8 to run the application The hello message is printed on the Application Console Getting Started Guides GJ Send Feedback Altera Corporation 1137 4 92 Getting Started with Tracing ee 215 Figure 4 65 Hello Message App Console 2 E Target Console Error Log oc al Ek Bi Y Linked LinuxAppDebug_DevkKit Preparing the debug session a cd home root export LD LIBRARY PATH home root LD LIBRARY PATH gdbserver 5000 home root heLllo Process home root hello created pid 201 Listenin
182. table gt Shared Library gt Static Library gt E Makefile project Show project types and toolchains only if they are supported on the platform Set the Linker Script 1 Go to Project gt Properties Getting Started Guides Altera Corporation GJ Send Feedback ug 1137 4 10 Set the Linker Script mre 2 15 An outline is not available Problems X Tasks EJ Console Properties 0 items Description _ Resource 2 Go to C C Build gt Settings gt GCC Linker gt Image and then click Linker Script Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 2014 12 15 Cc type filter text b Resource Builders 4 C C Build Build Variables Environment Logging Settings Tool Chain Editor C C General Project References Run Debug Settings Settings Set the Linker Script 4 11 an aw a ves mmj E Configuration Tool Settings 4 Build Steps a amp GCC C Compiler Target Preprocessor Symbols Includes Optimization Debugging 3 Warnings Miscellaneous a GCC Assembler Target 3 Symbols Includes Debugging Warnings Miscellaneous a GCC C Linker 3 Image Libraries Objects 3 Warnings GS Miscellaneous Remove unused sections Strip all symbols m 3 Browse to lt SoC EDS installation directory gt host_tools mentor gnu arm
183. tance Figure 4 71 Select USB Blaster II Instance JTAG Chain Configuration device is selected x Hardware Please Select Setup USB Blasterll 1 1 3 3 m Device Scan Chain gt gt SOF Manager Lo hiles soc_ system sot Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 l l 7 2014 12 15 Cross triggering Prerequisites 6 In SignalTap II on the JTAG Chain Configuration gt Device select the FPGA device Figure 4 72 Select FPGA device JTAG Chain Configuration JTAG ready x Devic 1 SOCVHPS 0x4BA00477 2 5CSEBA6 ES SCSEMAG Ox02D020DD KALAN PLA bf hal a pen uy Pr a re re Ema Hardware USB Blasterll 1 1 3 3 4 97 7 In SignalTap II under SOF Manager click the Browse button browse to the file lt SoC EDS Installa tion directory gt examples hardware cv_soc_devkit_ghrd output_files soc_system sof and click Open Figure 4 73 Browse Program Files JTAG Chain Configuration JTAG ready x Hardware USB Blasterll 1 1 3 3 Device 2 5CSEBA6 ES SCSEM SOF Manager i z Browse Program Files 8 In Signal Tap II under SOF Manager click the Program button to program the FPGA Figure 4 74 Program FPGA JTAG Chain Configuration JTAG ready x Scan Chain Hardware USB Blasterll 1 1 3 3 Device 2 5CSEBA6 ES 5CSEM Sel sors a UP see h Program Device 9 After the
184. te to physical SD cards These rights are not required when only working with disk image files Please contact the IT department if you do not have the proper rights on your PC Tool Options The utility is a command line program The table describes all the command line options and the figure shows the he 1p output from the tool Altera Corporation Linux Software Development Tools GJ Send Feedback ug 1137 2014 12 15 Tool Options 12 3 Table 12 1 Command Line Options p filename Required Specifies Preloader file to write b filename Specifies Bootloader file to write a write Required Specifies action to take Only write action is supported Example a write disk_file Required unless d optionis Specifies disk image file or physical disk to used write to A disk image file is a file that contains all the data for a storage volume including the partition table This can be written to a physical disk later with another tool For physical disks in Linux just specify the device file For example dev mmcblko For physical disks in Windows specify the physical drive path such as physicaldrive2 or use the drive letter option d to specify a drive letter The drive letter option is the easiest method in Windows d Optional specify disk drive letter to write to Example d E When using this option the disk_file option cannot be specified h Displays help message and exits version Displays script vers
185. tera Corporation GJ Send Feedback Se ese ug 1137 4 80 Importing the Linux Application Debugging Sample Application 2014 12 15 Figure 4 53 Import Existing Project Select Create new projects from an archive file or directory Select an import source v General Archive File amp Existing Projects into Workspace G File System S Preferences Cancel 3 In the Import Projects dialog box select the Select Archive File option 4 Click Browse then navigate to lt SoC EDS installation directory gt embedded examples software select the file Altera SoCFPGA HelloWorld Linux GNU tar gz and click OK Altera Corporation Getting Started Guides GJ Send Feedback ug 1137 ee bois 4 81 2014 12 15 Importing the Linux Application Debugging Sample Application Figure 4 54 Select Imported File import Projects Select a directory to search for existing Eclipse projects Select root directory Select archive file _ e altera SoCFPGA HelloWorld Linux GNU tar gz v Browse Projects Altera SoCFPGA HelloWorld Linux GNU Altera SoCFPGA HelloWorld Liilf Select All Deselect All J Refresh 5 Working sets C Add project to working sets 5 Click Finish The project is imported The project files are displayed in the Project Explorer panel The following files are part of the project Table 4 3 Project Files hello c Sample application source code Ma
186. tion about the Yocto Eclipse Plugin refer to the Rocketboards website Linux Software Development Tools Altera Corporation GJ Send Feedback Support and Feedback 2014 12 15 ug 1137 o lt Subscribe GJ Send Feedback Altera values your feedback Please contact your Altera TSFAE or submit a service request at myAltera to report software bugs potential enhancements or obtain any additional information Related Information myAltera Account Sign In 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing or
187. tre rent treet ARE ERE 4 104 ARM DS 5 Altera Osan ssspenccenennoraesaccaees pus vstenseaanssseaneewsaesesiupesunenssnnsesstepocens 5 1 aroe Pe lt r re T nT E T ete eer 5 1 Bare metal Project Mandgenmieni srrnenincoprrieiennteie ii ien e a Daz Bare metal Project Management using Makefiles tees eeseeseeeeceseeeeeesceeeecseseeseeeeeeseeeseeees 5 2 GCC Based Bare Metal Project Management eeeeessecessececeseeeeseeeeeesceeeaceeeaseceeeseeeeaeeeses 5 5 ARM Compiler Bare Metal Project Management eeseeeeeseeceseeeesesceesseecescseeaeseeeseeeeeees 5 11 DEDUS OIE ere ee er AEE eS eee eee eee ner re ern 5 22 Accessing Debug Configurations eesssseesseseseseseeeeeesceecsceeescsceasscseeacseeasscseeaeeeeecseeeseeees 5 22 Creatine a New Debug Connor ati i cassie cheeteeceescenecedctnyeeceasstdiaeestaoeesehsctadicetcatniceeetesietteie ee 5 23 Debug Oop she eA iz 6 01m 8 66a c eee ee me ner weet ere ei a orn errr a aa 5 25 PT SU UCN sascha eect ernst ce neg E sqnecestoeesetane ceeds emete ects sostandoncneeesans 5 34 Emb dd d Command NN ssc ps Gases cin a cstcesices ot ces as dea cases entessspaicdanbsawenescaeerss 6 1 HPS Preloader User GONG erasers E A oenasiwsastennnaseses 7 1 HPS On 400 czy O rin E E EEE E T E eer eer 7 1 Prelo der Support Package GeneralOTosseiiierdioenodeenen iei eii e ora Rae eTR a eiia 7 2 Altera Corporation TOC 4 Hardware dindor PES aeren O er er serra et ee eee ee 7 3 Using the Preloader Support Package Generator G
188. tting Started Guides Altera Corporation GJ Send Feedback 1137 4 106 HPS Triggering FPGA Example 2014 12 15 Figure 4 88 Run Analysis Instance Manager Pe 9 u SS Ready Ready to acquire acquire Lr Instance Status Ryn Analysis Memory 102 Small NA Medium NA auto Not running says 10240 bits NA NA 8 SignalTap II will run the analysis and wait for the trigger from HPS Figure 4 89 Acquisition in Progress Instance Status LEs 587 Memory 102 Small NA Medium NA auto Waiting for 587 cells 10240 bits NA NA 9 In Eclipse debugger click the Interrupt button or press F9 This will stop the cores and send the trigger to FPGA 10 SignalTap II will detect the trigger from HPS perform an acquisition and stop This will be indicated by the status changing back to Ready to acquire Related Information e ARM DS 5 Altera Edition on page 5 1 For more information refer to the ARM DS 5 Altera Edition section e Cyclone V Coresight Debug and Trace For more information about Tracing refer to the Coresight Debug and Trace section in volume 3 of the Cycone V Device Handbook e Online ARM DS 5 Documentation The ARM DS 5 Altera Edition reference material can be accessed online on the documentation page of the ARM website www arm com and from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation e Rocket Boards For more information about Linux refer to the Rocketboards we
189. tus_hps help lt option gt to obtain more details about each option For example quartus_hps help 0 Altera Corporation HPS Flash Programmer User Guide GJ Send Feedback ug 1137 2014 12 15 HPS Flash Programmer Command Line Examples 9 5 Example 9 1 Program File to Address 0 of Flash quartus_hps c 1 o P input bin programs the input file input bin into the flash starting at flash address 0 using a cable M Example 9 2 Program First 500 Bytes of File to Flash Decimal quartus_hps c 1 o PV a 1024 s 500 input bin programs the first 500 bytes of the input file input bin into the flash starting at flash address 1024 followed by a verification using a cable M Note Without the prefix 0x for the flash address the tool assumes it is decimal Example 9 3 Program First 500 Bytes of File to Flash Hexadecimal quartus_hps c 1 o PV a 0x400 s 500 input bin programs the first 500 bytes of the input file input bin into the flash starting at flash address 1024 followed by a verification using a cable M Note With the prefix 0x the tool assumes it is hexadecimal Example 9 4 Program File to Flash Repeating Twice at Every 1 MB quartus_hps c 1 o BPV t 2 i 0x100000 input bin programs the input file input bin into the flash using a cable M The operation repeats itself twice at every 1 megabyte MB of the flash address Before the program operation the tool ensures the flash is blank After the progra
190. ware Software Development Flow 1 5 Hardware Software Development Flow The Altera hardware to software handoff utilities allow hardware and software teams to work independ ently and follow their respective familiar design flows Figure 1 1 Altera Hardware to Software Handoff Preloader Device Tree The following handoff files are created when the hardware project is compiled e Handoff folder contains information about how the HPS component is configured including things like which peripherals are enabled the pin MUXing and IOCSR settings and memory parameters e svd file contains descriptions of the HPS registers and of the soft IP registers on FPGA side e sopcinfo file contains a description of the entire system The handoff folder is used by the preloader generator to create the Preloader For more information about the handoff folder refer to the HPS Preloader User Guide The svd file contains the description of the registers of the HPS peripheral registers and registers for soft IP components in the FPGA portion of the SoC This file is used by the ARM DS 5 Debugger to allow these registers to be inspected and modified by the user SOPC Information sopcinfo file containing a description of the entire system is used by the Device Tree Generator to create the Device Tree used by the Linux kernel For more information refer to the Device Tree Generator chapter Note The soft IP register descriptions are n
191. website to convert other file formats such as Executable and Linking Format File elf Hexadecimal Intel Format File hex or S Record File srec to a binary format The output file format is binary 2 The preloader image tool always creates the output image at the beginning of the binary file If the image must be programmed at a specific base address you must supply the address information to the flash programming tool 3 The output file contains only preloader images Other images such as Linux SRAM Object File sof and user data are programmed separately using a flash programming tool or related utilities in the U boot on the target system Related Information Mentor Graphics For more information about the GNU Compiler Collection GCC toolchain refer to the Mentor Graphics website Operation of the Preloader Image Tool The preloader image tool runs on a host machine The tool generates the header and CRC checksum and inserts them into the final preloader image with the preloader program image and preloader exception vector For certain flash memory tools the position of the preloader images must be aligned to a specific block size the preloader image tool generates any padding data that may be required The preloader image tool optionally decodes and validates header information when given a pre generated preloader image Figure 7 4 Basic Operation of the Preloader Image Tool Padding CRC Checksum Preloader P
192. with two dashes in between You will need to use this number to activate your license in DS 5 as shown in the Activating the License section Free Web Edition For the free SoC EDS Web Edition you will be able to use DS 5 perpetually to debug Linux applications over an Ethernet connection Get your ARM license activation code from the SoC Embedded Design Suite download page on the Altera website http dl altera com soceds and then activate your license in DS 5 as shown in the Activating the License section 30 Day Evaluation of Subscription Edition If you want to evaluate the SoC EDS Subscription Edition you can get a 30 Day Evaluation activation code from the SoC Embedded Design Suite download page on 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any infor
193. wlib axf objdump arm altera eabi nm hwlib axf gt hwlib axf map cp f C altera 14 0 embedded ds 5 examples hardware cv_soc_devk arm altera eabi objdump d u boot spl axf gt u boot spl axf objdump D orp alt_address_space o gt le alt_bridge_manager lor alt_cache o arm I gt fa alt_clock_manager 15 57 42 Build Finished took 13s 769ms 4 r RUL i r 4 f am Running the Hardware Library Sample Application The bare metal sample application comes with a pre configured Eclipse Workspace Launcher that allows you to load run and debug the sample application The Workspace Launcher uses the Altera USB Blaster II board connection It uses a debugger script to load and run the Preloader to configure the HPS component and then loads the sample application Altera Corporation Getting Started Guides GJ Send Feedback 1137 se as Running the Hardware Library Sample Application 4 63 To run the sample application perform the following steps 1 In the Eclipse IDE click Run gt Debug Configurations to open the Debug Configurations dialog box 2 In the Connection tab in the Debug Configurations dialog box ensure the selected target is Altera gt Cyclone V gt Bare Metal Debug gt Debug Cortex A9_0 via Altera USB Blaster 3 Under Connections tab click Browse to select the USB Blaster connection Figure 4 40 Debug Configurations Debug Configurations Create manage and run configurations
194. ype ug 1137 2014 12 15 Project name TestProject i V Use default location Location C Workspace TestProject Choose file system default z Project type se Bare metal Executable Empty Project Toolchains Browse Compiler 5 Hello World Project gt amp Bare metal Library gt Executable ARM Compiler 6 gt amp Shared Library Altera Baremetal GCC DS 5 GCC b amp Static Library gt Makefile project V Show project types and toolchains only if they are supported on the platform b Bare metal library Select Bare metal Library gt Empty Project and click Finish Altera Corporation ARM DS 5 Altera Edition GJ Send Feedback ug 1137 201 4 12 15 Build Settings 3 9 Figure 5 7 Bare metal Library Project Type C Project Create C project of selected type Project name TestProject Use default location Location C Workspace TestProject Choose file system default hi Project type gt amp Bare metal Executable 4 Bare metal Library Empty Project b E Executable gt Shared Library b Static Library gt G Makefile project Build Settings Once the project is created the project properties can be accessed by going to Project gt Properties ARM DS 5 Altera Edition Altera Corporation GJ Send Feedback 5 10 Build Settings Figure 5 8 Project Properties ey Problems X Tasks EJ Console Properties 0 items Descri
195. zard 3 Accept the license agreement and click Next 4 Accept the default installation directory or browse to another installation directory and click Next Note If you have previously installed the Quartus II software accept the default SoC EDS installation directory to allow the Quartus II software and the SoC EDS Tool Suite to operate together 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYAN 101 Innovation Drive San Jose CA 95134 ug 1137 2 2

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