STD 7000 7604 TTL I/O Card USER`S MANUAL
Contents
1. a x PE SY Ja gt ox 0 5 ie Y y MODIFIER MNEMONIC INSTR LABEL Clear B INSTR HEXADECIMAL LIN ADR 8 1 6 5 SYSREGETR 141532 BUS BUFFERS Qn DS 17 04 03 Di EE ef E dddd didi DO amp GC 444449 GERE ARR DE A x la 77 oo tk 211 Iz ur LILLE 4444444 E 1 741532 1 Ley 25 29 2 a GEBEN DEE APA ARE SUNT ARE PCO PCI y 4 15 8 10 0 7 25 e 7 10 6 p 10 5 ES mit 5 los A 4 0 3 mt 3 0 2 2 N HE f UO 0 yt No 851 354 ideas 87 6 N m 7 re PAQ 1 5 LS m 5 1 4 P 1 3 LS 3 1 2 IN ral 2 14 R 1101 0 Mo SX SELECTS 10F 8 ADDRESS BLOCKS 32 PORTS PER BLOCK 1 0 UF 0 1 UF GND 75 1 ALL RESISTOR VALUES ARE 4 7K 1 NOTES UNLESS OTHERWISE SPECIFIED ue 1 6 5 9 i 10401 N C 5Y L 741532 A Ci c2 7 i SY SELECTS 1 OF 4 ADDRESS BLOCKS f PORTS PER BLOCK 810 2 7 9 2 6 10 e 15 H 5 24 12 23 13 3 2 2 4 M 15 yo 2 0 8 10 3 7 9 7 02 10 e 3 5 ti 5 3 4 i 3 3 3 2 14 IS 1 1 0 3 0 fo ASSEMBLY NO 04484 PARTS LIST NO 12. 0 U 7604 ASSEMBLY FIGURE 5 4 ASSY 104484 PORT BIT 1 2 3 4 5 6 7 8 N O OUTPUT DRIVE INPUT LOADING MNEMONIC VOLTS us 2 GROUND 41 51 enoj eroun Ew cop me 07 L3 im Ee po s 99 E N KN E C E BSEC 01 Ls 1 2 s L 38 E e o 01 45 lim eel r Hong 5 Toor 2 L J ja sars Tol suse fas sus neo rak ple 0 Perese Tall svsneser cna OC E wl elmu cs moen E E Ax E 5 Tov Designates Active Low Level Logic Edge Connector Pin List FIGURE 6 e Address Data and Control Busses meet all STD BUS general electrical specifications except AQ A1 and A2 which are 2 LSTTL loads each A 7604 OPERATING SUBROUTINE MODULES This section provides flow diagrams and subroutines to operate your 7604 card These may be used intact or used as models to construct subroutines for a specific application The subroutines are written in 8080 family assembly code and will execute on 8080 8085 and Z80 processors The memory addresses selected are compatible with Pro Log s 7801 8085A and 7803 280 processor cards The 7604 port addresses used are the ad
3. PILJPRO LOG STD 7000 7604 TTL I O Card USER S MANUAL 7604 TTL I O Card USER S MANUAL CORPORATION 9 81 7604 TTL 1 0 CARD USER S MANUAL TABLE OF CONTENTS SECTION SECTION 2 SECTION 3 SECTION 4 SECTION 5 SECTION 6 SECTION 7 SECTION 8 SECTION 9 Product Overview Block Diagram Functional Description General Purpose Interface Mapping Address Decoder Operation Changing the 7604 s Port Address 7604 Card Environmental Specification Electrical Specifications Mechanica 7604 Operating Subroutine Modules Maintenance 0000 7604 TTL I O CARD TTL INPUT OUTPUT CARD This card provides 8 ports of which any numbercan be input or output ports or output ports with readback 64 I O lines total The ports are accessed at 16 pin DIP sockets on the card The output lines are TTL compatible with the ability to drive 16 low power Schottky TTL Loads each 4 TTL loads A reset line is available to clear all Output ports simultaneously The input lines are TTL compatible with an input rating of 4 low power Schottky loads The ports are configured as input or output ports simply by removing the unused 1 associated with that port If the input buffer is retained output port data may be read back into the Processor The 7604 decodes eight address lines with provi sions for expansion and memory map
4. SAVE BEC LOAD B WITH OLD DATA EXCLUSIVE OR OLD DATA WITH NEW DATE STORE BITS HAT CHANGED OLD DATA WITH CHANGES STORE BITS THAT ENT TO ZERO ANDU OLD DATA WITH CHANGES STORE BITS THAT WENT TO ONE RESTORE 5 C RETURN SET BITS INPUT PRESENT STATUS OR IN NEW BITS OUTPUT NEW STATUS RETURN CLEAR BITS INPUT PRESENT STATUS MASK OFF UNWANTED BITS OUTPUT NEW STATUS RETURN gt PROGRAM ASSEMBLY FORM i PRO LOG CORPORATION check Bits 1 2ErQ 1010000 89554 ONE 010 e 011030 CHANGES DATE Ke 019 ww 1010 CHANGES OOOO LI 010 01011010 CHANGE 8 Q oJ KI _ FR 2 I 4 46 x amp 2 no a E A gt 2 5 u a p L 4 2 S 2 RA 1 S 3 ES gt t 144446 iss Q 4 a s Y si 4 8 3 4 gt a whee 3 Hi BE Ri res BA ka ma mma f m y qa 23813 5 INSTR O ad lt a gt n REE 5 SER zli z p 7 HEXADECIMAL INSTR PAGE 100001 2 7 PROGRAM ASSEMBLY FORM PRO LOG CORPORATION TITLE 7604 DATE COMMENTS UAM i a 4 i e Bils in P dut PY IN 4 3 a a e 4 fi e Ly f LI
5. NOME RC ONE IA CUNG 2 MNEM PARAMETER USER WORST CASE ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS For Input Port PARAMETER MIN UNIT High level input voltage TTT iysterests 7 for Input current each port line represents 4 LSTTL loads For Output Port 1 LSTTL load 0 4mA STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS SUPPLY CURRENT MA A E BUS INPUT LOAD See Figure b STD BUS OUTPUT DRIVE Input characteristics with output chip removed See Figure 6 Output characteristics with input chip installed 8mA LOOMA u Vec 4 5V 101 gt gt gt VCC 4 5V Each output can drive 16 LSTTL A 9 MECHANICAL Meets all STD BUS general mechanical specifications May require one additional card slot width for ribbon cable access to ports connector dependent Connectors use low profile l6 pin DIP plugs with heavy duty pins T and B Ansley Catalog No 609 165 or equivalent 699 Aa id 9 us 1 78524 10 Y X Uu QJ U U U U 2000058 RIO HK uU 5 WT ENS WY WY WP 20 u U 765273 HEE SUN ao A BEE a 0000000 00000000 8 00000 Is ue 7415244 3000058 UK OW WY 3 WWF TU WP 745273 o 9 o 9 0 O O O O O O o e 0080000 Cy al Q
6. 04485 8 1 0 5 7 9 6 6 8 6 5 4 6 3 L 2 0 8 6 1 6 i o b 0 4 1 7 7 2 vis 8 din 1 5 ym 7 7 1 4 1574 a 1 3 U22 SE PE 8 Four 7 7 1 4 i Fi VO 7 0 5 A PRO LOG CORPORATION 1888 COC AU en Bee SCHEMATIC 7604 SETZE UNIVERSAL TIL I O CARD crom vam TE Kd C3 i 3 A 20000000 00000000 sx lt lt 9 SS A otf DE TAL A amp REF DESIGNATIONS ARE FOR LOCATING PURPOSES ONLY AND MAY NOT APPEAR ON ACTUAL PART AN TOENTIEY WITH ASSY REV LETTER USING RUBBER STAMP OENDTES PINNO 1 OF IC S 3 BOARD TO CONFORM WITH ASSY PROCEDURES ASIDDA N TO CONFIGURE AS INPUT PORTS REMOVE ICs PER TABLE 1 0 WHEN USED AS AN OUTPUT 74157445 BE LEFT IN AN MAPED PORT NOTES UNI ESS OTHERWISE SPECIFIED 8 7 INPUT A PORTS BOMS 20 IB REA o o o 0 o 9 O O Ra ejo 9 o o 9 e o 9 o 9 0_8 o 9 9 9 9 ef 5 0 0 o 6 Oo 9 0 0 6 d 01 PORTS Ule U23 A Ll ASSY 14444 19 it REQ AOD OFM 25 ADIY D Noles t1 ADDED PAF f IR GINA PEN iC TABLE T REMOVE NITE UT LANH 743775 Ui ge B u Ta 7k NETWORK RI R13 8 7 ASSEMBLY 7004 UNIVERSAL TTL I O CARD SCHEMATIC NO 104483
7. PARTS LIST NO 104985 DJ mis 2 1 GO USER S MANUAL Bi PR0 t0G 2411 Garden Road Monterey California 93940 O Telephone 408 372 4593 TWX 910 360 7082 106665B 600 9 81
8. dress jumper selections made when the 7604 is shipped To use these subroutines in systems other than those described above the memory and or 1 0 port addresses may require change for compatibility The flow diagrams presented can be easily translated into the assembly code used by any microprocessor since they show the steps required to achieve 7604 operation without reference to a particular microprocessor The check bits subroutine will compare the present input port status with the port status from the last time that the port was read To use the routine the HL pointer must point to a place in memory where port status is stored Also the port must be read into the accumulator before calling the routine Upon return from the routine the location that the HL pointer was previously set will contain new port status Plus the next four locations will contain change status Uses Registers A H and L M XX New Data location HL was set to Old Data M2 XX Changes XX Bits to era peal XX Bits to One Memory after Return The set bit routine can set a bit or bits on an output port To use the routine load the accumulator with the bits that should be changed Input chip must be installed The clear bit routine can clear a bit or bits on an output port To use the routine load the accumulator with the bits that should be changed Input chip must be installed CHECK BITS
9. ping An on card jumper system allows users to establish the eight consecutive port addresses occupied by the 7604 FEATURES e 8 Ports configurable as input or output or output with readback e User selectable port address 256 port field Outputs Drive 16 low power Schottky TTL loads Provision for expansion and memory mapping All IC s socketed Single 5V operation PORT f CONNECTORS 22222 CARD SELECT OECODEN DECODER QUTPUT PORT SELECT DECODER OUTPUT PORTS SHADING IMDI ATES SOCKETS INOICATES ACTIVE LOW LOGIC F1GURE 1 2 FUNCTIONAL The 7604 is shipped fully populated The card is customized to A input and B output ports such that B 8 ports by removing the unused input buffer or output port latch according to the following table OUTPUT PORTS INPUT PORTS PORT NO IC NUMBER IC NUMBER Leaving the input buffer in at output ports allows the Processor to read back the output port data to check for noise alteration or to use the output port as a data register The 7604 provides 64 alternating data and ground lines These signal lines can be up to 10 feet 3 05m long with proper electrical considerations When writing to an eight bit output port the data bus data is latched in the output port The output data will remain latched in that state until it is written to with new data or the SYSRESET signal clears the port When reading from an 8 bit input port the of
10. t each address The RD and WR inputs control the input gating and output latch functions Le ADDRESS DECODER OPERATION Refer to the schematic Document 104483 The 7605 uses four cascaded 74LS42 decoders U3 U4 U5 and U6 to decode address lines 0 7 These decoders are enabled only when IORQ and IOEXP are active Address lines AQ Al A2 and the WR signal are used to gate the select strobes from U6 that control the output ports Address lines AO Al A2 and the RD signal are used to gate the select strobes from U5 that control the input ports CHANGING THE 7604 s PORT ADDRESS Refer to the Assembly diagram Document 104484 Locate decoders U3 and U4 74LS42 adjacent to the STD BUS edge connector Each decoder device has a dual row of pads which form decoder output select matrices Make one and only one connection to each of the matrices adjacent to U3 and U4 The decoder jumper pads numbered as shown in Figure 3 are adjacent to the decoder chips on the 7604 Also shown are the jumpers at and YO which produce hexadecimal port addresses 00 01 02 thru 07 the selections made when the card is shipped Sooo sy Card Address Selection FIGURE 3 The 1 0 address mapping and jumper selection table for eight addresses per card shows where to place jumper straps to obtain any eight sequential port addresses in the hexadecimal range 00 FF Using the lower of the 2 digit hexadecimal addresses desired find
11. the most significant hexadecimal address digit along the vertical axis and the least significant hex digit on the horizontal axis For example port addresses 00 01 02 thru 07 are obtained by connecting jumpers at XO and YO The only restriction that applies in address selection for the 7604 is that the lower of the eight port addresses 00 as shipped must occur only at every eighth possible address for example the sequence 01 02 03 thru 08 is not allowed by the decoder The pad matrices adjacent to U3 and U4 are on 0 10 inch 0 25cm centers The jumper wires may be conveniently replaced by wirewrap post if frequent address selection changes are anticipated MOST LEAST SIGNIFICANT HEX ADORESS SIGNIFICANT EAST SIGNIFICANT HEX ADORESS en hex ADDRESS 0 2131415 417 s e jajsjcjoje r A A rl R CIA METIA LEE ETE Ea oo ee a We BARRER AE a cee Tl Oe UNE waw JE II EEE EEE TTT HARTA gt gt 4 I O Address Mapping And Jumper Selection Tables For 8 Addresses Per Card FIGURE 4 5 7604 CARD ENVIRONMENTAL SPECIFICATIONS RECOMMENDED OPERATING LIMITS ABSOLUTE NON OPERATING LIMITS PARAMETER mm me max min mx ITS o Humidity 5 95 0 95 Non condensing 6 ELECTRICAL SPECIFICATIONS 7604 GENERAL PURPOSE TTL 1 0 CARD ELECTRICAL TEST SPECIFICATION RECOMMENDED OPERATING LIMITS ABSOLUTE NON OPERATING LIMITS Bee i3
12. the port lines at the time of the read is transferred to the data bus RESET The SYSRESET line clears all eight output ports to zero simultaneous y system power up the SYSRESET signal clears the output ports GENERAL PURPOSE INTERFACE state The 7604 is useful as a general purpose TTL interface card If flat cable or twisted pair discrete wire cable assemblies are used the ground signal ground of the 1 0 connectors minimizes crosstalk between inter system signal lines in electrically noisy environments DATA BUS 5V BUFFER OUTPUT STROBE lt e RESET FROM PORT SELECT DECODERS E KO IMPOT STROBE FROM OTHER CIRCUITS 7415244 TYPICAL 1 0 CIRCUIT FIGURE 2 O KE MA TO am Lb WILKI AA ATT CBM LAL IIA ART eee I ee ee EL ED ZU A el etus Ett Te SP TRON SEM SARL TON Lun ATE ETE GA L L AL LLLI A 1524 3 Card Address Mapping The 7604 Card is selected by a decoded combination of address lines A3 A7 The user chooses the card address combination by connecting one jumper wire each from SX and SY to pad matrices adjacent to U3 and U4 see diagram The 7604 is shipped mapped at Hex Port Address 00 To map the 7604 anywhere in the hexadecimal address range 00 to FF change the decoder outputs connected to SX and SY Port Addresses Address lines AO A1 and A2 select one of eight Port addresses One input port and one output port reside a
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