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MN101LR05D/04D/03D/02D LSI User`s Manual

1. Setup Function Register LCCTR5 TM5MD TMIOSEL5 Bitname SEGSL41 TM5OEN TM5CK1 0 TM5IOSEL 1 SEG41 1 Other than 11 0 TMBIO output 0 11 0 TMBIO input Other than 11 P21 Table 7 6 4 P22 Function Selection Setup Function Register LCCTRS5 SC2MD1 SC23SEL Bitname SEGSL40 SC2SBIS SC2IOM SC2SELO 1 SEG40 5 1 0 1 SBI2B 0 0 22 Table 7 6 5 P23 Function Selection Setup Function Register LCCTR5 SC2MD1 SC23SEL Bitname SEGSL39 SC2SBOS SC2SBIS SC2IOM SC2SEL1 1 SEG39 11 72 2 1 SBO2B 0 1 1 SDA2B 0 0 0 P23 1 When serial data is output set the P2DIR P2DIR3 to 1 2 When serial data is input and output set the bit to 1 Table 7 6 6 P24 Function Selection Setup Function Register LCCTR5 SC2MD1 SC23SEL Bit name SEGSL38 SC2SBTS SC2SEL2 1 SEG38 SBT2B SCL2B 0 P24 1 When the LSI is the master of Clock synchronous communication or communicates IIC bus set the P2DIR P2DIR4 to 1 Chapter 7 I O Port Port 2 VII 41 Chapter 7 Port VII 42 Port 2 Table 7 6 7 P25 Function Selection Setup Function Register LCCTR5 SC2MD2 SC23SEL Bit name SEGSL37 SC2SBCSEN SC2SEL3 1 SEG37 1 1 SBCS2B 0 P25 1 Whe
2. 7 12 2 4 Periodic Interrupt Control eren XII 10 12 2 5 Clock XIL11 12 20 RTE Status Register eoo RC Ret ett 14 12 3 REC Operation e en eee etn tee 15 12 3 1 Clock Data Reading 16 12 3 2 Setup Example etes eee hq ote eee cett ens 17 Chapter 13 Serial Interfac 1 VS OVENI EW 2 A as GS E EAS XIII 3 13 12 Block Di gratn ivre ce Dee Petit XIII 5 13 2 Control Registers rro eso e tee re e PE Pene ee epe heit XIII 7 13 2 L Registers sioe Sonet de taa e Spes XIII 7 13 2 2 Input Output Pin Control Register eese nennen XIII 9 13 23 Receive Data osi tie te ip pleine e Heredes XIII 10 13 2 4 Transmit Data Buffer a n D S ener XIII 10 13 25 aec E pitur t XIII 11 13 2 6 Status Register onset sete eene DID OBIECIT XIII 19 13 2 7 Address Setting Re isters esteso ettet e tette eee XIII 22 13 2 8 BRTM Operation Mode Setting Register sse XIII 22 13 2 9 BRTM Operation Enable Register eene XIII 23 13 2 I0 BRTM Clock Select Register entente bte tre ce eee ee XIII 24 13 2 11 BR
3. Characteristics _ 40 to 485 C Limits Parameter Symbol Condition Unit MIN TYP MAX Reset 1 supply Vpp3 With auto reset VnsTL 3 6 2 Auto reset voltage VnsrH Low gt High 1 10 1 23 1 35 V E3 detection level VnsrL Vppao High gt Low 1 10 1 18 1 30 E4 z 5 10 Vims Power supply Detection E5 Detection error 2 0 2 0 1 05 1 15 1 25 1 10 1 20 1 30 1 15 1 25 1 35 1 20 1 30 1 40 1 25 1 35 1 45 1 30 1 40 1 50 1 40 1 50 1 60 1 50 1 60 1 70 1 60 1 70 1 80 1 70 1 80 1 90 Detection Vivi 1 80 1 90 2 00 V 1 90 2 00 2 10 2 00 2 10 2 20 2 10 2 20 2 30 2 20 2 30 2 40 2 30 2 40 2 50 2 40 2 50 2 60 2 50 2 60 2 70 2 60 2 70 2 80 2 70 2 80 2 90 2 80 2 90 3 00 Electrical Characteristics 29 Chapter 1 Overview 1 4 6 Program Condition B uB Vppao 1 8 V to 3 6 V Vas 0 V F ReRAM Program Condition Ta 40 C to 85 Limits Parameter Symbol Condition Unit MIN TYP MAX Supply voltage V _ Fl for programming DDEW 1 8 3 6 V Guaranteed number of NUM Program area 1000 T rewriting 14 Data area 100000 Data hold time THOLD 10 ew year 14 cycle from elimination to writing is counted as the number of rewriting Even if the same block is rewritte
4. Refer to Table 1 2 3 for LCD control pins 1 10 Comparison of Product Specification Chapter 1 Overview 1 3 Pin Description 1 3 1 Pin Configuration m Q 25 e gt gt Odmmane 24007709 y x x l lu lt gt lt EzzzEEERC S lt lt lt 550080585 hi LU h m en m mn 9 0 0 0 0000 OO ZZZ222220000 oo JlZiw QOOO OO O OO uui u gt gt 9 000 1 60 Q 31 o c lt OOOO gt gt gt gt a 0 h n gt n CO LO f N O O O LO st GN YT r P P cO CO CO CO CO vss 1 P63 SEG8 IRQ3B XI 2 P62 SEG9 IRQ2B 3 P61 SEG10 IRQ1B NATRON 4 P60 SEG11 IRQ0B P27 NRST 5 P57 SEG12 TM8IOA KEY3B CLKOUTB IRQ2A OSC1 P80 6 P56 SEG13 TM3IOA KEY2B IRQ3A OSC2 P81 7 P55 SEG14 TM1IOA KEY1B TM9IOC P00 8 P54 SEG15 SBCS3B KEY0B TM4IOB P01 9 MN101LR05D P53 SEG16 SBT3B SCL3B TM8IOC TM2IOB BUZB P02 80 pin P52 SEG17 SBO3B SDA3B TM7IOC TM0IOB NBUZB P03 P51 SEG18 SBI3B TM7IOA SDA3A P04 Top View P50 SEG19 SBCS1B CLKOUTA TM2IOA TMOIOA SCL3A P05 P47 SEG20 SBT1B TM8IOB SBI3A P06 P46 SEG21 SBO1B TXD1B TM9IOA SBCS3A P07 P45 SEG22 SBIHB RXD1B IRQOA ANO P1O P44 SEG23 SBCS2A I
5. 8 abs8 abs12 An ADD 8 Dm MOVW 8 DWm MOVW 8 JSR d12 label JSR d16 label MOV 8 abs8 abs12 PUSH OR 8 Dm AND 8 Dm When the extension code is b 0010 When the extension code is b 0011 MOV abs12 Dm MOV abs8 D MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am io8 D MOV d4 SP Dm MOV d8 An Dm MOV 108 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn d7 d7 d7 d7 BCS d7 BLT d7 BLE d7 BEQ d4 BNE d4 MOVW DWn HA MOVW BGEd11 BRA 911 11 411 BCS 911 BLTd11 BLEd11 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp 8 Dm MOVW abs8 Am MOVW abs8 Dwm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVWDWn abs8 CBNE 8 Dm d7 CMPW 16 MOVW 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am BRA d4 MOVW DWn Am 04 5 MOVW DWn d4 SP PUSH Dn ADDW 8 SP ADDW 4 SP JSRV Extension code b 0010 2nd nibble 3rd nibble mm oo MOVW CMPW MOVW SPAm 5 BTST 8 Dm JSR A0 UMP A1 JSR A1 PSW Dm REP 43 BGT d7 d7 BLS d7 BNC 47 BNS d7 BVC d7 BVS d7 NOT Dn ROR Dn BGTd11 BHId11 BLSd11 d11 BNSd11 BVCd11 5 411 ASR
6. 8 8 2 3 Timer Registers dede de tct ua s s a 9 lt Contents 4 gt 8 3 S DIt TIMET a apuman GER EE 15 8 3 1 15 8 32 Setup Example obediens eee d ueber tette VIII 19 8 4 8 bit Event Counts x ee dig beet dE VIII 20 8 4 1 Operation eere eO RI a esi DER Pe VIII 20 8 4 2 8 bit Event Count Setup Example a a eere enne VIII 22 8 5 8 bit Timer P lse OUtpUt cem crt secat eise dentes eed VIII 23 8 5 Operation 2 35 erede ERU VIII 23 8 522 Setup Example uec etse VIII 24 8 6 a bit PWM Output iet ne tete crei ere e et tree beo ge dd VIII 25 8 6 1 Operation Timer 0 Timer 2 and Timer 4 erre VIII 25 8 622 Setup Example aden donee VIII 27 8 6 3 PWM Output With Additional Pulse Timer 0 Timer 2 Timer 4 VIII 28 8 7 Simple Pulse Width Measurement a VIII 29 8 7 1 Operation Timer 0 Timer 2 and Timer 4 seen nre VIII 29 8 7 2 Set p Example oit ob RT RR Rente aec eese VIII 30 8 8 8 bit Timer Cascade Connection ides eec dit cett p d epe e ee ete VIII 31 8 8 T Operation ian Ron anite Abe eee I tinea
7. A D Converter ADC 16 1 2 Block Diagram m ADC Block Diagram 1 0 ANCTR0 ANCTR2 ANCHS0 aaah 51 gt 52 ANLADE 4 IRQO timer 7 ANCKO 2 interrupt control EVENT ANCK2 ANSTSELO Y ANSHO ANSTSELI A D conversion ADIRQ ANSHI control 7 7 7 ANBUF1 ANBUFO ANBUF10 5 we ANBUF11 VREFP SJ ANBUF12 ANBUF13 ANBUF14 4 ANBUF15 ANBUF05 ANBUF16 ANBUF06 ANBUF17 _ ANBUE07 ANO f 7 AN1 conversion AN2 Y data upper 8 bits AN3 Sample 12 bits A D MUX and hold comparator AN5 A D conversion data lower 4 bits AN6 AN7 Vss SYSCLK 2 Y SYSCLK 3 M l gt 1 2 N SYSCLK 4 I SYSCLK 6 1 6 gt MUX SYSCLK 8 MUX m SYSCLK 12 SYSCLK 16 gt SCLK Figure 16 1 1 ADC Diagram Overview XVI 3 Chapter 16 A D Converter ADC 16 2 Control Registers The ADC control registers consists of the control registers ANCTRn and the data storage buffers ANBUFn 16 2 1 Registers Table 16 2 1 shows the registers that control the ADC Table 16 2 1 ADC Control Registers Address Register name ANCTRO OxOSF60 A D control register 0 1 0x03F61 A D control register 1 ANCTR2 0x03F62 A D control register 2 ANBUF0 0x03F64 ADC data storage buffer 0 ANBUF1 0x03F65 ADC data storage buffer 1 ANEN0 0x03F5C Analog in
8. This LSI has a built in booster circuit BSTVOL for LCD drive which generates a voltage of 2 or 3 times the LCD reference voltage 2or3 Times Boosting When BSTVOL generates 2 or 3 times input the LCD reference voltage Vy from VLC3 pin When REFVOL is used the above voltage input is not needed Three times the reference voltage Vy is output from pin and two times the reference voltage Vi is output from the VLC2 pin Insert a capacitor at VLC1 VSS VLC2 VSS and C1 C2 pins 2 Times Boosting When BSTVOL generates 2 times input the LCD reference voltage Vy from the short circuit of VLC2 and VLC3 pins 2 times the reference voltage Vy c3 is output from VLCI pin Insert a capacitor at VLC1 VSS and C1 C2 pins In 2 or 3 times boosting the condition of 1 3 x lt Vi lt 1 2 V must be ensured 1 In 2 times boosting the condition of 1 2 x lt Vice Vica lt 1 8 V must be ensured 17 3 3 Reference Voltage Circuit REFVOL This LSI has a built in reference voltage circuit REFVOL which can be used with BSTVOL to generate LCD drive voltage The output voltage of REFVOL is independent of VDD30 and is generated from 0 9 V to 1 8 V REFVOL outputs the reference voltage from VLC3 and BSTVOL outputs the boost voltage from VLCI VLC2 When using the BSTVOL and the REFVOL connect a capacito
9. Setup Function Register LCCTR3 SC1MD1 SC01SEL Bitname SEGSL21 SC1SBOS SC1SBIS SC1IOM SC1SEL1 1 x SEG21 101 72 2 1 SBO1B 0 1 1 1 TXD1B 0 0 P46 1 When serial data is output set the P4DIR P4DIR6 to 1 2 When serial data is input and output set the bit to 1 Table 7 8 9 P47 Function Selection Setup Function Register LCCTR3 SC1MD1 SCO1SEL Bit name SEGSL20 SC1SBTS SC1SEL2 1 SEG20 1 1 1 SBT1B 1 0 47 1 When the LSI is the master of Clock synchronous communication set the P4DIR P4DIR7 to 1 Port 4 Chapter 7 Port 7 9 Port5 ncr s lt sAEET WYa sa The following table shows the special functions of Port 5 Table 7 9 1 Port 5 pin Special function P50 SEG19 SBCS1B P51 SEG18 SBI3B P52 SEG17 SBO3B SDA3B P53 SEG16 SBT3B SCL3B P54 SEG15 KEY0B SBCS3B E P55 SEG14 KEY1B TM1IOA P56 SEG13 KEY2B 57 SEG12 KEY3B TM8IOA CLKOUTB The assignment and selection of SEGn differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 9 1 Setup of Port 5 u nnf Table 7 9 2 P50 Function Selection Setup Function Register LCCTR2 SC1MD3 SCO1SEL Bit SEGSL19 SC1SBCSEN SC1SEL3 1 SEG19
10. EN6 Figure 3 2 1 Block diagram of Group 0 interrupt III 30 Control Registers Group Interrupt 0 LVD interrupt PERHDT DTO edge detection A D interrupt I x PERHDT DT1 edge detection DMA interrupt I PERHDT DT2 edge detection VI PERHDT DT3 H edge detection DMA Addreg interrupt IP 4 DMA Error interrupt IP YO OU UY edge detection When the interrupt factor and set clear by software ocurred at the same time set clear by software is given priority PERI1EN 0 p EN1 EN2 EN3 EN4 4 Figure 3 2 2 Block diagram of Group 1 interrupt Chapter 3 Interrupts Group Interrupt 1 Control Registers III 31 Chapter 3 Interrupts 3 3 External Interrupts The LSI has 8 external interrupts shown in Table 3 3 1 Table 3 3 1 External Interrupt Functions Rising or Falling Both edge edge triggered interrupt triggered interrupt External Interrupt Pin name Noise filter Key interrupt III 32 External Interrupts Chapter 3 Interrupts 3 3 1 External Interrupt Control Registers sn n Table 3 3 2 shows the external interr
11. 1 8 Start the TM6 operation TM6BEN 0x03F7C bp0 TM6EN 1 1 Set the TM6CLRS bit of the timer 6 mode register TM6MD to 0 to enable the initialization of the timer 6 binary counter TM6BC 2 Set the PERIOEN1 bit of the PERIOEN register to 0 to disable the interrupt 3 Set the TM6CK3 1 bits of the TM6MD register to select the clock source In this case SYSCLK is selected 4 Set the interrupt generation cycle to the timer 6 compare register TM6OC Atthis time is initialized to 0x00 5 Set the TM6CLRS bit of the TM6MD register to 1 to enable the interrupt request generation 6 the PERIOLV1 0 bits of the peripheral function group 0 interrupt level control register PERIOICR to select the interrupt level Clear the corresponding interrupt request bit of PERIODT register if it may have already been set 3 1 5 Set up procedure for Interrupt control register for peripheral function group 7 Set the PERIOEN1 bit of the PERIOEN register 1 to enable the interrupt 8 Set the 6 bit of the TM6BEN register to 1 to start the timer 6 When TM60C is set TM6BC is initialized to 0x00 When TM6BC value matches the value specified in the timer 6 interrupt request is set at the next count clock and TM6BC is cleared to 0x00 to restart counting 8 bit Free running Timer X 11 Chapter 10 General Purpose Time Base Free
12. Bit name Description Always read as 0 Alarm 0 setting 0 AM ALOIRQH6 1 This bit must be set in 12 hour clock mode In 24 hour clock mode this bit must be set to 0 Alarm 0 Hour setting lt 24 hour clock mode gt Set a value within the range of 00 to 23 using the BCD format lt ln 12 hour clock gt Set a value within the range of 00 to 11 using the BCD format The value which doesn t exist must not be set AL0IRQH5 0 m Alarm 0 Day of Week Setting Register ALOIRQW 0x03ED6 Bit name At reset 0 0 0 0 0 0 Access bp Bit name Description Always read as 0 Alarm 0 Day of the week setting 000 Sunday 001 Monday 010 Tuesday AL0IRQW2 0 011 Wednesday 100 Thursday 101 Friday 110 Saturday 111 Setting Prohibited AL0IRQW RTCALOIRQ ALOIRQMI ALOIRQH and AL0IRQW must be set when RTCALOIRQ ALOIRQSET is 0 lt Alarm 0 interrupt is not guaranteed if the prohibited value is set in ALOIRQMI ALOIRQH and XII 6 Control Registers Chapter 12 Real Time Clock RTC 12 2 3 Alarm 1 Interrupt Registers W Alarm 1 Interrupt Control Register RTCAL1IRQ 0x03ED7 Bit name At reset Access Bit name Description Always read as 0 AL1IRQSET Alarm 1 interrupt control 0 Disabled 1 Enabled Always read as 0
13. SDAn SCLn SCnTIRQ IIC3STRT IIC3ADD_ACC IIC3BUSBSY i A Set data to TXBUFn Set data to TXBUFn Figure 13 5 9 Slave Transmission Timing 1 Detect start condition 2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive ACK bit 7 Set data to TXBUFn in interrupt handler 8 Transmit data XIII 64 IIC Communication Chapter 13 Serial Interface m Slave Transmission Timing NACK Reception 2 0 0 S 6 7 p er 8 bits transmission r ST O MsQAM SDAn SCLn SCnTIRQ IICSSTRT ACC IIC3BUSBSY a A a Set data to TXBUFn Figure 13 5 10 Slave Transmission Timing NACK Reception 1 Detect start condition 2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive NACK bit 7 Release SDAn and SCLn IIC Communication XIII 65 Chapter 13 Serial Interface Slave Reception Timing Stop Condition Detection 0 2 G 9 5 6 0 1 4 2 data lt lt lt 8 bit reception i reception E tor ot ey m SDAn Nr go SCLn SCnTIRQ IICSSTRT IICSADD ACC IICSBUSBSY Hd Set dummy data to TXBUFn Set dummy data to TXBUFn Fi
14. Access m mme Output data 7 0 P4OUT7 0 0 Output Low Vss level 1 Output High Vppgo level Port 5 Output Register PSOUT 0x03F15 Bit name At reset Access e mmm Output data 7 0 P5OUT7 0 0 Output Low 1 Output High Vpp3o level VII 6 Control Registers Chapter 7 I O Port Port 6 Output Register 6 0x03F16 Bit name At reset Access x m sme Output data 7 0 P6OUT7 0 0 Output Low Vss level 1 Output High Vppso level Port 7 Output Register PZOUT 0 03 17 Bit name At reset Access m mmm Output data 7 0 P7OUT7 0 0 Output Low Vss level 1 Output High Vppso level Port 8 Output Register 0 03 18 Bit name At reset Access Bit name Description Always read as 0 Output data P80UT5 0 0 Output Low Vss level 1 Output High Vppso level Control Registers VII 7 Chapter 7 I O Port 7 2 2 Port n Input Registers PnIN is the register to read the input data from when I O is used as a general purpose port Port 0 Input Register POIN 0x03F20 Bit name At reset Access m e Input data 7 0 POIN7 0 0 Input Low Vss level 1 Input High Vppsao level
15. Indino 1891 indino OISN1L 1891 1ndino 00 g 19junoo awn 00 oui Xm 4ejunoo 2000 X 1000 X 0000 1991 2 181siD84 Jaedwioo eum 1 saedwoo eum z 1e1siDo1 daedwog y y WA y yooja Figure 9 11 2 1 One shot Pulse Output Timing with dead time IX 61 IGBT Output with Dead Time Chapter 9 16 bit Timer 9 11 2 Setup Example e oro W Setup Example of IGBT Output with Dead Time Timer 7 Here is an example that using Timer 7 with HCLK 8 MHz as a clock source while the external inter rupt 0 input signal is generated the IGBT output waveform having a duty cycle of 1 4 and a frequency of 200 Hz is output from the TM7IO and TMSIO output pins with a dead time of 0 01 ms or 0 02 ms added The setup procedure and its description are shown below IGBT trigger IRQO IGBT waveform TM71O output waveform TMBIO output waveform 0 01 ms 0 02 ms 0 01 ms 0 02 ms 0 01 ms 200 Hz Figure 9 11 3 Output Waveform of TM7IO and TM8IO Setting Register Description Disable the timer counter M7MD TM7EN 0
16. LCD output control register 4 XVII 13 LCCTR5 0x03E8B LCD output control register 5 XVII 14 LCDSEL 0x03E8E R W Readable Writable Control Registers LCD COM SEG selection register XVII 15 Chapter 7 I O Port 7 2 1 Port n Output Registers PnOUT is the register to set output data in when I O is used as a general purpose port m Port 0 Output Register POOUT 0x03F10 Bit name POOUT7 0 At reset X X X X X X X X m Output data POOUT7 0 0 Output Low Vss level 1 Output High Port 1 Output Register P1OUT 0x03F11 Bit name P10UT7 0 At reset X X X X X X X X Access R W R W R W R W R W R W R W R W e mmm mmm _ Output data 7 0 P1OUT7 0 0 Output Low Vss level 1 Output High Vppao level Port 2 Output Register P2OUT 0x03F12 Bit name At reset Access m Output data 7 0 P2OUT7 0 0 Output Low Vss level 1 Output High Vppao level Control Registers VII 5 Chapter 7 Port Port3 Output Register 0x03F13 Bit name At reset Access e sm E Output data 7 0 P3OUT7 0 0 Output Low 1 Output High Vppao level Port 4 Output Register PAOUT 0x03F 14 Bit name At reset
17. Table 7 12 4 P82 Function Selection Setup Function Register ANEN1 Bit name ANEN12 1 C1 0 P82 Table 7 12 5 P83 Function Selection Setup Function Register ANEN1 Bit name ANEN13 1 2 0 P83 Table 7 12 6 P84 Function Selection Setup Function Register ANEN1 Bit name ANEN14 1 VLC3 0 P84 Table 7 12 7 P85 Function Selection Setup Function Register ANEN1 Bit name ANEN15 1 VLC2 0 P85 Port 8 Chapter 7 I O Port VII 59 Chapter 7 Port VII 60 Port 8 Chapter 8 8 bit Timer Chapter 8 8 bit Timer VIII 2 8 1 Overview This LSI has six 8 bit timers Timer 0 to Timer 5 pins used for each 8 bit Timer has three pin groups Group A and Group B ex Timer 0 has TMOIOA and TMOIOB In this chapter the suffix of A and B is omitted to describe functions of 8 bit Timer 8 1 1 Functions SSS IMMM Table 8 1 1 shows functions that can be used for each timer Table 8 1 1 8 bit Timer Functions Interrupt source TMOIRQ TM1IRQ TM2IRQ TM4IRQ PERIOIRQO Event count Timer pulse output PWM output PWM output with additional pulses 5 TM1IOA P55 TM1IOB P20 TM2IOA PO05 TM2IOB P02 56 TMSIOB P72 TM4IOA P34 TM4IOB P01 5
18. XXXXXXX 0 Pi MN m Slave address R W ACK Data ACK XXXXXXX 1 cordon Slave RAW Data XXXXXXX 1 2 Slave address R W ACK Data XXXXXXX 0 22 Slave address R W ACK Data Communication Data from other IIC Figure 13 5 1 Communication Sequence in 7 bit Addressing Format Chapter 13 Serial Interface 13 5 2 Operation nuu ome Serial Reset SCIFn has a built in serial reset function for abnormal operation SCnMD0 3 other than SCnMDO0 IIC3STE SCnMD3 IIC3STPC SCnMD3 IIC3REX and SCnMD3 IIC3ACKO must be changed during the serial reset of SCIFn SCnSTR SCnTEMP SCnREMP SCnORE bp6 0 of SCnIICSTR and SC3MD3 IIC3STPC are initialized by the serial reset when setting SC3MD2 SCnRSTN to 0 W Generating Transfer Clock SCnCLK and Baud Rate Timer Output Clock BRTM SCnCLK SCnCLK is identical with BRTM SCnCLK in communication mode This function is common with the Clock Synchronous communication For more information see XIII 30 In slave communication set BRTM_SCnCLK to detect start stop condition See Table 13 5 1 interrupt Source A communication completion interrupt SCnTICR occurs when transmitting receiving ACK NACK or detecting the forced termination of a communication A stop condition detection interrupt SCnSICR occurs when
19. Access Bit name Description BSTVOL enable control LCUPEN 0 stop 1 start Reserved Must be set to 0 LCUPCK selection 000 LCUPCKS x 1 8 001 LCUPCKS x 1 16 LCUPCKDIV2 0 010 LCUPCKS 1 32 011 LCUPCKS x 1 64 100 LCUPCKS x 1 128 110 111 Setting prohibited LCUPCKS selection 000 SCLK 001 HCLK 2 010 HCLK 2 011 HCLK 26 100 HCLK 27 101 HCLK 28 110 111 Setting prohibited LCUPCKS2 0 Control Registers XVII 5 Chapter 17 LCD m LCD Mode Control Register 1 LCDMD1 0x03E81 Bit name LCVREN LCVRO4 0 At reset 0 0 Access Bit name LCVREN REFVOL enable control 0 stop 1 start Description 6 5 Always read as 0 4 0 LCVRO4 0 XVII 6 Control Registers Output voltage of REFVOL Incremented by 0 05 V 00000 0 9 V 00001 0 95 V 10010 1 8 V 10011 11111 Setting prohibited m LCD Mode Control Register 2 LCDMD2 0x03E82 Bit name LCMODS Reserved LCDTY2 0 Chapter 17 LCD At reset 0 0 0 Access Bit name Description LCD display driver control 0 Stop 1 Start LCMOD1 0 LCD display mode 00 Normal 01 All LCD on 10 All LCD off 11 Setting prohibited LCMODS Selects a display waveform 0 Line reverse 1 Frame reverse Reserved Must be set to 0 LCDTY2 0 LCD display duty
20. mode Watchdog timer HALT STOP 0 1 2 3 conticue counting mode STOP stop counting CPU can t return the CPU operating mode because interrupt as the return factor is not occured again Figure 4 2 13 Example of Not Returning to CPU Operating Mode Mode Control Function IV 23 Chapter 4 Clock Mode Voltage Control NORMAL SLOW mode Disable maskable interrupts Set the PSW MIE to 0 and set all interrupt enable bits XICR IE to 0 Enable interrupt which Set the xICR IE of the return factor to 1 triggers return Return factor interrupt occured z Set HALT STOP mode Watchdog timer HALT STOP HALTO 1 2 3 continue counting mode STOP stop counting Retum iactoranterrupr detected 207 When the transition corresponds to 1 in Figure 4 2 1 the oscillation stabilization wait time is inserted Watchdog timer NORMAL SLOW HALTO 1 2 3 continue counting mode STOP restart counting Enable maskable interrupts Set the PSW MIE to 1 Interrupt service routine Y Figure 4 2 14 Operation in STANDBY Mode and Interrupt Acceptance Sequence with Interrupt Disabled Set the PSW MIE to 0 before the transition to STANDBY mode Insert 3 NOP instructions right after the instruction for the transition to STANDBY mode set 1 ting to CPUM HALT or CPUM STOP The instruction for the transition
21. TM5CK1 0 1 1 1 0 SEGO 1 E 1 TMBIO output 0 11 1 TMBIO input 0 Mis P73 VII 56 Port 7 Table 7 11 6 P74 Function Selection Setup Function Register LCCTRO Bit name COMSLS3 1 0 74 Table 7 11 7 P75 Function Selection Setup Function Register LCCTR0 Bit name COMSL2 1 COM2 0 P75 Table 7 11 8 P76 Function Selection Setup Function Register LCCTRO Bit name COMSL1 1 COM1 0 P76 Table 7 11 9 P77 Function Selection Setup Function Register LCCTRO Bit name COMSLO 1 COMO 0 P77 Port 7 Chapter 7 I O Port VII 57 Chapter 7 Port 7 12 Port 8 The following table shows the special functions of Port 8 7 12 1 Table 7 12 1 Port 8 pin Special function P80 OSC1 IRQ2A P81 OSC2 IRQ3A P82 C1 P83 C2 P84 VLC3 P85 VLC2 Setup of Port 8 Function setup of Port 8 is shown below VII 58 Port 8 Table 7 12 2 P80 Function Selection Setup Function Register ANEN1 IRQIEN IRQISELO Bit name ANEN10 2 IRQ2SEL 1 OSC1 1 0 IRQ2A 0 P80 Table 7 12 3 P81 Function Selection Setup Function Register ANEN1 IRQIEN IRQISELO Bit name ANEN11 IRQISEN IRQ3SEL 1 OSC2 1 0 IRQ3A 0 i P81
22. B10 HRCCLK10 FCNT 00 10 MHz Vpp30 1 8 V to 3 6 V F B11 Frequency HRCCLKS8 01 8 Vpp3o 1 3 V to 3 6 V al B12 HROCLKI EGNIT 10 1 MHz Electrical Characteristics Chapter 1 Overview VnsrL to 3 6 V Vss 0 V 1 1 V at auto reset function Ta 40 C to 85 C Limits P t Symbol Conditi Unit MAE d MIN TYP MAX funccik 8 10 MHz B13 Temperature Voltage er 0 Cto 50 C 1 5 1 5 4 dependence T 8R0 MH B14 Epp HncctK 8 10 MHz T Ta 40 to 85 Temperature Voltage E 1 MHz 10 10 di dependence F5 Ta 40 C to 85 C ae 0 0 Internal low speed RC oscillation B16 Frequency Vppao Vnsrt to 3 6 V 40 kHz 817 Temperature Voltage Ere Ta 40 C to 85 m _ dependence 10 Output frequency of the internal high speed RC oscillation can be selected by setting the FCNT bit of HCLKCNT register OSC1 fHOSCCLK OSC2 LSI 2 C11 Feedback resistor is embedded Figure 1 4 1 High speed oscillation XI fsosccLk XO LSI C22 C21 Feedback resistor is embedded Figure 1 4 2 Low speed oscillation c
23. 18 18 3 x 1 fsyscLK XVI 10 Operation Chapter 16 A D Converter ADC conversion cycle depending on phase differences between system clock and A D conversion 1 A D conversion time indicated in Table 16 3 2 may shorten up to one cycle time of A D clock m A D Resistor Ladder Control ANCTRO ANLADE is set to 1 to apply current to the resistor ladder for A D conversion When A D con version is stopped the ANCTRO ANLADE is set to 0 to save the power consumption Conversion Starting Factor Setup A D conversion starting factor is set by ANCTR2 ANSTSELI 0 The ANCTR2 ANSTSEL1 0 are set to select the starting factor of External interrupt 0 Timer 7 interrupt or A D conversion interrupt In addition the A D conversion is started by setting the ANCTR2 ANST to 1 When External Interrupt 0 is selected as the A D conversion starting factor the valid edge Y should be assigned by IRQOICR REDGO The interrupt valid edge need to be assigned before selecting the interrupt 0 factor Y for A D conversion starting factor Conversion Starting Setup The start of A D conversion is set by the ANCTR2 ANST The A D conversion is started by setting the ANCTR2 ANST to 1 When A D conversion is started by External Interrupt 0 factor Timer 7 interrupt factor or A D conversion interrupt factor the ANCTR2 ANST is set to 1 automatically after External Interrupt
24. 9 ATOS 10H Figure 10 1 1 Block Diagram Timer 6 Time Base Timer X 3 Overview Chapter 10 General Purpose Time Base Free Running Timer 10 2 Control Registers The timer 6 consists of the binary counter TM6BC and compare register TM6OO and is controlled by mode register TM6MD setting The time base timer is controlled by using the mode register TM6MD and time base timer clear register TBCLR Start stop operation of both timers is controlled with the enable signal of the timer 6 enable register TM6BEN 10 2 1 Control Registers 10 2 1 shows registers that control timer 6 and time base timer Table 10 2 1 Control Registers Address Register Name TM6BC 0x03F78 Timer 6 binary counter TM6OC 0x03F79 Timer 6 compare register TM6MD OxOSF7A Timer 6 mode register TM6BEN 0x03F7C Timer 6 enable register Tiere Peripheral function Group 0 interrupt level PERIOICR OxOSFFD control register Peripheral function Group 0 interrupt enable PERIOEN OxOSFDC register Peripheral function Group 0 interrupt factor register PERIODT OxOSFDD TM6MD OxOSF7A Timer 6 mode register TBCLR 0x03F7B Time base timer clear control register f PERIOICR 0x03FFD Peripheral function Group 0 interrupt level Time base timer control register Peripheral function Group 0 interrupt enable PERIOEN OxOSFDC register Peripheral f
25. 7 Output Yes changed P05 SBT3A SCL3A TMOIOA TM2IOA CLKOUTA Yes SBI3A TM8IOB Yes 07 SBCS3A TM9IOA Yes 10 ANO IRQOA KEYOA Port 1 At each port the I O direction and the pull up resistor Pl ANTIRQTA KEYTA No connection is controlled individually 12 AN2 IRQ4C KEY2A At LSI reset each is set to input mode and the pull up resistor is not connected P13 AN3 IRQ5C KEY3A Input No P14 AN4 IRQ4A KEY4A OCD_CLK Output No P15 _ P16 ANG6G IRQ6A KEY6A 17 AN7 KEY7A 20 SEG42 TM1IOB TM9IOB Yes Port 2 At each port the direction and the pull up resistor Pel SEGATTMSIOR Yes connection is controlled individually P22 SEG40 SBI2B Yes At LSI reset each pin is set to input mode and the pull up Input resistor is not connected P23 SEG39 SBO2B SDA2B Output Yes The drive strength of output Nch transistor can be P24 SEG38 SBT2B SCL2B Yes changes P25 SEG37 SBCS2B Yes P26 SEG36 SBI1A RXD1A Yes P27 NRST Input No Port 2 Output LSI is reset by setting P2OUT P20UT7 to 0 SEG35 SBO1A TXD1A Yes Port 3 At each port the direction and the pull up resistor SEG34 SBTIA Yes connection is controlled individually P32 SEG33 SBCSIA Yes At LSI reset each pin is set to input mode and the pull up resistor is not connected P33 SEG32 BUZA Input Yes The drive strength of output Nch transistor can be P34 SEG3
26. BRT1SCLK BRT1SCLK 2 BRT1SCLK 4 BRT1SCLK 8 BRT1SCLK 16 BRT1SCLK 32 BRT1SCLK 64 0111 BRT1SCLK 128 1000 1001 1010 1011 1100 BRT1SCLK 256 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 8 Description 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRT1SCLK is the clock selected with BRTM_S_CKSEL BRTM_S1_CKSEL BRTMO count clock selection 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 BRTOSCLK BRTOSCLK 2 BRTOSCLK 4 BRTOSCLK 8 BRTOSCLK 16 BRTOSCLK 32 BRTOSCLK 64 BRTOSCLK 128 BRTOSCLK 256 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 8 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRTOSCLK is the clock selected with BRTM 5 CKSEL BRTM SO CKSEL Control Registers 25 Chapter 13 Serial Interface m BRTM23 Count Clock Select Register BRTM S23 CK Bit name Initial value Access Bit name Description BRTMS count clock selection 0000 BRT3SCLK 0001 5 2 0010 5 4 0011 5 8 0100 5 16 0101 BRT3SCLK 32 0110 5 64 0111 5 128 1000 BRT3SCLK 256 1001 SYSCLK 1010 SYSCLK 2 1011 SYSCLK 4 1100 SYSCLK 8 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRT3SCLK is the clock selected with BRTM S CKSEL BRTM S3 CKSEL 2 count clock selection 0000 BRT2SCLK 0001 BRT2SCLK 2 0010 BRT2SC
27. In the event count the internal enable signal becomes ON status at the falling edge of the first count clock after the TMnMD1 TMnEN is set to 1 When it is assumed that the setting value of compare register is N the first interrupt is generated at the falling edge of N 2 th count clock The following interrupts are generated at the falling edge of N 1 th count clock IX 26 16 bit Event Count Chapter 9 16 bit Timer W Count Timing of TMnIO Input at Both Edges Selected Timer 7 and Timer 8 The binary counter counts up at the falling and rising edges of TMnIO input signal that is divided or not TMnIO input Count clock TMnEN bit Compare register 1 Binary counter Interrupt request 0000 0001 02 04 032 0000 0001 Figure 9 4 2 Count Timing of TMnIO Input at Both Edges Selected 7 and 8 1 When selecting the both edge count the count is executed only at the normal operation mode with high speed oscillation Also when setting the TMnMD3 TMnCKSMP to 1 to select the system clock SYSCLK the count is not executed correctly Input signal from TMnIO should be set to the cycle more than twice the HCLK When the other signal with the shorter cycle is input the count may not be executed correctly 16 bit Event Count IX 27 Chapter 9 16 bit Timer IX 28 9 4 2 Setup Example Te W Event Count Setup Example Here is an example that using timer 7 d
28. bp 7 6 5 4 3 2 1 0 Bit name Reserved Reserved Reserved DBA0 At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W Bit name Description Always read as 0 Reserved Must be set to 0 Assignment of bank for destination data access address DBA0 0 bank 0 1 bank 1 Bit manipulation instruction depends on the value of the SBNKR register both of for reading and writing 12 Overview Chapter 2 CPU 2 1 10 Special Function Register B a sx This LSI locates the special function registers I O spaces at the addresses 0x03C00 to 0x03FFF in memory space The special function registers of this LSI are located as shown below The addresses 0x03000 to are reserved Table 2 1 5 MN101LRO5D Register Map Reserved 0x03D7X 0x03D8X FBEWER WADDR L WADDR H 0x03D9X Reserved 0x03DFX 0x03E0X DMCTROL DMCTROH DMCTR1L DMCTR1H DMSRCL DMSRCM DMSRCH DMDSTL DMDSTM DMDSTH DMCNTL DMCNTH 0x03E1X PRICKCN PRICKCN PRICKCN T1 T2 Ox03E2X 0x03E3X SCOMDO SC0MD1 SCOMD2 SCOMD3 SCOSTR RXBUFO TXBUFO 0x03E4X SC1MDO SC1MD1 SC1MD2 SC1MD3 SC1STR RXBUF1 TXBUF1 0x03E5X SC2MDO SC2MD1 SC2MD2 SC2MD3 SC2AD Reserved SC2STR WDATA _M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SC
29. P2IN P3IN P4IN P5IN P6IN P7IN P8IN Reserved TMIOENO TMIOSEL0 TMIOEN1 TMIOSEL1 PODIR P1DIR P2DIR P3DIR P4DIR P5DIR P6DIR P7DIR P8DIR Reserved CLKOUT IRQISEL1 Ox03F4X POPLUP PiPLUP P2PLUP P3PLUP P4PLUP PePLUP P7PLUP P8PLUP IRGISELO KEYIEN KEYSEL 0x03F5X POODC P1ODC 200 P30DC P40DC P5ODC P6ODC ANENO ANEN1 BUZCNT Ox03F6X ANCTRO ANCTR1 ANCTR2 ANBUFO ANBUF1 LVICTRO LVICTR1 LVICTR2 PWCTRO PWCTR1 Reserved 0x03F7X TMOBC TM1BC TMOOC TM1OC TMOMD TM1MD CKOMD CK1MD TM6BC TM6BEN BUZCTR 0 03 8 TM2BC TM2OC TM3OC TM2MD TM3MD CK2MD CK3MD 0x03F9X TM4BC TM5BC TM4OC TM5OC TM4MD TM5MD CK4MD CK5MD TM7MD4 TM8MD4 TM7BCL TM7BCH TM7OC1L TM7OC1H TM7PR1L TM7PR1H TM7ICL TM7ICH TM7MD1 TM7MD2 TM7OC2L TM7OC2H TM7PR2L TM7PR2H TM7DPR1 TM7DPR2 0x03FBX TM8BCL TM8BCH TM8OC1L TM8OC1H TM8PR1L TM8PR1H TM8ICL TM8ICH TM8MD1 TM8MD2 TM8OC2L TM8OC2H TM8PR2L TM8PR2H TM7MD3 TM8MD3 0x03FCX TM9BCL TM9OC1L TM9OC1TH TMSICL TMSICH TM9MD2 TM9OC2L TM9OC2H TM9PR2L 2 TM9MD3 NFCTRO1 NFCTR23 NFCTR45 NFCTR67 EDGDT PERIOEN PERIODT PERHEN PERHDT 0x03FEX NMICR IRQ0ICR IRQ1ICR IRQ2ICR IRQ3ICR IRQ4ICR IRQ5ICR IRQ6ICR IRQ7ICR TMOICR TM1ICR TM2ICR TM3ICR TM4ICR
30. 17 2 3 2 Extended Calculation Control Register 18 2 4 Extended Calculation 3 II 20 2 4 1 About Extended Calculation Instruction eese nennen II 20 2 4 2 MULWU 16 bit x 16 bit multiplication unsigned aa II 21 2 4 3 16 bit x 16 bit multiplication Signed eee 22 2 4 4 DIVWU 32 bit 16 bit division unsigned eese II 23 2 4 5 BCDADD BCD addition without II 24 2 4 6 BCDADDC BCD addition with carry enne II 25 2 4 7 BCDSUB BCD subtraction without a II 26 2 4 8 BCDSUBC BCD subtraction with carry enne ener nnne II 27 pERMCID sobs II 28 2 5 T Reset fUDCUIOD etaed ere A II 28 2 5 2 ReSet SEQUENCE Lacon ode eb REUS sas II 29 2 5 3 Oscillation Stabilization Wait Time sessi II 30 Chapter 5 Interrupts i o n Rc aha III 1 SEL OVERVICW Soi aeu Hee aep ERROR SE ERE III 2 T Block Diagram i eot Ucet III 3 312 Operation sae cede tier bebe pee 4 3 1 3 Maskable Interrupt Control Register Setup sess 15 3 1 4 Group Interrupt Control Register Setup sese III 17 5 2 Co
31. 21 TMSIOB P73 Pulse width measurement External Interrupt 0 IRQOA P10 IRQOB P60 External Interrupt 2 IRQ2A P80 IRQ2B P62 External Interrupt 4 IRQ4A P 14 IRQ4B P72 IRQ4C P12 Cascade connection V 16 bit counter N 16 bit counter Y 16 bit counter Clock source HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SYSCLK 2 SYSCLK 4 SCLK TM0IO input HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SYSCLK 2 SYSCLK 8 SCLK TM1IO input HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SYSCLK 2 SYSCLK 4 SCLK TM2IO input HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SYSCLK 2 SYSCLK 8 SCLK TMSIO input HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SYSCLK 2 SYSCLK 4 SCLK TM4IO input HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SYSCLK 2 SYSCLK 8 SCLK input HCLK Machine clock for high speed operation SCLK Machine clock for low speed operation SYSCLK System clock 4 1 Clock Control Overview Chapter 8 8 bit Timer 8 1 2 8 bit Timer Block Diagram 8 bit Timer block diagram is shown in Figure 8 1 1 Timer 0 Timer 2 and Timer 4 are described Timer n Timer 1 Timer 3 and Timer 5 are described Timer m HCLK 4 Emo 16 TMmOC register register matching detection M 0 TMmBC register x TMmIO output Timer m output generation TMmCK1 0 TMmMD register TMmPSC1 0
32. 74 75 P76 COM1 P77 The assignment and selection of LCD control pins differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 11 1 Setup of Port 7 IE ESE s ER Table 7 11 2 P70 Function Selection Setup Function Register LCCTR0 LCDSEL IRQIEN IRQISELO Bit name SEGSL3 COMSL7 IRQI6EN IRQ6SEL 1 1 gt E COM7 1 0 SEG3 1 1 IRQ6B 0 i P70 Table 7 11 3 P71 Function Selection Setup Function Register LCCTR0 LCDSEL IRQIEN IRQISELO Bit name SEGSL2 COMSL6 IRQ5SEL 1 1 COM6 1 0 SEG2 1 1 IRQ5B 0 P71 Chapter 7 Port Table 7 11 4 P72 Function Selection Setup Function Register LCCTR0 LCDSEL IRQIEN IRQISELO TM3MD TMIOSELO Bit name SEGSL1 COMSL5 IRQI4EN IRQ4SEL TM3OEN 1 0 TMSIOSEL 1 1 COM5 1 0 SEG1 1 1 IRQ4B 1 Ier thari 1 output 0 _ 11 0 11 1 TM3IO input 0 Other than P72 11 Table 7 11 5 P73 Function Selection Setup Function Register LCCTR0 LCDSEL TMIOEN0 TM5MD TMIOSELO Bitname SEGSLO COMSL4
33. I 35 161 Usage Notes MESTRE I 35 1 6 2 Dnu sed Pts sete eqq i Ule ue D eigen ence tate ess 1 36 1 6 3 Supply u 1 38 1 6 Power Supply cioe tih t petes 1 39 1 1 2 1 OVerVIe W conet o p ERRARE II 2 2 1 1 CPU Control Registers ie Ie II 3 2 1 2 Data Registers DO DI D2 D3 operenie fet teet rne cheated ete tee eee ene 3 2 1 3 Address Registers 0 A1 01 20 4 2 1 1 2 0 3 2 12 Stack Pointer SP oU uec a edm 4 2 1 5 Proeram Counter 4 2 1 6 Processor Status Word PSW 5 2 17 Address Space i coo es yasa 7 2 1 8 Addressing 9 2 1 9 Bank Function tech nte II 11 2 1 10 Special Function Register rite ee ote d erret pere ie pere rbi Erit eth 13 2 2 Bus nteffaCe II 14 2 2 T Bus Controllers ERR EE ERN epe APER ERE ets II 14 2 2 2 Access Cycle us sre ane eR ERE OR HERO E CERE ERES II 15 2 23 Control Registers desee ABR ee uineas II 16 2 3 Extended Calculation Function 17 lt Contents 1 gt DES ONI DA A abu
34. VIII 31 8 82 Setup Example s lah ettet huu tius VIII 33 Chapter 9 T6 bit Tami Pinus Hv IX 1 ES TTAuID IX 2 9 2 To bit Frmer Control Registers ooo teni enun ime leti 4 9 2 1 Programmable Timer Registers IX 6 9 2 2 Timer Mode R gistets uz aun tn inhi nad ORDRE Ix 10 9 3 T6 Dit Timer aie as e oc e e ia scored et IX 21 9 3 1 Op ration OB bp ep IX 21 9 3 2 Setup Example RP debo tete e m et Reg IX 24 9 4 16 bit Event Count a eere E OI Rte IX 25 9 4 Operation oie Fete imet e iie o ei e dece e et ee IX 25 942 Setup Example R en ene ehe S ERE ees IX 28 9 5 16 bit Timer Pulse e uu na au eene ener treten tentent tentent Saa 29 9 5 1 M IX 29 9 5 2 Setup Example d td Um T RTI IX 30 9 6 16 bit Standard PWM Output with Continuously Variable Duty eese IX 31 9 61 ded me deleti eben IX 31 9 6 2 Setup Example pene orit podeis tee IX 34 9 7 16 bit High Precision PWM Output with Continuously Variable Period Duty IX 35 lt Contents 5 gt 97 T Operation iore tei AH CE DEOR DE IX 35 9772 Setup Examples chasis eee ii tee Saaremaa IX 38 9 8
35. 4 0 14 C 2pF 16pF 18 pF R and C will be simplified to calculate 8 2 0 us Set the conversion clock that Tap gt 2 0 us When the setting of sample hold time ANCTRO ANSHI 0 is 2 set A D conversion clock ADCLK 1 0 MHz External analog signal LSI outut circuit Equivalent circuit of ADC ROUT RAD ANN 1 ANN X 40 5 ____ pr 16 pF 777 777 Figure 16 3 5 Example W External Capacitor When is large the input load will essentially comprise only Rap Cap and by providing a large capac itance 1000 pF to 1 uF outside It is also recommended that a large capacitance is added to outside as the protection against noise for the analog signal In this case ADC may not be possible to follow the analog signal with the large differential coefficient by an external capacitor affecting as a low path filter When converting a high speed analog signal insert a low impedance buffer When using this ADC evaluate enough that A D conversion is ensured the expected precision External analog signal LSI pu outut circuit Equivalent circuit of ADC Rout ANN ANN 2 4 0 i 2 pF T 7 7 16 pF 777 TIT 777 1000 pF to 1 Figure 16 3 6 Circuit Example with External Capacitor Ope
36. Interrupt enable for RTC TBT TBTIRQEN 0 Disable 1 Enable Interrupt cycle select for RTC TBT 000 128 Hz 001 64 Hz 010 32 Hz 2 0 011 16 2 100 8Hz 101 4Hz 110 2Hz 111 1Hz XI 4 Control Register Chapter 11 RTC Time Base Timer RTC TBT RTC TBT Control Register 1 TBTCNT1 Bit name TBTCLKOE TBTCLKOS3 0 At reset 0 0 0 0 0 Access Bit name Description Clock output enable for RTC TBT TBTCLKOE 0 Disable 1 Enable Always read as 0 Clock output select for RTC TBT 0000 256 Hz 0001 128 Hz 0010 64 Hz TBTCLKOS 0011 32 Hz 3 0 0100 16 Hz 0101 8 Hz 0110 4 Hz 0111 2 Hz 1000 1 Hz Control Register 5 Chapter 11 RTC Time Base Timer RTC TBT 11 2 2 Register was ra rr c rm rn m RTC TBT Register TBTR 0x03EEC Bit name T128HZ At reset X Access Bit name Description 7 T1HZ T1HZ output of RTC TBT 6 T2HZ T2HZ output of RTC TBT 5 T4HZ T4HZ output of RTC TBT 4 3 2 T8HZ T8HZ output of RTC TBT T16HZ T16HZ output of RTC TBT T32HZ T32HZ output of RTC TBT 1 T64HZ T64HZ output of RTC TBT 0 T128HZ T128HZ output of RTC TBT eral times and confirm that those values are same Otherwise the indeterminate data during a When reading the TBTR register during the time base timer operation read the register sev counting up ma
37. a abs16 Absolute abs18 branch instruction only E abs18 abs20 branch instruction only abs8 ir led o Specifies an 8 bit offset from the address 0 00000 The value of SBNKR or DBNKR Specifies an 8 bit offset from the top address of the 0 0 special function register area 0x03F00 Reuses the memory address accessed and is only The value of SBNKR available with the MOV and MOVW instructions or DBNKR Combined use with absolute addressing reduces code size RAM short io8 short 108 1 H half byte bit Figure 2 1 6 Addressing Mode 10 Overview Chapter 2 CPU 2 1 9 Bank Function Bank function allows the data access the area over the address of 0x10000 Bank function can be used by setting the proper bank area to the bank register for source address SBNKR and the bank register for destination address DBNKR At reset the two registers shows indicate bank 0 Bank func tion is valid after setting PSW BKD to 0 Table 2 1 4 Address Range Bank area Address Range bank 0 0x00000 to OxOFFFF bank 1 0x10000 to Ox1FFFF When SBNKR or DBNKR are changed at interrupt processing save them onto the stack area and restore them by software mode It is allocated for I O short instruction for data access from 0x03F00 to OxOSFFF For
38. counter TMnIO output PWM output 0000 Figure 9 7 2 Count Timing of High Precision PWM Output when compare register 2 is set to 0x0000 PWM output is High while the counter is stopped by setting TMnMD1 TMnEN to 0 16 bit High Precision PWM Output with Continuously Variable Period Duty Chapter 9 16 bit Timer W Count Timing of High Precision PWM Output when compare register 2 is set to compare register 1 1 Count clock eS UA ibj tec TMnEN bit Compare N register 1 register 2 Binary R 0000 0001 0000 0001 TMnIO output PWM output Figure 9 7 3 Count Timing of High Precision PWM Output When 2 is set to TMnOC1 1 N 1 When outputting the high precision PWM set the TMnMD2 TMnBCR to 1 to select TMnOC1 compare match as the binary counter clear source and the PWM set source to High state Also set the TMnMD2 TnPWMSL to 1 to select TMnOC2 compare match as the PWM reset source to Low state The PWM output at the initial state is Low It changes to High at the time the PWM tion is selected by setting the TMnMD2 TMnPWM When outputting the high precision PWM set the values of TMnOC1 and 2 as follow 2 lt 1 If TMnOC2 gt TMnOC1 the PWM output is fixed to Hig
39. LCD driver Segment output 43 pins SEG0 42 39 pins SEG4 42 31 pins SEG0 30 21 pins SEG0 20 Common output 4 pins COM0 3 8 pins COM0 7 4 pins COM0 3 4 pins COM0 3 Oscillation HOSCCLK SOSCCLK HRCCLK SRCCLK HOSCCLK SOSCCLK HRCCLK SRCCLK HOSCCLK SOSCCLK HRCCLK SRCCLK SOSCCLK HRCCLK SRCCLK Package 1 Timer function is available 2 Chip select pin is not assigned 80pinTQFP 64pinTQFP 48pinTQFP Comparison of Product Specification 32pinHQFN 1 7 Chapter 1 Overview Table 1 2 2 Functions of I O Port lO MN101LRO5D MN101LRO4D MN101LROS3D MN101LRO2D Port 7 6 4 3 1 7 5 4 3 2 1 0 7 2 5 al 4 4 4 al 4 al 4l 6 4 4 4 al 4 4 2 3 NI 3 3l 4 0 Nj 4 al 4 4 4 4 4 4 Y implemented port Y implemented I O port selectable N channel transistor drive strength not implemented Table 1 2 3 Functions of LCD Control MN101LRO5D MN101LRO4D MN101LROSD 4 3 4 4 3 not implemented LCD control function is not implemented in MN101LR02D Set 0 to the registers and bits corresponding to the functions which not implemented 1 8 Comparison of Product Specifica
40. RXBUF1 0x03E45 SCIF1 Reception Data Buffer XIII 10 TXBUF1 0x03E46 SCIF1 Transmission Data Buffer XIII 10 SC01SEL 0x03F1C SCIF01 I O Pin Switching Control Register XIII 9 SC2MDO 0x03E50 SCIF2 Mode Register 0 XIII 12 SC2MD1 0x03E51 SCIF2 Mode Register 1 XIII 14 SC2MD2 0x03E52 SCIF2 Mode Register 2 XIII 16 SC2MD3 0x03E53 SCIF2 Mode Register 3 XIII 18 SC2AD 0x03E54 SCIF2 Address Setting Register XIII 22 SC2STR 0x03E56 SCIF2 Status Register XIII 20 SC2IICSTR 0x03E57 SCIF2 Status Register for IIC dedicated XIII 21 RXBUF2 0x03E58 SCIF2 Reception Data Buffer XIII 10 TXBUF2 0x03E59 SCIF2 Transmission Data Buffer XIII 10 SC23SEL 0x03F1D SCIF23 Pin Switching Control Register XIII 9 Control Registers 7 Chapter 13 Serial Interface Register Address Access Register name symbol SC3MD0 0x03E60 SCIF3 Mode Register 0 XIII 12 SC3MD1 0x03E61 SCIF3 Mode Register 1 XIII 14 SC3MD2 0x03E62 SCIF3 Mode Register 2 XIII 16 SC3MD3 0x03E63 SCIF3 Mode Register 3 XIII 18 SC3AD 0x03E64 SCIF3 Address Setting Register XIII 22 SC3STR 0x03E66 SCIF3 Status Register XIII 20 SC3IICSTR 0 03 67 SCIF3 Status Register for IIC dedicated XIII 21 RXBUF3 0x03E68 SCIF3 Reception Data Buffer XIII 10 TXBUF3 0x03E69 SCIF3 Transmission Da
41. Control Registers XIII 13 Chapter 13 Serial Interface SCIFn 2 3 Mode Register 1 SC2MD1 SC3MD1 Bit name SCnSBTS SCnSBIS SCnSBOS Initial value 0 0 0 Access Bit name SCnIOM Description Data input pin selection 0 SBIn 1 SBOn SCnSBTS SBTn function control 0 Disable 1 Enable Input or Output transfer clock SCnSBIS Serial input control selection 0 Disable 1 fixed input 1 Enable Serial data input SCnSBOS SBOn function selection 0 Disable 1 Enable Serial data output SCnIFS Interrupt trigger selection Selectable only in Clock Synchronous communication and always set 0 in IIC communication 0 Communication completion interrupt 1 TXBUFn empty interrupt SCnMST Clock master salve selection Selectable only in Clock Synchronous communication and always set 1 in IIC communication 0 Clock slave 1 Clock master XIII 14 Control Registers 0 is always read out Chapter 13 Serial Interface m SCIFn n 0 1 Mode Register 2 SC0MD2 SC1MD2 Bit name SCnBRKF SCnBRKE Initial value 0 Access Bit name Description UART Frame mode specification 00 Data 7 bit stop 1 bit SCnFM1 0 01 Data 7 bit stop 2 bit 10 Data 8 bit stop 1 bit 11 Data 8 bit stop 2 bit UART parity bit selection At transmission At reception 00 Add 0
42. Bit name Access Bit name Description Clock control for DMA function PRICKCNT17 0 disabled 1 enabled Clock control for Serial 3 function PRICKCNT16 0 disabled 1 enabled Clock control for Serial 2 function PRICKCNT15 0 disabled 1 enabled Clock control for Serial 1 function PRICKCNT14 0 disabled 1 enabled Clock control for Serial 0 function PRICKCNT13 0 disabled 1 enabled Clock control for Timer 9 PRICKCNT12 0 disabled 1 enabled Clock control for Timer 8 PRICKCNT11 0 disabled 1 enabled Clock control for Timer 7 PRICKCNT10 0 disabled 1 enabled IV 10 Clock Control Chapter 4 Clock Mode Voltage Control m Clock Supply Control Register 2 PRICKCNT2 0x03E12 Clock supply control register 2 controls clock supply to peripheral functions bp 5 4 3 2 1 0 Bit name PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT 25 24 23 22 21 20 Initial value 0 0 0 0 0 0 Access Bit name Description Always read as 0 PRICKCNT25 Clock control for RTC time base timer function 0 disabled 1 enabled PRICKCNT24 Clock control for Noise filter function Noise is removed by sampling 0 disabled 1 enabled PRICKCNT23 Clock control for LVI function 0 disabled 1 enabled PRICKCNT22 Clock control for 12 bit A D function 0 disabled 1 enabled
43. Description Select capture trigger edge 0 Both edges 1 Specified edge T9PWMSL Select PWM mode 0 Set duty through TM9OC1 1 Set duty through TM9OC2 TM9BCR Select timer clear source 0 Overflow by full count 1 Match between TM9BC and TM9OC1 TM9PWM Select timer output waveform 0 Timer output 1 PWM output TM9IRS1 Select timer interrupt source 0 Counter clear 1 Match of TM9BC and 9 1 T9ICEN Input capture operation enable 0 Disabled 1 Enabled T9ICT1 0 Select capture trigger 00 External Interrupt 0 input signal 01 External Interrupt 1 input signal 10 External Interrupt 2 input signal 11 External Interrupt 3 input signal 16 bit Timer Control Registers IX 19 Chapter 9 16 bit Timer Timer 9 Mode Register TM9MD3 name TM9CKSMP At reset 0 Access Select sampling clock for capture 0 Count clock 1 SYSCLK Always read as 0 1 When capture function is not used set the TM9MD3 TM9CKSMP to 0 Set the Timer 9 mode registers while the TM9MD1 TM9EN is 0 And the TM9MD1 TM9EN Y must not be changed at the same time as the other bit IX 20 16 bit Timer Control Registers Chapter 9 16 bit Timer 9 3 16 bit Timer 9 3 1 Operation gm 16 bit Timer Operation Timer 7 Timer 8 and Timer 9 When the value of TMnBC matches the setting value of
44. SCLn i 3 5 x SCnCLK i I J n 4 Transfer rate SCnCLK divided by 8 Figure 13 5 3 SCLn without Low Period Extension by Slave Device Standard Mode I 1 1 H lt Transfer clock output from the LSI E ou I I I SCLn I bd N lt I i i in I I Low period extension by slave 3 5 x SCnCLK i 1 Transfer rate SCnCLK divided by 9 Figure 13 5 4 SCLn with Low Period Extension by Slave Device Standard Mode XIII 60 IIC Communication Chapter 13 Serial Interface 1 gt I I I Transfer clock I output from the LSI i 1 1 1 1 lt SOEN 2 x SCnCLK 1 Transfer rate SCnCLK divided by 8 Figure 13 5 5 SCLn without Low Period Extension by Slave Device High speed Mode LF LALA LALA LALA LT LT L T I I I I I I 1 High period extension 1 lt gt I I I I I 1 Transfer clock output from the LSI _ 1 1 2 x SCnCLK Low period extension by slave Transfer rate SCnCLK divided by 9 Figure 13 5 6 SCLn with Low Period Extension by Slave Device High speed Mode Set the rising time of SCLn to the period of up to 0 5 SCNCLK in Standard Mode or up to 1 Y SCnCLK in High speed Mode IIC Communication XIII 61 Chapter 13 Serial Interface 13 5 3 Timing W Master Transmission Timing 1 2 3 4 5 6
45. The setup procedure and its description are shown below IGBT trigger TM7IO output 152 59 Hz lt Figure 9 9 4 Output Waveform of TM7IO output pin Setting Disable the timer counter Register TM7MD TM7EN 0 Description Disable the timer count operation Select the IGBT output pin TMIOEN1 TM7OEN 1 PODIR PODIR4 1 Select the IGBT output pin Chapter 7 I O Port Set the timer mode register M7MD3 T7IGBTEN 1 M7MD2 TM7PWM 1 M7MD1 TM7CL 0 Enable the IGBT output M7MD2 TM7BCR 0 Select the TM7BC clear source Select the IGBT trigger source M7MD3 T7IGBTTR 1 Select the IGBT trigger level M7MD4 T7NODED 1 Select No as the dead time M7MD1 TM7CK1 0 00 T T T T TM7MD3 T7IGBT1 0 01 T T T TM7MD1 TM7PS1 0 00 Select HCLK as the count clock source Set the High period of IGBT TM7PR1 0x3FFF Set the High period of IGBT output Setup value 65536 4 1 16383 0x3FFF Set the external interrupt IRQISEL0 IRQ0SEL 0 IRQIEN IRQIOEN 1 Enable the external interrupt pin Enable the timer counter IX 50 TM7MD1 TM7EN 1 16 bit Standard IGBT Output with Variable Duty Enable the timer count operation Chapter 9 16 bit Timer 9 10 16 bit High Precision IGBT Output with Variable Period Duty The high precision IGBT signal is output from TM7IO or 8 pin while the ti
46. 0 Bit name IRQI6EN IRQISEN IRQI4EN IRQI3EN IRQI2EN IRQI1EN IRQIOEN At reset 0 0 0 0 0 0 0 Access Bit name Description Always read as 0 IRQIGEN IRQ6 input enable control 0 Disable 1 Enable IRQ6A IRQ6B IRQIBEN IRQ5 input enable control 0 Disable 1 Enable IRQ5A IRQ5B IRQ5C IRQIAEN IRQ4 input enable control 0 Disable 1 Enable IRQ4A IRQ4B IRQ4C IRQISEN IRQS input enable control 0 Disable 1 Enable IRQ3A IRQ3B 2 IRQ2 input enable control 0 Disable 1 Enable IRQ2A IRQ2B IRQI1EN IRQ1 input enable control 0 Disable 1 Enable RQ1A IRQ1B IRQIOEN IRQO input enable control 0 Disable 1 Enable IRQOA IRQOB External Interrupts Ill 35 Chapter 3 Interrupts W External Interrupt Input pin Selection Register 0 IRQISELO bp 6 5 4 3 2 1 0 Bit name IRQ6SEL IRQ5SEL IRQ4SEL IRQ3SEL IRQ2SEL IRQ1SEL IRQOSEL At reset 0 0 0 0 0 0 0 Access Bit name Always read as 0 Description IRQ6SEL IRQ6 pin selection 0 IRQ6A P16 1 IRQ6B P70 IRQ5SEL IRQ5 pin selection 0 IRQ5A P15 1 IRQ5B P71 IRQ4SEL IRQ4 pin selection 0 IRQ4A P14 1 IRQ4B P72 IRQSSEL IRQ3 pin selection 0 IRQ3A P81 1 IRQ3B P63 IRQ2SEL IRQ2 pin sel
47. 01 External interrupt 0 or setting ANST bit to 1 10 Timer 7 interrupt or setting ANST bit to 1 11 A D conversion interrupt or setting ANST bit to 1 XVI 6 Control Registers Always read as 0 16 2 3 Data Buffers Chapter 16 A D Converter ADC m ADC Data Storage Buffer 0 ANBUFO 0x03F64 This register stores lower 4 bits data after A D conversion ANBUFO7 ANBUFO6 5 ANBUF04 Bit name At reset X X X Mese m ADC Data Storage Buffer 1 ANBUF1 0x03F65 This register stores upper 8 bits after A D conversion Bit name ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 At reset X X X X X X X X Access R R R R R R R R Control Registers XVI 7 Chapter 16 A D Converter ADC 16 3 Operation The following shows the procedures for setting ADC circuit 1 Setthe analog input terminal Set the analog input terminal by Be sure to set Analog input control register before applying analog voltage to the terminals 2 Select the analog input terminal Select the analog input pin from AN7 to ANO by setting the ANCTR1 ANCHS2 to 0 3 Select the A D conversion clock Select the A D conversion clock by setting the ANCTRO ANCK2 0 Set the conversion clock TApcr between 750 ns
48. 19 Chapter 17 LCD lt gt In the case of generating the drive voltage outside the LSI Supply each voltage described in Table 17 3 2 to VLC1 VLC2 and VLC3 Figure 17 3 1 shows the connection with the external resistors and each capacitor should be 0 1 uF Table 17 3 2 Voltage level of VLC1 VLC2 VLC3 Pin Name Voltage Level Static 1 2 bias 1 3 bias Vss Vicp Vss Vicp Vss 1 2 Vss 2 3 Vss Vss 1 3 Vss Vi cp LCD drive voltage the maximum voltage supplied to LCD panel a Static Vppao VLcp VDD30 input VLC1 VLC2 VLC3 b 1 2duty 1 2bias Vpp3o VDD30 input VLC1 VLC2 R VLC3 h l R VSS c 1 3duty to 1 8duty 1 3bias Vppao Vicp VDD30 o input VLCI S R VLC2 Rc VLC3 vss Figure 17 3 1 Connection Examples of LCD Power Supply when using external voltage dividing resistor XVII 20 Operation Chapter 17 LCD In Figure 17 3 1 power is consumed at resistors all the time Figure 17 3 2 is the method to stop the above power consumption VDD30 VLC1 VLC2 VLC3 VSS Vpp3o Port Vss input Figure 17 3 2 Connection example for LCD power supply Operation XVII 21 Chapter 17 LCD lt 2 gt In the case of generating the drive voltage with BSTVOL The re
49. Bit name SCnCE1 Description Clock polarity selection 0 Initial value High 1 Initial value Low SCnCTM Communication mode selection 0 Single byte communication 1 Consecutive byte communication IICSDEM Always set to 0 SCnDIR Transfer bit selection 0 MSB first 1 LSB first IIC3STE Start condition selection Selectable only communication always set to 0 in Clock Synchronous communication 0 Disable 1 Enable Reserved XIII 12 Control Registers Always set 111 m SCIFn n 0 1 Mode Register 1 SC0MD1 SC1MD1 Bit name SCnSBTS SCnSBIS SCnSBOS Chapter 13 Serial Interface Initial value 0 0 0 Access Bit name SCnIOM Description Data input pin selection 0 SBIn 1 SBOn SCnSBTS SBTn function control 0 Disable 1 Enable Input or Output transfer clock SCnSBIS function control 0 Disable 1 fixed input 1 Enable Serial data input SCnSBOS SBOn function control 0 Disable 1 Enable Serial data output SCnCKM BRTM output clock division control 0 Not divided 1 Divided SCnMST Clock master salve selection 0 Clock slave 1 Clock master SCnDIV Division ratio of BRTM output clock 0 Divided by 8 1 Divided by 16 SCnCMD Communication mode selection 0 Clock Synchronous communication 1 UART communication
50. Clock Source HCLK HCLK 2 HCLK 2 3 SYSCLK SCLK SCLK 2 SCLK 2 3 lt Time Base Timer gt Function An interrupt can be generated at a given set time Clock Source HCLK and SCLK Interrupt generation cycle 2 2 N 7 8 9 10 12 13 14 15 lt Timer 7 gt Function Square wave output PWM output duty cycle are programmable one shot pulse output IGBT output event count and input capture Clock Source Generated clock by dividing HCLK SYSCLK SCLK or TM7IO input by 1 2 4 or 16 lt Timer 8 gt Function Square wave output PWM output duty cycle are programmable event count and input capture Clock Source Generated clock by dividing HCLK SYSCLK SCLK or TM8IO input by 1 2 4 or 16 lt Timer 9 gt Function Square wave output PWM output duty cycle are programmable event count and input capture Clock Source Generated clock by dividing HCLK SYSCLK SCLK or TM9IO input by 1 2 4 or 16 MN101LR03D and MN101LR02D cannot be used square wave output PWM output event count and TM9IO lt RTC time base timer RTC TBT gt Function Clock generation for the Real Time Clock RTC Frequency correction Correction Range 488 ppm to 31220 ppm Accuracy approx 0 48 ppm to 30 52 ppm Clock Source SOSCCLK or SRCCLK lt Real Time Clock RTC gt Function Calendar calculation adjustment of leap year Periodic interrupt 0 5 s 1 s 1 min and 1 hour A
51. Figure 13 3 10 Reception Timing in STANDBY mode Reception at rising edge 38 Communication Chapter 13 Serial Interface 13 3 3 Operation Timing Transmission Timing Writing period to TXBUFn 3 5T T when consecutive communication mode SBTn SBOn SCnTBSY Set data to TXBUFn 4 Communication completion interrupt Figure 13 3 11 Transmission Timing At Falling Edge SCnCKPH bit 0 Twait Writing period to TXBUFn 3 5T T when consecutive communication mode SBTn SBOn SCnTBSY 7 Set data to TXBUFn Communication completion interrupt Figure 13 3 12 Transmission Timing At Rising Edge SCnCKPH bit 0 Clock Synchronous Communication XIII 39 Chapter 13 Serial Interface W Reception Timing Twait Writing period to TXBUFn 3 5T T when consecutive communication mode SBTn SBOn SBIn SCnRBSY Set data to TXBUFn d Communication completion interrupt Figure 13 3 13 Reception Timing At Rising Edge SCnCKPH bit 0 Twait Writing period to TXBUFn 3 5T T f f when consecutive communication mode SBTn SBOn SBIn SCnRBSY Set data to TXBUFn d Communication completion interrupt Figure 13 3 14 Reception Timing At Falling Edge SCnCKPH bit 0 40 Communication Chapter 13 Serial Interface 13 3 4 Setting Procedure B i s rw
52. Mode Control Function IV 13 Chapter 4 Clock Mode Voltage Control To make clock switching between HCLK and SCLK stable and synchronized the frequency 1 of HCLK must be 2 5 times or more than that of SCLK Although HCLK oscillates IDLE mode do not operate the peripheral circuits with HCLK Y Peripheral circuits must be enabled with HCLK after the CPU goes to NORMAL mode 14 Mode Control Function Chapter 4 Clock Mode Voltage Control 4 2 1 NORMAL Mode W Transition SLOW to NORMAL When the transition from SLOW to NORMAL the oscillation stabilization wait for HCLK is ensured by hard ware Figure 4 2 2 shows the transition procedure to NORMAL The transition to NORMAL through IDLE can be allowed when HCLK must be stable in IDLE as shown in Figure 4 2 3 SLOW mode Transition to NORMAL mode Set the CPUM as described in Table 4 1 3 Automatic high speed oscillation stabilization wait time by hardware NORMAL mode Figure 4 2 2 Transition Flow from SLOW to NORMAL Until entering NORMAL mode since the CPUM is set to transmit to NORMAL mode Y SYSCLK is generated from SCLK SLOW mode Transition to IDLE mode Set the CPUM as described in Table 4 1 3 iron eost gt NO Transition to OSC mode YES Transition to RC mode Start the internal high speed oscillation Start the external high speed oscillatio HCLKCNT HRCCNT 1 HCLKCNT
53. Set the interrupt cycle 0x04 Set the interrupt generation cycle Set the timer mode register TMOMD TMOPWM 0 TM0MD TM0MOD 0 Select the timer normal operation TMOMD TMOCK1 0 11 Select TMOIO input as the count clock source Set the interrupt level TMOICR TMOLV1 0 Enable the interrupt TMOICR TMOIE 1 Refer to 3 1 3 Maskable Interrupt Control Register Setup VIII 22 Enable the timer counter 8 bit Event Count TMOMD TMOEN 1 Enable the timer count operation Chapter 8 8 bit Timer 8 5 8 bit Timer Pulse Output 8 5 1 Operation m Operation of Timer Pulse Output In the timer pulse output function a pulse signal with a given frequency can be output from TMnIO pin Timers can output the signal with twice the cycle which is set in TMnOC Refer to Table 8 1 1 for the pulse output pin Count Timing of Timer Pulse Output TMnEN bit Compare register cat _ ah en counter Interrupt request A B TMnIO output Figure 8 5 1 Count Timing of Timer Pulse Output A The signal with twice the cycle which is set in TMnOC is output from TMnIO pin B When the value of TMnBC matches the setting value of TMnOC TMnBC is cleared to 0x00 and TMnIO output timer output is inverted 8 bit Timer Pulse Output VIII 23 Chapter 8 8 bit Timer 8 5 2 Setup Example r UPns 2 Timer Pulse Output
54. TBCLR6 TBCLR5 TBCLR4 TBCLR3 TBCLR2 TBCLR1 TBCLRO At reset Access Ww W W W W W W W Control Registers X 5 Chapter 10 General Purpose Time Base Free Running Timer 10 2 3 6 Enable Register This register controls the starting operation of the timer 6 and the time base timer W Timer 6 Enable Register TM6BEN 0x03F7C bp Bit name At reset Access Bit name Description Always read as 0 Time base timer operation control 0 Stop 1 Start Timer 6 operation control 0 Stop 1 Start X 6 Control Registers Chapter 10 General Purpose Time Base Free Running Timer 10 2 4 Timer Mode Register This is a readable writable register that controls the timer 6 and the time base timer W Timer 6 Mode Register TM6MD 0x03F7A bp 7 6 5 4 3 2 1 0 Bit name TM6CLRS TM6IR2 TM6IR1 TM6IRO TMeCK2 TM6CK1 TM6ICKO At reset Bit name TM6CLRS Description Timer 6 binary counter clear select 0 Enable the initialization of TM6BC when TM6OC is written 1 Disable the initialization of TM6BC when TM6OC is written When TM6CLRS 0 is disabled When TM6CLRS 1 PERIOIRQ1 is enabled TM6IR2 to 0 Interrupt cycle of time base timer select 000 Time base selection clock x 1 27 001 Time base selection cl
55. Vppso 3 0 V Vppig 1 8 V 21 34 fHosccuk fuRccLk 10 MHz C2 1552 Vpp30 3 0 V Vppig 1 8 V 2 1 3 0 8 MHz C3 Vppao 3 0 V Vppig 1 8 V 1 72 2 5 fHnccLk funccuk 8 MHz C4 1504 Vppao 9 0 V Vpp18 1 8V 0 94 1 5 Operating supply fsyscik 2 current fuosccuk 4 MHz C5 1505 Vppao 9 0 V Vpp18 1 8 V 0 84 1 3 fsyscLk furccik 1 MHz 6 1206 3 0 V Vppig 1 3 V 0 22 0 36 fsvscuk mA fsoscoLk 32 768 kHz 7 1557 Vppao 3 0 V Vppig 1 1 V m 5 6 9 5 fsosccud fsrccLk 40 kHz C8 3 0 V Vppig 1 1 V 42 11 6 2 24 Electrical Characteristics Chapter 1 Overview Vss 0 V C DC Characteristics Ta 40 C to 85 C Limits Parameter Symbol Condition MIN T MAX Unit HALTO mode C9 509 8 MHz 0 24 0 33 mA Vppao 3 0 V Vppig 1 1 V HALT2 mode fsoscciK 32 768 kHz C10 Ippio Vppao 3 0 V Vppig 1 1 V 0 2 0 4 25 HOSCCLK HRCCLK SRCCLK are stopped Supply current in HALT3 mode HALT fgqsccLk 32 768 kHz C11 15511 Vppao 3 0 V Vppig 1 1 V 0 5 0 7 Ta 25 C HALT
56. eee Eo ene eit e tede e PE ete eed XX 11 Contents 10 gt lt Contents 11 gt Chapter1 Overview Chapter 1 Overview 1 1 Hardware Features MNI01LR05D is described in this LSI user s manual For MN101LRO4D MN101LR03D and MN101LR02D refer to 1 2 Comparison of Product Specification and 1 3 1 Pin Configuration m Features In this document the divided clock and the frequency of it are described as follows Divided clock Clock name n n division ratio Frequency fclock name CPU Core AM13L core LOAD STORE architecture 3 or 4 stage Pipeline Machine Cycle and Operating Voltage High Speed mode 100 ns 10 MHz Max Vppao 1 8 V to 3 6 V 1 0 us 1 MHz Max 1 3 V to 3 6 V Low Speed Mode 25 40 kHz Max 1 1 V to 3 6 V Operating Mode NORMAL mode High Speed mode SLOW mode Low Speed mode HALT mode High Speed Low Speed mode STOP mode Embedded Memory ROM ReRAM 64 KB Programmable area 62 KB Data area 2 KB RAM 4 KB ReRAM Specification Program voltage 1 8 V to 3 6 V Program cycles 1 K Program area 100 K Data area Data is rewritable in bytes without data erase Clock Oscillator 4 circuits External Low Speed Oscillation SOSCCLK 32 768 kHz crystal or ceramic External High Speed Oscillation HOSCCLK up to 10 MHz crystal or ceramic Internal Low Speed Oscillation SRCCLK 40 kH
57. 2 Overview Chapter 19 On Board Debugger 19 2 List of on board debugging functions Table 19 2 1 List of on board debugging functions On board Debugging Functions Single step execution Descriptions Step execution as a source line or a unit of assembler Support or Not number of support channels Supported Functional step Execution execution Step execution which a subroutine is defined as 1 step Supported Program execution Basic execution Supported Microcomputer reset Reset for Microcomputer Supported Dump Dump display of memory Supported Edit Edit memory to specified value Supported Data display change Watch Display memory in a specified format when the program is running User program has possible to abort during access so the real time performance slows down little Supported Inspect Display according to a data structure of specified variable Supported Display Change register Display and change the specified register Supported RAM monitor function Display memory when the program is running User program has possible to abort during access so the real time performance slows down little Supported Back trace function Execute the back trace of stack frames and display the progress of function call Supported Effective address Define address and range Factor Data access Forced break Define acc
58. 6 5 Always read as 0 4 0 DMBG4 0 DMA start trigger 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 software trigger IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 KEY interrupt Timer 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt 01111 Timer 7 interrupt 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 Timer 7 input capture factor Timer 8 interrupt Timer 8 input capture factor Timer 9 interrupt Timer 9 input capture factor Serial interface 0 reception interrupt Serial interface 0 transmission interrupt Serial interface 0 buffer empty factor Serial interface 1 reception interrupt Serial interface 1 transmission interrupt Serial interface 1 buffer empty factor Serial interface 2 transmission complete interrupt Serial interface 2 buffer empty factor Serial interface 3 transmission complete interrupt Serial interface 3 buffer empty factor 11111 A D conversion interrupt DMA Controller Control Registers XIV 5 Chapter 14 DMA Controller 6 m Control Register 0 upper side DMCTROH 0x03E01 bp 7 6 5 4 3 1 Bit name DMUT DMTM DMDAM At reset 0 0 0 0 0 0 Access R R W R W R W bp Bit name Description
59. 7 6 Always read as 0 Data transmission unit 5 DMUT 0 8 bit 1 16 bit 4 Always read as 0 Transfer mode 3 DMTM 0 Burst transfer 1 Single transfer 2 Always read as 0 Destination Address increment control 1 DMDAM 0 Enable Incremented 1 Disable Fixed 0 Always read as 0 DMA Controller Control Registers Chapter 14 DMA Controller m Control Register 1 lower side DMCTR1L 0x03E02 bp 7 6 5 4 3 2 1 0 Bit name 5 gt DMTEN At reset 0 0 0 0 0 0 0 0 Access R R R R R W bp Bit name Description 7 1 Always read as 0 DMA transfer enable control After the DMTEN is set DMA waits for the DMA start trigger to occur 0 DMTEN When the software trigger is selected in DMCTR0L DMBG4 0 DMA transfer starts immediately after the DMTEN is set to 1 When the last data is transferred the DMTEN is cleared to 0 by hardware Setting the DMTEN to 0 during DMA transfer makes the transfer finished which is called Emergency stop DMA Controller Control Registers XIV 7 Chapter 14 DMA Controller XIV 8 m Control Register 1 upper side DMCTR1H 0x03E03 bp 7 6 5 4 3 2 1 0 Bit name DMOVF DMRQF At reset 0 0 0 0 0 0 0 0 Access R R R R R R bp Bit name Description 7 5 Always read as 0 DMA Error detection When the DMA Error occurs
60. Addressing modes 9 Instructions T byte Min asic portion 1 byte Min Instruction length Extended portion 0 5 byte x n 0 lt n lt 10 Internal operating frequency Max 10 MHz Instruction execution Min 1 cycle Basic performance Register to register operation Min 1 cycle Load Store Min 1 cycle Condition branch non branching 1 cycle branching 3 cycles Pipeline 3 stage instruction fetch decode execution 4 stage memory access 128 KB Data area 64 KB x 2 banks Address space One shared memory for Instruction and data Interrupt Vector interrupt 3 interrupt levels Low power STOP mode HALT mode consumption mode Overview Chapter 2 CPU 2 1 1 CPU Control Registers oGf Vs M o ET The LSI allocates the peripheral circuit registers in memory space 0x03000 to CPU control registers are also allocated in the space Table 2 1 2 CPU Control Registers Address Register name 0x03F00 CPU mode control register MEMCTR 0x03F01 Memory control register CKCTR 0x03F04 Clock control register AUCTR 0x03F07 Extended calculation control register SBNKR Bank register source address DBNKR 0x03F0B Bank register for destination address NMICR OxOSFE1 Non maskable interrupt control register OxOSFE2 xxxICR to Maskable interrupt control register OxO3FFE 2 1 2 Data Registers 00 D1 D2 03 Data registers DO to D3 are 8 bit ge
61. Always read as 0 1 0 TM5CK1 0 VIIL 14 8 bit Timer Control Registers Clock source select 00 HCLK 01 TM5PSC prescaler output 10 SCLK 11 TM5IO input Chapter 8 8 bit Timer 8 3 8 bit Timer 8 3 1 Operation In the 8 bit timer operation the timer can generate interrupts periodically 8 bit Timer Operation Timer 0 to Timer 5 The interrupt generation cycle of the timer is determined by selecting the clock source and setting the value of TMnOC in advance When the value of TMnBC matches the setting value of timer n compare register an inter rupt request is generated at the next count clock Then the timer n binary counter is cleared and restarts counting up from 0x00 The clock source can be selected depending on timers as shown in the table below Clock source Time per Count Timer 1 Timer 2 Timer 3 4 Timer 5 HCLK 100 ns HCLK 4 400 ns HCLK 16 1 6 us HCLK 32 3 2 us HCLK 64 6 4 us HCLK 128 12 8 us SYSCLK 2 400 ns SYSCLK 4 800 ns SYSCLK 8 1600 ns SCLK 30 5 us 10 MHz 32 768 kHz fevsci k HCLK 2 5 MHz When using SCLK as a clock source the timer counts at the falling edge of the count clock Y When using other clocks the timer counts at the rising edge of the count clock 8 bit Timer VIII 15 Chapter 8 8 bit Timer W Count Timing of Timer Operation Tim
62. Bit name At reset Access e mam E Input data 7 0 P7IN7 0 0 Input Low Vss level 1 Input High Vppao level VII 10 Control Registers Port 8 Input Register P8IN 0x03F28 Bit name Chapter 7 At reset Access Bit name Always read as 0 Description Input data 0 Input Low Vss level 1 Input High Vpp3o level Control Registers VII Port 11 Chapter 7 Port 7 2 3 Port n Direction Control Registers PnDIR is the register to control I O direction of I O when it is used a general purpose port m Port 0 Direction Control Register PODIR 0x03F30 BE IU aaa oe Bit name PODIR7 0 At reset 0 0 0 0 0 0 0 0 aw mw m mme Dem mode selection 7 0 PODIR7 0 0 Intput mode 1 Output mode m Port 1 Direction Control Register P1DIR 0x03F31 woes d ee At reset 0 0 Access sme I O mode selection 7 0 P1DIR7 0 0 Intput mode 1 Output mode m Port 2 Direction Control Register P2DIR 0x03F32 Bit name P2DIR6 0 At reset 0 0 Access Bit name Description Always read as 0 mode selection P2DIR6 0 0 Intput mode 1 Output mode VII 12 Control Registers Chapter 7 I O Port m Port 3 Direction Control Register P3DIR 0x03F33 Bit nam
63. Bite name Always read as 0 Description LVINFSCK2 0 Noise sampling frequency 000 fHCLK 001 1 25 010 26 011 27 100 28 101 22 110 219 111 LVINFEN VI 6 Control Register Noise filter enable control 0 Disabled 1 Enabled Chapter 6 Power Supply Voltage Detection 6 3 Setting Example 6 3 1 PSVD Setting Example m Mode Transition Operation with PSVD The following procedure shows that CPU transits from STOP to NORMAL mode when VDD30 exceeds 2 0 V Setup Procedure Description 1 Disable all maskable interrupts 1 Clear the MIE bit of PSW to disable all maskable PSW interrupts To change the interrupt control registers this bp6 MIE 0 step must be performed 2 Set the detection voltage 2 Set the LV4 to 0 bits of LVICTRO to 01100 to set the LVICTRO 0x03F66 level of power supply voltage detection to 2 0 V bp4 to 0 LV4 to LVO 01100 3 Enable power supply detection function 3 Set the LVION bit of LVICTR1 to 1 to enable the power LVICTR1 0x03F67 supply voltage detection function bp0 LVION 1 4 Wait for power supply voltage detection 4 Wait for the power supply voltage function activation function activation time 1 5 ms or more wait 1 5 ms 5 Clear the interrupt request bit 5 Clear the interrupt request bits by reading PERI1DT and PERI1DT 0xO03FDF writing the r
64. Clock Counter second minute hour date date of week month year Figure 12 1 1 Block Diagram of RTC Chapter 12 Real Time Clock RTC 12 2 Control Registers Table 12 2 1 lists the registers that control RTC Table 12 2 1 List of Control Registers Symbol Address R W Register Name Page RTCCTR 0x03ED0 RTC control register RTCALOIRQ 0x03ED3 ALOIRQMI 0x03ED4 ALOIRQH 0x03ED5 ALOIRQW 0x03ED6 arm 0 interrupt control register arm 0 minutes setting register arm 0 hours setting register arm 0 day of week setting register AL1IROMI 0x03ED8 AL1IRQH 0x03ED9 AL1IRQD AL1IRQMO 0x03EDB arm 1 month setting register RTCCIRQ 0x03ED2 Periodic interrupt control register RTCSD 0x03EE0 Seconds setting register RTCMID 0x03EE1 Minutes setting register RTCHD 0x03EE2 Hours setting register RTCWD 0x03EE3 Day of week setting register RTCDD 0x03EE4 Day setting register RTCMOD 0x03EE5 Month setting register RTCYD 0x03EE6 Year setting register RTCSTR 0x03ED1 RTC status register arm 1 minutes setting register arm 1 hours setting register arm 1 day setting register Al Al Al Al RTCAL1IRQ 0x03ED7 Alarm 1 interrupt control register Al Al Al Al Control Registers XII 3 Chapter 12 Real Time Clock RTC 4 12 2 1 RTC Control Register m RTC Control Register RTCCTR 39 D TTG Eze ren ee At reset Acce
65. Description Enable the IGBT output Select the IGBT output pin TMIOEN1 TM7OEN 1 TMIOEN1 TM8OEN 1 PODIR PODIR4 1 P5DIR P5DIR7 1 Select the IGBT output pin Chapter 7 I O Port Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation starts counting up from 0x0000 The IGBT output waveform is High until TM7BC matches the setting value of TM7OC2 The IGBT output waveform changes to Low at the TM7OC2 compare match The TM7BC continues counting up The IGBT output waveform returns to High when the binary counter is cleared by the TM7OCI compare match The IGBT output waveform with dead time is output from the TM7IO pin The inverted IGBT output waveform with dead time is output from the TM8IO pin IGBT Output with Dead Time IX 63 Chapter 9 16 bit Timer IX 64 IGBT Output with Dead Time Chapter 10 General Purpose Time Base Free Running Timer Chapter 10 General Purpose Time Base Free Running Timer 10 1 Overview This LSI has time base timer and 8 bit free running timer timer 6 The time base timer is a 15 bit timer 10 1 4 Functions Table 10 1 1 shows the clock source and the interrupt generation cycle that can be used for the timer 6 and the time base timer counter Table 10 1 1 Clock Source and Interrupt Generation Cycle Time base timer Timer 6 8 bit free running 8 bit timer operation Yes
66. Function Clock Source Timer 3 gt Function Clock Source Timer 4 gt Function Clock Source Timer 5 gt Function Clock Source Square wave output additional pulse PWM output event count simple pulse width measurement HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SCLK SYSCLK 2 SYSCLK 4 and TMOIO input Square wave output event count 16 bit cascade connection connected with Timer 0 HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SCLK SYSCLK 2 SYSCLK 8 and input Square wave output additional pulse PWM output event count simple pulse width measurement HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SCLK SYSCLK 2 SYSCLK 4 TM2IO input Square wave output event count 16 bit cascade connection connected with Timer 2 HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SCLK SYSCLK 2 SYSCLK 8 and TM3IO input Square wave output additional pulse PWM output event count simple pulse width measurement HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SCLK SYSCLK 2 SYSCLK 4 and TM4IO input Square wave output event count 16 bit cascade connection connected with Timer 4 HCLK HCLKA HCLK 16 HCLK 64 HCLK 128 SCLK SYSCLK 2 SYSCLK 8 and TMSIO input MNIOILRO2D cannot be used square wave output event count and 510 Hardware Features 1 3 Chapter 1 Overview lt Timer 6 gt Function One minute timer can be generated in combination with a time base timer
67. IV 17 4 2 3 STANDBY Mode nito iR nd t CORDE RUE FO ERR EHE RT REGE IV 19 4 2 4 Note for Transition to STANDBY ener IV 23 4 3 Voltage Control he ee pe o nm feed Rae IV 26 4 3 T OVerVIeW suatu ettet e de n pe nier re Ec ere PU ete ee IV 26 4 32 Register Tasten dt nO Ieri ee A es REL OE rre dee eee IV 26 4 3 3 Power Supply Control Register sees ener nennen nee IV 27 4 34 Operation eee peii eiie tre teresa ehe IV 29 4 4 Mode Voltage Clock Transition 3 teet het ir et ee ra 31 Chapter 5 Watchdog Timer WDT 1 Sl OVelVISW dee dE Re Rp eame V 2 5 2 WDT Control Register ere Ee eee te rtt naa ee ERE ene usss 3 23 2 WDT Control RESIS EL 3 SS 4 ants meet RP V 4 S 3 2Set up EX8mpl e uuu Iuda Ee ies eie ene eb c e tee Ere bro V 5 Chapter 6 Power Supply Voltage Detection a VI 1 un A O SAE E ORS VI 2 6 1 1 Power Supply Voltage Detection VI 2 6 2 Control Register zo seo bebes Pete HERO ERO Re aU Q r VI 3 6 2 Registers P VI 3 6 2 2 Power Supply Voltage Detection Control 1 V
68. Interrupt 3 LV1 0 11 uem y C nes D IM1 0 00 Main program PSW IM1 0 11 PSW MIE 1 Interrupt 1 occurs Accepted because LV1 0 lt IM1 0 and MIE 1 LV1 0 00 Interrupt acceptance cycle IM1 0 00 Interrupt handler 1 When MIESET is 0 MIE is set to 0 n When MIESET is 1 MIE is set to 1 lt Interrupt 2 occurs LV1 0 10 RTI 1 1 0 1 1 Interrupt acceptance cycle IM1 0 10 When MIESET is 0 MIE is set to 0 When MIESET is 1 MIE is set to 1 Interrupt handler 2 ii o 11 x TI Interrupt 3 generated z Not accepted because LV1 0 IM1 0 LV1 0 11 Y Parentheses indicates hardware processing 1 Interrupt 2 is not accepted because LV1 0 10 gt PSW IM1 0 00 2 After the RTI execution of Interrupt 1 Interrupt 2 is accepted because LV1 0 10 lt PSW IM1 0 11 Figure 3 1 6 Processing Sequence for Maskable Interrupts Overview 11 Chapter 3 Interrupts m Multiple maskable interrupt control When MEMCTR MIESET 15 0 and an interrupt is accepted PSW MIE is set to 0 and the multiple maskable interrupt is not occurred To enable the multiple interrupts occurrence set MEMCTR MIESET to 1 by software before accepting inter rupts or set PSW MIE to 1 by software in the interrupt handler a Do not write access to xICR of maskable interrupts when PSW
69. KEYIEN KEYSEL TMIOEN0 TM1MD TMIOSEL0 Bit name SEGSL14 KEY1SEL 1 TM1CK1 0 TM1IOSEL 1 SEG14 1 1 0 Other than 11 a KEY1B 1 Other than 11 0 TM1IO output 5 0 11 0 TM1IO input Other than 11 P55 VII 50 Port 5 Chapter 7 I O Port Table 7 9 8 P56 Function Selection Setup Function Register LCCTR2 KEYIEN KEYSEL TMIOEN0 TM3MD TMIOSEL0 Bit name SEGSL13 KEYI2EN KEY2SEL TM3OEN TM3CK1 0 TM3IOSEL 1 SEG13 1 1 0 Other than 11 KEY2B 1 Other than 11 0 TMSIO output 0 1 11 0 TMSIO input Other than 11 P56 Table 7 9 9 P57 Function Selection Setup Function Register LCCTR2 KEYIEN KEYSEL TMIOEN1 TM8MD1 TMIOSEL1 CLKOUT Bit name TM8IOSEL CLKOEN SEGSL12 KEYISEN KEYSSEL TM8OEN TM8CK1 0 1 0 CLKOSEL 1 0 SEG12 1 1 0 1 Other than 00 0 TMBIO output 0 10 0 10 00 0 TMBIO input 0 Other than 1 1 CLKOUTB 10 0 57 Port 5 VII 51 Chapter 7 Port 7 10 Port 6 The following table shows the special functions of Port 6 Table 7 10 1 Port 6 pin Special function P60 SEG11 IRQ0B P61 SEG10 IRQ1B P62 IRQ2B P63 SEG8 IRQ3B P64 SEG7 KEY4B SBIOA RXDOA P65 SEG6 KEY5B
70. KEYSEL2 KEY2 pin selection 0 KEY2A P12 1 KEY2B P56 KEYSEL1 KEY1 pin selection 0 KEY1A P11 1 KEY1B P55 KEYSELO KEYO pin selection 0 KEYOA P10 1 KEYOB P54 External Interrupts III 43 Chapter 3 Interrupts W KEY Interrupt Input Control Register KEYIEN bp 7 6 5 4 3 2 1 0 Bit name KEY7EN KEY6EN KEY4EN 2 KEY1EN KEYOEN At reset 0 0 0 0 0 0 0 0 Access Bit name KEY7EN KEY7 input enable control 0 Disable 1 Enable KEY7A KEY7B Description KEY6EN KEY6 input enable control 0 Disable 1 Enable KEY6A KEY6B KEY5 input enable control 0 Disable 1 Enable KEY5A KEY5B KEY4EN KEY4 input enable control 0 Disable 1 Enable KEY4A KEY4B KEY3EN KEYS input enable control 0 Disable 1 Enable KEY3A KEY3B 2 2 input enable control 0 Disable 1 Enable KEY2A KEY2B KEY1EN KEY1 input enable control 0 Disable 1 Enable KEY1A KEY1B III 44 External Interrupts KEYO input enable control 0 Disable 1 Enable KEYOA KEYOB Chapter 3 Interrupts 3 3 2 Rising Falling edge triggered interrupt Em TI Rising or falling edge interrupt can be selected with IRQOICR IRQ2ICR IRQ4ICR IRQS
71. Operation Multiplies the signed 16 bit value of DWO register by the signed 16 bit value of DW1 lower 16 bit of the result in the DWO register register and store the upper 16 bit of the result 82 bit in the DW1 register and the Bit Changes Size Cycles Codes VF 0 NF Set if the MSB of the result is 1 otherwise set to 0 CF 0 ZF Set if the result is 0 otherwise set to 0 Execution of 16 bit x 16 bit multiplication signed 6 nibbles 4 cycles 0000 0010 0111 0000 0010 0000 1 Store the multiplier to DWO register and the multiplicand to DW register 2 Execute MOV 0x02 0x03F07 Extended calculation macro instruction MULW 3 The value of the signed 16 bit of DWO register is multiplied by the signed 16 bit of DW1 register Then the upper 16 bit of the results 32 bit is stored in DW1 register and the lower 16 bit register is stored in DWO reg Ister This extended calculation instruction is generated by the compiler for MN101L series by a appointing an option mmuldivw When this extended calculation instruction is executed the handy address HA is updated in Y 0x03F07 Extended Calculation Instruction Chapter 2 CPU 2 4 4 DIVWU 32 bit 16 bit division unsigned SSS es DIVWU MOV 0x04 0x03F07 DW1 DW0 DWO DW1 Operation Divides the unsigned 32 bit value which is stored in the DW1 register upper 16 bit and DW
72. Port VII 30 7 2 12 Analog input Control Register 0 Port1 Analog input control register selects the pin function General IO GIO or A D input W Analog Input Control Register 0 Port 1 ANENO 0x03F5C dew prede sime Bit name ANENO7 0 At reset 0 0 0 0 0 0 0 0 m mme Select the pin function GIO or A D input 7 0 07 0 0 GIO 1 A D input Control Registers Chapter 7 I O Port 7 2 13 Analog input Control Register 1 Port8 Analog input control register 1 selects the pin function General IO GIO or Analog input m Analog Input Control Register 1 ANEN1 0x03F5D Bit name ANEN15 ANEN14 ANEN13 ANEN12 ANEN11 ANEN10 At reset 0 0 0 0 dese LO T Bit name Description Always read as 0 Select the pin function GIO or Analog input ANEN15 0 GIO P85 1 VLC2 Select the function GIO Analog input ANEN14 0 GIO P84 1 VLC3 Select the pin function GIO or Analog input ANEN13 0 GIO P83 1 C2 Select the pin function GIO or Analog input ANEN12 0 GIO P82 1 C1 Select the pin function GIO or Analog input ANEN11 0 GIO P81 1 OSC2 Select the pin function GIO or Analog input ANEN10 0 GIO P80 1 OSC1 Control Registers VII 31 Chapter 7 I O Port VII 32 7 2 14 Buzzer output Buzzer output pin control Register Buzzer output Buzzer output pin
73. Port 1 Input Register OxO3F21 Bit name At reset VII 8 Access me mmm ER Input data 7 0 7 0 0 Input Low Vss level 1 Input High Vpp3o level Control Registers Chapter 7 I O Port m Port 2 Input Register P2IN 0x03F22 Bit name At reset Access e sm Input data 7 0 P2IN7 0 0 Input Low Vss level 1 Input High Vppao level Port 3 Input Register OxO3F23 Bit name At reset Access m mme Input data 7 0 P3IN7 0 0 Input Low Vss level 1 Input High Vpp3o level m Port 4 Input Register P4IN 0x03F24 Bit name At reset Access e mmm mmn Input data 7 0 P4IN7 0 0 Input Low Vss level 1 Input High Vppao level Control Registers VII 9 Chapter 7 I O Port 5 Input Register P5IN 0x03F25 Bit name At reset Access me mmm mmmn Input data 7 0 P5IN7 0 0 Input Low Vss level 1 Input High Vppao level Port 6 Input Register OxO3F26 Bit name At reset Access m mme Input data 7 0 P6IN7 0 0 Input Low Vg level 1 Input High Vppao level m Port 7 Input Register P7IN OxO3F27
74. an interrupt request TMnIRQ is generated at the next count clock The source of TMnIRQ can be selected by TMnMD2 TMnIRSI 16 bit timer can generate another independent interrupt request TMnOC2IRQ depending on the setting value of TMnOC2 TMnMD2 TMnBCR can select the factor of which TMnBC is cleared to 0x0000 TMnBC is cleared and restarts counting up again When TMnBC is cleared 0 0000 the value of timer n preset register is loaded to timer n compare register The value of the compare register with double buffer structure can be changed continuously without disturbing the cycle even during the timer operation TMnIC with a software function When using the MOVW instruction indeterminate data during counting may be read So read the register value several times and confirm those data are identical When using the capture function writing to TMnIC can capture the count value of TMnBC to the TMnIC to read the count value during counting precisely For more information refer to 9 8 1 Operation a When reading the value of TMnBC use a 16 bit access instruction MOVW or write data to If the count clock is changed during counting the counter can t count up correctly Change the count clock after the timer operation is stopped Q lt Set Timer n mode register while the TMnMD1 TMnEN is set to 0 to stop counting change CPU operation mode NORMAL to SLOW when high speed oscillation cl
75. lt abs 18 6 15 0 gt 7 0 15 8 gt memB SP 1 7 memB8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 7 bp19 16 mem8 SP 2 bp3 0 abs18 label H PC JSR label SP 3 SP PC 9 bp7 0 mem8 SP max 3 i 5 2d 000 bbbH lt abs 20 6 15 0 gt PC 9 bp15 8 mem8 SP 1 PC 9 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 9 bp19 16 mem8 SP 2 bp3 0 abs20 label H PC 1 d7 sign extention 2 d11 sign extention 3 notbranch branch 4 912 sign extention 5 416 sign extention 6 aa abs18 17 16 7 B abs20 19 8 bbb abs20 18 16 Instruction set 9 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Mnemonic JSRV 04 NOP Instruction NOP NOP Control Instructions REP imm3 Operation SP 3 SP PC 3 bp7 0 memB SP PC 3 bp15 8 gt mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 3 0 19 16 mem8 SP 2 bp3 0 mem8 x 04080 tbl4 lt lt 2 PC bp7 0 mem8 x 04080 tbl4 lt lt 2 1 gt 5 15 8 8 040805 lt lt 2 2 5 7 gt mem8 x 04080 tbl4 lt lt 2 2 bp3 0 gt PC bp19 16 mem8 SP PC bp7 0 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 PC H mem8 SP 2 bp3 0 PC bp19 16 SP 3 SP mem8 SP gt PSW mem8 SP 1 PC bp7 0 mem8 SP 2 gt PC bp15 8 mem8 SP 3 bp7 PC H mem8 SP 3 p3
76. stop bit In consecutive data reception SCnSTR SCnRBSY is held at 0 for the period from a stop bit to the next start bit Full duplex UART Communication Chapter 13 Serial Interface m Data Storage to TXBUFn In MSB first mode write transmission data to TXBUFn in order from the upper bit For example when transmitting 7 bit data write data to TXBUFn from bp7 to bpl as shown in Figure 13 4 2 Each bit from A to G is transmitted in the order from G to A In LSB first mode write transmission data to TXBUFn in order from the lower bit For example when transmitting 7 bit data write data to TXBUFn as shown Figure 13 4 3 Each bit from A to G is transmitted in the order from A to G 7 6 5 4 3 2 1 0 G F E D C B A Figure 13 4 2 Transmission Data Storage MSB first TXBUFn G F E D C B A Figure 13 4 3 Transmission Data Storage LSB first m Data Storage to RXBUFn In MSB first mode reception data are stored in RXBUFn in order from the upper bit For example when receiving 7 bit data each bit from A to G A is the first reception bit is stored in RXBUFn from bp7 to as shown Figure 13 4 4 In LSB first mode reception data are stored in RXBUFn in order from the lower bit For example when receiving 7 bit data each bit from A to G A is the first reception bit is stored in RXBUFn from bp0 to bp as shown in Figure 13 4 5 RXBUFn A B C D E F G Figur
77. 0 0 Highest NMI 0 1 Higher NMI level 0 1 1 0 Lower NMI level 0 to 1 1 1 Lowest level 0 to 2 W Bank Function Control When BKD is set to 1 bank function is not valid and data access area is limited within the address of 0x00000 to OxOFFFF At the interrupt occurrence bit is set to 1 and the bank function is invalid When returning from the above interrupt procedure the set value of BKD is returned to the one which is set before the interrupt occurrence To enable the bank function in an interrupt service routine set the BKD to 0 before access Y ing to data If xxxICR is written when PSW MIE is 1 there s no guarantee of proper operation 1 Before setting the interrupt control register XxxICR set PSW MIE to Overview Chapter 2 CPU 2 1 7 Address Space Figure 2 1 5 shows the address space in CPU The CPU has 12 KB of RAM area Max and 112 KB of ROM area Max This LSI has 4 KB of RAM and 64 KB of ROM The instruction access can be used as linear address space except Special function register space The data access needs bank specification in every 64 KB The initial value 15 first 64 KB space 0x00000 to The data area consists of an area of 256 bytes beginning at 0x00000 that supports efficient accesses with RAM short addressing and an special function area of 256 bytes beginning at 0x03F00 that supports efficient accesses
78. 11 0 P05 1 When the LSI is the master of Clock synchronous communication or communicates on IIC bus set the PODIR PODIRS5 to 1 Table 7 4 8 Function Selection Setup Function Register SC3MD1 SC23SEL TMIOEN1 TM8MD1 TMIOSEL1 SC3SBIS SC3IOM SC3SELO TM8CK1 0 E 1 0 0 0 ormer nan SBI3A 10 1 ara 01 TMBIO output 0 0 10 01 TM8IO input 0 Other than 10 Table 7 4 9 P07 Function Selection Setup Function Register SC3MD2 SC23SEL TMIOEN1 TM9MD1 TMIOSEL1 Bit name Tm SC3SEL3 TM9OEN TM9CK1 0 aa 1 1 0 _ SBCS3A and 00 TM9IO output 0 10 00 TMSIO input Other than 10 P07 VII 36 1 When the LSI outputs the chip select signal set the PODIR PODIR7 to 1 Port 0 75 Port 1 The following table shows the special functions of Port 1 7 5 1 Table 7 5 1 Port 1 Pin Special function P10 AN0 IRQ0A KEY0A P11 AN1 IRQ1A KEY1A P12 AN2 IRQ4C KEY2A P13 AN3 IRQ5C KEY3A P14 AN4 IRQ4A KEY4A P15 5 IRQ5A KEY5A P16 AN6 IRQ6A KEY6A P17 AN7 KEY7A Setup of Port 1 Table 7 5 2 P10 Function Selection Setup Function Register ANEN0 IRQIEN IRQISELO KEYIEN KEYSEL Bit name ANENOO IRQIOEN IRQOSEL KEYIOEN KEYOSEL 1 AN0 1 0 0 IRQ0A 0 1 0 KEY0A i 0 P10 Table 7 5 3 P11 Function Selection Setup Function Regi
79. A Once the IGBT trigger is input the IGBT operation is valid at the next clock After the IGBT operation becomes valid the IGBT output holds Low until the next count clock B While the IGBT trigger is valid and the binary counter counts up from 0x0000 to the TM7OC2 compare match the IGBT output is High Only for the 181 cycle of counting the output is High from 0x0001 C After the TM7OC2 compare match the output changes to Low The binary counter continues counting up until it is cleared by the TM7OCI compare match D When the binary is cleared the IGBT output returns to High E When the IGBT trigger becomes invalid the timer is initialized and the IGBT output is forced to be Low 16 bit High Precision IGBT Output with Variable Period Duty IX 53 Chapter 9 16 bit Timer IX 54 W Count timing of High Precision IGBT Output when compare register 2 0x0000 Timer 7 wo clock I J i TM7EN bit Compare i N register 1 H i H i i x 0000 register 2 i i i IGBT trigger em Cer s TM71O output IGBT output TM8IO output IGBT output Figure 9 10 2 Count timing of High Precision IGBT Output when compare register 2 0x0000 When the timer is not operating by setting the TM7MD1 TM7EN to 0 outputs from both TM7IO and TM8IO are Low gm Count tim
80. I O Port m Port6 Pull up Resistor Control Register 0x03F46 Bit name At reset Access e mmm Pull up resistor selection 7 0 P6PLU7 0 0 Not added 1 Added Port 7 Pull up Resistor Control Register P7PLUP 0x03F47 Bit name At reset Access m mme Pull up resistor selection 7 0 P7PLU7 0 0 Not added 1 Added m Port 8 Pull up Resistor Control Register P8PLUP 0x03F48 Bit name At reset Access Always read as 0 Pull up resistor selection 0 Not added 1 Added Control Registers VII 17 Chapter 7 Port VII 18 7 2 5 Port n N ch Open drain Control Registers PnODC is the register to control N ch open drain control of I O m Port 0 N ch Open drain Control Register POODC 0x03F50 Bit name POODC7 At reset 5 w T 9 se s Tn Tn POODC7 N ch open drain output selection 0 Push pull output 1 N ch open drain output Always read as 0 POODC5 4 Bit name N ch open drain output selection 0 Push pull output 1 N ch open drain output At reset Access Always read as 0 POODC5 N ch open drain output selection 0 Push pull output 1 N ch open drain output Control Registers Always read as 0 Chapter 7 I O Port W Port 2 N ch Open
81. IRQNWDG is not cleared by hardware Before RTI instruction is executed in the NMI inter Y rupt handler they must be cleared 22 Control Registers Chapter 3 Interrupts 3 2 2 External Interrupt Control Register isuwa ua Dw aUII W External Interrupt 0 to 6 Control Register IRQnICR n 0 1 2 3 4 5 6 bp 3 Bit name Reserved At reset Access Bit name Description Interrupt level Set interrupt level from 0 to 3 Interrupt trigger edge 0 Falling edge 1 Rising edge Always read as 0 Reserved Must be set to 0 Always read as 0 Interrupt enable control 0 Disable 1 Enable Interrupt request detection 0 Not detected 1 Detected bp 3 Bit name Reserved At reset 0 Access Bit name Description Interrupt level Set interrupt level from 0 to 3 Always read as 0 Reserved Must be set to 0 Always read as 0 Interrupt enable control 0 Disable 1 Enable Interrupt request detection 0 Not detected 1 Detected Control Registers III 23 Chapter 3 Interrupts 3 2 3 Peripheral Group Interrupt Control Register rS Group 0 Group 1 Interrupt Level Control Register PERIOICR PERI1ICR bp 7 6 5 4 3 2 1 0 Bit name LV1 LVO Reserved 0 0 0 0 0 0 0 0 At reset Access R W R W R R R W R R R
82. In this situation the frequency of OSCSTBCLK is equal to half the of SCLK After the oscillation stabilization the CPU enters the SLOW mode OSCSTBCLK is described in the Fig 4 1 1 Reset Chapter 2 CPU Oscillation Stabilization Wait Time Control Register DLYCTR 0x03F03 Bit name At reset Access Bit name Description Always read as 0 Oscillation stabilization wait cycle selection 0000 2 x 1 fogcsTBCLK 0001 213 x 1 foscstecik 0010 212 x 1 lt 0011 2 x 1 foscsTBcLk 0100 210 x 1 0101 29 x 1 0110 28 x 1 0111 2 x 1 foscstBcLK 1000 2 x 1 fogcsTBCLK 25 x 24 x 23 Q foscsTBCLK gt gt 1001 Q 1 foscsTBcLkK 1010 1 fOSCSTBCLK 1011 1 fOSCSTBCLK 1100 22 x 1 foscsTBcLK 1101 Prohibited 1110 Prohibited 1111 Prohibited Qe lt stabilization wait cycle of external oscillation should be determined in consultation with 1 the manufacturer Internal high speed oscillation 15 us or more 1 Set the stabilization wait cycle of internal oscillation to match the following conditions Internal low speed oscillation 100 us more Reset 1 31 Chapter 2 CPU 32 Reset Chapter 3 Interrupts Chapter 3 Interrupts III 2 3 1 Overview The LSI provides vectored interrupt services consisti
83. Interrupt source PERIOIRQ2 PERIOIRQ1 HCLK SCLK SYSCLK HER HCLK 2 41 Clock source SCLK 1 HCLK 2 3 71 SCLK 2 2 SCLK 2 3 2 Interrupt generation cycle 27 x 1 28 x 1 ficuK 29 x 1 210 x 212 x 1 213 x 1 1 214 x 213 x 1 fucLK 2 x 1 28 x 1 29 x 1 fscLk 219 x 1 fscLk 212 x 1 21 21 x 1 215 x 1 The interrupt generation cycle is decided by the arbitrary value written to TM6OC HCLK machine clock high speed oscillation SCLK machine clock low speed oscillation SYSCLK system clock Chapter 4 4 1 Clock Control 1 It is available when HCLK is selected as a clock source of time base timer 2 It is available when SCLK is selected as a clock source of time base timer X 2 Overview Chapter 10 General Purpose Time Base Free Running Timer 10 1 2 Block Diagram W Timer 6 Time Base Timer Block Diagram eseq 4 J Naal Naona LOuIOIH3d ISH O89WL Jejunoo 16 8 OO9NL JejsiBoJ 110 9 9 JOU ATOS HTOEL 1 258709 TESAL EO9WI zaon DIO9WI
84. Key Code Setting Set key code 128 bits and activate Security Function Security_Key_Check_Lib Ox6F21A Key Code Authentication Authenticate the key code 128 bits and deactivate Security Function temporarily Byte_Suspend_Lib Ox6F225 Programming Byte Data in Data Area The data in specified address is programmed When programming is not complete in a given time the programming is suspended Word Suspend Lib Ox6F22A Programming Word 2 Byte Data in Data Area The data in specified address is programmed When programing is not complete in a given time the programming is suspended a When a command library is subroutine called in an interrupt process during execution of another command library double activation error occurs Command Library XVIII 7 Chapter 18 ReRAM 8 Library Chapter 19 On Board Debugger Chapter 19 On Board Debugger 19 1 Overview The LSI has an on board chip debugger OCD for program development and data writing to OCD is used with the external debug unit PanaX EX It is unnecessary to implement the monitor program in user program area Refer to the following URL for the details of the on board debugging http www semicon panasonic co jp e micom onboard panax_ex html When LSI is connected to PanaX EX VDD18 is always set to 1 8V even when the 1 1V or 1 1 3V is set by software XIX
85. RXBUF1 RXBUF2 RXBUF3 Bit name RXBUFn7 RXBUFn6 RXBUFn5 RXBUFn4 RXBUFn3 RXBUFn2 RXBUFn1 RXBUFnO Initial X X x X X X X X value Access R R R R R R R R 5 Bmw we _ RXBUFn7 0 Received data is stored 13 24 Transmit Data Buffer SCIFn n 0 1 2 3 Transmission Data Buffer TXBUFO TXBUF1 TXBUF2 TXBUF3 EE ML Lm pg X X X X X X X X Initial value Access 5 Bam ton _____ TXBUFn7 0 Set the data to be transmitted XIII 10 Control Registers Chapter 13 Serial Interface 13 2 5 Mode Register SCIFn 0 1 Mode Register 0 SCOMDO SC1MDO name SCnCE1 Reserved SCnCTM SCnDIR Reserved Reserved Reserved Reserved Initial value 0 0 0 0 0 1 1 1 Access Bit name Description Clock polarity selection 1 0 Initial value High 1 Initial value Low Reserved Always set to 0 Communication mode selection SCnCTM 0 Single byte communication 1 Consecutive byte communication Transfer bit selection 4 SCnDIR 0 MSB first 1 LSB first 3 0 Reserved Always set 0111 Control Registers XIII 11 Chapter 13 Serial Interface m SCIFn 2 3 Mode Register 0 SC2MD0 SC3MD0 Bit name IICSDEM IIC3DIR IICSSTE Reserved Reserved Reserved Initial value 0 0 0 1 1 1 Access
86. SCLK 16 16bit Capture Register TMnICH TMnICL 16bit Preset Register TMnPR1H TMnPR1L 16bit Compaer Register TMnOC1H TMnOC1L Match detection 16bit Bynary Counter TMnBCH TMnBCL Match detection 16bit Compare Register2 TMnOC2H 21 16bit Preset Register TMnPR2H TMnPR2L 8bit Dead time Counter 1 Match detection 8bit Dead time Compare Register 1 8bit Dead time Preset Register1 1 TM7DPR1 8bit Dead time Preset Register2 1 TM7DPR2 TMnIRQ Timer PWM output generation IGBT output generation 1 TMnIO gt TMnOC2IRQ 1 Function of Timer 7 only Figure 9 1 1 16 bit Timer n Block Diagram n 7 8 and 9 Overview Chapter 9 16 bit Timer IX 3 Chapter 9 16 bit Timer 9 2 16 bit Timer Control Registers Table 9 2 1 shows the registers that control 16 bit timer Table 9 2 1 16 bit Timer Control Registers Symbol Address R W Register Name Page TM7BCL 0x03FA0 R Timer 7 binary counter lower 8 bits TM7BCH OxOSFA1 R Timer 7 binary counter upper 8 bits TM7OC1L 0x03FA2 Timer 7 compare register 1 lower 8 bits TM7OC1H 0x03FA3 Timer 7 compare register 1 upper 8 bits TM7PR1L 0x03FA4 Timer 7 preset register 1 lower 8 bits TM7PR1H 0x03FA5 Timer 7 preset register 1 upper 8 bits TM7ICL Ox03FA6 Timer 7 input capture register lower 8 bits TM7ICH 7 Timer 7 input capture register upper 8 bits T
87. W bit and bit SCnIICSTR IIC3DATA_ERR is set to 1 as judged the serial communication is forced to be terminated When the situation occurs clear IIC3DATA ERR to 0 and restart a communication When the LSI is a master and the above situation occurs the LSI continues communication until single byte is transmitted and SCnTIRQ occurs at the end of byte transmission If the arbitration lost occurs the LSI changes to slave and stop communication When the LSI is a slave and the above situation occurs SCnTIRQ occurs and the LSI stop communication m Arbitration Lost When LSI is a master if transmission data doesn t match SDAn signal level SCnSTR IIC3ABT LST is set and SDAn and SCLn are released as judged it an arbitration lost The arbitration lost detection does not cause SCnTIRQ but if the slave address sent from another master matches the value of SCnAD after an arbitration lost detection SCnTIRQ occurs Confirm LST at the next interrupt timing SCnTIRQ or SCnSIRQ Clear LST by program General Call Communication When a general call is detected SCnIICSTR IIC3ADD and SCnIICSTR IIC3GCALL are set and send ACK bit The value of SCnIICSTR IIC3GCALL is valid only when SCnTIRQ occurs in the slave address recep tion W Operation of Transmission Data Buffer register TXBUFn and Transmission Data Buffer Empty Flag SCnTEMP TXBUFn is a buffer to store transmission data The data are
88. When RTI instruction executes PSW IM1 0 go back to the value of it before the interrupt acceptance e NMI is accepted PSW IM1 0 change to 00 When MEMCTR MIESET is 1 PSW MIE is set to 1 a When an interrupt is accepted PSW MIE changes as follows 5 When MEMCTR MIESET is 0 PSW MIE is set to 0 NMI has priority over maskable ones Refer to Chapter 20 20 2 Instruction set for BE and BD instructions Overview Interrupt Acceptance Operation hardware processing When an interrupt is accepted the LSI executes the following sequence by hardware 1 Stack Pointer SP is updated SP 6 SP PSW BKD is set to 1 The bank function is disabled MEMCTR MIESET is copied to PSW MIE MEMCTR MIESET PSW MIE LV 1 0 of the accepted interrupt is copied to PSW IM1 0 LV1 0 PSW IMI 0 PSW and PC i e the return address are saved to the stack PSW Address SP PC bit 7 to 0 Address SP 1 The remaining PC is saved to the stack PC bits 15 to 8 Address SP 2 PC bits 19 to 16 and H Address SP 3 is saved to the stack Lower half of HA Address SP 4 Upper half of HA Address SP 5 The hardware branches program to the address in the vector table 7 0 New SP PSW Lower after interrupt to 0 acceptance 15 to 8 Reserved AR Address HA7 to 0 HA15 to 8 Old SP Higher b
89. abs8 bp label if mem8 abs8 bp 1 PC 8 d1 1 label H PC i memB abs8 bp 0 PC48 PC TBNZ io8 bp label if mem8 IOTOP i08 bp 1 4 d 6 d i PC 7 d7 label H PC if mem8 IOTOP i08 bp 0 PC 7 PC TBNZ io8 bp label if mem8 IOTOP i08 bp 1 PC 8 d1 1 label H PC if mem8 IOTOP i08 bp 0 8 PC TBNZ abs16 bp label if memB abs16 bp 1 4 d 6 d i 9 7 i memB abs16 bp 0 9 PC TBNZ abs16 bp label if mem8 abs16 bp 1 PC 10 d1 1 label H i memB abs16 bp 0 PC 10 JMP An 0 PC 19 16 An PC 15 0 0 PC H JMP label abs18 label H PC 3 i abs 18b 5 0 gt JMP label abs20 label H PC 9 4 i 0008 bbbH abs 20 6 JSR SP 3 SP PC 3 bp7 0 8 5 3 max 2 i4 2d PC 3 bp15 8 mem8 SP 1 PC 3 H memB8 SP 2 bp7 0 mem8 SP 2 bp6 4 3 0 19 16 mem8 SP 2 bp3 0 0 PCbp19 16 An PCbp15 0 0 JSR label SP 3 SP PC 5 bp7 0 mem8 SP max 2 i 4 2d PC 5 bp15 8 mem8 SP 1 5 mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 5 bp19 16 mem8 SP 2 bp3 0 PC 5 d12 label H PC JSR label SP 3 SP PC 6 bp7 0 8 5 max 2 i 4 2d 6 5 15 8 mem8 SP 1 PC 6 H memB8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 6 bp19 16 mem8 SP 2 bp3 0 PC 6 d16 label H PC JSR label SP 3 SP PC 7 bp7 0 mem8 SP max 2 i 4 2d
90. ated and output from TMnIO pin 16 bit High Precision PWM Output Operation PWM waveform with a given period and duty cycle is generated by setting to the PWM period and set ting TMnOC2 to High period of the PWM duty W Count Timing of High Precision PWM Output at Normal TMnEN bit Compare register 1 Compare register 2 je 8 counter TMnIO output PWM output A Count time 8 Compare registser 2 setting value 1 PWM basic waveform Count time Compare registser 1 setting value 1 Figure 9 7 1 Count Timing of High Precision PWM Output at Normal PWM output waveform A PWM output is High while the binary counter counts up from 0x0000 to the setting value of the com pare register 2 PWM output changes to Low when the binary counter matches the setting value of the compare register 2 then the binary counter continues counting up until the binary counter is cleared by the com pare match C PWM output returns to High when the binary counter is cleared 16 bit High Precision PWM Output with Continuously Variable Period Duty IX 35 Chapter 9 16 bit Timer IX 36 W Count Timing of High Precision PWM Output when compare register 2 is set to 0x0000 Count clock TMnEN bit Compare register 1 Compare register 2 Binary 0000 nt N 0000
91. imm8 PC 9 PC CBNE imm8 abs8 label if mem8 abs8 zimms8 PC 10 d1 1 label H if mem8 abs8 imm8 10 CBNE imm8 26516 label if mem8 abs16 4imms PC 114 d7 label H PC if mem8 abs16 imms 11 PC CBNE imm8 abs16 label if mem8 abs16 zimm8 PC 12 d11 label H if mem8 abs16 imm8 12 8 TBZ abs8 bp label if mem8 abs8 bp 0 PC 7 d7 label H PC if mem8 abs8 bp 1 7 PC TBZ abs8 bp label if mem8 abs8 bp 0 PC 8 d1 1 label H PC if mem8 abs8 bp 1 8 PC TBZ i08 bp label if mem8 IOTOP i08 bp 0 PC 7 47 label H PC if mem8 IOTOP Hio8 bp 1 PC 7 PC TBZ i08 bp label Instruction set 0 8 411 PC iftmem8 IOTOP io8 bp 1 8 PC 1 d4 sign extention 2 d7 sign extention 3 11 sign extention 4 not taken taken Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Execution Machine Code Cycle 5 6 Mnemonic Operation TBZ abs16 bp label if memB abs16 bp 0 4 d 6 d i 9 7 PC i memB abs16 bp 1 9 PC TBZ abs16 bp label if memB abs16 bp 0 PC 10 d11 label H i memB abs16 bp 1 10 TBNZ abs8 bp label if memB abs8 bp 1 4 d 6 d i PC 7 d7 label H PC i memB abs8 bp 0 PC 7 PC TBNZ
92. lt XIII 8 Control Registers 13 2 2 Chapter 13 Serial Interface Input Output Pin Control Register SCIF011IO Pin Switching Control Register SCO1SEL Bit name SC1SEL3 SC1SEL2 SC1SEL1 SC1SELO SCOSEL3 SCOSEL2 SCOSEL1 SCOSELO Initial value 0 0 0 0 0 0 0 0 Access bp Bit name Description SC1SEL3 0 SCOSEL3 0 SCIF1 pin group selection 0000 SBCS1A SBT1A SBO1A TXD1A SBI1 A RXD1A 1111 SBCS1B SBT1B SBO1B TXD1B SBI1B RXD1B Setting other value is prohibited SCIFO pin group selection 0000 SBCSOA SBTOA SBOOA TXDOA SBIOA RXDOA 1111 SBCSOB SBTOB SBOOB TXDOB SBIOB RXDOB Setting other value is prohibited SCIF23 I O Pin Switching Control Register SC23SEL Bit name SC3SEL3 SC3SEL2 SC3SEL1 SC3SELO SC2SEL3 SC2SEL2 SC2SEL1 SC2SELO Initial value 0 0 0 0 0 0 0 0 Access bp Bit name Description SCIF3 pin group selection 0000 SBCS3A SBT3A SCL3A SBO3A SDA3A SBI3A i SC3SEL3 0 4411 SBCS3B SBT3B SCL3B SBO3B SDA3B SBI3B Setting other value is prohibited SCIF2 pin group selection 3 0 SC2SEL3 0 0000 SBCS2A SBT2A SCL2A SBO2A SDA2A SBI2A 1111 SBCS2B SBT2B SCL2B SBO2B SDA2B SBI2B Setting other value is prohibited Control Registers XIII 9 Chapter 13 Serial Interface 13 2 3 Receive Data Buffer m SCIFn 0 1 2 3 Reception Data Buffer RXBUFO
93. mem8 IOTOP io8 0000 0010 MOV imm8 abs8 imm8 mem8 abs8 0001 0100 MOV imm8 abs12 imm8 mem8 abs12 0001 0101 MOV imm8 abs16 imm8 mem8 abs16 1101 1001 MOV Dn HA Dn mem8 HA 1101 00Dn MOVW DWm mem16 An gt DWm 1110 00 MOVW An Am mem16 An gt 1110 10Aa MOVW d4 SP DWm mem16 d4 SP gt DWm 1110 011d MOVW d4 SP Am mem16 d4 SP gt 1110 010a MOVW 88 5 DWm mem16 d8 SP gt DWm 1110 011d MOVW d8 SP Am mem16 d8 SP gt Am 1110 010a mem16 d16 SP gt DWm 1110 001d MOVW d16 SP Am mem16 d16 SP gt Am 1110 000a MOVW abs8 DWm mem16 abs8 DWm 1100 011 MOVW abs8 Am mem16 abs8 gt Am 1100 010a MOVW d16 SP DWm abs8 MOVW abs16 DWm mem16 abs16 gt DWm 1100 011 MOVW 16 Am mem16 abs16 1100 010a MOVW DWn Am DWn mem16 Am 1111 00 MOVW Am mem16 Am 1111 10 MOVW DWn d4 SP DWn mem16 d4 SP 1111 0110 MOVW An d4 SP An mem16 d4 SP 1111 010A MOVW DWn 98 5 DWn mem16 d8 SP 1111 0110 An d8 SP 16 98 5 1111 010 MOVW DWn d16 SP DWn mem16 d16 SP 1111 0010 MOVW d16 SP An mem16 d16
94. resistor is not connected P63 SEG8 IRQ3B Input Yes The drive strength of output Nch transistor can be P64 SEG7 KEY4B SBIOA RXDOA Output Yes changed P65 SEG6 KEY5B SBO0A TXD0A Yes P66 SEG5 KEY6B SBTOA Yes P67 SEG4 KEY7B SBCS0A Yes P70 COM7 SEG3 IRQ6B Yes Port 7 At each port the direction and the pull up resistor P71 COM6 SEG2 IRQ5B Yes connection is controlled individually P72 COM5 SEG1 IRQ4B TM3IOB Yes At LSI reset each pin is set to input mode and the pull up resistor is not connected P73 COM4 SEGO TMSIOB Input Yes The drive strength of output Nch transistor can be P74 COM3 Output Yes changed P75 COM2 Yes P76 COM1 Yes P77 COMO Yes P80 OSC1 IRQ2A No Port 8 At each port the I O direction and the pull up resistor P81 5 2 connection is controlled individually At LSI reset each pin is set to input mode and the pull up P82 C1 Input No p resistor is not connected P83 C2 Output No P84 VLC3 No P85 VLC2 No Pin Description 1 17 Chapter 1 Overview Table 1 3 3 Special Function Pin Pin name ase Description SBIOA RXDOA Input Serial data input pins SBIOB RXDOB Pull up resistor can be added by setting PnPLUP SBI1A RXD1A Select the input mode by setting PnDIR SBI1B RXD1B Select the serial data input by setting SCnMD1 SCnSBIS n 0 1 2 3 SBI2A SBI2B SBI3A SBI3B SBOOA TXDOA Input Serial data I O pins SBOOB
95. rte d ee ed Oe Ionen eret ing XVI 10 16 3 2 Setup Procedure entere ete dee XVI 12 16 3 3 Cautions een Ue EE EUIS XVI 13 Chapter POPE D 1 ette cet e e ka Buih unai au iu busua ets XVII 2 17 1 1 LCD Driver Circuit Block Diagram XVII 3 17 2 Control R gistets napa aaa err eerie bete 4 17 2 1 LCD Mode Control 1 amp XVII 5 17 2 2 EC D Port Control deiner ertet XVII 9 I A3 Operation ee odo Et ute E ti Opa EU n eae D Rp Une XVII 17 17 31 LEDDRYV Operation 17 17 3 2 Voltage Booster Circuit XVII 18 17 3 3 Reference Voltage Circuit REFVOL eese ener enne nnne XVII 18 17 3 4 LCD Drive Voltage Selection sees XVII 19 17 3 5 LCD Frame Frequency Setup e onere etenim epi p th XVII 24 17 3 6 Setup Examples of REFVOL and BSTVOL eee XVII 25 17 4 E CD Display Examples einer tepore eter 26 17 1 LED Display 5 26 17 4 2 LCD Operation Setup Example Static eee XVII 28 17 4 3 LCD Display Example 1 2 4 essent XVII 29 17 4 4 LCD Operation Setup
96. 0 as you like IRQ0ICR IR should be set to 0 4 Enable IRQ0 IRQ0ICR Set the IRQOICR IE to 1 must be changed when IRQnICR IE is 0 After the interrupt edge is changed IRQnICR IR 1 Interrupt edge rising edge falling edge or both edges rising edge and falling edge of IRQn must be cleared before setting IRQnICR IE is 1 External Interrupts Chapter 3 Interrupts 3 3 4 Key Interrupt Ea u am SVMr s Key interrupt KEYIRQn pin can be selected with the KEYIEN and KEYSEL is generated when one of the KEYIRQ pins goes from High to Low Setting example of KEYIRQ The following example shows how to use P10 P11 P12 and P13 as KEYIRQ pins and generate IRQ7 Settings Register Description Set the input direction of P1DIR Set P1DIR P1DIR3 0 to 0000 P10 P11 P12 and P13 Add the pull up resistors P1PLUP Set P1PLUP P1PLU3 0 to 1111 Set P10 P11 P12 and P13 as KEYSEL Set KEYSEL KEYSEL3 0 to 0000 KEYIRQ pins KEYIEN Set KEYIEN KEYENS 0 to 1111 Set the Interrupt level of IRQ7 IRQ7ICR Set IRQ7ICR LV1 0 as you like IRQ7ICR IR should be set to 0 Enable IRQ7 IRQ7ICR Set IRQ7ICR IE to 1 3 3 5 Noise Filter Function Noise Filter NF controlled with NFCTRO1 NFCTR23 NFCTR45 and NFCTR67 is available to eliminate input noise at the external interrupt pins IRQn NF samples the input signal at IRQn and when the input sig
97. 0 is gen erated and the A D conversion is started The ANCTR2 ANST is cleared to 0 automatically after the conversion data is stored Operation XVI 11 Chapter 16 A D Converter ADC 16 3 2 Setup Procedure W Initial setup of A D conversion operation The following flow chart shows the initial setup procedure of A D conversion operation START Analog input pin setting Analog pin function selection ANENO ANENO 1 PnDIR PnDIRm 0 PnPLU PnPLUm 0 PnODC PnODCm 0 Channel selection ANCTR1 ANCHS2 0 ANn A D conversion clock S H time setting ANCTRO ANCK2 0 any ANCTRO0 ANSH1 0 any ANCTRO ANLADE 0 A D resistor ladder ON ANCTRO ANLADE 1 A D converion star factor selection ANCTR2 ANSTSEL1 0 any Figure 16 3 2 Initial setup procedure of A D conversion operation After initial setup the A D conversion is started when the selected A D conversion start factor occurs The conversion completion can be confirmed by monitoring A D conversion interrupt or the ANCTR2 ANST When the conversion is restarted by changing the setting after the A D conversion set the Y ANCTRO ANLADE to 0 to change the setup after stopping an analog circuit Note that operation is not guaranteed if the procedures above are not properly conducted 1 After setting the ANCTR0 ANLADE to 1 and waiting for 12 conversion clocks start A D version XVI 12 Operation
98. 0012 1 interrupt TM1ICR 0x03FEB 12 0x04030 0x00130 Timer 2 interrupt TM2ICR 0 0 13 0 04034 0 00134 3 interrupt 0x03FED 14 0x04038 0x00138 Timer 4 interrupt TM4ICR 15 0x0403G 0x0013C Timer 7 interrupt TM7ICR 16 0 04040 0 00140 7 compare 2 match interrupt TM7OC2ICR 0x03FF0 17 0x04044 0x00144 Timer 8 interrupt TM8ICR 0x03FF1 18 0x04048 0x00148 Timer 8 compare 2 match interrupt TM8OC2ICR 0x03FF2 19 0 0404 0 0014 Timer 9 interrupt TM9ICR Ox03FF3 20 0x04050 0x00150 Timer 9 compare 2 match interrupt TM9OC2ICR 0x03FF4 21 0x04054 0x00154 Serial interface 0 reception interrupt SCORICR Ox03FF5 22 0x04058 0x00158 Serial interface 0 transmission interrupt SCOTICR Ox03FF6 23 0x0405C 0x0015C Serial interface 1 reception interrupt SC1RICR Ox03FF7 24 0x04060 0x00160 Serial interface 1 transmission interrupt SC1TICR OxOSFF8 25 0x04064 0x00164 Serial interface 2 transmission complete interrupt SC2TICR Ox03FF9 26 0x04068 0x00168 Serial interface 2 stop condition interrupt SC2SICR Ox03FFA 27 0x0406C 0 0016 Serial interface transmission complete interrupt SC3TICR 0x03FFB 28 0x04070 0x00170 Serial interface 3 stop condition interrupt SC3SICR 0x03FFG Group 0 interrupt which consists of the following interrupts Timer 5 interrupt Timer 6 interrupt 29 0x04074 0x00174 TBT interrupt PERIOICR 0x03FFD RTC TBT interrupt RTC interrupt RTC Alarm0 interr
99. 01 sseJppe LST 18v oll uLsoliuos uonoelep 1sol Tivobe uondeoeg 1 1041009 u UOI i 1031009 yogjes diu i ulgs ivulas tasuos Tasezos urd 199l s diuo uono l s 195 ejep 1sej snouo1upu S 49019 4OVN PIOV OII uonejeueB dois 84085 3 i 1 uomneJeueb pes 5 1085 lt lt uorssiusueJ lt ivuogs 1198998195295 jndino eyeq 8085405 14 495 88105 84895 yius ius uondeoeu tes 18690 S WiH8 4 1 lt i jos id QW us Wiug aW S Indino W 188 219 005 US WlH8 N3 MIOSAS MTIOSMI1OH pneg 1 5188426 IqIWuOS HH9UDS 0d IUOS SI8SUDS LANUS 0 L0q3U0S cQ oS 0395915 9 49 Od LSEDIEGNUOS ALSEOIOGNUDS 1 Jejjnq uoissiuisuei Jejnq uond 5 H YIGUOS OGWUOS 951 lt gt 95 1 dv
100. 1 SEG29 1550 72 2 1 SBOOB 0 1 1 1 TXD0B 5 0 0 P36 1 When serial data is output set the P3DIR P3DIR6 to 1 2 When serial data is input and output set the bit to 1 Table 7 7 9 P37 Function Selection Setup Function Register LCCTR4 SCOMD1 SCO1SEL Bit name SEGSL28 SCOSBTS SCOSEL2 1 SEG28 1 1 1 SBTOB 0 5 P37 1 When the LSI is the master of Clock synchronous communication set the P3DIR P3DIR7 to 1 Port 3 Chapter 7 I O Port VII 45 Chapter 7 Port 7 8 Port 4 The following table shows the special functions of Port 4 Table 7 8 1 Port 4 pin Special function P40 SEG27 SBCS0B P41 SEG26 SBI2A P42 SEG25 SBO2A SDA2A P43 SEG24 SBT2A SCL2A P44 SEG23 SBCS2A P45 SEG22 SBI1B RXD1B P46 SEG21 SBO1B TXD1B P47 SEG20 SBT1B The assignment and selection of SEGn differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 8 1 Setup of Port 4 Table 7 8 2 P40 Function Selection Setup Function Register LCCTR3 SCOMD3 SC01SEL Bit name SEGSL27 SCOSBCSEN SCOSEL3 1 SEG27 0 101 1 SBCS0B 0 40 1 When the LSI outputs the chip select signal set the P4DIR P4DIRO0 to 1 Table 7 8 3 P41 Function Selection Setup Function Register LCCTR3 SC2MD1 SC23SEL Bit name SEGSL26 SC2SBIS S
101. 1 71 1 SBCS1B 0 E P50 1 When the LSI outputs the chip select signal set the PSDIR P5DIRO to 1 Table 7 9 3 P51 Function Selection Setup Function Register LCCTR2 SC3MD1 SC23SEL Bit name SEGSL18 SC3SBIS 5 SC3SELO 1 5 SEG18 1 0 1 SBI3B 0 0 5 51 Port 5 VII 49 Chapter 7 I O Port Table 7 9 4 P52 Function Selection Setup Function Register LCCTR2 SC3MD1 SC23SEL SEGSL17 SC3SBOS SC3SBIS SC3IOM SC3SEL1 1 SEG17 1 1 72 2 1 SBO3B 0 1 1 1 SDA3B 0 0 52 1 When serial data is output set the P5DIR P5DIR2 to 1 2 When serial data is input and output set the bit to 1 Table 7 9 5 P53 Function Selection Setup Function Register LCCTR2 SC3MD1 SC23SEL SEGSL16 SC3SBTS SC3SEL2 1 SEG16 1 1 1 SBT3B SCL3B 0 0 P53 1 When the LSI is the master of Clock synchronous communication set the PSDIR P5DIR3 to 1 Table 7 9 6 P54 Function Selection Setup Function Register LCCTR2 KEYIEN KEYSEL SC3MD2 SC23SEL SEGSL15 KEYIOEN KEYOSEL e SC3SEL3 1 s 5 5 SEG15 1 1 0 KEYOB 0 101 1 SBCS3B 0 P54 1 When the LSI outputs the chip select signal set the P5DIR P5DIR4 to 1 Table 7 9 7 P55 Function Selection Setup Function Register LCCTR2
102. 10 General Purpose Time Base Free Running Timer lt Stop the timer when switching the count clock If the count clock is changed during counting the timer doesn t count correctly When the timer 6 binary counter TM6BC is read the operation uncertain value on count ing up may be read Writing the value to the timer 6 compare register TM6OC during counting is prohibited The sampled signal of the TM6EN TBEN bit with the count clock controls start stop of the binary counter of the timer 6 and the time base timer this LSI Therefore note the follow ing two points To read the binary counter value after the timer has stopped set the TM6EN bit to wait for 1 count cycle and read the value When reading the value without waiting for 1 count cycle use the program to read the value of the binary counter multiple times In this case the read value is count value 1 II When changing the timer setting clock selection function switching etc wait for 1 count clock after setting the TM6EN TBEN bit to 0 to stop the timer Then Restart the timer If the setting is switched during the timer operation the timer operation is not guaranteed When the binary counter reaches the setting value of the compare register the interrupt request is set and the binary counter is cleared at the next count clock So set the compare register as follows the value of compar
103. 2 Set the operation mode to 1 3 duty driving 3 Select HCLK 215 as an LCD clock source 4 Select SEGO 5 and COMO 2 pins 5 Set the display data 23 on the segment output latch 6 Start the LCD XVII 34 LCD Display Examples Chapter 17 LCD 17 4 7 Display Example 1 4 duty 1 4 duty Segment Latch 0x03E93 0x03E92 0x03E91 0x03E90 A electrode B electrode OFF LCDPANEL LCD ON S N COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock Undefined Data 1 0 Undefined COM Vict Vice Vica Vss Vict Vics Vss SEG COM SEG 1 3VLco 0 1 3 M ON OFF OFF OFF OFF S selected voltage N non selected voltage Vico LCD driving voltage LCD Display Examples XVII 35 Chapter 17 LCD Frame period COM3 COM2 COM1 COMO SEG3 data A electrode COM3 SEG3 B electrode COM1 SEG3 Figure 17 4 4 LCD display example in 1 4 duty XVII 36 LCD Display Examples 17 4 8 LCD Operation Setup 1 4 duty B ss LCD Operation Setup Example 1 4 duty The following example is to display 23 on a 8 segment type LCD panel two digits through segment pins SEGO to SE
104. 2 cycles dead time is one count longer than the normal IGBT Output with Dead Time Chapter 9 16 bit Timer W Count Timing of IGBT Output with Dead Time Timer 7 ar EI cidem ou pesa 98ZIA L cHdQZIN L E HHdQZINL 1991 1unoo Figure 9 11 1 Count Timing of IGBT Output with Dead Time IX 59 IGBT Output with Dead Time Chapter 9 16 bit Timer IX 60 IGBT output waveform with dead time at the falling edge setting A Until the IGBT output is valid from the IGBT trigger input the TM7IO and 8 are 7 Low 8 Low B TM7IO rises after the time that is one count clock count clock x the dead time preset register 1 from the rising edge of the next count clock of the IGBT trigger input elapses C TM7IO falls at the next count clock from the compare match between the binary counter and TM70C2 D TMSIO rises after the time that is count clock x the dead time preset register 2 1 elapses E TMSIO falls at the next count clock from the compare match between the binary counter and TM7OCI TM7IO rises after the time that is count clock x the dead time preset register 1 1 elapses since TMSIO falls G As soon as the IGBT trigger is invalid the TM7IO and TM8IO are TM7IO Low TM8IO Low When using the IGBT
105. 4 N ch current capacity selection register P5OUT 0x03F15 Port 5 output register P5IN 0x03F25 Port 5 input register P5DIR 0x03F35 Port 5 direction control register P5PLUP 0x03F45 Port 5 pull up resistor control register P50DC 0x03F55 Port 5 N ch open drain control register P5NLC 0x03EC4 Port 5 N ch current capacity selection register P6OUT 0x03F 16 Port 6 output register P6IN 0x03F26 Port 6 input register P6DIR 0x03F36 Port 6 direction control register Control Registers Chapter 7 I O Port VII 3 Chapter 7 I O Port VII 4 Register P6PLUP Address 0x03F46 Function Port 6 pull up resistor control register VII 17 P6ODG 0x03F56 Port 6 N ch open drain control register VII 21 0x03EC5 Port 6 N ch current capacity selection register VII 24 P7OUT 0x03F17 Port 7 output register VII 7 P7IN 0x03F27 Port 7 input register VII 10 P7DIR 0x03F37 Port 7 direction control register VII 14 P7PLUP 0x03F47 Port 7 pull up resistor control register VII 17 P7NLG 0x03EC6 Port 7 N ch current capacity selection register VII 24 P8OUT 0x03F18 Port 8 output register VII 7 P8IN 0x03F28 Port 8 input register VII 11 P8DIR 0x03F38 Port 8 direction control register VII 14 P8PLUP 0x03F48 P
106. 7 8 address data gt 4 8 bits transmission gt transmission SDAn SCLn SCnTIRQ lIC3BUSBSY A Set data to TXBUFn Set data to TXBUFn Set IIC3STPC Figure 13 5 7 Master Transmission Timing 1 Generate start condition by setting data to TXBUFn 2 Transmit Address data slave address R W bit 3 Receive ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive ACK bit 7 Set SCnMD3 IIC3STPC in interrupt handler 8 Generate stop condition XIII 62 IIC Communication Chapter 13 Serial Interface W Master Reception Timing 1 2 6 0 0 it address data p 4 reception p lt M transmission SCnTIRQ IIC3SBUSBSY A o Set data to TXBUFn Set dummy data to TXBUFn Set 5 Figure 13 5 8 Master Reception Timing 1 Generate start condition by setting data to TXBUFn 2 Transmit Address data slave address R W bit 3 Receive ACK bit 4 Set SCnMD3 JIC3REX to 1 and write dummy data to TXBUFn in interrupt handler 5 Receive data 6 Transmit NACK bit 7 Set SCnMD3 1IIC3STPC in interrupt handler 8 Generate stop condition IIC Communication 63 Chapter 13 Serial Interface W Slave Transmission Timing 0 2 0 0 5 6 70 8 address ia 8 bit transmission e M ag reception H
107. 7 10 3 8 bit Free r nmng Tamers oe erint RR E RE pa eee X 8 10 3 T Operation CU Uo E bd X 8 103 2 Setup Example ce bee ete ea ett e e tase X 11 10 4 Time Base Timer oo cete ent ee RU ERE rtu etie teer e Eee trea X 12 10 4 1 Giu Dae v X 12 10 4 2 Setup Ex mple l s BAe A i ek a er ee ea 14 Chapter 11 Time Base Timer 0 0001 1011 XI 1 uuu ER E E RE E OE EEE EE EE OEE EEEE XI 2 11 1 T BP nctiOns ote EEE 2 11 2 Contr l Register uoo eee hen eui piedpote tere pie eut legen XI 3 11 2 1 RTC TBT Control RegISfer a 4 1L2 2 RTGSTBT eR e evt baee ees XI 6 11 2 3 RTC TBT Frequency Adjustment Register a eene XI 7 Contents 6 gt 11 3 RTC TBT Operation REID eH XI 9 11 3 1 RTC TBT Operation itte aaa Hc leash XI 9 11 3 2 Operation Setting Example ence dte aayqa XI 10 Chapter 12 Re l Time lock RTC senes uscite eto estet latas ped XII 1 12 1 OVery1ew eoe ORE entere e eee XII 2 12 2 Control Registers eee etre Rem Upper XII 3 12 2 1 Control ERE Ero te eb mesh 4 12 2 2 Alarm 0 Interrupt Registers XII 5 12 2 3 Alarm 1 Interrupt Registers
108. 8 Clock Control W Clock Supply Control Register 0 PRICKCNTO 0x03E10 Clock supply control register 0 controls clock supply to peripheral functions bp 7 6 5 4 3 2 Chapter 4 Clock Mode Voltage Control 1 0 Bit name PRICKCNT 07 06 PRICKCNT PRICKCNT PRICKCNT 05 04 PRICKCNT 03 PRICKCNT 02 PRICKCNT 01 PRICKCNT 00 Initial value 0 0 0 0 0 0 0 0 Access Bit name PRICKCNT07 Description Clock control for RTC function 0 disabled 1 enabled PRICKCNT06 Clock control for Timer 6 and General time base timer 0 disabled 1 enabled PRICKCNT05 Clock control for Timer 5 0 disabled 1 enabled PRICKCNT04 Clock control for Timer 4 0 disabled 1 enabled PRICKCNT03 Clock control for Timer 3 0 disabled 1 enabled PRICKCNT02 Clock control for Timer 2 0 disabled 1 enabled PRICKCNT01 Clock control for Timer 1 0 disabled 1 enabled PRICKCNT00 Clock control for Timer 0 0 disabled 1 enabled Clock Control 9 Chapter 4 Clock Mode Voltage Control m Clock Supply Control Register 1 PRICKCNT1 0x03E11 Clock supply control register 1 controls clock supply to peripheral functions bp 7 6 4 3 2 1 0 PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT 17 16 15 14 13 12 11 10 Initial value 0 0 0 0 0 0 0 0
109. Access Bit name Description 7 2 Always read as 0 Select capture trigger 1 T8ICT2 0 Timer 0 interrupt 1 Timer 1 interrupt Binary counter clear enable at capture 0 T8CAPCLR 0 Disabled not cleared 1 Enabled cleared The TM8MD4 T8CAPCLR is valid when the timer is in active Note that the binary counter is 1 not cleared when capturing data while the timer is stopped must not be changed at the same time as the other bit lt Set the Timer 8 mode registers while the TM8MD1 TM8EN is 0 And the TM8MD1 TM8EN 16 bit Timer Control Registers IX 17 Chapter 9 16 bit Timer Timer 9 Mode Register 1 TM9MD1 0x03FC8 Bit name T9ICEDG1 At reset 0 Access Bit name Always read as 0 Description Select capture trigger edge T9ICEDG1 0 Falling edge 1 Rising edge Timer output enable 0 Enabled 1 Disabled reset Control timer count 0 Disabled 1 Enabled Select count clock 00 1 1 clock TM9PS1 0 01 1 2 clock 10 1 4 clock 11 1 16 clock Select clock source 00 HCLK TM9CK1 0 01 SYSCLK 10 TM9IO input 11 SCLK IX 18 16 bit Timer Control Registers Timer 9 Mode Registers 2 TM9MD2 0x03FC9 Bit name T9ICEDG0 T9PWMSL TM9BCR TM9PWM TM9IRS1 T9ICEN Chapter 9 16 bit Timer At reset 0 0 0 0 0 0 Access Bit name T9ICEDG0
110. BCDADD DO BCD D1 BCD DO BCD BCD addition with carry MOV 32 0x3F07 Extended calculation macro instruction BCDADDC DO BCD D1 BCD PSW CF DO BCD BCD subtraction without carry MOV 64 0x3F07 Extended calculation macro instruction BCDSUB BCD D1 BCD 00 BCD BCD subtraction with carry 128 Ox3F07 Extended calculation macro instruction BCDSUBC 00 BCD D1 BCD PSW CF gt 00 BCD bit changes Extended Calculation Function Chapter 2 CPU Chapter 2 CPU 2 3 2 Extended Calculation Control Register Extended calculation can be executed by setting the extended calculation control bit W Extended Calculation Control Register AUCTR 0x03F07 7 6 5 4 3 2 0 AUBCDSUBC AUBCDSUB AUBCDADDC AUBCDADD Reserved AUDIVU AUMULU 0 0 Bit name AUBCDSUBC 0 0 0 0 Description BCD subtraction with carry 0 Disabled 1 Enabled 0 AUBCDSUB BCD subtraction without carry 0 Disabled 1 Enabled AUBCDADDC BCD addition with carry 0 Disabled 1 Enabled AUBCDADD BCD addition without carry 0 Disabled 1 Enabled Reserved AUDIVU Must be set to O Unsigned division execution 0 Disabled 1 Enabled Signed multiplication execution 0 Disabled 1 Enabled 18 AUMULU Extended Calculation Fu
111. CF 1 PC 5 d1 1 label H PC if CF 0 5 PC BLT label if VF NF 1 PC 4 d7 label H PC if VF4NF 0 PC 4 BLT label if VFANF 1 PC 5 d11 label H PC if VF NF 0 PC 5 BLE label if VFANF ZF 1 PC 44d7 label H gt PC if VFANF ZF 0 PC 4 PC BLE label if VFANF ZF 1 PC 51d1 1 label H PC if VFANF ZF 0 PC45 PC BGT label if VFANF ZF 0 PC 44d7 label H gt PC if VFANF ZF 1 PC 4 gt PC BGT label if VFANF ZF 0 PC 5 d1 1 label H PC ZF 1 PC 5 PC 1 94 sign extention 2 d7 sign extention 3 d11 sign extention 4 nottaken taken Instruction set 7 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET BHI label ZF 0 PC 5 d7 label H PC ZF 1 5 BHI label ZF 0 PC 6 d11 label H PC ZF 1 PC 6 gt PC BLS label ZF 1 PC 5 d7 label H PC ZF 0 5 BLS label if CF ZF 1 PC 6 d11 label H gt PC ZF 0 6 PC BNC label if NF 0 PC 5 d7 label H if NF 1 5 gt PC BNC label if NF 0 PC 6 d11 label H gt PC if NF 1 6 PC BNS label if NF 1 PC 5 d7 labe H PC if NF 0 PC 5 PC BNS label 1 PC
112. Chapter 4 Clock Mode Voltage Control System Clock Control Register CKCTR 0x03F04 bp 1 Bit name OSCSEL2 0 Initial value 0 0 0 0 Access Bit name Description Always read as 00000 The frequency of SYSCLK 000 001 fusci k 2 010 fusci k 4 OSCSEL2 0 011 8 100 1 6 101 fusci k 32 110 Setting is prohibited 111 Setting is prohibited Set the PSW MIE to 0 before changing the data of CPU or CKCTR Y Insert 3 NOP instructions right after the instruction for changing CPUM or CKCTR a The instruction for changing the data of CPUM or CKCTR must not be executed in the inter nal RAM V 6 Clock Control Chapter 4 Clock Mode Voltage Control High speed Oscillation Clock Control Register HCLKCNT 0x03F05 bp 7 3 2 1 0 Bit name HCLKSEL Reserved Reserved HOSCCNT HRCCNT Initial value 0 1 1 0 0 Access Bit name HCLKSEL Description High speed oscillation clock select 0 Internal high speed oscillation 1 External high speed oscillation Select internal high speed oscillation set the bit from 1 to 0 when HRC CNT 1 Internal High speed oscillation frequency select 00 1 MHz 01 Setting is prohibited 10 8 MHz 11 10 MHz Always read as 0 Reserved Always set to 111 HOSCCNT External high speed oscilla
113. Disable the timer count operation M7MD2 TM7BCR 1 Select the TM7BC clear source and the duty determination M7MD2 T7PWMSL 1 source of IGBT output Set the timer mode register M7MD3 T7IGBTTR 0 Select the IGBT trigger level and IGBT trigger edge M7MD2 T7ICEDGO 1 TM7MD3 T7IGBTDT 0 Select the dead time input timing T T T TM7MD3 T7IGBT1 0 01 Select the IGBT trigger source T Set the external interrupt IRQISEL0 IRQ0SEL 0 Enable the external interrupt pin IRQIEN IRQI0EN 1 Set the interrupt level IRQ0ICR IRQ0LV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Enable the interrupt IRQOICR IRQOIE 1 Set the timer mode register TM7MD1 TM7CK1 0 00 Select HCLK as the count clock source TM7MD1 TM7PS1 0 00 Set the IGBT output cycle TM7PR1 0x9C3F Set the IGBT output cycle Setup value 40000 1 39999 0x9C3F Set the High period of IGBT TM7PR2 0x270F Set the High period of IGBT output Setup value 40000 4 1 9999 0x270F Set the dead time TM7DPR1 Ox4F The time from the falling edge of 7 to the rising edge of TM7DPR2 Ox9F TMBIO 0 02 ms 0x4F The time from the falling edge of TM8IO to the rising edge of 0 01 ms Ox9F IX 62 IGBT Output with Dead Time Setting Set the timer mode register Register TM7MD3 T7IGBTEN 1 TM7MD2 TM7PWM 1 TM8MD3 TM8SEL 1 TM7MD1 TM7CL 0 Chapter 9 16 bit Timer
114. Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am AADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm d8 SP Dm MOV d16 An Dm MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm ANDs amp PSW oRs8PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 D MOVW abs16 Am MOVW abs16 DWm CBEQ 8 Dm d11 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d11 CBEQ 8 abs8 d7 d11 CBNE 8 abs8 d7 d11 MOVW d16 SP Am d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 DIVU MOVW An d16 SP MOVWDWn dt amp SP MOVW 08 5 MOVWDWn d amp SP MOVW MULU Instruction map 11 Chapter 20 Appendix Extension code 6 0011 2nd nibble 3rd nibble 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 TBZ abs8 bp d7 TBZ abs8 bp d11 1 2 abs8 bp d7 TBNZ abs8 bp d11 2 CMP Dn Dm 3 ADD Dn Dm 4 TBZ i08 bp d7 TBZ 8 011 5 2 io8 bp d7 TBNZ io8 bp d1 1 6 7 AND Dn Dm 8 BSET io8 bp BCLR io8 bp 9 UMP abs18 label JSR abs18 label A XOR Dn Dm XOR 8 Dm B JADDC Dn Dm BSET abs16 bp BCLR abs16 bp D BTST abs16 bp p m posa 8 0516 d7 d11 CBNE 8 abst6 d7 d11 TBZ abs16 bp d7 TBZ abs16 bp
115. Extended Calculation Instruction 23 Chapter 2 CPU II 24 2 4 5 BCDADD BCD addition without carry BCDADD MOV 0x10 0x03F07 Operation BCD D1 BCD DO BCD Adds the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and stores the result 8 bit after the BCD correction to the DO register Bit Changes Size Cycles Codes VF 0 NF 0 CF Set if the result is bigger than 99 otherwise set to 0 6 nibbles 4 cycles ZF Set if the result is 0 otherwise set to 0 0000 0010 0111 0000 0000 0001 W Execution of BCD addition without carry 1 Store the 8 bit value of the two digit BCD to add to the DO register and D1 register 2 Execute MOV 0x10 0x03F07 Extended calculation macro instruction BCDADD 3 Adds the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and stores the result 8 bit after the BCD correction to the DO register 0x03F07 1 When this extended calculation instruction is executed the handy address HA is updated the result is not guaranteed 1 In this instruction do not enter the value that can not represented BCD If you enter it Extended Calculation Instruction Chapter 2 CPU 2 4 6 BCDADDC BCD addition with carry BCDADDC MOV 0x20 0x03F07 D0 BCD D1 BCD PSW CF D0 BCD
116. OVlVGQOT IV1VGQO1 777 Eevvlvaol penssi yoye 1ndino sBuum lt 4 LALGOT1 04400 ____ pop Bulpiaip yoojn doi 4 7 1195 lt 0 zawao1 0 5 Figure 17 1 1 LCD Driver Circuit Block Diagram XVII 3 Overview Chapter 17 LCD 17 2 Control Registers Table 17 2 1 shows the registers that control LCDDRV Table 17 2 1 LCD Control Registers Register Address Function LCDMD0 0x03E80 LCD mode control register 0 XVII 5 LCDMD1 0x03E81 LCD mode control register 1 XVII 6 LCDMD2 0x03E82 LCD mode control register 2 XVII 7 LCDMD3 0x03E83 LCD mode control register 3 XVII 8 LCDMD4 OxOSECE LCD mode control register 4 XVII 8 LCCTRO 0x03E86 LCD output control register 0 XVII 9 LCCTR1 0x03E87 LCD output control register 1 XVII 10 LCCTR2 0x03E88 LCD output control register 2 XVII 11 LCCTR3 0 03 89 LCD output control register XVII 12 LCCTR4 OxO3E8A LCD output control register 4 XVII 13 LCCTR5 0x03E8B LCD output control register 5 XVII 14 LCDSEL 0x03E8E LCD display select register XVII 15 LCDATA0 42 0x03E90 0x03EBA LCD segment latch XVII 16 R W Readable Writable XVII 4 Control Registers Chapter 17 LCD 17 2 1 LCD Mode Control Registers m LCD Mode Control Register 0 LCDMDO 0x03E80 Bit name LCUPEN Reserved LCUPCKDIV2 At reset 0 0 0 0
117. PRICKCNT21 Clock control for Buzzer function 0 disabled 1 enabled PRICKCNT20 Clock control for LCD function 0 disabled 1 enabled Clock Control 11 Chapter 4 Clock Mode Voltage Control 4 1 2 Change of the External Low speed Oscillation Capability Bi Di The external low speed oscillation starts with high current driving capability at LSI power on After the oscilla tion stabilization the LSI changes the oscillation to low current driving capability for the low power consump tion If the current driving capability of oscillation is not enough it can be changed by the rewriting enable register FBEWER 0x03D80 and the clock mode control register CLKMD 0x03D8C To change the current driving capability set the registers in operation with the internal low speed oscillation SLOW mode SYSCLK SRCCLK Set the Rewriting Enable Register FBEWER 5 Set the Clock mode Control Register CLKMD bit6 4 010 Set the Rewriting Enable Register FBEWER 00 Changed the Current Driving Capability of External Slow speed Oscillation Figure 4 1 2 Change of the External Low speed Oscillation Capability IV 12 Clock Control Chapter 4 Clock Mode Voltage Control 4 2 Mode Control Function This LSI operates in one of the following 5 modes NORMAL SLOW HALT STOP IDLE CPUM controls the mode transition LSI reset or interrupts make the LSI recover from STANDBY mode HALT ST
118. Port 0 Table 7 4 1 Port 0 Pin Special function TM9IOC TM4IOB 4 TM2IOB TM8IOC BUZB TMOIOB TM7IOC NBUZB SBO3A SDA3A TM7IOA SBT3A SCL3A TMOIOA TM2IOA SBI3A SBCS3A CLKOUTA TM8IOB TM9IOA 7 4 1 Setup of Port 0 Table 7 4 2 P00 Function Selection Setup Function Register TMIOEN1 TM9MD1 TMIOSEL1 Bit name TM9OEN TM9CK1 0 TM9IOSEL1 0 1 Other than 10 10 TM9IO output 10 10 TM9IO input Other than 10 P00 Table 7 4 3 P01 Function Selection Setup Function Register TM4MD TMIOSELO Bit name TM40EN TM4CK1 0 TM4IOSEL 1 Other than 11 1 TM4IO output 11 1 TM4IO input Other than 11 P01 VII 34 Port 0 Table 7 4 4 P02 Function Selection Chapter 7 O Port Setup Function Register TMIOENO TM2MD TMIOSELO TMIOEN1 TM8MD1 TMIOSEL1 BUZCNT Bitname 2 2 1 0 TM2IOSEL TM8OEN TM8CK1 0 BUZEN BUZSEL Otherthan 4 0 Other than 0 TM2IO output 11 10 11 1 0 0 E TM2IO input 1 M NE 0 TM8IO output 0 Other than 10 10 0 TM8IO input 11 0 Other than 1 1 BUZB 10 0 P02 Table 7 4 5 P03 Function Selection Setup Function Register TMIOENO TMOMD TMIOSE
119. SBOOA TXDOA P66 SEG5 KEY6B SBTOA P67 SEG4 KEY7B SBCSOA The assignment and selection of SEGn differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 10 1 Setup of Port 6 LLLA LA T Table 7 10 2 P60 Function Selection VII 52 Port 6 Setup Function Register LCCTR1 IRQIEN IRQISELO Bit name SEGSL11 IRQIOEN IRQOSEL 1 SEG11 1 1 IRQ0B i 0 P60 Table 7 10 3 P61 Function Selection Setup Function Register LCCTR1 IRQIEN IRQISELO Bit name SEGSL10 IRQHEN IRQ1SEL 1 SEG10 1 1 IRQ1B 0 0 7 61 Chapter 7 I O Port Table 7 10 4 P62 Function Selection Setup Function Register LCCTR1 IRQIEN IRQISELO Bit name SEGSL9 IRQ2SEL 1 SEG9 1 1 IRQ2B 0 0 P62 Table 7 10 5 P63 Function Selection Setup Function Register LCCTR1 IRQIEN IRQISELO Bit name SEGSL8 IRQISEN IRQ3SEL 1 SEG8 1 1 IRQ3B 0 0 P63 Table 7 10 6 P64 Function Selection Setup Function Register LCCTR1 KEYIEN KEYSEL SCOMD1 SCO1SEL Bit name SEGSL7 KEYIAEN KEYASEL SCOSBIS SCOIOM SCOSELO 1 SEG7 1 1 0 KEY4B 0 0 0 SBIOA RXDOA 0 0 P64 Tab
120. SCnIICSTR IC3WRS Slave transmission la Set transmission data to TXBUFn Set dummy data to TXBUFn Start slave transmission Start slave reception End of slave transmission End of slave reception Communication completion interrupt Communication completion interrupt Communication completion Communication completion NO YES Stop condition detection interrupt generation IIC coommunication completion Figure 13 5 14 Slave Communication Setting Flow Diagram Serial transfer clock is needed to be set with BRTM_S_EN BRTM_S_MD IIC Communication 69 Chapter 13 Serial Interface XIII 70 IIC Communication Chapter 14 DMA Controller Chapter 14 DMA Controller 14 1 Overview Direct memory access controller DMA allows the direct data access in all memory area without CPU has priority to access data in memory area over CPU For internal memory ReRAM RAM CPU can access memory during DMA data transfer if the bus collision between DMA and CPU doesn t happen DMA has the following features Table 14 1 1 Function Data transmission unit 8 bit or 16 bit Maximum number of DMA transfer 210 1 External interrupt including Key interrupt Internal interrupt and Soft DMA start trigger ware trigger Transfer mode Single transfer or Burst transfer Emergency stop DMA transfer can be stopped during DMA data transfer by software
121. SCnSBCSLV SCIFn n 2 3 Set SCnMD2 SCnSBCSEN to 1 and select the direction SCnMD2 SCnSBCSLYV When the LSI is a master the chip select signal outputs from SBCSn When the LSI is a slave the input signal to SBTn is masked and SBOn is high impedance state while chip select signal input to SBCSn is negated In time division 2 wire communication with SBOn be careful to prevent data collision at Y SBOn When the LSI only send data receive data set SCnMD1 SCnSBIS to 0 Y When the LSI only receive data not send data set SCnMD1 SCnSBOS to 0 Clock Synchronous Communication 29 Chapter 13 Serial Interface XIII 30 W Setting of Transfer Clock SCnCLK SCIFn n 0 1 operates with SCnCLK which is generated based on BRTM output clock BRTM_SCnCLK When SCnMD1 SCnCKM is 0 SCnCLK is the same as BRTM_SCnCLK When SCnMD1 SCnCKM is 1 SCnCLK is as follows When SCnMD1 SCnDIV is 0 SCnCLK is BRTM_SCnCLK divided by 8 When SCnMD1 SCnDIV 15 1 SCnCLK is BRTM_SCnCLK divided by 16 SCnCLK of SCIF n 2 3 is the same as BRTM_SCnCLK When the LSI is a master SCnCLK is output from SBTn as a transfer clock When the LSI is a slave set the frequency of SCnCLK to the value faster than the transfer clock s and as close to the transfer clock s as possible Generating Baud Rate Timer Output Clock BRTM_SCnCLk SCIFn has a dedicated Baud Rate Timer BRTMn Select a count clock fo
122. SEG8 P57 selection SEG4 P57 selection SEGSL8 0 P63 0 P57 0 P57 1 SEG8 1 SEG8 1 SEGA SEG7 P64 selection SEG7 P60 selection SEG3 P60 selection SEGSL7 0 64 0 P60 0 60 1 SEG7 1 SEG7 1 SEG3 SEGO P65 selection SEG6 P61 selection SEG2 P61 selection SEGSL6 0 P65 0 P61 0 P61 1 SEG6 1 SEG6 1 SEG2 SEG5 P66 selection SEG5 P62 selection SEG1 P62 selection SEGSL5 0 P66 0 P62 0 P62 1 SEG5 1 SEG5 1 SEG1 SEG4 P67 selection SEG4 P63 selection SEG0 P63 selection SEGSL4 0 P67 0 P63 0 P63 1 SEG4 1 SEG4 1 SEGO XVII 10 Control Registers Chapter 17 LCD LCD Port Control Register 2 LCCTR2 0x03E88 Bit name SEGSL19 SEGSL18 SEGSL17 SEGSL16 SEGSL15 SEGSL14 SEGSL13 SEGSL12 At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LRO5D MN101LRO4D MN101LROSD SEG19 P50 selection SEG19 P40 selection SEG11 P40 selection SEGSL19 0 P50 0 P40 0 P40 1 SEG19 1 SEG19 1 SEG11 SEG18 P51 selection SEG18 P41 selection SEG10 P41 selection SEGSL18 0 P51 0 P41 0 P41 1 SEG18 1 SEG18 1 SEG10 SEG17 P52 selection SEG17 P42 selection SEG9 P42 selection SEGSL17 0 P52 0 P42 0 P42 1 SEG17 1 SEG17 1 SEG9 SEG16 P53 selection SEG16 P43 selection SEG8 P43 selection SEGSL16 0 P53 0 P43 0 P43 1 SEG16 1 SEG16 1 SEG8 SEG15 P54 selection SEG15 P44 selection SEG7 P44 selection SEGSL15 0 P54 0 P44 0 P44 1 SEG15 1 SEG15 1 SEG7 SEG14 P55 se
123. SP 1111 000A MOVW DWn abs8 DWn mem16 abs8 1101 0110 MOVW An abs8 An 8 1101 010A MOVW DWn abs16 DWn mem16 abs16 1101 0110 MOVW An abs16 An mem16 abs16 1101 010A MOVW DWn HA DWn mem16 HA 1001 010D MOVW An HA An mem16 HA 1001 011A imm8 DWm sign imms DWm 0000 110d MOVW imm8 Am zero imms Am 0000 111a MOVW imm16 DWm imm16 DWm 1100 111d 1 d8 sign extention 2 d4 zero extention 3 d8 zero extention 4 5 8 sign extention 6 8 zero extention 7 When the access address is odd number the execution cycle is added 1 d Instruction set 5 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Mnemonic MOVW imm16 Am Operation imm16 Am Execution Cycle 111 H6 Machine Code 5 6 MOVW SP SP Am 100a MOVW An SP An SP 101A MOVW DWn DWm DWn gt DWm 00Dd MOVW Dwn Am DWn Am 11Da MOVW An DWm 11Ad MOVW An Am An 00Aa PUSH Dn SP 1 SP Dn mem amp SP 10Dn PUSHAn SP 2 SP 2 mem16 SP 011 POP Dn mem8 SP Dn SP 1 SP 10Dn POP An mem16 SP gt Dn SP 2 SP 011 EXT DWm ADD Dn Dm si
124. Setup Example Here is an example that using Timer 7 the PWM output waveform with the 1 4 duty cycle and 122 1 Hz is output from TM7IO output pin HCLK at fic 8 MHz is selected as a clock source The setup procedure and its description are shown below TM71O output 122 1 Hz Figure 9 6 4 Output Waveform of TM71O Output Pin Setting Register Description Disable the timer counter M7MD TM7EN 0 Disable the timer count operation Select the timer output pin MIOEN1 TM7OEN 1 Select the timer output pin ODIR PODIR4 1 Chapter 7 I O Port Set the timer mode register M7MD2 TM7PWM 1 Select the PWM output M7MD2 TM7BCR 0 Select the TM7BC clear source M7MD1 TM7CK1 0 00 Select HCLK as the count clock source M7MD1 TM7PS1 0 00 Set the High period of PWM M7PR1 0x3FFF Set the High period of PWM output Setup value 65536 4 1 16383 0x3FFF Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation The PWM output at the initial state is Low It changes to High at the time the PWM opera tion is selected by setting TM7MD2 TM7PWM to 1 IX 34 16 bit Standard PWM Output with Continuously Variable Duty Chapter 9 16 bit Timer 9 7 16 bit High Precision PWM Output with Continuously Variable Period Duty 9 7 1 Operation In the high precision PWM output function a PWM waveform with a given period and duty cycle can be gener
125. TMOMD TMOPWM 0 TMOMD TMOMOD 1 Select the pulse width measurement function TMOMD TMOCK1 0 01 Select the prescaler as the clock source Set the prescaler CKOMD TMOPSC1 0 CKOMD TMOBAS 1 Select SYSCLK 2 Set the compare register TMOOC OxFF Set the value larger than that of the Low period of measured pulse width Set the interrupt level TMOICR TMOLV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Set the interrupt valid edge IRQOICR REDGO 1 Set the external interrupt valid edge Enable the interrupt TMOICR TMOIE 1 Enable the external interrupt Enable the timer counter TMOMD TMOEN 1 Enable the timer count operation The internal enable is set while the sampled signal at the count clock which is External Interrupt 0 IRQO input is Low level TMOBC starts counting up from 0x00 after the internal enable is set Timer 0 continues counting up while IRQO is Low and stops counting up when the sampled signal of IRQO becomes High level At the same time Low period of IRQO input can be detected by reading the value of TMOBC in the interrupt process VIII 30 Simple Pulse Width Measurement Chapter 8 8 bit Timer 8 8 8 bit Timer Cascade Connection 8 8 1 Operation 16 bit timers in cascade connection are the combination of the following 8 bit timers Timer 0 connected with Timer 1 Timer 2 connected with Time
126. TMnEN bit register 1 Binary counter Capture trigger Capture register 0002 0006 Figure 9 8 4 Binary Counter Clear Function at Capture Timer 7 and Timer 8 16 bit Timer Capture Function IX 45 Chapter 9 16 bit Timer 9 8 2 Setup Example W Capture Function Setup Example Here is an example that using Timer 7 the value of the binary counter is loaded to the capture register at the interrupt generation edge of IRQO signal to measure the pulse width The rising edge is selected for the interrupt generation edge and capture trigger generation edge The following is an example of setup procedures External Interrupt 0 IRQO input interrupt interrupt processing processing gt Pulse width to be measured Figure 9 8 5 Pulse Width Measurement of External Interrupt 0 Input Signal Setting Disable the timer counter Register TM7MD TM7EN 0 Description Disable the timer count operation Disable the interrupt TM7ICR TM7IE 0 Disable the timer interrupt Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 00 Select HCLK as the count clock source Set the compare register TM7PR1 0xFFFF Setup data in TM7PR1 is loaded to TM7OC1 Set the timer mode register TM7MD2 T7ICT1 0 00 Select the capture trigger source TM7MD1 T7ICEDG1 1 TM7MD2 T7ICEDGO 1
127. TXDOB Output Pull up resistor can be added by setting PnPLUP SBO1A TXD1A Select the output mode by setting PnDIR SBO1B TXD1B Select the serial data output by setting SCnMD1 SCnSBOS n 0 1 2 3 SBO2A SDA2A Select the push pull or Nch open drain by setting PnODC SBO2B SDA2B SBOSA SDA3A SBOSB SDA3B SBO3C SDA3C SBTOA Input Serial clock I O pins SBTOB Output Pull up resistor can be added by setting PnPLUP SBT1A Select the input or output mode by setting PnDIR SBT1B Select the serial clock I O by setting SCnMD1 SCnSBTS n 0 1 2 3 SBT2A SCL2A Select the push pull or Nch open drain by setting PnODC SBT2B SCL2B SBT3A SCL3A SBT3B SCL3B SBT3C SCL3C SBCS0A SBCS0B Input Serial chip select I O pins SBCS1A SBCS1B Output Pull up resistor can be added by setting PnPLUP SBCS2A SBCS2B Select the input or output mode by setting PnDIR SBCS3A SBCS3B Select the serial chip select by setting SCnMD3 SCnSBTS n 0 1 or SCnMD2 SCnSBCSEN n 2 3 TMOIOA TMOIOB Input Timer pins TM11IOA TM1IOB Output When capturing the external event signal select the input mode by setting PnDIR TM2IOA TM2IOB To output the timer output signal select the output mode by setting PnDIR and the output port with TMIOENn TMIOSELn 0 1 TM4IOA TM4IOB TMBIOA TMSIOB TM7IOA TM7IOB TM8IOA TM8IOB TMSIOA TMSIOB ANO AN1 AN2 AN3 Input Analog input pins for ADC AN4 AN5 AN6 AN7 Select the analog in
128. Table 15 2 1 Buzzer Control Registers Address Register name BUZCTR 0x03F7F R W Buzzer Control Register XV 4 PODIR 0x03F30 R W Port 0 direction control register VII 12 P3DIR 0x03F33 R W Port 3 direction control register VII 13 BUZCNT 0x03F5F Buzzer output Buzzer output terminal control register VII 32 Control Register XV 3 Chapter 15 Buzzer XV 4 15 2 2 Buzzer Control Register m Buzzer Control Register BUZCTR 0x03F7F uj mm mu L 0 0 0 0 0 0 0 0 At reset Access R W R W R W R W R R R R Bit name Description Buzzer output selection 0 Buzzer output disable 1 Buzzer output enable Buzzer output frequency selection 000 214 001 213 010 212 011 fuciK 2 100 219 101 22 110 24 111 23 Always read as 0 1 The BUZCTR BUZOE and BUZCTR BUZS2 0 must not be set at the same time When the BUZCTR BUZOE is 0 Low level signal is output from BUZ NBUZ Control Register Chapter 15 Buzzer 15 3 Operation 15 3 1 Operation m Buzzer Output Frequency The frequency of buzzer output is decided by the setting value of BUZCTR BUZS2 0 and the frequency of HCLK and SCLK Table 15 3 1 Buzzer Output Frequency fucLk BUZS2 BUZS1 BUZSO B
129. Updating the Timer 7 preset register 1 and 2 is prohibited during IGBT operation 9 9 1 Operation m IGBT Trigger IGBT trigger can be selected from IRQO IRQ1 IRQ2 and Timer 7 count operation by setting the TM7MD3 TMT7IGBTO 1 The IGBT output operates by detecting the trigger input level When setting the TM7MD3 T7IGBTTR to 1 to select the rising edge the count operation is executed while the corresponding interrupt pin is High When setting the TM7MD3 T7IGBTTR to 0 to select the falling edge the count operation is executed while the corresponding interrupt pin is Low To control the activation with the instruction select TM7EN count operation In that case the timer count oper ation and IGBT output are controlled with the TM7MD1 TM7EN When setting the bit to 1 to start counting the count operation continues until the bit is set to 0 to stop counting Be sure to set the TM7MD3 T7IGBTO 1 before setting the TM7MD1 TM7EN 16 bit Standard IGBT Output Operation Timer 7 Detecting the trigger by the external interrupt signal through the external interrupt interface block while setting the High period of duty in 7 generates the IGBT waveform with a specified duty The cycle is the time of the 16 bit timer full count overflow The standard IGBT output function can be used in Timer 7 Table 9 9 1 IGBT Output Pin xr TM7IOA output TM8IOA output IGBT output pin TM7IOB output TM8IOB output TM
130. XIV 2 Overview Chapter 14 DMA Controller 14 1 1 Block Diagram DMCTRnL H 0 1 control register Access size 4 Timing control signal Whole control IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 KEY interrupt DMSRCL M H Timer 0 interrupt Source address register Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Source address 4 Timer 5 interrupt Timer 7 interrupt DMDSTL M H mer 7 input capture factor Destination address register Timer ginterpt mE Timer 8 input capture factor Destination address e Timer 9 interrupt Timer 9 input capture factor Serial interface 0 reception interrupt 4 DMCNTL H Serial interface 0 transmission interrupt Transfer word count register Serial interface 0 buffer empty factor Serial interface 1 reception interrupt Serial interface 1 transmission interrupt Serial interface 1 buffer empty factor Serial interface 2 transmission complete interrupt Serial interface 2 buffer empty factor Serial interface 3 transmission complete interrupt Serial interface 3 buffer empty factor A D conversion interrupt Figure 14 1 1 Block Diagram Overview XIV 3 Chapter 14 DMA Controller 14 2 DMA Controller Control Registers Table 14 2 1 shows the list of DMA control registers Table 14 2 1 DMA Control Registers Address Register Name MCTR
131. access to the memory space 0x13F00 to Ox13FFF please use the addressing mode expect absolute register indirect or register relative indirect Refer to Chapter 2 2 1 8 Addressing Modes a While bank function is valid regardless of bank setting please use the absolute addressing a Stack area must be set in the bank 0 Our linker supports the function that prevents data from straddling over bank boundaries See MN101C MN101E Series Cross assembler User s Manual for details Overview 1 11 Chapter 2 CPU m Bank Register for Source Address SBNKR 0x03F0A The SBNKR is used to specify bank area for loading instruction Once this register is specified bank control is valid for all addressing modes except I O short instruction and stack relative indirect instruction Refer to 2 1 8 Addressing Modes bp 3 2 1 Bit name Reserved Reserved Reserved At reset 0 0 0 0 Access Bit name Description Always read as 0 Reserved Must be set to 0 Assignment of bank for source data access address SBAO 0 bank 0 1 bank 1 m Bank Register for Destination Address DBNKR 0x03F0B The DBNKR is used to specify bank area for storing instruction Once this register is specified bank control is valid for all addressing modes except I O short instruction stack relative indirect instruction and bit manipulation instruction Refer to 2 1 8 Addressing Modes
132. active and the clock is supplied only to Real time clock CPU wakes up from HALT mode by interrupt or reset When resetting the normal reset operation is executed When an interrupt occurs the mode is returned to the same status as before changing to HALT mode The transition procedure from CPU operating mode to HALT mode is shown below Transition procedure from NORMAL mode to HALTO mode Set CPUM HALT to 1 Transition procedure from NORMAL mode to HALT2 mode Set CPUM HALT to 1 and CPUM OSCMOD to 0 at the same time while the low speed oscillation is sta ble Transition procedure from SLOW mode to HALT1 HALT3 mode Set CPUM HALT to 1 If CPUM HALTMOD is O and 1 the mode changes to HALT1 HALT3 respectively Transition procedure from NORMAL mode to HALT1 HALT3 mode Set CPUM HALT to 1 CPUM OSCMOD to 0 and CPUM CLKSEL to 0 at the same time while the low speed oscillation is stable If CPUM HALTMOD is 0 and 1 the mode changes to and HALT3 respectively The transition procedure from SLOW mode to HALTO mode Set to 1 CPUM OSCMOD to 1 and CPUM CLKSEL to 1 at the same time The transition procedure from SLOW mode to HALT2 mode Set CPUM HALT to 1 CPUM OSCMOD to 0 and CPUM CLKSEL to 1 at the same time Figure 4 2 10 and Figure 4 2 11 show the transition procedure from CPU operating mode to HALT mode NORMAL SLOW mode Transition to HALTO HALT1 HALT2 mode S
133. adequate time for HCLK oscillation stabilization by program 5 0018 voltage change time PWCTR1 PWUPTM2 0 500 us or more HCLK oscillation stabilization DLYCTR DLY3 0 6 0018 voltage change time PWCTR1 PWUPTM2 0 4 ms or more HCLK oscillation stabilization DLYCTR DLY3 0 IV 32 Mode Voltage Clock Transition Chapter5 Watchdog Timer WDT Chapter 5 Watchdog Timer WDT 5 1 Overview The watchdog timer WDT generates NMI WDIRQ when the dedicated counter WDT Counter is not cleared during the error detect period and overflows When two consecutive WDIRQs occur without clearing WDT Counter the LSI is reset by hardware The clock source of WDT Counter is selected from SOSCCLK or SRC CLK Reset Write to WDCTR SOSCCLK R WDIRQ WDT Counter Reset Interrupt SRCCLK WDTCLK Overflow control LSI reset WDCTR WDCKSEL WDCTR The following table shows the relationship between CPU mode and the WDT operation when WDT is active WDT Counter is initialized when the LSI is reset or is in STOP mode Table 5 1 1 Relationship between CPU mode and WDT operation CPU mode WDT Counter operation Continue to count Sen ONAL Count operation doesn t stop even during the mode transition Stop counting The value of WDT Counter is cleared WDIRQ is not generated STOP mode STOP When the WDIRQ is generated the LSI can be in unexpected state Therefore appro
134. and are used for data transmission and reception respectively 4 wire Communication Data transmission and reception are executed with 3 pins of 3 wire communication and a chip select pin SBCSn Clock Synchronous Communication Chapter 13 Serial Interface 13 3 2 Operation TTT m Initialization Serial Reset SCIFn has a built in serial reset function for abnormal operation Registers other than TXBUFn must be changed during the serial reset of SCIFn The way of serial reset is as follows SCIFn n 0 1 SCnMD2 SCnBRKF and SCnSTR are initialized by setting SCnMD3 SCnRSTN to 0 SCIFn n 2 3 SCnSTR and SCnIICSTR are initialized by setting SCnMD2 SC3RSTN to 0 m Pin Settings 1 To use the data pins SBOn SBIn the following settings are required lt 2 wire communication gt At data reception Set SCnMD1 SCnSBIS to 1 and SCnMD1 SCnSBOS to 0 At data transmission Set SCnMD1 SCnSBIS to 0 and SCnMD1 SCnSBOS to 1 lt 3 wire communication gt Set SCnMD1 SCnSBIS and SCnMD1 SCnSBOS to 1 SCnIOM must be set to 0 2 To use the clock pin SBTn the following setting is required At master SCnMD1 SCnMST is 1 the communication clock outputs from SBTn At slave SCnMD1 SCnMST is 0 input the communication clock to SBTn 3 In 4 wire communication the following setting of the chip select pin SBCSn is required SCIFn n 0 1 Set SCnMD3 SCnSBCSEN to 1 and select the direction SCnMD3
135. at trailing edge SCnSBCSE N SBCSn function selection Selectable only in Clock Synchronous communication always set 0 in IIC communication 0 Disabled 1 Enabled Chip select I O SCnSBCSLV SBCSn polarity selection Selectable only in Clock Synchronous communication and always set 0 in IIC communication 0 Active low 1 Active high Control Registers 0 is always read out Chapter 13 Serial Interface m SCIFn n 0 1 Mode Register SC0MD3 SC1MD3 Bit name SCnFDC1 SCnFDC0 SCnRSTN SCnRSRN SCnCKPH SCnSBCS SCnSBCS EN LV Initial value 0 0 Access 7 6 Bit name SCnFDC1 0 Description Output level selection after the final bit of SBOn is transmitted 00 Fixed at 1 High output 01 Hold the final data 10 Fixed at 0 Low output 11 Setting prohibit SCnRSTN Serial reset control in Clock Synchronous communication 0 Reset 1 Reset release Serial reset control in UART transmission 0 Reset 1 Reset release SCnRSRN Always set to 0 in Clock Synchronous communication Serial reset control in UART reception 0 Reset 1 Reset release SCnCKPH Clock phase selection Selectable only in Clock Synchronous communication Always set 0 in IIC communication 0 Data transmission at leading edge data reception at trailing edge 1 Data reception at leading edge data transmission at trai
136. bit Timer 9 4 16 bit Event Count 9 4 1 Operation For event count operation TMnIO input can be used as a count clock source and divided by 1 not divided 2 4 or 16 The event count input pin is shown in Table 9 1 1 W Count Timing of TMnIO Input The binary counter counts up at the falling edge of TMnIO input signal that is divided or not TMnlO input TMnEN bit Internal enable Compare register Binary 0000 0001 0002 ma 00004 0001 counter Interrupt request Figure 9 4 1 Count Timing TMnIO Input 16 bit Event Count IX 25 Chapter 9 16 bit Timer 1 When reading the value of use 16 bit instruction MOVW or write data to TMnIG with a software function When using the MOVW instruction indeterminate data during counting may be read So read the register value several times and confirm those data are identical When using the capture function Writing to TMnIC can capture the count value of TMnBC to TMnIC to read the count value during counting precisely For more information refer to 9 8 1 Operation When using TMnIO input be sure to set each mode register and preset register after select ing SYSCLK as a count clock source Then select TMnIO input to start a timer As for the 16 bit timer only when using TMnIO input it is possible to return from STOP HALT2 HALT3 mode When using the event input TMnIO input clear TMnBC before starting the timer operation
137. by 8 bit Timer The input signal from an external interrupt pin for the simple pulse width measurement is sampled at the count clock The binary counter of the timer counts up while the sampled signal is Low It is available to measure the pulse width by reading the count value of the timer For pulse width measurement pins refer to Table 8 1 1 Count Timing of Simple Pulse Width Measurement Count clock External interrupt IRQn TMnEN bit Internal enable Compare register FF cs counter Figure 8 7 1 Count Timing of Simple Pulse Width Measurement The internal enable signal is generated while the timer is in active by setting TMnMD TMnEN to 1 and the sig nal sampled at the count clock is Low The signal is input from an external interrupt pin for the simple pulse width measurement While the internal enable signal is High the timer counts up Simple Pulse Width Measurement VIII 29 Chapter 8 8 bit Timer 8 7 2 Setup Example m Setup Example of Simple Pulse Width Measurement by 8 bit Timer Here is an example that Timer 0 measures Low pulse width of the input signal of IRQ0 SYSCLK 2 is selected a clock source for Timer 0 The setup procedure and the description of each step are shown below Setting Disable the timer counter Register TMOMD TMOEN 0 Description Disable the timer count operation Set the timer mode register
138. capture function is generated at an interrupt signal of Timer 0 or 1 TMnEN bit Compare register 1 counter Timer 0 1 interrupt Capture trigger Capture 0000 0114 5558 register Figure 9 8 3 Capture Count Timing with a Trigger of an Interrupt of Timer 0 or 1 Timer 7 and Timer 8 3 TMnMD2 TnICT1 0 to 11 Set TMnMD2 and TMnMD4 to select the capture trigger When 1 A capture trigger is generated at an interrupt signal of Timer 0 or 1 when setting the selecting the Timer 0 or 1 interrupt as a capture trigger the selected edge is invalid clock Therefore the edge of the external interrupt input signal may not be detected when an inter val of interrupt input signal is shorter than capture clock cycle To prevent this please set count clock of Timer 0 or Timer 1 to be slower than the capture clock cycle a A capture trigger is generated by sampling the interrupt signal of Timer 0 or 1 at the capture IX 44 16 bit Timer Capture Function Chapter 9 16 bit Timer m Binary Counter Clear Function at Capture Timer 7 and Timer 8 When selecting the external interrupt input signal or Timer 0 1 interrupt as a capture trigger the binary counter can be cleared at a capture operation When clearing the binary counter at a capture operation set the TMnMD4 TnCAPCLR to 1 However the binary counter can be cleared only during the timer count operation Count clock
139. channels MNIOILROAD 6 channels MNIOILRO3D 4 channels MN101LRO2D 3 channels e ports 69 pins Selectable N channel transistor drive strength 55 pins MN101LR04D 53 pins selectable N channel transistor drive strength 41 pins MN101LR03D 37 pins selectable N channel transistor drive strength 27 pins MN101LR02D 22 pins selectable N channel transistor drive strength 19 pins Clock Output HCLK SCLK SYSCLK or RTCCLK can be output Automatic Reset Circuit Low voltage Detection Circuit LVI LCD Driver 43 segment outputs 4 common outputs 39 segment outputs 8 common outputs Display mode Static 1 2 to 1 8 duty Bias 1 2 1 3 Built in boost External resistor divider MNIOILRO4D 3 segment outputs 4 common outputs Display mode Static 1 2 to 1 4 duty MNIOILRO3D 21 segment outputs 4 common outputs Display mode Static 1 2 to 1 4 duty MNIOILRO2D does not have LCD driver function Hardware Features 1 5 Chapter 1 Overview Package MN101LR05D 80 1212 12 mm square 0 5 mm pitch halogen free MN101LR04D TQFP064 P 1010 10 mm square 0 5 mm pitch halogen free MNIOILRO3D TQFP048 P 0707 7 mm square 0 5 mm pitch halogen free MNIOILRO2D HQFN032 A 0505 5 mm square 0 5 mm pitch halogen free Panasonic halogen free semiconductor products refer to the products made of molding resin and interposer which conform to the following standards B
140. communication is executed without a communication blank To execute a communication without a blank write the next data to TXBUFn before the 7th bit of data 1 byte is received after the data in TXBUFn was read out to the transmission shift register SCnTRB and SCnTEMP changed to 0 Refer to the inverted triangle sign of Figure 13 3 11 Figure 13 3 12 Figure 13 3 13 and Figure 13 3 14 If this restriction is not satisfied the communication blank occurs secutive communication When a setting timing is delayed a transfer clock is masked and a 1 In consecutive communication mode set to TXBUFn for slave device to enable the communication does not work properly W Single byte Communication Mode When SCnMDO SCnCTM is 0 single byte communication mode is selected In this mode the following blank is inserted 1 When writing the next data to TXBUFn by the time specified with inverted triangle sign in Figure 13 3 11 Figure 13 3 12 Figure 13 3 13 and Figure 13 3 14 the blank period of up to 4 5T including Twait of 3 5T is inserted between each byte data transmission reception 2 Other than the above 1 the blank period of up to 4 5T including Twait of 3 5T is inserted after writing the next data to TXBUFn When the LSI is a master the transfer clock output is stopped while the serial communication is not executed When the LSI is a slave the transfer clock input to SBTn is masked while the seri
141. correction Setup Function LCCTRO SEGSLO LCDSEL COMSL4 COM4 SEGO TM5lO output TM5lO input P73 Setup Function LCCTRO SEGSLO LCDSEL COMSL4 1 COM4 SEGO TM5lO output TM5IO input P73 lt Record of Changes 2 gt Details of revision from Ver 1 2 to Ver 1 3 in MN101LR05D 04D 03D 02D LSI User s Manual is shown below According to the details of revision Definition of the table below is classified into seven groups Revision concerning descriptions in LSI User s Manual Writing error correction Description change Description addition Description deletion Revision concerning LSI specifications Specification change Specification addition Specification deletion Modification Ver 1 3 Details of Revision Definition Page Title Table 1 2 4 Line Writing error correction Port P46 Serial Interface SBCS2A Port P46 Serial Interface SBO1B TXD1B B Operating Condition Specification change Temperature Voltage dependence Eps MIN 5 0 MAX 5 0 Temperature Voltage dependence MIN 10 0 TYP MAX 10 0 Specification change Temperature Voltage dependence Erg MIN 15 0 TYP 15 0 Temperature Voltage dependence Erg MIN 20 0 TYP 20 0 C DC Char acteristics Specification change Operating supply current DD2 MAX 4 3 mA Operating supply current 1502 3 0 Specification change Operati
142. details of control registers including operation methods and setting examples motructure of This Manual Each section of this manual consists of a title summary main text hint precautions and warnings and references The layout and definition of each section are shown below Header Chapter number and Chapter title Section title Basie CPU Sub section title 2 8 Reset 8 1 Reset operation Main text the CPU contents are reset and registers are intialized when the NRST pin P 27 is pulled to low E Initiating a Reset There are two methods to initiate areset 1 Drive the NRST pin low for at least four clock cycles NTST pin should be holded low for more than 4 clock cycles 200 ns ta 20 NRST pin 4 tClock cycles I 200 ns at a 20 MHz Figure 2 8 1 Minimum Reset PUlse Width P 2 Setting the P2OUT7 flag of the P2OUT register to 0 outputs low level at P Hint 27 NRST pin And transfering to reset by program software reset be executed If the internal LSI is reset and register is initiated the P2OUT 7 flag becomes 1 and reset is released Important information from the text On this LSI the starting mode is NORMAL mode that high oscillation i Precautions and 4 s the base clock warnings hat gives pulse for enough low level time at sudeen unconnected And r the precautions to prevent set can be generated even if its pulse is low lev
143. duty and 1 4 duty by using MN101LR05D 1741 LCD Display Example static m Static Segment Latch 0 03 97 0x03E96 95 0x03E94 0x03E93 0 03 92 0 03 91 0 03 90 electrode B electrode ISEG6 SEGS ISEG4 SEG3 ISEG2 SEG1 o OFF LCDPANEL LCD ON COM S COM S LCD OFF SEG S SEG N LCD clock Undefined Data 1 0 Undefined Vici COM Vss Vici SEG Vss T P ev pee ee COM SEG 0 Eois sb l ces a fee se ee ON OFF OFF S selected voltage N non selected voltage Vico LCD driving voltage COM COMO always outputs the selected voltage in static XVII 26 LCD Display Examples Chapter 17 LCD Frame period COM0 VLCD A electrode COM0 SEG4 B electrode COMO SEG6 ON Figure 17 4 1 LCD display example in static LCD Display Examples XVII 27 Chapter 17 LCD 17 4 2 LCD Operation Setup Example static BZ s a es The following example is to display 2 on a 8 segment type LCD panel one digit display through segment pins SEGO to SEG7 and a common pin COMO in static supplied from external voltage source Other conditions are described as follows HCLK 4 MHz LCD display clock HCLK 2P 122 Hz LCD frame frequency 122 Hz Setup Procedure Desc
144. error occurs 1 Read out the received data of RXBUFn when SCnSTR SCnREMP is 1 Activation Source for Communication Data write to TXBUFn is the trigger to start data transmission or reception When the LSI only receive data not send data write dummy data to TXBUFn m First Bit Specification for Transfer When SCnMDO SCnDIR is 0 MSB first transfer is selected When SCnMDO SCnDIR is 1 LSB first transfer is selected Clock Synchronous Communication XII 35 Chapter 13 Serial Interface XIII 36 W Interrupt Source Select For SCIFn n 0 1 interrupt source can be selected with SCnMD2 SCnIFS When SCnIFS is 1 an interrupt occurs by an empty detection of TXBUFn detecting that SCnSTR SCnTEMP is 0 When SCnIFS 1 0 interrupt communication complete interrupt occurs after single byte communication has finishes For SCIFn n 2 3 interrupt source can be selected with SCnMD1 SCnIFS When SCnIFS is 1 an interrupt occurs by an empty detection of TXBUFn detecting that SCnSTR SCnTEMP is 0 When SCnIFS 1 0 interrupt communication complete interrupt occurs after single byte communication has been completed Transmission BUSY Flag SCIF0 and SCIF1 When SCnMDI SCnSBOS is 1 SCnSTR SCnTBSY is set to 1 by writing data to TXBUFn When SCnSTR SCnTEMP is 0 SCnSTR SCnTBSY is cleared to 0 by a communication complete interrupt If SCnTEMP is 1 by writing data to TXBUFn before a comm
145. falling edges IRQ1 trigger selection EDGSEL1 0 Rising edge or falling edge 1 Both edges Rising and falling edges IRQO trigger selection EDGSELO 0 Rising edge or falling edge 1 Both edges Rising and falling edges When EDGSELn is 0 rising edge or falling edge is selected with IRQnICR REDGn 38 External Interrupts W Noise Filter 01 Control Register NFCTR01 bp 7 6 5 3 2 Chapter 3 Interrupts 1 Bit name NF1SCK2 NF1SCK1 NF1SCK0 NF0SCK2 NF0SCK1 NF0SCK0 At reset 0 0 0 0 0 0 Access Bit name NF1SCK2 NF1SCK1 NF1SCK0 Description IRQ1 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 219 111 fscLK IRQ1 noise filter operation 0 Disabled 1 Enabled NFOSCK2 NFOSCK1 NFOSCKO IRQO noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 219 111 fscLK IRQO noise filter operation 0 Disabled 1 Enabled External Interrupts III 39 Chapter 3 Interrupts III 40 W Noise Filter 23 Control Register NFCTR23 bp 7 6 5 3 2 1 Bit name NF3SCK2 NF3SCK1 NF3SCK0 NF2SCK2 NF2SCK1 NF2SCK0 At reset 0 0 0 0 0 0 Access Bit name NF3SC
146. following documents related to MN101L series are available e MNIOIL Series Instruction Manual Describes the instruction set MNIOIC MNIOIE Series C Compiler User s Manual Usage Guide Describes the installation commands and options of the C Compiler MNIOIC MNIOIE Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler MNIOIC MNIOIE Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler MNIOIC MNIOIE Series Cross assembler User s Manual Describes the assembler syntax and notation PanaX EX Installation Manual Describes the steps to install the Integrated Development Environment DebugFactory Builder C compiler and the real time OS It also describes the procedure to setup the on board environment PanaX EX Commander User s Manual Describes the usage and notes on designing target board mCaution The related documents listed above are subject to change without notice Use the latest version of each document for designing mContact Information Please contact our sales division About This Manual 3 gt Contents Chapter1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 Clock Mode Voltage Control Chapter 5 Watchdog Timer WDT Chapter 6 Power Supply Voltage Detection Chapter 7 Port Chapter 8 8 bit Timer Chapter 9 16 bit Timer N oni BJO TP
147. function is disabled pull down the to Vss NATRON Input when auto reset function is enabled with the resistor the value of which is typically between 10 and 100 DMOD Input Pull down the pin to Vss with the resistor the value of which is typically between 1 5 and 100 Recommendation between 10 and 100 1 When unused pins are not connected the microcomputer does not have the problem However it is easily influenced by the serge or noise Evaluate enough for determining the appropriate configuration 2 When pins are unused set them to the general purpose port function 3 Evaluate enough in consideration of the influence by exogenous noise and decide the condition of each pin Cautions for Circuit Setup 1 37 Chapter 1 Overview 1 6 3 Power Supply E Isns s OOI TOTOn W Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on Failure to the sequence can cause the destruc tion of the LSI because of the large current Input protection Input resistance Forward current generation N Figure 1 6 5 and Input Pin Voltage Relation between Power Supply and Reset Input Voltage with Auto reset disable After the LSI turns on input the sufficient reset pin voltage to be recognized as the reset signal For more information refer to the 2 5 1 Reset function Reset pin low
148. interrupt Overflow detection 0 Not detected 1 Detected Negative detection 0 Not detected 1 Detected Carry detection 0 Not detected 1 Detected Zero detection 0 Not detected 1 Detected Zero Detection ZF ZF is set to 1 when all bits 0 in the operation result Otherwise zero bit is set to 0 Carry Detection CF CF is set to 1 when carry from or a borrow to the MSB occurs Carry bit is set to when no carry or borrow occurs Negative Detection NF NF is set to 1 when MSB is 1 and set to 0 when MSB is 0 Negative bit is used to handle a signed value Overflow Detection VF VF is set to 1 when the operation results overflow as a signed value Otherwise overflow bit is set to 0 Over flow bit is used to handle a signed value Overview CPU 1 5 Chapter 2 CPU 1 6 W Interrupt Mask Level IM1 to IMO Interrupt mask level IM1 IMO controls the accept level of maskable interrupt m Maskable Interrupt Enable MIE When MIE is set to 1 the maskable interrupt which is not masked with IMO is accepted and the value of MEMCTR MIESET is load into MIE When MIE is set to 0 all maskable interrupts are not accepted Table 2 1 3 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level MIE Priority Acceptable interrupt level IM1 IMO 0 Don t care Non maskable interrupt NMI
149. is activated the calendar information can be obtained by reading CALENDAR registers described in Chapter 12 2 5 To avoid misreading the calendar information because of the occurrence of the calendar update while reading it the following procedure 1 or 2 must be performed 1 Using 1 second periodic interrupt In the interrupt handler of 1 second periodic interrupt read the calendar information Start periodic interrupt with a cycle of a second is generated Yes Read clock data Complete reading clock data Figure 12 3 1 Clock Data Reading Procedure 1 2 Reading the calendar information several times Reading the calendar information several times until confirming the calendar information is stable Read clock data 1st time Read clock data 2nd time Read clock data N time 1 st data 2nd data N time data Figure 12 3 2 Clock Data Reading Procedure 2 XII 16 RTC Operation Chapter 12 Real Time Clock RTC 12 3 2 Setup Example r mOn T rE F W Periodic Interrupt Setup Example The following is an example to generate a periodic interrupt with a cycle of a minute with the RTC function Set the initial time to 01 01 00 Thursday April 01 2010 in 24 hour display mode The setup procedure and the description of each step are shown below Step Setting Symbol Description RTC stops RTCCTR Setthe CLKEN bit to Periodic inte
150. it can t be guaranteed that lt Note 2 gt Insert 3 NOP instructions right after Description change If priority level of the interrupt to be used is not equal to or higher than the mask level If the value of xICR LV1 0 for an inter rupt to be used as a return factor is equal or larger Figure 4 2 14 Writing error correction When returning from STOP mode wait for oscillation to stabilize NORMAL SLOW mode lt Watchdog timer HALTO0 1 2 3 continue counting HALT2 STOP restart counting lt When the transition corresponds to 1 in Figure 4 2 1 the oscillation stabilization wait time is inserted NORMAL SLOW mode lt Watchdog timer HALTO 1 2 3 continue counting STOP restart counting Description addition The instruction for the transition to STANDBY mode must not be executed in the internal RAM Record of Changes 4 Modification Ver 1 3 Page Title Figure 4 2 15 Line Definition Writing error correction Details of Revision lt When returning from STOP mode wait for oscillation to stabilize NORMAL SLOW mode lt Watchdog timer HALT0 1 2 3 continue counting HALT2 STOP restart counting lt When the transition corresponds to 1 in Figure 4 2 1 the oscillation stabilization wait time is inserted NORMAL SLOW mode lt Watchdog timer HALTO 1 2 3 continue counting STOP restart counting Description addition
151. level recognition voltage lower limit 0 15 x VDD30 6 ms or more Figure 1 6 6 Power Supply and Reset Input Voltage 1 38 Cautions for Circuit Setup Chapter 1 Overview 1 6 4 Power Supply Circuit mw sr Cautions for Power Circuit Design The MOS logic such a microcomputer is high speed and high density So the power circuit should be designed taking into consideration of AC line noise ripple caused by LED driver An example of a circuit with emitter follower type is shown below Set the noise filter capacitors closer to microcomputer power pins VDD30 Microcomputer VSS For noise filterring Figure 1 6 7 Power Circuit Example emitter follower type Cautions for Circuit Setup 1 39 Chapter 1 Overview 1 40 Cautions for Circuit Setup Chapter2 CPU Chapter 2 CPU 1 2 2 1 Overview The AM13L core CPU upward compatible with MN101C E core has the enhanced calculation units shortens the interrupt latency and has the 16 bit bus architecture to access instruction data memory and peripheral circuits The CPU executes most of instructions in one clock cycle and achieves high performance comparable to a 16 bit microcomputers Table 2 1 1 Basic Specifications of CPU Load Store architecture Reaisters Data 8 bit x 4 9 Address 16 bit x 2 Structure SP 16 bits Others PC 21 bits PSW 8 bits Number of instructions 39
152. mode Set CPUM STOP to 1 Transition procedure from SLOW mode to STOP mode Set CPUM STOP to 1 Transition procedure from NORMAL mode to STOP1 mode Set CPUM STOP to 1 CPUM OSCMOD to 0 and CPUM CLKSEL to 0 at the same time while the low speed oscillation is stable Transition procedure from SLOW mode to STOPO mode Set CPUM STOP to 1 CPUM OSCMOD to 1 and CPUM CLKSEL to 1 at the same time NORMAL SLOW mode Transition to STOPO STOP1 mode Set the CPUM as described in Table 4 1 3 STOPO STOP1 mode Figure 4 2 12 Transition Flow from CPU Operating Mode to STOP Mode the value of PSW IM1 0 before transition to STANDBY mode it is impossible to return to a If the value of xICR LV1 0 for an interrupt to be used as a return factor is equal or larger than CPU operating mode by a maskable interrupt Mode Control Function Chapter 4 Clock Mode Voltage Control 4 2 4 Note for Transition to STANDBY Mode While PSW MIE is set to 1 if it can t be guaranteed that an interrupt for wakeup re occurs after the transition to STANBY mode since a maskable interrupt for wakeup has occurred before the transition to STANBY mode by setting the CPUM register CPU can not wake up from STANDBY mode Figure 4 2 13 shows the example that CPU can not wake up from STANDBY mode Therefore it is necessary to prevent CPU from accepting a maskable interrupt for wakeup before the transition to STANDBY mode T
153. of transmission buffer and wait for transmission completion Register name SCnSTR1 SCnTBSY SCnSTR1 SCnTEMP Repeat these procedures from step 1 to execute the next communication Description Confirm that both SCnSTR1 SCnTBSY and SCnSTR1 SCnTEMP become 0 When an interrupt is enabled a communication complete interrupt SCnTIRQ occurs Even in that case confirm that above two flags are 0 Setting of break transmission SCnMD2 SCnBRKE 1 Set a break transmission Data write to TXBUFn TXBUFn Set dummy data to TXBUFn Wait for a break transmission completion SCnSTR1 SCnTBSY SCnSTR1 SCnTEMP Confirm that both S CnSTR1 SCnTBSY and SCnSTR1 SCnTEMP become 0 When an interrupt is enabled a communication complete interrupt SCnTIRQ occurs Even in that case confirm that above two flags are 0 Release a break transmission SCnMD2 SCnBRKE 0 Release setting of a break transmission Break transmission end Full duplex UART Communication 55 Chapter 13 Serial Interface XIII 56 13 5 IIC Communication This section describes IIC communication The index of Interface denotes 2 3 unless otherwise noted When executing IIC communication with SCIFn set SCnMD3 SCnCMD to 1 13 5 1 Format W Transfer Format SCIFn supports 7 bit addressing format in which 7 bit slave addresses are sent following a start condition
154. of the 8 bit timer For PWM output pins refer to Table 8 1 1 W Count Timing of PWM Output at Normal Count 77 clock TMnEN bit Compare register carr Ot re rr on p eed dee counter A B TMnIO output PWM output lt n V Time set in the compare register PWM basic waveform overflow time of binary counter Interrupt request Figure 8 6 1 Count Timing of PWM Output at Normal When TMnPOP bit is 0 e A PWM output is High while TMnBC counts up from 0x01 to the setting value of TMnOC B PWM output changes to Low when TMnBC matches the setting value of TMnOC then TMnBC contin ues counting up until it overflows As for the initial setting the PWM output is changed from Low to High when setting the TMnMD TMnPWM when TMnPOP bit 0 to select the PWM operation 8 bit PWM Output VIII 25 Chapter 8 8 bit Timer W Count Timing of PWM Output when the compare register is 0x00 TMnEN bit Compare register counter TMnIO output PWM output Figure 8 6 2 Count Timing of PWM Output when the compare register is 0x00 W Count Timing of PWM Output when the compare register is OxFF TMnEN bit Compare register counter TMnIO output PWM output Figure 8 6 3 Count Timing of PWM Output when the compare register is OxFF LI When TMnMD TMnEN is 0 timer function is s
155. ook O 9 on r Z S 5 m 6 gt 2 gt 20 x x m 2 2 dg 40099 useem s gt zz 6 N G O D gt Tis 9 5 Figure 1 3 4 MN101LR02D Pin Configuration 1 14 Pin Description 1 3 2 Pin Description izu V S 81 Table 1 3 1 Power Supply Oscillation Reset Mode Pin Input noe Pin name Output Description VDD30 Power supply VSS Connect the capacitor of 1 uF or more between VDD30 and VSS Apply 0 V to VSS VDD18 Internal power output pin Connect the capacitor of 1 uF between VDD18 and VSS to stable Vpp18 Connect the bypass capacitor of 0 1 uF between VDD18 and VSS VDD11 Internal power output 1 1 V Connect the capacitor of 1 uF or more between VDD11 and VSS VLC1 LCD power supply pin VLC2 Supply the power under the following conditions VLC3 VDD30 lt VLC1 lt 3 6 V and 0 V lt VLC3 lt VLC2 lt VLC1 Capacitors described in Chapter 17 3 4 must be connected in each pin When LCD function is not used connect VLC1 to VDD30 C1 LCD voltage boost capacitor pin C2 When using the internal LCD booster circuit connect the capacitor of 0 22 uF between C1 and C2 VREFP ADC Reference power supply pin When is not used connect VREFP to VDD30 The voltage level of VREFP must be over 0 8 at any time including LSI power on OSC1 Input Externa
156. output voltage VDD18 PWCTRO Set VDDLV1 0 to 10 Set the oscillation stabilization wait For the oscillation stabilization wait and inter DLYCTR Pa and interrupt XXXICR rupt refer to 2 5 3 Oscillation Stabilization Wait Time and 8 3 External Interrupts respectively Transition to HALT2 mode CPUM Set to 00010101 NOP instruction Insert 3 NOP instructions IV 30 Voltage Control Chapter 4 Clock Mode Voltage Control 4 4 Mode Voltage Clock Transition The following Table 4 4 1 shows the state transition by changing the operation mode VDD18 voltage and clock The mode name in Table 4 4 1 is described in accordance with a rule below Operation mode VDD18 voltage SYSCLK Oscillating clock except SYSCLK Special mode SYSCLK is described in NORMAL SLOW IDLE HALTO or HALT1 mode Oscillating clock except SYSCLK or Special mode that corresponded to each condition is described For example NORMAL 18 HCLK SCLK NORMAL mode VDD18 1 8 V S YSCLK HCLK HOSC HRC SCLK SOSC SRC Oscillating HALT2 11 SCLK DEEP HALT2 mode VDD18 1 1 V SYSCLK Stop SCLK SOSC SRC Oscillating Deep STANDBY a The blanks in Table 4 4 1 mean the mode which setting is prohibited or cannot change Mode Voltage Clock Transition IV 31 Chapter 4 Clock Mode Voltage Control Table 4 4 1 Mode Voltage Clock Transition Destination mode NORMAL_18_HCLK IDEL_13_SCLK_HRC SLO
157. output with dead time set the values of TM7OC1 and 2 as follow TM7OC2 x TM7OC1 If TMnOC2 gt 1 the IGBT output are at the falling edge setting TM71O fixed to Low TM8IO fixed to Low If the IGBT trigger is enabled before 2 count clock cycles elapsed after the IGBT trigger is disabled the preset register data set during the IGBT operation may not be loaded to the compare register or the dead time preset register data set during the IGBT operation may not be reflected If the event input is selected as a count clock source the preset register data set during the IGBT operation may not be loaded to the compare register or the dead time preset register data set during the IGBT operation may not be reflected 1 Ifthe event input is selected as a count clock source the dead time preset register data not be reflected even if it is set when the IGBT operation is disabled To prevent this select the system clock SYSCLK as a count clock source at first and set the data to the dead time preset register Then select the event input TM7IO as a clock source to start IGBT opera tion When selecting IRQO 1 or 2 as IGBT trigger the IGBT operation may start at most one count clock before and after the usual start IGBT Output with Dead Time Chapter 9 16 bit Timer One shot Pulse Output Setting One shot pulse can be output by setting the TM7MD4 T7ONESHOT to 1
158. parity 00 Check 0 parity 01 Add 1 parity 01 Check 1 parity 10 Add odd parity 10 Check odd parity 11 Add even parity 11 Check even parity UART Parity addition enable control SCnNPE 0 Enabled 1 Disabled Interrupt trigger selection Selectable only in Clock Synchronous communication and always set 0 in UART SCnIFS communication 0 Communication completion interrupt 1 TXBUFn empty interrupt SCnPM1 0 UART Break reception monitor SCnBRKF 0 Data reception 1 Break reception UART Break transmission control SCnBRKE 10 Data transmission 1 Break transmission Control Registers XIII 15 XIII 16 Chapter 13 Serial Interface SCIFn 2 3 Mode Register 2 SC2MD2 SC3MD2 Bit name SCnFDC1 SCnFDC0 SCnRSTN SCnCKPH SCnSBCSEN SCnSBCSLV Initial value 0 0 0 0 0 0 Access Bit name SCnFDC1 0 Description Output level selection after the final bit of SBOn is transmitted 00 Fixed at 1 High output 01 Hold the final data 10 Fixed at 0 Low output 11 Setting prohibit SCnRSTN Serial reset control 0 Reset 1 Reset release 0 is always read out SCnCKPH Clock phase selection Selectable only in Clock Synchronous communication always set 0 in IIC communication 0 Data transmission at leading edge data reception at trailing edge 1 Data reception at leading edge data transmission
159. rd vn tas s i gt 434u0S H1SuoS uonoelep euie14 LH vn years Lu vi aos 0115 2571161025 uoioejes 195 1s snouoiuoSu S 4909 uolssiuisuen peppe A ued in i nz peppe dois u vn I i 13 s 8185709 1005 poppe iq uers auos s uoissiulsue 19 S1691 145 191516 145 A vulgs i vuogs D 4 1 1SWUuOS Lawuos 0135 05 1951005 u u u u 1199008199100 209895 0 1905 udnaxd E 0 LINdquoS zaWuos Jejinq uolssiwsues i 4 0 IN4uOS zqdWuOs koa guogs Y Woluos Lawuos VuO8S uiquos odWuos aS1 lt gt aSW dVMS 11195409 1951 0905 iagram 1311 SCIFn n 0 1 Block Di Figure XIII 5 Overview Chapter 13 Serial Interface AISOESUOS ZQNUOS N3SO8SuOS 05 Y LSWUOS LGNYOS Y us 5 Y 3tHiOuOS H 1SuOS uono l p 5 0019 a 1SOIluOS uono l p 1H1S OIl H 1SOlIuOS uonoejep 1
160. s stop condition is detected SCnSIRQ doesn t occur when it is generated by the LSI W Generating Start Restart Condition When SC3MDO IICSSTE is 1 a restart condition is generated by setting an address data consisting of 7 bit slave address R W bit to TXBUFn A start condition is generated by writing a address data to TXBUFn regard less of the value of SC3MDO IIC3STE Start Condition Setup Example 1 1 2 3 1 1 1 Start condition Slave address Restart condition Slave address Write slave address in TXBUFn Write slave address in TXBUFn Write data in TXBUFn after setting SCnMDO IIC3STE to 1 after setting SCnMDO IIC3STE to 1 after setting SCnMDO IIC3STE to 1 Figure 13 5 2 Setting Example of Start Condition Generating Stop Condition A stop condition is generated by writing 1 to SC3MD3 IIC3STPC When a stop condition is generated IIC3STPC is automatically cleared Note that a stop condition is generated by writing 1 to even if SCIFn is not a master In addition a stop condition detection interrupt SCnSIRQ does not occur when the LSI generates the stop condi tion IIC Communication 57 Chapter 13 Serial Interface W Detection of Start Restart Condition and Stop Condition When a start restart condition is detected SC3IICSTR IIC3STRT is set to 1 When the received slave address is equal to SCnAD SC3IICSTR IIC3STRT is cleared to 0 by setting data to TXBUFn durin
161. step are shown below XII 18 Setting RTC stops RTCCTR Description Set the CLKEN bit to 0 Alarm interrupt disabled RTCALOIRQ Set the ALOIRQSET bit to 0 Display mode setting RTCCTR Set the HDMD bit to 0 Clock data setting Set the clock data to 01 01 00 Thursday using the following registers RTCWD Set it to 0x04 RTCHD Set it to 0x01 RTCMID Set it to 0x01 Alarm interrupt enabled RTCALOIRQ Set the ALOIRQSET bit to 1 Alarm detection enabled Alarm time setting RTCALOIRQ Set the ALOIRQWEN ALOIRQHEN and ALOIRQMIEN bits to 1 Set the alarm time to 10 23 Saturday using the fol lowing registers ALOIROW Set it to 0x6 ALOIRQH Set it to 0x10 ALOIRQMI Set it to 0x23 Interrupt level setting All maskable interrupts disabled PSW PERIOICR Set the IE bit to 0 Set the PERIOLV1 0 bits to 00 Clear the corresponding interrupt request bit of PERIODT register if it may have already been set Refer to 3 1 5 Set up procedure for Interrupt control register for peripheral function group Alarm 0 Interrupt enabled PERIOEN Set the PERIOENB bit to 1 Refer to Chapter 3 Interrupts Maskable interrupts enabled PSW Set the IE bit to 1 RTC starts RTCCTR For PSW refer to Chapter 2 CPU For PERIOICR and PERIOEN refer to Chapter 3 Interrup
162. the DMOVF is set to 1 4 DMOVF The DMOVF is cleared to 0 by writing DMCTR1L DMTEN 0 Not Detect 1 Detect 3 1 Always read as 0 DMA Busy monitor The DMRGF is set to 1 when the DMA start trigger occurs 0 DMROF In the case of the single transfer the DMRQF is cleared to 0 at the end of single data transfer In the case of the burst transfer the DMRQF is cleared to 0 at the end of the last burst data transfer 0 Not Busy 1 Busy DMA Controller Control Registers 14 2 2 Source Address Register DMA Source Address Register lower side DMSRCL 0x03E04 Chapter 14 DMA Controller bp 7 6 5 4 3 2 1 0 Bit name DMSA7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description Source address lower side bit 0 to 7 7 0 DMSA7 0 This register shows the address where the next data to be loaded is contained Source Address Register middle side DMSRCM 0x03E05 bp 7 6 5 4 3 2 1 0 Bit name DMSA15 8 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description Source address middle side bit 8 to 15 7 0 DMSA15 8 gt This register shows the address where the next data to be loaded is contained DMA Source Address Register upper side DMSRCH 0x03E06 bp 7 6 5 4 3 2 1
163. the flow diagram of transi tion to from STANDBY mode Before the transition to STANDBY mode the following settings are required 1 Set the PSW MIE and xICR IE to 0 to disable all maskable interrupts 2 Select the interrupt source to wake up CPU from STANBY mode and set only the corresponding xICR IE to 1 Set the PSW MIE to 1 3 Set STANBY mode in the CPUM NORMAL SLOW Set PSW MIE to 0 Disable all interrupts and set all interrupt enable bits xICR IE to Enable interrupt which Set the xICR IE of the return factor to 1 triggers return and set PSW MIE to 1 Set HALT STOP mode i Watchdog timer HALT STOP HALTO 1 2 3 continue counting V mode STOP stop counting Interrupt of return factor occured When returning from HALT2 STOP mode wait for oscillation to stabilize Watchdog timer NORMAL SLOW HALT0 1 2 3 continue counting mode STOP restart counting Interrupt service routine Y Figure 4 2 9 Transition to from STANDBY Mode Mode Control Function IV 19 Chapter 4 Clock Mode Voltage Control IV 20 m Transition to HALT Mode The system can change from any mode of NORMAL and SLOW to HALTO HALTI HALT2 HALT3 mode In mode CPU is stopped operating while the oscillators remain active In HALT2 HALT3 mode only the low speed oscillator remains
164. the prescaler CKOMD TMOPSC1 0 Select SYSCLK 2 CKOMD TMOBAS 1 Set the interrupt cycle OxF9 Set the cycle of timer interrupt Setup value 249 OxF9 Set the interrupt level TMOICR TMOLV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Enable the interrupt TMOICR TMOIE 1 Enable the timer counter TMOMD TMOEN 1 Enable the timer count operation 8 bit Timer VIII 19 Chapter 8 8 bit Timer VIII 20 8 4 8 bit Event Count 8 4 1 Operation In the event count operation an external input as a count clock can be counted 8 bit Event Count Operation In the event count operation TMnBC counts the input signal to the TMnIO pin from the external When the value of TMnBC matches the setting value of timer n compare register an interrupt request is generated at the next count clock For event count input clock of each timer refer to Table 8 1 1 W Count Timing of TMnIO Input When TMnIO input is selected TMnIO input becomes the count clock of Timer n The binary counter starts counting up at the falling edge of the TMnIO input signal TMnlO input TMnEN bit Compare register m s P counter Interrupt request Figure 8 4 1 Count Timing of TMnIO Input 8 bit Event Count Chapter 8 8 bit Timer When is read on the operation uncertain value on counting up may be read Writing th
165. till the interrupt request 1 If the timer interrupt request bit may have already been set before the timer starts the timer interrupt request bit should be cleared 8 bit Timer VIII 17 Chapter 8 8 bit Timer quency oscillation clock HCLK or the prescaler output TMnPSC is selected as a clock source stop the timer before the mode transition After the mode transition activate the timer again In the SLOW HALT1 mode do not select HCLK or any clock generated from HCLK as a timer clock source 1 When changing the CPU operation mode from NORMAL to SLOW while the high fre 1 When is set to 00 clear TMnBC before starting the timer operation 18 8 bit Timer Chapter 8 8 bit Timer 8 3 2 Setup Example W Timer Operation Setup Example Timer 0 to Timer 5 Here is an example that the periodic interrupt of Timer 0 is generated to execute the timer function An interrupt is generated every 250 cycles 200 us by selecting SYSCLK 2 at fsyscik 2 5 MHz operation a clock source The setup procedure and the description of each step are shown below Setting Description Disable the timer counter TMOMD TMOEN 0 Disable the timer count operation Disable the interrupt TMOICR TMOIE 0 Disable the timer interrupt Set the timer mode register TMOMD TMOPWM 0 Select the normal timer operation TMOMD TMOMOD 0 TMOMD TMOCK1 0 01 Select the clock source Set
166. times the LCD reference voltage W 3 2 or 1 2 Times Boosting Specification deletion W 3 2 or 1 2 Times Boosting When BSTVOL generates 3 2 or 1 2 times Note Specification deletion In 3 2 or 1 2 times boosting the condi tion Table 17 3 3 Record of Changes 5 Specification deletion 3 2 1 2 times boost Inquiries If you have questions regarding technical information on this manual please visit the following URL Panasonic Corporation URL http www semicon panasonic co p en Microcomputer Home Page http www semicon panasonic co jp e micom MN101LR05D 04D O3D O2D LSI User s Manual October 7 2013 1st Edition 5th Printing Issued by Panasonic Corporation O Panasonic Corporation 2013 Semiconductor Business Division Automotive amp Industrial Systems Company Panasonic Corporation 1 Kotari yakemachi Nagaokakyo City Kyoto 617 8520 Japan Tel 81 75 951 8151 http www semicon panasonic co jp en 010413 Printed in Japan Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Panasonic MN101LR04DXW MN101LR05DXW
167. to STANDBY mode must not executed in the internal RAM IV 24 Mode Control Function Return factor interrupt occured 2 Return factor interrupt detected z NORMAL SLOW mode Enable interrupt which triggers return Set HALT STOP mode mode HALT STOP When the transition corresponds to 1 in Figure 4 2 1 the oscillation stabilization wait time is inserted NORMAL SLOW mode Enable maskable interrupts Setti Enable writing in the MEMCTR interrupt request flag IRWE 1 Rewrite the interi xICR rupt request flag R 0 Disable writing of the MEMCTR interrupt request flag IRWE 0 Execute following program Chapter 4 Clock Mode Voltage Control Disable maskable interr Set the PSW MIE to 0 Sable maskable Interrupts and set all interrupt enable bits xICR IE to 0 Set the xICR IE of the return factor to 1 Watchdog timer HALT0 1 2 3 continue counting STOP stop counting Watchdog timer HALT0 1 2 3 continue counting STOP restart counting he PSW MIE to 1 Y Figure 4 2 15 Operation in STANDBY Mode and Interrupt Non acceptance Sequence with Interrupt Disabled Set the PSW MIE to 0 before the transition to STANDBY mode Insert 3 NOP instructions right after the instruction for the transition to STANDBY mode set ting to CPUM HALT or CPUM STOP The i
168. with I O short addressing A A 256 B 0 00000 RAM short addressing area 000100 Oo ae a Internal RAM 4 KB 0x01000 16 KB 4KB 0x03000 Special function register area 256 0x03F00 a E ian 094000 Interrupt A vector table BANKO 0x04080 Subroutine 64 vector table 904060 Instruction code 48 KB 0x04100 Data 0x04900 Internal ROM 64 KB lt gt lt 0x10000 Instruction code Table data 0x13FFF BANK1 64 KB Y Y 1 Figure 2 1 5 Address Space Overview 1 7 Chapter 2 CPU The value of internal RAM is uncertain when power is applied to it It needs to be initialized 1 before using mented space where memory ROM special function register others not 1 There s no guarantee of proper operation when an access is executed to the non imple arranged Don t allocate the instruction code to a special function register area And this area cannot 1 use as stack area 8 Overview Chapter 2 2 1 8 Addressing Modes OOOO The AM13L microcomputer core supports the 9 addressing modes Each instruction uses a combination of the following addressing 1 Register direct Immediate Register indirect Register relative indirect Absolute RAM short 2 3 4 5 Stack relative indirect 6 7 8 I O short 9 These addressing modes are well suited for language compilers Fo
169. 0 Access be Bimme _ j Always read as 0 Alarm 1 Day setting AL1IRQD5 0 Set a value within the range of 01 to 31 using the BCD format The value which doesn t exist must not be set 8 Control Registers Chapter 12 Real Time Clock RTC W Alarm 1 Month Setting Register AL1IRQMO 0x03EDB Bit name AL1IRQMO4 0 At reset Access Always read as 0 Alarm 1 Month setting AL1IRQMO4 0 Set a value within the range of 01 to 12 using the BCD format The value which doesn t exist must not be set Alarm 1 interrupt is not guaranteed if the prohibited value is set in AL1IRQMI AL1IRQH 1 AL1IRQD and AL1IRQW RTCAL1IRQ AL1IRQMI AL1IRQH AL1IRQD and AL1IRQW must be set when RTCAL1IRQ AL1IRQSET is 0 Control Registers XII 9 Chapter 12 Real Time Clock RTC XII 12 2 4 Periodic Interrupt Control Register W Periodic Interrupt Control Register RTCCIRQ 0x03ED2 ope ee 404 mmm At reset 0 GROFEN GROMEN 0 0 0 0 0 0 0 Access Bit name CIRQHEN R W R W R W R W Description Always read as 0 Periodic interrupt control The periodic interrupt is generated every hour 0 Disable 1 Enable CIRQMIEN Periodic interrupt control The periodic interrupt is generated every minute 0 Disable 1 Enable CIRQSEN Periodic i
170. 0 PC bp19 16 mem8 SP 4 gt mem8 SP 5 gt HA h 5 6 gt 5 2 gt imm3 1 Execution Cycle max 6 d 3i 6 20 21 max 4 2d i 6 2 1111 1110 lt 4 gt 0000 0001 0000 0011 0000 0000 0010 0001 1 Machine Code BE PSW amp PSW 0010 0010 0000 BD PSW xC0 PSW 0010 0011 0000 1 When the value of SP is odd number the execution cycle is added 1 d 2 imm 1 repeat count 0 rep imm3 1 Other than the instruction of MN101L Series the assembler of this Series has the following 10 1 instructions as macro instructions assembler will interpret the macro instructions below as the assembler instructions Instruction set macro instructions replaced instructions remarks on pn INC DEC Dn Dn DD DD INC An DDW DEC An DDW INC2 An Dn 1 gt zZz gt gt gt gt gt gt gt DWn DWm SP Dm 0 SP Dm Dn SP Dn 0 SP SP DWm 0 SP DWm DWn SP DWn 0 SP SP Am 0 SP Am An SP An 0 SP 20 3 Instruction map MN101L SERIES INSTRUCTION MAP 1st nibble 2nd nibble m O O PP o o O N 20 Appendix
171. 0 Bit name DMSA16 At reset 0 0 0 0 0 0 0 0 Access R R R R R R R R W bp Bit name Description 7 1 Always read as 0 Source address upper side bit 16 0 DMSA16 This register shows the address where the next data to be loaded is contained DMA Controller Control Registers XIV 9 Chapter 14 DMA Controller 14 2 3 Destination Address Register B SS SSS SSS Destination Address Register lower side DMDSTL 0x03E08 bp 7 6 5 4 3 2 1 0 Bit name DMDA7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description Destination address lower side bit 0 to 7 7 0 DMDA7 0 This register shows the address where the next data from source address is stored DMA Destination Address Register middle side DMDSTM 0x03E09 bp 7 6 5 4 3 2 1 0 Bit name DMDA15 8 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 DMDA15 8 Destination address middle side bit 8 to 15 This register shows the address where the next data from source address is stored Destination Address Register upper side DMDSTH 0x03E0A bp 7 6 5 4 3 2 1 0 Bit name DMDA16 At reset 0 0 0 0 0 0 0 0 Access R R R R R R R R W bp Bit name Description 7 1 Always read as 0 0 DMDA16 Destination address uppe
172. 0 1 Symbol Definitions Following is the list of symbols used in the instruction specifications Nibble 15 unit for expressing size and a nibble is equivalent to half byte 4 bits Reg Reg1 Reg2 register used for general meaning Dn Dm Data register 8 bits DWn DWm DWk Data register 16 bits DWn l Lower 8 bits of 16 bit data register DWn h Higher 8 bits of 16 bit data register An Am Address register 16 bits PSW Processor Status Word 8 bits PC Program Counter 21 bits SP Stack Pointer 16 bits HA Handy Address 16 bits Lower 8 bits of Address HA h Higher 8 bits of Handy Address abs Absolute address used for general meaning abs8 Absolute address 8 bits abs12 Absolute address 12 bits abs16 Absolute address 16 bits abs18 Absolute address 18 bits abs20 Absolute address 20 bits Memory space specified by the contents of the parentheses imm immediate value used for general meaning imm3 Immediate value 3 bits imm4 Immediate value 4 bits imm8 Immediate value 8 bits imm16 Immediate value 16 bits tbl4 Table address 4 bits d4 Displacement 4 bits d7 Displacement 7 bits d8 Displacement 8 bits XX 2 Symbol Definitions 412 416 bp bpdata bpn sb msb 108 IOTOP lt lt n gt gt n VF NF CF ZF temp label Mem mem8 xxx Dis
173. 0 3 to 0 3 up to 4 6 Output pin voltage Vo 0 3 to 0 3 up to 4 6 V A4 Input Output pin voltage 0 3 to 0 3 up to 4 6 AS avs E lout peak 30 Peak output current p4 g loL2 peak 10 All pins peak 10 B Average output O x mA A9 current 1 P1 8 loi avg 5 A10 All pins avg 5 11 Total output current for all pins ToL 60 12 1 ITOH 60 A13 Power dissipation 230 85 mW A15 Storage temperature Tstg 55 to 125 The values are applied to any period of 100 ms To stabilize the internal power supply voltage connect bypass capacitors as follows to at least one or more points close to the LSI Capacitors of 1uF or more between VDD30 and VSS Capacitors of 0 1 uF and 1uF or more between VOUT18 and VSS The absolute maximum ratings are the limit values beyond which the IC may be damaged Operation is not guaranteed under these conditions The value is applied when selecting the large current output by setting PnNLC register Electrical Characteristics 1 4 s B Operating Condition Chapter 1 Overview 2 Operating Condition Vss 0 V Ta 40 C to 85 C Limits Parameter Symbol Condition Unit MIN TYP MAX Supply voltage 5 B1 fsvscuk lt 10 0 MHz 1 8 3 6 B2 Supply voltage Vpp2 l
174. 0 interrupt 1 Timer 1 interrupt Binary counter clear enable at capture T7CAPCLR 0 Disabled not cleared 1 Enabled cleared The TM7MD4 T7CAPCLR is valid when the timer is in active Note that the binary counter is Y not cleared when capturing data while the timer is stopped Set the Timer 7 mode registers while the TM7MD1 TM7EN is 0 And the TM7MD1 TM7EN Y must not be changed at the same time as the other bit 16 bit Timer Control Registers IX 13 Chapter 9 16 bit Timer W Timer 8 Mode Register 1 TM8MD1 0x03FB8 Bit name T8ICEDG1 At reset 0 Access Bit name Always read as 0 Description Select capture trigger edge T8ICEDG1 0 Falling edge 1 Rising edge Timer output enable 0 Enabled 1 Disabled reset Control timer count 0 Disabled 1 Enabled Select count clock 00 1 1 clock TM8PS1 0 01 1 2 clock 10 1 4 clock 11 1 16 clock Select clock source 00 HCLK TM8CK1 0 01 SYSCLK 10 TM8IO input 11 SCLK IX 14 16 bit Timer Control Registers W Timer 8 Mode Register 2 TM8MD2 0x03FB9 Bit name T8ICEDG0 T8PWMSL TM8BCR TM8PWM TM8IRS1 T8ICEN Chapter 9 16 bit Timer At reset 0 0 0 0 0 0 Access Bit name T8ICEDG0 Description Select capture trigger edge 0 Both edges 1 Specified edge T8PWMSL Select PWM mode 0 Set duty through TM8
175. 000 1 1 Static 001 1 2 010 1 8 011 1 4 100 1 5 101 1 6 110 1 7 111 1 8 Control Registers XVII 7 Chapter 17 LCD m LCD Mode Control Register LCDMD3 0x03E83 Bit name Reserved LCCKS2 0 At reset 0 0 Access Bit name Reserved Must be set to 0 Description LCCKS2 0 LCDCLK selection 0000 LCDCLKS 23 0001 LCDCLKS 24 0010 LCDCLKS 25 0011 LCDCLKS 28 0100 LCDCLKS 27 0101 LCDCLKS 28 0110 LCDCLKS 29 0111 LCDCLKS 210 1000 LCDCLKS 2 1001 LCDCLKS 212 1010 1111 Setting prohibited LCDCLKS selection 000 SCLK Low speed clock 001 HCLK High speed clock 24 010 HCLK High speed clock 2 011 HCLK High speed clock 26 100 HCLK High speed clock 27 101 HCLK High speed clock 28 110 111 Setting prohibited LCD Mode Control Register 4 LCDMD4 0x03ECE Bit name Reserved At reset 0 Access Must be set to 0 LCUPMD XVII 8 Control Registers BSTVOL boost voltage selection 0 Three times voltage boost 1 Two times voltage boost Chapter 17 LCD 17 2 2 LCD Port Control Registers JES pis a a LCD port control registers are described the control bits for each product m LCD Port Control Register 0 LCCTR0 0x03E86 Bit name SEGSL3 SEGSL2 SEGSL1 SEGSLO COMSL3 C
176. 03 Always read as 0 Clock source select 000 HCLK 4 010 HCLK 16 TM5PSC1 0 2100 TM5BAS 100 HCLK 64 110 HCLK 128 X01 SYSCLK 2 X11 SYSCLK 8 8 bit Timer Control Registers VIII 7 Chapter 8 8 bit Timer VIII 8 8 2 2 Programmable Timer Registers Rupa r The programmable timer register consists of timer compare register and timer binary counter TMnBC Timer n Compare Register 0x03F72 1 0x03F73 TM2OC 0x03F82 0x03F83 TMAOC 0x03F92 TM5OC 0x03F93 Timer n compare register is an 8 bit register which stores a value compared with timer n binary counter bp Bit name At reset Access TMOOC TM3OC and TM2OC TM5OC and 4 must be accessed simultaneously with a When setting the compare register in cascade connection pair of registers TM1OC and 16 bit access instruction MOVW W Timer n Binary Counter TMOBC 0x03F70 TM1BC 0x03F71 2 0x03F80 TM3BC 0x03F81 TM4BC 0x03F90 TM5BC 0x03F91 Timer n binary counter is an 8 bit up counter If any data are written to the timer n compare register while the counter is stopped the timer n binary counter is cleared to 0x00 bp Bit name At reset Access and TMOBC TM3BC and TM2BC TM5BC and TM4BC must be accessed simultaneously lt When reading the value of TMnBC register in ca
177. 03EE2 Bit name At reset Access Bit name Description Always read as 0 setting 0 1 24 hour clock mode bit setting of the HD6 is ignored Hour setting lt 24 hour clock mode gt Set a value within the range of 00 to 23 using the BCD format The value is incremented by one from 00 to 23 per hour In 12 hour clock Set a value within the range of 00 to 11 using the BCD format The value is incremented by one from 00 to 11 per hour The value which doesn t exist must not be set HD5 to 0 m Day of Week Setting Register RTCWD Bit name At reset Access Bit name Description Always read as 0 Day of the week setting 000 Sunday 001 Monday 010 Tuesday 011 Wednesday 100 Thursday 101 Friday 110 Saturday 111 Setting Prohibited The value is incremented by one from 000 to 110 per day WD2 to 0 XII 12 Control Registers Chapter 12 Real Time Clock RTC m Day Setting Register RTCDD 0x03EE4 Bit name At reset Access Bit name Description Always read as 0 Day setting Set a value within the range of 01 to 31 using the BCD format The value is incremented by one from 01 to 31 per day The value which doesn t exist must not be set DD5 to 0 Month Sett
178. 0L 0x03E00 DMA control register0 lower side MCTR0H 0x03E01 DMA control register0 upper side MCTR1L 0x03E02 DMA control register1 lower side MCTR1H 0x03E03 DMA control register1 upper side MSRCL 0x03E04 DMA source address register lower side MSRCM 0x03E05 DMA source address register middle side MSRCH 0x03E06 DMA source address register upper side MDSTL 0x03E08 DMA destination address register lower side MDSTM 0x03E09 DMA destination address register middle side MDSTH destination address register upper side MCNTL 0x03E0C DMA transfer word count register lower side MCNTH 0x03E0D DMA transfer word count register upper side R W Readable and Writable R Readable Setup data of DMA control registers except DMCTR1L in Table 14 2 1 must not be changed Y when the DMCTR1L DMTEN is 1 In STOP HALT2 HALT3 mode DMA cannot be used Y Halt DMA before entering STOP HALT2 HALT3 mode XIV 4 Controller Control Registers 14 2 1 DMA Control Register c TO rJ m DMA Control Register 0 lower side DMCTR0L 0x03E00 Chapter 14 DMA Controller bp Bit name DMSAM DMBG4 0 At reset 0 Access R W R R W R W R W R W R W bp Bit name Description DMSAM Source Address increment control 0 Enable Incremented 1 Disable Fixed
179. 1 1 16 Overview Chapter 3 Interrupts 3 1 4 Group Interrupt Control Register Setup uso Ya EJ Setup PERInDT n 0 1 by Software The each bit of the PERInDT is set to 1 by the hardware and software and cleared to 0 only by software When the interrupt occurs the corresponding bits 15 set to 1 and the maskable interrupt occurs depending on the setting of the each bit of PERInEN Above bits can be set to 1 by software and it generates the maskable interrupt Unlike xICR IR each bit of PERInDT 15 not cleared by hardware and needs to be cleared by software The each bit of PERInDT is changed as the following table Value before write Write data Value after write Value change Not changed Bit is set Not changed Bit is cleared When clearing all bits of the PERInDT read the value of PERInDT first and then write the same value to PERInDT lt Each bit of PERInDT is not cleared by hardware and needs to be cleared by software Don t change the bit of PERInICR while the corresponding bit of the PERInEN and the InDT is 1 When changing PERInICR the interrupt may be accepted unintentionally lt When the two events one is that an interrupt trigger causes PERInDT DTm to be set to 1 and the other is that PERInDT DTm is set or cleared by software occur at the same time the value of software is set in PERInDT Dm Over
180. 1 Internal high speed oscillation stabilization wait time 15 us Switching the source oscillation of HCLK HCLKCNT HCLKSEL 0 NORMAL mode SYSCLK HRCCLK Figure 4 2 5 Clock Change Flow from HOSCCLK to HRCCLK IV 16 Mode Control Function Chapter 4 Clock Mode Voltage Control 4 2 2 SLOW Mode m Transition from NORMAL to SLOW Figure 4 2 6 shows the mode transition procedure from NORMAL to SLOW The low speed clock oscillation is enabled in the low speed oscillation clock control register SCLKCNT Fig ure 4 1 1 shows the Operation Enable signal for external slow speed oscillation circuit or internal slow speed oscillation circuit NORMAL mode NO CPUM XIMOD 1 Y Start the low speed oscillation CPUM XIMOD 1 YES v The low speed oscillation stabilization wait time Transition to SLOW mode Set the CPUM as described in Table 4 1 3 When SCLKCNT SOSCCNT 1 SOSCCLK starts Wh LKCNT SRCCNT 1 SRCCLK SLOW mode SCLKCNT SRCC SRCCLK starts Figure 4 2 6 Transition Flow from NORMAL Mode to SLOW Mode The oscillation stabilization wait time should be determined in consultation with the manufac 1 turer of oscillator Mode Control Function 17 Chapter 4 Clock Mode Voltage Control Clock Change from SRCCLK to SOSCCLK Figure 4 2 7 shows the clock change procedure from SRCCLK to SOSCCLK SLOW mode SYSCLK SRC
181. 1 2 XVII 31 17 4 5 LCD Display Example 1 3 duty sese XVII 32 17 4 6 LED Operation Setup 1 3 duty eei et ete iere XVII 34 17 4 7 LCD Display Example 1 4 XVII 35 17 4 8 LCD Operation Setup 1 4 XVII 37 Chapter TS ReERAM des XVIII 1 18 1 Overview of R RAM one ete XVIII 2 18 1 1 ReRAM Rewriting XVIII 2 19 12 ReRAM Area dig eto eee idee ipe inr dee or reos XVIII 3 18 1 3 Data Protection Function XVIII 3 18 2 Self programming Rewriting nennen nennen XVIII 4 18 2 1 Procedures for XVIII 5 18 2 2 Interrupts during Programming 2 2 nennen nennen nennen XVIII 5 18 3 ReRAM Control Registers eret titor tet pe HE XVIII 6 18 4 Command Library ert o e E EE ERE petto HERR 7 lt Contents 9 gt Chapter 19 On Board Debu g8ger XIX 1 19 T OVerview cto tento tea EE IIO DE OT Hed XIX 2 19 2 List of on board debugging functions nn nennen nennen nne eene XIX 3 Chapter 20 Appendix 1 20 1 Symbol Definitions n eite tente teret pe tree Pere h u a XX 2 20 2 Instruction RR n eR ia aes XX 5 20 3 Instr ction m p
182. 1 TM4IOA TM7IOB NBUZA Output Yes changed P35 SEG30 SBI0B RXDOB Yes P36 SEG29 SBO0B TXD0B Yes P37 SEG28 SBTOB Yes 1 16 Pin Description Chapter 1 Overview Pin Input Output Function drive strength Description name Output selectable 40 5 27 5 50 Yes Port 4 At each port the I O direction and the pull up resistor 41 SEG26 SBI2A Yes connection is controlled individually P42 SEG25 SBO2A SDA2A Yes At LSI reset each pin is set to input mode and the pull up resistor is not connected P43 SEG24 SBT2A SCL2A Input Yes The drive strength of output Nch transistor can be P44 SEG23 SBCS2A Output Yes changed P45 SEG22 SBI1B RXD1B Yes P46 SEG21 SBO1B TXD1B Yes 47 SEG20 SBT1B Yes P50 SEG19 SBCS1B Yes Port 5 At each port the I O direction and the pull up resistor 51 SEG18 SBISB Yes connection is controlled individually P52 SEG17 SBO3B SDA3B Yes At LSI reset each pin is set to input mode and the pull up resistor is not connected P53 SEG16 SBT3B SCL3B Input Yes The drive strength of output Nch transistor can be 54 SEG15 KEY0B SBCS3B Output Yes changed P55 SEG14 KEY1B TM1IOA Yes P56 SEG13 KEY2B TM3IOA Yes P57 SEG12 KEY3B TM8IOA CLKOUTB Yes P60 SEG11 IRQ0B Yes Port 6 At each port the direction and the pull up resistor P61 SEG10 IRQ1B Yes connection is controlled individually P62 SEG9 IRQ2B Yes At LSI reset each pin is set to input mode and the pull up
183. 1 or 1 N BRTM count clock HCLK 2 a 0 1 2 3 4 5 6 7 8 SCLK 2 b 0 1 2 3 4 5 6 7 8 SYSCLK 2 c 0 1 2 3 4 5 6 First transfer bit MSB first or LSB first Address format 7 bit address General call address Communication mode Standard mode 100 kHz High speed mode 400 kHz Interrupt SCnTICR SCnSICR Chapter 13 Serial Interface 13 1 2 Block Diagram 1elod us JeisiDe1 105 US WlH8 N3 WlH8 106 8 108 1 1ndino 319 49 Wiug d 05 1 aK S 4 21 lt P _ us W1Hg QW S 19os diuo AIQUOS LQNUOS 49 E9S9J i 1SWuOS Lawuos 99d I wwouos Lanuos 513 49 15 109 1 diu Jo31uoo 3 guias 3HHOuOS H1 SU2S uonoejep unueAQ Hvf snouoJupu S Y49009 i MaduOS u1suog uoroejep ued
184. 13 1 3 Table 13 1 4 and Table 13 1 5 show the serial interface functions Table 13 1 3 Functions of Clock Synchronous Communication SCIF0 SCIF1 SCIF2 SCIF3 Transfer clock SCIF0 SCIF1 Generated by dividing BRTMn output clock by 1 8 or 16 SCIF2 SCIF3 Generated by dividing BRTMn output clock by 1 Duty of BRTM output clock 1 1 BRTM count clock HCLK 2 a 0 1 2 3 4 5 6 7 8 SCLK 2 b 0 1 2 3 4 5 6 7 8 SYSCLK 2 c 0 1 2 3 4 5 6 First transfer bit MSB first or LSB first Clock polarity amp phase selection 2 3 4 communication Consecutive communication Interrupt SCnTICR Table 13 1 4 Functions of UART Communication SCIF0 SCIF1 Transfer clock Generated by dividing BRTMn output clock by 8 or 16 Duty of BRTM output clock 1 1 or 1 N BRTM count clock HCLK 2 0 1 2 3 4 5 6 7 8 SCLK 2 b 0 1 2 3 4 5 6 7 8 SYSCLK 2 c 0 1 2 3 4 5 6 First transfer bit MSB first or LSB first Number of transfer bit 7 or 8 bits Number of Stop bit 1 or 2 bits Parity bit 0 parity 1 parity Odd parity Even parity Interrupt SCnTICR SCnRICR Overview 3 Chapter 13 Serial Interface XIII 4 Overview Table 13 1 5 Functions of IIC Communication SCIF2 SCIF3 Transfer clock Generated by dividing BRTMn output clock by 8 Duty of BRTM output clock 1
185. 16 bit Timer Capture F nc ti n IX 39 9 8 1 Opetation aaa yaa P ordi mp IX 39 9 8 2 Setup Examples u E ge 46 9 9 16 bit Standard IGBT Output with Variable Duty 0 00 cece cess IX 47 9 9 15 2 ge et tube uiui cbe fee eo pre IX 47 9 9 Setup Example s s aba S teneienis IX 50 9 10 16 bit High Precision IGBT Output with Variable Period Duty sse IX 51 9 10 1 Operation i oer e t eee Pre irte Ot tet IX 51 9 10 2 Setup 25 Dp HDi IX 57 9 11 IGBT Output with Dead Time genet eerie tret rere itp IX 58 9441 Operation i aote ce e STR e ee Re ed IX 58 9 11 2 Set p Example oett de pte ide ec dpt e p ien IX 62 Chapter 10 General Purpose Time Base Free Running Timer 1 10 1 OVerview o e o HR RERO ETE TP DURER DARE pr 2 10 1 1 Functions rib ete ete Pete o Sete t e RE I Report his 2 10 12 Block Diagram fepe Hee asua HE 3 10 2 Control R gistets re te he c A bere e X 4 10 21 Control Registers ones epe Ree EAE Sun X 4 10 2 2 Programmable Timer Registers 2 2 2 01 000000000 nre entren 5 10 2 3 Timer 6 Enable Register X 6 10 2 4 Timer Mode Registers sci tee ca ete ere e tete e rh aaa AiG
186. 2IICST R SC3IICST R RXBUF2 TXBUF2 0x03E6X SC3MDO SC3MD1 SC3MD2 SC3MD3 SC3AD Reserved SC3STR RXBUF3 TXBUF3 0x03E7X _ BRTM_S_ BRTM_ _ _ Reserved Reserved _ BRTM_ BRTM_ BRTM_ S_MD EN S_CKSEL 01_ S23 CK 50 1 52 53 0x03E8X LCDMD0 LCDMDT LCDMD2 LCDMD3 LCCTRO LCCTRT LCCTR2 LCCTR3 LCCTR4 LCCTR5 LCDSEL 0x03E9X LCDATA0 LCDATAT LCDATA2 LCDATA3 LCDATA4 LCDATA5 LCDATA6 LCDATA7 LCDATA8 LCDATA9 LCDATAT0 LCDATATT LCDATA12 LCDATAT3 LCDATAT4 LCDATA15 LCDATA16 LCDATA17 LCDATA18 LCDATA19 LCDATA20 LCDATA21 LCDATA22 LCDATA23 LCDATA24 LCDATA25 LCDATA26 LCDATA27 LCDATA28 LCDATA29 LCDATA30 LCDATA31 0x03EBX LCDATA32 LCDATA33 LCDATA34 LCDATA35 LCDATA36 LCDATA37 LCDATA38 LCDATA39 LCDATA40 LCDATA41 LCDATA42 PONLC P2NLC P3NLC P4NLC P5NLC P6NLC P7NLC LCDMD4 Reserved RTCCTR ATCCIRG CALOR ALTIROM Q AL0IRQMI ALOIRQH ALOIRQW Q AL1IROMI AL1IRQH AL1IRQD RTCSD RTCMID RTCHD RTCWD RTCDD RTCMOD RTCYD TBTCNTO 1 TBTADJL TBTADJH Reserved CPUM MEMCTR WDCTR DLYCTR HCLKCNT SCLKCNT AUCTR Reserved SBNKR DBNKR Reserved Reserved 0x03F1X POOUT P1OUT P2OUT P3OUT P4OUT P5OUT P6OUT P7OUT Reserved SC01SEL SC23SEL Reserved Reserved 0x03F2X
187. 3 Serial Interface 13 2 9 BRTM Operation Enable Register m Operation Enable Register BRTM S EN bp 3 2 1 0 BRTM 53 BRTM 52 BRTM 51 BRTM SO EN EN EN EN Initial value 0 0 0 0 Access R R R R R W R W R W R W Bit name Bit name Description 0 is always read out count operation BRTM_S3_EN 0 Disabled 1 Enabled BRTM2 count operation BRTM S2 EN 0 Disabled 1 Enabled BRTM1 count operation BRTM S1 EN 0 Disabled 1 Enabled BRTMO count operation BRTM 50 EN 0 Disabled 1 Enabled Control Registers 23 Chapter 13 Serial Interface 13 2 10 BRTM Clock Select Register m BRTM Base Clock Select Register BRTM S CKSEL Bit name BRTM_ S3_CKSEL BRTM_ S2 CKSEL _ S1_CKSEL Initial value 0 0 0 Access R W R W R W Bit name Description 0 is always read out BRTMS base clock 0 HCLK 1 SCLK BRTM2 base clock 0 HCLK 1 SCLK BRTM1 base clock 0 HCLK 1 SCLK base clock 0 HCLK 1 SCLK BRTM_S3_CKSEL BRTM_S2_CKSEL BRTM_S1_CKSEL BRTM_S0_CKSEL XIII 24 Control Registers Chapter 13 Serial Interface m BRTM01 Count Clock Select Register BRTM_S01_CK Bit name Initial value Access Bit name BRTM1 count clock selection 0000 0001 0010 0011 0100 0101 0110
188. 3 1 j SEG35 LCDATA36 0x3EB4 111 gt SEG36 LCDATA37 Ox3EB5 11 1 SEG37 LODATA39 0X3EB7 S 2 550 LCDATA39 Ox3EB7 SEG39 LCDATA40 0x3EB8 1 11 SEG40 LCDATA41 Ox3EB9 SEG41 LCDATA42 L 1 bL d SEG42 Figure 17 2 1 Correspondence of segment output latch and segment common pins XVII 16 Control Registers Chapter 17 LCD 17 3 Operation 17 3 1 LCDDRV Operation LCDDRV displays data with SEGn and COMn in static 1 2 duty with 1 2 bias or 1 3 to 1 8 duty with 1 3 bias When LCDDRV is turned off the voltage of Vy c is output from COMn and SEGn a At reset all the common and segment pins are in high impedance LCDDRV can t be used when the LSI is in STOP mode Y Before transiting to STOP mode the following procedures must be executed 1 Set LCDMD2 LCUPEN to 1 and deactivate LCDDRV 2 When BSTVOL is activated set LCDMDO LCUPEN to After deactivating BSTVOL the voltage level of VLC1 is 3 When REFVOL is activated set LCDMD1 LCVREN to 0 After LSI reset VLC1 is in high impedance until the LDCDMDO LCUPEN is set to 1 When BSTVOL is used t output voltage from VLC1 to drive LCD display LOCDMDO LCUPEN should be set to 1 after releasing LSI reset Recommended Operation XVII 17 Chapter 17 LCD 17 3 2 Voltage Booster Circuit BSTVOL
189. 3E92 SEG2 SEG2 LCDATA3 0x3E93 1 LL SEG3 SEG3 LCDATA4 0 3 94 Ld j SEG4 SEG4 SEGO LCDATA5 0 3 95 SEG5 SEG5 1 LCDATA6 0 3 96 ___ j SEG6 SEG6 SEG2 LCDATA7 0 3 97 SEG7 SEG7 SEG3 LCDATA8 0x3E98 1 1 jJ SEG8 SEG8 SEG4 LCDATA9 0 3 99 gt SEG9 SEG9 SEG5 LCDATA10 Ox3E9A 5 0 SEG10 SEG6 LCDATA11 0x3E9B 1 1 L SEG11 11 LCDATA12 Ox3E9C 111 SEG12 SEG12 LCDATA13 0x3E9D 1 1 L J SEG13 5 LCDATA14 fs 2 SEG14 SEG14 LCDATA15 0x3E9F 1 j SEG15 SEG15 SEG7 LCDATA16 Ox3EAO 1 j SEG16 SEG16 SEG8 LCDATA17 0x3EA1 111 SEG17 SEG17 SEG9 LCDATA18 Ox3EA2 11 SEG18 SEG18 5 10 LCDATA19 111 SEG19 SEG19 SEG11 LCDATA20 0x3EA4 1 j SEG20 SEG20 SEG12 LGDATAO2 OXGEAG gt Seas SEG22 SEGA LCDATA22 Ox3EA6 2 SEG22 SEG22 SEG14 LCDATA23 Ox3EA7 1 1 LL SEG23 SEG23 SEG15 LCDATA24 8 11 SEG24 SEG24 5 16 LCDATA25 9 1 1 SEG25 SEG25 SEG17 LCDATAD OxJEAB 2 27 SEG27 SEGI LCDATA27 Ox3EAB gt SEG27 SEG27 SEG19 LCDATA28 Ox3EAC 11 L SEG28 SEG28 SEG20 LCDATA29 Ox3EAD 111 gt SEG29 SEG29 LCDATA30 Ox3EAE 1 j SEG30 SEG30 LCDATA31 0 111 SEG31 LCDATA32 Ox3EBO 1 Ld j SEG32 LCDATA33 0x3EB1 ____ j j SEG33 LCDATA34 0x3EB2 i SEG34 LCDATA35 0x3EB
190. 5 Chapter 9 16 bit Timer 9 2 1 Programmable Timer Registers 1 Programmable timer registers must be accessed with 16 bit access instruction Compare registers are 16 bit registers for storing the values compared with binary counters These registers are loaded with the comparing data stored in preset registers in advance Timer n Compare Register 1 Lower 8 bits 0x03FA2 TM80C1L 0x03FB2 TM9OC1L 0x03FC2 Bit name At reset Access Timer n Compare Register 1 Upper 8 bits TM7OC1H 0x03FA3 0x03FB3 TM9OC1H 0x03FC3 Bit name At reset Access Timer n Compare Register 2 Lower 8 bits TM7OC2L 0x03FAA TM8OC2L TM9OC2L Bit name At reset Access Timer n Compare Register 2 Upper 8 bits TM7OC2H 0x03FAB TM8OC2H TM9OC2H OxO3FCB Bit name At reset Access X 6 16 bit Timer Control Registers Chapter 9 16 bit Timer Preset registers are buffer registers for compare registers When writing data to the preset register while the counting 1 stopped the same data 1 loaded to the compare ister When writing data to the preset register while counting the data of preset register is loaded to the compare register at the timing when the binary counter is cl
191. 6 d11 label H if NF 0 6 PC BVC label if VF 0 PC 5 d7 label H if VF 1 PC 5 gt PC BVC label if VF 0 PC 6 d11 1 label H PC BVS label if VF 1 PC 5 d7 label H PC if VF 0 PC 5 gt PC BVS label if VF 1 PC 6 if VF 1 PC 6 d11 labelj H PC if VF 0 6 gt PC BRA label PC 3 d4 label H PC BRA label PC 4 d7 label H PC BRA label PC 5 d11 label H CBEQ imm8 label if Dm imms 6 97 PC if Dm imm8 6 PC CBEQ imm8 label if Om imm8 8 011 PC if Dmzimm8 8 PC CBEQ imm abs8 label if mem8 abs8 imm8 PC49 d7 label H PC if mem8 abs8 zimm8 9 PC CBEQ imm8 abs8 lable if mem8 abs8 imm8 PC 10 d11 label H if mem8 abs8 imm8 PC 10 PC CBEQ imme abs16 label if mem8 abs16 imm8 PC 11 d7 label H if mem8 abs16 zimm8 11 PC CBEQ imme abs16 lable if memB8 abs16 imm8 PC 12 d11 label H gt if mem8 abs16 zimm PC 12 PC CBNE imm8 Dm label iftDmsimm8 PC 6 d7 label H gt PC PC 6 PC CBNE imm8 Dm label 8 011 PC if Om imm8 PC 8 gt PC CBNE imm8 abs8 label if mem8 abs8 zimms8 PC 9 d7 label H PC if memB abs8
192. 60 to P67 P70 to P77 Schmitt input C27 High level input voltage Ving 0 8Vpp30 Vpp30 C28 Low level input voltage 0 0 2Vppso C29 Input leakage current Vj V to EN zx 1 C30 Pull down resistance 30 100 300 C31 1 output 3 0 Visas mA 24 gt sr m CE Input 5 P27 NRST C34 High level input voltage Vins 0 8Vppao Vppso V C35 Low level input voltage Vics 0 0 15Vppso C36 Pull down resistance mus Us 30 100 300 1 26 Electrical Characteristics Chapter 1 Overview Vppao to 3 6 V Vss 0 V 1 1 V at auto reset function Ta 40 C to 85 C Limits Parameter Symbol Condition Unit MIN TYP MAX Display output pin 1 COMO to at VI Vss output MN101LR02D is not applicable Potential difference of Vici 3 0 V V z d output waveform OSM 10 pA os M Display output pin 2 SEGO to SEG42 at Vi Vss output MN101LRO2D is not applicable Voltage difference of Vic1 3 0 V V ee output waveform 999 2 06 xV LCD boost output pin 1 VLC1 VLC2 VLC3 VLC3 Triple output compared to the reference voltage output MN101LR02D is not applicable C39 Vici Vpp30 VRSTL to 3 0 V 2 7 3 0 3 3 V 1 0 V Ta 25 C V LOS 1 2 2 2 a Output voltage LC2 ILCD display OFF SEG COM 9 V
193. 7 LCD 17 3 6 Setup Examples of REFVOL and BSTVOL W The following example shows how to display 23 8 segment type LCD panel by using SEG0 SEG3 and COMO COM3 with the voltage generated with REFVOL BSTVOL The display mode with 1 4 duty output and 1 3 bias is selected Setup Procedure Description 1 Select the boost mode of BSTVOL 1 Select the three times boost mode LCDMD4 0x03ECE bp0 LCUPMD 0 2 Activate BSTVOL and REFVOL 2 Activate BSTVOL and REFVOL LCDMD1 0x03E81 bp7 LCVREN 1 LCDMDO 0x03E80 bp7 LCUPEN 1 3 amp pins setting 3 Select SEG0 3 and 3 pins LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp3 0 COMSL3 0 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 4 Les 4 Select HCLK 218 display clock x bp6 3 LCCK3 0 0111 bp2 0 LCCKS2 0 101 5 Select a display duty 5 Select 1 4 as a display duty LCDMD2 0x03E82 bp2 0 LCDTY2 0 011 6 Set the display data 6 Set the display data 23 on the segment output latch LCDATAO 0x03E90 0x0E LCDATA1 0x03E91 0x05 LCDATA2 0x03E92 0 0 LCDATA3 0x03E93 0x07 7 Activate the LCD 7 Start the LCD LCDMD2 0x03E82 bp7 LCEN 1 Operation 25 Chapter 17 LCD 17 4 LCD Display Examples This section describes how to connect the segment and common signals to LCD panel and shows the LCD dis play and waveforms in static 1 2 duty 1 3
194. 7 0 P37 1 SEG20 1 SEG20 1 SEG12 XVII 12 Control Registers Chapter 17 LCD m LCD Port Control Register 4 LCCTR4 0x03E8A Bitname SEGSL35 SEGSL34 SEGSL33 SEGSL32 SEGSL31 SEGSL30 SEGSL29 SEGSL28 At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG35 P30 selection SEGSL35 0 P30 1 SEG35 SEG34 P31 selection SEGSL34 0 P31 1 SEG34 SEG33 P32 selection SEGSL33 0 P32 Must be set to 0 1 SEG33 SEG32 P33 selection SEGSL32 0 P33 Must be set to 0 1 SEG32 SEG31 P34 selection SEGSL31 0 P34 1 SEG31 SEG30 P35 selection SEG30 P20 selection SEGSL30 0 P35 0 P20 1 SEG30 1 SEG30 SEG29 P36 selection SEG29 P21 selection SEGSL29 0 P36 0 P21 1 SEG29 1 SEG29 SEG28 P37 selection SEG28 P26 selection SEG20 P26 selection SEGSL28 0 P37 0 P26 0 P26 1 SEG28 1 SEG28 1 SEG20 Control Registers XVII 13 Chapter 17 LCD m LCD Port Control Register 5 LCCTR5 0x03E8B Bit name SEGSL42 SEGSL41 SEGSL40 SEGSL39 SEGSL38 SEGSL37 SEGSL36 At reset 0 0 0 0 0 0 0 Access Bit name MN101LRO5D Always read as 0 Description MN101LRO4D MN101LROSD SEGSL42 SEG42 P20 selection 0 P20 1 SEG42 SEGSL41 SEG41 P21 selection 0 P21 1 SEG41 SEGSL40 SEGSL39 SEG40 P22 selection 0 P22 1 SEG40 SE
195. 71OC output 8 output Table 9 9 2 IGBT Trigger TM7MD3 T7IGBT1 0 T7IGBTTR IRQO falling edge 01 IRQO IRQO rising edge 01 IRQ1 falling edge 10 IRQ1 rising edge 10 11 11 IRQ2 falling edge IRQ2 rising edge TM7EN count operation 16 bit Standard IGBT Output with Variable Duty IX 47 Chapter 9 16 bit Timer IX 48 W Count timing of Standard IGBT Output Normal Timer 7 Count clock TM7EN bit i i DON register 1 h IGBT trigger counter TM7IO output IGBT output A B C D E Figure 9 9 1 Count timing of Standard IGBT Output Normal A Once the IGBT trigger is input the IGBT operation is valid at the next clock After the IGBT operation becomes valid the IGBT output holds Low until the next count clock B While the IGBT trigger is valid and the binary counter counts up from 0x0000 to the TM7OC2 compare match the IGBT output is High Only for the 1st cycle of counting the output is High from 0x0001 C After the TM7OC2 compare match the output changes to Low and the binary counter continues counting up until it overflows D When the binary counter overflows the IGBT output returns to High E When the IGBT trigger becomes invalid the timer is initialized and the IGBT output is forced to be Low 16 bit Standard IGBT Output with Variable Duty Chap
196. 9 ms SCLK 21 250 ms 8 MHz 4 MHz 2 MHz 32 768 kHz 2 When SCLK is used as the clock source the timer counts at falling edge of the count clock Y When other clock is used it counts rising edge of the count clock X 8 8 bit Free running Timer Chapter 10 General Purpose Time Base Free Running Timer W Count Timing of Timer Operation Timer 6 Binary counter counts up with the selected clock source as a count clock Count clock TM6CLRS bit Compare i j li wu register i d i i 2 i JUDOOLOOGOUOOAOUOU counter 1 4 Interrupt EDT request i 3 5 Figure 10 3 1 Count Timing of Timer Operation Timer 6 1 When any data is written to the compare register during the TM6CLRS 0 the binary counter is cleared to 0x00 2 Even if any data is written to the compare register during the TM6CLRS 1 the binary counter is not cleared 3 When the binary counter reaches the setting value of the compare register during the TM6CLRS 1 an inter rupt request is set at the next count clock 4 When an interrupt request is set the binary counter is cleared to 0x00 and restarts counting 5 Even if the binary counter reaches the setting value of the compare register during the TM6CLRS 0 no interrupt request is set 8 bit Free running Timer X 9 Chapter
197. 9F Timer 8 mode register 4 TM8ICR 0x03FF1 Timer 8 interrupt control register Timer 7 Timer 8 TM8OC2ICR 0x03FF2 Timer 8 compare register 2 match interrupt control register IX 4 16 bit Timer Control Registers Chapter 9 16 bit Timer Address Register Name TM9BCL 0x03FC0 Timer 9 binary counter lower 8 bits TM9BCH 0x03FC1 R Timer 9 binary counter upper 8 bits TM9OC1L 0x03FC2 R Timer 9 compare register 1 lower 8 bits TM9OC1H 0x03FC3 Timer 9 compare register 1 upper 8 bits TM9PR1L 0x03FC4 Timer 9 preset register 1 lower 8 bits TM9PR1H 5 Timer 9 register 1 upper 8 bits TM9ICL 0x03FC6 Timer 9 input capture register lower 8 bits TM9ICH OxOSFC7 Timer 9 input capture register upper 8 bits Timer 9 TM9MD1 OxOSFC8 Timer 9 mode register 1 TM9MD2 0x03FC9 Timer 9 mode register 2 TM9OC2L 0x03FCA Timer 9 compare register 2 lower 8 bits TM9OC2H 0x03FCB Timer 9 compare register 2 upper 8 bits TM9PR2L Timer 9 register 2 lower 8 bits TM9PR2H 0x03FCD Timer 9 preset register 2 upper 8 bits TM9MD3 0x03FCE Timer 9 mode register 3 TM9ICR Ox03FF3 Timer 9 interrupt control register TM9OC2ICR 0x03FF4 Timer 9 compare register 2 match interrupt control register 16 bit Timer Control Registers
198. A 1 Large current capacity 8mA VII 22 Control Registers Chapter 7 I O Port W Port 4 N ch Current Capacity Selection Register PANLC 0x03EC3 Bit name At reset Access e mmm mmm _ N ch current capacity selection 7 0 P4NLC7 0 0 normal current capacity 2mA 1 Large current capacity 8 W Port 5 N ch Current Capacity Selection Register PSNLC 0x03EC4 Bit name At reset Access m mme N ch current capacity selection 7 0 P5NLC7 0 0 normal current capacity 2mA 1 Large current capacity 8mA Control Registers VII 23 Chapter 7 Port Port 6 N ch Current Capacity Selection Register 6 0x03EC5 Bit name At reset Access e mmm e N ch current capacity selection 7 0 P6NLC7 0 0 normal current capacity 2mA 1 Large current capacity 8mA m Port 7 N ch Current Capacity Selection Register 7 0x03EC6 Bit name At reset Access m mme Dee N ch current capacity selection 7 0 P7NLC7 0 0 normal current capacity 2mA 1 Large current capacity 8mA VII 24 Control Registers Chapter 7 I O Port 7 2 7 8 bit Timer output control Register 8 bit Timer output control register selects the pin function General IO GIO or 8 bit Timer output 8 bit Time
199. A SBT3A SCL3A P05 9 P43 SEG8 IRQ4C 2 AN2 P12 10 P42 SEG9 IRQ5C AN3 P13 lt gt 111 VREFP prm Qacara ZEHSHHRGHTAA 32 3 lt lt G 0 0 0 0 0 000 C0 C0 D CO C0 D D zazaacaaacmgmgamGm 90895828925 xxi oa Eo lt lt lt amd 5950 939 na SEH gt 00 a E N la Ci i oo 1 3 3 MN101LR03D Pin Configuration IRQ3B IRQ2B IRQ1B IRQOB TM8IOA KEYSB CLKOUTB TM3IOA KEY2B TM1IOA KEY1B SBCS2A SBT2A SCL2A SBO2A SDA2A P41 SEG10 SBI2A 40 5 11 5 50 Pin Description Chapter 1 Overview 1 13 Chapter 1 Overview gt lt m m lt 2 gt x lt x lt x lt E G lt Ono 385 gt gt gt gt 0 c 0 ON XI lt gt P57 TM8IOA KEYSB CLKOUTB P56 TMSIOA KEY2B NATRON P55 TM1lIOA KEY1B P27 NRST MN101LRO2D 4 P44 SBCS2A 32 pin 7 4 CLKOUTA TM2IOA TMOIOA SBTSA SCL3A P05 8 5 06 IRQSC KEYSA 13 lt P43 SBT2A SCL2A 42 5 2 SDA2A 4 gt 1 5 2 17 40 5 50 AON Oa N OQ s i sb
200. AL1IRQMOEN Alarm 1 Month comparator enable control 0 Disable 1 Enable AL1IRQDEN Alarm 1 Day comparator enable control 0 Disable 1 Enable Always read as 0 AL1IRQHEN Alarm 1 Hour comparator enable control 0 Disable 1 Enable AL1IRQMIEN Alarm 1 Minute comparator enable control 0 Disable 1 Enable Alarm 1 Minutes Setting Register AL1IRQMI 0x03ED8 Bit name At reset 0 Access Bit name Always read as 0 6 0 Alarm 1 Minute setting Set a value within the range of 00 to 59 using the BCD format The value which doesn t exist must not be set Control Registers XII 7 Chapter 12 Real Time Clock RTC W Alarm 1 Hours Setting Register AL1IRQH 0x03ED9 Bit name AL1IRQH6 AL1IRQH5 0 At reset 0 0 0 Access Bit name Description Always read as 0 Alarm 1 setting 0 AM AL1IRQH6 1 PM This bit must be set in 12 hour clock mode When 24 hour clock mode this bit must be set to 0 Alarm 1 Hour setting lt 24 hour clock mode gt Set a value within the range of 00 to 23 using the BCD format lt ln 12 hour clock gt Set a value within the range of 00 to 11 using the BCD format The value which doesn t exist must not be set AL1IRQH5 0 m Alarm 1 Day Setting Register AL1IRQD 0x03EDA Bit name AL1IRQD5 0 At reset 0 0 0
201. ANCHS2 0 A D Conversion Clock Setup The A D conversion clock is set by the ANCTRO ANCK2 0 Set the A D conversion cycle between 750 ns and 100 us Table 16 3 1 shows the machine clock HCLK SCLK SYSCLK and the A D conversion cycle calculated as fsyscrk fgcrk 2 Table 16 3 1 A D Conversion Clock and A D Conversion Cycle AID A D conversion cycle TApci k conversion clock 10 MHz fecik 32 768 kHz 400 ns Setting is prohibited 600 ns Setting is prohibited SYSCLK 2 61 035 us SYSCLK 3 91 552 us 122 070 us Setting is prohibited 183 105 us Setting is prohibited 244 140 us Setting is prohibited 366 210 us Setting is prohibited 488 281 us Setting is prohibited SCLK 30 517 us SYSCLK 4 800 ns SYSCLK 6 1 2 us SYSCLK 8 1 6 ns SYSCLK 12 2 4 SYSCLK 16 3 2 us W A D Conversion Sample hold Time Ts Setup The sample hold time of A D conversion is set with the ANCTRO ANSH1 0 The sample hold time of A D conversion depends on the external circuit so set the appropriate value based on the analog input impedance Table 16 3 2 Sample Hold Time of A D Conversion and A D Conversion Time Sample hold A D conversion cycle T clock ycle Tap ANSH1 0 x 2 18 2 3 x 1 fsyscLK x 6 x 18 6 3 x 1 fsyscLK Tanck X 18
202. ART by using SCIFn set SCnMD1 SCnCMD to 1 13 4 1 Communication Form 1 wire UART Data is transmitted or received by using either TXDn or RXDn TXDn is used for both data transmission and reception RXDn is used for data reception only 2 wire UART full duplex UART Data are transmitted and received with 2 wire communication by using both TXDn and RXDn TXDn is used for data transmission and RXDn is used for data reception Be sure to set the data frame and parity bit on the transmission reception data to the same setting When the serial communication is not executed set data reception pin to High level Y Otherwise SCIFn does not work properly XIII 46 Full duplex UART Communication Chapter 13 Serial Interface W Setup of Data Frame and Parity Bit Figure 13 4 1 shows data format of UART communication Frame Figure 13 4 1 Data Format UART Communication Character bit Data frame consists of following types of bit that are shown in Table 13 4 1 Set character and stop bits with SCnMD2 SCnFM1 0 Table 13 4 1 Data Types of Full duplex UART Communication Start bit 1 bit Character bit 7 to 8 bits Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1to 2 bits Table 13 4 2 shows the types of parity bit Set the parity bit with SCnMD2 SCnNPE SCnMD2 SCnPM 1 0 Table 13 4 2 Parity Bit of UART Serial Interface SCnMD2 SCn
203. BT_LST it is not changed When writing 0 to IIC3ABT_LST it is cleared to 0 ma When writing 1 to IICSDATA ERR it is not changed When writing 0 to IIC3DATA_ERR it is cleared to 0 Q lt When detecting the General call address ACK bit is always sent to the IIC master IIC3GCALL is valid only when the interrupt caused by the reception of the General call address occurs Control Registers XIII 21 Chapter 13 Serial Interface 13 2 7 Address Setting Register gm SCIFn n 2 3 Address Setting Register SC2AD SC3AD Bit name IIC3AD7 IIC3AD6 5 IIC3AD4 IIC3AD3 IIC3AD2 IIC3AD1 Initial value 0 0 0 0 0 0 0 0 Access 13 2 8 BRTM Operation Mode Setting Register m BRTM Operation Mode Setting Register BRTM_S_MD Bit name BRTM_S3_MD BRTM_S2_MD BRTM_S1_MD BRTM_SO_MD Initial value 0 0 0 0 Access 0 is always read out Duty mode of BRTM3 output clock BRTM_S3_MD 0 1 1 Duty mode of BRTM2 output clock BRTM_S2_MD 0 1 1 1 1 N Duty mode of BRTM1 output clock BRTM_S1_MD 0 1 1 mode of output clock BRTM_SO_MD 0 1 1 1 1 N 1 1 Duty mode The period is 2 x N 1 x Count Clock Period 1 N Duty mode The Period is 1 x Count Clock Period However N 0 is excluded N is the value of BRTM_Sn_OC XIII 22 Control Registers Chapter 1
204. C2IOM SC2SELO 1 SEG26 1 0 0 SBI2A 0 0 41 VII 46 Port 4 Table 7 8 4 P42 Function Selection Setup Function Register LCCTR3 SC2MD1 SC23SEL SEGSL25 SC2SBOS SC2SBIS SC2IOM SC2SEL1 1 SEG25 1 1 72 2 0 SBO2A 0 1 1 0 SDA2A 0 0 P42 1 When serial data is output set the P4DIR P4DIR2 to 1 2 When serial data is input and output set the bit to 1 Table 7 8 5 P43 Function Selection Setup Function Register LCCTR3 SC2MD1 SC23SEL Bit name SEGSL24 SC2SBTS SC2SEL2 1 SEG24 1 1 0 SBT2A SCL2A J 0 P43 1 When the LSI is the master of Clock synchronous communication or communicates on IIC bus set the P4DIR P4DIR3 to 1 Table 7 8 6 P44 Function Selection Setup Function Register LCCTR3 SC2MD2 SC23SEL Bitname SEGSL23 SC2SBCSEN SC2SEL3 1 SEG23 TU 0 SBCS2A 0 P44 1 When the LSI outputs the chip select signal set the P4DIR P4DIR4 to 1 Table 7 8 7 P45 Function Selection Setup Function Register LCCTR3 SC1MD1 SCO1SEL Bit name SEGSL22 SC1SBIS SC1IOM SC1SELO 1 SEG22 1 0 1 SBI1B RXD1B 0 0 P45 Port 4 Chapter 7 I O Port VII 47 Chapter 7 I O Port VII 48 Table 7 8 8 P46 Function Selection
205. CLK NO Y Start the external low speed oscillation SCLKCNT SOSCCNT 1 YES 4 External low speed oscillation stabilization wait time Switching the source oscillation of SCLK SCLKCNT SCLKSEL 0 SLOW mode SYSCLK SOSCCLK Figure 4 2 7 Clock Change Flow from SRCCLK to SOSCCLK speed oscillation set the SCLKSEL bit of SCLKCNT register to 1 after setting the SOSC CNT bit of SCLKCNT register to 1 and the enough oscillation stabilization wait time has elapsed The oscillation stabilization wait time should be determined in consultation with the manufac turer of oscillator 1 change the operating clock from the internal low speed oscillation to the external low Clock Change from SOSCCLK to SRCCLK Figure 4 2 8 shows the clock change procedure from SOSCCLK to SRCCLK SLOW mode SYSCLK SOSCCLK Start the internal low speed oscillation SCLKCNT SRCCNT 1 Internal low speed oscillation stabilization wait time 100 us Switching the source oscillation of SCLK SCLKCNT SCLKSEL 0 SLOW mode SYSCLK SRCCLK Figure 4 2 8 Clock Change Flow from SOSCCLK to SRCCLK IV 18 Mode Control Function Chapter 4 Clock Mode Voltage Control 4 2 3 STANDBY Mode The transition from CPU operating mode NORMAL SLOW to STANDBY mode HALT STOP is executed by the program CPU wakes up from 5 mode by the interrupt Figure 4 2 9 shows
206. CPU outage in voltage transition 32 fscr k 32 768 kHz 977 us Setting Register name Description Set CPU outage in voltage transition PWCTR1 Set PWUPTM2 0 to 011 Set output voltage VDD18 PWCTRO Set VDDLV1 0 to 10 NOP instruction Insert 3 NOP instructions Transition to NORMAL mode CPUM Set to 00000111 Be sure to execute the setting in SLOW mode lt Voltage Control IV 29 Chapter 4 Clock Mode Voltage Control m Voltage Transition of VDD18 by Mode Transition Figure 4 3 2 shows the example of voltage transition of VDD18 by mode transition For the mode transition method refer to 4 2 Mode Control Function When the Deep STANDBY mode control that change the voltage from 1 3 V or 1 8 V to 1 1 is enabled during the mode transition from NORMAL to HALT2 STOPO the STANB Y mode with low power consumption can be set by just updating the CPUM register The Deep STANDBY mode is enabled by setting the PWCTR1 DEEPMOD to 1 1 8 V 11 oN VDD18 output voltage DEEPMOD 0 VDD18 output Operating mode NORMAL HALT2 NORMAL HAT2 NORMAL CPU idle time Figure 4 3 2 Voltage Transition of VDD18 by Mode Transition The setting example of the transition to Deep STANDBY mode Figure 4 3 2 is shown below Setting Register name Description Set Deep STANDBY mode PWCTR1 Set DEEPMOD to 1 Set
207. Chapter 16 A D Converter ADC 16 3 3 Cautions As A D conversion could be easily damaged by noise sufficient anti noise measures are needed m Anti noise measures Connect capacitors to analog input pins AN7 to ANO which is positioned close to VSS pins In addition Connect capacitors the different capacities more than two are recommended to ADC reference volt age pins VREFP which is positioned close to VSS pins Digital Voo Analog 0030 VSS Power Supply Vss Set near the VSS pin Figure 16 3 3 ADC Recommended Example 1 Set near the VSS pin Figure 16 3 4 ADC Recommended Example 2 During the A D conversion if the output level of is changed or the additional peripheral circuits are switched to ON OFF the ADC may operate incorrectly as the analog control ter minals cannot be fixed At circuit board evaluation confirm the waveform of analog input pins Operation XVI 13 Chapter 16 A D Converter ADC m Sample Hold Time This LSI contains sample hold capacitor Cap 16 pF input pin capacitor 2 pF and resistor Rap 4 0 Set the sample hold time based on the time constant with Cap Cro Rap and impedance of external analog signal output circuit It is recommended to select to be Tap gt 87 RC For example when Rour 10 Tap is determined as follows R 10
208. Continuously Variable Period Duty Chapter 9 16 bit Timer 9 8 16 bit Timer Capture Function 9 8 1 Operation In the capture function the value of the binary counter is read at the following When one of IRQO to IRQ3 which is synchronized with the system clock or the count clock is input When an interrupt of Timer 0 or Timer 1 occurs When the arbitrary data are written to the capture register W Capture Operation with External Interrupt Signal as a Trigger Input capture trigger is generated by the external interrupt input signal Set TMnMD1 TMnMD2 to select the capture trigger Table 9 8 1 show the available types of capture trigger and bit settings Table 9 8 1 Capture Trigger Capture trigger source we TnICT1 0 TnICEDG0 TnICEDG1 IRQO falling edge 00 0 1 0 IRQO rising edge 00 0 1 1 IRQ0 both edges 00 IRQO 0 IRQ1 falling edge 01 IRQ1 1 0 IRQ1 rising edge 01 IRQ1 1 1 IRQ1 both edges 01 IRQ1 0 IRQ2 falling edge 10 IRQ2 1 0 IRQ2 rising edge 10 IRQ2 1 1 IRQ2 both edges 10 IRQ2 0 IRQ3 falling edge Timer 9 11 IRQ3 1 0 IRQ3 rising edge Timer 9 11 IRQ3 1 1 IRQ3 both edges Timer 9 11 IRQ3 0 16 bit Timer Capture Function IX 39 Chapter 9 16 bit Timer 1 When the system clock SYSCLK is selected as the capture clock by setting the TMnMD3 TMnCKSMP to 1 the clock for the binary counter is the one that is selected by
209. D correction to the DO register Bit Changes Size Cycles Codes VF 0 6 nibbles NF 0 4 cycles CF Set if the result is smaller than 0 otherwise set to 0 ZF Set if the result is 0 otherwise set to 0 0000 0010 0111 0000 0000 1000 W Execution of BCD subtraction with carry 1 Store the 8 bit value of the two digit BCD as a subtrahend to the DO register Store the 8 bit value of the two digit BCD as a minuend to the D1 register Store the carry to the PSW 2 Execute MOV 0x80 0x03F07 Extended calculation macro instruction BCDSUBC 3 Subtracts the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and subtracts the PSW CF further and stores the result 8 bit after the BCD correction to the DO register a When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it 1 the result is not guaranteed Extended Calculation Instruction 27 Chapter 2 CPU 2 5 Reset 2 5 1 Reset function This LSI has the following four types of reset factors Power on reset when the NATRON pin is tied to Low Power down reset when the NATRON pin is tied to Low Low level signal input to NRST pin Two consecutive WDT overflow The LSI starts up in SLOW mode 28 Reset Chapter 2 CPU 2 5 2 Re
210. DBY mode bp 7 6 5 4 3 2 1 0 Bit name Reserved Reserved DEEP Reserved PWDPTM SERVANT MOD 2 1 0 Initial value 0 0 1 1 0 0 Access R W R R R W R W R W R W R W Bit name Reserved Always set to 0 Description Reserved When transition of VDD18 set to 1 after the microcomputer starts up Always read as 0 DEEPMOD VDD18 setting when the transition from NORMAL mode to HALT2 STOPO mode 0 Voltage transition disabled 1 Change to 1 1 V Voltage returns to the same level as it was before the transition at return CPU starts up again after the time set in PWUPTM2 0 Reserved When transition of VDD18 set to 0 after the microcomputer starts up 2 0 Set outage of CPU and clock when updating VDD18 000 8 fscLk 001 8 fscLk 010 16 5 244 us at faci k 244 us at fscLK 488 us at 011 32 fscLK 977 us at 100 64 1953 us at 101 128 faci 3906 us at fscLK 110 256 fgcLk 7813 us at fscLK 111 512 15625 us at 32 768 kHz 32 768 32 768 32 768 2 32 768 2 32 768 kHz 32 768 2 32 768 kHz 2 2 From 1 1 V to 1 3 V 4 ms or more Set the PWCTR1 PWUPTM2 0 to match the following conditions before the transition from 1 1 V to 1 8 Vor to 1 3 V From 1 1 V to 1 8 V 500 us or more Only the
211. DC4 2 0 Push pull output 1 N ch open drain output Always read as 0 N ch open drain output selection P5ODC0 0 Push pull output 1 N ch open drain output VII 20 Control Registers Port 6 N ch Open drain Control Register P6ODC 0x03F56 Bit name P6ODC7 5 Chapter 7 I O Port At reset 0 Access N ch open drain output selection 0 Push pull output 1 N ch open drain output Always read as 0 Control Registers VII 21 Chapter 7 Port 7 2 6 Port n N ch Drive Strength Selection Registers PnNLC is the register to select the drive strength of Nch output transistor of I O Port 0 N ch Current Capacity Selection Register Bit name PONLC7 0 At reset 0 0 0 0 0 0 0 0 mw ww nw m mme Dee N ch current capacity selection 7 0 7 0 0 normal current capacity 2mA 1 Large current capacity 8mA Port 2 N ch Current Capacity Selection Register 2 0x03EC1 At reset 0 0 Access R R W Bit name Description Always read as 0 N ch current capacity selection P2NLC6 0 0 normal current capacity 2 1 Large current capacity 8mA Bit name At reset Access m sme mm _ N ch current capacity selection 7 0 P3NLC7 0 0 normal current capacity 2m
212. DT Dn 1 Load the value of PERInDT to Dn mov Dn PERInDT 1 clear the PERInDT 2 Dm Extract the request bit that interrupt is enabled Routine of bitO factor btst 0x01 Dn beq bitO_end When bit0 is set to 1 interrupt program gt the interrupt program corresponding to bit0 is executed corresponding to bit0 bit0_end 27 Routine of bit1 factor btst 0x02 Dn beq bit1_end Tu When is set to 1 interrupt program gt the interrupt program corresponding to bit1 is executed corresponding to bit1 bit end Routine of bit7 factor btst 0x80 Dn beq bit7_end When bit7 is set to 1 interrupt program the interrupt program corresponding to bit7 is executed corresponding to bit7 bit7_end rti Figure 3 1 9 Sample program of Group 0 Group 1 interrupt service routine Overview 19 Chapter 3 Interrupts 3 2 Control Registers Interrupt Control Registers is listed in Table 3 2 1 Table 3 2 1 Interrupt Control Registers Address Register name NMICR Ox03FE1 Non maskable interrupt control register IRQOICR Ox03FE2 External interrupt 0 control register IRQ1ICR 0x03FE3 External interrupt 1 control register IRQ2ICR 0x03FE4 External interrupt 2 control register IRQ3ICR 0x03FE5 External interrupt 3 control register IRQ4ICR 0x03FE6 External interrupt 4 control register IRQ5ICR 0x03FE7 External interrupt 5 control regi
213. Fn before the next data is received Table 13 4 3 UART Communication Error Sources Flag name Error content SCnSTR SCnORE Overrun error Sale received before reading the previous received data from SCnSTR SCnPEK error A parity bit error is detected SCnSTR SCnFEF Flamingerror stop bit is not detected XIII 50 W Break Transmission To transmit a break set SCnMD2 SCnBRKE to 1 and write dummy data to TXBUFn In break transmission all data all bits of the data frame is 0 is transmitted To send a normal data set SCnMD2 SCnBRKE to 0 a Be sure to write data to SCnBRKE while both SCnSTR SCnTBSY SCnSTR SCnTEMP are O W Break Reception A break is detected with SCnMD2 SCnBRKF When the break is detected SCnBRKF is set to 1 at the event of SCnRIRQ SCnBRKF is updated every time SCnRICR occurs so read out SCnBRKF before the next data is received m Consecutive Communication Mode Consecutive Data Transmission Before setting the next transmission data to TXBUFn confirm that SCnSTR SCnTEMP is 0 after the previous data is set to TXBUFn The next transmission data must be set by 0 5 transfer clock before the last stop bit of the previous data frame is transmitted If this restriction is not satisfied the communication blank more than 1 bit length may occurs between transmis sion data Consecutive Data Reception A start bit can be detected immediately after
214. G3 and common pins COMO to COM3 with 1 4 duty and 1 3 bias supplied from external voltage divider Other conditions are described as follows HCLK 4 MHz LCD display clock HCLK 2P 122 Hz LCD frame frequency 31 Hz Chapter 17 LCD Setup Procedure Description 1 Stop the LCD LCDMD2 0x03E82 bp7 LCEN 0 2 Set a display duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 011 3 Set a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 LCCTRO 0x03E86 bp7 4 SEGSL3 0 1111 bp3 0 COMSL3 0 1111 1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 b Set the display data LCDATAO 0x03E90 OxOE LCDATA1 0 03 91 0x05 LCDATA2 0x03E92 0 0 LCDATAS 0x03E93 20x07 6 Activate the LCD LCDMD2 0x03E82 bp7 LCEN 1 4 Set Segment and common output pins 1 Stop the LCD 2 Set the operation mode to 1 4 duty driving 3 Select HCLK 2 as a display clock 4 Select SEG0 3 and COMO 3 pins b Set the display data 23 on the segment output latch 6 Start the LCD LCD Display Examples XVII 37 Chapter 17 LCD XVII 38 LCD Display Examples Chapter 18 ReRAM Chapter 18 ReRAM 18 1 Overview of ReRAM Table 18 1 1 shows the outline of ReRAM specifications Table 18 1 1 Outline of ReRAM Specifications Function Description Memory size 64 KB Program endurance Pro
215. G39 P23 selection 0 P23 1 SEG39 SEGSL38 SEGSL37 SEG38 P24 selection 0 P24 1 SEG38 SEG37 P25 selection 0 P25 1 SEG37 14 Control Registers SEGSL36 SEG36 P26 selection 0 P26 1 SEG36 Must be set to 0 Chapter 17 LCD m LCD Display Select Register LCDSEL 0x03E8E Bit name COMSL7 COMSL6 COMSL5 COMSL4 At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LRO5D MN101LRO4D MN101LROS3D Always read as 0 SEG3 CON7 selection COMSL7 0 SEG3 1 COM7 SEG2 COM6 selection COMSL6 0 SEG2 1 COM6 SEG1 COM5 selection COMSL5 0 SEG1 1 COM5 SEG0 COM4 selection COMSL4 0 SEGO 1 COM4 Must be set to 0 Control Registers XVII 15 Chapter 17 LCD Segment Output Latch LCDATA0 42 0x03E90 0x03EBA 8 bit segment output latch LCDATAn is assigned for each segment Each bit is read in synchronization with the COMn timing and is output from the SEGn LCDATAn can be read or written like RAM and the values of them are not valid at reset Figure 17 2 1 shows the relation of segment output latch and segment common pins these differ in each product COM COMS COMS COMI TRUE TTL Register Address yi bite bits bit4 bit2 bito OED LCDATAO 0 3 90 Ll l l _ SEGO SEGO LCDATA1 0x3E91 11 j SEGI SEGI LCDATA2 0x
216. HOSCCNT 1 Internal high speed oscillation External high speed oscillation stabillization wait time stabillization wait time Transition ot NORMAL mode Set the CPUM as described in Table 4 1 3 NORMAL mode Figure 4 2 3 Transition Flow from SLOW to NORMAL through IDLE Mode Control Function 15 Chapter 4 Clock Mode Voltage Control Clock Change from HRCCLK to HOSCCLK Figure 4 2 4 shows the clock change procedure from HRCCLK to HOSCCLK NORMAL mode SYSCLK HRCCLK NO HCLKCNT HOSCCNT 1 Y YE Start the external high speed oscillation 5 HCLKCNT HOSCCNT 1 External high speed oscillation stabilization wait time lt Switching the source oscillation of fosc HCLKCNT HCLKSEL 1 NORMAL mode SYSCLK HOSCCLK Figure 4 2 4 Clock Change Flow from HRCCLK to HOSCCLK CNT to 1 and the wait time to stabilize the frequency of HOSCLK must be ensured After HOSCCNT is stable set the HCLKCNT HCLKSEL to 1 The oscillation stabilization wait time should be determined in consultation with the manufac turer of oscillator lt Before changing the operating clock from HRCCLK to HOSCCLK set the HCLKCNT HOSC Clock Change from HOSCCLK to HRCCLK Figure 4 2 5 shows the clock change procedure from HOSCCLK to HRCCLK NORMAL mode SYSCLK HOSCCLK NO HCLKCNT HRCCNT 1 Start the internal high speed oscillation YES HCLKCNT HRCCNT
217. I is the master of Clock synchronous communication or communicates on IIC bus set the P3DIR P3DIR1 to 1 Table 7 7 4 P32 Function Selection Setup Function Register LCCTR4 SC1MD3 SC01SEL Bit name SEGSL33 SC1SBCSEN SC1SEL3 1 SEG33 1 1 0 SBCS1A 0 P32 1 When the LSI outputs the chip select signal set the P3DIR P3DIR2 to 1 Table 7 7 5 P33 Function Selection Setup Function Register LCCTR4 BUZCNT Bit name SEGSL32 BUZEN BUZSEL 1 SEG32 1 0 BUZA I 0 P33 Table 7 7 6 P34 Function Selection Setup Function Register LCCTR4 TMIOENO TM4MD TMIOSELO 1 TM7MD1 TMIOSEL1 BUZCNT Bit SEGSL31 L TM4IOSEL TM7OEN L irr NBUZEN NBUZSEL 1 SEG31 1 b 0 0 bae 0 TMAIO output 0 11 0 0 br ig 0 TM4IO input 0 1 M 01 0 7 output 0 10 01 0 input 0 Other than 1 0 NBUZA 10 0 P34 VII 44 Port3 Table 7 7 7 P35 Function Selection Setup Function Register LCCTR4 SCOMD1 SCO1SEL Bit name SEGSL30 SCOSBIS SCOIOM SCOSELO 1 SEG30 1 0 1 SBIOB RXDOB 0 0 P35 Table 7 7 8 P36 Function Selection Setup Function Register LCCTR4 SCOMD1 SCO1SEL Bitname SEGSL29 SCOSBOS SCOSBIS SCOIOM SCOSEL1
218. IA 6 3 Setting Examples etr t OG REGE E C eg to RENE VI 7 6 3 I PSVD S t ng inet Dee eet tente VI 7 Chapter 7 VO POED des alana abu kuupa sanpa iu ene adc d 1 DNO ID VII 2 I O Port Overview conte t ed reme ple tecpiep ree ndi VII 2 722 Control Registers ro tene BRE OE OO PO HE Tei epe VII 3 7 2 1 Port n Output Registers cea e e acha ERU ee ere ee teet VII 5 7 2 2 Port n Input Regist rs iced ete tee E ER PG HERI E RR enirn VII 8 7 2 3 Port n Direction Control Registers a eene eene VII 12 7 2 4 Port n Pull up Resistor Control VII 15 7 2 5 Port n N ch Open drain Control Registers essere VII 18 Contents 3 7 2 6 Port n N ch Drive Strength Selection Registers VII 22 7 2 7 8 bit Timer output control Register 25 7 2 8 8 bit Timer input output pins selection 1 esee VII 26 7 2 9 16 bit Timer output control Register VII 27 7 2 10 16 bit Timer input output pin selection Register VII 28 7 2 11 Clock output Clock output pin control Register eene VII 29 7 2 12 Analog input Control Register 0 1 VII 30 7 2 13 Analog input Control Register 1 8 00 1 VII 31 7 2 14 Buzzer output Buzzer output pin control Registe
219. ICR and IRQGICR Setting example of rising edge triggered interrupt The following example shows how to enable the rising edge triggered IRQ4 at P72 Settings Set P72 as IRQ4 pin Register IRQIEN IRQISELO IRQISEL1 Description Set IRQIEN IRQ4EN to 1 Set IRQISELO IRQASEL to 1 Set IRQISEL1 IRQACSEL to 0 Select the rising edge triggered IRQ4 IRQ4ICR Set IRQ4ICR REDG to 1 Set the Interrupt level of IRQ4 IRQ4ICR Set IRQ4ICR LV1 0 as you like IRQ4ICR IR should be set to 0 Enable IRQ4 IRQ4ICR Set IRQ4ICR IE to 1 must be changed when IRQnICR IE is 0 After the interrupt edge is changed IRQnICR IR a Interrupt edge rising edge falling edge or both edges rising edge and falling edge of IRQn must be cleared before setting IRQnICR IE is 1 External Interrupts 45 Chapter 3 Interrupts III 46 3 3 3 Both edges triggered Interrupt Both edges rising edge and falling edge interrupt can be specified with the EDGDT W Setting example of both edges interrupt The following example shows how to select the both edges triggered IRQO at P10 Settings Set P10 as IRQO pin Register IRQIEN IRQISELO Description Set IRQIEN IRQOEN to 1 Set IRQISELO IRQOSEL to 0 Set P10 as the IRQO pin 2 Select the both edges triggered IRQO EDGDT Set EDGDT EDGDTO to 1 3 Set the Interrupt level of IRQ0 IRQ0ICR Set IRQ0ICR LV1
220. IO output IGBT output TM8IO output IGBT output Figure 9 10 4 One shot Pulse Output of High Precision IGBT Normal 16 bit High Precision IGBT Output with Variable Period Duty IX 55 Chapter 9 16 bit Timer One shot Pulse Output of High Precision IGBT when compare register 2 0x0000 Timer 7 TM7EN i Flag i Count Clock 7 Lf Ei Lf Lf E ee TNA Compare Register 1 Compare Register 2 IGBT Trigger Binary i 0000 0001 0002 N TM71O output IGBT output TM8IO output IGBT output Figure 9 10 5 One shot Pulse Output of High Precision IGBT when compare register 2 0x0000 One shot Pulse Output of High Precision IGBT when compare register 2 compare register 1 Timer 7 TM7EN bit Compare register 1 Compare N register 2 i i i i IGBT trigger 0000 0001 X 0002 N X 0000 TM7IO output IGBT output TMBIO output IGBT output Figure 9 10 6 One shot Pulse Output of High Precision IGBT when compare register 2 compare register 1 IX 56 16 bit High Precision IGBT Output with Variable Period Duty Chapter 9 16 bit Timer 9 10 2 Setup Example Sa High Precision IGBT Output Setup Example is an example that using Timer 7 with HCLK 10 MHz as clock source the IGBT output wave form with the 1 4 duty cycle and 400 Hz i
221. ION SET Data Transfer Instructions MOV Dn Dm Dn Dm 1010 DnDm MOV imm8 Dm imm8 gt 1010 DmDm MOV Dn PSW Dn gt PSW 1001 01Dn MOV PSW Dm PSW gt 0001 01Dm 8 gt Dm 0100 1ADm MOV d8 An Dm mem8 d8 An Dm 0110 1ADm MOV d16 An Dm mem8 d16 An Dm 0110 1ADm MOV d4 SP Dm IB d4 SP gt Dm 0110 01Dm MOV d8 SP Dm mem8 d8 SP Dm 0110 01Dm 0110 00Dm i08 IB IOTOP io8 gt Dm 0110 00Dm MOV abs8 Dm gt Dm 0100 01Dm d16 SP MOV abs12 Dm mem8 d16 SP gt mem8 abs12 Dm 0100 00Dm MOV abs16 Dm mem8 abs16 Dm 1100 00Dm MOV Dn Am Dn 8 0101 1aDn MOV Dn 98 Dn mem8 d8 Am 0111 1 MOV Dn d16 Am Dn mem8 d16 Am 0111 1aDn MOV Dn d4 SP Dn mem8 d4 SP 0111 01Dn MOV Dn d8 SP Dn mem8 d8 SP 0111 01Dn MOV Dn d16 SP Dn mem8 d16 SP 0111 00 08 Dn mem8 IOTOP io8 0111 00 abs8 Dn mem8 abs8 0101 01Dn Dn abs12 Dn mem8 abs12 0101 00 Dn abs16 Dn mem8 abs16 1101 00Dn MOV imme io8 imm8 gt
222. IRQISELO KEYIEN KEYSEL Bit name ANENO6 IRQIGEN IRQ6SEL KEYI6EN KEY6SEL 1 AN6 1 0 0 IRQ6A 0 1 0 KEY6A 0 2 16 Table 7 5 9 17 Function Selection Setup Function Register ANEN0 KEYIEN KEYSEL Bit name ANEN07 KEYI7EN KEY7SEL 1 1 0 KEY7A 0 P17 Port 1 Chapter 7 I O Port VII 39 Chapter 7 I O Port 7 6 Port 2 The following table shows the special functions of Port 2 Table 7 6 1 Port 2 pin Special function P20 SEG42 TM1IOB TM9IOB P21 SEG41 TM5IOA P22 SEG40 SBI2B P23 SEG39 SBO2B SDA2B P24 SEG38 SBT2B SCL2B P25 SEG37 SBCS2B P26 SEG36 SBI1A RXD1A P27 NRST The assignment and selection of SEGn differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 6 1 Setup of Port 2 Table 7 6 2 P20 Function Selection Setup Function Register LCCTR5 TM1MD TMIOSELO TMIOEN1 TM9MD1 TMIOSEL1 SEGSL42 1 0 TM1IOSEL TM9OEN 0 ra 7 SEG42 Other than i 0 Oper Wan TM1IO output 11 10 T 0 TM1IO input 0 1 Otherthan 01 TM9IO output 10 10 01 TM9IO input 0 P20 VII 40 Port 2 Table 7 6 3 P21 Function Selection
223. K2 NF3SCK1 NF3SCK0 Description IRQ3 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 219 111 fscLK IRQ3 noise filter operation 0 Disabled 1 Enabled NF2SCK2 NF2SCK1 NF2SCK0 IRQ2 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 210 111 fscLK External Interrupts IRQ2 noise filter operation 0 Disabled 1 Enabled m Noise Filter 45 Control Register NFCTR45 bp 7 6 5 3 2 Chapter 3 Interrupts 1 Bit name NF5SCK2 NF5SCK1 NF5SCKO NF4SCK2 NFASCK1 NF4SCKO At reset 0 0 0 0 0 0 Access Bit name NF5SCK2 NF5SCK1 NF5SCKO Description IRQ5 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 210 111 fci IRQ5 noise filter operation 0 Disabled 1 Enabled NF4SCK2 NF4SCK1 NF4SCKO IRQ4 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 210 111 fscLK IRQ4 noise filter operation 0 Disabled 1 Enabled External Interrupts Ill 41 Chapter 3 Interrupts III 42 N
224. LK 4 0011 BRT2SCLK 8 0100 BRT2SCLK 16 0101 BRT2SCLK 32 0110 BRT2SCLK 64 0111 BRT2SCLK 128 1000 BRT2SCLK 256 1001 SYSCLK 1010 SYSCLK 2 1011 SYSCLK 4 1100 SYSCLK 8 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRT2SCLK is the clock selected with BRTM S CKSEL BRTM S2 CKSEL XIII 26 Control Registers Chapter 13 Serial Interface 13 2 11 Compare Register aaa BRTMn n 0 1 2 3 Compare Register BRTM_S0_OC BRTM S1 OC BRTM S2 OC BRTM_S3 Bit name Initial value Access m Dem _ _ Sn_OC7 0 compare register Control Registers 27 Chapter 13 Serial Interface XIII 28 13 3 Clock Synchronous Communication This section describes the Clock Synchronous communication The index of serial interface SCIF denotes 0 1 2 3 unless otherwise noted When communicating with Clock Synchronous by using SCIFn n 0 1 set SCnMD1 SCnCMD to 0 When communicating with Clock Synchronous by using SCIFn n 2 3 set SCnMD3 SCnCMD to 0 13 3 4 Form 2 wire Communication Data transmission or reception is executed with a clock pin SBTn and a data pin SBOn or SBIn SBOn can be used for data transmission and reception SBIn is used only for data reception 3 wire Communication Data transmission and reception are executed with 3 pins SBTn SBOn and SBIn SBOn
225. LO TMIOEN1 TM7MD1 TMIOSEL1 BUZCNT TMOOEN TMOCK1 0 TM7OEN TM7CK1 0 SU NBUZEN NBUZSEL 1 0 7 than 0 TMOIO output 0 11 1 0 Ed 0 TMOIO input 1 10 0 7 output 0 Other than 10 10 0 TM7IO input 11 0 Other than 1 1 NBUZB 10 0 P03 Table 7 4 6 P04 Function Selection Setup Function Register SC3MD1 SC23SEL TMIOEN1 TM7MD1 TMIOSEL1 Bitname SC3SBOS SC3SBIS SC3IOM SC3SEL1 TM7OEN TM7CK1 0 161 2 2 0 0 5 Other than 5 1 1 0 0 10 1 than 00 7 output 0 0 0 10 00 TM7IO input 0 Other than 15 P04 1 When serial data is output set the PODIR P0DIR4 to 1 2 When serial data is input and output set the bit to 1 Port 0 VII 35 Chapter 7 I O Port Table 7 4 7 P05 Function Selection Setup Function Register SC3MD1 SC23SEL TMOMD TMIOENO TM2MD TMIOENO TMIOSELO CLKOUT TM0IOSE CLKOEN Bitname SC3SBTS SC3SEL2 1 0 TMOOEN 2 1 0 TM2OEN CLKOSEL 11 0 mae 0 0 a 0 1 a ii 0 or TMOIO output 11 ee 0 0 TMOIO input 0 1 0 O TM2IO output 0 Other than 11 0 0 TM2IO input 11 Otherthan 0 1 0 CLKOUTA
226. M7MD1 0x03FA8 Timer 7 mode register 1 TM7MD2 0x03FA9 Timer 7 mode register 2 TM7OC2L Timer 7 compare register 2 lower 8 bits TM7OC2H 0x03FAB Timer 7 compare register 2 upper 8 bits TM7PR2L 0 0 Timer 7 preset register 2 lower 8 bits TM7PR2H 0x03FAD Timer 7 preset register 2 upper 8 bits TM7DPR1 OxOSFAE Timer 7 dead time preset register 1 TM7DPR2 Ox03FAF Timer 7 dead time preset register 2 TM7MD3 Timer 7 mode register 3 TM7MD4 0x03F9E Timer 7 mode register 4 TM7ICR OxOSFEF Timer 7 interrupt control register TM7OC2ICR OxOSFFO Timer 7 compare register 2 match interrupt control register TM8BCL 0x03FB0 R Timer 8 binary counter lower 8 bits TM8BCH 0x03FB1 R Timer 8 binary counter upper 8 bits TM8OC1L 0x03FB2 Timer 8 Compare register 1 lower 8 bits TM8OC1H 0x03FB3 Timer 8 Compare register 1 upper 8 bits TM8PR1L 0x03FB4 Timer 8 preset register 1 lower 8 bits TM8PR1H 0x03FB5 Timer 8 preset register 1 upper 8 bits TM8ICL 0x03FB6 Timer 8 input capture register lower 8 bits TM8ICH 0x03FB7 Timer 8 input capture register upper 8 bits TM8MD1 0x03FB8 Timer 8 mode register 1 TM8MD2 0x03FB9 Timer 8 mode register 2 TM8OC2L Timer 8 compare register 2 lower 8 bits TM8OC2H 0x03FBB Timer 8 compare register 2 upper 8 bits TM8PR2L 0x03FBC Timer 8 preset register 2 lower 8 bits TM8PR2H 0x03FBD Timer 8 preset register 2 upper 8 bits TM8MD3 0x03FBF Timer 8 mode register 3 TM8MD4 0x03F
227. MIE is 1 When the multiple interrupt acceptance is enabled be careful not to happen stack overflow 12 Overview Chapter 3 Interrupts The following figure shows the processing sequence when the higher priority level interrupt occurs while process ing the lower priority level interrupt Interrupt 1 LV1 0 10 Interrupt 2 LV 1 0 00 Main Program PSW IM1 0 11 Interrupt 1 occurs z Accepted because LV1 0 lt IM1 0 LV1 0 10 MIE 1 IM1 0 10 Interrupt acceptance cycle Interrupt handler 1 Interrupt 2 occurs Z Accepted because MIE 1 and LV1 0 lt IM1 0 LV1 0 00 M1 0 00 Interrupt acceptance cycle Interrupt handler 2 Restart interrupt handler 1 RTI IM1 0 10 RTI IM1 0 11 Y Parentheses indicates hardware processing Figure 3 1 7 Processing Sequence for Multiple Interrupts Overview Ill 13 Chapter 3 Interrupts NMI Processing Figure 3 1 8 shows the processing sequence of NMI PSW IM1 0 11 NMI 1 occurs 0 00 Interrupt acceptance cycle NMI handler 1 NMI 2 occurs 2 RTI IM1 0 11 IM1 0 00 Interrupt acceptance cycle j NMI handler 2 RTI IM1 0 11 Parentheses indicates hardware processing Y 51 The multiple interrupts n
228. MOD 1 HOSCCLK HRCCLK SRCCLK are stopped HALT3 mode fgqsccLk 32 768 kHz C12 12012 3 0 V Vppig 1 1 V 2 9 85 C HALTMOD 1 HOSCCLK HRCCLK SRCCLK are stopped Vosige fV 25 C 1 24 Gis 2013 HOSCCLK HRCCLK 0 00 20 Supply current in SOSCCLK SRCCLK are stopped STOP Vooo 3 0 V 1 1 1 V 85 14 z 2 6 0014 HOSCCLK HRCCLK SOSCCLK SRCCLK are stopped 12 The supply current is measured with Ta 25 C no load and all the analog part in the power down state The pull up down resis tors are not connected Each supply current is measured with the following conditions Ipp1 5 Operating supply current After setting all input and output pins to the input mode Vppig the Logic supply voltage to 1 8 V the oscillation mode to NORMAL the external oscillation fix the input pins to level and input the 10 4 MHz square wave which has the amplitude from to Vss from OSC1 pin 1602 4 Operating supply current After setting all input and output pins to the input mode the Logic supply voltage to 1 8 V the oscillation mode to NORMAL the internal high oscillation 10 8 MHz fix the input pins to level Ippe Operating supply current After setting all input and output pins to the input mode Vpp1g the Logic supply voltage to 1 3 V the oscilla
229. MS 9Siuw peeu LSWUOS LGWYOS ____ x vuigs iulgs 4188105 1856205 vulgs 0125008799208 lt INOIUOS guogs gt vuogs 13 1 2 SCIFn n 2 3 Block Diagram Figure Overview XIII 6 13 2 Control Registers Seri Chapter 13 al Interface Registers of SCIFn and baud rate timer hereafter indicated as BRTMn that generates a transfer clock are shown in Table 13 2 1 13 2 1 Registers Register symbol SCOMDO Table 13 2 1 Serial Interface Control Registers Address 0x03E30 Access Register name SCIFO Mode Register 0 XIII 11 SCOMD1 0x03E31 SCIFO Mode Register 1 XIII 13 SCOMD2 0x03E32 SCIFO Mode Register 2 XIII 15 SCOMD3 0x03E33 SCIFO Mode Register 3 XIII 17 SCOSTR 0x03E34 SCIFO Status Register XIII 19 RXBUF0 0x03E35 SCIF0 Reception Data Buffer XIII 10 TXBUF0 0x03E36 SCIF0 Transmission Data Buffer XIII 10 SC01SEL 0x03F1C SCIF01 I O Pin Switching Control Register XIII 9 SC1MD0 0x03E40 SCIF1 Mode Register 0 XIII 11 SC1MD1 0x03E41 SCIF1 Mode Register 1 XIII 13 SC1MD2 0x03E42 SCIF1 Mode Register 2 XIII 15 SC1MD3 0x03E43 SCIF1 Mode Register 3 XIII 17 SC1STR 0x03E44 SCIF1 Status Register XIII 19
230. NPE SCnPM1 SCnPMO Transmission Reception Fixed to 0 Confirm parity bit is 0 Fixed to 1 Confirm parity bit is 1 For the total number of 1 of Confirm the total number of 1 of character bit odd 0 even 1 character and parity bits is odd For the total number of 1 of Confirm the total number of 1 of character bit odd 1 even 0 character and parity bits is even Parity bit is not added Parity bit is not checked Full duplex UART Communication XIII 47 Chapter 13 Serial Interface 13 4 2 Operation Circuit Initialization Serial Reset SCIFn has a built in serial reset function for abnormal operation Registers other than TXBUFn and SCnMD2 SCnBRKE must be changed during serial reset SCnSTR SCnMD2 SCnBRKF are initialized by setting both SCnMD3 SCnRSTN and SCnMD3 SCnRSRN to 0 m Pin Settings lt wire communication At data reception Set SCnMD1 SCnSBIS to 1 and SCnMD1 SCnSBOS to 0 At data transmission Set SCnMD1 SCnSBIS to 0 and SCnMD1 SCnSBOS to 1 When SCnMD1 SCnIOM is 1 data reception via SBOn is enabled lt 2 wire communication gt Set both SCnMD1 SCnSBIS and SCnMD1 SCnSBOS to 1 SCnIOM must be set to 0 UART communication set SCnMD1 SCnSBTS SCnMD3 SCnSBCSEN to 0 1 In time division 1 wire communication with SBOn be sure to prevent data collision at SBOn When the LSI only send data no
231. O DOJ Ed lt gt Chapter 10 General Purpose Time Base Free Running Time Chapter 11 Time Base Chapter 12 Real Time Clock Chapter 13 Serial Interface Chapter 14 DMA Controller Chapter 15 Buzzer Chapter 16 A D Converter ADC Chapter 17 LCD Chapter 18 ReRAM Chapter 19 On Board Debugger Chapter 20 Appendix ND gt oo N O01 E LO Contents Contents Chapter Ov Srv OW Pid Hardware 2 1 2 Comparison of Product Specification cece 1 7 13 ondb ios 1 11 1 3 1 Pin Configuration aene een er thee tie ie 1 11 1 3 2 Pin Description eoe eite ete q hasa su q 1 15 1 4 Electrical Characteristics u 1 4 1 Absolute Maximum Ratings a 1 4 2 Operating 801 1 43 DC CHaracteristiCs i eie eee rhe e ie o ee dye t cede et ee de 1 4 4 A D Converter Characteristics 1 4 5 Reset Power supply Detection 1 29 1 4 6 ReRAM Program Condition eese 1 30 1 5 Package ne otra ORO dU ED aie ARMs ae 1 31 1 6 Cautions for Circuit Setup eaedem eet ted
232. O register lower 16 bit by the unsigned 16 bit value of AO register and stores the quotient 16 bit of the result in DWO register and the remainder 16 bit of the result in DW1 register Bit Changes Size Cycles Codes If VF is 0 VF 0 if the quotient is an unsigned 16 bit value NF Set if the MSB of the quotient is 1 otherwise set to CF 0 ZF Set if the MSB of the quotient is 0 otherwise set to 0 If VF is 1 VF 1 if the quotient is not an unsigned 16 bit value NF Undefined CF 0 ZF Undefined W Execution of 32 bit 16 bit division unsigned 6 nibbles 21 cycles 0000 0010 0111 0000 0100 0000 1 Store the upper 16 bit of the dividend to DW1 register the lower 16 bit of the dividend to DWO register and the divisor to AO register 2 Execute MOV 0x04 0x03F07 Extended calculation macro instruction DIVWU 3 The value of the unsigned 32 bit which is stored in register upper 16 bit and DWO register lower 16 bit is divided by the value of the unsigned 16 bit of AO register Then the quotient 16 bit of the result is stored in DWO register and the remainder 16 bit of the result is stored in DW1 register appointing an option mmuldivw a This extended calculation instruction is generated by the compiler for MN101L series by 1 When this extended calculation instruction is the handy address is updated 0x03F07
233. O input TM2IO input TM4IO input HCLK Machine clock for High speed oscillation SCLK Machine clock for Low speed oscillation SYSCLK System clock 4 1 Clock Control 8 bit Timer Cascade Connection VIII 31 Chapter 8 8 bit Timer VIII 32 The binary counters and the compare registers corresponding to two timers in cascade connection operate as a 16 bit register respectively When activating the timer set the TMnMD TMnEN for lower 8 bit timer to 1 A waveform of the timer pulse and an interrupt request is output from the upper 8 bit timer Select the clock source with the register for the lower 8 bit timer Other settings and the timing to count are the same as a single 8 bit timer operation When using Timer 0 connected with Timer 1 in cascade a timer pulse and an interrupt request are output from Timer 1 Low fixed data are output from Timer 0 as the timer pulse Timer 0 interrupt should be disabled though any interrupt request of Timer 0 is not generated When using Timer 2 connected with Timer 3 in cascade a timer pulse and an interrupt request are output from Timer 3 Low fixed data are output from Timer 2 as the timer pulse Timer 2 interrupt should be disabled though any interrupt request of Timer 2 is not generated When using Timer 4 connected with Timer 5 in cascade a timer pulse and an interrupt request are output from Timer 5 Low fixed data are output from Timer 4 as
234. OA pin In order to output a 50 kHz pulse select HCLK for clock source and set 1 2 cycle 100 kHz in the Timer 7 compare register HCLK at fici 8 MHz is selected as a clock source The setup procedure and its description are shown below Setting Register Description Disable the timer counter TM7MD TM7EN 0 Disable the timer count operation Select the timer output pin TMIOEN1 TM7OEN 1 Select the timer output pin PODIR PODIR4 1 Chapter Z VO Porl Set the timer mode register TM7MD2 TM7PWM 0 Select the timer output TM7MD2 TM7BCR 1 Select the TM7BC clear source TM7MD1 TM7CL 0 Enable the timer output TM7MD1 TM7CK1 0 00 Select HCLK as the count clock source TM7MD1 TM7PS1 0 00 Set the output cycle TM7PR1 0x004F Set the timer output cycle Setup value 80 1 79 0x004F Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation IX 30 16 bit Timer Pulse Output Chapter 9 16 bit Timer 9 6 16 bit Standard PWM Output with Continuously Variable Duty 9 6 1 Operation In the standard PWM output function a PWM waveform with a given duty cycle can be generated and output from TMnIO pin 16 bit Standard PWM Output PWM waveform with a given duty cycle is generated by setting TMnOCI to High period of the PWM duty And the period of the PWM is the time of the full count overflow of the 16 bit timer The PWM output pin is shown i
235. OC1 1 Set duty through TM8OC2 TM8BCR Select timer clear source 0 Overflow by full count 1 Match between TM8BC and TM8OC1 TM8PWM Select timer output waveform 0 Timer output 1 PWM output TM8IRS1 Select timer interrupt source 0 Counter clear 1 Match between TM8BC and TM8OC1 T8ICEN Input capture operation enable 0 Disabled 1 Enabled T8ICT1 0 Select capture trigger 00 External Interrupt 0 input signal 01 External Interrupt 1 input signal 10 External Interrupt 2 input signal 11 Timer Interrupt 16 bit Timer Control Registers IX 15 Chapter 9 16 bit Timer W Timer 8 Mode Register 3 TM8MD3 0x03FBF Bit name TM8SEL TM8PWMF IM8PWMO At reset 0 0 0 0 0 Access Bit name Description Select sampling clock for capture TM8CKSMP 0 Count clock 1 SYSCLK Always read as 0 Select count edge of TM8IO TM8CKEDG 0 Falling edge 1 Both edges Select output TM8SEL 0 Timer 8 output 1 IGBT output Control PWM output while Timer 8 is stopped TM8PWMF 0 Low 1 High Select polarity of Timer 8 PWM output TM8PWMO 0 Normal 1 Inverted Always read as 0 lt When capture function is not used set the TM8MD3 TM8CKSMP to 0 IX 16 16 bit Timer Control Registers W Timer 8 Mode Register 4 TM8MD4 0x03F9F Bit name Chapter 9 16 bit Timer T8ICT2 T8CAPCLR At reset 0 0
236. OICR 0x03FFD Group 0 interrupt level control register PERIOEN 0x03FDC Group 0 interrupt enable register PERIODT 0x03FDD Group 0 interrupt factor register PERI1ICR OxOSFFE Group 1 interrupt level control register PERI1EN Group 1 interrupt enable register PERI1DT 0x03FDF Group 1 interrupt factor register III 20 Control Registers Chapter 3 Interrupts Write access to xICR must be done when PSW MIE is There s no guarantee of proper operation if xICR is written with when PSW MIE is 1 When an xICR LV1 0 is set to 11 the interrupt IRQ does not occur Control Registers III 21 Chapter 3 Interrupts 3 2 1 Non maskable Interrupt NMI Control Register Non maskable Interrupt NMI Control Register NMICR 0x03FE1 When the undefined instruction is detected IRQNPG is set to 1 and NMI occurs When the WDT overflows IRQNWDG is set to 1 and NMI occurs bp 6 5 4 3 2 1 0 Bit name IRQNPG IRQNWDG Reserved At reset 0 0 0 0 0 0 0 Access R R R R R W R W R W 7 3 Always read as 0 Detection of Undefined instruction execution IRQNPG 0 Not detected 1 Detected WDT overflow detection IRQNWDG 0 Not detected 1 Detected Reserved Must be set IRQNPG is not cleared by hardware Before RTI instruction is executed in the NMI interrupt 1 handler they must be cleared
237. OM1 SEG5 Frame period Chapter 17 LCD VLCD lt lt lt lt lt lt lt lt lt lt lt lt Vss 1 3Vucp 0 1 3 4 VLcD 1 3Vucp 0 1 3 Figure 17 4 3 LCD display example in 1 3 duty LCD Display Examples XVII 33 Chapter 17 LCD 17 4 6 LCD Operation Setup 1 3 duty aa r G The following example is to display 23 on 8 segment type LCD panel two digit display through segment pins SEGO to SEGS and common pins COMO to COM2 with 1 3 duty and 1 3 bias supplied from external volt age divider The specific settings are as follows HCLK 4 MHz LCD display clock HCLK 2 gt 122 Hz Frame frequency 41 Hz Setup Procedure Description 1 Stop the LCD LCDMD2 0x03E82 bp7 LCEN 0 2 Set a display duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 010 3 Set an LCD clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 LCCTRO 0x03E86 bp7 4 SEGSL3 0 1111 bp2 0 COMSL2 0 111 1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 5 Set LCD panel display data LCDATAO 0x03E90 0x06 LCDATA1 0x03E91 0x07 LCDATA2 0x03E92 0x00 LCDATAS3 0x03E93 0x04 LCDATA4 0x03E94 0x07 LCDATAS5 0x03E95 0x02 6 Activate the LCD LCDMD2 0x03E82 bp7 LCEN 1 4 Set Segment and common output pins 1 Stop the LCD
238. OMSL2 COMSL1 COMSLO At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LRO5D MN101LRO4D MN101LROS3D COM7 SEG3 P70 selection SEG3 P64 selection SEGSL3 0 P70 0 P64 1 COM7 SEG3 1 SEG3 COM6 SEG2 P71 selection SEG2 P65 selection SEGSL2 0 P71 0 P65 1 COM6 SEG2 1 SEG2 Must be set to 0 COM5 SEG1 P72 selection SEG1 P66 selection SEGSL1 0 P72 0 P66 1 COM5 SEG1 1 SEG1 COM4 SEG0 P73 selection SEGO P67 selection SEGSLO 0 P73 0 P67 1 COM4 SEGO 1 SEGO COM3 P74 selection COM3 P70 selection COMSLS3 0 P74 0 P70 1 COM3 1 COM3 COM2 P75 selection COM2 P71 selection COMSL2 0 P75 0 P71 1 COM2 1 COM2 COM1 P76 selection COM1 P72 selection COMSL1 0 P76 0 P72 1 COM1 1 COM1 77 selection 73 selection COMSLO 0 P77 0 P73 1 COMO 1 COMO Control Registers XVII 9 Chapter 17 LCD LCD Port Control Register 1 LCCTR1 0x03E87 Bit name SEGSL11 SEGSL10 SEGSL9 SEGSL8 SEGSL7 SEGSL6 SEGSL5 SEGSL4 At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG11 P60 selection SEG11 P50 selection SEGSL11 0 P60 0 P50 Must be set to 0 1 SEG11 1 SEG11 SEG10 P61 selection SEG10 P55 selection SEG6 P55 selection SEGSL10 0 P61 0 P55 0 P55 1 SEG10 1 SEG10 1 SEG6 SEG9 P62 selection SEGO9 P56 selection SEG5 P56 selection SEGSL9 0 P62 0 P56 0 P56 1 SEG9 1 EG9 1 SEG5 SEG8 P63 selection
239. OP Figure 4 2 1 shows the transition between each operation mode For detail of transition between operation mode VDD 18 voltage and clock refer to 4 4 Mode Voltage Clock Transition CPU operation mode NORMAL mode N N j l HALTO mode gt HCLK oscillation SCLK oscillation STOP mode HCLK CPU operation l l SCLK oscillation stop Stop STOP0 mode 2 HALT2 mode i T gt l HCLK stop s 4 HCLK stop SCLK stop lt SCLK oscillation 1 A ff PH I I IDLE mode 51 2 oscillation 3 SCLK CPU operation 2 2 I Stow mode HALT1 mode HALTMOD 0 I l stop n SCLK oscillation HCLK stop Stop E SCLK CPU operation SCLK stop ty P HALTS mode HALTMOD 1 HCLK stop SCLK oscillation x X 1 Oscillation stabilization wait time is automatically inserted HCLK High speed oscillation clock 2 When changing from the state that SCLK SCLK Low speed oscillation clock is stopped oscillation stabilization wait time is inserted 3 Ensure adequate time for oscillation stabilization by program Figure 4 2 1 Transition between Operation Modes Do not perform the transition that is not listed in Figure 4 2 1
240. Operation Adds the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and PSW CF and stores the result 8 bit after the BCD correction to the D0 reg ister Bit Changes Size Cycles Codes VF 0 6 nibbles 0 4 cycles CF Set if the result is bigger than 99 otherwise set to 0 ZF Set if the result is 0 otherwise set to 0 0000 0010 0111 0000 0000 0010 W Execution of BCD addition without carry 1 Store the 8 bit value of the two digit BCD to add to the DO register and D1 register Store the carry in the PSW 2 Execute MOV 0x20 0x03F07 Extended calculation macro instruction BCDADDC 3 Adds the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and PSW CF and stores the result 8 bit after the BCD correction to the DO register a When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it 1 the result is not guaranteed Extended Calculation Instruction 25 Chapter 2 CPU II 26 2 4 7 BCDSUB 0 40 0x03F07 BCDSUB BCD subtraction without carry a a Operation DO BCD D1 BCD DO BCD Subtracts the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and stores the result 8 bit af
241. Panasonic MICROCOMPUTER MN101L MN101LR05D 04D 03D 02D LSI User s Manual Pub No 21705 015E Request for your special attention and precautions in using the technical information and semiconductors described in this book 1 If any of the products or technical information described in this book is to be exported or provided to non residents the laws and regulations of the exporting country especially those with regard to security export control must be observed 2 The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company Therefore no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book 3 The products described in this book are intended to be used for general applications such as office equipment communications equipment measuring instruments and household appliances or for specific applications as expressly stated in this book Consult our sales staff in advance for information on the following applications Special applications such as for airplanes aerospace automotive equipment traffic signaling equipment combustion equipment life support systems and saf
242. RQ1A KEY1A 1 11 P43 SEG24 SBT2A SCL2A IRQ4C AN2 P12 P42 SEG25 SBO2A SDA2A 5 1 P41 SEG26 SBI2A VREFP P40 SEG27 SBCS0B Figure 1 3 1 MN101LR05D Pin Configuration OQ st LO XO F O xh L0 O O v Q CO st QR ROXORON QU GI QI QI G QI CD CO CD 02 CD 00 OD 3 9 55 88588 59856505 EEEE LOROLO KOROLO KOKOKOKOKO KORO 22 00 0 0 9 9 9 0 CO CD 93 03 CO lt lt lt lt lt lt ETEO lt lt lt 56722 9 2mm wt 10 co y ae 666 2 FO 920 9 mm Ha zd gt oo 72 gt 00 xg CU S lt 5 IO 5 E oo Pin Description 1 11 Chapter 1 Overview 1 12 IRQ2A IRQ3A 2 IRQ4C 2 IRQ5C Pin Description N 2 4 O O AN2 P12 4 14 ANS P13 4 gt 15 VREFP VDD11 DMOD CLK IRQ4A KEYAA 4 14 VDD18 VDD30 VLC1 P85 VLC2 m gt Bon Lau 200 000 200000 QN CO QN ST o 00 G 5 P70 COM3 IRQ6B P65 SEG2 SBOOA TXDOA KEY5B P64 SEG3 SBIOA RXDOA KEY4B P67
243. Running Timer 12 10 4 Time Base Timer 10 4 1 Operation W Time Base Timer Time Base Timer The timer generates interrupts regularly by selecting a clock source and a interrupt generation cycle Table 10 4 1 shows the interrupt generation cycles on each clock source Table 10 4 1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle 27 x 16 us 28 1 32 us 29 x 64 us 210 x 1 128 us HCLK 21 x 1 512 us 213 1 1024 us 214 x 2048 us 215 4096 us 2 x 3 9 ms 28 x 7 8 ms 2 x l fsci 15 6 ms 210 x 4 feci 31 3 ms SCLK 212 x 1 fscLK 125 ms 213 x 1 fscLk 250 ms 214 x 500 ms 215 x 1000 ms 8 MHz fsck 32 768 kHz Time Base Timer Chapter 10 General Purpose Time Base Free Running Timer W Count Timing of Timer Operation Time Base Timer The counter counts up with the selected clock source as a counter clock 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 10 9 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 Figure 10 4 1 Count Timing of Timer Operation Time Base Timer e When the selected interrupt cycle elapsed the time base interrupt request PERIODT2 of the peripheral function group 0 interrupt factor register PERIODT is set to 1 Stop the timer when switching the coun
244. SCnSBOS SCnMD1 SCnSBIS SCnMD1 SCnSBTS SCnMD2 SCnSBCSEN Set pins to be used for serial communication to 1 Pin setting Enable serial output PnMD Enable communication pins Clear interrupt source SCnTICR SCnTIR 0 Clear the interrupt source Enable interrupt SCnTICR SCnTIE To use an interrupt set SCnTICR SCnTIE to 1 BRTMm counting start BRTM_S_EN BRTM_Sn_E N 1 BRTM starts counting XIII 42 11 Clock Synchronous Communication Release serial reset SCIFn n 0 1 SCnMD3 SCnRSTN 1 lt SCIFn 2 3 SCnMD2 SCnRSTN 1 Release the serial reset After that serial communication is enabled Chapter 13 Serial Interface m Data Transmission Reception 1 byte Communication Mode Setting Register name Empty confirmation of transmis SCnSTR SCnTEMP sion buffer Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn TXBUFn Set transmission data in TXBUFn Wait for communication comple tion lt SCIFn n 0 1 gt SCnSTR SCnTBSY SCnSTR SCnRBSY SCIFn n 2 3 gt SCnSTR SCnTBSY lt SCIFn n 0 1 gt When the communication has been completed SCnTBSY and SCnRBSY become 0 When an interrupt is enabled a communication complete inter rupt SCnTIRQ occurs lt SCIFn n 2 3 gt When the communication has been completed SCnTBSY becomes 0 When interrupt is enabled a communication complete inte
245. SEGO SBCSOA KEY7B P66 SEG1 SBTOA 6 MN101LR04D KEY7A AN7 P17 IRQ6A KEY6A 6 16 OCD DATA IRQ5A KEYSA AN5 P15 64 pin Top View e N GN CN QN CO B n BD CE o X LO CV N GN 00000 WW LLI LLI LLI LLI LLI 000000 amp lt lt lt asss dadag s Bg NBUZA TM4IOA TM7IOB SEG23 P34 lt gt 129 SBI0B RXD0B SEG22 P35 SBO0B TXD0B SEG21 P36 SBT0B SEG20 P37 P63 SEG4 IRQ3B P62 SEG5 IRQ2B P61 SEG6 IRQ1B P60 SEG7 IRQ0B P57 SEG8 TM8IOA KEY3B CLKOUTB P56 SEG9 TM3IOA KEY2B P55 SEG10 TM1IOA KEY1B P50 SEG11 SBCS1B P47 SEG12 SBT1B P46 SEG13 SBO1B TXD1B 45 5 014 5 1 RXD1B P44 SEG15 SBCS2A P43 SEG16 SBT2A SCL2A P42 SEG17 SBO2A SDA2A P41 SEG18 SBI2A P40 SEG19 SBCS0B Figure 1 3 2 MN101LR04D Pin Configuration m gt 92598 2000 2555 oo C lea O OOO 0 22000000 Q OQ 2 0 gt gt gt gt O D G O LO CO N Sb Sb Sb CO vss 10 P63 SEGO xi 2 P62 SEG1 XO 3 P61 SEG2 NATRON 4 P60 SEG3 P27 NRST 5 P57 SEG4 IRQ2A OSC1 P80 6 MN101 LRO3D P56 SEG5 IRQ3A OSC2 P81 7 48 pin P55 SEG6 TM7IOA SBO3A SDASA P04 gt 8 View P44 SEG7 CLKOUTA TM2IOA TMOIO
246. Select the capture trigger edge Set the external interrupt IRQISELO IRQOSEL 0 IRQIEN IRQIOEN 1 Enable the external interrupt pin Set the timer mode register TM7MD3 TM7CKSMP 0 Select the count clock for capture sampling Set the external interrupt IRQOICR REDGO 1 Set the external interrupt valid edge Set the interrupt level IRQOICR IRQOLV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Enable the interrupt IRQOICR IRQOIE 1 Set the timer mode register TM7MD2 T7ICEN 1 Enable the capture trigger function Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation counts up from 0x0000 Synchronizing with the External Interrupt 0 input signal the value of TM7BC is loaded to TM7IC At that time the pulse width from a rising edge of the external interrupt input signal to the next rising edge can be measured by reading the value of TM7IC through the interrupt process and calculating the difference between that value and the last capture value the last value of TM7IC IX 46 16 bit Timer Capture Function Chapter 9 16 bit Timer 9 9 16 bit Standard IGBT Output with Variable Duty Trigger of the standard IGBT output be selected from 1 2 and Timer 7 count operation After starting the count operation the other operation is the same as that of the 16 bit standard PWM output 1
247. Setup Example Here is an example that a 50 kHz pulse is output from TMOIO pin of Timer 0 In order to output a 50 kHz pulse select SYSCLK 2 for clock source and set 1 2 cycle 100 kHz in the Timer 0 compare register at fgyscik 10 MHz The setup procedure and the description of each step are shown below Setting Register Description Disable the timer counter TMOMD TMOEN 0 Disable the timer count operation Select the timer output TMIOENO TMOOEN 1 Select the timer output pin PODIR PODIRS 1 Chapter 7 VO Ror Set the timer mode register TMOMD TMOPWM 0 Select the timer normal operation TMOMD TMOMOD 0 TMOMD TMOCK1 0 01 Select the prescaler as the clock source Set the prescaler CKOMD TMOPSC1 0 Select SYSCLK 2 CKOMD TMOBAS 1 Set the output cycle 0x31 Set the timer output cycle Setup value 49 0x31 Enable the timer counter TMOMD TMOEN 1 Enable the timer count operation If any data are written to TMnOC while TMnBC is stopped the timer output turns to Low VIIl 24 8 bit Timer Pulse Output Chapter 8 8 bit Timer 8 6 8 bit PWM Output 8 6 1 Operation Timer 0 Timer 2 and Timer 4 8 04 PWM Output Operation Timer 0 Timer 2 and Timer 4 have PWM function a PWM waveform with a given duty cycle is generated by set ting TMnOC to High period of the PWM duty And the period of the PWM is the time of the full count overflow
248. TM Compare R egISfer DS aS nennen nennen enne XIII 27 13 3 Clock Synchronous Communication essent nennen trennen eene erret XIII 28 133 IINE p P LE XIII 28 13 3 2 Operation u en gere isl Hp bt pai a opa XIII 29 13 3 3 Operation Timing a nuna iei ert eerte eto saus XIII 39 13 3 4 Settna Procedure ie toti preferite ae edens XIII 41 13 4 Full duplex UART Communication s esseere a eene nen nennen nennen ene XIII 46 13 4 1 Communication XIII 46 Contents 7 13 42 Operation ORDRE XIII 48 13 4 3 Dimimg s See ere e beet te ead a AM ds XIII 52 1344 Set ng procedure eoe medetur XIII 54 13 5 TIC Communication itr re i Rp XIII 56 13 5 1 Form t sana D a a Se Q ey oon 56 13 52 Operation orte pte ei ete eite ries XIII 57 13 5 3 Taming 3 aD a N RUE eH RH a XIII 62 135 Setup o itta ee oet tci tung XIII 68 Chapter 14 DMA Controller XIV 1 T4 POVE EW XIV 2 1471 1 Block Ee he XIV 3 14 2 DMA Controller Control 1 XIV 4 1421 DMA Control Register e ope t eh be yen ttes XIV 5 14 2 2 DMA Source Address Register sasaqa sayana XIV 9 14 2 3 DMA Destination Address Register essere XIV 10 14 2 4 DMA Tran
249. TM7ICR 0x03FFX TM8ICR iue TM9ICR ca SCORICR SCOTICR SC1RICR SC1TICR SC2TICR SC2SICR SC3TICR SC3SICR ER eR Reserved Reserved Reserved Reserved Reserved Do not access read write to the Reserved address If accessing them proper operation is Y not guaranteed Overview 13 Chapter 2 CPU Il 14 2 2 Bus Interface 2 2 1 Bus Controller The CPU provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation There are three buses ROM bus RAM bus and peripheral extension bus C BUS They connect to the internal ROM internal RAM internal peripheral circuits respectively The bus control block controls the parallel opera tion of instruction read and data access Figure 2 2 1 shows functional block diagram of the bus controller Interrupt control Instruction queue Program address Operand address Bus controller Interrupt bus Address decoder Memory mode setting Memory control register Instruction input bus Data input bus Data output bus Peripheral extension bus C BUS Internal peripheral functions Figure 2 2 1 Functional Block Diagr
250. TMmBAS CKmMD register TMmCAS bit TMmMD register register TMmIRQ interrupt HCLK 4 e S X HCLK 16 detection HCLK 32 MnBC register TMnIRQ interrupt HCLK 64 SYSCLK 2 X Overflow Timer n output TMnIO output ee SCLK TMnIO TMnCK1 0 TMnMD register TMnPSC1 0 TMnBAS CKnMD register Figure 8 1 1 Block Diagram of Timer n and Timer m Overview VIII 3 Chapter 8 8 bit Timer 8 2 8 bit Timer Control Registers 8 bit Timer control registers consist of following registers Timer prescaler selection registers Programmable timer registers Timer mode registers Table 8 2 1 shows registers that control 8 bit Timers Table 8 2 1 8 bit Timer Control Registers Address Register Name TMOBC 0x03F70 Timer 0 binary counter TM0OG 0x03F72 Timer 0 compare register Timer 0 TM0MD 0x03F74 Timer 0 mode register CK0MD 0x03F76 Timer 0 prescaler selection register TM0ICR OxOSFEA Timer 0 interrupt control register TM1BC 0x03F71 Timer 1 binary counter TM1OG 0x03F73 Timer 1 compare register Timer 1 TM1MD 0x03F75 Timer 1 mode register CK1MD 0x03F77 Timer 1 prescaler selection register TM1ICR 0x03FEB Timer 1 interrupt control register TM2BC 0x03F80 Timer 2 binary counter TM2OG 0x03F82 Timer 2 compare register Timer 2 TM2MD 0x03F84 Timer 2 mode register CK2MD 0x03F86 Timer 2 prescaler se
251. The instruction for the transition to STANDBY mode must not be executed in the internal RAM Table 4 3 1 Writing error correction 2 16 kHz lt lt 40 kHz 2 16 kHz lt fsyscLk lt 40 kHz 32 kHz lt fscLK lt 40 kHz Note 4 Description addition The voltage of VDD18 can be changed to match the following conditions Note 4 Description addition The voltage of VDD18 can be changed to match the following conditions PWCTR1 Writing error correction 000 8 fscuk 256 us at fscuk 111 51 2 fscLK 16384 us at 4 000 8 fscuk 244 us at fscuk 111 512 fscuk 15625 us at fsck Note 2 Description addition Only the clock supplied to CPU is halted Table 7 6 1 Table 7 7 1 Table 7 8 1 Table 7 9 1 Table 7 10 1 Table 7 11 1 remark Writing error correction The assignment and selection of 17 2 3 LCD Port Control Registers The assignment and selection of 17 2 2 LCD Port Control Registers Table 17 1 1 LCD Voltage Booster Circuit Specification deletion Boosts reference voltage input by 2 3 times 1 2 3 2 time Boosts reference voltage input by 2 3 times 17 3 2 Volt age Booster Circuit BSTVOL 1 Specification deletion LCD drive which generates a voltage of 2 3 3 2 1 2 times the LCD refer ence voltage LCD drive which generates a voltage of 2 or 3
252. Transmission data buffer writing Termination processing of IIC communication Set data to TXBUFn Figure 13 5 13 Master communication Setting Flow Diagram XIII 68 IIC Communication Setting Example of Slave Communication Chapter 13 Serial Interface Note 1 As initial setting register changed at the time of serial reset is shown below Please change it if needed such as interrupt setting or port setting Master setting at slave address transmission SCnMD0 Be sure to set it to 0 Be sure to set it to 0 Be sure to set it to 0 SCnMD1 Be sure to set it to 1 Be sure to set 1 Serial reset Be sure to set it to 1 SCnMD2 SCnRSTN 0 Be sure to set it to 1 Be sure to set it to 1 Be sure to set it to 0 Initial setting 1 SCnMD2 Be sure to set it to 0 Be sure to set it to 0 Be sure to set it to 0 End of serial reset SCnMD3 BS sure to set i 19 e sure to set it to 0 Be sure to set T Be sure to set it to 1 er nMD0 nMD nAD register NIE ES Slave reception start Receive the slave address R W bit from the master Slave reception end and so forth Received slave address is equal to SCnAD YES ACK transmission by hardware Communication completion interrupt NACK transmission by hardware Check of data transmission and reception Slave reception
253. V s Refer to the following pages for the setting procedure in clock synchronous mode Setting Page Initial setting before communication XIII 42 Data transmission reception 1 byte communication mode XIII 43 Data transmission 1 byte communication mode XIII 43 Data reception 1 byte communication mode XIII 44 Data transmission reception consecutive communication mode XIII 44 Data transmission consecutive communication mode XIII 45 Data reception consecutive communication mode XIII 45 Clock Synchronous Communication 41 Chapter 13 Serial Interface m Initial Setting Before Communication Setting Register name Description Disable interrupt SCnTICR SCnTIE 0 Disable the interrupt for SCIFn to be used Reset lt SCIFn n 0 1 gt SCnMD3 SCnRSTN 0 lt SCIFn n 2 3 gt SCnMD2 SCnRSTN 0 Reset SCIFn to be used Pin setting Disable serial output PnMD Set pins to general purpose ports BRTMn setting BRTM_S_MD BRTM S CKSEL BRTM 501 CK BRTM S23 CK BRTM Sn OC While BRTMn is active set BRTM S EN BRTM Sn EN to 0 to stop counting Output clock cycle and duty for BRTMn are set Mode register setting SCnMDO SCnMD1 SCnMD2 SCnMD3 Set SCIFn operation mode Pin setting Enable communication pins lt SCIFn n 0 1 gt SCnMD1 SCnSBOS SCnMD1 SCnSBIS SCnMD1 SCnSBTS SCnMD3 SCnSBCSEN SCIFn 2 3 SCnMD1
254. V with no load 54 103 boost clock 125 09 b ia Electrical Characteristics 1 27 Chapter 1 Overview 1 4 4 A D Converter Characteristics Vpp o 3 0 Vss Ta 40 C to 85 C D A D Converter characteristics 13 Limits Parameter Symbol Condition Unit MIN TYP MAX D1 Resolution RSL m 12 Bits D2 Nonlinearity error INL s 4 Differential non linearity LSB DS DNL 3 0 V Vas 0 V 3 04 Zero voltage transition Tap 750 ns 25 10 30 z mV D5 full scale voltage 2970 2990 transition D6 AD conversion time tev fsvscik 8 MHz Tap 750 ns 15 38 us D7 Sampling time ts Tap 750 ns 1 5 i D8 Reference voltage VREFP 1 8 EN Vppao lt V D9 Analog input voltage VAIN Vss z VREFP Analog input leakage At channel off u n n D10 current ANL 0 V to ps 13 Typ denotes the clock cycle for A D conversion The value from D2 to 05 are guaranteed under the condition of Vrerp 3 0 V and Vss 0 V 28 Electrical Characteristics 1 4 Reset Power supply Detection Characteristics Chapter 1 Overview E Reset Power supply Detection Vppao to 3 6 V Vss 0 V 1 1 V at auto reset function
255. VL 2 0 gt Interrupt IRQNMI Chapter 3 Interrupts Vector 1 External interrupt 0 NMICR A Undefined WDTOVF Instruction pe 1 Vector 2 i 7 6 5 4 3 2 1 0 IRQOICR LV1 0 IE IR 1 DEC Vector N Group 0 interrupt 1 DEC Vector 30 kes ae eee Group 1 interrupt Figure 3 1 1 Interrupt Block Diagram Overview 3 Chapter 3 Interrupts 3 1 2 Operation B Esa s W H ioG Interrupt Processing Sequence Figure 3 1 2 shows the flow of a interrupt processing When an interrupt occurs and is accepted the Program Counter Processor Status Word PSW and Handy Address HA are saved onto the stack by hardware and CPU jumps to the address specified by the corresponding interrupt vector At the end of interrupt handler execute the RTI instruction to go back to the main program which had been executed before the interrupt was accepted Start Interrupt handler Main program Hardware processing Save PC PSW HA Interrupt 7 occurs Transition Time 6 SYSCLK cycle
256. W_18_SCLK HALTO_18_HCLK HALT1_18_SCLK HALT1_11_SCLK SLOW_13_SCLK HALTO_13_HRC_SCLK HALTO 13 HRC HALT2 18 SCLK HALT2 13 SCLK HALT2 11 SCLK DEEP HALTS 13 SCLK HALT3 11 SCLK STOPO 18 STOPO 13 STOP1 18 STOP1 13 W 11 STOP1 11 IDLE 18 SCLK HCLK NORMAL 18 HCLK SCLK NORMAL 13 HRC SCLK SCLK HALTO 18 HCLK SCLK HALT1 13 SCLK HALTS 18 SCLK STOPO 11 DEEP NORMAL 13 HRC z SLO RESET ER NORMAL 18 HCLK SCLK NORMAL 18 HCLK NORMAL 13 HRC SCLK NORMAL 13 HRC SLOW 18 SC SLOW 13 SCLK SLOW 11 SCLK HALTO 18 HCLK SCLK HALTO 18 HCLK HALTO 13 SCLK HALTO 13 HRC HALT1 18 SCLK HALT1 13 SCLK HALT1 11 SCLK HALT2 18 SCLK Source mode HALT2 13 SCLK HALT2 11 SCLK DEEP HALT3 18 SCLK HALT3 13 SCLK HALT3 11 SCLK STOPO 18 _ STOPO_ STOP 1_ STOP 1_ STOP1_11 IDLE 18 SCLK HCLK IDEL 13 SCLK HRC M Operation mode change V VDD18 voltage change Oscillation stabilization wait process 51 Reset Power supply voltage activation 6 ms SRC oscillation stabilization 211 fsnc 2 2 SCLK oscillation stabilization DLYCTR DLY3 0 3 HCLK oscillation stabilization DLYCTR DLY3 0 4 Ensure
257. ach CPU Mode Clock Source for LODCLKS CPU Mode Clock Source for LCUPCKS HCLK based SCLK based NORMAL SLOW HALTO HALT1 HALT2 HALTS STOPO STOP1 Operation Mode Standby Mode LCD operation is enabled A Displaying data can be maintained LCD operation is disabled The supply voltage to VLC1 Vi c4 must be kept between and 3 6 V Y Vppao lt Vici lt 3 6 When LCDDRV is not used Supply to pin At this time VLC2 VLC3 C1 C2 pins are used as general purpose ports XVII 2 Overview Chapter 17 LCD iagram t Block Di Ifcul LCD Driver C 17 1 1 SSA 093 was 77 293 OWOOINWOO 77 EDTA 69 19 e Ajddns UOWWOD 191009 emod I4 li 119 gt 0 FOHAOT TSH 32010 19150084 xn XAW 7 lt 9 0 p cm 2 LdOW21 8
258. al communication is not exe cuted When the LSI is a slave inform a master device when the transfer clock output form the mas Y ter can be input in the LSI Clock Synchronous Communication 37 Chapter 13 Serial Interface Communication in CPU STANBY Mode In CPU STANBY mode a communication complete interrupt of slave reception can make CPU operation mode return from CPU STANBY mode to NORMAL mode Read reception data in RXBUFn after the return to NOR MAL mode Before CPU operation mode becomes NORMAL mode write data to TXBUFn as an activation source While in communication during STANBY mode be sure to set SCnCTM and SCnCKPH bits to 0 When the reception with STANDBY mode in SDIFO SCIF1 set SCnMDO SCnCTM and Y SCnMD3 SCnCKPH to 0 If they are not set to 0 SCIFn does not work properly When the reception with STANDBY mode SDIF2 SCIF3 set SCnMDO SCnCTM and Y SCnMD2 SCnCKPH to 0 If they are not set to 0 SCIFn does not work properly tion source with a data write to TXBUFn occurred So change CPU operation mode to a A transfer clock can be input after a time of 3 5 transfer clocks has elapsed since the activa STANDBY mode after that Normal mode Standby mode Normal mode gt a 3 51 RUM ROS M IU c Tuscos Waiting stable oscillation SBTn SBO SBI SCnRBSY Set data to TXBUFn Communication completion interrupt
259. aler Selection Register CKOMD 0x03F76 bp 3 0 Bit name TMOADDEN TMOBAS At reset Access Bit name Description Always read as 0 TMOADD1 0 Position of additional pulse within 4 cycles of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle TMOADDEN PWM output with additional pulses control 0 Disabled 8 bit PWM output 1 Enabled TMOPSC1 0 TMOBAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 32 110 HCLK 64 X01 SYSCLK 2 X11 SYSCLK 4 Timer 1 Prescaler Selection Register CK1MD 0x03F77 bp 0 Bit name TM1BAS At reset 0 Access Bit name Description Always read as 0 TM1PSC1 0 TM1BAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 64 110 HCLK 128 X01 SYSCLK 2 X11 SYSCLK 8 8 bit Timer Control Registers VIII 5 Chapter 8 8 bit Timer Timer 2 Prescaler Selection Register CK2MD 0x03F86 bp 5 4 3 0 Bit name TM2ADD1 0 TM2ADDEN TM2BAS At reset 0 0 0 0 Access Bit name Description Always read as 0 TM2ADD1 0 Position of additional pulse within 4 cycles of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle TM2ADDEN PWM output with addi
260. am of the Bus Controller Bus Interface 2 2 2 Access Cycle Table 2 2 1 shows the wait cycle and the access cycle of ROM bus RAM bus peripheral extension bus C BUS Table 2 2 1 Bus access cycle Type of bus ROM bus Access address 0x04000 to 0x040FF 0x04900 to 0x13FFF Wait cycle Access cycle 0x04100 to 0x048FF RAM bus 0x00000 to OxOOFFF Peripheral extension bus C BUS 0x03000 to OXOSBFF 0 03 00 to OxO3FFF Bus Interface Chapter 2 CPU Chapter 2 CPU 2 2 3 Control Registers The memory control register MEMCTR controls bus interface function Memory Control Register 0x03F01 bp 4 0 Bit name Reserved MIESET At reset Access Bit name Description Always read as 0 Base address specification for interrupt vector table IVBM 0 Interrupt vector base 0x04000 1 Interrupt vector base 0x00100 Reserved Must be set to 0 Always read as 0 Software write set up for interrupt request bit 0 Even if data is written to each interrupt control register xxxICR the state of the interrupt request bit xxxIR will not change 1 Software write enable Always read as 0 Setting to allow multiple interrupts bit MIESET 0 After accepted an interrupt MIE bit in PSW is set to 0 1 After accepted an interrupt MIE bit in PSW is set to 1 The interrupt request may be clear
261. ame SCnSTR SCnTEMP Chapter 13 Serial Interface m Data Transmission Consecutive Communication Mode Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn The first data transmission TXBUFn Set transmission data in TXBUFn Empty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR SCnTEMP becomes 0 since communi cation starts Data write to TXBUFn The second and subsequent data transmission TXBUFn Set the next transmission data in TXBUFn Consecutive communication or not When continuing data transmission repeat procedures from step 3 When completing data transmission go to step 6 Wait for communication comple tion lt SCIFn n 0 1 2 3 gt SCnSTR SCnTBSY lt SCIFn n 0 1 2 3 gt When the communication has been completed SCnTBSY becomes 0 When an interrupt is enabled a communication complete inter rupt SCnTIRQ occurs Transmission end Setting Empty confirmation of transmis sion buffer Register name SCnSTR SCnTEMP Repeat these procedures from step 1 to execute the next com munication Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn The first data transmission TXBUFn Set dummy data in TXBUFn Empty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR SCnTEMP becomes 0 since communi cation starts Data write to TXBUF
262. ame Description Reserved Must be set to 0 Always read as 0 The level of Viv 00000 1 10 V 00001 1 15 V 00010 1 20 V 00011 1 25 V 00100 1 30 V 00101 1 35 V 00110 1 40 V 00111 1 50 V 01000 1 60 V 01001 1 70 V 01010 1 80 V 01011 1 90 V 01100 2 00 V 01101 2 10 V 01110 2 20 V 01111 2 30 V 10000 2 40 V 10001 2 50 V 10010 2 60 V 10011 2 70 V 10100 2 80 V 10101 2 90 V 10110 11111 Prohibited a LV4 0 bits must be set when the LVICTR1 LVION is 0 VI 4 Control Register Chapter 6 Power Supply Voltage Detection m PSVD Control Register 1 LVICTR1 0x03F67 Bit name LVIOUT At reset 0 0 0 0 Access Bite name Description Always read as 0 Vppao monitor bit LVIOUT 0 lt 1 gt Vivi PSVD enable control 0 Disabled 1 Enabled The LVIOUT is not sticky bit and it could change after the LVIIRQ is generated 1 To set the PERITEN PERI1ENO more than 1 5 ms is required since the is set to 1 To read the LVICTR1 LVIOU more than 1 5 ms is required since the LVION is set to 1 Control Register VI 5 Chapter 6 Power Supply Voltage Detection m PSVD Control Register 2 LVICTR2 0x03F68 The LVICTR2 controls whether to add the noise filter on the output of PSVD and the sampling frequency of it Bit name LVINFEN At reset 0 0 Access
263. and 100 us depending on the resonator to be used 4 Setthe sample hold time Set the sample hold time by the ANCTRO ANSH1 0 Select the appropriate value based on the analog impedance The steps of 2 to 4 can be performed in random order The steps of 3 and 4 can be operated simultaneously 5 Set the A D resistor ladder Set the ANCTRO ANLADE to 1 to apply current to the resistor ladder so that ADC will be in standby condi tion 6 Select the ADC activation factor then start A D conversion Set the ANCTR2 ANST to 1 to enable the ADC or set the ANCTR2 ANSTSEL1 0 to 01 or 10 to enable the ADC by external trigger factor 7 A D conversion A D conversion is compared and determined sequentially by MSB after the sampling in the sample hold time which is set in the step 4 8 Complete A D conversion After A D conversion is completed the result of the conversion is stored in ANBUFO and ANBUFI A D con version interrupt is generated and the ANCTR2 ANST is cleared to 0 XVI 8 Operation Chapter 16 A D Converter ADC Set ANCTR0 ANLADE to 1 then start A D conversion after waiting for 12 conversion clocks When ADC is started again after setting ANCTR2 ANST to 0 and ADC was stopped by force during A D conversion start ADC after waiting for an equivalent time of 2 system clock 2 converter clock or longer When the A D conversion is converted that select the start by Exter
264. apacitor value Connect the external capacitance to match the oscillator used When using the crystal or ceramic oscillator consult your oscillator manufacturer to decide the external capacitance value since the oscillation frequency changes depending on the The external low speed oscillation of other than 32 768 kHz can t be used 1 22 Electrical Characteristics Chapter 1 Overview Vpp3o 1 8 V to 3 6 V Vss 0 V Vast 1 1 V at auto reset function Ta 40 C to 85 G Limits P bol Conditi Unit arameter Symbo ondition External clock input 1 OSC1 OSC2 is open MN101LR02D is not applicable B18 Clock frequency 1 0 10 0 MHz B19 High period time 11 t 45 ll Figure 1 4 3 B20 Low period time 11 twit 45 ns B21 Rise time twrt 5 0 Figure 1 4 3 B22 Fall time tut 5 0 11 Set the clock duty ratio to the value from 45 to 55 0 9VDD30 0 1VDD30 lt twh1 gt lt twit gt gt lt twri gt lt twf1 lt twc1 gt Figure 1 4 3 OSC1 timing diagram Electrical Characteristics 1 23 Chapter 1 Overview 1 4 3 DC Characteristics 0 C DC Ch teristi ss aracteristics Ta 40 C to 85 C Parameter Symbol Condition mits Unit MIN TYP MAX Supply current 12 10 MHz C1
265. ascade connection 3 TM3EN Timer 3 count enable 0 Disabled 1 Enabled Always read as 0 1 0 TM3CK1 0 VIII 12 8 bit Timer Control Registers Clock source select 00 HCLK 01 TM3PSC prescaler output 10 SCLK 11 input W Timer 4 Mode Register TM4MD 0x03F94 bp 6 5 4 Chapter 8 8 bit Timer Bit name TM4POP TM4MOD TM4PWM At reset 0 0 0 Access Bit name Always read as 0 Description TM4POP Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High TM4MOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P14 P72 P12 TM4PWM Timer 4 operation mode select 0 Normal timer operation 1 PWM operation TM4EN Timer 4 count enable 0 Disabled 1 Enabled Always read as 0 1 0 TM4CK1 0 Clock source select 00 HCLK 01 TM4PSC prescaler output 10 SCLK 11 TM4IO input 8 bit Timer Control Registers VIII 13 Chapter 8 8 bit Timer W Timer 5 Mode Register TM5MD 0x03F95 bp 4 Bit name TM5CAS At reset 0 Access Bit name 7 5 Description Always read as 0 4 TM5CAS Timer 5 operation mode select 0 Normal timer operation 1 Cascade connection 3 TMSEN Timer 5 count enable 0 Disabled 1 Enabled
266. ble interrupt Register name SCnTICR SCnTIE 0 SCnRICR SCnRIE 0 XIII 55 Description Disable the interrupt for SCIFn to be used Serial reset SCnMD3 SCnRSTN 0 SCnMD3 SCnRSRN 0 Execute serial reset Pin setting 1 Disable communication pins Set pins to general purpose ports to disable communication pins Refer to the chapter IO Port for setting general purpose ports BRTMn setting BRTM S MD BRTM S CKSEL BRTM S01 CK BRTM S23 CK BRTM Sn OC While BRTMn is active set BRTM S EN BRTM Sn EN to 0 to stop counting Output clock cycle and duty for BRTMn are set Mode register setting SCnMDO SCnMD1 SCnMD2 SCnMD3 Set SCIFn operation mode Pin setting 2 SCnMD1 SCnSBOS SCnMD1 SCnSBIS Set pins used for serial communication to 1 Pin setting 3 Enable communication pins Enable communication pins Clear interrupt source SCnTICR SCnTIR SCnRICR SCnRIR Clear the interrupt source Enable interrupt SCnTICR SCnTIE SCnTICR SCnTIE Enable the interrupt to be used BRTMm counting start BRTM_S_EN BRTM_Sn_ EN 1 BRTM starts counting Release serial reset 54 Full duplex UART Communication SCnMD3 SCnRSTN 1 SCnMD3 SCnRSRN 1 Release the serial reset After that serial communication is enabled W Data Transmission Setting Empty confirmation of transmis sion buffer Register name SCnSTR SCnTEMP Chapt
267. bp Bit name Description Interrupt level bit Set interrupt level from 0 to 3 Always read as 0 Reserved Must be set to 0 Always read as 0 III 24 Control Registers Chapter 3 Interrupts Group 0 Interrupt Enable Register PERIOEN bp Bit name At reset Access Bit name Description Always read as 0 RTC Alarm1 interrupt enable control 0 Disable 1 Enable RTC Alarm0O interrupt enable control 0 Disable 1 Enable RTC interrupt enable control 0 Disable 1 Enable RTC TBT interrupt enable control 0 Disable 1 Enable TBT interrupt enable control 0 Disable 1 Enable Timer6 interrupt enable control 0 Disable 1 Enable 5 interrupt enable control 0 Disable 1 Enable Control Registers III 25 Chapter 3 Interrupts Group 0 Interrupt Factor Register PERIODT bp Bit name At reset Access Bit name Description Always read as 0 RTC Alarm1 interrupt request detection 0 Not detected 1 Detected RTC AlarmoO interrupt request detection 0 Not detected 1 Detected RTC interrupt request detection 0 Not detected 1 Detected RTC TBT interrupt request detection 0 Not detected 1 Detected TBT interrupt request detection 0 Not detected 1 Detected Timer6 interrupt request detection 0 Not detected 1 Dete
268. clock supplied to CPU is halted The clock supplied to peripheral function is not halted Stop the clock for each function Voltage Control Chapter 4 Clock Mode Voltage Control 4 3 4 Operation O u W Voltage Transition of VDD18 by Program Figure 4 3 1 shows the example of voltage transition of VDD18 by program When SLOW mode the PVCTRO VDDLV 1 0 are set to change the output voltage VDD18 and achieve low power consumption or high speed operation depending on the operating frequency Voltage transition cannot be set in NORMAL mode It is also impossible to change the voltage from 1 3 V to 1 8 V and from 1 8 V to 1 3 V After updating the PWCTR0 VDDLV1 0 CPU clock is halted for the time set in the PWCTR1 PWUPTM2 0 while the voltage is boosted during i and iii shown in the Figure 4 3 1 Although CPU clock is not halted while the voltage is stepped down during ii and iv shown in the Figure 4 3 1 it does not affect the operation 18V 13V F 4 1 4 V F i A VDD18 output voltage Power i VDDLV1 0 00 00 00 VDD18 output 14V v 14V gt 2 Operating mode SLOW NORMAL SLOW NORMAL SLOW MAX operating speed 40 kHz 1MHz 40kHz 10MHz 40kHz Figure 4 3 1 Voltage Transition of VDD18 by Program The setting example to change VDD18 from 1 1 V to 1 8 V at iii in Figure 4 3 1 is shown below
269. commended Circuit m Sample Hold Time Description addition m Sample Hold Time Figure 16 3 5 Circuit Example m External Capacitor lt Record of Changes 1 gt Description addition External Capacitor Figure 16 3 6 Circuit Example with External Capacitor Details of revision from Ver 1 3 to Ver 1 4 in MN101LR05D 04D 03D 02D LSI User s Manual is shown below According to the details of revision Definition of the table below is classified into seven groups Revision concerning descriptions in LSI User s Manual Writing error correction Description change Description addition Description deletion Revision concerning LSI specifications Specification change Specification addition Specification deletion Modification Ver 1 4 Page Title C DC Char acteristics Definition Specification addition Details of Revision Supply current in HALT Ippio MIN TYP 0 2 uA MAX 0 4 uA Description change C10 15510 to C13 15013 C11 15011 to 14 15914 Figure 4 1 2 Writing error correction Set the Clock mode Control Register CLKMD bit6 4 100 Set the Clock mode Control Register CLKMD bit6 4 010 W Setting Example of Writing error correction CPU outage in voltage transition 16 fscLK 32 768 kHz 488 us CPU outage in voltage transition 32 fscuk 32 768 kHz 977 us Table 7 11 5 Writing error
270. control register selects the pin function General IO GIO or Buzzer output and selects the output pin of BUZ NBUZ BUZA BUZB NBUZA or NBUZB m Buzzer output Buzzer output pin control Register BUZCNT 0x03F5F DESC a r 20 Bit name NBUZEN BUZEN NBUZSEL BUZSEL At reset 0 0 0 0 0 0 0 0 mm n n n n nw mw mw Bit name Description Always read as 0 NBUZEN Select the pin function GIO or NBUZ output 0 GIO 1 NBUZ output NBUZA NBUZB NBUZSEL Select the pin function GIO or BUZ output 0 GIO 1 BUZ output BUZA BUZB Select the output pin of NBUZ output function 0 NBUZA P34 1 NBUZB P03 BUZSEL Control Registers Select the output pin of BUZ output function 0 BUZA P33 1 BUZB P02 Chapter 7 I O Port 7 3 Port Functions Each I O can be used as a general purpose port which is controlled with PnOUT PnIN PnDIR PnPLU PnODC and PnNLC registers Each port also has a special function the detail of which is described after 7 4 Port 0 For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Reg isters MN101LR05D is described in this section 1 The assignment and selection of LCD control pins SEGn and differ in each product I O Port Functions VII 33 Chapter 7 Port 7 4 Porto The following table shows the special functions of
271. cted Ill 26 Control Registers Timer5 interrupt request detection 0 Not detected 1 Detected Group 1 Interrupt Enable Register PERI1EN bp Chapter 3 Interrupts Bit name At reset Access Bit name Description Always read as 0 DMA Error interrupt enable control 0 Disable 1 Enable DMA AddReq interrupt enable control 0 Disable 1 Enable DMA interrupt enable control 0 Disable 1 Enable A D interrupt enable control 0 Disable 1 Enable LVD interrupt enable control 0 Disable 1 Enable Control Registers III 27 Chapter 3 Interrupts Group 1 Interrupt Factor Register PERI1DT bp Bit name At reset Access Bit name Description Always read as 0 DMA Error interrupt request detection 0 Not detected 1 Detected DMA AddRegq interrupt request detection 0 Not detected 1 Detected DMA interrupt request detection 0 Not detected 1 Detected A D interrupt request detection 0 Not detected 1 Detected 28 Control Registers LVD interrupt request detection 0 Not detected 1 Detected 3 2 4 Other Interrupt Control Register Chapter 3 Interrupts W Other Interrupt Control Register TMnICR 0 1 2 3 4 7 8 9 TMnOC2ICR n 7 8 9 SCnRICR n 0 1 SCnSICR 2 3 SCnTICR n 0 1 2 3 Register sp
272. d TBNZ abs16 bp d7 TBNZ abs16 bp d11 12 Instruction Chapter 20 Appendix Instruction map 13 Record of Changes Details of revision from Ver 1 4 to Ver 1 5 in MN101LR05D 04D 03D 02D LSI User s Manual is shown below According to the details of revision Definition of the table below is classified into seven groups Revision concerning descriptions in LSI User s Manual Writing error correction Description change Description addition Description deletion Revision concerning LSI specifications Specification change Specification addition Specification deletion Modification Ver 1 5 Page Title m mended Line Definition Description addition Details of Revision Unconnect the pins Note 2 Description change When recovering from SLOW HALT2 STOPO Set the stabilization wait cycle of inter nal oscillation to match W Multiple maskable Description change When MEMCTR MIESET is 1 and an interrupt is processed When MEMCTR MIESET is 0 and an interrupt is accepted Figure 3 1 9 4 2 Description change mov PERInDT Dn mov Dn PERInDT Save the value of PERInDT in Dn mov PERInDT Dn mov Dn PERInDT Load the value of PERInDT to Dn Description addition Description addition mov PERInEN Dm and Dm Dn Extract the request bit that Figure 4 2 1 shows the transiti
273. d Figure 18 2 1 Memory Map in Self programming Rewriting Method When Self Programming can not be performed because of program troubles which may Y happen in an early phase of development program the data of ReRAM with Programmer writing method XVIII 4 Self programming Rewriting Method 18 2 1 Procedures for Rewriting Chapter 18 ReRAM Figure 18 2 2 shows the ReRAM programming flow Start Rewriting 1 Set the FBEWER to 0x4B 2 Set the necessary parameters in the control registers 1 Call 3 Subroutine call Software Library 2 Return 4 Set the FBEWER to any value other than 0x4B End Rewriting 1 Rerer to Table 18 3 1 Library Start ReRAM Programming Library End 2 The reteruned value of the command library is stored in D0 Figure 18 2 2 ReRAM programming flow If not NMI as execution of the undefined instruction is generated To access a command library FBEWER needs to be set to 0x4B 1 When programming the voltage of VDD18 must be set to 1 8 V with the PWCTR0 18 2 2 Interrupts during Programming When an interrupt occurs during the execution of a command library the processing of the command library is suspended and the interrupt process is executed After the Interrupt process is finished the command library is resumed Self programm
274. dic interrupt and the alarm interrupt The periodic interrupt occurs according to the condition set in the RTCCIRQ There are two alarm interrupts Alarm 0 and Alarm 1 lt Alarm 0 interrupt Alarm 0 interrupt occurs when the condition which is defined with the ALOIRQMI the ALOIRQH and the ALOIRQW matches the calendar counter When the RTCALOIRQ ALOIRQSET is 0 Alarm 0 interrupt does not occur When the RTCALOIRQ ALOIRQWEN is 0 ALOIRQW is not compared with the calendar calculator When the RTCALOIRQ ALOIRQHEN is 0 ALOIRQH is not compared with the calendar calculator When the RTCALOIRQ ALOIROMIEN is 0 ALOIROMI is not compared with the calendar calculator Alarm 1 interrupt Alarm 1 interrupt occurs when the condition which is defined with the the ALIIROH the ALIIRQD and ALIIRQMO matches the calendar counter When the RTCALIIRQ AL IIRQSET is 0 Alarm 1 interrupt does not occur When the RTCALIIRQ ALIIROMIEN is 0 ALIIROMI is not compared with the calendar calculator When the RTCALIIRQ ALIIRQHEN is 0 ALIIRQH is not compared with the calendar calculator When the RTCALIIRQ ALIIRQDEN is 0 ALIIRQD is not compared with the calendar calculator When the RTCALIIRQ ALIIRQMOEN is 0 ALIIRQMO is not compared with the calendar calculator RTC Operation XII 15 Chapter 12 Real Time Clock RTC 12 3 1 Data Reading Procedure u O s sss After
275. directly to the power supply and ground respectively Do not mount the LSI on the printed circuit board in the wrong direction in order not to destroy it because of the meltdown of wiring due to large current etc Cautions for Operation 1 If the LST is used close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Operation temperature should be well considered If the temperature is over the guaranteed value unexpected operation could be occurred 3 Operation voltage should be also well considered Ifthe operation voltage is over the operating range reliability lifetime due to the aged deterioration can not be guaranteed If the operating voltage is below the operating range unexpected operation could be occurred Cautions for Circuit Setup 1 35 Chapter 1 Overview 1 6 2 Unused Pins ur s Unused Pin only for output Unconnect the unused output pin Output Figure 1 6 1 Unused Pin only for output Unused Pin only for input Pull up or down the unused input pins with the resistor the value of which is typically between 10 and 100 kO When the input voltage level is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and becomes noise sources to the internal power supply Input pin Pull up Input resistor Input 4 Pull do
276. drain Control Register P2ODC 0x03F52 Bit name 200 5 3 At reset 0 0 Access bp Bit name Description 7 6 Always read as 0 N ch open drain output selection 5 3 P2ODC5 3 0 Push pull output 1 N ch open drain output 2 0 Always read as 0 Port 3 N ch Open drain Control Register 0x03F53 Bit name P3ODC2 0 At reset 0 Access Description N ch open drain output selection 7 6 P3ODC7 6 0 Push pull output 1 N ch open drain output 5 3 Always read as 0 N ch open drain output selection 2 0 P3ODC2 0 0 Push pull output 1 N ch open drain output Control Registers VII 19 Chapter 7 Port Port 4 Open drain Control Register P4ODC 0x03F54 Bit name P4ODC4 2 P4ODC0 At reset 0 0 0 Access Description N ch open drain output selection P40DC7 6 0 Push pull output 1 N ch open drain output Always read as 0 N ch open drain output selection P4ODC4 2 0 Push pull output 1 N ch open drain output Always read as 0 N ch open drain output selection P4ODC0 0 Push pull output 1 N ch open drain output Port 5 N ch Open drain Control Register 0x03F55 Bit name P5ODC4 2 P5ODC0 At reset 0 0 0 0 Access 7 5 Always read as 0 N ch open drain output selection P5O
277. e At reset Access e mmm E I O mode selection 7 0 P3DIR7 0 0 Intput mode 1 Output mode m Port 4 Direction Control Register P4DIR 0x03F34 Bit name P4DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W I O mode selection 0 Intput mode 1 Output mode Bit name P5DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W m sme I O mode selection P5DIR7 0 0 Intput mode 1 Output mode Control Registers VII 13 Chapter 7 Port Port 6 Direction Control Register P6DIR 0x03F36 Bit name At reset Access me mam e I O mode selection 7 0 P6DIR7 0 0 Intput mode 1 Output mode m Port 7 Direction Control Register P7DIR 0x03F37 Bit name P7DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W I O mode selection 0 Intput mode 1 Output mode Bit name P8DIR5 0 At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W m sme em Always read as 0 mode selection P8DIR5 0 0 Intput mode 1 Output mode VII 14 Control Registers Chapter 7 I O Port 7 2 4 Port n Pull up Resistor Control Registers PnPLU is the register to control the pull up resistor addition to I O Port 0 Pull up Resisto
278. e 13 4 4 Reception Data Storage MSB first RXBUFn G F E D C B A Figure 13 4 5 Reception Data Storage LSB first Full duplex UART Communication XIII 51 Chapter 13 Serial Interface 13 4 3 Timing W Transmission Twait 2 5T T Poo bo 1o do Po J Parity Stop Stop SCnTBSY x Set data toTXBUFn Transmission completion interrupt Figure 13 4 6 Transmission Timing with Parity Bit TXD pin SCnTBSY x Set data to TXBUFn Transmission completion interrupt Figure 13 4 7 Transmission Timing without Parity Bit XIII 52 Full duplex UART Communication Chapter 13 Serial Interface m Reception Parity Stop Stop RXDn bit bit SCnRBSY A Start condition input Reception completion interrupt Figure 13 4 8 Reception Timing with Parity Bit Stop Stop bit bit RXDn SCnRBSY A Start condition input Reception completion interrupt Figure 13 4 9 Reception Timing without Parity Bit Full duplex UART Communication XIII 53 Chapter 13 Serial Interface 13 4 4 Setting procedure The setting procedure of full duplex UART is shown as follows Setting Page Initial Setting Before Communication Data Transmission XIII 54 XIII 55 Data Reception XIII 55 UART Break Transmission m Initial Setting Before Communication Setting Disa
279. e register setting the counts till the interrupt request generation 1 If the TM6CLRS bit of the TM6MD register is set to 0 TM6BC can be initialized every time the value of TM6CC register is rewritten However in that state the timer 6 interrupt is dis abled If you use the timer 6 interrupt set the TM6CLRS bit to 1 after rewriting the value of the TM6OC register On the timer 6 clock source selection if the time base timer output is selected the clock setup of the time base timer is necessary X 10 8 bit Free running Timer 10 3 2 Setup Example W Timer Operation Setup Timer 6 The timer 6 generates interrupts regularly for the clock function Interrupts are generated every 250 dividing 62 5 Chapter 10 General Purpose Time Base Free Running Timer us when selecting SYSCLK at fsyscrk 4 MHz a clock source The setup procedure and the description of each step are shown below Setup Procedure Description 1 Enable the binary counter initialization TM6MD 0x03F7A bp7 TM6CLRS 0 2 Disable the interrupt PERIOEN 0x03FDC PERIOEN1 0 3 Select the clock source TM6MD 0x03F7A bp3 1 6 1 001 4 Set the interrupt generation cycle TM6OC 0x03F79 0xF9 5 Enable the interrupt request generation TM6MD 0x03F7A bp7 IM6CLRS 1 6 Set the interrupt level PERI0ICR 0x03FFD bp7 6 PERIOLV1 0 01 7 Enable the interrupt PERIOEN 0x03FDC
280. e value to TMnOC during counting is prohibited The sampled signal of the TMnMD TMnEN with the count clock controls start stop of the binary counter of 8 bit timer this LSI Therefore note the following two points To read the binary counter value after the timer has stopped set the TMnMD TMnEN to 0 wait for 1 count cycle and read the value When reading the value without waiting for 1 count cycle use the program to read the value of the binary counter multiple times In this case the read value is count value 1 Il When changing the timer setting clock selection function switching etc wait for 1 count clock after setting the TMnMD TMnEN to 0 to stop the timer Then Restart the timer If the setting is switched during the timer operation the timer operation is not guaranteed 8 bit Event Count 21 Chapter 8 8 bit Timer 8 4 2 8 bit Event Count Setup Example W Event Count Setup Example Here is an example that an interrupt is generated by detecting the falling edge of the TMOIO input 5 times The setup procedure and the description of each step are shown below Setting Disable the timer counter Register TMOMD TMOEN 0 Description Disable the timer count operation Disable the interrupt TMOICR TMOIE 0 Disable the timer interrupt Select the event input TMIOSELO TMOIOSELO 0 PODIR PODIRS 0 Select the event clock input pin Chapter 7 I O Port
281. ead as 0 4 TM1CAS Timer 1 operation mode select 0 Normal timer operation 1 Cascade connection 3 TM1EN Timer 1 count enable 0 Disabled 1 Enabled Always read as 0 1 0 TM1CK1 0 VIII 10 8 bit Timer Control Registers Clock source select 00 HCLK 01 TM1PSC prescaler output 10 SCLK 11 TM1IO input W Timer 2 Mode Register TM2MD 0x03F84 bp 6 5 4 Chapter 8 8 bit Timer Bit name TM2POP TM2MOD TM2PWM At reset 0 0 0 Access Bit name Always read as 0 Description TM2POP Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High TM2MOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P80 P62 TM2PWM Timer 2 operation mode control 0 Normal timer operation 1 PWM operation TM2EN Timer 2 count enable 0 Disabled 1 Enabled Always read as 0 1 0 TM2CK1 0 Clock source select 00 HCLK 01 TM2PSC prescaler output 10 SCLK 11 TM2IO input 8 bit Timer Control Registers VIII 11 Chapter 8 8 bit Timer W Timer 3 Mode Register TM3MD 0x03F85 bp 4 Bit name TM3CAS At reset 0 Access Bit name 7 5 Description Always read as 0 4 TM3CAS Timer 3 operation mode select 0 Normal timer operation 1 C
282. ead out Reserved This bit must be set to 2 0 TMOCK2 0 Clock source selection 000 IOCLK 001 IOCLK 8 010 IOCLK 32 011 Setting prohibited 100 Setting prohibited 101 Timer underflow 110 Timer2 underflow 111 lOCLK 128 The bit position of each register is shown Bit name The bit symbol is shown There are following two kinds of statements in addition to the bit symbol Reserved This is the reserved bit This bit is not mounted Initial value It may be different on an actual table The value of the bit immediately after reset release is shown with binary number When the value immediately after reset release is unfixed value this item is indicated as X Access This bit is readable W This bit is writable Description The outline of the bit function and setting values are shown Access the bit according to the description in this item About This Manual 2 mFinding Desired Information This manual provides three methods for finding the desired information quickly and easily 1 Refer to the index at the front of the manual to locate the beginning of each section 2 Refer to the table of contents at the front of the manual to locate the desired titles 3 The chapter number and chapter title are located at the top corner of each page and the section titles are located at the bottom corner of each page mRelated Manuals Note that the
283. ead value to PERI1DT Refer to 3 1 4 Group Interrupt Control Register Setup 6 Set the interrupt level 6 Set the interrupt level by the PERI1LV1 to 0 bits of PERI1ICR Ox03FFE PERI1ICR If the interrupt mask level of PSW needs to bp7 to 6 PERITLV1 to 0 change set the IM1 to IMO bits of PSW PSW bp5 to 4 IM1 to IMO 7 Enable interrupt 7 Set the PERI1ENO bit of PERI1EN to enable interrupt PERI1EN Ox03FDE bpO PERITENO 1 8 Enable all maskable interrupts 8 Set the MIE bit of PSW to enable maskable interrupts PSW bp6 MIE 1 9 Check power supply voltage 9 Monitor the LVIOUT bit of LVICTR1 periodically LVICTR1 0x03F76 bp1 LVIOUT 0 Setting Example VI 7 Chapter 6 Power Supply Voltage Detection VI 8 Setup Procedure Description 10 When the LVIOUT bit is operating 10 When the monitored LVIOUT bit is 0 the operating mode transits to STOP mode mode transits to STOP mode CPUM 0x03F00 bp3 STOP 1 11 Return from STOP mode by interrupt 11 When the power supply voltage exceeds 2 0 V an interrupt is generated to return from STOP mode In that case after returning from the interrupt CPU enters STOP mode although is higher than V yj It prevents returning from STOP mode at rising of the power supply voltage To avoid such operation refer to the addresses saved to stack in interrupt processing If it is considered that the operation as abo
284. eared W Timer n Preset Register 1 Lower 8 bits TM7PR1L 0x03FA4 TM8PR1L 0x03FB4 TM9PR1L OxOSFCA Bit name At reset Access W Timer n Preset Register 1 Upper 8 bits TM7PR1H 0x03FA5 TM8PR1H 0x03FB5 TM9PR1H 0x03FC5 Bit name At reset Access W Timer n Preset Register 2 Lower 8 bits TM7PR2L 0x03FAC TM8PR2L 0x03FBC TM9PR2L OxOSFCC Bit name At reset Access W Timer n Preset Register 2 Upper 8 bits TM7PR2H 0x03FAD TM8PR2H 0x03FBD TM9PR2H OxOSFCD Bit name TMnPR2H7 0 At reset X X Access a Timer 7 preset register 1 and 2 must not be changed during IGBT operation 16 bit Timer Control Registers IX 7 Chapter 9 16 bit Timer 8 Binary counters 16 bit up counters If data is written to the preset register 1 TMnPR1L to TMnPR1H while the counting is stopped the binary counter is cleared to 0x0000 For Timer 7 the binary counters are cleared to 0x0000 while IGBT operation is disabled at IGBT setting The binary counters for Timer 7 and 8 can be cleared to 0x0000 at a capture operation while counting by setting the register Timer n Binary Counter Lower 8 bits TM7BCL 0x03FA0 TM8BCL OxO3FBO TM9BCL OxOSFCO Bit name At reset Access Timer n Binary Counter Upper 8 bi
285. ecification of above other interrupt control registers is described below bp 3 Bit name Reserved At reset Access Bit name Interrupt level Set interrupt level from 0 to 3 Description Always read as 0 Reserved Must be set to 0 Always read as 0 Interrupt enable control 0 Disable 1 Enable Interrupt request detection 0 Not detected 1 Detected Control Registers III 29 Chapter 3 Interrupts 3 2 5 Block diagram of Peripheral function group interrupt m Block diagram of Group 0 Group 1 interrupt interface Timer 5 interrupt gt detection PE RIODT DTO Timer 6 interrupt I edge detection RIODT DT1 interrupt m edge detection RIODT DT2 RTC TBT interrupt m edge detection RIODT DT3 RTC interrupt edge detection PE RIODT DT4 RTC Alarm0 interrupt I i edge detection PE RIODT DT5 RTC Alarm1 interrupt me edge detection When the interrupt factor and set clear by software ocurred at the same time set clear by software is given priority PE RIODT DT6 PERIOEN URVETEVETEVEV ENO EN1 EN2 ENS EN4 EN5
286. ect SEGO 7 and 1 pins LCCTRO 0x03E86 bp7 4 SEGSL3 0 1111 bp1 0 COMSL1 0 11 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 5 Set the display data 5 Set the display data 23 on the segment output latch LCDATAO 0x03E90 0x01 LCDATA1 0x03E91 0x03 LCDATA2 0x03E92 0x02 LCDATAS3 0x03E93 0x02 LCDATA4 0x03E94 0x00 LCDATAS 0x03E95 0x03 LCDATA6 0x03E96 0x02 LCDATA7 0x03E97 0x03 6 Activate the LCD 6 Start the LCD operation LCDMD2 0x03E82 bp7 LCEN 1 LCD Display Examples XVII 31 Chapter 17 LCD 17 4 5 LCD Display Example 1 3 duty 1 3 duty Segment Latch Ox03EBA vee Ox03E94 0x03E93 0 03 92 0 03 91 0 03 90 open A electrode B electrode oN OFF LCDPANEL LCD ON S COM N S COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock Undefined Data qs 0 Undefined COM Vici Vica Vss SEG Vic Vice 7 Vics Vss Vico COM SEG 1 3VLco 0 1 3Vico be sree ON OFF OFF OFF OFF S selected voltage N non selected voltage Vico LCD driving voltage XVII 32 LCD Display Examples COM2 COM1 COM0 A electrode COM2 SEG5 B electrode C
287. ection 0 IRQ2A P80 1 IRQ2B P62 IRQ1SEL IRQ1 pin selection 0 IRQ1A P11 1 IRQ1B P61 III 36 IRQOSEL External Interrupts IRQO pin selection 0 IRQOA P10 1 IRQOB P60 W External Interrupt Input pin Selection Register 1 IRQISEL1 bp Chapter 3 Interrupts Bit name At reset Access Bit name Always read as 0 Description IRQ5CSEL IRQ5 pin selection 0 IRQ5A IRQ5B P15 P71 1 IRQ5C 13 IRQ4CSEL IRQ4 pin selection 0 IRQ4A IRQ4B P14 P72 1 IRQ4C P12 Always read as 0 External Interrupts Ill 37 Chapter 3 Interrupts m Both Edges Interrupt Control Register EDGDT bp 6 5 4 3 2 1 0 Bit name EDGSEL6 EDGSEL5 EDGSEL4 EDGSEL3 EDGSEL2 EDGSEL1 EDGSELO At reset 0 0 0 0 0 0 0 0 Access Bit name Description Always read as 0 IRQ6 trigger selection EDGSEL6 0 Rising edge or falling edge 1 Both edges Rising and falling edges IRQ5 trigger selection EDGSEL5 0 Rising edge or falling edge 1 Both edges Rising and falling edges IRQ4 trigger selection EDGSEL4 0 Rising edge or falling edge 1 Both edges Rising and falling edges IRQ3 trigger selection EDGSEL3 0 Rising edge or falling edge 1 Both edges Rising and falling edges IRQ2 trigger selection EDGSEL2 0 Rising edge or falling edge 1 Both edges Rising and
288. ed when operating the xICR by software while the MEM CTR IRWE is 1 For example when the bit operation to xICR is executed the xICR is read modified and overwritten by CPU the interrupt request which occurs during the above read to write cycle is cleared because the IR is overwritten with 0 by software To avoid this set the MEMCTR IRWE to 0 which prevent the interrupt missing by software a Always set the MEMCTR IRWE to 0 except in writing xICR IR by software set to 0 If MEMCTR MIESET is set to 1 when PSW MIE is 1 the operation can not be a Setting the MEMCTR MIESET to 1 disables all maskable interrupts after the PSW MIE is guaranteed Il 16 Bus Interface 2 3 Extended Calculation Function 2 3 1 Overview The LSI contains the following calculator functions Calculation 16 bit x 16 bit multiplication unsigned Table 2 3 1 List of Extended Calculation Functions Instruction 1 Ox3F07 Extended calculation macro instruction MULWU Operation DWO DW1 gt DW1 DW0 Execution cycle 16 bit x 16 bit multiplication signed MOV 2 0x3F07 Extended calculation macro instruction MULW DWO DW1 DW1 DW0 32 bit 16 bit division unsigned 4 0x3F07 Extended calculation macro instruction DIVWU DW1 AO gt DW1 BCD addition without carry MOV 16 0x3F07 Extended calculation macro instruction
289. efore interrupt acceptance Figure 3 1 5 Stack Operation during Interrupt Acceptance Overview Chapter 3 Interrupts Ill 9 Chapter 3 Interrupts 1 10 m Interrupt Return Operation RTI instruction RTI instruction makes the LSI go back to the program which had been executed before the interrupt occurred Before RTI execution if the data of D0 D1 D2 D3 and AO A1 registers was saved in the interrupt handler with PUSH instruction they are needed to be backed to each registers with POP instruction The following is the processing sequence invoked by RTI instruction 1 PSW are restored from the stack SP 2 PC i e the return address are restored from the stack SP 1 to SP 3 3 HA are restored from the stack SP 4 SP 5 4 SP is updated SP 6 SP 5 Jump to the program address of PC Registers such as data registers DO D1 D2 D3 or address registers 0 1 are not saved Y by hardware so save them onto the stack with PUSH instruction if necessary The reserved bits bp6 to bp4 in the address where the PC bit19 to bit16 bitH are saved to Y the stack are reserved Do not change them by software Overview Chapter 3 Interrupts Maskable Interrupt Processing The following figure shows the processing sequence when the lower priority level interrupt occurs while process ing the higher priority level interrupt Interrupt 1 LV 1 0 00 Interrupt 2 LV1 0 10
290. el as the oscillation clock is under 4 clocks take notice of noise any loss of functionality or damage to the chip a When the power voltage low circuit is connected to NTST pin circuit t Please be sure to read footer Page and section title 11 48 Reset This page serves as an example to the explanations above It may be different on an actual page About This Manual 1 gt mAbout Register Table How to read the register table in each chapter is shown below 15 8 bit Timer Register specification Each item is explained below This register table serves as an example to the explanations above Register name lode Registers Register symbol Register address Access size Values of the timer mode register gontorl the ogeration initialization clock source selectjon of each timer For setting clock sourges refer to 15 3 Clofk Source Selection I Timer 0 Mode Register TMOMD 0x0A200 8 bit Access Register bp 7 6 5 4 3 2 1 Bit name TMOCNE TMOLDE Reserved TMOCK2 0 Initial value 0 0 0 0 0 0 0 Access RW RW R R RW RW RW bp Bit name Description 0 Deactivated 1 Activated Timer 0 operation control TMOLDE 0 Initialization release 1 Initialization Binary counter initialization 0 is always r
291. ens during the time after the DMA start trigger occurs and before DMA reads the last data from Source Address for example the period A in the Figure 14 3 2 DMA Error interrupt occurs mem X KK DMCNTL DMA y i i Memory Access interrupt start trigger Period A i Period B lt gt gt DMTEN of DMCTR1L Set the DMTEN to 1 by software for next DMA When interrupt occurs the DMTEN is cleard to 0 by hardware Figure 14 3 2 Example of Burst Transfer DMA Data Transfer XIV 13 Chapter 14 DMA Controller 14 Data Transfer Chapter 15 Buzzer Chapter 15 Buzzer 15 1 Overview Buzzer circuit outputs the square wave generated by dividing HCLK by 1 2 to 1 24 or SCLK by 1 2 to 1 24 HCLK Y Clock Divider SCLK gt R 214 L_THCLK 2 213 212 BUZCTR BUZS2 0 Count Clear Output gt Output BUZA BUZB BUZCTR BUZOE Controller 29 Control gt Inverted Buzzer Output NBUZA NBUZB 9 Reset 24 BUZCTR BUZOE scLk 23 BUZCTR BUZS2 0 Figure 15 1 1 Buzzer Block Diagram XV 2 Overview Chapter 15 Buzzer 15 2 Control Register 15 2 1 Registers Table 15 2 1 shows the Buzzer Control Registers
292. er 0 to Timer 5 The binary counter counts up with the selected count clock as shown below This is the basic operation for all functions of 8 bit timer Count Clock TMnEN bit Internal enable Compare register I D um X 9 C CCC counter Interrupt request Figure 8 3 1 Count Timing of Timer Operation Timer 0 to Timer 5 A If any data are written to the compare register while the count operation is disabled the TMnMD TMnEN is set to 0 the binary counter is cleared to 0x00 B When activating the counter by setting the TMnMD TMnEN to 1 the internal enable is set at the next count clock Then the binary counter starts counting up from the next count clock where the internal enable has been set C When the value of binary counter matches the setting value of compare register an interrupt request is generated at the next count clock Then the binary counter is cleared and restarts counting up D Even if the compare register is rewritten while the count operation is enabled the TMnMD TMnEN is set to 1 the binary counter is not changed E When the count operation is disabled the TMnMD TMnEN is set to 0 the internal enable is reset at the next count clock The binary counter stops counting VIII 16 8 bit Timer Chapter 8 8 bit Timer Stop the timer when switchi
293. er 1 is set to 0x0000 10000 PWM output is High while the counter is stopped by setting TMnMD1 TMnEN to 0 IX 32 16 bit Standard PWM Output with Continuously Variable Duty Chapter 9 16 bit Timer W Count Timing of Standard PWM Output when compare register 1 is set to OxFFFF Compare 2022 2 register 1 counter TMnIO output PWM output Figure 9 6 3 Count Timing of Standard PWM Output when compare register 1 is set to 0xFFFF When outputting the standard PWM set the TMnMD2 TMnBCR to 0 to select the full count overflow as the binary counter clear source and the PWM set source to High state The TMnOC1 compare match or the TMnOC2 compare match can be selected as a PWM output reset source Low output with the TMnMD2 TnPWMSL The PWM output at the initial state for Timer 7 and 9 is Low It changes to High at the time the PWM operation is selected by setting the TMnMD2 TMnPWM For Timer 8 it is in accordance with the setting of the TM8MD2 TM8PWMF and TM8MD2 TM8PWMO preset register to clear the binary counter and the PWM waveform Otherwise the PWM lt When restarting the PWM operation after PWM operation has been stopped write data to the waveform of the first cycle is not guaranteed 16 bit Standard PWM Output with Continuously Variable Duty IX 33 Chapter 9 16 bit Timer 9 6 2 Setup Example Ei eae W Standard PWM Output
294. er 13 Serial Interface Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn TXBUFn Set transmission data in TXBUFn Transmission end Setting Start bit reception Register name Repeat these procedures from step 1 to execute the next communication Description Detect a start bit Wait for communication completion SCnSTR SCnREMP When reception data are stored in RXBUFn SCnSTR SCnREMP is set to 1 When an interrupt is enabled a communication complete interrupt SCnTIRQ occurs Reception error and break reception SCnSTR SCnBRKF SCnSTR SCnFEF SCnSTR SCnPEK SCnSTR SCnERE If an error occurs SCnSTR SCnERE is set to 1 Take measures such as data retransmission since reception data may be destroyed When a break reception SCnBRKF is set to 1 The above flag is updated every frame data reception Confirm the flag immediately after communication has been completed The flag can be also confirmed at step 5 if there is enough time to check it Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn Confirmation of overrun error SCnSTR SCnORE SCnSTR SCnERE If SCnORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea sures such as data retransmission since reception data may be destroyed Reception end m UART Break Transmission Setting Empty confirmation
295. errupt Upper 8 bits timer TM1ICR TM1IE 0 Lower 8 bits timer 2 Set the timer mode register TMOMD TMOPWM 0 Select the timer normal operation Lower 8 bits timer TMOMD TMOMOD 0 3 Set the cascade connection TM1MD TM1CAS 1 Select the cascade connection 3 Set the clock source TMOMD TMOCK1 0 01 Select the prescaler as the clock source Lower 8 bits timer 4 Set the prescaler CKOMD TMOPSC1 0 Select SYSCLK 2 Lower 8 bits timer CKOMD TMOBAS 1 6 Set the interrupt cycle 0xC3 Set the interrupt generation cycle TM10C 0x09 Setup value 2500 1 0x09C3 6 Set the interrupt level TM1ICR TM1LV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Upper 8 bits timer 8 Enable the interrupt TM1ICR TM1IE 1 Upper 8 bits timer 9 Enable the timer counter TMOMD TMOEN 1 Enable the timer count operation Lower 8 bits timer 8 bit Timer Cascade Connection VIII 33 Chapter 8 8 bit Timer VIII 34 8 bit Timer Cascade Connection Chapter9 16 bit Timer Chapter 9 16 bit Timer 9 1 Overview Table 9 1 1 shows the functions of 16 bit Timer Table 9 1 1 16 bit Timer Functions Timer 7 TM7 Timer 8 TM8 Timer 9 TM9 2 Interrupt source TM7IRQ TM7OC2IRQ TM8IRQ TM8OC2IRQ TM9IRQ TM9OC2IRQ Timer operation Event count Timer pulse output Standard PWM output with variable duty High precision PWM output with var
296. ess type R W data size 1 2 bytes data data mask range and NOT Stop execution forcibly by pressing the escape key or by clicking stop icon of GUI Supported 1 channel Supported Software break Replacement specified address instruction with break instruction Supported Software Instruction break Software break to ROM area Supported 2 channels Execution address break Hardware Define address and range Supported Data access break Define access type R W data size 1 2 bytes data data mask range and NOT Supported Malfunction detection Support Unimplemented instruction break Break by execution of unimplemented instruction Supported Function use frequency measurement Profile function Measure the frequency of subroutine function execution Supported non intrusive functions Break setting memory reference and changing trace setting and display during program is executing The real time performance slows down little by RAM monitor or Watch Supported On board programming On board programming to embedded non volatile memory by using the function of On board debug Supported Refer to DebugFactory Builder for MN101 help for details of debugging functions List of on board debugging functions Chapter 19 On Board Debugger XIX 4 List of on board debugging functions Chapter 20 Appendix Chapter 20 Appendix 2
297. et the CPUM as described in Table 4 1 3 HALT mode Figure 4 2 10 Transition from CPU Operating Mode to HALTO HALT1 HALT2 Mode Mode Control Function Chapter 4 Clock Voltage Control NORMAL SLOW mode NO CPUM XIMOD 1 Start the low speed oscillation CPUM XIMOD 1 The low speed oscillation stabilization wait time Transition to HALT3 mode Set the CPUM as described in Table 4 1 3 When SCLKCNT SOSCCNT 1 SOSCCLK starts When SCLKCNT SRCCNT 1 SRCCLK starts HALT3 mode Figure 4 2 11 Transition Flow from CPU Operating Mode to HALT3 Mode If the value of xICR LV1 0 for an interrupt to be used as a return factor is equal or larger than the value of PSW IM1 0 before transition to STANDBY mode it is impossible to return to CPU operating mode by a maskable interrupt Mode Control Function IV 21 Chapter 4 Clock Mode Voltage Control IV 22 W Transition to STOP Mode The system changes from mode of NORMAL SLOW to STOP0 STOP1 mode In any case both oscilla tion and CPU are stopped A reset or an interrupt is a source for wake up from STOP mode Figure 4 2 12 shows the transition procedure from CPU operating mode to STOP mode In STOP mode the value of the WDT counter is cleared After waking up from STOP mode oscillation stabiliza tion wait time is inserted and the timer starts counting Transition procedure from NORMAL mode to STOPO
298. etecting the falling edge of the TM7IOA input 5 times generates the first interrupt only and subsequent interrupts are generated every 4 detections The setup procedure and its description are shown below Step Setting Register Description Disable the timer counter TM7MD1 TM7EN 0 Disable the timer count operation Disable the interrupt TM7ICR TM7IE 0 Disable the timer interrupt Select the event input TMIOSEL1 TM7IOSEL1 0 00 Select the event clock input pin PODIR PODIR4 0 Chapter 7 I O Port Set the timer mode register TM7MD1 TM7CK1 0 01 Select SYSCLK as the clock source TM7MD1 TM7PS1 0 00 Set the interrupt cycle TM7PR1 0x0003 Set the interrupt generation cycle Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source TM7MD1 TM7CK1 0 10 Select TM7IO input as the count clock source TM7MD1 TM7PS1 0 00 Set the interrupt level TM7ICR TM7LV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup Enable the interrupt 7 7 1 Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation 16 bit Event Count Chapter 9 16 bit Timer 9 5 16 bit Timer Pulse Output 9 5 1 Operation 16 bit Timer Pulse Output Operation In the timer pulse output function a pulse signal with an arbitrary frequency can be output from TMnIO pin Timers can output the signal with twice the cycle which is set in 1 or
299. ety devices in which exceptional quality and reliability are required or if the failure or malfunction of the products may directly jeopardize life or harm the human body It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application unless our company agrees to your using the products in this book for any special application e products and product specifications described in this book are subject to change without notice for modification and or im 4 The products and product specificat described in this book bject to chang hout fi difi d provement At the final stage of your design purchasing or use of the products therefore ask for the most up to date Product Standards in advance to make sure that the latest specifications satisfy your requirements 5 When designing your equipment comply with the range of absolute maximum rating and the guaranteed operating conditions operating power supply voltage and operating environment etc Especially please be careful not to exceed the range of absolute maximum rating on the transient state such as power on power off and mode switching Otherwise we will not be liable for any defect which may arise later in your equipment Even when the products are used within the guaranteed values take into the consideration of incidence of break down and failure
300. ference voltage is supplied from outside of the LSI When BSTVOL is used with the input reference voltage from outside of the LSI the LCD drive voltage described in Figure 17 3 3 is generated Connect the capacitor of 0 22 uF at VLC1 VSS VLC2 VSS VLC3 VSS Table 17 3 3 Voltage Level of VLC1 VLC2 VLC3 when BSTVOL is used Pin Name Voltage Level 2 times boost 2 3 times boost Static 1 2 bias 2 x Vice is output 1 3 bias 3 x Vica is output Supply the reference voltage Vi c2 Vi 2 x Vica is output Supply the reference voltage the LCDMDO LCUPCKDIV2 0 and LCDMDO LCUPCKS2 0 or generate LCD drive voltage a When the brightness of LCD panel is not enough increase the frequency of LCUPCK with outside the LSI Refer to 1 In the case of generating the drive voltage outside the LSI XVII 22 Operation Chapter 17 LCD lt 3 gt In the case of generating the drive voltage with BSTVOL The reference voltage is generated with REFVOL REFVOL output the reference voltage between 0 9 V and 1 8 V and BSTVOL generate 2 3 times higher voltage of the reference voltage Table 17 3 4 shows the output voltage from VLC1 VLC2 VLC3 Connect the capacitor of 0 22 uF at VLCI VSS VLC2 VSS and VLC3 VSS Table 17 3 4 Voltage level of VLC1 VLC2 VLC3 when BSTVOL REFVOL are used 2 3 times boost Pin Name Voltage Level 1 3 bias 3 x Vi is output 2
301. fter the TMnMD1 TMnEN is set to 1 When it is assumed that the set ting value of TMnOC1 is N the first interrupt is generated at the rising edge of N 2 th count clock The following interrupts are generated at the rising edge of N 1 th count clock Be sure to set a count clock of 16 bit timer while a timer interrupt is disabled 16 bit Timer IX 23 Chapter 9 16 bit Timer 9 3 2 Setup Example W Timer Operation Setup Example Here is an example that the periodic interrupt of Timer 7 is generated every 1000 cycles 250 us with selecting HCLK 2 at fycpK 8 MHz as a clock source The setup procedure and its description are shown below Setting Disable the timer counter Register TM7MD1 TM7EN 0 Description Disable the timer count operation Disable the interrupt TM7ICR TM7IE 0 Disable the timer interrupt Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 01 Select the clock source Set the interrupt cycle TM7PR1 0x03E7 Set the cycle of timer interrupt Setup value 1000 1 999 0x03E7 Set the interrupt level TM7ICR TM7LV1 0 Enable the interrupt 7 7 1 Refer 3 1 3 Maskable Interrupt Control Register Setup IX 24 Enable the timer counter 16 bit Timer TM7MD1 TM7EN 1 Enable the timer count operation Chapter 9 16
302. g the bit to 1 to select the rising edge the count operation is executed while the corresponding inter rupt pin is High When setting the bit to 0 to select the falling edge the count operation is executed while the corresponding interrupt pin is Low To control the activation with the instruction select TM7EN count operation In that case the timer count oper ation and IGBT output are controlled with the TM7MD1 TM7EN When setting the bit to 1 to start counting the count operation continues until the bit is set to 0 to stop counting Be sure to set the TM7MD3 T7IGBTO 1 before setting the TM7MD1 TM7EN In this case The setting of the TM7MD3 T7IGBTTR is invalid When the counter is stopped the binary counter is cleared at the same time The data of the preset register are loaded to the compare register in synchronization with the count clock W Dead Time Count The dead time counter counts the timer source clock When the dead time is set to be inserted at the falling edge the time from the falling edge of TM8IO to the rising edge of TM7IO is set by TM7DPRI and the time from the falling edge of TM71IO to the rising edge of TM8IO is set by the TM7DPR2 The dead time inserted actually is the setting value in TM7DPR2 cycles Only during the period from the time when the IGBT output is enabled by the IGBT trigger to the first rising edge of TM71O in the input at IGBT falling edge the dead time is the setting value in TM7DPR1
303. g the interrupt processing right after the slave address reception When the received slave address is not equal to SCnAD SC3IICSTR IIC3STRT is cleared automatically by hardware Confirm a busy flag to detect a stop condition Conditions to detect a start or a stop condition are shown in the table below Table 13 5 1 Start Condition Stop Condition Detection Condition High period of SCLn SCnCLK period x 3 Start Condition SDAn setup time gt SCnCLK period x 2 SDAn hold time 2 SCnCLK period x 2 High period of SCLn SCnCLK period x 3 Stop Condition SDAn setup time gt SCnCLK period x 2 SDAn hold time 2 SCnCLK period x 2 Busy Flag IIC3BUSBSY is set when a start condition is detected on the IIC bus and is cleared when a stop condition is detected It is possible to check that communication is executed between devices IIC bus m ACK NACK Transmission and Detection When the LSI receive data select ACK NACK transmission with SCnMD3 JIC3ACKO When LSI send data confirm that ACK NACK is received with SCnMD3 IIC3ACKO First Bit Specification for Transfer First bit for transfer can be selected Select MSB first or LSB first with SCnMDO IIC3DIR XIII 58 IIC Communication Chapter 13 Serial Interface W Detection of Communication Forcibly Terminated When a start stop condition is detected during the transmission reception of data including a slave address and R
304. gn Dn DWm Dm Dn Dm 000d ADD imm4 Dm Dm sign imm4 gt Dm ADD imm8 Dm Dm imm8 Dm ADDC Dn Dm Dm CF 2 Dm ADDW DWn DWm DWm DWn gt DWm ADDW DWn Am Am Am ADDW imm4 Am Am sign imm4 gt Am ADDW imm8 Am Am sign imm8 gt Am ADDW imm16 Am Am imm16 Am ADDW imm4 SP SP sign imm4 SP ADDW imm8 SP SP sign imm8 SP ADDW imm16 SP SP imm16 5 SP ADDW imm16 DWm DWm imm16 gt DWm ADDUW Dn Am Am zero Dn ADDSW Dn Am Am sign Dn gt Am SUB Dn Dn Dm Dm Dn gt SUB Dn Dn Dn Dn gt Dn SUB imm8 Dm Dm imm8 gt Dm SUBC Dn Dm Dm CF gt Dm SUBW DWn DWm DWm DWn gt DWm SUBW DWn Am Am DWn gt Am SUBW imm16 DWm DWm imm16 gt DWm SUBW imm16 Am Am imm16 gt Am MULU Dn Dm Dm Dn DIVU Dn DWm DWm Dn gt DWm l DWm h CMP Dn Dm Dm Dn PSW CMP imm8 Dm Dm imm8 PSW CMP imm8 abs8 mem8 abs8 imma PSW CMP imm8 abs12 mem8 abs12 imm8 PSW CMP imm8 abs16 mem8 abs16 imm8 PSW CMPW DWn DWm DWm DWn PSW CMPW DWn Am Am DWwn PSW CMPW Am PSW CMPW imm16 DWm DWm imm16 PSW CMPW imm16 Am Bitwise Log
305. gnal as trig ger is disabled Set the TMnMD2 TnICEN to 1 to enable the trigger of the external interrupt signal IX 42 16 bit Timer Capture Function Chapter 9 16 bit Timer W Capture Operation with a Trigger of Software Writing A capture trigger can be generated by writing an arbitrary value to TMnIC Synchronizing with this capture trig ger the value of the binary counter is loaded to TMnIC TMnEN bit Compare register Binary 01110112 0113 0114 555515556 sss sss N counter System clock Capture trigger Capture 0000 0114 5558 Figure 9 8 2 Capture Count Timing with a Trigger of Software Writing T A capture trigger is generated at the writing signal to the input capture register synchronizing with the capture clock Synchronizing with this capture trigger the value of the binary counter is loaded to the input capture regis ter The value loaded to the capture register is the binary counter value at the falling edge of the capture trigger The other count timing is the same as that of the timer operation On hardware there is no bit to disable the capture operation triggered by software writing The capture operation is enabled regardless of the TMnMD2 TnICEN 16 bit Timer Capture Function IX 43 Chapter 9 16 bit Timer m Capture Operation with a Trigger of an Interrupt of Timer 0 or 1 Timer 7 and Timer 8 A capture trigger of the input
306. gram area 62 KB 1000 times Min Data area 2 KB 100 000 times Min Programming Voltage Vppao 1 8V to 3 6 V Reading Voltage Vppso 1 1 V to 3 6 V Data retention duration 10 years ReRAM programming method Programmer writing Self programming Programming data unit 1 Byte Max 64 Bytes at once Function of data protection Protective function Security function 1811 ReRAM Rewriting Method The data of ReRAM can be programmed with the following method Programmer writing ReRAM is programmed with an external unit such as a debugger PanaX EX or a serial programmer Self programming ReRAM is programmed with the software embedded in the program area XVIII 2 Overview of ReRAM Chapter 18 ReRAM 18 1 2 ReRAM Area Table 18 1 2 shows program data and reserved areas in RERAM Table 18 1 2 Application of ReRAM area Application Access cycle Rewriting 0x04000 to Ox040FF Program area Available 0x04900 to 0x13FFF Store the user program Y Data area 0x04100 to 0x048FF Store the data 2 cycles Available User program can be stored in this area Reserved area Ox6F00049 OxeFBEF 3 Software library for programming ReRAM is stored leyele 18 1 3 Data Protection Function The following functions are available to protect the data of m Protective Function Protective Function prevents uninten
307. gure 13 5 11 Slave Reception Timing Stop Condition Detection 1 Detect start condition 2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set dummy data to TXBUFn in interrupt handler 5 Receive data 6 Transmit ACK bit 7 Set dummy data to TXBUFn in interrupt handler 8 Detect stop condition XIII 66 IIC Communication Chapter 13 Serial Interface W Slave Reception Timing Restart Condition Detection 1 2 3 4 5 6 7 8 227 i e 8 bits reception P SDAn SCLn SCnTIRQ IIC3STRT IICSADD ACC IICSBUSBSY c Set dummy data to TXBUFn Set dummy data to TXBUFn Figure 13 5 12 Slave Reception Timing Restart Condition Detection 1 Detect start condition 2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set dummy data to in interrupt handler 5 Receive data 6 Transmit ACK bit 47 Set dummy data to TXBUFn in interrupt handler 8 Detect restart condition IIC Communication 67 Chapter 13 Serial Interface 13 5 4 Setup Example Setting Example of Master Communication 1 As initial setting register changed at the time of serial reset is shown below Please change it if needed such as interrupt setting or port setting Master setting at slave address transmission SCnMD0 Be sure to seti Be sure to set i Be sure to se SCnMD1 Be sure to se sure to
308. h 16 bit High Precision PWM Output with Continuously Variable Period Duty IX 37 Chapter 9 16 bit Timer 9 7 2 Setup Example v lt Ossm TKm s R nnae U 55 W High Precision PWM Output Setup Example Here is an example that using Timer 7 the PWM output waveform with the 1 4 duty cycle and 400 Hz is output from TM7IO output pin HCLK 2 8 MHz is selected as a clock source The setup procedure and its description are shown below TM7IO output 400 Hz Figure 9 7 4 Output Waveform of TM71O output pin Step Setting Register Description 1 Disable the timer counter TM7MD TM7EN 0 Disable the timer count operation Select the timer output pin MIOEN1 TM7OEN 1 Select the timer output pin ODIR PODIR4 1 Chapter 7 I O Port M7MD2 TM7PWM 1 Select the PWM output Set the timer mode register M7MD2 T7PWMSL 1 source of PWM output M7MD1 TM7CK1 0 00 Select HCLK 2 as the count clock source M7MD1 TM7PS1 0 01 Set the PWM cycle 1 0x270F Set the cycle PWM output Setup value 10000 1 9999 0x270F Set the High period of PWM TM7PR2 0x09C3 Set the High period of PWM output Setup value 10000 4 1 2499 0x09C3 T P T TM7MD2 TM7BCR 1 Select the TM7BC clear source and the duty determination T T T Enable the timer counter TM7MD1 TM7EN 1 Enable the timer count operation IX 38 16 bit High Precision PWM Output with
309. hannel 7 AN0 to AN7 of analog input can be switched by software When the ADC is stopped the power consumption be reduced by turning the A D resistor ladder off The ADC is activated by setting a register an external interrupt a timer 7 interrupt and an A D conversion inter rupt 16 1 1 Functions Table 16 1 1 shows the ADC functions Table 16 1 1 ADC Functions Function Content Number of A D Input Pins 8 pins Pin Name AN7 to ANO Interrupt ADIRQ Resolution 12 bits Conversion Time Minimum 15 38 us at TADCLK 750 ns Input Range Vss to Power Reduction A D resistor ladder ON OFF lt This function can not be used in STOP HALT mode Normal operation state NORMAL to Low speed operation state SLOW Low speed operation state SLOW to Idle state IDLE to Normal operation state NOR 1 Do not execute mode switching as follows MAL If the above mode switching is executed the result of A D conversion can not be guaranteed To realize a low power consumption it is recommended that the A D resistor ladder is turned off while the A D conversion is not executed XVI 2 Overview Chapter 16
310. hapter 11 RTC Time Base Timer RTC TBT 11 3 RTC TBT Operation 11 3 1 RTC TBT Operation RTC TBT counts up at the rising edge of SCLK after the internal reset T128HZ T64HZ T32HZ T16HZ T8HZ T4HZ and T2HZ bits of the TBTR register are used as RTC TBT inter rupt The interrupt request is generated at the rising edge of each output When writing data to the TBTR register it is cleared and T128HZ T64HZ T32HZ T16HZ T8HZ TAHZ T2HZ and T1HZ become 0 TBTR Write request T256HZ T128HZ T SSS pU i eee a Mmm ET Figure 11 3 1 Output Waveform and clearing time of RTC TBT RTC TBT Operation XI 9 Chapter 11 RTC Time Base Timer RTC TBT 11 3 2 Operation Setting Example k iOussOO s vnsrsm svs nwAsOohuhiVsi W Interrupt of RTC TBT 128 Hz periodic interrupt by RTC TBT is generated The setup procedure and the description of each step are shown below Setting Description Disable all maskable interrupts PSW Set the MIE bit to 0 Set the interrupt level PERIOICR Set the PERIOLV1 0 bits to 00 Clear the corresponding interrupt request bit of PERIODT register if it may have already been set Refer to Chapter 3 3 1 3 Maskable Interrupt Control Register Setup Set output of RTC TBT interrupt TBTCNTO Set the TBTIRQSEL2 0 bits of register to 000 Enable output of RTC TBT TBTCNTO Set the TBTIRQEN bit of TBTCNO register to 1
311. he pin of Timer 4 TM4IOA or TM4IOB TM4IOSEL 0 TM4IOA P34 1 TM4IOB P01 Select the pin of Timer 3 or TM3IOSEL 0 TMSIOA P56 1 TM3IOB P72 Select the pin of Timer 2 TM21OA or TM2IOB TM2IOSEL 0 TM2IOA P05 1 TM2IOB P02 Select the pin of Timer 1 TM1IOA or 1 TM1IOSEL 0 TM1IOA P55 1 TM1IOB P20 Select the pin of Timer 0 TMOIOA or TMOIOB TMOIOSEL 0 TMOIOA P05 1 TMOIOB VII 26 Control Registers Chapter 7 I O Port 7 2 9 16 bit Timer output control Register 16 bit Timer output control register selects the pin function General IO GIO or 16 bit Timer output 16 bit Timer output control Register TMIOEN1 0x03F2E Bit name TM8OEN TM7OEN At reset 0 pes Bit name Description Always read as 0 Select the pin function GIO or Timer 9 output TM9OEN 0 GIO 1 Timer 9 output TM9IOA TM9IOB TM9IOC Select the pin function GIO or Timer 8 output TM8OEN 0 GIO 1 Timer 8 output TM8IOA TM8IOB TM8IOC Select the pin function GIO or Timer 7 output TM7OEN 0 GIO 1 Timer 7 output TM7IOA TM7IOB TM7IOC Control Registers VII 27 Chapter 7 Port 7 2 10 16 bit Timer input output pin selection Register 16 bit Timer input output pin selection register selects the output pin of 16 bit Timer TMnIOA to TMnIOO gm 16 bit Timer input ou
312. he timer mode register TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 00 Select HCLK as the count clock source Set the IGBT output cycle TM7PR1 0x61A7 Set the IGBT output cycle Setup value 25000 1 24999 0x61A7 Set the High period of IGBT TM7PR2 0x1869 Set the High period of IGBT output Setup value 25000 4 1 6249 0x1869 Enable the timer counter TM7MD1 TM7EN 1 16 bit High Precision IGBT Output with Variable Period Duty Enable the timer count operation 57 Chapter 9 16 bit Timer IX 58 9 11 IGBT Output with Dead Time The IGBT output with dead time which is delay time for ON OFF is output from TM71IO or TMSIO pin when the referenced IGBT signal is inverted The output trigger is selected from IRQO 1 2 and Timer 7 count operation Updating the Timer 7 preset register 1 2 and Timer 7 dead time preset register 1 2 is prohib Y ited during IGBT operation 9 11 1 Operation IGBT Output Operation with Dead Time Timer 7 The IGBT output with dead time can be selected with the TM7MD4 T7NODED The dead time value can be set with TM7DPR1 and TM7DPR2 Only Timer 7 can support the IGBT output with dead time m IGBT Trigger IGBT trigger can be selected from IRQO 1 2 and Timer 7 count operation by setting TM7MD3 TM7IGBTO 1 When using IRQO 1 and 2 as a IGBT trigger the valid level is selected by setting the TM7MD3 T7IGBTTR When settin
313. iable duty cycle TM7IOA P04 TM7IOB P34 TM7IOC P03 TMBIOA P57 TM8IOB P06 TMBIOC P02 TMQIOA P07 9 P20 9 P00 Standard IGBT output with variable duty High precision IGBT output with variable duty cycle 7 P04 7 P34 7 P03 TMBIOA P57 8 P06 TM8IOC P02 Capture function Clock source pins used for each 16 bit Timer has three pin groups Group A Group B and Group C ex Timer 7 TM7 HCLK HCLK 2 HCLK 4 HCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 16 TM7IO input TM71O input 2 TM71O input 4 TM7IO input 16 SCLK SCLK 2 SCLK 4 SCLK 16 has TM7IOA TM7IOB and TM7IOC In this chapter the suffix of A and 1 omitted to describe functions of 16 bit Timer Overview HCLK HCLK 2 HCLK 4 HCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 16 TM8IO input TM8IO input 2 TM8IO input 4 TM8IO input 16 SCLK SCLK 2 SCLK 4 SCLK 16 HCLK HCLK 2 HCLK 4 HCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 16 TM9IO input TM9IO input 2 TM9IO input 4 TM9IO input 16 SCLK SCLK 2 SCLK 4 SCLK 16 16 bit Timer n Block Diagram n 7 8 and 9 HCLK HCLK 2 HCLK 4 HCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 M SYSCLK 16 TMnIO input TMnIO input 2 TMnIO input 4 TMnIO input 16 SCLK SCLK 2 SCLK 4
314. ical Instructions AND Dn Dm Am imm16 PSW Dm amp Dn gt gt 0111 DnDm AND imm8 Dm amp imm8 gt 0001 11Dm AND imm8 PSW PSW amp imm8 PSW 1001 0010 OR Dn Dm Dm Dn gt 0110 DnDm OR imm8 Dm Dm imm8 gt Dm 0001 10Dm OR imm8 PSW PSW imm8 gt PSW 1001 0011 lt 8 XX 6 XOR Dn Dm Dm Dn gt Dm 1010 DnDm XOR imm8 Dm Instruction set Dm imm8 Dm m ol o 1010 DmDm lt 8 1 D DWn d DWm 2 A An a Am 3 4 D DWk 5 D DWm 6 4 sign extention 7 8 sign extention 8 Dn zero extention 9 10 When the access address is odd number the execution cycle is added 1 d MN101L SERIES INSTRUCTION SET gt Dm 20 Appendix Dn msb temp Dn Isb gt Dn gt gt 1 Dn temp gt Dn msb Dn lsb CF Dn gt gt 1 Dn 0 D
315. ing Register RTCMOD OxO3EE5 Bit name At reset Access Bit name Description Always read as 0 Month setting Set a value within the range of 01 to 12 using the BCD format The value is incremented by one from 01 to 12 per day The value which doesn t exist must not be set MODA to 0 Year Setting Register RTCYD Bit name At reset Access bp Bit name Description Year setting Set a value within the range of 00 to 99 using the BCD format YD7t00 The value is incremented by from 00 to 99 per day The value which doesn t exist must not be set The Year ending in 00 or divisible by 4 is set as a leap year automatically Control Registers XII 13 Chapter 12 Real Time Clock RTC 12 2 6 Status Register m Status Register RTCSTR 0x03ED1 re weer le ee SE SET TES At reset 0 0 0 0 0 0 0 1 Access R R R R R R R R 5 rm fon _ _ Leap year flag LEAPFL 0 RTCYD does not show a leap year 1 The RTCYD shows a leap year XII 14 Control Registers Chapter 12 Real Time Clock RTC 12 3 RTC Operation When the RTCCTR CLKEN is set to 1 RTC starts time counting by using the clock registers described in 12 2 5 Clock Registers RTC has two types of interrupts the perio
316. ing Rewriting Method XVIII 5 Chapter 18 ReRAM 18 3 ReRAM Control Registers 18 3 1 shows ReRAM control registers Register symbol FBEWER Address 0x03D80 Table 18 3 1 ReRAM Control Registers Access Register name and function Rewriting enable register 0x4B Enable programming Others Disable programming WADDR_L WADDR_M WADDR_H 0x03D82 0x03D83 0x03D84 Rewrite address register Specify the address to be rewritten WBC 0x03D85 Rewrite byte count register Specify the number 1 of rewriting data can be set 0 to 63 P L P WDATA M 0x03D86 0x03D87 XVIII 6 ReRAM Control Registers Rewrite data pointer register Specify the start address of RAM area in which stores rewriting data Chapter 18 ReRAM 18 4 Command Library Table 18 4 1 shows command libraries for rewriting of the ReRAM Table 18 4 1 Command Libraries Library name Write Code Lib Write Data Lib Address Ox6F205 Ox6F20A Function Programming Data in Program Area Specified byte number 2 64 bytes is programmed Programming Data in Data Area Specified byte number 2 64 bytes is programmed Byte_Write_Lib Ox6F220 Programming Byte Data in Data Area Specified one byte is programmed Protect Set Lib Ox6F210 Protective Function Setting Activate Protective Function in the specified address area Security_Key_Set_Lib 0 6 215
317. ing of High Precision IGBT Output when compare register 2 compare register 1 Timer 7 Cont 1 A A A T A clock TM7EN bit Compare register 1 Compare YY 2 H H IGBT trigger oue Xo Con Qe TM7IO output MN IGBT output TM8IO output IGBT output Figure 9 10 3 Count timing of High Precision IGBT Output when compare register 2 compare register 1 16 bit High Precision IGBT Output with Variable Period Duty Chapter 9 16 bit Timer When using the high precision IGBT output set the TM7MD2 TM7BCR to 1 to select the TM7OC1 compare match as the binary counter clear source and the IGBT output set source to High state Also set the TM7MD2 T7PWMSL to 1 to select 7 2 compare match as the IGBT output reset source to Low state The IGBT output at the initial state becomes Low when setting the TM7MD3 T7IGBTEN to select the IGBT output It changes to High at the second count clock cycle from the trigger input When using the high precision IGBT output set the values of TM7OC1 and 2 as follow TM7OC2 lt TM7OC1 If TMnOC2 gt TMnOC1 the IGBT output is fixed to High One shot Pulse Output of High Precision IGBT Normal Timer 7 TM7EN bit Compare register 1 N Compare I I register 2 i i E E E E i M IGBT trigger Binary ANS NE TM7
318. interrupt Enable RTC TBT interrupt PERIOEN Set the PERIOENG bit to 1 Enable the maskable interrupt PSW Set the MIE bit to 1 For PERIOICR and PERIOEN refer to Chapter 3 Interrupts For PSW refer to Chapter 2 CPU XI 10 Operation Chapter 12 Real Time Clock RTC Chapter 12 Real Time Clock RTC XII 2 12 1 Overview Real Time Clock RTC provides the calendar function Table 12 1 1 shows functions of RTC Table 12 1 1 RTC Function Function Description Clock source RTC time base timer output 1 Hz Time display Auto calender years with the last two digits from 00 until 99 Adjustment for leap year Years ending in 00 and divisible by 4 are set as leap years Two time Display mode 12 hour clock or 24 hour clock Periodic interrupt 1 2 second 1 second 1 minute 1 hour Alarm 0 interrupt Generated when specified date hour minute match Alarm 1 interrupt RTC time base timer output 2 Hz RTC time base timer output 1 Hz Overview Generated when specified month day hour minute match Controls periodic interrupts yn Periodic interrupt Controls n Alarm 0 interrupts p Alarm O interrupt Controls Alarm 1 interrupts 0 5 seconds 1 second 1 minute 1 hour h Alarm 1 interrupt Operation control
319. ion For more information refer to XIII 35 Activation Source for Communication Data write to TXBUFn is the trigger to start data transmission In data reception a communication starts with a detection of start bit Low level input time of 0 5 transfer clock or more is required for a detection of start bit Interrupt In data transmission transmission complete interrupt SCnTIRQ occurs every 1 frame transmission completion In data reception reception complete interrupt SCnRIRQ occurs every 1 frame reception completion Full duplex UART Communication XIII 49 Chapter 13 Serial Interface Transmission BUSY Flag When SCnMDI SCnSBOS is 1 SCnSTR SCnTBSY is set to 1 by writing data to TXBUFn When SCnSTR SCnTEMP is 0 no data existed in TXBUFn SCnSTR SCnTBSY is cleared to 0 when SCn TICR occurs While SCnSTR SCnTEMP is 1 data existed in TXBUFn SCnSTR SCnTBSY is held at 1 when SCnTICR occurs m Reception BUSY Flag When SCnMD1 SCnSBIS is 1 SCnSTR SCnRBSY is set to 1 by a start bit detection When SCnTICR occurs SCnSTR SCnRBSY is cleared to 0 Reception Error Flag Reception error sources are shown in Table 13 4 3 All error flags are updated when a reception finishes SCnSTR SCnERE shows the logical OR of three error flags When the data is received before the previous data is read from RXBUFn SCnSTR SCnORE is set to 1 To clear SCnSTR SCnORE set SCnREMP to 0 by reading data from RXBU
320. ion mode 1 byte communication mode When the LSI is a master wait time for communication start Twait of up to 3 5 transfer clocks is inserted until communication starts after a data write to TXBUFn When the LSI is a slave T must be ensured until a trans fer clock is input after a data write to TXBUFn Write data to TXBUFn only when SCnSTR SCnTEMP is 0 Y If data is written to TXBUFn while SCnTEMP is 1 SCIFn does not work properly by external noise while serial communication is not executed Transfer clock input is enabled a When the LSI is a slave a transfer clock is not input to prevent abnormal operation caused after a wait time of 3 5 transfer clocks has elapsed after a data is written to TXBUFn Reception Data Buffer RXBUFn and Reception Buffer Empty Flag SCnREMP RXBUFn is a buffer to store the received data The received data in the reception shift register is transferred to RXBUFn automatically SCnSTR SCnREMP is set to 1 when reception data is stored in RXBUFn and is cleared to 0 when the data is read out from RXBUFn Be sure to read out the received data in RXBUFn before the following data reception finishes The received data in RXBUFn is updated with new data every time the data reception is completed If data is read from RXBUFn when SCnREMP is 0 SCIFn does not work properly When receiving the following data before reading the data in RXBUFn register an overrun
321. ion with the falling edge of the clock Figure 13 3 6 3 wire Communication Transmission Reception Timing When SCnCKPH 0 and SCnCE1 0 32 Clock Synchronous Communication Chapter 13 Serial Interface SBT pin Data is received in synchronization with the falling edge of the clock SBI pin Data is sent in synchronization with the rising edge of the clock SBO pin Figure 13 3 7 3 wire Communication Transmission Reception Timing When SCnCKPH 0 and SCnCE1 1 Figure 13 3 8 shows the 4 wire communication waveform when SCnCKPH 1 Data are received at a leading edge and transferred at a trailing Conversely During 4 wire communication when SCnCKPH 0 data are received at a trailing edge and transferred at a leading edge as shown in Figure 13 3 9 In master communication a transfer clock is output from SBTn after the time of 0 5 transfer clock 0 5 has elapsed since SBCSn was asserted In slave communication input a transfer clock to SBTn after the time of 0 5 transfer clock 0 5 T has elapsed since SBCSn was asserted The last bit data output hold time of transmission data is different depending on the value of SCnCKPH Refer to Figure 13 3 8 and Figure 13 3 9 Allow adequate 1 T time for the last bit of reception data to hold data T 1 4 SBTn i i Bonomi XL X X C SBTn 0 5T minimum value SCnCE1 1 i 5 receptiontiming ____ __ 4 imn At mas
322. l high speed oscillation pin OSC2 Output When the external high speed oscillation is needed connect the oscillator to the pins The external clock can be input through OSC1 and leave OSC2 open XI Input External low speed oscillation pin XO Output When the external low speed oscillation is needed connect the oscillator to the pins NRST Input Reset pin N channel open drain pin Output When NRST is set to Low LSI is initialized LSI reset condition is described in 2 5 Reset DMOD Input Mode setting pin Always set DMOD to Low level except for connecting the external LSI debugger or serial program mer NATRON Input Auto reset control pin To use the auto reset function set NATRON to Low level If not set NATRON to High level Chapter 1 Overview The voltage level of VREFP must be over 0 8 at any time including LSI power on Pin Description 1 15 Chapter 1 Overview Table 1 3 2 General purpose Port Function Pin Output Pin Function Input drive strength Description namg Output selectable TM9IOC Yes Port 0 At each port the direction and the pull up resistor BDA Yes connection is controlled individually 02 TM2IOB TM8IOC BUZB Yes At LSI reset each pin is set to input mode and the pull up resistor is not connected POS TMOIOB TM7IOC NBUZB Input Yes The drive strength of output Nch transistor can be P04
323. l interrupt input pin selection register 0 IRQISEL1 0x03F3F External interrupt input pin selection register 1 EDGDT 0x03FD4 Both edges interrupt control register NFCTR45 0x03ED2 Noise filter 45 control register IRQ5ICR 0x03FE7 External interrupt 5 control register IRQIEN 0x03F4C External interrupt input control register IRQISELO 0x03F4D External interrupt input pin selection register 0 IRQISEL1 0x03F3F External interrupt input pin selection register 1 EDGDT 0x03FD4 Both edges interrupt control register NFCTR45 0x03ED2 Noise filter 45 control register External Interrupts 33 Chapter 3 Interrupts III 34 External interrupt IRQ6ICR Address 0x03FE8 Register name External interrupt 6 control register IRQIEN 4 External interrupt control register IRQISELO 0x03F4D External interrupt input pin selection register 0 EDGDT 0x03FD4 Both edges interrupt control register NFCTR67 0x03ED3 Noise filter 67 control register External Interrupts IRQ7ICR 0x03FE9 External interrupt 7 control register KEYSEL 0x03F4F KEY interrupt input pin selection register KEYIEN 0x03F4E KEY interrupt input control register NFCTR67 0x03FD3 Noise filter 67 control register W External Interrupt Input Control Register IRQIEN bp 6 5 4 3 2 1 Chapter 3 Interrupts
324. larm0 interrupt date month minute Alarml interrupt month day hour minute Buzzer Output Inverted Buzzer Output Output frequency fgcLg 2 M 9 10 11 12 13 14 fscix 2N N 23 4 MNIOILRO2D can be used inverted buzzer output only Serial Interface 4 units Serial Interface 0 1 Full duplex UART Clock synchronous serial Function Full duplex UART Parity check Detection of overrun error framing error Selectable transfer bits of 7 or 8 Clock synchronous serial SPI compatible 2 3 or 4 wire communication MSB LSB first selectable multiple bytes transmission is available Clock Source external clock dedicated baud rate timer Serial Interface 2 3 gt Multi master IIC Clock synchronous serial Function Multi master IIC Clock synchronous serial SPI compatible 2 3 or 4 wire communication MSB LSB first selectable multiple bytes transmission is available Clock Source external clock dedicated baud rate timer Hardware Features Chapter 1 Overview MN101LR03D Serial Interface 3 Clock synchronous serial cannot be used 3 and 4 wire communication and is not compatible with SPI Chip select pin is not assigned MN101LR02D Serial Interface 1 Not implemented Serial Interface 3 Clock synchronous serial cannot be used 4 wire communication and is not compatible with SPI Chip select pin is not assigned A D Converter ADC 1 unit Resolution 12 bits Analog signal input channel 8
325. le 7 10 7 P65 Function Selection Setup Function Register LCCTR1 KEYIEN KEYSEL SCOMD1 SCO1SEL Bit name SEGSL6 KEYIBEN KEY5SEL SCOSBOS SCOSBIS SCOIOM SCOSEL1 1 SEG6 1 1 0 0 0 KEY5B 1 1 2 2 0 0 SBO0A TXD0A 0 1 1 0 0 0 0 P65 1 When serial data is output set the P6DIR P6DIR5 to 1 2 When serial data is input and output set the bit to 1 Port 6 VII 53 Chapter 7 Port Table 7 10 8 P66 Function Selection Setup Function Register LCCTR1 KEYIEN KEYSEL SCOMD1 SCO1SEL Bitname SEGSL5 KEYI6EN KEY6SEL SC0SBTS SCOSEL2 1 SEG5 1 1 0 E KEY6B 0 1 1 0 SBTOA 0 P64 1 When the LSI is the master of Clock synchronous communication set the P6DIR P6DIR6 to 1 Table 7 10 9 P67 Function Selection Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD3 SC01SEL Bit name SEGSL4 KEY7SEL SC0SBCSEN SCOSEL3 1 SEG4 1 1 0 KEY7B 0 1 71 0 SBCS0A i 0 P67 1 When the LSI outputs the chip select signal set the PeDIR P6DIR7 to 1 VII 54 Port 6 Chapter 7 I O Port 7 11 Port 7 The following table shows the special functions of Port 7 Table 7 11 1 Port 7 pin Special function P70 COM7 SEG3 IRQ6B P71 COM6 SEG2 IRQ5B P72 COM5 SEG1 IRQ4B TM3IOB P73 COM4 SEGO 5
326. lection SEG14 P45 selection SEGSL14 0 P55 0 P45 1 SEG14 1 SEG14 SEG13 P56 selection SEG13 P62 selection SEGSL13 0 P56 0 P62 Must be set to 0 1 SEG13 1 SEG13 SEG12 P57 selection SEG12 P46 selection SEGSL12 0 P57 0 P46 1 SEG12 1 SEG12 Control Registers XVII 11 Chapter 17 LCD LCD Port Control Register 3 LCCTR3 0x03E89 Bitname SEGSL27 SEGSL26 SEGSL25 SEGSL24 SEGSL23 SEGSL22 SEGSL21 SEGSL20 At reset 0 0 0 0 0 0 0 0 Access Description Bit name MN101LRO5D MN101LRO4D MN101LROSD SEG27 P40 selection SEG27 P30 selection SEG19 P30 selection SEGSL27 0 P40 0 P30 0 P30 1 SEG27 1 SEG27 1 SEG19 SEG26 P41 selection SEG26 P31 selection SEG18 P31 selection SEGSL26 0 P41 0 P31 0 P31 1 SEG26 1 SEG26 1 SEG18 SEG25 P42 selection SEG25 P32 selection SEG17 P32 selection SEGSL25 0 P42 0 P32 0 P32 1 SEG25 1 SEG25 1 SEG17 SEG24 P43 selection SEG24 P33 selection SEG16 P33 selection SEGSL24 0 P43 0 P33 0 P33 1 SEG24 1 SEG24 1 SEG16 SEG23 P44 selection SEG23 P34 selection SEG15 P34 selection SEGSL23 0 P44 0 P34 0 P34 1 SEG23 1 SEG23 1 SEG15 SEG22 P45 selection SEG22 P35 selection SEG14 P35 selection SEGSL22 0 P45 0 P35 0 P35 1 SEG22 1 SEG22 1 SEG14 SEG21 P46 selection SEG21 P36 selection SEG13 P36 selection SEGSL21 0 P46 0 P36 0 P36 1 SEG21 1 SEG21 1 SEG13 SEG20 P47 selection SEG20 P37 selection SEG12 P37 selection SEGSL20 0 P47 0 P3
327. lection register VIII 6 TM2ICR 0x03FEC Timer 2 interrupt control register III 29 TM3BC 0x03F81 Timer 3 binary counter VIII 8 TM3OG 0x03F83 Timer 3 compare register VIII 8 Timer 3 TM3MD 0x03F85 Timer 3 mode register VIII 12 CK3MD 0x03F87 Timer 3 prescaler selection register VIII 6 TM3ICR 0x03FED Timer 3 interrupt control register III 29 TM4BC 0x03F90 Timer 4 binary counter VIII 8 4 0x03F92 Timer 4 compare register VIII 8 Timer 4 TM4MD 0x03F94 Timer 4 mode register VIII 13 CK4MD 0x03F96 Timer 4 prescaler selection register VIII 7 TM4ICR 0x03FEE Timer 4 interrupt control register III 29 TM5BC 0x03F91 Timer 5 binary counter VIII 8 TM5OG 0x03F93 Timer 5 compare register VIII 8 TM5MD 0x03F95 Timer 5 mode register VIII 14 Timer 5 CK5MD 0x03F97 Timer 5 prescaler selection register VIII 7 PERI0ICR 0x03FFD Peripheral function Group 0 interrupt level control register III 24 PERIOEN OxOSFDC Peripheral function Group 0 interrupt enable register 25 PERIODT 0x03FDD Peripheral function Group 0 interrupt factor register III 26 VIII 4 8 bit Timer Control Registers 8 2 1 Chapter 8 8 bit Timer Timer Prescaler Selection Registers The timer prescaler selection registers select divided HCLK or SYSCLK as the count clock of 8 bit timer addi tion these registers control the function of PWM output with additional pulses for Timer 0 2 and 4 Timer 0 Presc
328. lf byte bit i Instruction fetch wait cycle d Data load store wait cycle max a b Execution cycle the maximum value in listed number a b is effective XX 4 W List of symbols used in flag changes flag is a general term of lower 4 bit VF NF ZF of PSW flag changes no flag changes 0 flag is always 0 l flag is always 1 Execution cycle Execution cycle may change depending on the status of the pipeline and the memory space to access Execution cycle described in this chapter is based on the following conditions The execution cycle considers the instruction fetch wait cycle and the data load store wait cycle the instruction fetch wait cycle and the data load store wait cycle depend on the resources to access Refer to LSI manual for details And it may increase by the pipeline stall instruction supply shortfall register conflict etc Refer to MN101L Series Instruction Manual for details EX 1 BSET abs8 bp Cycle 2 2d If the data access cycle is 1 d 0 then the execution cycle becomes 2 2 0 2 cycles If the data access cycle is 3 d 2 then the execution cycle becomes 2 2 2 6 cycles 2 JSR label Cycle max 2 i 442d If the instruction fetch cycle is 2 1 1 and the data access cycle is 1 d 0 then the execution cycle becomes 2 1 4 2 0 4 cycles Symbol Definitions Chapter 20 Appendix 20 2 Instruction set MN101L SERIES INSTRUCT
329. ling edge SCnSBCSEN SBCSn function selection Selectable only in Clock Synchronous communication Always set 0 in UART communication 0 Disabled 1 Enabled Chip select I O SCnSBCSLV SBCSn polarity selection Selectable only in Clock Synchronous communication Always set 0 in UART communication 0 Active low 1 Active high 0 is always read out Control Registers 17 Chapter 13 Serial Interface m SCIFn n 2 3 Mode Register 3 SC2MD3 SC3MD3 Bit name Reserved Reserved IIC3STPC IIC3TMD IIC3REX IIC3ACKS IICSACKO Initial value 0 0 0 0 0 0 0 Access Bit name Description Reserved Always set to 0 IIC stop condition generation IIC3STPC 0 None 1 Generate stop condition IIC communication mode IIC3TMD 0 Standard mode 1 High speed mode Selection of Transmission reception in master communication IIC3REX 0 Transmission mode 1 Reception mode Communication mode selection SCnCMD 0 Clock Synchronous communication 1 communication Always set 1 ACK NACK detection when IIC3REX is 0 0 ACK detected 1 NACK detected ACK NACKACK bit level selection 1 when IIC3REX is 1 0 ACK transmission 1 NACK transmission advance since IIC3STPC is cleared to 0 by hardware after the stop condition is generated To avoid rewriting a value
330. llation 4 External low speed oscillation Table 4 1 1 Clock Oscillation Circuit Figure 4 1 1 Description change Added operation enable control circuit CPUM CLKSEL Writing error correction Select clock control 0 Low speed clock SCLK 0 High speed clock HCLK Select clock control 0 Low speed clock SCLK 1 High speed clock HCLK Description addition Set the PSW MIE to 0 before chang ing the data of CPU or CKCTR Record of Changes 3 Description addition The instruction for changing the data of CPUM or CKCTR must not be exe cuted in the internal RAM Modification Ver 1 3 Page Title Line Definition Description addition Details of Revision Set the PSW MIE to 0 before chang ing the data of CPU or CKCTR Description addition The instruction for changing the data of CPUM or CKCTR must not be exe cuted in the internal RAM Specification addition 4 1 2 Change of the External Low speed Oscillation Capability Description deletion 4 2 1 Overview NORMAL Mode IDLE Mode Figure 4 2 2 Description addition When SCLKCNT SOSCCNT 1 SOSCCLK starts Figure 4 2 6 Description change Set the CPUM as described in Table 4 2 1 Set the CPUM as described in Table 4 1 3 Figure 4 2 7 Description change Figure 4 2 7 Transition Flow from RC Mode to OSC Mode Figu
331. mer starts counting up using the external interrupt input signal as a trigger A trigger of the high precision IGBT output can be selected from IRQO 1 2 or Timer 7 count operation After starting the count operation the other operation is the same as that of the 16 bit high precision PWM output lt Updating the Timer 7 preset register 1 and 2 is prohibited during IGBT operation 9 10 1 Operation m IGBT Trigger IGBT trigger can be selected from IRQO 1 2 and Timer 7 count operation by setting the TM7MD3 TM7IGBTO 1 The IGBT output starts by detecting the trigger input level When setting the TM7MD3 T7IGBTTR to 1 to select the rising edge the count operation is executed while the corresponding interrupt pin is High When setting the TM7MD3 T7IGBTTR to 0 to select the falling edge the count operation is executed while the corresponding interrupt pin is Low To control the activation with the instruction select TM7EN count operation In that case the timer count oper ation and IGBT output are controlled with the TM7MD1 TM7EN When setting the bit to 1 to start counting the count operation continues until the bit is set to 0 to stop counting Be sure to set the TM7MD3 T7IGBTO 1 before setting the TM7MD1 TM7EN In this case The setting of TM7MD3 T7IGBTTR is invalid When the counter is stopped the binary counter is cleared at the same time The data of the preset register are loaded to the compare register in synchroni
332. mode possible to occur to semiconductor products Measures on the systems such as redundant design arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury fire social damages for example by using the products 6 Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors ESD EOS thermal stress and mechanical stress at the time of handling mounting or at customer s process When using products for which damp proof packing is required satisfy the conditions such shelf life and the elapsed time since first opening the packages 7 This book may be not reprinted or reproduced whether wholly or partially without the prior written permission of our company 20100202 If you have any inquiries or questions about this book or our semiconductor products please contact our sales division PanaXSeries is a registered trademark of Panasonic Corporation The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations About This Manual mObjective The primary objective of this LSI manual is to describe the features of this product including an overview CPU basic functions interrupt port timer serial interface and other peripheral hardware functions Each section consists of brief functional information block diagrams and the
333. must not be set to BRTM_Sn_OC In Clock Synchronous communication BRTM_SCnCLK with 1 N duty must not be used as 1 a transfer clock when SCnMD1 SCnCKM is Clock Synchronous Communication 31 Chapter 13 Serial Interface W Setting of Clock Pin SBTn Figure 13 3 1 shows the relation among SBTn level at bus idle serial communication is not executed active edge of SBTn at data transmission reception and SCnMD0 SCnCE1 SCnMD3 SCnCKPH n 0 1 and SCnMD2 SCnCKPH n 2 3 Leading edge represents the first edge of square wave when communication is started Trailing edge repre sents the inverted edge of Leading edge For example when SBTn during non communication is High the first falling edge after the start of communication is Leading edge and the inverted rising edge is Trailing edge Table 13 3 1 Clock Edge of Data Transmission and Reception SBTn status during Clock edge in data 2275 Clock edge in data reception non communication transmission SCnCE1 SCnCKPH Leading edge falling Trailing edge rising Trailing edge rising Leading edge falling Leading edge rising Trailing edge falling Trailing edge falling Leading edge rising Figure 13 3 6 and Figure 13 3 7 show the 3 wire communication waveform when SCnCKPH 0 SBT pin ata is received in synchronization with the rising edge of clock SBI pin Data is sent in synchronizat
334. n The second and subsequent data transmission TXBUFn Set the next dummy data in TXBUFn Wait for communication comple tion SCnSTR SCnREMP When reception data are stored in RXBUFn SCnSTR SCnREMP is set to 1 When an interrupt is enabled a communication complete inter rupt SCnTIRQ occurs Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn Confirmation of overrun error lt SCIFn n 0 1 gt SCnSTR SCnORE SCnSTR SCnERE lt SCIFn n 2 3 gt SCnSTR SCnORE If SCnORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea Sures such as data retransmission since reception data may be destroyed SCnERE is only for SCIFn 0 1 Consecutive communication or not When continuing data transmission repeat procedures from step 3 When completing data transmission go to step 9 Reception end After the operations from step 5 to step7 are executed the communication is completed since data reception to be set in step 4 has not been completed Repeat these procedures from step 1 to execute the next com munication Clock Synchronous Communication 45 Chapter 13 Serial Interface 13 4 Full duplex UART Communication This chapter describes a full duplex UART communication The index of serial interface denotes 0 1 unless otherwise noted When communicating with U
335. n unsigned B u waw ss MULWU MOV 0x01 0x03F07 DWO DW1 DW1 DW0 Operation Multiplies the unsigned 16 bit value of DWO register by the unsigned 16 bit value of register and store the upper 16 bit of the result 82 bit in the DW1 register and the lower 16 bit of the result in the DWO register Bit Changes Size Cycles Codes VF 0 6 nibbles NF Set if the MSB of the result is 1 otherwise set to 0 4 cycles CF 0 ZF Set if the result is 0 otherwise set to 0 0000 0010 0111 0000 0001 0000 Execution of 16 bit x 16 bit multiplication unsigned 1 Store the multiplier to DWO register and the multiplicand to DW register 2 Execute MOV 0x01 0x03F07 Extended calculation macro instruction MULWU 3 The value of the unsigned 16 bit of DWO register is multiplied by the unsigned 16 bit of DW1 register Then the upper 16 bit of the result 32 bit is stored in DW1 register and the lower 16 bit is stored in DWO register This extended calculation instruction is generated by the compiler for MN101L series by Y appointing an option mmuldivw When this extended calculation instruction is executed the handy address HA is updated in Y 0x03F07 Extended Calculation Instruction 21 Chapter 2 CPU II 22 2 4 3 MULW 16 bit x 16 bit multiplication signed B aS asss T MULW MOV 0x02 0x03F07 DWO DW1 DW1 DW0
336. n Table 9 1 1 W Count Timing of Standard PWM Output at Normal TMnEN bit Compare register 1 Binary o000 0001 4 N 1 N 2 y FFFEKFFFF 0000 0001 2m N 1 counter TMnIO output PWM output p lt gt B Count time Compare registser 1 setting value 1 gt PWM basic waveform overflow time of the binary counter Figure 9 6 1 Count Timing of Standard PWM Output at Normal As for PWM output waveform A PWM output is High while the binary counter counts up from 0x0000 to the setting value of the com pare register B PWM output changes to Low when the binary counter matches the setting value of the compare register then the binary counter continues counting up until it overflows C PWM output returns to High when the binary counter overflows 16 bit Standard PWM Output with Continuously Variable Duty IX 31 Chapter 9 16 bit Timer W State at PWM Output Disabled and Polarity Timer 8 The TM8MD3 TM8PWME can control the TM8IO output waveform at PWM output disabled The polarity of PWM output can be selected with the TM8MD3 TM8PWMO W Count Timing of Standard PWM Output when compare register 1 is set to 0x0000 PUT UE TMnEN bit Compare register 1 Binary 0000 0001 0000 0001 v NH counter TMnIO output PWM output Figure 9 6 2 Count Timing of Standard PWM Output when compare regist
337. n msb Bit manipulation Instructions BSET io8 bp Dn lsb temp gt gt 1 Dn CF Dn msb temp gt CF mem8 IOTOP io8 amp bpdata PSW 1 gt 8 abs8 bp mem8 abs8 amp bpdata PSW 1 mem8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 1 gt mem8 abs16 bp BCLR io8 bp mem8 IOTOP io8 amp bpdata PSW 0 mem8 IOTOP i08 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 0 mem8 abs8 bp BCLR abs16 bp mem8 abs16 amp bpdata PSW 0 mem8 abs16 bp BTST imm8 Dm Dm amp imm8 PSW BTST abs8 bp Branch Instructions BEQ label mem8 abs16 amp bpdata PSW ZF 1 2 0 3 PC 3 d4 labelj H PC BEQ label if 2F 1 PC 4 d7 label H gt PC 2 0 PC 4 PC BEQ label 2 0 PC 5 PC BNE label if ZF 0 PC 3 d4 label H if ZF 1 5 11 gt PC ZF 1 PC43 PC BNE label if ZF 0 PC 4 d7 label H gt PC 2 1 PC 4 2 PC BNE label 2 0 5 11 PC 2 1 PC 5 gt PC BGE label if VF NF 0 PC 4 d7 label H PC I VF NF 1 PC 4 PC BGE label if VF NF 0 PC 54d1 1 label H if VF NF 1 PC 5 PC BCC label 0 PC 4 d7 label H PC BCC label BCS label BCS label if
338. n only once rewrite of each of blocks is individually counted as a rewrite count 1 30 Electrical Characteristics Chapter 1 Overview 1 5 Package Dimension Package code TQFP080 P 1212 Unit mm 1 00 4 SEATING PLANE Figure 1 5 1 80 Package Dimension Package Dimension 1 31 Chapter 1 Overview W Package code TQFP064 P 1010 12 00 0 20 10 00 0 10 32 1 25 10 00 0 10 12 00 0 20 0 50 0 20 0 05 n o S E 1 00 1 20 max SEATING PLANE 0 15 0 05 d 0 to 8 0 50 0 10_ Figure 1 5 2 64 TQFP Package Dimension 1 32 Package Dimension Unit mm aS S Chapter 1 Overview W Package code TQFP048 P 0707 Unit mm 21220 SEATING PLAN Figure 1 5 3 48 TQFP Package Dimension Package Dimension 1 33 Chapter 1 Overview Package code HQFN032 A 0505 Unit mm 5 004 0 08 E 4 0 4 I e p gt M J Die Pad Expose Figure 1 5 4 32 Package Dimension This package dimension is subject to change Before using this product obtain product spec 1 ifications from our sales offices 1 34 Package Dimension Chapter 1 Overview 1 6 Cautions for Circuit Setup 1 6 1 Usage Notes W Connection of VDD30 and VSS VDD30 and VSS pins should be connected
339. n the LSI outputs the chip select signal set the P2DIR P2DIR5 to 1 Table 7 6 8 P26 Function Selection Setup Function Register LCCTR5 SC1MD1 SC01SEL Bitname SEGSL36 SC1SBIS SC1IOM SC1SEL0 1 SEG36 1 0 0 SBI1A RXD1A 0 0 P26 7 7 Port The following table shows the special functions of Port 3 The assignment and selection of SEGn differ in each product Table 7 7 1 Port 3 pin Special function P30 SEG35 SBO1A TXD1A P31 SEG34 SBT1A P32 SEG33 SBCS1A P33 SEG32 BUZA P34 SEG31 TM4IOA TM7IOB NBUZA P35 SEG30 SBIOB RXDOB P36 SEG29 5 TXD0B P37 SEG28 SBTOB For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Registers 7 1 1 Setup of Port 3 Table 7 7 2 P30 Function Selection Setup Function Register LCCTR4 SC1MD1 SC01SEL Bit name SEGSL35 SC1SBOS SC1SBIS SC1IOM SC1SEL1 1 SEG35 11 2 72 0 SBO1A 0 1 1 TXD1A 0 0 0 P30 1 When serial data is output set the P3DIR P3DIRO to 1 2 When serial data is input and output set the bit to 1 Port 3 Chapter 7 Port Table 7 7 3 P31 Function Selection Setup Function Register LCCTR4 SC1MD1 SC01SEL SEGSL34 SCISBTS SC1SEL2 1 SEG34 1 1 0 SBT1A 0 P31 1 When the LS
340. nal interrupt 0 Timer 7 interrupt or A D conversion interrupt as the start A D conversion factor and set the ANCTR2 ANST to 0 during A D conversion and A D conversion is finished forcibly if the conversion is stopped forcibly by setting ANCTR2 ANST to 0 set the ANCTR2 ANSTSEL1 0 to 00 before setting ANCTR2 ANST If the data of ANCTRO or ANCTR1 is changed during A D conversion the operation and the result of A D conversion cannot be guaranteed Set the ANCTR ANLADE to 0 to turn the A D resistor ladder off before changing the data of ANCTRO or ANCTR1 TADCLK x 1 2 3 4 5 6 7 17 18 19 20 A D conversion clock H ANST bit 3 conversion start conversion time conversion _ end preparation t bito 80 met period Ts comparison comparison T m Samping Determine Determine Determine Determine bit 11 bit 10 bit 1 bit 0 conversion e f interrupt ADIRQ Figure 16 3 1 Operation of A D conversion sample hold time at 2 1 Before reading out the value of the A D conversion A D conversion should be done several times to prevent noise error by confirming the match of level by program or by using the average value Operation XVI 9 Chapter 16 A D Converter ADC 16 3 1 Setup c rIIF W Input Pins of A D Conversion Setup Input pins for ADC is selected by the ANCTR1
341. nal is sam pled three times and the level of it is not changed the signal can pass through NF Umm E ECC CE EN Input signal at IRQn Signal passed through NF Figure 3 3 1 Eliminating input noise at IRQn with NF NF cannot be used in STOP or HALT mode When an IRQn is used as the trigger to return Y from the STOP or HALT mode NF of the IRQn must not be used External Interrupts Ill 47 Chapter 3 Interrupts Setting example of NF The following example shows how to select the positive edge triggered IRQO at P10 and enable NF of IRQO Settings Register Description Set P10 as IRQO pin IRQIEN Set IRQIEN IRQOEN to 1 IRQISELO Set IRQISELO IRQOSEL to 0 Set P10 as the IRQO pin Select the positive edge triggered IRQOICR Set IRQOICR REDGO to 1 IRQ0 Activate NF of IRQ0 NFCTR01 Set NFCTRO1 NFOEN to 1 Set the Interrupt level of IRQ0 IRQOICR Set IRQOICR LV1 0 as you like IRQOICR IR should be set to 0 Enable IRQO IRQOICR Set IRQOICR IE to 1 a NF setting must be finished before enabling the interrupt Ill 48 External Interrupts Chapter 4 Clock Mode Voltage Control Chapter 4 Clock Mode Voltage Control 4 1 Clock Control The LSI has 4 types of clock oscillation circuits Table 4 1 1 Clock Oscillation Circuits Internal high speed oscillation circuit Max 10 MHz clock HRCCLK can be generated High speed clock is generated by con
342. nction Unsigned multiplication execution 0 Disabled 1 Enabled Chapter 2 CPU Each bit is set to 0 by hardware when calculation is finished lt Do not set several bits simultaneously Q lt Do not read AUCTR Do not access AUC TR by the bit manipulation instructions Q lt By writing the following C language you can avoid generation of data load instructions and bit manipulation instructions AUBCDSUB b 0 b D1 a A tmov 0x40 0x03F07 N c DO AUBCDSUB result in1 in2 Hu Extended Calculation Function 19 Chapter 2 CPU 2 4 Extended Calculation Instruction 2 4 1 About Extended Calculation Instruction About this Table Changes of VF NF CF ZF of PSW with change e with no change in always 0 0 in always 1 1 Instruction format 1 8 a Operation Operation descrition Size Cycles Codes Size Cycles Bit Changes Size Cycles Codes Codes the shortest are shows by using Caution Read with caution in order to operate program normally Figure 2 4 1 About this Table m Signs Addition Subtraction S Multiplication Division gt Substitution Remainder DW1 DWO 32 bit data high 16 bits DW1 register and low 16 bits DWO register are stored 20 Extended Calculation Instruction Chapter 2 CPU 2 4 2 MULWU 16 bit x 16 bit multiplicatio
343. necting crystal or ceramic oscillator to OSC1 OSC2 pins External high speed oscillation circuit Internal low speed oscillation circuit 40 kHz clock SRCCLK can be generated Low speed clock is generated by connecting crystal oscillator to XI XO External low speed oscillation circuit pins NNUS Operation Enable CPUM STOP HCLKCNT HCLKSEL OSC1 External HOSCCLK High speed osc2 AKH Oscillation eu L Internal HRCCLK x High speed Clock High speed Oscillation HCLKCNT HRCCNT CPUM OSCMOD Operation Enable CPUMSTOP Q _ 5 HSCLK HSCLK X Divider SYSCLK SCLKCNT SOSCCNT gt System Clock CPUM XIMOD Operation Enable 1 2 CPUM STOP SCLKCNT SCLKSEL Divider GoSCSTBCLK Oscillation Stabilization Clock XI gt Exema sosCCLK CPUM CLKSEL Low speed N Oscillation 4 U SCLK Internal SRCCLK x Low speed Clock Low speed Oscillation SCLKCNT SRCCNT s CPUMXIMOD CKCTR OSCSEL2 0 control the divider ratio of SYSCLK CPUM STOP _ Operation Enable Figure 4 1 1 Block Diagram of Clock Control After reset the LSI operates in SLOW mode where SYSCLK is equal to SRCCLK To lower the LSI power consumption the clock supply to the peripheral circuits can be con trolled with the 1 2 registers Fo
344. ned Vict COM Vice Vica Vss Vici SEG Vice Vica Vss Vico 1 2V icp COM SEG 0 1 2 S selected voltage non selected voltage LCD driving voltage LCD Display Examples XVII 29 Chapter 17 LCD Frame period COM1 VLCD Vici COMO Vice Vica Vss Vict SEG6 Vice Vica data Vss 1 2 electrode 0 COM1 SEG6 1 2VLcD 1 2Vicp B electrode 0 COMO SEG6 1 2 Figure 17 4 2 LCD display example in 1 2 duty XVII 30 LCD Display Examples Chapter 17 LCD 17 4 4 LCD Operation Setup 1 2 duty The following example is to display 23 on a 8 segment type LCD panel two digit display through segment pins SEGO to SEG7 and common pins COMO to COMI with 1 2 duty and 1 2 bias supplied from external volt age divider The specific details are as follows HCLK 4 MHz LCD display clock HCLK 2P 122 Hz LCD frame frequency 61 Hz Setup Procedure Description 1 Stop the LCD 1 Stop the LCD LCDMD2 0x03E82 bp7 LCEN 0 2 Set a display duty 2 Set the operation mode to 1 2 duty driving LCDMD2 0x03E82 bp2 0 LCDDTY2 0 001 3 Set a display clock 3 Select HCLK 215 as a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 4 Set Segment and common output pins 4 Sel
345. neral purpose registers The four data registers can be paired to form the 16 bit data registers DWO DO D1 and DW1 D2 D3 The initial value of Dn is 0x00 15 8 7 0 Data register Figure 2 1 1 Data Registers 2 1 3 Address Registers AO 1 These registers are used as address pointers specifying data locations The initial value of An is 0x0000 Address register Figure 2 1 2 Address Registers Overview 1 3 Chapter 2 CPU 2 1 4 Stack Pointer SP Em Uuuu U gt This register shows the top address of the stack The initial value of SP is 0x0100 15 0 Figure 2 1 3 Stack Pointer 2 1 5 Program Counter PC gt This register gives the address of the currently executed instruction and the LSB shows the half byte 4 bit infor mation The value of vector table at the address of 0 04000 is stored in PC just after the LSI reset 19 Figure 2 1 4 Program Counter 1 4 Overview Chapter 2 2 1 6 Processor Status Word PSW PSW is pushed onto the stack at interrupt occurrence and popped at returning from the interrupt service routine automatically Processor Status Word PSW bp Bit name At reset Access Bitname Description Bank function control 0 Bank addressing is enabled 1 Bank addressing is disabled Maskable interrupt enable control 0 Disable 1 Enable Interrupt mask level Controls accept level of maskable
346. ng of LSI reset Non Maskable Interrupts and Maskable Interrupts The transition time from the interrupt occurrence to interrupt handler is 6 SYSCLK cycles at a minimum and the same amount of time is needed at a minimum when returning from the interrupt handler Each interrupt has a interrupt control register hereinafter described as xICR and x is replaced with other words For example in the case of Timer 0 interrupt control register x is replaces with All interrupt control registers are described in 3 2 Control Registers which includes the interrupt request bit IR the inter rupt enable bit IE and the interrupt level bits LV 1 0 IR is set to 1 by the corresponding interrupt trigger and cleared to 0 when the interrupt is accepted IR can also be set and cleared by software IE controls the interrupt occurrence and can be set and cleared only by software IE is valid when PSW MIE is 1 NMICR the interrupt control register of NMI doesn t have IE LV1 0 control the priority level of an interrupt There is three levels of interrupt priority and the lower vector number has priority when several interrupts with the same interrupt priority level occur A maskable interrupt is accepted when LV1 0 is less than PSW IM1 0 NMI is handled in priority to maskable interrupts Overview 3 1 1 Block Diagram level deter mination IRQL
347. ng supply current DD3 MAX 3 4 mA Operating supply current 2 5 mA Specification change Operating supply current DD4 MAX 1 9 mA Operating supply current 1504 15 mA Specification change Operating supply current DD6 MAX 0 45 Operating supply current 1506 0 36 Specification change Supply current in HALT DD9 MAX 0 48 mA Supply current in HALT 1509 0 33 Specification change Supply current in STOP DD12 MAX 0 12 Supply current STOP 15012 0 24 E Recom mended Con dition of Each Pin Description change the value of which is typically between 100 O and 1000 O the value of which is typically between 1 5 kO and 100 kO Recom mendation between 10 and 100 kQ 2 1 7 Description change II 10 and 11 in 2 2 Memory Space Merged 11 10 and 11 in ever 1 2 into 2 1 7 Address Space 2 1 9 Description change 2 2 1 Bank Function 2 1 9 Bank Function 2 1 10 Description change 2 2 2 Special Function Register 2 1 10 Special Function Register Table 2 1 5 Specification change 0x03D8C Reserved in Table 2 2 2 0x03D8C CLKMD Note 2 Writing error correction When recovering from Deep STANDBY mode When recovering from SLOW HALT2 STOPO Table 4 1 1 Description change 1 Internal high speed osci
348. ng the count clock If the count clock is changed during counting the timer doesn t count correctly lt Do not change the TMnMD TMnEN simultaneously with other bits to avoid errors in opera tion lt When is read on the operation uncertain value on counting up may be read Writing the value TMnOC during counting is prohibited The sampled signal of the TMnMD TMnEN with the count clock controls start stop of the binary counter of 8 bit timer this LSI Therefore note the following two points lt To read the binary counter value after the timer has stopped set the TMnMD TMnEN to 0 wait for 1 count cycle and read the value When reading the value without waiting for 1 count cycle use the program to read the value of the binary counter multiple times In this case the read value is count value 1 II When changing the timer setting clock selection function switching etc wait for 1 count clock after setting the TMnMD TMnEN to 0 to stop the timer Then Restart the timer If the setting is switched during the timer operation the timer operation is not guaranteed When the value of timer n binary counter matches the setting value of timer n compare regis ter an interrupt request is generated at the next count clock and the timer n binary counter is cleared So set the compare register as follows Setting value of the compare register counts
349. nstruction for the transition to STANDBY mode must not be executed in the internal Mode Control Function 25 Chapter 4 Clock Mode Voltage Control IV 26 4 3 Voltage Control 4 3 1 Overview The LSI has 3 kinds of power supply voltage 1 1 V 1 3 V and 1 8 V Depending on the operating supply voltage operating frequency and target value of power consumption power supply voltage is selected and supplied to CPU the peripheral function RAM and ReRAM The relation of the output voltage VDD 18 to operating power supply voltage operating frequency and operating mode is shown in the table below Table 4 3 1 Relation of Output Voltage VDD18 to Operating Power Supply Voltage Frequency and Mode Enable Setting is prohibited i Operating mode VDD30 Maximum VDD18 9 Operating power operating HALTO 2 HALT1 3 supply range V frequency Output voltage V NORMAL SLOW STOPO STOP1 1 1 to 3 6 1 3 to 3 6 1 8 to 3 6 1 fsyscik or lt 1 MHz 2 16 kHz lt fsyscLK lt 40 kHz 32 kHz lt fecik lt 40 kHz 4 3 2 Register List Table 4 3 2 shows a list of power supply control registers Table 4 3 2 Power Supply Control Registers PWCTRO OxO3F6C R W Power supply control register 0 IV 27 PWCTR1 OxOSF6D R W Power supply control register 1 28 R W Readable Writable Voltage Control Chapter 4 Clock Mode Voltage Control 4 3 3 Power Sup
350. nterrupt control The periodic interrupt is generated every second 0 Disable 1 Enable CIRQSO5EN Periodic interrupt control The periodic interrupt is generated every 1 2 second 0 Disable 1 Enable Always read as 0 which means that RTC stops lt The periodic interrupt of 1 2 or 1 second can occur even when the RTCCTR CLKEEN is 0 must not be set to 1 lt More than one bit of the CIRQHEN the CIRQMIEN the CIRQSEN and the CIRQSO5EN 10 Control Registers Chapter 12 Real Time Clock RTC 12 2 5 Clock Registers Seconds Setting Register RTCSD Bit name At reset Access bp Bit name Description 7 Always read as 0 Second setting Set a value within the range of 00 to 59 using the BCD format The value which doesn t exist must not be set The value is incremented by one from 00 to 59 per second 6 to 0 SD6 to 0 m Minutes Setting Register RTCMID 0x03EE1 Bit name At reset Access bp Bit name Description 7 Always read as 0 Minute setting Set a value within the range of 00 to 59 using the BCD format The value which doesn t exist must not be set The value is incremented by one from 00 to 59 per minute MID6 to 0 Control Registers XII 11 Chapter 12 Real Time Clock RTC m Hours Setting Register RTCHD 0x
351. ntro oce og aem enean rH RHODE egeo eie III 20 3 2 1 Non maskable Interrupt NMI Control Register esee III 22 3 2 2 External Interrupt Control Register 23 3 2 3 Peripheral Group Interrupt Control Register n III 24 3 2 4 Other Interrupt Control Register enne entrent III 29 3 2 5 Block diagram of Peripheral function group interrupt sese 30 3 3 External InterruptfS poe e einen III 32 3 3 1 External Interrupt Control Registers sese enne III 33 3 3 2 Rising Falling edge triggered interrupt sesseseseeeeeneeeeeeeneenenenen III 45 3 3 3 Both edges triggered Interrupt nsnsi III 46 334 Key Interrupt e rare e e petu eee red III 47 3 3 5 Noise Filter Function ERREUR ERREUR iere III 47 Chapter 4 Clock Mode Voltage Control enne enne IV 1 4 T Clock no et be qe er ote epe sun ge Ee ek e IV 2 4 1 T Control Registers u aqna rre Rer e e e ied ere IV 3 4 1 2 Change of the External Low speed Oscillation Capability eese IV 12 4 2 Mode Control FUn tIoh IV 13 Contents 2 gt 4 2 1 NORMAL e rt IER ER D EH IV 15 4 22 SLOW eR me TM Mead
352. o disable a maskable interrupt set PSW MIE to 0 before a maskable interrupt for wakeup occurs In addition while CPUM STOP CPUM HALT is set to 1 CPU returns to CPU operating mode by a maskable interrupt for wakeup regardless of the value of PSW MIE The value of xICR LV 1 0 for an interrupt as a return factor needs to be smaller than the value of PSW MIE In this way even if a maskable interrupt for wakeup occurs before the transition to STANDB Y mode CPU can return to CPU operating mode by a maskable interrupt for wakeup since the interrupt is detected after the transi tion to STANDBY mode However the interrupt processing is not executed because CPU just returns to CPU operating mode in this func tion To execute the interrupt processing it is necessary to set PSW MIE to 1 after returning to CPU operating mode Figure 4 2 14 shows the operation in STANDBY mode and the acceptance sequence of interrupt while an inter rupt is disabled When not executing the interrupt processing it is necessary to set XICR IR to 0 by software Figure 4 2 15 shows the operation in STANDBY mode and the non acceptance sequence of interrupt while an interrupt is disabled NORMAL SLOW mode Enable maskable interrupts Set PSW MIE to 1 Enable interrupt which triggers return Return factor interrupt occured z Interrupt service routine Set HALT STOP Set xICR IE as the return factor
353. ock HCLK is selected as a clock source stop the timer at first After CPU operation mode has been changed start the timer again In SLOW HALT1 mode do not select high speed oscil lation clock HCLK for a clock source lt When writing data to the 16 bit preset register TMnPR1 and TMnPR2 use a 16 bit instruc tion MOVW lt 16 bit Timer IX 21 Chapter 9 16 bit Timer W Count Timing of Timer Operation Timer 7 Timer 8 and Timer 9 This is the basic operation for all functions of 16 bit timer Count clock TMnEN bit Internal enable Preset register Compare register A Binary 0000 0001 0002 0000 o001 0002 0003 counter A B E Interrupt request Figure 9 3 1 Count Timing of Timer Operation Timer 7 Timer 8 and Timer 9 A If data are written to the preset register while the count operation is disabled the TMnEN bit is set to 0 the same data are loaded to the compare register and the binary counter is cleared to 0x0000 at the next count clock B When activating the counter by setting the TMnEN bit to 1 the internal enable is set at the next count clock Then the binary counter starts counting up from the next count clock where the internal enable has been set The count operation is executed at the rising edge of the count clock e C Even if the preset register is rewritten while the count operation is enabled the TMnEN bit i
354. ock x 1 28 010 Time base selection clock x 1 29 011 Time base selection clock x 1 210 100 Time base selection clock x 1 212 101 Time base selection clock x 1 213 110 Time base selection clock x 1 214 111 Time base selection clock x 1 215 TM6CKS to 1 Timer 6 clock source select 000 HCLK 001 SYSCLK 010 SCLK 011 Setting prohibited 100 Time base selection clock x 1 213 101 Setting prohibited 110 Time base selection clock x 1 27 111 Setting prohibited TM6CKO Time base timer clock source select 0 HCLK 1 SCLK Control Registers X 7 Chapter 10 General Purpose Time Base Free Running Timer 10 3 8 bit Free running Timer 10 3 1 Operation 8 bit Free running Timer Timer 6 The generation cycle of the timer interrupt should be set in advance by selecting the clock source and setting the compare register When the binary counter TM6BC reaches the setting value of the compare register an interrupt request is generated at the next count clock and the binary counter is cleared to restart counting up from 0x00 Table 10 3 1 shows selectable clock sources Table 10 3 1 Clock Source at Timer Operation Timer 6 One count time Clock source At fici 8 MHz At fici k 4 MHz 2 MHz HCLK 125 ns 250 ns 500 ns SCLK 30 5 us SYSCLK 250 ns 500 ns 1000 ns HCLK 27 16 us 32 us 64 us HCLK 213 1024 us 2048 us 4096 us SCLK 2 3
355. of 128 sec Period of 32 sec Period of 8 sec Period of 2 sec Accuracy Period of 128 sec Period of 32 sec Period of 8 sec Period of 2 When selecting 32 768 kHz clock 488 ppmto 488 ppm 1954 ppm 1952 ppm 7813 ppm 10 7805 ppm 31250 ppm to 31220 ppm 0 48 1 92 7 63 30 52 T128HZ T64HZ T32HZ T16HZ T8HZ T4HZ T2HZ T1HZ 8 bit counter Frequency Adjustment Figure 11 1 1 RTC TBT Block Diagram XI 2 Overview Chapter 11 RTC Time Base Timer RTC TBT 11 2 Control Register Table 11 2 1 shows registers for controlling RTC TBT Table 11 2 1 Control Register Address Register Name OxOSEEA RTC TBT control register 0 RTC TBT control register 1 OxO3EEC RTC TBT register OxOSEEE RTC TBT frequency adjustment register for lower bits OxOSEEF RTC TBT frequency adjustment register for upper bits Control Register XI Chapter 11 RTC Time Base Timer RTC TBT 11 2 1 Control Register RTC TBT Control Register 0 0x03EEA o IBTRGEN 1 0 0 0 0 0 0 0 0 At reset Access R W R W R W R W R W R W R W R W Bit name Description Clock source select for RTC TBT TBTCLKSEL 0 SOSCCLK 1 SRCCLK Adjustment period select for RTC TBT 00 128 sec ADJCNT1 0 01 32 10 8sec 11 2 sec Always read as 0
356. of IIC3STPC be sure not to set the SCnMD3 n 2 3 with read modify write instructions such as BSET or BCLR lt The readout value of IIC3STPC can be different from the value that is written to the bit in lt 1 When reception mode IIC3REX bit 1 cannot be read out XIII 18 Control Registers 13 2 6 Status Register See rm F m SCIFn 0 1 Status Register SCOSTR SC1STR Chapter 13 Serial Interface Bit name SCnTBSY SCnRBSY SCnTEMP SCnREMP SCnFEF SCnPEK SCnORE SCnERE Initial value 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit name SCnTBSY Data transmission state 0 IDLE 1 During transmission Description SCnRBSY Data reception state 0 IDLE 1 During reception SCnTEMP Transmission data buffer empty detection 0 Detected 1 Not detected SCnREMP SCnFEF Reception data buffer empty detection 0 Detected 1 Not detected UART frame error detection 0 Not detected 1 Detected SCnPEK UART parity error detection 0 Not detected 1 Detected SCnORE Overrun error detection 0 Not detected 1 Detected SCnERE Error detection 0 Not detected 1 Detected Control Registers XIII 19 Chapter 13 Serial Interface m SCIFn n 2 3 Status Register SC2STR SC3STR Bit name SCnTBSY SCnTEMP SCnREMP Initial value Access Bit name Descrip
357. oise Filter 67 Control Register NRCTR67 bp 7 6 5 3 2 1 Bit name NF7SCK2 NF7SCK1 NF7SCK0 NF6SCK2 NF6SCK1 NF6SCK0 At reset 0 0 0 0 0 0 Access Bit name NF7SCK2 NF7SCK1 NF7SCK0 Description IRQ7 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 219 111 fscLK IRQ7 noise filter operation 0 Disabled 1 Enabled NF6SCK2 NF6SCK1 NF6SCK0 IRQ6 noise sampling frequency 000 001 29 010 1 26 011 27 100 29 101 29 110 219 111 fscLK External Interrupts IRQ6 noise filter operation 0 Disabled 1 Enabled m KEY Interrupt Input pin Selection Register KEYSEL bp 7 6 5 4 3 2 1 Chapter 3 Interrupts 0 Bit name KEYSEL7 KEYSEL6 KEYSEL5 KEYSEL4 KEYSEL3 KEYSEL2 KEYSEL1 KEYSELO At reset 0 0 0 0 0 0 0 0 Access Bit name KEYSEL7 KEY7 pin selection 0 KEY7A P17 1 KEY7B P67 Description KEYSEL6 KEY6 pin selection 0 KEY6A P16 1 KEY6B P66 KEYSEL5 KEY5 pin selection 0 KEY5A P15 1 KEY5B P65 KEYSEL4 KEY4 pin selection 0 KEY4A P14 1 KEY4B P64 KEYSEL3 KEYS pin selection 0 KEYSA P13 1 KEY3B P57
358. on between each operation mode Figure 4 2 1 Writing error correction NORMAL mode SCLK oscillation HALTO mode SCLK oscillation NORMAL mode SCLK oscillation stop HALTO mode SCLK oscillation stop Description addition 2 3 Note Description addition Do not perform the transition that is not listed in Figure 4 2 1 Figure 4 2 5 Description addition Internal high speed oscillation stabili zation wait time Internal high speed oscillation stabili zation wait time 15 us Figure 4 2 8 Description addition Internal low speed oscillation stabiliza tion wait time 80 us Internal low speed oscillation stabiliza tion wait time 100 us Voltage Transition Program Setting example Description change Merged with 30 in Ver1 4 Voltage Transition Mode Transi tion Setting example Description change Merged with 30 in Ver1 4 4 4 Description addition 4 4 Mode Voltage Clock Transition 11 2 3 Description addition Frequency adjustment rate x 0x200000 in hexadecimal Frequency adjustment rate x 0x200000 in hexadecimal At Adjust ment period 128 sec Hint Description addition During the A D conversion if the out put level of LSI is changed Note Description deletion Be sure to conduct the following proce dures to ensure Figure 16 3 5 Description deletion Figure 16 3 5 Re
359. on control register POPLUP POODC 0x03F40 0x03F50 Port 0 pull up resistor control register Port 0 N ch open drain control register PONLC Port 0 N ch current capacity selection register P1OUT 0x03F11 Port 1 output register P1IN 0x03F21 Port 1 input register P1DIR 0x03F31 Port 1 direction control register P1PLUP 0x03F41 Port 1 pull up resistor control register P1ODG 0x03F51 Port 1 N ch open drain control register P2OUT 0x03F12 Port 2 output register 0x03F22 Port 2 input register P2DIR 0x03F32 Port 2 direction control register P2PLUP 0x03F42 Port 2 pull up resistor control register P2NLG 0x03EC1 Port 2 N ch current capacity selection register P3OUT 0x03F13 Port 3 output register P3IN 0x03F23 Port 3 input register P3DIR 0x03F33 Port 3 direction control register P3PLUP 0x03F43 Port 3 pull up resistor control register P3ODG 0x03F53 Port 3 N ch open drain control register P3NLG 0x03EC2 Port 3 N ch current capacity selection register P4OUT 0x03F14 Port 4 output register P4IN 0x03F24 Port 4 input register P4DIR 0x03F34 Port 4 direction control register P4PLUP 0x03F44 Port 4 pull up resistor control register P4ODG 0x03F54 Port 4 N ch open drain control register P4NLG 0x03EC3 Port
360. ore the DMCTRIL DMTEN is set to 1 by software for example the period B in the Figure 14 3 1 DMA AddReq interrupt occurs If the DMA start trigger happens during the time after the DMA start trigger occurs and before DMA reads the data not limited to the last single data from Source Address for example the period A in the Figure 14 3 1 DMA Error interrupt occurs DMCNTH 3 X 2 X 1 0 N DMCNTL h i DMA gt DMA lt gt DMA Period A DMA start trigger Period A start trigger Period A start trigger interrupt Period B i of DMCTR1L Set the DMTEN to 1 by software for next DMA When DMA interrupt occurs the DMTEN is cleard to 0 by hardware Figure 14 3 1 Example of Single Transfer XIV 12 DMA Data Transfer Chapter 14 DMA Controller 14 32 Burst Transfer Mode When DMA start trigger occurs data the size of which is decided with DMCTROH DMUT is transferred in single burst until the data transfer counter consisting of DMACNTH and DMACNTL are decremented to zero When all the data transfer finishes DMA interrupt occurs If the DMA start trigger happens during the time after DMA reads the last burst data from Source Address and before the DMCTRIL DMTEN is set to 1 by software for example the period B in the Figure 14 3 2 DMA AddReq interrupt occurs If the DMA start trigger happ
361. ort 8 pull up resistor control register VII 17 SC01SEL 0x03F1C SCIFO1 I O pin control register XIII 9 SC23SEL OxOSF1D SCIF23 I O pin control register XIII 9 TMIOENO OxOSF2C 8 bit timer output control register VII 25 TMIOSELO OxOSF2D 8 bit timer input output pin selection register VII 26 1 0x03F2E 16 bit timer output control register VII 27 TMIOSEL1 0x03F2F 16 bit timer input output pin selection register VII 28 CLKOUT 0x03F3E Clock output control register VII 29 IRQIEN 0x03F4C External interrupt input control register 111 35 IRQISELO 0x03F4D External interrupt input pin selection register 0 111 36 IRQISEL1 0x03F3F External interrupt input pin selection register 1 11 37 KEYIEN Ox03F4E KEY interrupt input control register III 44 KEYSEL 0x03F4F KEY interrupt input pin selection register III 43 ANEN0 0x03F5C Analog input control register 0 Port 1 VII 30 ANEN1 0x03F5D Analog input control register 1 Port 8 VII 31 BUZCNT 0x03F5F Buzzer output control register VII 32 LCCTR0 0x03E86 LCD output control register 0 XVII 9 LCCTR1 0x03E87 LCD output control register 1 XVII 10 LCCTR2 0x03E88 LCD output control register 2 XVII 11 LCCTR3 0x03E89 LCD output control register 3 XVII 12 LCCTR4
362. oscillation disabled 1 High speed oscillation enabled Select clock control CLKSEL 0 Low speed clock SCLK 1 High speed clock HCLK Set the CPUM in one of states described in Table 4 1 2 lt Any other value which is not described in the Table 4 1 2 must not be set to the CPUM The LSI has the following function to prevent malfunction m HALT 0 CLKSEL 1 and OSCMOD 0 is not be valid CLKSEL 0 and XIMOD 0 is not valid STOP 1 and HALT 1 is not valid OCDMOD 0 and XIMOD 0 is not valid Set the PSW MIE to before changing the data of CPU or CKCTR Y Insert 3 NOP instructions right after the instruction for changing CPUM or CKCTR a The instruction for changing the data of CPUM or CKCTR must not be executed in the inter nal RAM V 4 Clock Control Chapter 4 Clock Mode Voltage Control Table 4 1 3 Operating Mode Control and Clock Oscillation Status CPUM Clock and CPU Status Operation mode HALTMOD XIMOD OSCMOD CLKSEL SCLK System clock Stop Active ane NORMAL Active IDLE Active Active Active SLOW Stop Active Active Stop HALTO Active Active Stop HALT1 Stop Active Stop HALT2 Stop Active Stop HALT3 Stop Active Stop STOPO Stop Stop Stop STOP1 Stop Stop Stop For the setting procedure of mode transition refer to 4 2 Mode Control Function Clock Control 5
363. ot accepted during NMI handler After RTI instruction NMI 2 is accepted If the undefined instruction occurs the following processing is not guaranteed 2 If the request of NMI 1 is not cleared NMI 1 is accepted again after RTI instruction Figure 3 1 8 Processing Sequence for Non Maskable Interrupt 14 Overview 3 1 3 W Setting xICR IR by software Maskable Interrupt Control Register Setup is set to 1 when the interrupt trigger occurs and cleared to 0 by hardware when the interrupt is accepted To operate IR by software MEMCTR IRWE needs to be set to 1 interrupt Control Register Setup Procedure Setup procedures of xICR of maskable interrupt is described below Setup Procedure Description 1 Disable all maskable interrupts PSW MIE 0 2 Select the interrupt factor 3 Permission settings of multiple interrupt MEMCTR MIESET 4 Enable the write interrupt request bit MEMCTR IRWE 1 5b Rewrite the interrupt request bit xICR IR 6 Disable the write interrupt request bit MEMCTR IRWE 0 7 Set the interrupt level xICR LV1 0 PSW IM1 0 8 Enable the interrupt xICR IE 1 9 Enable all maskable interrupts PSW MIE 1 Clear PSW MIE to disable all maskable interrupts which is needed especially before xICR is changed Select the interrupt factor such as interrupt edge selection or timer interrupt cycle change Set the permission of multiple interru
364. placement 11 bits Displacement 12 bits Displacement 16 bits Bit position to 7 8 bit data whose bp bit contains 1 when bp is 0 b 00000001 when bp is 1 b 00000010 when bp is 7 b 10000000 Bit position to 19 Bit position LSB Bit position MSB Displacement within the special function register area 0 to 255 03 00 Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Bit inversion n bit shift left n bit shift right Overflow flag Negative flag Carry flag Zero flag Temporary register Move Remainder Reflection of the operation result Address Memory used for general meaning 8 bit data the memory specified by xxx Symbol Definitions Chapter 20 Appendix XX 3 Chapter 20 Appendix mem16 xxx 16 bit data in the memory specified by xxx sign xxx Sign extended data of xxx zero xxx Zero extended data of xxx d4 label 4 bit displacement between PC and label 16 to 15 nibbles d7 label 7 bit displacement between PC and label 128 to 127 nibbles d11 label 11 bit displacement between PC and label 1024 to 1023 nibbles d12 label 12 bit displacement between PC and label 2048 to 2047 nibbles d16 label 16 bit displacement between PC and label 65536 to 65535 nibbles RPC Repeat counter H Ha
365. ply Control Register Rl s O A Power Supply Control Register 0 PWCTRO 0x03F6C The power supply control register 0 controls the switching Vppig output of the power supply generation circuit bp 7 6 5 4 3 2 1 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved VDDLV1 VDDLV0 Initial value 1 0 0 0 0 0 0 0 Access Bit name Description Always set to 000000 Reserved If the value other than 0 is set this register value is not updated Select output voltage VDD18 00 1 1 V VDDLV1 0 01 1 3 V 10 1 8 V 11 Setting is prohibited Insert 3 NOP instructions right after the instruction to change VDD18 write instruction to the PWCTRO VDDLV1 0 When using the instruction to change VDD18 disable the transfer function lt PWCTRO register can be update only in SLOW mode of VDD18 can changed to match the following conditions 1 1 V to 1 8 V or 1 8 V to 1 1 V 1 1 V to 1 3 V or 1 3 V to 1 1 V The voltage of VDD18 must not be changed in the following conditions 1 3 V to 1 8 V or 1 8 V to 1 3 V Voltage Control IV 27 Chapter 4 Clock Mode Voltage Control IV 28 Power Supply Control Register 1 PWCTR1 0x03F6D The power supply control register 1 controls CPU outage when changing the output voltage VDD18 and Deep STAN
366. ply current STOP After setting the Logic supply voltage to 1 1 V and the oscillation mode to STOP fix the input pins to level and make 5 1 and XI pins open C1 C5 MN101LRO02D is not applicable Electrical Characteristics 1 25 Chapter 1 Overview Vpp3o Vast to 3 6 V Vss 0 V 1 1 V at auto reset function Ta 40 C to 85 C Parameter Symbol Condition US Unit MIN TYP MAX Input pin 1 NATRON C15 High level input voltage Vint 0 8Vpp30 Vppso C16 Low level input voltage 0 0 2Vpp30 C17 Input leakage current Vi OV to 1 Input 2 DMOD C18 High level input voltage Vin2 0 8Vpp30 C19 Low level input voltage Vio 0 0 2Vppao C20 Pull down resistance 3 0 V Vi 30 100 300 Input Output pin 3 P10 to 17 P80 to P85 Schmitt input C21 High level input voltage Ving 0 8Vppao Vppso C22 Low level input voltage 0 0 2Vpp30 C23 Input leakage current V 0V to ES ES 1 24 Pull down resistance IRH3 21 2 30 100 300 C25 output Voms Vpp3o 3 0 Vlogs 2d mA 24 x C26 2 output Vois Vppao 3 0 V 10 2 0 mA 0 4 Input Output 4 POO to P07 P20 to P26 P30 to P37 P40 to P47 P50 to P57 P
367. priate Y measures to make the LSI operate normally should be taken V 2 Overview Chapter 5 Watchdog Timer WDT 5 2 WDT Control Register 5 2 1 WDT Control Register WDT Control Register WDCTR 0x03F02 Bitname WDCKSEL At reset 0 Access Bit name Description Select watchdog time clock source WDCKSEL 0 SRCCLK 1 SOSCCLK Always read as 0 Watchdog error detect period setup 000 2 1 001 28 x 1 wDTCLK 010 2 x 1 wDTCLK 011 2 x 1 100 212 x 1 wDTCLK 101 214 x 1 110 216 x 1 111 218 x 1 fwpreui WDT enable control 0 Disable 1 Enable The WDCKSEL must be changed when the WDEN is 0 WDT starts operation by setting Y the WDEN to 1 and the WDEN is not cleared except when the LSI is reset WDT Control Register V 3 Chapter 5 Watchdog Timer WDT V 4 5 3 Operation 5 3 1 WDT Operation WDT Counter needs to be cleared periodically to avoid WDT overflow WDT Counter is cleared by writing something the WDCTR WDT generates WDIRQ when WDT Counter is not cleared during the error detect period and overflows WDT counter should be cleared with BSET instruction for example BSET WDCTR 0 to avoid changing the error detection time etc unintentionally Operation Chapter 5 Watchdog Timer WDT 5 3 2 Setup Example The following
368. procedure shows the example of WDT operation SRCCLK is selected as WDCLK and the error time period is 218 x 1 fwpTCLE Setup Example Set the error detection period WDCTR Set the WDCKSEL to 0 Set the WDTS2 0 to 111 Activate WDT WDCTR Set the WDEN to 1 Setup Example 1 Clear WDT Counter WDCTR Clear WDT counter before it overflows m Setup Example Handling interrupt NMICR WDIRQ is generated when WDT Counter overflows Check that NMICR IRQNWDG is set to 1 and take appropri ate measures to make the LSI operate normally again Refer to Chapter 3 Interrupts about NMICR Operation V 5 Chapter 5 Watchdog Timer WDT V 6 Operation Chapter6 Power Supply Voltage Detection 6 Chapter 6 Power Supply Voltage Detection 6 1 Overview 6 1 1 Power Supply Voltage Detection Overview This LSI has the power supply voltage detector PSVD to detect power supply voltage and generate interrupt PS VD compares the power supply voltage and the detection voltage Vj yj and generates the interrupt LVIIRQ when the level of Vppao crosses that of Vr vr be changed between from 1 1 V to 2 9 V with the LVICTRO register PSVD operates regardless of the value of the CPU control register Power supply voltage Vpp3o VLVI 4 LVION bit LVIOUT bit Interrupt reques
369. pt Multiple interrupt is allowed when MIESET is set to 1 Set MEMCTR IRWE to enable IR to be rewritten which is needed only when IR is changed by software Rewrite xICR IR Clear the bit with this method because it may already be set Disable IR setting by software Set the interrupt level of xICR and PSW IM1 0 Set xICR IE to enable the interrupt Enable all maskable interrupts Overview Chapter 3 Interrupts Ill 15 Chapter 3 Interrupts xICR IR is set when the corresponding interrupt occurs or the edge switching of the interrupt is done regardless of the value of xICR IE Clear IR to 0 following the setup procedures 4 to 6 Before operating set PSW MIE to 0 There s no guarantee of proper operation when writing to xICR while PSW MIE is 1 Always set MEMCTR IRWE to 0 except when writing xICR IR by software The interrupt request may be cleared when operating xICR by software while the MEM CTR IRWE is 1 For example when the bit operation to xICR is executed xICR is read modified and overwritten by CPU the interrupt request which occurs during the above read to write cycle is cleared because IR is overwritten with 0 by software To avoid this set MEMCTR IRWE to 0 which prevent the interrupt missing by software Before setting MEMCTR MIESET set PSW MIE to 0 There s no guarantee of proper oper ation when writing to MEMCTR MIESET while PSW MIE is
370. pty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR SCnTEMP becomes 0 since communica tion starts Data write to TXBUFn The second and subsequent data transmission TXBUFn Set the next transmission data in TXBUFn Wait for communication comple tion SCnSTR SCnREMP When reception data are stored in RXBUFn SCnSTR SCnREMP is set to 1 When an interrupt is enabled a communication complete inter rupt SCnTIRQ occurs Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn Confirmation of overrun error lt SCIFn n 0 1 gt SCnSTR SCnORE SCnSTR SCnERE lt SCIFn n 2 3 gt SCnSTR SCnORE If SCnORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take measures such as data retransmission since reception data may be destroyed SCnERE is only for SCIFn n 0 1 Consecutive communication or not When continuing data transmission repeat procedures from step 3 When completing data transmission go to step 9 Transmission reception end Clock Synchronous Communication After the operations from step 5 to step7 are executed the com munication is completed since data reception to be set in step 4 has not been completed Repeat these procedures from step 1 to execute the next com munication Setting Empty confirmation of transmis sion buffer Register n
371. pulses can be added in 4 cycles of the basic PWM waveform Where to place or not to place additional pulses during 4 cycles of the basic PWM waveform 1 controlled by set ting CKnMD TMnADD1 0 Figure 8 6 5 shows the setting value of CKnMD TMnADD1 0 and the location of additional pulses PWM basic waveform 4 cycles I I PWM basic waveform 8bit 256 resolution l CKnMD TMnADD1 0 90 L No additional pulse Interrupt request additional pulse PWM basic waveform 11256 pulse width i 0 additional pulse I additional pulse During 4 cycles of the PWM basic waveform additional pulses 1 256 pulse width of PWM basic waveform can be added in any of the cycles 0 to 3 Figure 8 6 5 Count timing of PWM Output with Additional Pulses Method An interrupt occurs at the 4th cycle of the PWM basic waveform 28 8 PWM Output Chapter 8 8 bit Timer 8 Simple Pulse Width Measurement 8 7 1 Operation Timer 0 Timer 2 and Timer 4 m Simple Pulse Width Measurement Operation
372. put control register 0 R W Readable Writable R Read only XVI 4 Control Registers Chapter 16 A D Converter ADC 16 2 2 Control Registers m A D Control Register 0 ANCTRO 0x03F60 Ce tests 0 0 0 0 0 0 0 0 At reset Access R W R W R W R W R W R W R R Bit name Description Sample hold time 00 TADCLK x2 01 TADCLK x6 10 TADCLK x 18 11 Prohibited A D conversion clock ADCLK 000 SYSCLK 2 001 SYSCLK 3 010 SYSCLK 4 011 SYSCLK 6 100 SYSCLK 8 101 SYSCLK 12 110 SYSCLK 16 111 SCLK as 750 ns lt lt 100 us A D resistor ladder control ANLADE 0 A D resistor ladder OFF 1 A D resistor ladder ON Always read as 0 Control Registers XVI 5 Chapter 16 A D Converter ADC m Control Register 1 ANCTR1 0x03F61 Bit name ANCHS2 0 At reset 0 Access 7 3 Always read as 0 Analog input channel 000 AN0 pin 001 AN1 pin 010 AN2 pin ANCHS2 0 011 AN3 pin 100 AN4 pin 101 AN5 pin 110 AN6 pin 111 AN7 pin m Control Register 2 ANCTR2 0x03F62 Bit name At reset Access bp Bit name Description A D conversion status 0 Finish Stop 1 Start Converting ANSTSEL1 0 A D conversion starting factor selection 00 Setting ANST bit to 1
373. put pin with ANENO IRQOA IRQOB Input External interrupt input pins IRQ1A IRQ1B Select the external interrupt pin with IRQIEN IRQISELO and IRQISEL1 IRQ2A IRQ2B IRQSA IRQSB IRQ4A IRQ4B IRQ4C IRQSA IRQSB IRQSC IRQ6A IRQ6B Input Key interrupt input pins KEY1A KEY1B Select the key interrupt pin with KEYIEN and KEYSEL KEY2A KEY2B KEY4A KEY4B KEY5A KEY5B KEY6A KEY6B KEY7A KEY7B COMn n 0 to 7 Output LCD common output pins 1 18 Select the common output with LCCTRn Pin Description Chapter 1 Overview Input Output Description SEQGn n 0 to 42 Output LCD segment output pins Select the segment output pin with LCCTRn BUZA BUZB Output Buzzer output pin Select the buzzer output pin with BUZCNT NBUZA NBUZB Output Inverted Buzzer output pin Select the inverted buzzer output pin with BUZCNT CLKOUTA CLKOUTB Output Clock output pins Select the clkout pin with CLKOUT OCD_CLK Input On board debugger pins OCD_DATA Output These pins are used for on board debugging Pin Description 1 19 Chapter 1 Overview 1 20 1 4 Electrical Characteristics 1 4 1 Absolute Maximum Ratings A Absolute Maximum Ratings 2 3 Vss 0 V Parameter Symbol Rating Unit A1 Supply voltage Vppao 0 3 to 4 6 V A2 Input pin voltage VI
374. put signal 11 Timer Interrupt 16 bit Timer Control Registers IX 11 Chapter 9 16 bit Timer W Timer 7 Mode Register 3 TM7MD3 0x03FBE Bit name T7IGBTTR T7IGBTDT T7IGBTEN At reset 0 0 0 0 Access Bit name Description Select sampling clock for capture TM7CKSMP 0 Count clock 1 SYSCLK Always read as 0 Select count edge of TM7IO TM7CKEDG 0 Falling edge 1 Both edges Select trigger level T7ZIGBTTR 0 High 1 Low Input timing of IGBT dead time T7IGBTDT 0 Falling edge 1 Rising edge IGBT enable T7IGBTEN 0 Disabled 1 Enabled Select IGBT Timer activation source 00 Timer 7 count operation T7IGBT1 0 01 External Interrupt 0 input signal 10 External Interrupt 1 input signal 11 External Interrupt 2 input signal TM7MD3 T7IGBTEN 0 lt When IGBT output operation is not used set the following TM7MD3 T7IGBT1 0 00 a WHen the capture function is not used set the TM7MD3 TM7CKSMP to IX 12 16 bit Timer Control Registers Chapter 9 16 bit Timer W Timer 7 Mode Register 4 TM7MD4 0x03F9E Bit name T7NODED T7ICT2 At reset 0 0 0 0 Access Bit name Description Always read as 0 Select pulse T7ONESHOT 0 Continuous pulse 1 One shot pulse Set dead time T7NODED 0 Yes 1 No Always read as 0 Select capture trigger T7ICT2 0 Timer
375. r sess VII 32 T3 W O Port Functions ete te queden qam drei eet VII 33 JAEPOREQ S ies humos uerunt a Ra VII 34 TAL Setup of POLE Jure reete tree etr een aborder mS S EE redes VII 34 7 9 Port titio abel VII 37 Tod Setup ob Port uu nte paced m debe ie deo menm qd 37 T 6 Pott 40 7 6 Setup OL pisqu aaa 40 TEP ROLE u human anush asahan asas waslpas e 43 7 7 1 Setup of VII 43 7 8 POEt A io UE due uaa meet ah dus VII 46 7 8 1 Setup of Port VII 46 7 9 POERES 4 iacet t Se E es VII 49 7 9 Setup of eme vega eee Sh Dua usual s VII 49 TAO Port 6 25 n tes S bebe annui aa ioe a phan ERES 52 Setup of Porto eere ueni enar edel eh EPI VII 52 TIL tel ae ek ERES EHI ECHANGES VII 55 TAL Setup of Shukusyasqhakaqayqhuyssuqapisaya VII 55 712 VII 58 7 12 1 Setup Of Port 8 rr eee ee ae VII 58 Chapter 8 8 Dit TIMET sasaqa qasisqa asas 1 SOV OLVICW E CE 2 FAN eei 2 8 1 2 8 bit Timer Block Diagram 3 8 2 8 bit Timer Control Registers 4 8 2 1 Timer Prescaler Selection Registers 5 8 2 2 Programmable Timer Registers
376. r rupt SCnTIRQ occurs Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn Confirmation of overrun error lt SCIFn n 0 1 gt SCnSTR SCnORE SCnSTR SCnERE lt SCIFn n 2 3 gt SCnSTR SCnORE If SChORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea sures such as data retransmission since reception data may be destroyed SCnERE is only for SCIFn n 0 1 Transmission reception end m Data Transmission 1 byte Communication Mode Setting Register name Empty confirmation of transmis SCnSTR SCnTEMP sion buffer Repeat these procedures from step 1 to execute the next com munication Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn TXBUFn Set transmission data in TXBUFn Wait for communication comple tion lt SCIFn n 0 1 2 3 gt SCnSTR SCnTBSY lt SCIFn n 0 1 2 3 gt When the communication has been completed SCnTBSY becomes 0 When an interrupt is enabled a communication complete inter rupt SCnTIRQ occurs Transmission end Repeat these procedures from step 1 to execute the next com munication Clock Synchronous Communication XII 43 Chapter 13 Serial Interface W Data Reception 1 byte Communication Mode Setting Empty confirmation of transmis sion buffer Register name SCnSTR SCnTEMP Descrip
377. r BRTMn with BRTM S CKSEL S01 CK and 523 CK When BRTM S EN BRTM Sn EN is set to 1 the binary counter of BRTMn BRTM Sn starts counting up When Sn BC becomes equal to Sn OC BRTM Sn BC is cleared at the next count clock and restarts counting up While the duty of BRTM SCnCLK is 1 1 BRTM 5 MD BRTM Sn MD is 0 the cycle and operation of BRTMn are shown in the figure below BRTM SnCLK Cycle 2 x N 1 x Count Clock Cycle N Setting value of BRTM Sn OC BRTN Sn BC 800 BRTM_SncLK T Figure 13 3 1 BRTMn Count Operation Duty 1 1 Count Clock HCLK 0x00 Figure 13 3 2 BRTMn Count Operation Duty 1 1 Count Clock HCLK N 0x01 Clock Synchronous Communication Chapter 13 Serial Interface While the duty is 1 N BRTM_S_MD BRTM_Sn_MD 1 the cycle and operation of BRTMn are shown in the figure below BRTM_SnCLK Cycle N 1 x Count Clock Cycle N Setting value of BRTM_Sn_OC The setting of N 0x00 is disabled Figure 13 3 3 BRTMn Count Operation Duty 1 N Count Clock HCLK N 0x01 Hek 8 P Il Il syscek J I LT LI LI LI l f LIT L BRIMSn EN BRTN_Sn_BC 8 h00 BRTM LD Figure 13 3 4 BRTMn Count Operation Duty 1 N Count Clock HCLK 4 0x01 Figure 13 3 5 BRTMn Count Operation Duty 1 N Count Clock HCLK N 0x03 lt When the duty is 1 N the value of 0x00
378. r Control Register POPLUP 0x03F40 aa Rae NE SS il Bit name POPLU7 0 At reset 0 0 0 0 0 0 0 0 aw aw m e Pull up resistor selection 7 0 POPLU7 O 0 Not added 1 Added m Port1 Pull up Resistor Control Register P1PLUP 0x03F41 ce ee ee JU a At reset Access m sme Pull up resistor selection 7 0 P1PLU7 0 0 Not added 1 Added Port 2 Pull up Resistor Control Register P2PLUP 0x03F42 Bit name P2PLU6 0 At reset 0 0 Access Always read as 0 Pull up resistor selection P2PLU6 0 0 Not added 1 Added Control Registers VII 15 Chapter 7 Port Port 3 Pull up Resistor Control Register 0x03F43 Bit name At reset Access me mmm Pull up resistor selection 7 0 P3PLU7 0 0 Not added 1 Added m Port 4 Pull up Resistor Control Register PAPLUP 0x03F44 Bit name At reset Access m mme Pull up resistor selection 7 0 P4PLU7 0 0 Not added 1 Added m Port 5 Pull up Resistor Control Register PSPLUP 0x03F45 Bit name At reset Access 89 sme Pull up resistor selection P5PLU7 0 0 Not added 1 Added VII 16 Control Registers Chapter 7
379. r example if Timer 0 is not used the clock supply to Timer 0 is stopped by setting the PRICKCNTO PRICKCNTOO to 2 Clock Control Chapter 4 Clock Mode Voltage Control 4 1 1 Control Registers Table 4 1 2 shows control registers of clock control functions Table 4 1 2 Clock Control Registers Address Register name CPUM 0x03F00 R W CPU mode control register IV 4 CKCTR 0x03F04 R W System clock control register IV 6 HCLKCNT 0x03F05 R W High speed oscillation clock control register IV 7 SCLKCNT 0x03F06 R W Low speed oscillation clock control register IV 8 0x03E10 R W Clock supply control register 0 IV 9 PRICKCNT1 0x03E11 R W Clock supply control register 1 10 2 0 03 1 2 R W Clock supply control register 2 IV 11 R W Readable Writable Clock Control Chapter 4 Clock Mode Voltage Control m CPU Mode Control Register CPUM 0x03F00 bp 3 1 0 Bit name HALTMOD OSCMOD CLKSEL Initial value 0 0 0 0 Access Bit name Description Always read as 00 STOP mode request 0 not STOP mode 1 STOP mode HALT mode request 0 not HALT mode 1 HALT mode HALT1 HALT3 mode control HALTMOD 0 Go to HALT1 mode 1 Go to HALT3 mode Low speed oscillation control 0 Low speed oscillation disabled 1 Low speed oscillation enabled High speed oscillation control OSCMOD 0 High speed
380. r of 0 22 uF to VLC2 VLC3 and C2 For more details refer to 17 3 4 LCD Drive Voltage Selection XVII 18 Operation Chapter 17 LCD 17 3 4 LCD Drive Voltage Selection LCD drive voltage can be generated with one of the three method described in Table 17 3 1 Table 17 3 1 LCD Drive Voltage Supply Method Method of generating LCD drive voltage Description 1 Generate the drive voltage Supply the voltage generated outside of the LSI to VLC1 VLC2 outside the LSI and VLC3 Generate the drive voltage lt 2 or 3 times boosting gt with BSTVOL Supply the reference voltage V to VLC3 The reference voltage is supplied 2 times higher voltage of Vi is output from VLC2 from outside of the LSI 3 times higher voltage of VI is output from VLC1 lt 1 2 or 3 2 times boosting 1 3 bias gt 2 Supply the reference voltage Vi c to VLC2 1 2 times lower voltage of Vi c is output from 3 2 times higher voltage of VI c is output from lt 2 times boosting 1 2 bias gt Supply the reference voltage Vico to VLC2 and VLC3 2 times higher voltage of Vi c is output from Generate the drive voltage No need to supply voltage from outside of the LSI with BSTVOL The reference voltage is generated with REFVOL The supply voltage to VLC1 Vi c4 must be kept between and 3 6 V 1 Vppao lt Vici lt 3 6 Operation
381. r operation instruction register direct and immediate be used All of the addressing modes be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit Increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed There 3 instructions that can use this mode MOV Dn HA MOVW DWn MOVW An HA Combining handy addressing with absolute addressing reduces code size For transfer data between memory 8 addressing modes register indirect register relative indirect stack relative indirect absolute RAM short I O short handy can be used Refer to IMN101L Series Instruction Manual Overview CPU 1 9 Chapter 2 CPU Higher 4 bit of data access Addressing Modes Effective address Description address when bank addre ssing is enabled Dn DWn Directly specifies the register Only internal registers can Register direct An SP be specified PSW imm4 imm8 Directly specifies the operand or mask value appended imm16 to the instruction code An Specifies the address using an address register The value of SBNKR or DBNKR Specifies the address using an address register with 8 The value of SBNKR An d bit displacement or DBNKR Specifies the address using an address register with 16 value of SBNKR An 916 bit displacement or DBNKR Specifies the address using the prog
382. r output control Register TMIOENO 0x03F2C Bit name TM5OEN TM4OEN TM3OEN TM2OEN TM1OEN TMOOEN At reset 0 0 0 0 dese LOT Bit name Description Always read as 0 Select the pin function GIO or Timer 5 output TM5OEN 0 GIO 1 Timer 5 output TM5IOA TM5IOB Select the pin function GIO or Timer 4 output TM4OEN 0 GIO 1 Timer 4 output TM4IOA TM4IOB Select the pin function GIO or Timer 3 output TM3OEN 0 GIO 1 Timer 3 output TM3IOA TM3IOB Select the pin function GIO or Timer 2 output TM2OEN 0 GIO 1 Timer 2 output TM2IOA TM2IOB Select the pin function GIO or Timer 1 output TM1OEN 0 GIO 1 Timer 1 output TM1IOA TM1IOB Select the pin function GIO or Timer 0 output TMOOEN 0 GIO 1 Timer 0 output TMOIOA TMOIOB Control Registers VII 25 Chapter 7 Port 7 2 8 8 bit Timer input output pins selection Register 8 bit Timer input output pins selection register selects the pin of Timer8 TMnIOA or TMnIOB 8 bit Timer input output pins selection Register TMIOSELO 0x03F2D bp 7 6 5 4 3 2 1 0 5 TM4 TM3 TM2 TM1 TM0 IOSEL IOSEL IOSEL IOSEL IOSEL IOSEL At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W Bit name Description bp i 7 6 Always read as 0 Select the pin of Timer 5 TM5IOA or TM5IOB TM5IOSEL 0 TM5IOA 21 1 TM5IOB P73 Select t
383. r side bit 16 This register shows the address where the next data from source address is stored XIV 10 DMA Controller Control Registers 14 2 4 DMA Transfer Word Count Register m DMA Transfer Word Count Register DMCNTL 0x03E0C DMCNTH 0x03E0D Chapter 14 DMA Controller bp 7 6 5 4 3 2 1 0 Bit name DMCT7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp 15 14 13 12 11 10 9 8 Bit name DMCT9 8 At reset 0 0 0 0 0 0 0 0 Access R R R R R R R W R W bp Bit name Description 15 10 Always read as 0 Number of DMA transfer This value is decremented when each transfer is finished 0x000 Prohibited 9 0 DMCT9 0 0x001 1 time 0x002 2 times Ox3FF 219 1 times transfers maximum DMA Controller Control Registers XIV 11 Chapter 14 DMA Controller 14 3 Data Transfer There are two transfer modes single transfer and burst transfer which are selected with the DMCTR0H DMTM 14 8 4 Single Transfer Mode When the DMA start trigger occurs single data the size of which is decided with DMCTR0H DMUT is trans ferred and the data transfer counter consisting of DMCNTH and DMCNTL are decremented by one When all the single data transfer finishes DMA interrupt occurs If the DMA start trigger happens during the time after DMA reads the last single data from Source Address and bef
384. r3 or Timer 4 connected with Timer 5 operates as a 16 bit timer in cascade connection Timer 0 connected with Timer 1 Timer 2 connected with Timer 3 Timer 4 connected with Timer 5 In cascade connection the timer corresponding to lower 8 bits of the 16 bit counter is grouped into Type Timer 0 and the timer of upper 8 bits is grouped into Type Timer 1 Timer 0 Timer 2 and Timer 4 are Type Timer 0 Timer 1 Timer 3 and Timer 5 are Type Timer 1 m Operation of 16 bit Timer Cascade Connection Timer 0 connected with Timer 1 Timer 2 connected connected with Timer 3 Timer 4 connected with Timer 5 The timer functions in 16 bit cascade connection are listed in Table 8 8 1 Table 8 8 1 Timer Functions in 16 bit Cascade Connection Timer 0 to Timer 1 Timer 2 to Timer 3 Timer 4 to Timer 5 Interrupt source TM1IRQ PERIOIRQO 5 TM2IOA P05 TM4IOA P34 TM0IOB P03 TM2IOB P02 TM4IOB P01 Timer Output TM1IOA P55 TMSIOA P56 21 p TM1IOB P20 72 TM5IOB P73 PWM output Pulse width measurement External interrupt 0 IRQOA P10 IRQOB P60 External interrupt 2 IRQ2A P80 IRQ2B P62 External interrupt 4 IRQ4A P14 IRQ4B P72 IRQ4C P12 HCLK HCLK HCLK HCLK 4 HCLK 4 HCLK 4 HCLK 16 HCLK 16 HCLK 16 HCLK 32 HCLK 32 HCLK 32 Clock source HCLK 64 HCLK 64 HCLK 64 SYSCLK 2 SYSCLK 2 SYSCLK 2 SYSCLK 4 SYSCLK 4 SYSCLK 4 SCLK SCLK SCLK TMOI
385. ram counter with 44 4 bit displacement and H bit Immediate a Register indirect 5 a d8 a 916 d4 PC branch instructi only 47 branch instructi only dii PC branch instructi PC 011 only 912 PC Specifies the address using the program counter wi branch instructi PC 412 12 bit displacement and H bit only d16 PC Specifies the address using the program counter wi branch instructi Peate 16 bit displacement and H bit only d4 Specifies the address using the program counter wi Register relative dun 7 bit displacement and H bit indirect Specifies the address using the program counter wi 11 bit displacement and H bit Specifies the address using stack pointer with 4 bit displacement Specifies the address using stack pointer with 8 bit 0 0 displacement Specifies the address using stack pointer with 16 bit 0x0 displacement Specifies the address using operand value appended to value of SBNKR the instruction code Optimum operand length can be or DBNKR used to specify the address The value of SBNKR 26512 or DBNKR The value of SBNKR or DBNKR SP 94 a 98 SP Stack relative SP 48 indirect a SP 916 abs8 abs12
386. ration Chapter 17 LCD Chapter 17 LCD 17 1 Overview This LSI has an LCD driver circuit LCDDRV which is composed of 43 segment output pins and 4 common out put pins 39 segment output pins and 8 common output pins The LCDDRV has an LCD reference voltage circuit REFVOL and a voltage booster circuit BSTVOL Table 17 1 1 shows the functions of LCDDRV Table 17 1 1 LCD Functions Function Details Dut Static y 1 2 to 1 8 duty LCD Power Supply Vici Vice LCD Reference Voltage Circuit REFVOL 0 05 V increments within a range of 0 9 V to 1 8 V LCD Voltage Booster Circuit BSTVOL Boosts reference voltage input by 2 3 times Clock Source for LCD Display LEDCLKS SCLK 24 HCLK 25 HCLK 2 HCLK 27 HCLK 28 LCDCLKS 23 LCDCLKS 2 LCDCLKS 25 LCDCLKS 2 LCDCLKS 2 LCD CLKS 28 LCDCLKS 29 LCDCLKS 2 LCDCLKS 2 LCDCLKS 21 Clock Source for BSTVOL LCUPCKS SCLK HCLK 2 HCLK 25 HCLK 26 HCLK 27 HCLK 28 LCUPCKS x 1 8 LCUPCKS x 1 16 LCUPCKS x 1 32 LCUPCKS x 1 64 LCUPCKS x 1 128 LCDCLKS Selected clock with LCDMD3 LCCKS2 0 LCDCLK Selected clock with LCDMD3 LCCK3 0 LCUPCKS Selected clock with LCDMD0 LCUPCKS2 0 LCUPCK Selected clock with LODMDO LCUPCKDIV2 0 LCD Display Clock LCDCLK Boost Clock for BSTVOL LCUPCK LCD operations are restricted depending on the CPU mode which is shown in Table 17 1 2 Table 17 1 2 LCD Function Restrictions in E
387. re 4 2 7 Clock Change Flow from SRCCLK to SOSCCLK Figure 4 2 8 Description change Figure 4 2 8 Transition Flow from OSC Mode to RC Mode Figure 4 2 8 Clock Change Flow from SOSCCLK to SRCCLK Figure 4 2 9 Writing error correction HALT STOP mode lt Watchdog timer HALTO0 1 4 stop counting HALT2 STOP clear counting NORMAL SLOW mode lt Watchdog timer HALTO 1 4 restart counting HALT2 STOP start counting HALT STOP mode lt Watchdog timer HALT0 1 2 3 continue counting STOP stop counting NORMAL SLOW mode lt Watchdog timer HALTO 1 2 3 continue counting STOP restart counting Figure 4 2 10 Writing error correction Figure 4 2 10 Transition Flow Diagram from CPU Operating Mode to HALTO HALT1 Mode Figure 4 2 10 Transition from CPU Operating Mode to HALTO HALT1 HALT2 Mode Figure 4 2 11 Description change HALTMOD 1 HALT 1 Set the CPUM as described in Table 4 1 8 Description deletion Note 1 If it can t be guaranteed that Note 2 gt Insert 3 NOP instructions right after Description change If priority level of the interrupt to be used is not equal to or higher than the mask level If the value of xICR LV1 0 for an inter rupt to be used as a return factor is equal or larger Figure 4 2 12 Description change STOP 1 Set the CPUM as described in Table 4 1 3 Description deletion lt Note 1 gt If
388. ription 1 Stop the LCD 1 Stop the LCD LCDMD2 0x03E82 bp7 LCEN 0 2 Set a display duty 2 Set the operation mode to static driving LCDMD2 0x03E82 bp2 0 LCDDTY2 0 000 3 Set a display clock 3 Select HCLK 215 as a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 4 Set Segment and common output pins 4 Select SEGO 7 and COMO pins LCCTRO 0x03E86 bp7 4 SEGSL3 0 1111 bp0 COMSLO 1 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 5 Set the display data 5 Set the display data 2 on the segment output latch LCDATAO 0x03E90 0x00 LCDATA1 0x03E91 0x00 LCDATA2 0x03E92 0x01 LCDATA3 0x03E93 0x01 LCDATA4 0x03E94 0x00 LCDATAS 0x03E95 0x01 LCDATA6 0x03E96 0x01 0x03E97 0x01 6 Activate the LCD 6 Start the LCD LCDMD2 0x03E82 bp7 LCEN 1 28 LCD Display Examples Chapter 17 LCD 17 4 8 LCD Display Example 1 2 duty m 1 2 duty Segment Latch ce 0x03E96 0 03 95 0x03E94 0 03 93 92 0 03 91 0 03 90 open SEG7 A electrode B electrode o OFF LCDPANEL LCD ON COM S COM N COM S COM N LCD OFF SEG S SEG S SEG N_ SEG N LCD clock Undefined Data 1 0 Undefi
389. rite an arbitrary value to the time base timer clear control register TBCLR to initialize the time base timer 5 Set the PERIOLV1 0 bits of the peripheral function group 0 interrupt level control register PERIOICR to select the interrupt level Clear the corresponding interrupt request bit of PERIODT register if it may have already been set 3 1 5 Set up procedure for Interrupt control register for peripheral function group 6 Set the PERIOEN2 bit of the PERIOEN register to 1 to enable the interrupt 7 Set the TBEN bit of the TM6BEN register to 1 to start the time base timer e When the selected interrupt cycle elapsed the time base interrupt request bit PERIODT2 of the interrupt con trol register for peripheral function Group 0 PERIODT is set to 1 Time Base Timer Chapter 11 Time Base Timer RTC TBT Chapter 11 RTC Time Base Timer RTC TBT 11 1 Overview RTC time base timer RTC TBT generates 1 Hz clock with SCLK of 32 768 kHz for Real Time Clock RTO 11 1 1 Functions Table 11 1 1 shows the function of RTC TBT Table 11 1 1 RTC TB Function T Function Description Clock source SCLK SOSCCLK or SRCCLK is selected Interrupt 1 Hz 2 Hz 4 Hz Frequency of RTC TBT interrupt 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz In the case of SCLK of 32 768 kHz Adjustment for the 1 Hz clock period Range 7 bit counter TBTCNTO TBTCLKSEL Period
390. rnal Interrupt Signal 3 A capture trigger is generated at the both edges of the external interrupt m input signal Synchronizing with this capture trigger the value of binary counter is loaded to the input capture register The value loaded to the capture register is the binary counter value at the falling edge of the capture trigger When the specified edge is selected as the capture trigger source the capture trigger is generated only at the specified edge of the interrupt signal The other count timing is the same as that of the timer operation When the binary counter is used as a free run counter which counts from 0x0000 to OxFFFF set Compare register 1 to OxFFFF or set the TMnMD2 TMnBCR to 0 Even if an event occurs before the value of the input capture register is read out the value of the input capture register is rewritten capture clock Therefore the edge of the external interrupt input signal may not be detected when an inter val of interrupt input signal is shorter than capture clock cycle 1 capture trigger signal is generated by sampling the external interrupt input signal at the 16 bit Timer Capture Function IX 41 Chapter 9 16 bit Timer It takes 1 or 2 capture clocks to load the value of the binary counter to the capture register since a capture trigger is sampled at the capture clock In the initial state after releasing the reset the setting of the external interrupt si
391. romine 900 ppm Maximum Concentration Value Chlorine 900 ppm Maximum Concentration Value Bromine Chlorine 1500 ppm Maximum Concentration Value The above mentioned standards are based on the numerical value described IEC61249 2 21 Antimony and its compounds are not added intentionally Operating Ambient Temperature Ta 40 C to 85 C 1 6 Hardware Features Chapter 1 Overview 1 2 Comparison of Product Specification port Table 1 2 1 Functions Function Specification MN101LR05D MN101LR04D MN101LR03D MN101LR02D N channel transistor drive strength Interrupt Internal interrupt 31 31 31 29 External interrupt 8 Z IRQ0 6 1 KEY0 7 8 71 0 6 1 KEY1 7 8 7 IRQO 6 1 KEY1 5 3 2 IRQ4 5 1 1 7 Timer 5 Timer I O TMSIO TMSIO 5 9 Timer I O TM9IO TM9IO 1 Serial interface 1 EI Serial interface 3 Serial communication pins SBO3 SDA3 SBT3 SCL3 SBI3 SBCS3 SBO3 SDA3 SBT3 SCL3 SBI3 SBCS3 SBO3 SDA3 SBT3 SCL3 SBO3 SDA3 SBT3 SCL3 SBI3 Clock synchronous 2 3 or 4 wire 2 3 or 4 wire 2 wire 2 or 3 wire SPI compatible EI 2 2 Buzzer Buzzer output Inverted buzzer output BUZ NBUZ BUZ NBUZ BUZ NBUZ NBUZ ADC Analog input 8 pins AN0 7 6 pins AN2 7 4 pins AN2 5 3 pins AN3 5
392. rrupt disabled RTCCIRQ Setthe CIRQMIEN bit to 0 Display mode setting RTCCTR Set the HDMD bit to 0 Clock data setting Set the clock data to 01 01 00 Thursday April 01 2010 using the following registers RTCYD Set it to 0x10 RTCMOD Set it to 0x04 RTCDD Set itto 0x01 RTCWD Set it to 0x04 RTCHD 0x01 RTCMID Set it to 0x01 RTCSD Set it to 0x00 Periodic interrupt enabled RTCCIRQ Set the CIRQMIEN bit to 1 All maskable interrupts disabled PSW Set the MIE bit to 0 Interrupt level setting PERIOICR Set the PERIOLV1 0 bits to 00 Clear the corresponding interrupt request bit of PERIODT register if it may have already been set Refer to 3 1 5 Set up procedure for Interrupt control register for peripheral function group Periodic Interrupt enabled PERIOEN Set the PERIOEN4 bit to 1 Maskable interrupts enabled PSW Set the MIE bit to 1 RTC starts RTCCTR Set the CLKEN bit to 1 The RTC starts For PSW refer to Chapter 2 CPU For PERIOICR and PERIOEN refer to Chapter 3 Interrupts RTC Operation XII 17 Chapter 12 Real Time Clock RTC m Alarm Interrupt Setup Example The following is an example to generate the Alarm 0 interrupt at 10 23 on Saturday with the RTC function Set the initial time to 01 01 00 Thursday in 24 hour display mode The setup procedure and the description of each
393. s W Determination of Maskable Interrupt Acceptance The procedures of the interrupt acceptance is described below 1 IR is set to 1 2 When IE is 1 the interrupt request is sent to CPU 3 When LV1 0 is less than PSW IM1 0 and PSW MIE is 1 the above interrupt request is accepted 4 IR is cleared to 0 by hardware IE is not cleared by hardware PSW BKDMIE 1 ZF In the case of xICR LV1 0 lt PSW IM1 0 the interrupt is accepted 7 Figure 3 1 4 Determination of Interrupt Acceptance After IR is set to 1 by an interrupt trigger at step 1 if the same interrupt trigger occurs during Y the time of above 2 4 steps the latter interrupt trigger is ignored Overview 7 Chapter 3 Interrupts 8 W Explanation of PSW MIE and PSW IM1 0 PSW MIE is set to 0 when MEMCTR MIESET is 0 and NMI or a maskable interrupt is accepted e PSW MIE is set to 0 by software BE instruction is executed and MIE are set to 0 the LSI is reset PSW MIE is set to 1 when MEMCTR MIESET is 1 and NMI or a maskable interrupt is accepted e PSW MIE is set to 1 by software BD instruction is executed BKD and MIE is set to 1 PSW IM1 0 change when e PSW IM1 0 is set by software the LSI is reset an maskable interrupt is accepted and the value of PSW IM1 0 changes to the value of xICR IL1 0
394. s at least Transition Time 6 SYSCLK cycles at least Restart Restore PC PSW HA Execute RTI instruction Figure 3 1 2 Interrupt Processing Sequence is accepted but NMICR IRQNPG NMICR IRQNWDG PERIODT PERIODT6 0 and a xICR IR of maskable interrupt is cleared to 0 by hardware when the corresponding interrupt PERI1DT PERI1DT 4 0 are not cleared to 0 by hardware and must be cleared by software 4 Overview Chapter 3 Interrupts W Interrupt Vector Table Table 3 1 1 shows the interrupt vector address and the interrupt control registers Table 3 1 1 Interrupt Vector Table Vector Vector address Interrupt factor Interrupt control register number 0 IVBM 1 Name Address 0 0x04000 LSI Reset 1 0x04004 0x00104 Non maskable interrupt NMICR OxOSFE1 2 0x04008 0x00108 External interrupt 0 IRQOICR 0x03FE2 3 0 0400 0 0010 External interrupt 1 IRQ1ICR 0x03FE3 4 0x04010 0x00110 External interrupt 2 IRQ2ICR 0x03FE4 5 0x04014 0x00114 External interrupt 3 IRQ3ICR 0x03FE5 6 0x04018 0x00118 External interrupt 4 IRQ4ICR 0x03FE6 7 0 0401 0 0011 External interrupt 5 IRQ5ICR 0x03FE7 8 0x04020 0x00120 External interrupt 6 IRQ6ICR 0x03FE8 9 0x04024 0x00124 External interrupt 7 KEY interrupt IRQ7ICR 0x03FE9 10 0x04028 0x00128 Timer 0 interrupt TM0ICR 11 0 0402 0
395. s output from TM7IOA output pin using the external interrupt 0 input signal as a trigger The setup procedure and its description are shown below IGBT trigger TM7IO output 400 Hz Figure 9 10 7 Output Waveform of TM7IO output pin Setting Disable the timer counter Register TM7MD TM7EN 0 Description Disable the timer count operation Select the IGBT output pin TMIOEN1 TM7OEN 1 TMIOEN1 TM8OEN 1 PODIR PODIR4 1 P5DIR P5DIR7 1 Select the IGBT output pin Chapter 7 I O Port Set the timer mode register M7MD3 T7IGBTEN 1 M7MD2 TM7PWM 1 M7MD1 TM7CL 0 Enable the IGBT output Select the IGBT output M7MD2 TM7BCR 0 M7MD2 T7PWMSL 1 Select the TM7BC clear source and the duty determination source of IGBT output T T T TM8MD3 TM8SEL 1 T T T M7MD4 T7NODED 1 Select No as the dead time TM7MD3 T7IGBT1 0 01 Select the IGBT trigger source Set the external interrupt IRQOICR REDGO 1 Set the external interrupt valid edge Set the timer mode register TM7MD3 T7IGBTTR 0 TM7MD2 T7ICEDGO 1 Select the IGBT trigger level and IGBT trigger edge Set the external interrupt IRQISELO IRQOSEL 0 IRQIEN IRQIOEN 1 Enable the external interrupt pin Set the interrupt level IRQOICR IRQOLV 1 0 Enable the interrupt IRQOICR IRQOIE 1 Refer to 3 1 3 Maskable Interrupt Control Register Setup Set t
396. s set to 1 the binary counter is not changed D When the value of binary counter matches the setting value of compare register 1 the setting value of the preset register is loaded to the compare register and an interrupt request is generated at the next count clock And the binary counter is cleared to 0x0000 and restarts counting up E When the count operation is disabled the TMnEN bit is set to 0 the binary counter is stopped IX 22 16 bit Timer Chapter 9 16 bit Timer When the value of TMnBC matches the setting value of TMnOC an interrupt request is gen erated at the next count clock and the is cleared So set the TMnOC as follows Setting value of the compare register Counts till the interrupt request 1 When TMnOC1 compare match is selected as a TMnBC clear source and TMnOC2IRQ is used the setting value of TMnOC2 should be smaller than the one of TMnOC1 If the timer interrupt request bit may have already been set before the timer starts the timer interrupt request bit should be cleared When TMnBC is used as a free counter that counts from 0x0000 to set TMnOC1 to OxFFFF or set the TMnMD2 TMnBCR to 0 Do not change the TMnMD TMnEN simultaneously with other bits to avoid any error in oper ation lt In 16 bit timer operation the internal enable signal becomes ON status at the rising edge of the first count clock a
397. scade connection pair of registers TM1BC with 16 bit access instruction MOVW ing up may be read Alternatively the register must be read multiple times and those data lt When reading the value of TMnBC register while operating indeterminate data while count confirmed to be the same 8 bit Timer Control Registers 8 2 3 W Timer 0 Mode Register TMOMD 0x03F74 bp Timer Mode Registers 6 5 4 3 2 Chapter 8 8 bit Timer 1 0 Bit name At reset TMOPOP TMOMOD TMOPWM TMOEN TMOCK1 0 Access 0 R 0 0 0 0 0 R W R W R W R W R 0 0 R W R W bp Bit name Description 7 Always read as 0 Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High TMOMOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P10 P60 TMOPWM Timer 0 operation mode control 0 Normal timer operation 1 PWM operation Timer 0 count enable 0 Disabled 1 Enabled Always read as 0 TMOCK1 0 Clock source select 00 HCLK 01 TMOPSC prescaler output 10 SCLK 11 TMOIO input 8 bit Timer Control Registers VIII 9 Chapter 8 8 bit Timer W Timer 1 Mode Register TM1MD 0x03F75 bp 4 Bit name TM1CAS At reset 0 Access Bit name Description Always r
398. se Be sure to SCnMD2 IIC3RSTN O Be sure to se Be sure to se Be sure to se Iniial setting 1 SCnMD2 Be sure to se Be sure to se Be sure to set i End of serial reset SCnMD3 Be sure to set i SCnMD2 IIC3RSTN 1 Be sure to seti Be sure to set i Be sure to se 5 5 5 JOJO gt Other 5 0 SCnMD3 SCnAD register SCnMDO SCnDIR Select MSB first or LSB first Initializing monitor flag IICSSTE SCnIICSTR IIC3ABT_LST 0 SCnMD3 IIC3TMD SCnAD IIC3AD7 0 Slave address setting Serial transfer clock is needed to be set with BRTM S EN BRTM S MD Set a slave address and R W bit toTXBUFn and so forth 2 To avoid communication error confirm that serial communication is not executed with IIC3BUSBSY before starting next communication Start master communication Master communication completion SCnIICSTR IICaDATA ERR 0 YES 2 YES ACK bit detection SCnMD3 SCnACKO 1 NO YES Communication completion interrupt generation Arbitration lost detected YES FZ SCnIICSTR IICSABT LST 0 NO Continue communication ae YES Restart condition detected SCnlICSTR IC3STRT 1 YES 2 NO Stop condition generation Transmission reception mode selection SCnMD3 IIC3STPC 1 SCnMD3 IIC3REX IIC communication completion
399. set sequence 1 When NRST pin comes to high level from low level the internal binary counter starts counting The time range after the counter started counting before the overflow of it occurs is called the oscillation sta bilization wait time During reset internal registers and special function registers are initialized 2 After the oscillation stabilization wait time the internal reset is released and the CPU starts executing the pro gram the address of which is shown in the interrupt vector table at 0 04000 The internal RAM is not initialized at reset Y It needs to be initialized before used Reset 29 Chapter 2 CPU II 30 2 5 3 Oscillation Stabilization Wait Time The oscillation stabilization watt time is different in the following situations 1 When the LSI starts up from reset the wait time is equal to the initial value of the DLYCTR 2 When transiting from SLOW mode to NORMAL mode or recovering from HALT2 STOPO mode the wait time can be varied with the DLYCTR The value of the DLYCTR must be determined for stabilizing the HCLK oscillation In this situation the frequency of OSCSTBCLK is equal to half the of HCLK After the oscillation stabilization the CPU enters the NORMAL mode 3 When recovering from mode the wait time can be varied with the DLYCTR The value of the DLYCTR must be determined for stabilizing the SCLK oscillation
400. setting the TMnMD1 TMnCK1 0 and synchronized with SYSCLK However if HCLK or SYSCLK is selected with the TMnMD1 TMnCK1 0 the binary counter doesn t count correctly When selecting HCLK or SYSCLK set the TMnMD3 TMnCKSMP to Each capture trigger signal of the 16 bit timers Timer 7 9 is generated by sampling at the ing edge of the capture clock selected with the TMnMD3 TMnCKSMP Therefore even if a capture trigger is input the value of the binary counter is not loaded to the capture register until at the 2nd rising edge of the capture clock from the capture trigger If the clock which is slower than the CPU operation speed fsyscuk is used as the timer source clock set the TMnMD3 TMnCKSMP to SYSCLK Also the interval of each capture trigger should be set more than twice the clock cycle which is set in the TMnMD3 TMnCKSMP If the capture clock cycle is longer than the system clock the value of the capture register may be read out before capturing IX 40 16 bit Timer Capture Function Chapter 9 16 bit Timer W Capture Count Timing with a Trigger of Both Edges of External Interrupt Signal TMnEN bit Compare register Binary 0001 40111 0112 4 5555 5556 5557 5558 S N counter External interrupt m input signal Capture trigger Capture 0000 0111 0114 5555 5558 register z Figure 9 8 1 Capture Count Timing with Trigger of Exte
401. sfer Word Count Register sess XIV 11 14 3 DMA Data Transfer seis inte reete eee te e tert eerte rers XIV 12 14 3 1 Single Transfer Mode essere enne enne XIV 12 14 3 2 Burst Transtet Mode ee fertiles ec ee ee XIV 13 Chapter TS 1 15 1 2 15 2 Control Register iniecto tei eme o eO pie 3 15 2 1 oO ate eae otter ie ae XV 3 15 22 Buzzer Control Register uy tti tetti 4 15 3 0 XV 5 153 1 Operation zz eR a A a a eii XV 5 15 3 2 Setup e e Res 6 Chapter T6 A D Converter oan ag Ceo tuu boc nuqa tod ael ose pa phe bon XVI 1 L6 1 OVerVI W XVI 2 16 1 T E nctionS XVI 2 16 12 Block Diagram mH ERE oot i teint XVI 3 16 2 Control Registets aei cadi tendere etui te eti ie no er e ene XVI 4 162 1 Reg1sters ad ea d eem XVI 4 16 2 2 Control Registers oreet re tee ehe a rite bunu deen XVI 5 16 2 3 Data onus censo tee cp ett etm Ore XVI 7 Contents 8 16 3 Operation seat eoe ER PUO eH b XVI 8 16 3 1 Setup
402. ss Bit name Description 7104 Always read as 0 Display mode select 0 24 hour display mode 1 12 hour display mode RTC operation control 0 Stop 1 Start Always read as 0 HDMD must not be set when CLKEN is O Y HDMD and CLKEN must not be set at the same time Control Registers Chapter 12 Real Time Clock RTC 12 2 2 Alarm Interrupt Registers E n F Alarm 0 Interrupt Control Register RTCALOIRQ 0x03ED3 Bit name At reset Access Bit name Description Always read as 0 AL0IRQSET Alarm 0 interrupt control 0 Disabled 1 Enabled Always read as 0 AL0IRQWEN Alarm 0 Date comparator enable control 0 Disable 1 Enable AL0IRQHEN Alarm 0 Hour comparator enable control 0 Disable 1 Enable AL0IRQMIEN Alarm 0 Minute comparator enable control 0 Disable 1 Enable m Alarm 0 Minutes Setting Register ALOIRQMI 0x03ED4 Bit name AL0IRQMI6 0 At reset 0 Access Bit name Always read as 0 Alarm 0 Minute setting AL0IRQMI6 0 Set a value within the range of 00 to 59 using the BCD format The value which doesn t exist must not be set Control Registers XII 5 Chapter 12 Real Time Clock RTC W Alarm 0 Hours Setting Register ALOIRQH 0x03ED5 Bit name AL0IRQH6 AL0IRQH5 0 At reset 0 0 0 0 Access
403. ster IRQ6ICR 0x03FE8 External interrupt 6 control register IRQ7ICR 0x03FE9 External interrupt 7 control register KEY interrupt TM0ICR Ox03FEA Timer 0 interrupt control register TM1ICR Timer 1 interrupt control register TM2ICR 0x03FEC Timer 2 interrupt control register TM3ICR 0x03FED Timer 3 interrupt control register TM4ICR Ox03FEE Timer 4 interrupt control register TM7ICR OxOSFEF Timer 7 interrupt control register TM7OC2ICR OxOSFFO Timer 7 compare 2 match interrupt control register TM8ICR Ox03FF1 Timer 8 interrupt control register TM8OC2ICR Ox03FF2 Timer 8 compare 2 match interrupt control register TM9ICR Ox03FF3 Timer 9 interrupt control register TM9OC2ICR 0x03FF4 Timer 9 compare 2 match interrupt control register SCORICR Ox03FF5 Serial interface 0 reception interrupt control register SCOTICR Ox03FF6 Serial interface 0 transmission interrupt control register SC1RICR OxO3FF7 Serial interface 1 reception interrupt control register SC1TICR OxO3FF8 Serial interface 1 transmission interrupt control register SC2TICR OxOSFF9 Serial interface 2 transmission complete interrupt control register SC2SICR Serial interface 2 stop condition interrupt control register SC3TICR 0x03FFB Serial interface 3 transmission complete interrupt control register SC3SICR 0x03FFC Serial interface 3 stop condition interrupt control register PERI
404. ster ANENO IRQIEN IRQISELO KEYIEN KEYSEL Bit name ANENO1 IRQI1EN IRQ1SEL KEYI1EN KEY1SEL 1 AN1 1 0 0 IRQ1A 0 1 0 KEY1A 0 P11 Port 1 Chapter 7 I O Port VII 37 Chapter 7 I O Port Table 7 5 4 P12 Function Selection Setup Function Register ANEN0 IRQIEN IRQISEL1 KEYIEN KEYSEL Bit name ANEN02 IRQI4EN IRQ4CSEL 2 KEY2SEL 1 AN2 1 1 0 5 IRQ4C 0 1 0 KEY2A 0 2 P12 Table 7 5 5 P13 Function Selection Setup Function Register ANENO IRQIEN IRQISEL1 KEYIEN KEYSEL Bit name ANENO3 IRQIBEN IRQ5CSEL KEYISEN KEY3SEL 1 AN3 1 1 0 IRQ5C 0 1 0 KEY3A 0 P13 Table 7 5 6 P14 Function Selection Setup Function Register ANENO IRQIEN IRQISELO IRQISEL1 KEYIEN KEYSEL Bit name ANENO4 IRQI4EN IRQ4SEL IRQ4CSEL KEYI4EN KEY4SEL 1 1 0 0 0 IRQ4A 0 1 0 KEY4A 0 5 P14 Table 7 5 7 P15 Function Selection Setup Function Register ANEN0 IRQIEN IRQISELO IRQISEL1 KEYIEN KEYSEL Bit name ANENO5 IRQI5EN IRQ5SEL IRQ5CSEL KEYI5EN KEY5SEL 1 gt 2 5 1 0 0 0 IRQ5A 0 1 0 KEY5A 0 15 VII 38 Port 1 Table 7 5 8 P16 Function Selection Setup Function Register ANEN0 IRQIEN
405. t decease tbe eee ee NO es ee eee pee ee 3 4 LVION set Power supply voltage detection function is OFF LVION 0 1 Though power supply voltage at falling falls below the detection voltage the interrupt request is not generated and the LVIOUT bit is not cleared 2 Though power supply voltage at rising exceeds the detection voltage the interrupt request is not generated and the LVIOUT bit is not cleared Power supply voltage detection function is ON LVION 1 3 As power supply voltage at falling falls below the detection detection voltage Vivi the interrupt request is generated and the LVIOUT bit is cleared 4 As power supply voltage at rising exceeds the detection voltage Vivi the interrupt request is generated and the LVIOUT bit is set Figure 6 1 1 Power Supply Detection Waveform VI 2 Overview Chapter 6 Power Supply Voltage Detection 6 2 Control Register 6 2 1 Registers Table 6 2 1 shows the PSVD related registers Table 6 2 1 Power Supply Voltage Detection Control Registers Address Register name LVICTR0 0x03F66 PSVD control register 0 LVICTR1 0x03F67 PSVD control register 1 LVICTR2 0x03F68 PSVD control register 2 Control Register VI Chapter 6 Power Supply Voltage Detection 6 2 2 Power Supply Voltage Detection Control Registers PSVD Control Register 0 LVICTRO 0x03F66 Bite n
406. t 1 0 MHz 6 1 3 3 6 B3 Voos 1 lt 40 kHz 7 9 RAM retention B4 Vpp4 At STOP mode 9 1 1 3 6 supply voltage Operating speed 8 B5 toy Vppao 1 8 V to 3 6 V 0 1 Instruction execution time B6 t 2 Vpp z1 3Vto3 6V 1 0 5 l fsvscuk EM B7 tog Vpp3o 1 1 Vto 3 6 V 9 25 0 5 uu 5 Frequency for the system clock 6 When is generated by using the internal high speed oscillation 7 When fsyscuk is generated by using the external low speed oscillation or the internal low speed oscillation 8 tc1 2 When fsyscuk is generated by using the internal high speed oscillation or the external high speed oscillation However for tc2 only by using the internal high speed oscillation tc3 When fsyscuk is generated by using the internal low speed oscillation 9 When using auto reset function the lowest voltage is the auto reset detection voltage Vppao to 3 6 V Vss 0 V 1 1 V at auto reset function Ta 40 to 85 C Limits P iti i arameter Symbo Condition MIN T Unit Crystal oscillation 1 Figure 1 4 1 MN101LR02D is not applicable B8 Frequency 1 8 V to 3 6 V 1 0 10 0 MHz Crystal oscillation 2 Figure 1 4 2 B9 Frequency to 3 6 V 32 768 kHz Internal high speed RC oscillation 10 Vpp3o 1 8 Vto 3 6 V
407. t clock If the count clock is changed during counting Y the timer doesn t count correctly The timer can be initialized by writing an arbitrary value to the time base timer clear control register TBCLR Time Base Timer X 13 Chapter 10 General Purpose Time Base Free Running Timer 14 10 4 2 Setup Example W Timer Operation Setup Time Base Timer The time base timer generates interrupts regularly by selecting a interrupt generation cycle The interrupt genera tion cycle is x 1 2 1 024 ms 8 MHz The setup procedure and the description of each step are shown below Setup Procedure Description 1 Select the clock source TM6MD 0x03F7A TM6CKO 0 2 Disable the interrupt PERIOEN 0x03FDC bp2 PERIOEN2 0 3 Select the interrupt generation cycle TM6MD 0x03F7A bp6 4 TM6IR2 0 101 4 Initialize the time base timer TBCLR 0x03F7B 0x00 5 Set the interrupt level PERIOICR OxOSFEB bp7 6 G11LV1 0 01 6 Enable the interrupt PERIOEN 0x03FDC bp2 PERIOEN2 1 7 Start the time base timer operation TM6BEN 0x03F7C bp1 TBEN 1 1 Select HCLK as a clock source by the TM6CKO bit of the timer 6 mode register TM6MD 2 Set the PERIOEN2 bit of the PERIOEN register to 0 to disable the interrupt 3 Set the TM6IR2 0 bits of the TM6MD register to select the specified clock x 1 213 as an interrupt generation cycle 4 W
408. t receive data set SCnMD1 SCnSBIS to 0 Y When the LSI only receive data not send data set SCnMD1 SCnSBOS to 0 48 Full duplex UART Communication Chapter 13 Serial Interface W Setting of Transfer Clock SCnCLK SCIFn operates with SCnCLK which is generated based on BRTM output clock BRTM_SCnCLK Regardless of the setting value of SCnMD1 SCnCKM SCnCLK is as follows When SCnMD1 SCnDIV is 0 SCnCLK is generated by dividing BRTM_SCnCLK by 8 When SCnMD1 SCnDIV is 1 SCnCLK is generated by dividing BRTM_SCnCLK by 16 m Generating Baud Rate Timer Output Clock BRTM_SCnCLk This is common feature with the Clock Synchronous communication For more information refer to 30 Transmission Data Buffer TXBUFn and Transmission Buffer Empty Flag 5 This is a common feature with the Clock Synchronous communication For more information refer to XIII 35 Write data to TXBUFn only when SCnSTR SCnTEMP is 0 Y If data is written to TXBUFn while SCnTEMP is 1 SCIFn does not work properly to the first data transmission is the period of 3 5 transfer clocks a As in the Clock Synchronous communication a wait time from a data write to TXBUFn A start bit is transmitted after 2 5 transfer clocks after a data is written to TXBUFn Reception Data Buffer RXBUFn and of Reception Buffer Empty GCnREMP This is common feature with the Clock Synchronous communicat
409. ta Buffer XIII 10 SC23SEL 0x03F1D SCIF23 I O Pin Switching Control Register XIII 9 BRTM_S_MD 0x03E70 BRTM Operation Mode Setting Register XIII 22 BRTM_S_EN 0x03E71 BRTM Enable Register XIII 23 BRTM S CKSEL 0x03E72 BRTM Base Count Clock Selection Register XIII 24 BRTM_S01_CK 0x03E74 BRTM 01 Count Clock Selection Register XIII 25 BRTM_S23_CK 0x03E75 BRTM 23 Count Clock Selection Register XIII 26 BRTM_S0_OC 0x03E78 BRTM 0 Compare Register XIII 27 BRTM_S1_OC 0x03E79 BRTM 1 Compare Register XIII 27 BRTM_S2_OC 7 BRTM 2 Compare Register XIII 27 BRTM_S3_OC 0x03E7B BRTM 3 Compare Register XIII 27 R W Readable Writable R Read only In Clock Synchronous communication SCIFn n 0 1 mode registers SCnMDO 3 must be Y changed during serial reset of SCIFn In UART communication SCIFn n 0 1 mode regis ters SCnMDO 3 other than SCnMD2 SCnBRKE must be changed during the serial reset of SCIFn SCIFn n 2 3 mode registers SCnMDO 3 other than SCnMDO IICSSTE SCnMD3 IICSSTPC SCnMD3 IIC3REX and SCnMD3 IICSACKO must be changed during the serial reset of SCIFn _ _ _ _ must be changed during the serial reset of SCIFn The following registers must be changed while BRTM_S_EN BRTM_Sn_EN is BRTM S MD BRTM Sn MD BRTM S CKSEL BRTM Sn CKSEL BRTM Sn OC BRTM Sn CK3 0 of BRTM S01 CK and BRTM Sn 0 of BRTM S23 CK
410. ter SBOn sae X X X X X SBCSn Last bit hold period At master output A c f SBCSn At slave input Figure 13 3 8 4 wire Communication Transmission Reception Timing 1 Clock Synchronous Communication XIII 33 Chapter 13 Serial Interface T sence 0 TS ASJ OX X Y N SBTn 0 5T minimum value SCnCE1 1 E V VY AC X N Z SBIn reception timing no s SBOn SBOn At slave Last bit data hold period SBCSn 0 5 1 5 SCnCLK frequency At master output SBCSn At slave input Figure 13 3 9 4 wire Communication Transmission Reception Timing SCnCKPH 0 34 Clock Synchronous Communication Chapter 13 Serial Interface m Transmission Data Buffer TXBUFn and Transmission Buffer Empty Flag SCnTEMP TXBUFn is the buffer to store the data to be transmitted SCnSTR SCnTEMP is set to 1 when data is written to and is cleared to 0 when data in TXBUFn is transferred to the transmit shift register SCnTRB and the serial communication starts Write data to TXBUFn only when SCnTEMP is 0 When writing the next data to TXBUFn during single byte communication the following communication will be automatically started after the present communication fin ishes The blank period is different depending on the communication mode consecutive communicat
411. ter 9 16 bit Timer W Count timing of Standard IGBT Output when compare register 1 0x0000 Timer 7 TM7EN bit Compare register 10000 IGBT trigger counter TM7IO output IGBT output Figure 9 9 2 Count timing of Standard IGBT Output When compare register 1 0x0000 The IGBT output is Low while the TM7MD1 TM7EN is set to 0 to stop counting W Count timing of Standard IGBT Output when compare register 1 OxFFFF Timer 7 TM7EN bit Compare register 1 IGBT trigger Binary 0000 2 4 4FFFEJFFFF oooo 0 TE mU 0000 counter TM71O output IGBT output Figure 9 9 3 Count timing of Standard IGBT Output when compare register 1 OxFFFF When using the IGBT standard output set the TM7MD2 TM7BCR to 0 to select the full count overflow as the binary counter clear source and the IGBT output set source to High state The TM7OC1 compare match or TM7OC2 compare match can be selected for the IGBT out put reset source to Low state by setting the TM7MD2 T7PWMSL 16 bit Standard IGBT Output with Variable Duty IX 49 Chapter 9 16 bit Timer 9 9 2 Setup Example uE n 3 W Standard IGBT Output Setup Example is an example that using Timer 7 with HCLK 10 MHz as the clock source the IGBT output waveform with the 1 4 duty cycle and 152 59 Hz is output from TM7IOA output pin using IRQ0 input signal as a trigger
412. ter the BCD correction to the DO register Bit Changes Size Cycles Codes VF 0 NF 0 CF Set if the result is smaller than 0 otherwise set to 0 6 nibbles 4 cycles ZF Set if the result is 0 otherwise set to 0 0000 0010 0111 0000 0000 0100 W Execution of BCD subtraction without carry 1 Store the 8 bit value of the two digit BCD as a subtrahend to the DO register Store the 8 bit value of the two digit BCD as a minuend to the D1 register 2 Execute MOV 0x40 0x03F07 Extended calculation macro instruction BCDSUB 3 Subtracts the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and stores the result 8 bit after the BCD correction to the DO register 0x03F07 1 When this extended calculation instruction is the handy address is updated the result is not guaranteed 1 In this instruction do not enter the value that can not represented BCD If you enter it Extended Calculation Instruction Chapter 2 CPU 2 4 8 BCDSUBC BCD subtraction with carry j a SSS H sn lt Vr X BCDSUBC MOV 0x80 0x03F07 DO BCD D1 BCD PSW CF 00 BCD Operation Subtracts the DO register 8 bit and the D1 register 8 bit as the value of each two digit BCD and subtracts the PSW CF further and stores the result 8 bit after the BC
413. the timer pulse Timer 4 interrupt should be disabled though any interrupt request of Timer 4 is not generated At 16 bit cascade connection when rewriting the compare register to clear the binary counter set the TMnMD TMnEN for lower 8 bit timer to 0 to stop counting Then rewrite the compare registers Use 16 bit access instruction to set TM1OC to register TM2OC to register and TM5OC to 4 register During cascade connection PWM output function cannot be used When cascade connec tion always set the TMnMD TMnPWM to 0 ma When cascade connection read the value of TMnBC with the 16 bit access instruction MOVW lt 8 bit Timer Cascade Connection Chapter 8 8 bit Timer 8 8 2 Setup Example Timer Operation Setup Example of 16 bit Cascade Connection Here is an example of the timer function that the 16 bit timer Timer 0 connected with Timer 1 in cascade connec tion generates a periodic interrupt An interrupt occurs every 2500 cycles 1 ms by selecting SYSCLK 2 at 5 MHz as clock source The setup procedure and the description of each step are shown below Setting Register Description 1 Disable the timer counter TMOMD TMOEN 0 Disable the timer count operation Upper 8 bits timer TM1MD TM1EN 0 Lower 8 bits timer 2 Disable the interrupt TMOICR TMOIE 0 Disable the timer int
414. tion En Table 1 2 4 Pin Functions Power supply Oscillations Reset Mode control External interrupt KEY interrupt Serial interface Buzzer Clock output Chapter 1 Overview XI XO NATRON NRST OSC1 OSC2 TM9IOC o O N O Q G N TM4IOB TM2IOB TM8IOC BUZB TMOIOB TM71IOC NBUZB TM7IOA SBO3A SDA3A TMOIOA TM2IOA SBT3A SCL3A CLKOUTA TM8IOB SBISA 9 SBCS3A IRQ0A KEY0A IRQ1A KEY1A IRQ4C KEY2A IRQ5C KEY3A VREFP DMOD OCD_CLK OCD_DATA IRQ4A KEY4A IRQ5A KEY5A IRQ6A KEY6A KEY7A TM1IOB TM9IOB SBI2B SBO2B SDA2B SBT2B SCL2B SBCS2B SBI1A RXD1A SBO1A TXD1A SBT1A SBCS1A TM4IOA TM7IOB SBIOB RXDOB SBOOB TXDOB SBTOB SBCSOB SBI2A SBO2A SDA2A Comparison of Product Specification SBT2A SCL2A 1 9 Chapter 1 Overview Power supply External Serial Buzzer Oscillations interrupt interface Clock output Reset KEY interrupt Mode control SBCS2A SBI1B RXD1B SBO1B TXD1B SBT1B SBCS1B SBISB SBO3B SDA3B SBT3B SCL3B SBCS3B TM8IOA CLKOUTB SBI0A RXD0A SBO0A TXD0A 5 SBCSOA TMSIOB
415. tion Data transmission state in Clock Synchronous communication SCnTBSY 0 IDLE 1 During transmission 0 is always read out Transmission data buffer empty detection SCnTEMP 0 detected 1 Not detected Reception data buffer empty detection SCnREMP 0 detected 1 Not detected 0 is always read out Overrun error detection SCnORE 0 Not detected 1 detected XIII 20 Control Registers m SCIFn n 2 3 Status Register IIC SC2IICSTR SC3IICSTR Bit name IICSWRS _LST IICSADD _ IICSSTRT IIC3BUS BSY Reserved Chapter 13 Serial Interface IIC3DATA _ERR Initial value 0 0 0 0 0 0 0 Access R W R R Bit name IICSWRS Description Transmission reception mode in slave communication 0 Reception mode 1 Transmission mode R W IICSABT LST Arbitration lost detection 0 Not detected 1 Detected IICSADD ACC Slave address match detection 0 Not detected 1 Detected IICSSTRT Start condition detection 0 Not detected 1 Detected IICSBUSBSY Bus busy detection 0 Not detected 1 Detected Reserved x undefined value is always read out IICSGCALL General call detection 0 Not detected 1 Detected ERR Communication error detection 0 Not detected 1 Detected lt When writing 1 to IIC3A
416. tion Confirm that SCnSTR1 SCnTEMP is 0 Dummy data write to TXBUFnTX BUFn TXBUFn Set dummy data in TXBUFn Wait for communication comple tion lt SCIFn n 0 1 SCnSTR SCnRBSY SCIFn n 2 3 gt SCnSTR SCnTBSY lt SCIFn 0 1 gt When the communication has been completed SCnRBSY becomes 0 When an interrupt is enabled a communication complete interrupt SCnTIRQ occurs lt SCIFn n 2 3 gt When the communication has been completed SCnTBSY becomes 0 When an interrupt is enabled a communication complete interrupt SCnTIRQ occurs Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn Confirmation of overrun error lt SCIFn n 0 1 gt SCnSTR SCnORE SCnSTR SCnERE SCIFn n 2 3 SCnSTR SCnORE If SChORE SCnEREY is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea Sures such as data retransmission since reception data may be destroyed SCnERE is only for SCIFn 0 1 Reception end Setting Empty confirmation of transmis Sion buffer Register name SCnSTR SCnTEMP Repeat these procedures from step 1 to execute the next communication m Data Transmission Reception Consecutive Communication Mode Description Confirm that SCnSTR1 SCnTEMP is 0 Data write to TXBUFn The first data transmission TXBUFn Set transmission data in TXBUFn Em
417. tion circuit control 0 Disabled General purpose port selected 1 Enabled OSC1 OSC2 selected HRCCNT Internal high speed oscillation circuit control 0 Disabled 1 Enabled a The HCLKSEL must be set while the CPU is in NORMAL or IDLE mode and both the HOSC CNT and the HRCONT are 1 At this time HOSCCLK and HRCCLK must be stable Clock Control IV 7 Chapter 4 Clock Mode Voltage Control Low speed Oscillation Clock Control Register SCLKCNT 0x03F06 bp 7 2 1 0 Bit name SCLKSEL Reserved SOSCCNT SRCCNT Initial value 0 0 1 1 1 Access Bit name Description Low speed oscillation clock select SCLKSEL 0 Internal low speed oscillation 1 External low speed oscillation Always read as 0000 Reserved Always set to 1 External low speed oscillation circuit control SOSCONT 0 disabled 1 enabled Internal low speed oscillation circuit control SRCCNT 0 disabled 1 enabled The SCLKSEL must be set while both the SOSCCNT and the SRCCNT are 1 1 At this time HOSCCLK and HRCCLK must be stable When changing the SCLKSEL in Normal mode the following wait time must be ensured before disable the clock oscillation to be stopped Wait time two cycles of the external low speed oscillation two cycles of the internal low speed oscillation When changing the SCLKSEL in Slow mode the above wait time is not needed IV
418. tion mode to NORMAL the internal high oscillation 1 MHz fix the input pins level 1557 Operating supply current After setting all input and output pins to the input mode Vpp1g the Logic supply voltage to 1 1 V the oscillation mode to SLOW the external oscillation fix the input pins to level and input the 32 768 kHz square wave which has the amplitude from to Vss from XI pin Ipp8 Operating supply current After setting all input and output pins to the input mode the Logic supply voltage to 1 1 V the oscillation mode to SLOW the internal low oscillation 40 kHz fix the input pins to level pp Supply current in HALT After setting all input and output pins to the input mode the oscillation mode to HALTO the internal high oscillation fix the input pins to level Ipp1o Supply current in HALT After setting all input and output pins to the input mode the oscillation mode to HALT2 the external low oscillation fix the input pins to level and input the 32 768 kHz square wave which has the amplitude from to Ves from XI pin Ipp11 12 Supply current in HALT After setting all input and output pins to the input mode the oscillation mode to HALTS the exter nal low oscillation fix the input pins to level and input the 32 768 kHz square wave which has the amplitude from to Vss from XI pin 15013 14 Sup
419. tional programming The protect area is specified with Start Address and Data Size and up to three area can be protected Once Protective Function is activated the data in the protection area can not be overwritten Y Protective Function can not be deactivated by software Security Function Security Function is prevents all areas of the ReRAM reading or programming This function blocks interpolation and leak of the data in ReRAM Security Function is enabled or disabled with a key code 128 bit 1 key code cannot be changed once it is set Keep the key code in a safe place 1 Without the key code ReRAM programming rewriting cannot performed Overview of ReRAM 3 Chapter 18 ReRAM 18 2 Self programming Rewriting Method Self programming allows the ReRAM data programming by setting the FBEWER to Ox4B and using software libraries in the ReRAM reserved area Address MAP FBEWER Ox4B Address 0 03082 Access Disabled 0x03D87 0x04000 Program Area 256 B 0x04100 Data Area 2 KB 0x04900 Program Area 61 75 KB Access Disabled Address MAP FBEWER 0x4B Address 0x03p62 Registers for 0x03D87 Programming 0x04000 Program Area 256 B 0x04100 Data Area 2 0 04900 61 75 0x13FFF Access Disabled 0xX6F009 Reserved Area Rewritabl Ox6FBFF Access Disable
420. tional pulses control 0 Disabled 8 bit PWM output 1 Enabled TM2PSC1 0 TM2BAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 32 110 HCLK 64 X01 SYSCLK 2 X11 SYSCLK 4 Timer 3 Prescaler Selection Register 0x03F87 bp 0 Bit name TM3BAS At reset 0 Access Bit name Description 7to3 5 Always read as 0 Clock source select 000 HCLK 4 010 HCLK 16 TM3PSC1 0 2100 TM3BAS 100 HCLK 64 VIII 6 8 bit Timer Control Registers 110 HCLK 128 X01 SYSCLK 2 X11 SYSCLK 8 Chapter 8 8 bit Timer Timer 4 Prescaler Selection Register CK4MD 0x03F96 bp 5 4 3 0 Bit name TM4ADD1 0 TM4ADDEN TM4BAS At reset 0 0 0 0 Access Bit name Description Always read as 0 TM4ADD1 0 Position of additional pulse within 4 cycles of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle TM4ADDEN PWM output with additional pulses control 0 Disabled 8 bit PWM output 1 Enabled TM4PSC1 0 TM4BAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 32 110 HCLK 64 X01 SYSCLK 2 X11 SYSCLK 4 Timer 5 Prescaler Selection Register CK5MD 0x03F97 bp 0 Bit name TM5BAS At reset 0 Access Bit name Description 71
421. topped PWM output is High 26 8 bit PWM Output Chapter 8 8 bit Timer 8 6 2 Setup Example rOaIrrc m PWM Output Setup Example The PWM output waveform with the 1 4 duty cycle and 19 53 kHz is output from output pin of Timer 0 The oscillation of SYSCLK 2 is 5 MHz The setup procedure and the description of each step are shown below TMOIO output 19 53 kHz gt Figure 8 6 4 Output Waveform of TMOIO Output Pin Setting Register Description 1 Disable the timer counter TMOMD TMOEN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN0 TM0OEN 1 Select the timer output pin 3 PODIR PODIRS 1 Cha ter 7 VO Port Set the timer mode register TMOMD TMOPWM 1 Select the PWM operation 4 TMOMD TMOMOD 0 TMOMD TMOPOP 0 5 TMOMD TMOCK1 0 01 Select the prescaler as the clock source 6 Set the prescaler CKOMD TMOPSC1 0 X0 Select SYSCLK 2 CKOMD TMOBAS 1 7 Set the High period of PWM TMOCC 0x40 Set the High period of PWM output Setup value 256 4 64 0x40 8 Enable the timer counter TMOMD TMOEN 1 Enable the timer count operation 8 bit PWM Output VII 27 Chapter 8 8 bit Timer 8 6 3 PWM Output With Additional Pulse Timer 0 Timer 2 Timer 4 m PWM Output with Additional Pulse Method In this method a pulse whose period equals to one count clock period can be added on a PWM basic waveform Up to 3
422. tput pin selection Register TMIOSEL1 0x03F2F Bit name TM9IOSEL1 0 TM8IOSEL1 0 TM7IOSEL1 0 At reset 0 0 0 0 0 p Bit name Description Always read as 0 Select the pin of Timer 9 from TM9IOA to TM9IOC 00 TM9IOA P07 01 TM9IOB P20 10 TM9IOC P00 11 Prohibited Select the pin of Timer 8 from TM8IOA to TM8IOC 00 TM8IOA P57 01 TM8IOB P06 10 TM8IOC P02 11 Prohibited Select the of Timer 7 from TM7IOA to TM7IOC 00 TM7IOA P04 01 TM7IOB P34 10 TM7IOC P03 11 Prohibited TM9IOSEL 1 0 TM8IOSEL 1 0 TM7IOSEL 1 0 VII 28 Control Registers Chapter 7 I O Port 7 2 11 output Clock output pin control Register Clock output Clock output pin control register selects output clock and changes between General IO GIO and clock output W Clock output Clock output pin control Register CLKOUT 0x03F3E bp 3 2 0 Bit name CLKOCNT1 0 CLKOEN At reset 0 0 0 0 0 0 0 Access R W Bit name Description Always read as 0 Select output clock 00 SCLK 01 HCLK 10 SYSCLK 11 Time base timer output clock for RTC CLKOCNT 1 0 Select the output pin of clock output function CLKOSEL 0 CLKOUTA P05 1 CLKOUTB P57 Select the pin function GIO or clock output CLKOEN 0 GIO 1 Clock output CLKOUTA CLKOUTB Control Registers VII 29 Chapter 7
423. transferred from TXBUFn to a transmission shift reg ister SCnTRB automatically SCnTEMP is set to 1 by storing data to TXBUFn and is cleared to 0 when the data of TXBUFn is sent to SCnTRB and the communication starts When a data is written to TXBUFn during SCnTEMP being 1 the data can not be stored properly m Operation of Reception Data Buffer Register RXBUFn and Reception Data Buffer Empty Flag SCnREMP RXBUFn is a buffer to store the reception data Received data is stored in a received shift register SCnRDB at first and then it is moved to RXBUFn automati cally SCnSTR SCnREMP is set to 1 and SCnTIRQ occurs SCnREMP is cleared to 0 by reading out RXBUFn lt When data reception is received before the previous data is read from RXBUFn SCnORE is set Overrun Error Flag If the next data reception has been completed before a data read from RXBUFn an overrun error occurs and SCnSTR SCnORE is set to 1 Clear SCnORE by program IIC Communication XIII 59 Chapter 13 Serial Interface m Clock Extension in Master Communication SCLn is sampled at falling edges of SCnCLK in Standard Mode or rising edges of SCnCLK in High speed Mode When the transfer clock output from the LSI is High but SCLn is Low the high period of the transfer clock is extended since the slave device keeps SCLn Low I Transfer clock output from the LSI zQ di Do t b I
424. ts RTC Operation Set the CLKEN bit to 1 The RTC starts Chapter 13 Serial Interface Chapter 13 Serial Interface 13 1 Overview The LSI has 4 serial interfaces SCIF0 SCIF1 SCIF2 SCIF3 which support the following types of communica tion Table 13 1 1 Serial Interface Communication Types SCIF0 SCIF1 SCIF2 SCIF3 Clock Synchronous UART Full duplex Multi master IIC Table 13 1 2 shows pins used for each SCIF Each SCIF has two pin groups Group A and Group B In this chapter the suffix of A and is omitted to describe functions of SCIF Table 13 1 2 Serial Interface Pins Data pin SBOOA SBO0B SBO2A 65 P36 P42 SBIOA 58108 SBI2A 64 P35 P41 Clock synchronous SBTOA SBTOB SBT2A P66 P37 P43 SBCSOB SBCS2A P67 P40 P44 TXDOA TXDOB P65 P36 Clock I O pin Chip select pin Data pin Full duplex UART RXDOA RXDOB P64 P35 Data input pin Data I O pin Multi master IIC Clock pin For example in SCIFO Clock Synchronous communication the pin combination of SBOOA lt The combination of pins of Group A and Group B must not be used Group A SBIOA Group A SBTOB Group B is not be allowed XIII 2 Overview 13 1 1 Functions Chapter 13 Serial Interface Table
425. ts TM7BCH 0x03FA1 TM8BCH OxOSFB1 TM9BCH 0x03FC1 Bit name At reset Access Input capture registers are registers that hold the value loaded from the binary counters at a capture trigger Timer n Input Capture Register Lower 8 bits TM7ICL 0x03FA6 TM8ICL OxO3FB6 TM9ICL OxOSFC6 Bit name At reset Access Timer n Input Capture Register Upper 8 bits TM7ICH OxO3FA7 TM8ICH 0x03FB7 TM9ICH OxOSFC7 Bit name At reset Access 16 bit Timer Control Registers Timer 7 dead time preset register 1 and 2 are buffer registers of dead time compare registers Timer 7 Dead Time Preset Register 1 TM7DPR1 OxO3FAE bp 7 6 5 4 3 2 1 Chapter 9 16 bit Timer 0 Bit name TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 At reset Access W Timer 7 Dead Time Preset Register 2 TM7DPR2 0x03FAF bp 7 6 5 4 3 2 1 0 Bit name TM7DPR2 TM7DPR2 TM7DPR2 TM7DPR2 TM7DPR2 TM7DPR2 TM7DPR2 TM7DPR2 At reset Access 1 Timer 7 preset register 1 and 2 must not be changed during IGBT operating 16 bit Timer Control Registers IX 9 Chapter 9 16 bit Timer IX 10 9 2 2 Timer Mode Registers Timer 7 Mode Register 1 TM7MD1 0
426. twice the cycle of the 16 bit full count The pulse output pin is shown in Table 9 1 1 Table 9 5 1 shows register settings that control timer interrupt generation sources and timer pulse output cycles Table 9 5 1 16 bit Timer Interrupt Generation Source and Timer Pulse Output Cycle TMnMD2 TMnIRS1 TMnBCR Interrupt source Timer pulse output cycle TMnOC1 compare match Twice the value of TMnOC1 TMnOC1 compare match Twice the value of TMnOC1 TMnOC1 compare match Twice the TMnBC full count Full count overflow Twice the TMnBC full count Count Timing of 16 bit Timer Pulse Output TMnEN bit Compare register 00001 0001 0000 0001 2000 000 mc 0000 counter Interrupt request TMnIO output Figure 9 5 1 Count Timing of 16 bit Timer Pulse Output 16 bit Timer Pulse Output IX 29 Chapter 9 16 bit Timer In the initial state after releasing reset the timer pulse output is reset and fixed to Low Therefore release the reset of the timer pulse output by setting the TMnMD1 TMnCL to 0 Regardless of whether 1 stopped or in active the timer output becomes Low when the TMnMD1 TMnCL is set to 1 Release the reset of the timer pulse output when the timer count is stopped 9 5 2 Setup Example W Timer Pulse Output Setup Example Here is an example that using Timer 7 a 50 kHz pulse is output from TM7I
427. unction Group 0 interrupt factor PERIODT 0x03FDD register X 4 Control Registers 10 2 2 Programmable Timer Registers Chapter 10 General Purpose Time Base Free Running Timer The timer 6 is a 8 bit programmable counter Programmable counter consists of compare register TM6OC and binary counter TM6BC Binary counter is a 8 bit up counter When the TM6CLRS bit of the timer 6 mode register TM6MD is 0 and the interrupt cycle data is written to the compare register TM6OC the timer 6 binary counter TM6BC is cleared to 0x00 W Timer 6 Binary Counter TM6BC 0x03F78 bp 7 6 5 4 3 2 1 0 Bit name TM6BC7 TM6BC6 TM6BC5 TM6BC4 TM6BC3 TM6BC2 TM6BC1 TM6BCO At reset 0 0 0 0 0 0 0 0 Access R R R R W Timer 6 Compare Register TM6OC 0x03F79 bp 7 6 5 4 R 3 R 2 R 1 R 0 Bit name TM6OC7 TM6OC6 TM6OC5 TM6OC4 6 6 2 TM6OC1 TM6OC0 At reset X X X X X X X X Access The time base timer can be reset by the software The time base timer can be cleared by writing an arbitrary value to the time base timer clear control register TBCLR W Time Base Timer Clear Control Register TBCLR 0x03F7B bp 7 6 5 4 3 2 1 0 Bit name TBCLR7
428. unication completion interrupt SCnTBSY is held at 1 m Reception BUSY Flag SCIFO and SCIF1 When SCnMD1 SCnSBIS is 1 SCnSTR SCnRBSY is set to 1 by writing data to TXBUFn While SCnSTR SCnTEMP is 0 SCnSTR SCnRBSY is cleared to by a communication complete interrupt If SCnTEMP is 1 by writing data to TXBUFn before a communication completion interrupt SCnRBSY is held at 1 1 B Communication BUSY Flag SCIF2 and SCIF3 SCnSTRO SCnTBSY is set to 1 when data is written to TXBUFn When SCnSTR0 SCnTEMP is 0 SCnSTRO SCnTBSY is cleared to 0 by a communication complete interrupt If SCnTEMP is 1 by writing data to TXBUFn before a communication completion interrupt SCnTBSY is held at 1 A Reception Error Flag When receiving new data before reading out the data in RXBUFn an overrun error occurs and the following flags are set For SCIFn n 0 1 SCnSTR SCnORE and SCnSTR SCnERE are set to 1 SCnSTR SCnREMP is cleared to 0 by reading data of RXBUFn and SCnORE and SCnERE are cleared to 0 by a communication complete interrupt when SCnSTR SCnREMP is 0 For SCIFn n 2 3 SCnSTR SCnORE is set to 1 Clear SCnSTR SCnORE by software Clock Synchronous Communication Chapter 13 Serial Interface Consecutive Communication Mode When SCnMD0 SCnCTM is 1 consecutive communication mode 1 selected In this mode when the next data is written to TXBUFn by the specified timing the following
429. upt RTC Alarm1 interrupt Group 1 interrupt which consists of the following interrupts interrupt 30 0x04078 0x00178 LVD interrupt PERHICR OxO3FFE DMA interrupt DMA Addreq interrupt DMA Error interrupt Overview Il 5 Chapter 3 Interrupts 6 W Interrupt Level and Priority The LSI provides three levels of interrupt priority and the lower vector number has priority when several inter rupts with the same interrupt priority level occur For example when the vector 3 and the vector 4 are set to the priority of level 1 and those interrupt trigger occur simultaneously the interrupt of the vector 3 is accepted Maskable interrupts are accepted when LV 1 0 is less than PSW IM1 0 NMI is handled in priority to maskable interrupts Vector 1 Non maskable interrupt Priority Interrupt Vector No 1 Vector 1 Level0 Vector 2 5 6 2 Vector 2 2 3 Vector 5 9 Level1 Vector 3 4 4 Vector 6 5 Vector 3 8 Level2 Vector 7 6 Vector 4 7 7 Figure 3 1 3 Interrupt Priority Example Table 3 1 2 Relation between PSW IM1 0 and acceptable interrupts Mask Level PSW IM1 0 Priority Acceptable Interrupt IM1 IM0 Level 0 0 0 Highest NMI Level 1 0 1 NMI Maskable Interrupt of Level 0 Level 2 1 0 NMI Maskable Interrupt of Level 0 to 1 Level 3 1 1 Lowest NMI Maskable Interrupt of Level 0 to 2 Overview Chapter 3 Interrupt
430. upt control registers Table 3 3 2 External Interrupt Control Register External interrupt Address Register name IRQ0ICR 0x03FE2 External interrupt 0 control register IRQIEN 0x03F4C External interrupt input control register IRQISELO 0x03F4D External interrupt input pin selection register 0 EDGDT 0x03FD4 Both edges interrupt control register NFCTRO1 OxOSEDO Noise filter 01 control register IRQ1ICR 0x03FE3 External interrupt 1 control register IRQIEN 4 External interrupt control register IRQISELO 0x03F4D External interrupt input pin selection register 0 EDGDT 0x03FD4 Both edges interrupt control register NFCTRO1 OxOSEDO Noise filter 01 control register IRQ2ICR Ox03FE4 External interrupt 2 control register IRQIEN 0x03F4C External interrupt input control register IRQISELO 0x03F4D External interrupt input pin selection register 0 EDGDT OxOSFD4 Both edges interrupt control register NFCTR23 OxOSED1 Noise filter 23 control register IRQSICR Ox03FE5 External interrupt 3 control register IRQIEN 0x03F4C External interrupt input control register IRQISELO 0x03F4D External interrupt input pin selection register 0 EDGDT 0x03FD4 Both edges interrupt control register NFCTR23 OxOSED1 Noise filter 23 control register IRQ4ICR Ox03FE6 External interrupt 4 control register IRQIEN 0x03F4C External interrupt input control register IRQISELO 0x03F4D Externa
431. uzzer output frequency 10 MHz 0 0 0 0 61 kHz 10 MHz 0 0 1 1 22 kHz 4 MHz 0 1 0 0 98 kHz 4 MHz 0 1 1 1 95 kHz 2 MHz 1 0 0 1 95 kHz 2 MHz 1 0 1 3 91 kHz 32 kHz 1 1 0 2 kHz 32 kHz 1 1 1 4 kHz m Buzzer Output Pin Buzzer output pin and the polarity of it is decided with BUZCNT Refer to BUZCNT in 7 2 14 Buzzer output Buzzer output pin control Register for more information Operation XV 5 Chapter 15 Buzzer 15 3 2 Setup Example c r m Setup Example The following example shows how to output the buzzer of 2 44 kHz from BUZB pin under the 10 MHz of Setup Procedure Register Description Set the buzzer frequency BUZCTR Set the BUZCTR BUZS to 010 Set the buzzer output pin BUZCNT Select the P02 as the buzzer output pin by POOUT Setting the BUZCNT BUZEN to 1 PODIR Setting the BUZCNT BUZSEL to 1 Select the output direction and the output data of 1 at P02 Set the POOUT POOUT to 0 Set the PODIR PODIR2 to 1 Enable buzzer output BUZCTR Set the BUZCTR BUZOE to 1 Disable buzzer output BUZCTR Set the BUZCTR BUZOE to 0 Low level signal is output from buzzer output pin XV 6 Operation Chapter 16 A D Converter ADC Chapter 16 A D Converter ADC 16 1 Overview This LSI has an analog to digital converter ADC with 12 bits resolutions This ADC has a sample hold circuit the channel 0 to c
432. ve occurred rewrite the value of stack address or saved data to prevent the standby transition program execution a An interrupt may be generated between the step 9 and step 10 Setting Example Chapter 7 Port Chapter 7 I O Port VII 2 7 1 Overview 7 1 1 I O Port Overview I O port is controlled with the following registers Output Register PhOUT Input Register PnIN Direction Control Register PnDIR Pull up Control Register PnPLU Special Function Control Register PhODC PnNLC etc Table 7 1 1 shows the status of each port at LSI reset Table 7 2 1 shows the list of port control registers Table 7 1 1 I O port status at reset single chip mode mode Pull up resistor I O port Special function Port 0 Input mode No pull up resistor I O port Port 1 Input mode No pull up resistor port 412 VO port Port 3 Input mode No pull up resistor port Port 4 Input mode No pull up resistor port Port 5 Input mode No pull up resistor port Port 6 Input mode No pull up resistor port Port 7 Input mode No pull up resistor port Port 8 Input mode No pull up resistor port Overview 7 2 Control Registers Register Address 0x03F10 Table 7 2 1 I O Port Control Registers List Function Port 0 output register POIN PODIR 0x03F20 0x03F30 Port 0 input register Port 0 directi
433. view 17 Chapter 3 Interrupts 18 Group interrupt control register Setup Procedure Setup procedures of the group interrupt control register set by the software are as follow Setup Procedure Description 1 Disable all maskable interrupts PSW bp6 MIE 0 2 Clear PERInDT PERIODT PRI1DT 3 Set PERInEN PERIOEN PERI1EN 4 Set the interrupt level PERInICR PERIOICR PERI1ICR 5 Enable all maskable interrupts PSW bp6 MIE 1 6 Accept interrupt 7 Clear the interrupt request bits of PERInDT PERIODT PERITDT 1 Clear PSW MIE to disable all maskable interrupts which is needed especially when xICRis changed 2 Clear PERInDT by reading the value of PERInDT and setting the register to it When operating the interrupts that occurred before this setting please don t clear the applicable bits 3 Enable the interrupt occurrence 4 Set the interrupt level by PERInICR PERInLV1 0 5 Enable all maskable interrupts 6 Read the value of PERInDT and distinguish the interrupt factor by software 7 Clear the interrupt request bit by setting the applicable bits to 1 setting of PERInEN Please clear it by referring to setup procedure a When an interrupt occurs the corresponding bit of PERInDT is set to 1 regardless of the Overview Chapter 3 Interrupts m Sample program of Group interrupt service routine mov PERIn
434. wn resistor Input pin Figure 1 6 2 Unused Pin only for input Current Through Current Pch Input Pin Input Nch 0 3 Input voltage Vpp3o 3 V Structure of Input Inverter Characteristics of Input Inverter Figure 1 6 3 Structure and Characteristics of Input Inverter 1 36 Cautions for Circuit Setup Chapter 1 Overview and Output pin When the direction of unused I O pin is set to input pull up or down the pin with the resistor the value of which is typically between 10 and 100 When the unused I O pin is configured as output it should be left unconnected Output Control Pull up Output Control resistor Output OFF Output OFF Data Data Pull down resistor Input Enable Input Enable Figure 1 6 4 Unused I O Pins m Recommended Condition of Each Pin 3 Pin name Input Output Recommended condition of unused pins POO to 07 Inout Pull up or down the pins with the resistor the value of which is typically between 10 and P10 to P17 P 100 kO 1 2 P20 to P26 P30 to P37 P40 to P47 Input output 50 to 57 Output Unconnect the pins P60 to P67 P70 to P77 P80 to P85 XI Input Unconnect the pins XO Output Unconnect the pins When connecting capacitors between P27 and Vgg the discharge diodes between P27 and P27 Input output V 2030 Should be connected VREFP Set VREFP Pull up the pin to when auto reset
435. x Vicg is output The reference voltage 0 9 V to 1 8 V is output 1 3 to 1 8duty 1 3bias VDD30 input VLC1 VLC2 VLC3 55 C1 C2 Figure 17 3 3 Connection example of LCD power supply when BSTVOL REFVOL are used the LCDMDO LCUPCKDIV2 0 and LCDMDO LCUPCKS2 0 or generate LCD drive voltage a When the brightness of LCD panel is not enough increase the frequency of LCUPCK with outside the LSI Refer to lt gt In the case of generating the drive voltage outside the LSI Operation XVII 23 Chapter 17 LCD 17 3 5 LCD Frame Frequency Setup B nv mt SKMxx O04 m LCD Frame Frequency Setup The frequency of LCDCLK is determined with the LCDMD3 LCCKS2 0 and LCDMD3 LCCK3 0 LCD frame frequency is determined with the frequency of the LCDCLK and the LCDMD2 LCDY2 0 The following table shows the relation between the typical input frequency SCLK 32 kHz and LCD clocks Table 17 3 5 Input Frequency and LCD Clock Static Clock source Clock Frame frequency Hz LCCKS2 0 LCCK3 0 Static 1 2 duty 1 4 duty 1 8 duty 000 SCLK selected 0000 4096 4096 2048 1024 512 0001 2048 2048 1024 512 256 0010 1024 1024 512 256 128 0011 512 512 256 128 64 0100 256 256 128 64 32 0101 128 128 64 32 16 0110 64 64 32 16 8 0111 32 32 16 8 4 1000 16 16 8 4 2 1001 8 8 4 2 1 XVII 24 Operation Chapter 1
436. x03FA8 T TT TT Brame Tro umso 0 1 0 0 0 0 0 At reset 0 Access R R W R W R W R W R W R W R W Bit name Description Always read as 0 Select capture trigger edge T7ICEDG1 0 Falling edge 1 Rising edge Timer output enable 0 Enabled 1 Disabled reset Control timer count 0 Disabled 1 Enabled Select count clock 00 1 1 clock TM7PS1 0 01 1 2 clock 10 1 4 clock 11 1 16 clock Select clock source 00 HCLK TM7CK1 0 01 SYSCLK 10 TM7IO input 11 SCLK 16 bit Timer Control Registers Chapter 9 16 bit Timer W Timer 7 Mode Register 2 TM7MD2 0x03FA9 Bit name T7ICEDGO T7PWMSL TM7BCR TM7PWM TM7IRS1 T7ICEN At reset 0 0 0 0 0 0 Access Bit name Description Select capture trigger edge T7ICEDGO 0 Both edges 1 Specified edge Select PWM mode T7PWMSL 0 Set duty through TM7OC1 1 Set duty through TM70C2 Select timer clear source TM7BCR 0 Overflow by full count 1 Match between TM7BC and TM7OC1 Select timer output waveform TM7PWM 0 Timer output 1 PWM output Select timer interrupt source TM7IRS1 0 Counter clear 1 Match of TM7BC and TM7OC1 Input capture operation enable T7ICEN 0 Disabled 1 Enabled Select capture trigger 00 External Interrupt 0 input signal T7ICT1 0 01 External Interrupt 1 input signal 10 External Interrupt 2 in
437. y be read XI 6 Control Register 11 23 Frequency Adjustment Register Chapter 11 RTC Time Base Timer RTC TBT The frequency of T1HZ to T128HZ be adjusted with the TBTADJL the TBTADJH The following table shows the frequency adjustment rate of 1 2 Adjustment value 128 sec x Frequency adjustment rate x 2097152 Adjustment period sec in decimal Frequency adjustment rate x 0x200000 in hexadecimal At Adjustment period 128 sec Table 11 2 2 lists the setting value of TBTADJ10 0 and frequency adjustment rate Table 11 2 2 Frequency Adjustment Rate Adjustment period 128 sec TBTADJ10 0 Hexadecimal Frequency adjustment rate ppm 487 80 487 33 486 85 Control Register XI Chapter 11 RTC Time Base Timer RTC TBT Time Base Timer Frequency Adjustment Register for Lower Bits TBTADJL 0x03EEE Bit name At reset Access Bit name TBTADJ10 8 At reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W m Sm 7 3 Always read as 0 2 0 TBTADJ10 8 Frequency adjustment setting upper 3 bits RTC calculates the calendar with the clock generated by RTC TBT and therefore the calen dar calculation is affected by the frequency adjustment XI 8 Control Register C
438. z 20 Vppao 1 1 V to 3 6 V Internal High Speed Oscillation HRCCLK 10 8 MHz 3 Vppao 1 8 V to 3 6 V 1 MHz 10 Vppao 1 3 V to 3 6 V MNIOILRO2D does not have external high speed oscillation HOSCCLK Internal Operating Clock System Clock SYSCLK 10 MHz Max SYSCLK is generated by dividing HCLK or SCLK and the division ratio is 1 2 4 8 16 or 32 HCLK HOSCCLK or HRCCLK SCLK SOSCCLK or SRCCLK MNIOILRO2D cannot be selected HOSCCLK 1 2 Hardware Features Chapter 1 Overview Interrupt Circuit 31 internal interrupts except for 8 external interrupts MN101LR02D 29 internal interrupts except for 3 external interrupts 1 channel Data transfer size 8 bits 16 bits Maximum transfer counts 1023 Activation trigger external interrupts internal interrupts software setting the DMA start bit Watchdog Timer WDT Function Clock Source Timer Counter 1st watchdog time out generates NMI and 2nd consecutive time out generates a LSI reset WDTCLK SOSCCLK or SRCCLK 13 units General purpose 8 bit timer Timer 0 1 2 3 4 5 6 units General purpose 16 bit timer Timer 7 8 9 3 units 8 bit free run Timer 6 Time base timer 1 unit each RTC time base timer RTC TBT 1 unit Real Time Clock RTC 1 unit Timer 0 Function Clock Source Timer 1 gt Function Clock Source Timer 2 gt
439. zation with the count clock 16 bit High Precision IGBT Output with Variable Period Duty IX 51 Chapter 9 16 bit Timer 16 bit High Precision IGBT Output Operation Timer 7 When setting the TM7MD4 T7NODED to 1 the IGBT waveform with a specified duty can be generated by set ting the IGBT cycle in 7 1 and the High period of duty in TM7OC2 The high precision IGBT output function can be used in Timer 7 Table 9 10 1 IGBT Output Pin x m TM7IOA output TM8IOA output IGBT output pin TM7IOB output TM8IOB output TM7IOC output 8 output Table 9 10 2 IGBT Trigger TM7MD3 T7IGBT1 0 IRQO falling edge T7IGBTTR IRQO rising edge IRQ1 falling edge IRQ1 rising edge IRQ2 falling edge IRQ2 rising edge TM7EN count operation One shot Pulse Output One shot pulse can be output by setting the TM7MD4 T7ONESHOT to 1 IX 52 16 bit High Precision IGBT Output with Variable Period Duty Chapter 9 16 bit Timer W Count timing of High Precision IGBT Output Normal Timer 7 s Gi TM7EN bit Compare x x x N register 1 i i I I I register 2 i IGBT trigger m Ce Kec C Gp Xn TM7IO output Ll IGBT output A B 0 TM8IO output IGBT output Figure 9 10 1 Count timing of High Precision IGBT Output Normal

MN101LR05D/04D/03D/02D LSI User`s Manual

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