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Application Note Designing a Minimal PowerPC™ System

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1. T CLK lu T 2u 3u 4u 5u Time Seconds Figure 14 Pipelined Burst SRAM Single Beat Read Write Minimal PowerPC System Design MOTOROLA Figure 15 shows pipelined burst SRAMs that need ADSC asserted to start then TA asserted for a burst of four beats for the data After the first beat BAA is asserted to increment the address to the next location At the end of each transfer ADSC is strobed to deselect the SRAM CLK A HIGHO A HIGH1 A LOW29 A LOW30 A LOW31 AACK L TAL TEAL ADSC L BAA L SCS L SOE L BWE LO BWE_L1 BWE_L2 BWE_L3 BWE_L4 BWE_L5 BWE_L6 BWE_L7 RST_L HRESET_L IRESET COPHRST L MRESET f f f f f lu 2u 3u 4u 5u T CLK Time Seconds Figure 15 Pipelined Burst SRAM Burst Read Write MOTOROLA Minimal P
2. If this is not possible an alternative is to employ an inexpensive low skew clock generator such as the Motorola MPC904 as shown in Figure 19 Using a crystal or an oscillator with this device each component can have a dedicated clock signal This can make the board routing much easier and other devices in the Motorola MPC9xx family can provide other clocks that may be needed along with the primary system needs increasing integration MPC904 a equal length I j 4 J traces to each device NI PowerPC SRAM SRAM CPU Figure 19 MPC904 Clock Connection Note MPC604 class devices are not fully static and have minimum clock frequencies MPC603 and MPC750 class devices are fully static Refer to the respective hardware reference datasheets for details 32 Minimal PowerPC System Design MOTOROLA Part 5 Reset In order to properly condition a PowerPC processor the HRESET signal must be asserted whenever the system initially powers up and whenever the processor power supply or supplies fall below 5 of the nominal voltage described in the hardware specification The JTAG TRST signal must be asserted at reset as well to initialize the scan chain to a known state In addition the initial power up sequence requires that the HRESET signal be asserted for a minimum of 255 clocks in order to properly initialize the clock PLL and initialize hardware sign
3. 1 ELSE TEA L lt 0 END IF END PROCESS END BEHAVIOR LIBRARY LAT VHD USE LAT VHD VHD PKG ALL LIBRARY ieee USE ieee std logic 1164 all LIBRARY synth MOTOROLA Minimal PowerPC System Design BEAT3 0 23 USE synth vhdlsynth all ENTITY CYCLER IS PORT CTIME IN std logic vector 3 DOWNTO 0 CLK CLAIM L DOERR L RST L SCS L TBST L WE L IN std logic BACK L ADSC L BAA L TA L TEA L OUT std logic END ARCHITECTURE BEHAVIOR OF CYCLER IS COMPONENT SHELL CYCLER PORT CLK CLAIM L CTIMEO CTIME1 CTIME2 CTIME3 DOERR L RST L SCS L TBST L WE L IN std logic BACK L ADSC L BAA L TA L TEA L OUT std logic END COMPONENT BEGIN SHELL1 CYCLER SHELL CYCLER PORT MAP CLK gt CLK CLAIM L gt CLAIM L CTIME0 gt CTIME 0 CTIME1 gt CTIME 1 CTIME2 gt CTIME 2 CTIME3 gt CTIME 3 DOERR L gt DOERR L RST L gt RST L SCS L gt SCS L TBST L gt TBST L WE L gt WE L AACK L gt AACK L ADSC L gt ADSC L BAA L gt BAA L TA L gt TA L TEA L gt TEA L END BEHAVIOR CONFIGURATION SHELL2 CYCLER OF CYCLER IS FOR BEHAVIOR END FOR END SHELL2 CYCLER The preceeding code was produced by a state machine compiler so there are no comments and it is not very readable The code uses a one hot encoding one register encodes each state so each clock cycle the registers are reloaded with the encoded next state calculations in a typical Moore machine fashion The remainder of the code computes
4. CHIPSEL is if cycle is claimed and a 00 and claim L 0 a 01 and claim L 0 a 10 and claim L 0 at 11 and claim L 0 soe L lt 0 WHEN a 00 ELSE 1 xoe_L lt 0 WHEN a 01 or a 10 ELSE 1 foe L lt 0 WHEN a 11 ELSE 1 changed SET TIMER BEGIN IF fcs L 0 18 Provide corresponding timer value THEN ctime lt 0011 and claimL 0 and weL and claimL 0 and we L and claimL 0 and weL and claimL 0 and weL PROCESS fcs L xcs L 0 Flash Minimal PowerPC System Design 80 ns 15ns clocks 66 MHz corresponding address is presented the cycle is claimed and is not 1 1 1 1 Note that SRAM is not timer controlled so any value may be used All of these values should be changed if the bus frequency is If the clock rate is increased the system may fail cycles will be wasted If lowered clock Note there is a three clock overhead in the setup and termination of timed cycles one on entry one during AACK TA and one exiting when the timer is zero timing constants are offset by 3 Therefore 6 3 3 clocks MOTOROLA ELSIF xcs L 0 0 THEN ime lt 1001 ctime lt 1001 Slow I O 180 ns 15ns clocks 66 MHz 12 3 gt 9 clocks ELSE ctime lt 0001 Fast I O 60 ns 15ns clocks 66 MHz 4 3 gt 1 clocks EN
5. Figure 28 COP Connector Diagram NOTE There is no standardized way to number these headers consequently many different pin numbers have been observed on a variety of schematics Some are numbered top to bottom then left to right while others use left to right then top to bottom while still others number the pins clockwise from pin one as with an IC Regardless of any local standardization when adding a COP port to a system insure that the signal placement follows that of Figure 28 when viewed from above the connector The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals Table 6 shows the pin definitions Table 6 COP Pin Definitions Pins Signal Connection Applicable Processor Special 1 TDO TDO All See section 8 2 2 QACK QACK 603e 603ev 740 750 3 TDI TDI All 4 TRST TRST All Add 2K pulldown to ground Must be merged with on board TRST if any 5 RUN STOP RUN 604 604e Leave no connect for all other processors 6 VDD SENSE VDD All Add 2K pullup to VDD MOTOROLA Minimal PowerPC System Design 39 Table 6 COP Pin Definitions Continued Pins Signal Connection Applicable Processor Special 7 TCK TCK All 8 PRESENT Optional All Add 10K pullup to VDD May be used to separate JTAG scan chains see section 8 2 9 TMS TMS All 10 N A 11 SRESET SRESET All Merge with on board SRESE
6. LED output drivers xcsled buffer std_logic d in std logic vector 0 to 7 data bus input probel buffer std logic internal monitors monitor1 buffer std_logic ViewSynthesis bug end PORT DEFINITION AND ENTITY ARCHITECTURE BEHAVIOR OF MC is COMPONENT BYTEDEC stable 60X bus address current transfer size asserted if transfer is burst asserted if transfer is claimed asserted if transfer is write byte lane write selects stable 60X bus address asserted for active cycles asserted for write cycles SRAM chip selects amp enable Flash chip selects amp enable I O chip selects I O output enable std logic vector 3 downto 0 4 bit time value PORT a in std logic vector 29 to 31 tsiz in std logic vector 0 to 2 tbst_L in std_logic claim L in std_logic we_L in std_logic bwe_L buffer std logic vector 0 to 7 i END COMPONENT COMPONENT CHIPSEL PORT a in std logic vector 0 to 1 claim L in std logic we L in std_logic scs L soe L buffer std_logic fcs L foe L buffer std logic xcs L buffer std logic vector 0 to 1 xoe L buffer std logic ctime buffer i END COMPONENT COMPONENT INT PORT irg in std logic vector 0 to 3 int L buffer std_logic i END COMPONENT COMPONENT CYCLER PORT CTIME IN std logic vector 3 DOWNTO 0 MOTOROLA CLK CLAIM L DOERR_L RST L S
7. read or write BEGIN Convert transfer size and address into byte lane enables Write masking occurs later be L 0 lt 0 WHEN tsiz 001 and a 000 byte or tsiz 010 and a 000 half word or tsiz 100 and a 000 word or tsiz 000 and a 000 double word or tsiz 011 and a 000 three byte MOTOROLA Minimal PowerPC System Design 15 be L 1 lt be L 2 lt be L 3 lt be L 4 lt be L 5 lt be L 6 lt be L 7 lt Now mask bwe L 0 lt bwe L 1 lt bwe L 2 lt 16 or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN t
8. the size shown in an approximation of the actual size RS232 RS232 Serial Port 1 Serial Port 2 FPGA In Circuit Progra PowerPC MPC603 Expansion Connector ispL SI2064V JONVHVITO 134208 YOE O PBSRAM 64K x 32 Flash Flash 512K x 16 512K x 16 Flash Flash 512K x 16 512K x 16 Figure 31 Excimer Minimal System Board This design uses the standard 255 pin BGA pattern to allow any MPC603x or MPC604x device to be populated An MPC750 design could be easily created by expanding the size for an additional two PBSRAM devices A user defined I O area allows customer specific interfaces to be attached Miscellaneous discrete components are not shown Part 10 Conclusion A PowerPC design can be easily implemented with a small amount of hardware by following the examples listed in this paper The resulting system will exhibit fast memory access times and will allow benchmarking of various processors If desired the design can be enhanced with the following features Stream accesses to the same page of SRAM Handle SRAM deselect in parallel with other accesses even SRAM to eliminate dead time Support burst flash memory Move cycle recognition into the state machine this eliminates one clock latency on all memory cycles
9. NOT TIMERO AND NOT TIMER1 amp NOT TIMER1 amp NOT TIMER1 amp NOT TIMER1 AND NOT TIMER2 amp NOT TIMER2 amp NOT TIMER2 amp NOT TIMER2 AND NOT TIMER3 amp NOT TIMER3 amp NOT TIMER3 amp NOT TIMER3 AND 0000 OR IDLE amp IDLE amp IDLE amp IDLE AND DOERR L amp DOERR L amp DOERR L amp DOERR L AND SCS L amp SCS L amp SCS L amp SCS_L AND NOT CLAIM L amp NOT CLAIM L amp NOT CLAIM L amp NOT CLATM L AND TBST L amp TBST L amp TBST L amp TBST L AND CTIME3 SCTIME2 amp CTIME amp CTIMEO OR DESEL amp DESEL amp DESEL amp DESEL AND 1111 AND 0000 OR ERRORS ERROR amp ERROR amp ERROR AND 1111 AND 0000 OR IDLE amp IDLE amp IDLE amp IDLE AND NOT DOERR L amp NOT DOERR L amp NOT DOERR L amp NOT DOERR L AND 0000 OR IDLE amp IDLE amp IDLE amp IDLE AND DOERR L amp DOERR L amp DOERR L amp DOERR L AND NOT CLAIM L amp NOT CLAIM L amp NOT CLAIM L amp NOT CLAIM L AND NOT SCS L amp NOT SCS L amp NOT SCS L amp NOT SCS LJAND TBST L amp TBST L amp TBST L amp TBST L AND 0000 OR IDLE amp IDLE amp IDLE amp IDLE AND DOERR L amp DOERR L amp DOERR L amp DOERR L AND NOT TBST L amp NOT TBST L amp NOT TBST L amp NOT TBST LJAND NOT CLAIM L amp NOT CLAIM L amp NOT CLAIM L amp NOT CLAIM L AND NOT SCS L amp NOT SCS L amp NOT SCS L amp NOT s
10. arise from the need to handle misaligned transfers by breaking them into two separate cycles refer to the MPC603e and EC603e RISC Microprocessor User s Manual or the MPC750 RISC Microprocessor User s Manual for details on this process These cycles do not occur if unaligned transfers do not occur Since many C compilers do not generate such code the lines for three byte handling can be deleted to simplify the controller and reduce gate count 3 5 3 Chip Select The chip select module shown in Figure 11 generates the four chip select signals and selects the proper time delay for accesses to memory this information is used by the cycler module SCS SOE chipsel EEG XCS 07 XOE CTIME 0 3 Figure 11 Chip Select Module Table 5 shows the chip select actions based upon the address Table 5 Chip Select Encodings A 0 1 I O Area Time 66 MHz Bus Clock Count Timer Value 00 High speed SRAM array N A N A N A 01 High speed I O 60 ns 4 1 10 Slow speed I O 180 ns 12 9 11 Flash boot ROM 80 ns 6 3 The timer values in Table 5 have a constant overhead of three subtracted from the expected timer values This constant overhead is due to the start delay the final TA assertion and one clock needed to detect a zero count on the timer So for best performance the actual timer values are offset by 3 In examining chipsel the SRAM chip select is found to be fairly straightforward the other chip
11. controller the databus is wired and ready to accept a more complicated version if desired Minimal PowerPC System Design MOTOROLA INT_1 INT PORT MAP irq gt irq int L gt int L Assert HRESET to CPU when general reset is asserted or when COP resets it The active high RESET is only asserted on the general reset not by COP hreset_L lt 0 WHEN altrst_L 0 or cophrst L 0 ELSE 1 mreset lt 1 WHEN hreset_L ELSE 0 0 Set the LED monitor outputs when any I O action occurs While you could tie it to the chip selects LEDs need some current so it is best to keep them isolated fosled lt 1 WHEN fcs L 0 ELSE 0 scsled lt 1 WHEN scs L 0 ELSE 0 xcsled lt 1 WHEN xcs L 0 0 or xcs L 1 0 ELSE 0 END BEHAVIOR MOTOROLA Minimal PowerPC System Design 27 3 6 Waveforms This section shows several timing waveforms Figure 14 shows single beat access to SRAM which is similar to I O and Flash except that no timer is used to keep the performance high In this waveform the data is available on the second clock after the TS signal is asserted 28 TSIZO TSIZ1 TSIZ2 TBST 1 TEA L ADSC 1 BAA L scs_L SOE_L BWE Li BWE L BWE_L BWE_L BWE_L BWE_L BWE Li BWE L RST_L
12. design details http Awww mot com SPS PowerPC teksupport teklibrary index html PowerPMC750 Schematics Example of interrupt controller http Awww mot com SPS PowerPC teksupport teklibrary index html MOTOROLA Minimal PowerPC System Design 43 Mfax is a trademark of Motorola Inc The PowerPC name the PowerPC logotype PowerPC 603e and PowerPC 604e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical exp
13. either assert the claim 1 or doerr 1 signal to cause the appropriate actions to conclude the transfer cycle which is handled in the bus state machine cycler The general architecture of start is shown in Figure 9 WE_L CLAIM_L DOERR_L Figure 9 Start Detector Module The TT 0 4 signals do not change during the address tenure whether burst or single beat so the outputs remain valid until the memory controller asserts AACK The start module provides the global CLAIM_L signal used by other modules to detect whether a cycle is in progress or the DOERR_L signal used to terminate unclaimed cycles and a write signal WE_L to determine that the cycle is a write cycle These signals are used exclusively by other modules and remain valid until the memory controller completes the cycle by asserting AACK The VHDL code for this module is TIDEC monitors the TT bus and determines whether the TT is of interest to the MC or not If so a signal is provided for start and tt we L reflects the read write status NOTE TTDEC must not be optimized or errors will occur when hierarchical optimization is performed TTl and TT2 will be optimized away making it impossible to connect TIDEC to MC this is a bug in ViewSynthesis Recommended procedure is to dissolve TIDEC into it s parent level MC 12 Minimal PowerPC System Design MOTOROLA before optimization ViewSynthes
14. global or expensive monitor PROCESS clk rst L BEGIN IF rst_L 0 THEN we L lt 1 claim L lt 1 doerr L lt 1 sese se ELSIF clk EVENT and clk 1 THEN IF ts_L 0 and tt take 1 or claimL 0 and aack L 1 THEN claim L lt 0 we L lt tt we L ELSE claim L lt 1 we L lt 1 END IF IF tsL 0 and tt_take 0 or doerr L 0 and aack L 1 THEN doerr L lt 0 ELSE doerr L lt 1 END IF END IF END PROCESS END BEHAVIOR TS and something we want claimed but not AACK d else AACK or no claim TS and something we dont want errored but not AACK d else AACK or claim 3 5 2 Byte Write Enable The next group of signals to generate are the byte lane write enables BWE 0 7 These signals are generated by using the transfer size signals TSIZ 0 2 along with the lower address bus signals A 29 31 to determine which byte lanes should be active 14 Minimal PowerPC System Design MOTOROLA TSIZ 0 2 EVEN bytedec 8 TBST BWE 0 7 we_L _3 gt Figure 10 Byte Write Enable Module Note that the bytedec module examines the decoded write status WE_L but not CLAIM so the byte lane enables are asserted for all write cycles regardless of the activity of the CLAIM signal This is acceptable as long as the corresponding chip select signals disable the attached memory and I O devices which i
15. lt next TIMERO END IF END PROCESS PROCESS BEAT1 BEAT2 BEAT3 BEAT4 BURST CLAIM L CLOCK COUNT CTIMEO CTIMEL CTIME2 CTIME3 DESEL DOERR L ERROR IDLE SCS I L SINGLE TBST L TIMERO TIMERL TIMER2 TIMER3 WE L TIMER BEGIN IF BURST 1 THEN next BEAT1 lt 1 ELSE next_BEAT1 lt 0 END IF IF WE L 1 AND BEATI 1 THEN next BEAT2 lt 1 ELSE next BEAT2 lt 0 END IF IF BEAT2 1 THEN next BEAT3 lt 1 ELSE next BEAT3 lt 0 END IF IF WE I 0 AND BEATI 1 OR BEAT3 1 OR TIMERO 0 AND TIMER1 0 AND TIMER2 0 AND TIMER3 0 AND CLOCK 1 OR SINGLE 1 THEN next_BEAT4 lt 1 ELSE next BEAT4 lt 0 END IF IF DOERR L 1 AND TBST L 0 AND CLAIM I 0 AND SCS I 0 AND IDLE 1 THEN next BURST lt 1 ELSE next_BURST lt 0 END IF IF TIMERO 1 AND CLOCK 1 OR TIMERI 1 AND CLOCK 1 OR TIMER2 1 AND CLOCK 1 OR TIMER3 1 AND CLOCK 1 OR COUNT 1 THEN next_CLOCK lt 1 ELSE next_CLOCK lt 0 END IF IF DOERR I 1 AND SCS I 1 AND CLAIM I 0 AND TBST I 1 AND IDLE 1 THEN next COUNT lt 1 ELSE next COUNI lt 0 END IF IF BEAT4 1 THEN next DESEL lt 1 ELSE next DESEL lt 0 END IF IF DOERR I 0 AND IDLE 1 THEN next ERROR lt 1 ELSE next _ERROR lt 0 END IF IF DESEL 1 OR ERROR 1 OR DOERR 1 1 AND SCS L 1 AND TBST
16. selects differ in that a 4 bit timer value is generated to add delay to the assertion of TA MOTOROLA Minimal PowerPC System Design 17 The code for this module is All rights reserved Copyright 1998 by Motorola Inc Author Gary Milliorn Revision 0 2 Date 6 10 98 Notes CHIPSEL is the portion of the MC which decodes addresses and provides corresponding chip select outputs along with a clock timer value which determines the rate of memory accesses All logic is active low when appended with a L Passed speedwave check 6 16 98 library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all ENTITY CHIPSEL is PORT a claim L we L scs L s L fos L foe L xcs L xoe L ctime i buffer buffer buffer buffer buffer end PORT DEFINITION AND ENTITY std logic vector std logic std logic std logic std logic std logic vector 0 to 1 std logic std logic vector 3 downto 0 stable 60X bus address asserted for active cycles asserted for write cycles SRAM chip selects amp enables Flash chip selects amp enables I O chip selects I O output enable 4 bit time value ARCHITECTURE BEHAVIOR OF BEGIN Assert chip select scs L lt 0 WHEN ELSE xcs_L 0 lt 0 WHEN ELSE xcs _L 1 lt 0 WHEN ELSE fcs L 0 WHEN ELSE Assert corresponding output enables OE L if a write cycle
17. std logic arith all use ieee std logic unsigned all INT ENTITY INT is PORT irg in std logic vector 0 to 3 interupt inputs variable polarity int_L buffer std_logic interrupt output ARCHITECTURE BEHAVIOR OF INT is BEGIN int L lt 0 WHEN irg 0 1 or irq 1 or irq 2 ELSE 1 1 active high interrupts 0 active low interrupts END BEHAVIOR 38 Minimal PowerPC System Design MOTOROLA Part 8 COP The common on chip processor COP function of PowerPC processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor While adding a COP connection to any PowerPC system adds little to no cost it does add many benefits breakpoints watchpoints register and memory examination modification and other standard debugger features are possible through this interface The COP interface has a standard header for connection to the target system based on the 0 025 square post 0 100 centered header assembly often called a Berg header The connector typically has pin 14 removed as a connector key as shown in Figure 28 a e Ef 7 G NA ES DEE Spa S be Vg GR ie ie GE TOP VIEW EY Pins 10 12 and 14 are no connects No pin Pin 14 is not physically present QACK LU Z 12 LL Z p LU LU 09 io a Q Q
18. 1 0 AND IDLE 1 OR DOERR I 1 AND CLAIM I I AND IDLE 1 THEN next IDLE lt 1 ELSE next_IDLE lt 0 END IF if DOERR I 1 AND CLAIM I 0 AND SCS I 0 AND TBST I 1 AND IDLE 1 THEN next SINGLE lt 1 ELSE next_SINGLE lt 0 END IF TIMER lt BEATI amp BEATI amp BEAT1 amp BEAT1 AND WE _L amp WE L amp WE L amp WE L AND 0000 OR BEATI amp BEATI amp BEATI amp BEAT1 AND NOT WE L amp NOT WE L amp NOT WE L amp NOT WE L AND 0000 OR 1111 AND BEAT2 amp BEAT2 amp BEAT2 amp BEAT2 AND AND BEAT3 amp BEAT3 amp BEAT3 amp BEAT3 AND 1111 0000 OR BEAT48 BEAT48 BEAT48 BEAT4 AND 1111 AND 0000 OR BURST amp BURST amp BURST amp BURST AND 1111 AND 0000 OR Minimal PowerPC System Design MOTOROLA CLOCK amp CLOCK amp CLOCK amp CLOCK AND TIMER3 amp TIMER3 amp TIMER3 amp TIMER3 OR TIMER2 amp TIMER2 amp TIMER2 amp TIMER2 OR TIMERI amp TIMER1 amp TIMER1 amp TIMER1 OR TIMERO amp TIMERO amp TIMERO amp TIMERO AND TIMER3 amp TIMER2 amp TIMER1 amp TIMERO 0001 OR COUNT amp COUNT amp COUNT amp COUNT AND 1111 AND TIMER3 amp TIMER2 amp TIMER1 amp TIMERO 0001 OR CLOCK amp CLOCK amp CLOCK amp CLOCK AND NOT TIMERO amp NOT TIMERO amp NOT TIMEROS
19. 2CLK_OUTB L2SYNC OUT L2SYNC IN and L2ZZ Because the L2 interface is completely separate from the system bus it does not affect the design of a minimal system in any way Refer to the MPC750 RISC Microprocessor Hardware Specifications or the MPC750 Processor Cache Module Hardware Manual for further details 4 Minimal PowerPC System Design MOTOROLA Part 3 Memory System Design The one fairly complicated portion of a minimal system is the interface to the processor data bus Unlike CISC processors RISC processors do not typically perform data re alignment so the data from each external device must be placed on the proper data lane To attempt to use an 8 bit memory device to supply instructions or data to a 64 bit data bus 8 bidirectional latching transceivers must be used to move the byte to the correct byte lane on the 64 bit bus as shown in Figure 2 8 bit Memory Device MPC60x Memory Controller Figure 2 Byte Lane Redirection Because the processor expects from one to eight bytes on each non burst transfer the memory controller must generate from one to eight memory cycles to the 8 bit memory by generating the address es latching the resulting data and then presenting it to the processor with the TA signal This process must be reversed when writing to memory This can take significant amounts of logic and is the approach taken by the MPC106 ROM inter
20. AN1769 D REV 1 1 1 1999 PowerPe Application Note Designing a Minimal PowerPC System Gary Milliorn Motorola RISC Applications risc10Qemail sps mot com This application note describes how to design a small high speed Motorola PowerPC processor based system In this document the terms 60x and 7xx are used to denote a 32 bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 603e PowerPC 604e or PowerPC 7507 microprocessors respectively MPC60x and MPC7xx processors implement the PowerPC architecture as it is specified for 32 bit addressing which provides 32 bit effective logical addresses integer data types of 8 16 and 32 bits and floating point data types of 32 and 64 bits single precision and double precision This document contains the following topics Topic Page Part 1 Introduction 2 Part 2 Processor Design 3 Part 3 Memory System Design 5 Part 4 Clock 32 Part 5 Reset 33 Part 6 Power 34 Part 7 Interrupts 37 This document contains information on a new product under development by Motorola and IBM Motorola and IBM reserve the right to change or discontinue this product without notice Motorola Inc 1999 All rights reserved AA MOTOROLA Part 8 COP 39 Part 9 Physical Layout 42 Part 10 Conclusion 42 To locate any published errata or updates for this document refe
21. Allow address only cycles The possibilities are unlimited 42 Minimal PowerPC System Design MOTOROLA 10 1 Reference Materials Table 7 lists several documents which may be of use in learning to design a PowerPC system of any type Table 7 Reference Documentation Document Name Why MPC603EUM AD MPC603e and EC603e RISC Details on MPC603 MPC603e and MPE603e Rev 1 Microprocessor User s Manual interface MPC604EUM AD MPC604e RISC Microprocessor User s Details on MPC604 MPC604e interface Manual MPC750UM AD MPC750 RISC Microprocessor User s Details on MPC750 and MPC740 interface Manual Details on back side cache interface MPC106UM AD MPC106 PCI Bridge Memory Controller Details on bus interface and general User s Manual information on memory controller design MPCPCMEC D Processor Cache Module Hardware Details on power supply encoding and PCM Specifications socket optional 10 2 Resources Table 8 lists many resources that are available to help understand and design PowerPC systems Table 8 Resources What Why Where Excimer Reference Design Implementation of this application note VHDL code file and schematics teksupport teklibrary index html http www mot com SPS PowerPC Yellowknife X2 X4 Reference Designs PCM modules Examples of MPC60x systems and http www mot com SPS PowerPC teksupport teklibrary index html Application Notes High speed
22. CS L TBSTL AACK L ADSC L BAA L TA L TEA L IN std_logic OUT std logic Minimal PowerPC System Design interupt inputs var polarity interrupt output 25 END COMPONENT COMPONENT START PORT tt_take in std_logic asserted if good TT selection tt we L in std_logic asserted if good TT is write tsL in std logic transfer start strobe aack L in std logic asserted on transfer complete clk in std_logic bus clock rst_L in std_logic system reset claim L buffer std_logic asserted when cycle is claimed doerr L buffer std logic asserted when cycle not claimed we_L buffer std_logic byte lane write selects di END COMPONENT COMPONENT TTDEC PORT tt in std logic vector 0 to 4 current transfer type tt_take buffer std_logic asserted when TT matches types ttwL buffer std logic asserted when cycle is write monitor buffer std_logic unneeded ViewSynthesis bug i END COMPONENT SIGNAL tt take std logic asserted for TT matches SIGNAL tt we L std_logic asserted for TT match writes SIGNAL we L std logic asserted for write cycles SIGNAL claim L std_logic asserted for cycles to process SIGNAL doerr L std_logic asserted for cycles to TEA SIGNAL ctime std logic vector 3 downto 0 selected cycle time SIGNAL aack internal L std logic internal copy 26 BEGIN TTDEC 1 TTDEC
23. D IF END PROCESS SET_TIMER END BEHAVIOR The chipsel module is asynchronous because it relies on the synchronous signal claim_L and relies on the stability of the address bus a and write select we_L signals These latter two signals are guaranteed to be stable until TA is asserted because the cycler module also delays the assertion of AACK until the last TA The chip select module may be easily adapted to different device speeds and for different I O maps within PowerPC architecture limitations It may also be modified to provide access to internal register files or to increase the number of chip selects within limitations of the FPGA chosen 3 5 4 Cycler State Machine The cycler state machine module controls the remainder of any transaction claimed by the memory controller For optimal performance one of four flows are selected The flows are as follows e SRAM single beat transfer e SRAM burst transfer e Programmed length transfer I O and Flash e Error transactions The first two optimize speed for the SRAM accesses which are typically the majority of code and data accesses the latter are handled in a more programmed method Fortunately the streamlined nature of burst transfers keeps the cycler module from becoming too complicated Cycler finishes any non error transaction by asserting AACK and TA one to four times based upon the type of cycle When AACK is generated the cycle has been completed and
24. ERR L wy ADSC A 29 31 gt BWE 0 7 TSIZ 0 2 TBST AACK cycler gee RST gt TA CLK gt TEA Figure 8 Memory Controller Architecture 3 5 1 Start Detection Module Upon receiving a TS the memory controller must examine the TT 0 4 signals to determine the type of cycle that will be performed Of the 32 possible permutations only those found in Table 4 are of interest MOTOROLA Minimal PowerPC System Design 11 Table 4 TT Encoding TTO TT1 TT2 TT3 TT4 Transaction Memory Controller Action 0 0 0 1 0 Write with flush Single beat or burst write 0 0 1 1 0 Write with kill Burst write 0 1 0 1 0 Read Single beat or burst read 0 1 1 1 0 Read with intent to modify Burst read All remaining TT codes are either address only cycles which are not needed are caused by instructions not needed in single processor environments for example the eciwx ecowx dcbz Iwarx and stewx instructions or are reserved values These simplifications are possible because there is no need to snoop the processor bus to maintain cache coherency While software should not generate such cycles it is not reliable for a memory controller to simply ignore them The memory controller as the sole target of bus transactions must terminate unacceptable bus cycles with TEA otherwise the processor will wait forever for the ignored cycle to complete When any transfer begins the start module must
25. E_L3 BWE_L4 BWE L5 BWE L6 BWE L7 RST L t t t t t t t t t t t TELK 2u 3u 4u 5u 6u 7u Time Seconds Figure 17 O ROM Single Beat Read Write 3 7 Software When writing software using this simple memory controller be sure to consider the effects the restrictions have placed on the environment For example because the Flash and I O areas do not support burst transfers they cannot be made cacheable If either the instruction or data cache is enabled on any PowerPC processor burst transfers will always occur unless the memory management unit via BATs or PTEs is used to mark addresses as non cacheable MOTOROLA Minimal PowerPC System Design 31 Part 4 Clock Unlike some systems the clock circuitry for a minimal system is quite simple The processor memory controller and two SRAM memories all need a separate bus clock anywhere from 1 Hz to 100 MHz and have a 250 ps point to point skew allowance The simplest way to do this is to connect a crystal oscillator device to all four loads as shown in This is generally achievable with most clock oscillators 3 3V 10 to 83 MHz Oscillator equal length traces to each vi Rd device PowerP CPU Figure 18 Simplest Clock Connection The clock generator must have a very low output impedance in order to drive four loads from one output and it may be unacceptable unless the clock traces can be kept very short on the order of 3 cm or so
26. KSTP_OUT Cl CLKOUT Unused leave unconnected CSE 0 1 DP 0 7 DPE HALTED QREQ RSRV TC 0 2 TMS TDI TDO VOLTDETGND WT CKSTP IN DBWO DBDIS DRVMOD1 RUN Unused pullup or connect to VDD 3 3V SHD SRESET TBEN TLBISYNC XATS Li_TSTCLK LSSD MODE Unused connect directly to VDD 3 3V ABB ARTRY DBB GBL L2 TSTCLK TCK Unused connect to 10K pullup to VDD 3 3V BG DBG DRVMODO L2 INT Connect to ground DRTRY Connect to HRESET QACK Connect to 1K pulldown to ground PLL_CFG 0 3 Connect to VDD 3 3V or ground to configure CPU speed INT MCP SMI Connect to VDD pullup 3 3V and or interrupt controller VDD OVDD Connect to appropriate voltage level AVDD L2AVDD Connect to PLL filter as shown in hardware reference manual HRESET Connect to reset controller TRST Connect to reset controller or connect to 1K pulldown GND SYSCLK Connect to clock generator A 0 31 AACK TA TEA TBST TS TSIZ 0 2 Connect to memory controller TT 0 4 DH 0 31 DL 0 31 Connect to memory devices 1 This table combines MPC603x MPC604x and MPC750 processors Not all of these signals are present on every device 2 These signals are the only ones that need consideration in a minimal system design All others are assigned fixed values and can be safely ignored thereafter The MPC750 has additional signals for interfacing with a back side L2 cache L2ADDR 0 16 L2DATA 0 63 L2DP 0 7 L2CE L2WE L2CLK_OUTA L
27. M L asserted which is only allowed for SRAM This begins a four beat burst transfer with TA low for four clock cycles the state machine clocks at the bus frequency and so proceeds from BEAT to BEAT4 automatically In states BEAT1 through BEAT3 the BAA signal is asserted to cause the burst SRAM devices to increment the address This produces an SRAM access rate of 2 1 1 1 excluding the TS Alternately if CLAIM_L is asserted but not TBST and the cycle is for the SRAM SCS_L asserted then this is a single beat access to SRAM While this could have been handled by the timer say by presetting it to 0001 the overhead of checking the timer costs additional cycles By detecting SRAM single beats separately fast access to SRAM is guaranteed two clocks Otherwise the cycle is either an error or a single beat access to Flash or I O In the latter cases only one clock of TA is needed but a lengthy delay may be needed to give the peripheral device time to complete the access For such devices within the cycler state machine is an internal timer which is continually re loaded while in the IDLE state in any other state it counts downward When the timer reaches zero and the 20 Minimal PowerPC System Design MOTOROLA state is in COUNT the state machine switches to the BEAT4 state to terminate the cycle with TA and AACK For any cycles which cannot be handled by the memory controller DOERR_L will be asserted This is caused either by add
28. O devices such as real time clocks serial ports and other unique interfaces have fairly simple I O controls a chip select an output enable and a write control The I O controller can then be modeled very closely on the flash ROM controller both have simple controls and both are relatively slow One difference between flash ROM and I O is that most I O devices are 8 or perhaps 16 bits not 64 so I O devices must be attached to particular byte lanes The I O controller responds to any size write so data may be placed on any byte lane software is responsible for positioning and retrieving the data properly A fairly easy modification to the controller allows different I O times for each address decoded allowing fast and slow I O devices to be mixed Note that the write strobes direction control are the same byte write enables that have been described before This reuse will allow a reduction of the size and complexity of the controller but it also means that the software must generate the correct address when performing writes to I O devices greater than 8 bits wide For example in Figure 6 a 16 bit I O device is attached to D 0 15 and uses BWE1 so to access the controller software must issue 16 or 32 bit writes aligned with DO The controller will assert BWE1 all others are ignored XOE PC es BWEO I O Device DE XCS0 Remember 3 3V Devices ONLY Figure 6 I O Connections The I O cont
29. PORT MAP tt tt tt take tt take tt we L tt we L monitor gt monitorl START 1 START PORT MAP tt take tt take tt we L gt tt we L ts L gt ts L aack L gt aack internal L clk gt clk rst L gt rst L claim L gt claim L doerr L gt doerr L we L gt we L CHIPSEL 1 CHIPSEL PORT MAP a a high claim L claim L we L we L scs L gt scs L soe L gt so L fcs L fcs L foe L foe L xcs L gt xcs L xoe L gt xoe L ctime ctime BYTEDEC 1 BYTEDEC PORT MAP a gt a lo tsiz gt tsiz tbst L tbst L claim L gt claim L we L gt we L bwe L gt bwe L CYCLER 1 CYCLER PORT MAP CTIME gt ctime CLK clk CLAM L claim L DOERR L gt doerr_L RST_L rst L SCS L gt scs _ L TBST L tbst L AACK L gt aack_internal L ADSC L gt adsc L BAA L baa L TA L ta L TEA L gt tea L Copy internal aack to external aack since VHDL is fussy about connecting OUT s to BUFFER s aack_L lt 0 WHEN aack_internal L 0 ELSE 1 The databus port is not currently used add logic to use it to maintain its existance otherwise errors will be generated for unused ports probel lt 0 WHEN d 11111111 ELSE 1 Sideband modules that are not part of the memory controller but are needed for the Excimer project include the interrupt controller reset drivers and LED monitors Extremely simple interrupt
30. T if any 12 N A 13 HRESET HRESET All Merge with on board HRESET 14 N A All Key location pin should be removed 15 CKSTPO CKSTPO 603e 603ev 740 750 Add 10K pullup to VDD 16 Ground Digital Ground All 8 1 Merging Reset Signals The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button switches then the COP reset signals must be merged into these signals with logic It is not possible to just wire the reset signals together damage to the COP system or the target system may occur The arrangement shown in Figure 29 allows the COP to independently assert HRESET or TRST while insuring that the target can drive HRESET as well The pull down resistor on TRST insures that the JTAG scan chain is initialized during power on if the COP is not attached if it is it is responsible for driving TRST when needed PowerPC Erom Target oard Reset lt HRESET Sources PRESEI T HRESET TRST 2KQ COP Header Figure 29 COP Reset Merging 40 Minimal PowerPC System Design MOTOROLA 8 2 Multiple Scan Chains JTAG scan chains typically consist of numerous devices to perform in circuit testing of printed circuit boards Since some existing COP controller software may not be able to control the proces
31. a new one can begin at the next clock cycle Due to the pipelining nature of the SRAM it actually takes 5 beats to do a read cycle but one of those clock cycles has already been provided before cycler can leave the IDLE state by the synchronous start detector Figure 12 shows the end cycle module 4 CTIME 0 3 CLAIM_L gt TEA DOERR_L AACK SCS_L BAA TBST TA RST ADSC CLK Figure 12 End Cycle Module As the VHDL code for the cycler is generated by a state machine CAD program the code is uncommented and somewhat difficult to follow refer instead to Figure 13 for details MOTOROLA Minimal PowerPC System Design 19 CYCLER DIA Cycler Milliorn 98SEP25 IRST_L O ICLAIM_L amp ISCS_L amp ITBST I IDOERR L ICLAIM L amp SCS L amp ICLAIM L amp TBST_ ISCS_L amp TBST_ ERROR SINGLE COUNT WEL NWEL TIMER lt gt 0000 TIMER lt TIMER 1 TIMER 0000 Moore Machine State Outputs AACK_L not BEAT4 or ERROR ADSC_L not IDLE and SCS_L and ICLAIM_L or DESEL BAA_L not BURST or BEAT1 or BEAT2 BEAT4 or BEAT4 and WE_L and ITBST_L TA L not BEAT1 or BEAT2 or BEATS or BEAT4 or ITBST L and WE L or BURST and WE_L TEA_L not ERROR lava Vector Declarations CTIME 3 0 TIMER 3 0 Figure 13 Cycler State Flow The state machine switches from the IDLE state to the BEAT state on detection of any claimed burst cycle TBST Land CLAI
32. als The simplest way to achieve all of these goals is to use one of many inexpensive devices available to drive the reset lines at the proper time Called reset controllers or system supervisory controllers these devices are typically very inexpensive less than US 0 50 have small footprints SOT23 to SO8 and are widely available from Texas Instruments Maxim Semiconductor and others Figure 20 shows an example using these types of circuits 3 3V PowerPC 3 3V Supervisory Circuit 10K Dallas DS1834 V H 3 08V HRESET Trst 1ms J Open Drain L TRST Digital Reset Input optional Figure 20 Reset Using Supervisory Controller If the reliability of the power supply can be assured or if the power supply provides a failure output then the reset controller can be reduced to a simple R C network as shown in Figure 21 3 3V Power Supply with open drain PowerPC Power Failure Output R 10K POWERFAIL gt HRESET O L IN AN THF Figure 21 Simple Reset Controller Because the drain on the HRESET signal is negligible the simple equation t RC suffices to calculate the necessary values The above values shown give a 10 us reset which is sufficient for all bus speeds faster than 25 MHz MOTOROLA Minimal PowerPC System Design 33 Part 6 Power In order to increase speeds without excessive he
33. at loss the newest fastest PowerPC processors have cores which operate at low voltages To remain compatible with external devices the I O cells have remained at 3 3V This increases the complexity of a system somewhat by requiring multiple voltages levels Furthermore as transistor counts rise in the processors the static and transient current demands of the power supplies rise as well Consequently a well designed quiet and responsive power supply is a critical first step to a well designed PowerPC based system There are many ways to derive power ranging from batteries to radioisotope thermocoupled generators The two most popular methods are linear supplies and switching supplies which are considered in further detail in sections 6 1 and 6 2 6 1 Linear Regulators Linear regulators operate by dissipating unwanted energy in the form of heat With proper thermal management linear regulators are very easy to design inexpensive and provide quiet stable outputs The disadvantages are the heat and the inability to generate higher voltages Figure 22 shows an example of a linear 2 5 V power supply similar to that used on the Excimer board 5 0V we 2 5V Linear Tech LT1584CT H am E 0 1 F S 120 Figure 22 Excimer Linear Power Supply 6 2 Switchmode Regulators An alternate method of providing other voltages is to use a switching power supply These devices can efficiently convert
34. be provided by the memory controller at the same time Since SETI is asserted one clock after TS if the address matches an SRAM space the memory controller also asserts ADSC for memory cycles The BWE signals corresponding to the size of the transfer must be asserted if the cycle is a write cycle otherwise G must be asserted to read in data all byte lanes are driven and the processor selects the data from whichever byte lane is needed The remaining signal is ADV which must be asserted for three clock cycles if a burst transfer is selected otherwise it remains high Although the data rate could be throttled with ADV or G this is not necessary for the processor so to simplify the design only fast SRAMs will be accommodated The remaining portion of the SRAM controller to specify is the initial access time Most SRAMs available today can decode an address within 10 ns from the address strobe ADSC so there is no need to delay before beginning a transfer MPC750 Memory Controller BWE 0 7 Figure 4 Pipelined Burst SRAM Memory Connections MOTOROLA Minimal PowerPC System Design 7 Note that since we do not allow overlapped address and data tenures we do not know whether the next transfer is to the same SRAM page or not so we cannot stream data that is 3 1 1 1 1 1 1 1 cycles This requires much more logic and is left as an exercise for the reader A final issue which mu
35. cs L AND 0000 OR IDLE amp IDLE amp IDLE amp IDLE AND DOERR L amp DOERR L amp DOERR L amp DOERR L AND CLAIM L amp CLAIM L amp CLAIM L amp CLAIM L OR DOERR L amp DOERR L amp DOERR L amp DOERR L AND SCS Ls SCS L amp SCS L amp SCS LJAND NOT TBST L amp NOT TBST L amp NOT TBST L amp NOT TBST L AND 0000 OR SINGLE amp SINGLE amp SINGLE amp SINGLE AND 1111 AND 0000 se PROCESS BEAT4 ERROR BEGIN IF BEAT4 0 JAG ERROR 0 THEN AACK L lt 1 ELSE AACK I lt 0 END IF END PROCESS PROCESS CLAIM L DESEL IDLE SCS L BEGIN IF CLAIM I 1 AND DESEL 0 OR SCS I 1 AND DESEL 0 OR IDLE 0 Ud DESEL 0 THEN ADSC I lt 1 ELSE ADSC L lt 0 END IF END PROCESS PROCESS BEAT1 BEAT2 BEAT4 BURST TBST L WE L BEGIN IF BURST 0 AND BEATI 0 AND BEAT2 0 AND BEAT4 0 OR BURST 0 AND BEATI 0 AND BEAT2 0 AND WE I 1 OR BURST 0 AND BEATI 0 AND BEAT2 0 AND TBST I 1 THEN BAA I lt 1 ELSE BAA L lt 0 END IF END PROCESS PROCESS BEAT1 BEAT2 BEAT3 BEAT4 BURST TBST L WE L BEGIN IF BEATI 0 AND BEAT2 0 AND BEAT3 0 AND BEAT4 0 AND TBST L 1 AND BURST 0 OR BEATI 0 AND BEAT2 0 AND JAND BEAT4 0 AND WE I 1 THEN TA L lt 1 ELSE TA L lt 0 END IF END PROCESS PROCESS ERROR BEGIN IF ota 0 THEN TEA I lt
36. d have a low equivalent series resistance ESR rating to ensure the quick response time necessary Each bulk capacitor should be at least 100 F and there should be one device for every 20 high frequency capacitors more if they cannot be placed relatively close Part 7 Interrupts The PowerPC processor has one standard interrupt signal INT that can be connected to an external interrupt source if needed This is in keeping with the RISC philosophy in which software manages optional highly complex details and hardware aims to be fast As long as the interrupting device is level sensitive it can be wired directly to the processor s INT input perhaps with an inverter if necessary If extra interrupts are needed the simplest manner is to merge all level sensitive interrupts with a logic gate as shown in Figure 26 Level Sensitive I Interrupts Software must poll all potential interrupting devices to determine which one or more has caused the interrupt and clear it This approach does not allow any priority among interrupts nor can any interrupt be masked unless the interrupting device provides a means to do so PowerPC Ol Q T Z h QO NI Q Figure 26 Simple Interrupt Merging One way to quickly identify different interrupts is to assign them each an interrupt vector by reusing the special purpose interrupts SMI and MCP as shown in Figure 27 MOTOROLA Minimal Po
37. e low chip enable asserted for all operations This gives a flash memory architecture as shown in Figure 5 3 3V Remember 3 3V Device ONLY 3 3V Figure 5 Flash Memory Connections This implies that the ROM space is non cacheable since Flash ROM is so much slower than SRAM critical code should be copied to SRAM so this may not be considered a big performance limitation 8 Minimal PowerPC System Design MOTOROLA Note that 16 bit devices have been used This helps reduce the number of components at a cost of restricting writes to 16 32 or 64 bits in size If 8 bit writes are required then either 8 8 bit devices must be used or devices which have multiple byte enables A further restriction on flash memory is that reading is slow from 60 to 200 ns and writing is even slower as much as 15 ms The memory controller delays the assertion of TA for a fixed number of cycles on any access to match the read time this handles the read access properly and gives sufficient time for the flash device to begin the program operation the data does not need to be held throughout a write cycle Software must insure that a proper amount of time has elapsed after a write before another read or write occurs This can be done with a simple timing loop using I O to check the RDY BSY signals or the use of flash devices which can be queried by reading special addresses 3 3 I O Controls Most simple I
38. e low when appended with a L library ieee use ieee std logic 1164 all use ieee std logic arith all Minimal PowerPC System Design MOTOROLA use ieee std_logic_unsigned all MC ENTITY MC is PORT clk rst_L in std_logic general controls a_high in std logic vector 0 to 1 upper 60X address a_low in std logic vector 29 to 31 lower 60X bus address tsL in std logic transfer start tt in std logic vector 0 to 4 transfer type tsiz in std_logic vector 0 to 2 transfer size tbst_L in std_logic asserted if transfer is burst irg in std_logic vector 0 to 3 interrupt inputs altrst_L in std_logic alternate reset input cophrst_L in std_logic COP port HRESET input bwe L buffer std logic vector 0 to 7 byte lane write selects scs L soe L buffer std logic SRAM chip selects amp enable fcs _ L foe L buffer std logic Flash chip selects amp enable xcs L buffer std logic vector 0 to 1 I O chip selects xoe_L buffer std_logic I O output enable ta L tea L out std logic normal and error acks aack L out std logic address acks adsc L out std_logic SRAM address latch baa_L out std_logic SRAM burst address advance int L buffer std_logic interrupt output hreset_L buffer std_logic CPU HRESET output mreset buffer std_logic Misc active high reset output fcsled scsled buffer std_logic
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40. face for example For this minimal system we will instead take the approach that all memory is 64 bits wide By using 32 bit pipelined burst SRAM for the main memory and 16 bit Flash EPROM for start up code only 6 components will be needed the controlling logic will be simple and inexpensive and as a bonus the SRAM will allow very fast memory access speeds The use of SRAM for main memory has become more attractive as speed and size increases and price falls Currently SRAM devices at 66 MHz are commodity components due to their use as L2 caches in PCs even 100 MHz parts are not terribly expensive The minimal system block diagram is shown in Figure 3 MOTOROLA Minimal PowerPC System Design 5 MPC60x D 0 63 TT TSIZ TBST TS AACK TA TEA Memory Coniroller I O Space 16 bit FlashROM 4X 32 bit Pipelined Burst SRAM 2X The system address map is shown in Table 2 Figure 3 Minimal System Memory Architecture Table 2 Excimer Address Map Address A Devices Burstable chen Cycles Start End RAM 0x0000_0000 Ox3FFF_FFFF Y 3 1 1 1 Fast I O 0x4000_0000 Ox7FFF_FFFF N 4 Slow I O 0x8000_0000 OxBFFF_FFFF N 12 Flash OxC000 0000 OxFFFF FFFF N 6 The only challenging design problem faced is the handling of burst transfers The MPC60x family can operate with caches disabled thus preventing burst transfers but this typically exacts a terrible penalty in per
41. formance that makes the additional effort at handling them well worthwhile The first step in designing the memory controller abbreviated MC in code is to determine the types of controls that will be needed among the proposed memory devices Flash EPROMs SRAM and general I O Minimal PowerPC System Design MOTOROLA 3 1 SRAM Memory Controls The SRAM interface is centered around the controls necessary for a typical pipelined burst SRAM memory as used on the MPC750 back side cache or various other PC system s L2 cards Flow through SRAM memories could also be used but the timing for write operations would change Since this is a simple memory controller it will be architected for only one type of SRAM Most SRAM devices have numerous controls which are not needed leaving us with the following A n 0 Memory address including LSB for burst transfers and critical word first Addresses 0 and 1 are the LSBs and are used for burst transfer addresses ADSC Latches address for single beat or burst transfers ADV Increments address for burst transfers BWE a d Active low byte write enables if not asserted the cycle is a burst read G Active low output enable asserted for all read operations SEI Active low chip enable asserted for all operations The memory controller must generate these signals for all SRAM transfers whether single beat or burst transfers ADSC and SEI start the cycle by latching the address into the SRAM these must
42. high voltage low current energy into low voltage high current energy by storing it magnetically in an inductor Switching power supplies require more complicated logic and careful design but the rewards are that the efficiencies are high and that thermal dissipation is of little issue Because switchers work basically by periodically dumping energy into a low impedance load clocking noise and transient effects can make for a noisy supply unless components are carefully selected Figure 23 shows an example of a switching power supply 34 Minimal PowerPC System Design MOTOROLA 2 5uH 5 0V FRIE 7 MOSFET ele AN UA 1 3uH 6mQ Er SOW 2 5V Raytheon 8 1500uF Fairchild dj x3 RC5050 H Voltage 3p Encodin gt Inputs gt NOTE Not all details have been shown Figure 23 Simple Switching Power Supply This switcher has a 5 bit digital input which allows the output voltage to be set in 0 1 0 05V increments in two ranges between 1 2V to 3 6V This allows a single power supply to be easily programmed to meet current and future PowerPC processor requirements In addition the digital settings match those used on the PowerPC processor cache module interposer which allows the processor to automatically select the desired voltage 6 3 Power Supply Sequencing Once consequence of multiple power supplies is that when power is initially applied the voltage rails wi
43. ic END ARCHITECTURE BEHAVIOR OF SHELL CYCLER IS State variables for machine sreg SIGNAL BEAT1 next BEAT1 BEAT2 next BEAT2 BEAT3 next BEAT3 BEAT4 next BEAT4 BURST next BURST CLOCK next CLOCK COUNT next COUNT DESEL next I DESEL ERROR next ERROR IDLE next IDLE SINGLE next SINGLE std logic SIGNAL next TIMERO next TIMER1 next TIMER2 next TIMER3 std logic SIGNAL TIMER std logic vector 3 DOWNTO 0 ATTRIBUTE PERMEABILITY OF BEHAVIOR ARCHITECTURE IS TRUE BEGIN PROCESS CLK RST L next _BEAT1 next BEAT2 next BEAT3 next _BEAT4 next BURST next CLOCK next COUNT next DESEL next ERROR next IDLE next SINGLE next TIMER3 next_TIMER2 next TIMER1 next TIMERO BEGIN IF RST I 0 z THEN BEATI lt BEAT2 lt BEAT3 lt BEAT4 lt BURST lt CLOCK lt COUNT lt DESEL lt 0 ERROR lt 0 IDLE lt 1 SINGLE lt O TIMER3 lt 0 TIMER2 lt 0 TIMER1 lt 0 TIMERO lt 0 ELSIF CLK 1 AND CLK event THEN BEAT1 lt next BEAT1 Per se se se se Se Se Se See MOTOROLA Minimal PowerPC System Design 21 BEAT2 lt next BEAT2 BEAT3 lt next BEAT3 BEAT4 lt next BEAT4 BURST lt next BURST CLOCK lt next gt CLOCK COUNT lt next_COUNT DESEL lt next DESEL ERROR lt next ERROR IDLE lt next IDLE SINGLE lt next SINGLE TIMER3 lt next TIMER3 TIMER2 lt next TIMER2 TIMER1 lt next TIMERL TIMERO
44. individual byte lane s SRAM ROM scs Asserted on all SRAM accesses SRAM SOE Asserted on all SRAM read accesses SRAM ADSC Asserted on all burst SRAM accesses before the first cycle SRAM BAA Asserted on all burst SRAM accesses during cycles 2 4 SRAM FCS Asserted on all Flash accesses ROM FOE Asserted on all Flash read accesses ROM XCS 0 1 Asserted on all I O accesses I O XOE Asserted on all I O read accesses I O 10 Minimal PowerPC System Design MOTOROLA All other signals are either wired to the necessary state or are unused as described in Table 1 For example since the PowerPC bus is parked permanently detecting BG ABB DBG and DBB are unnecessary The memory controller interface then requires a total of 35 I O signals well within the capacity of any modern FPGA leaving lots of I O for additional functions 3 5 Memory Controller Details The remainder of Part 3 Memory System Design describes the internal operations of the memory controller as used on the Excimer reference board The code is based upon synthesizable VHDL code but could be easily adapted to Verilog and any of the several IC specific HDL variants that exist for Actel Altera Lattice Xilinx et al Figure 8 shows the internal architecture of the memory controller module SCS SOE y FCS A O 1 chipsel gt FOE ye XCS 0 1 TT 0 4 J XOE TS TIME 0 3 start CLAIM L DO
45. ing only on the load on the 3 3 V power supply Because such tracking is difficult to achieve PowerPC processors may be subjected to a differential voltage between the Vpp and OVpp power signals for up to 500 ys If the power supplies cannot track within specified limits within this period other means must be employed to correct the problem otherwise the long term reliability of the processor may be affected due to failure of internal protection circuitry One means of keeping two supplies synchronized is to use a so called bootstrap diode between two power rails An example is shown in 3 3V OVpnp Vv MUR420 A MUR420 z 2 5V Vpp Main Power Core Power Figure 25 Bootstrap Diodes The bootstrap diodes are selected such that a nominal Vpp will be sourced from the OVpp power supply until the Vpp power supply becomes active In the above example a pair of MUR420 Schottky barrier diodes are connected in series each has a forward voltage Vp of 0 6V at high currents and so provides a 1 2V drop maintaining the 2 5V power line at 2 1V Once the core power supply is stable at 2 5V then the bootstrap diode s will be reverse biased and only a few nanoamperes of leakage current will flow NOTE It is essential that the forward voltage be effective at the current levels needed by the processor 1 3 amps or so depending on the PowerPC device Many diodes have only a nominal Vp which falls off t
46. is doesn t seem to care about the NC input pins at that level Copyright 1998 by Motorola Inc All rights reserved Author Gary Milliorn Revision 0 1 Date 6 10 98 Notes All logic is active low when appended with a L Passed speedwave check 6 16 98 library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all TIDEC ENTITY TIDEC is PORT tt in std logic vector 0 to 4 current transfer type tt take buffer std logic asserted when TT matches types tt_we_L buffer std_logic asserted when cycle is write monitor buffer std_logic ViewSynthesis bug not useful end PORT DEFINITION AND ENTITY ARCHITECTURE BEHAVIOR OF TTDEC is SIGNAL wflush wkill read rwim std_logic BEGIN Detect only the following TT types tt take will be asserted for all cycles we will claim wflush lt 1 WHEN tt 0 0 and tt 1 0 and tt 2 0 and tt 3 1 and tt 4 0 ELSE 0 wkill lt 1 WHEN tt 0 0 and tt 1 0 and tt 2 1 and tt 3 1 and tt 4 0 ELSE 0 read lt 1 WHEN tt 0 0 and tt 1 1 and tt 2 0 and tt 3 1 and tt 4 0 ELSE 0 rwim lt 1 WHEN tt 0 0 and tt 1 1 and tt 2 1 and tt 3 1 and tt 4 0 ELSE 0 tt take lt wflush or wkill or read or rwim tt we L lt not wflush or wkill Needed due to ViewSyn
47. ll ramp up at different rates depending upon the nature of the power supply the type of load on each and the manner in which the different voltages are derived This can present a problem because the power supplies of a PowerPC processor have the following restrictions e VIN must not exceed OVpp by more than 0 3V at any time including requirement 1 during power on reset OVpp must not exceed Vpp AVpp by more than 1 2V at any time including requirement 2 during power on reset Vpp AVpp must not exceed OVpp by more than 0 4V at any time including requirement 3 during power on reset On most PowerPC processors the OVpp 3 3V I O load is typically less than 10 that of Vpp 2 5V core power and the I O cells are three stated during reset so a 3 3 V power supply may ramp up faster than the core voltage Alternately with more devices now operating at 3 3V including the PCI bus that power rail may be so loaded from a system perspective that the Vpp power will stabilize more quickly Figure 24 shows an example of two possible power sequencing waveforms MOTOROLA Minimal PowerPC System Design 35 Minimal Load 3 3V Ramp Maximum Load 3 3V Ramp requirement 2 requirement 3 Figure 24 Power Supply Sequencing It is virtually impossible to insure that all voltages ramp up to their steady state at an identical rate and at an identical time In either requirement 2 or requirement 3 will be violated depend
48. nal memory controller or I O interface that role has traditionally fallen to the Motorola MPC106 memory PCI cache controller For a small board such as outlined here the MPC106 is much more than is minimally needed Indeed complexity can sometimes reduce performance Cache coherency instructions use valuable bus cycles and allowing access by external masters such as cache requires delaying memory cycles in case the external device claims the cycle Instead for this design a programmable ASIC is used to provide the necessary controls for a block of RAM ROM and access to I O The controller is not programmable by software but is instead pre configured in hardware and memory access cycles are tuned to provide only the necessary signals With these restrictions and goals the typical block diagram may resemble that shown in Figure 1 2 Minimal PowerPC System Design MOTOROLA Motorola Motorola i 585 DS1834 Her PONS MPC904 optional MPE60x MPC7xx i Memory Controller Main Memory Start up Code Motorola Motorola Lattice 2 MCM69P737 4 29F800 2096V 512K PBSRAM 4M Flash 15ns 150 ns Lattice VO Port Motorola 16550 UART 2 74LCX245 Figure 1 Typical Minimal System Block Diagram Power Reset Processor Clock COP Serial Port 1 2 Conventions Various conventions used in this document are as follows SIGNAL Active high exte
49. o nothing at high current such devices are not acceptable 36 Minimal PowerPC System Design MOTOROLA 6 4 Bypassing A well designed power supply will be quickly undermined if a poor bypassing system is used Attention to bypassing is essential to eliminate poor ground return paths through the PCB and to help quell transient noise and voltage drooping due to switching consideration High frequency bypassing is provided by numerous 0 1 uF ceramic capacitors located near each power pin Only surface mount devices may be used and preferably in the smallest package possible 0805 or 0508 with power connections on the long side Each capacitor should have a direct via to the power or ground plane with a short connection to the power pin On PowerPC devices in BGA packages the solder pads connecting to power pins balls should be connected directly to a power or ground plane with a via Since there are no pins the bypass capacitors should surround the device on the bottom layer of the board If placing components on the bottom of the board is not allowed the next most preferable placement is to surround the part as close as possible to the BGA escape pattern In addition a good design will include several bulk storage capacitors distributed around the PCB and connected to the Vpp and OVpp power planes These capacitors provide local energy storage for quick recharging of the smaller bypass capacitors so the bulk capacitors shoul
50. owerPC System Design 29 Figure 16 shows that the Flash access is controlled by timed values in this case a value of 3 as provided by the chipsel module which produces a 6 clock access time 30 TEA_L SOE_L FCS_L FOE_L BWE_LO BWE_L1 BWE_L2 BWE L3 BWE L4 BWE L5 BWE L6 BWE L7 RST_L T CLK t t t t t H t t t t 1u 2u 3u 4u 5u 6u Time Seconds Figure 16 Flash ROM Single Beat Read Write Minimal PowerPC System Design MOTOROLA Figure 17 shows two back to back accesses one to the slow I O space and the second to the fast I O space ax JUY UU UU UU UU UU UU UU UU UY sis JE ee RE ee A HIGH1 A LOW29 A LOW30 A LOW31 TTO TT1 TT2 TT3 TT4 TSIZO TSIZ1 TsIz2 TBST_L TSL AACK L TAL TEAL XCS LO XCS L1 XOEL BWE_LO BWE_L1 BWE_L2 BW
51. r to the website at http www mot com SPS PowerPC Part 1 Introduction To keep the design simple only the most basic features necessary to run a debugger program are included These features are as follows e A PowerPC processor this includes the MPC603e MPC603ev MPC604 MPE603e MPE603ev MPE604 MPC740 and MPC750 e Flash ROM storage start up code e Read write memory downloaded code program variables e Serial I O channel communication e Memory and I O controller e Power clocks and reset While this application note is general in focus it will also occasionally diverge in order to describe the implementation details of an actual board known as Excimer which implements the basic techniques described in this application note The details of Excimer provide a base upon which you can build a design with the general sections describing ways to support customization 1 1 Design Philosophy The PowerPC high performance family MPC60x and MPC7xx bus interface may at first appear intimidating due to the presence of split address data bus tenuring bus snooping multiprocessing support cache coherency support and other advanced features Such features can be used to obtain additional performance for high performance systems but for the purposes of a small high speed embedded controller particularly one with only one bus master many of these complications can be avoided Since the processor does not contain an inter
52. ress only cycles or specialized data transfer instructions Iwarx etc for such cycles the state machine will assert TEA and AACK The behavior of PowerPC processors does not specify what happens when TEA is asserted during address only cycles however since this minimal system environment disallows such cycles the resulting behavior is allowable either the cycles are silently ignored and processing resumes or the processor takes an exception In all these cases AACK is not asserted until the last or only TA is asserted releasing the address tenure as well as the data tenure The re assertion delay inherent before TS can be asserted guarantees a one clock cycle recovery time on the data bus The VHDL code for this module is D USR GMILLI 1 MC CYCLER CYCLER VHD VHDL code created by Visual Software Solution s StateCAD Version 3 2 Thu Sep 24 16 16 39 1998 This VHDL code for use with Workview Office was generated using one hot state assignment with boolean code format Minimization is enabled implied else is enabled and outputs are manually optimized LIBRARY LAT VHD USE LAT VHD VHD PKG ALL LIBRARY ieee USE ieee std logic 1164 all LIBRARY synth USE synth vhdlsynth all ENTITY SHELL CYCLER IS PORT CLK CLAIM L CTIMEO CTIME1 CTIME2 CTIME3 DOERR L RST L SCS L TBST L WE L IN std logic AACK L ADSC L BAA L TA L TEA L OUT std_logic SIGNAL TIMERO TIMER1 TIMER2 TIMER3 std log
53. rnal signal pin SIGNAL Active low external signal pin signal Active high internal signal net used when describing the memory controller signal_L Active low internal signal net used when describing the memory controller L indicates active low for internal signals name A block of HDL code implementing a function Occasionally a name may have both forms for example the TS hardware signal may be detected in a fragment of HDL code which refers to it as ts_L Part 2 Processor Design The processor may be any member of the MPC60x or MPC7xx family All such devices offer 64 bit bus modes and the MPC603x parts also offer a 32 bit bus interface which can make the memory design even simpler at a cost of speed Since only the MPC603x parts support this mode it will not be used in this design but it should be kept in mind where the number of parts or cost is even more important than speed Since all high performance PowerPC processors use very similar bus interfaces the choice of processor may be based on cost and performance issues and not on the interface costs For a simple system with only one bus master many signals on the processor bus may be ignored or wired to the desired state refer to Table 1 for more information MOTOROLA Minimal PowerPC System Design 3 Table 1 PowerPC Bus Signal Connections Signal Treatment AP 0 3 APE BR C
54. roller supports both Motorola and PC control signals In addition these devices attach to the 3 3 V PowerPC data bus so they must not drive over 3 3V An easy solution to this is to add a 3 3 V buffer between the high speed memory path and the I O devices which has a side benefit of allowing faster memory operation due to reduced capacitive loading MOTOROLA Minimal PowerPC System Design 9 OE L 5V I O Device LVT245 OE RW 3 3V i I O Device XC51 cs DIR lt P 00 7 Figure 7 Buffered I O Connections 3 4 Collected Controls The previous sections have provided a general overview of the memory controller this section provides the details Table 1 shows most of the signals that are directly connected to the memory or I O or are wired to some particular state The controls needed for burst SRAM and flash ROM share common byte write enables the memory controller signals are listed in Table 3 Table 3 Memory Controller Signal Handling Signal Treatment Applies To TS Examined for start of a cycle All TT 0 4 TSIZ 0 2 TBST Examined for type of cycle All A 0 1 Examined for cycle destination RAM ROM I O All A 29 31 Examined for byte lane enables and burst transfer All AACK Asserted on final memory transfer All TA Asserted per beat on each memory transfer All TEA Asserted on each unsupported memory transfer All BWE 0 7 Asserted on writes on
55. s true for the devices used The VHDL code for the bytedec module is lengthy but straightforward The values are directly derived from the data alignment tables in the processor user manuals for example Table 8 3 and Table 8 4 of the MPC750 RISC Microprocessor User s Manual Burst transfers enable all byte lanes while all other transfers enable only the byte lanes based upon the address and transfer size BYTEDEC is the portion of the MC which provides individual byte write enabled for each byte lane depending upon the size and address of the transfer If the cycle is a read cycle no outputs are asserted at all Copyright 1998 by Motorola Inc All rights reserved Author Gary Milliorn Revision 0 1 Date 6 10 98 Notes All logic is active low when appended with a L Passed speedwave check 6 10 98 library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all ENTITY BYTEDEC is PORT a in std logic vector 29 to 31 stable 60X bus address tsiz in std logic vector 0 to 2 current transfer size tbst L in std logic asserted if transfer is burst we L in std_logic asserted if transfer is write bwe_L buffer std logic vector 0 to 7 byte lane write selects i end PORT DEFINITION AND ENTITY ARCHITECTURE BEHAVIOR OF BYTEDEC is SIGNAL be L std logic vector 0 to 7 byte lane enables
56. siz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tsiz 011 and a or tbst L 0 ELSE 1 0 WHEN tsiz 001 and a or tsiz 010 and a or tsiz 100 and a or tsiz 000 and a or tsiz 011 and a or tbst L 0 ELSE 1 the byte lanes with the write signal be L 0 or we L be L 1 or we L be L 2 or we L 111 110 100 000 101 were Minimal PowerPC System Design burst e half word word double word three byte three byte burst byte half word word double word three byte three byte three byte burst byte half word word double word three byte three byte three byte burst byte half word word double word three byte three byte three byte burst e half word word double word three byte three byte three byte burst e half word word double word three byte three byte burst byte half word word double word three byte burst MOTOROLA bwe L 3 lt be L 3 or we_L bwe L 4 lt be L 4 or we LJ bwe L 5 lt be L 5 or we LJ bwe L 6 lt be L 6 or we LJ bwe L 7 lt be L 7 or we LJ END BEHAVIOR The three byte cycles
57. sor if any other device is present in the scan chain it is often necessary to provide isolation for the PowerPC JTAG port Multiple scan chains is common on complex boards so this is nothing new however for small systems it may be more desirable to provide an isolation capability that is only created when debugging is desired and not while in mass production This isolation is shown in Figure 30 and can be done with logic as in Method 3 or manually with a removable jumper or zero ohm resistor or even an easily cut PCB trace Method 1 Method 2 Method 3 m gt og Jumper LVTO8 resistor Block Logic T r N I 7 x I N P PRESENF Isolation TDO lt Method TDI 3 COP MPC60x Other JTAG Port other devices TMS z TCK z TRST at Figure 30 COP Isolation As required by the IEEE 1189 1 JTAG standard even though TMS and TCK will be active when COP commands are issued the TDI chain for the rest of the system will float high causing only IDLE commands to be issued to all other JTAG devices NOTE Not all emulators assert the present signal If Method 3 the logic controlled method is used to separate the scan chain insure that the chosen emulator will provide the PRESENT signal MOTOROLA Minimal PowerPC System Design 41 Part 9 Physical Layout Figure 31 shows an example minimal system called Excimer
58. st be handled is terminating an access Burst SRAM s operate by streaming data into or out of the chip on each clock edge after an initial setup sequence ADSC until instructed to stop While read operations can be ignored by forcing G high write operations cannot be similarly controlled so instead a de select cycle must be performed after each access This is done by asserting ADSC without no chip select asserted when deselected the SRAM will stop reading or writing data 3 2 Flash Memory Controls Flash memory devices use traditional OE CS and WE signals to perform single beat read and write cycles burst transfers are not permitted whether the data width of the device is 8 bits or 16 bits Since the PowerPC bus does not care if data is placed on ignored byte lanes during read cycles it will be acceptable to use OE in common for all flash ROMs Write cycles require more care Requiring the processor to perform 64 bit writes is unacceptable because it is difficult that is requires the floating point unit on the MPC devices or impossible on the non floating point MPE devices to do a 64 bit single beat bus transfer Thus flash devices must be fully qualified with byte enables during write cycles Using standard flash devices will require the following control signals BWE 0 7 Active low byte write enables if not asserted the cycle is a read FOE Active low output enable asserted for all read operations FCS Activ
59. td Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po New Territories Hong Kong Mfax RMFAX0 email sps mot com TOUCHTONE 1 602 244 6609 US amp Canada ONLY 800 774 1848 World Wide Web Address http sps motorola com mfax INTERNET http motorola com sps Technical Information Motorola Inc SPS Customer Support Center 1 800 521 6274 electronic mail address crc Qwmkmail sps mot com Document Comments FAX 512 895 2638 Attn RISC Applications Engineering World Wide Web Addresses http www motorola com PowerPC http www motorola com netcomm AA MOTOROLA AN1769 D
60. the next state and provides the encoded output The code for calculating the timing value TIME looks complicated because all four bits are calculated in one statement 3 5 5 Memory Controller Module The final module is the memory controller itself which simply interconnects the previous modules and is shown previously in Figure 8 The VHDL code for this module is 24 MC is an FPGA which implements a simple but fast MC for the PowerPC 60X 7XX family of processors The controller is described in detail in Application Note AN17XX A minimal PowerPC System Design Most of MC is just a top level interconnect of lower level modules start checks TT and asserts CLAIM or DOERR depending on whether the transfer will be handled or not ttdec uses TT bits to separate cycles into handled and non handled types chipsel provides chip select and output enables for devices depending upon the current address Provides timing values for cycler to use Speculatively asserts ADSC bytedec provides byte write enables for SRAM and Flash cycler handles timing of assertion of AACK and TA or of AACK and TEA depending on CLAIM or DOERR status Handles burst single beat with various timings int simple interrupt merge Copyright 1998 Motorola Inc All rights reserved Author Gary Milliorn Revision 0 3 Date 6 21 98 Notes All logic is activ
61. thesis bug optimizes ttl and tt2 away then complains about their absence monitor lt read END BEHAVIOR START is the portion of the memory controller which decodes incoming transfers and decides whether they should be claimed by the controller or terminated with an error condition Copyright 1998 by Motorola Inc All rights reserved Author Gary Milliorn Revision 0 3 Date 9 23 98 Notes All logic is active low when appended with a L Passed speedwave check 6 16 98 Moved ADSC assertion to state machine library ieee use ieee std logic 1164 all MOTOROLA Minimal PowerPC System Design 13 use ieee std logic arith all use ieee std logic unsigned all ENTITY START is PORT tt take tt we L ts L aack L clk rst L claim L doerr L we L in std_logic in std_logic in std_logic in std_logic in std_logic in std_logic buffer std logic buffer std logic buffer std logic end PORT DEFINITION AND ENTITY asserted if good TT selection asserted if good TT is write transfer start strobe asserted on transfer complete bus clock system reset asserted when cycle is claimed asserted when cycle not claimed byte lane write selects ARCHITECTURE BEHAVIOR OF START is BEGIN Derive a D flop to maintain selected status The register must be globally clocked to fit well in the Lattice 2xxx FPGA architecture where clocks and resets are
62. werPC System Design 37 PowerPC a INTO AEE er INT1 a i INT2 e Figure 27 Interrupt Reuse This approach does have several limitations for the MCP interrupt in particular the HIDO EMCP bit and MSR ME enable bits must be properly set and the interrupt remains edge sensitive unless additional external hardware is used For systems needing a more traditional interrupt controller many FPGA vendors offer IP cores which implement PC style 8259 programmable interrupt controllers PIC There are sufficient resources in most FPGAs to include it with the memory controller by adding additional I O controls an 8 bit data bus and INT output and 1 n interrupt inputs Such an interrupt controller can include other advanced features such as edge sensitive to level sensitive conversion and interrupt prioritizing and masking Excimer uses a very simple interrupt merging system though provisions are in place to add programmable I O to do interrupt masking The VHDL code for the Excimer interrupt controller is INT is a small interrupt controller for the Excimer project which fits in some available gates of the Memory Controller MC Copyright 1998 by Motorola Inc All rights reserved Author Gary Milliorn Revision 0 1 Date 6 30 98 Notes All logic is active low when appended with a L Passed speedwave check 6 30 98 library ieee use ieee std logic 1164 all use ieee

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