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IP-OPTODA16CH4

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1. 0 means 10V output range and binary two s complement as output code Reading as 1 means OV to 10V output range and straight binary as output code DAC BUSY DAC Busy flag Reading as 1 indicates that a serial data transfer to the DAC is in progress Write access to the DAC Channel Select Register or DAC Load Register during active DACBUSY status is ignored and sets the Error flag Figure 4 2 STATREG DAC Status Register 12 4 3 Data Register 0x04 The DAC Data Register contains the DAC conversion data used by the DAC Channel Select command A write access to the DAC Channel Select Register starts the serial data transfer to the DAC and if selected the conversion into an analog value Immediately after a write to the DAC Channel Select register the DAC Data Register may be written with the next conversion data value However before the next write to the DAC Channel Select Register the DACBUSY status bit must be O The content of the DAC Data Register is valid until it is re written by the user The DAC Data Register does not need to be updated if the DAC conversion data value for the next DAC Channel Select command should be the same 16 Bit DAC value Bit Number Symbol Description Access Reset Value This register contains the desired DAC 15 0 conversion data value used by the DAC RAN 0x0000 Channel Select comman
2. eeee esee eene nennen tenen nennt nnn nnne 11 4 2 Status Register 0X03 uiua ecd die ic alin Aandi eg 12 4 3 Data Register 0x04 ei aei cer EES needed eda ccs 13 G Load Register 0X07 212 2 nii aee rd aeaaee aaea aa Aa e oc roce dete cee 13 DAG DATA wee cm 14 5 1 Bipolar Output Modle esseeseeeeeeeeeeeeses esee nennen nn nn anas nannten sitas nsn na nass sas eNA sa sR assa a 14 5 2 Unipolar Output Mode esseesesseeeeeeeeeeees seen een pase eame inna sane nsn tR nasi tasas ssa ep Rusa nnns sn nasa 14 JUMPER CONFIGURAT ION c5ccesc ecoute o rece nene e cene amne cene o SEEeEKEESEEe EE EEEEEKEE EEN 15 IP VO CONNEGTOBR eroi e eru se cue ema Enea Emu ER Ee EPu Enc Eo Ea FREE ETE EE re Cu Ee EFE EFE Ee Hv Era Ce rEEEHE 16 7 1 Analog Output Connections sees aa aietan en seen anede snnm ennt than anna nasa natn nn sn sn ansa nnn 16 7 2 Power Input Connections te de een ee 16 FIGURE 1 1 FIGURE 2 1 FIGURE 3 1 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 6 1 FIGURE 7 1 FIGURE 7 2 Table of Figures BLOCK DIAGRAM nee eain Ee ge Hd EE tee ERE E des EE eed ee dde 5 TECHNICAL SPECIFICATION FUNCTIONAL DESCRIPTION eee 6 ID PROM CONTENTS IP OPTODAt19G6CHA sse rennen rennen 9 CHANSEL DAC CHANNEL GEI ECTREGISTER eene 11 STATREG DAC STATUS REGISTER esee ener 12 DATAREG DAG D
3. the ideal gain and the actual gain of the DAC It is corrected by multiplying the data value by a correction factor The data correction values are obtained during factory calibration and are stored in the modules individual version of the ID PROM The DAC has a pair of offset and gain correction values for each single output channel The correction values are stored in the ID PROM as two s complement byte wide values in the range 32768 to 32767 For higher accuracy they are scaled to 1 4 LSB Because offset and gain correction values are dependent on the selected output voltage range the IP OPTODA16CH4 has 2 different sets of ID PROM data Depending on the jumper settings for the voltage range the corresponding set of correction values is automatically selected 2 2 1 DAC Correction Formula for OV to 10V Output Voltage Range The basic formula for correcting unipolar DAC output value is Data Value 1 Gain 262144 Offset 4 Data is the corrected digital value that should be sent to the DAC Value is the desired output value Gaingor and Offset are the correction factors from the ID PROM 2 2 2 DAC Correction Formula for 10V Output Voltage Range The basic formula for correcting bipolar DAC output value is Data Value 1 Gain 131072 OffSetcorr 4 Data is the corrected digital value that should be sent to the DAC Value is the desired output value Gaincor and Offset are the correction factors from th
4. 2 High Byte board dependent 0x33 DAC3 Gain Ch 3 Low Byte board dependent 0x35 DAC3 Gain Ch 3 High Byte board dependent 0x37 DAC4 Gain Ch 4 Low Byte board dependent 0x39 DAC4 Gain Ch 4 High Byte board dependent Not used OxSF 0x00 Figure 3 1 ID PROM Contents IP OPTODA16CH4 4 IP Addressing The IP OPTODA16CH4 is controlled by a set of registers which are directly accessible in the I O address space of the IP All registers are cleared by assertion of IP_RESET Address Name Function Size 0x01 CHANSEL DAC Channel Select Register byte 0x03 STATUS DAC Status Register byte 0x04 DATAREG DAC Data Register word 0x07 LOADDAC DAC Load Register byte 0x09 IDWRENA ID Write Enable Register byte IDWRENA is for factory use only Do not write to this register 4 1 Channel Select Register 0x01 The DAC Channel Select Register is used to load conversion data to the DAC internal data register of a selected DAC channel The DAC Data Register must be set up with the conversion data before the write to the DAC Channel Select Register is performed If Bit 7 is set to 0 the write access to the DAC Channel Select Register does only update the DAC internal data register of the selected DAC channel The DAC outputs are not updated in this case If Bit 7 is set to 1 the write access to the DAC channel Select Register first updates the DAC internal data register of the selected channel After t
5. ATA REGISTER iii ettet ritur rper e Potete ege eles ee 13 LOADREG DAC LOAD REGISTER ancia n aranan nter rr tete e pr n rtr et ined 13 JUMPER CONFIGURATION FOR OUTPUT VOLTAGE RANGE IP OPTODA16CHA4 15 ANALOG OUTPUT CONNECTIONS IP OPTODA1 6CH4 esee 16 POWER INPUT CONNECTIONS IPDOPTODATGCHA 16 Product Description The IP OPTODA16CH4 is an IndustryPack compatible module providing 4 channels of isolated 16 bit analog outputs Settling time to 0 003 is typical 10us The programmable output voltage range is 10V or 0 to 10V selectable by jumper configuration The DAC resets to OV output voltage in both unipolar and bipolar output voltage range The isolated DACs and the output buffers are powered by an on board DC DC converter Optocouplers are used for the DACs digital interfaces Each IP OPTODA16CH4 is factory calibrated The calibration information is stored in the Identification PROM unique to each IP and voltage range E 2 a 3 o o S ex o Figure 1 1 Block Diagram 2 Technical Specification Logic Interface Size UO Interface Analog Outputs Isolation Output Voltage Range Settling Time of DAC Calibration Data Output Current Load Capacitance Accuracy Linearity Monotonicity Wait States Power Requirements Temperature Range Humidity MTBF IndustryPack Logic Interface Single wide IP 50 conductor flat cable 4 D A channels All D A channels are galvanically isolated from th
6. SBS Technologies IP OPTODA16CH4 4 Channels of Optically Isolated 16 Bit D A Conversion User Manual SBS Technologies Inc Subject to change without notice Part Number 89004589 Rev 1 0 20030410 IP OPTODA16CH4 4 channels of optically isolated 16 bit D Aconversion SBS Technologies Inc 1284 Corporate Cenier Drive St Paul MN 55121 1245 Tel 651 905 4700 FAX 651 905 4701 Email support commercial sbs com http www sbs com 2003 SBS Technologies Inc IndustryPack is a registered trademark of SBS Technologies Inc QuickPack SDpacK and Unilin are trademarks SBS Technologies Inc PCeMIP is a trademark of SBS Technologies Inc and MEN Mikro GmbH SBS Technologies Inc acknowledges the trademarks of other organizations for their respective products mentioned in this document All rights are reserved No one is permitted to reproduce or duplicate in any form the whole or part of this document without the express consent of SBS Technologies Inc This document is meant solely for the purpose in which it was delivered SBS Technologies Inc reserves the right to make any changes in the devices or device specifications contained herein at any time and without notice Customers are advised to verify all information contained in this document The electronic equipment described herein generates uses and may radiate radio frequency energy which can cause radio interference SBS Technologies I
7. d Figure 4 39 DATAREG DAC Data Register For data coding see chapter DAC Data Coding 4 4 Load Register 0x07 Every write access to the DAC Load Register updates all 4 DAC outputs with the last value written into the DACs internal data register Write access to the DAC Load Register during active DACBUSY status is ignored and sets the ERROR flag in the DAC Status Register Bit Number Symbol Description Access Reset Value Write access updates all 4 DAC outputs with the conversion data stored in the DACs internal 7 0 data register W E DACBUSY status must be 0 before are write to the DAC Load Register Figure 4 4 LOADREG DAC Load Register 5 DAC Data Coding 5 1 Bipolar Output Mode If the DAC channels are configured for 10V output voltage range by the corresponding jumper configuration the following DAC data coding applies DATAREG OUTPUT Ox7FFF Full scale 0x8000 Full scale 0x0000 Midscale 5 2 Unipolar Output Mode If the DAC channels are configured for OV to 10V output voltage range by the corresponding jumper configuration the following DAC data coding applies DATAREG OUTPUT OxFFFF Full scale 0x8000 Midscale 0x0000 Zero scale 6 Jumper Configuration On the IP OPTODA16CH4 the desired DAC output voltage range is configured by a 3 pin jumper field The configured DAC
8. e ID PROM Gaincor and Offsetco correction factors are stored separately for each for the four DAC outputs Floating point arithmetic or scaled integer arithmetic is necessary to avoid rounding error while computing above formula 3 ID Prom Contents The Voltage Range bit of the DAC Status Register is used to select the correct set of data correction values for the actual selected voltage range transparent for the user 3 1 1D PROM Contents IP OPTODA16CH4 ADDRESS FUNCTION Content 0x01 ASCII TI 0x49 0x03 ASCII PR 0x50 0x05 ASCII A 0x41 0x07 ASCII C 0x43 0x09 Manufacturer ID 0xB3 0x0B Model Number 0x23 0x0D Revision 0x10 OxOF reserved 0x00 0x11 Driver ID low byte 0x00 0x13 Driver ID high byte 0x00 0x15 number of bytes used 0x1D 0x17 CRC variable 0x19 Version 10 0x0A 0x1B DAC1 Offset Ch 1 Low Byte board dependent 0x1D DAC1 Offset Ch 1 High Byte board dependent Ox1F DAC2 Offset Ch 2 Low Byte board dependent 0x21 DAC2 Offset Ch 2 High Byte board dependent 0x23 DAC3 Offset Ch 3 Low Byte board dependent 0x25 DAC3 Offset Ch 3 High Byte board dependent 0x27 DAC4 Offset Ch 4 Low Byte board dependent 0x29 DAC4 Offset Ch 4 High Byte board dependent 0x2B DAC1 Gain Ch 1 Low Byte board dependent 0x2D DAC1 Gain Ch 1 High Byte board dependent Ox2F DAC2 Gain Ch 2 Low Byte board dependent 0x31 DAC2 Gain Ch
9. e IP interface 10V or OV to 10V selectable by jumper common for all 4 channels To 0 003 in 10us typical In ID PROM for gain and offset correction for each channel 4mA for each channel 1nF typical INL 4LSB typical after calibration DNL 0 5LSB 16 bit over the specified temperature range IDSEL 1 wait state IOSEL no wait states 400mA typical 5V no load 430mA typical 5V with 4mA output current for each channel Operating 40 C to 85 C Storage 45 C to 125 C 5 9596 non condensing 283318h Figure 2 1 Technical Specification Functional Description 2 1 Analog Output The IP OPTODA16CH4 includes 4 channels of analog outputs with a resolution of 16 bits and a voltage range of 10V or OV to 10V The maximum output current for each channel is 4mA Each channel has a settling time to 0 003 of typical 10us Two voltage ranges are jumper selectable 10V or OV to 10V Voltage range selection covers all 4 channels The 4 analog outputs of the IP OPTODA16CH4 are galvanically isolated from the IndustryPack logic interface by optocoupler 2 2 Data Correction There are two errors which affect the DC accuracy of the DAC The first is the zero error offset For the DAC this is the data value required to produce a zero voltage output signal This error is corrected by subtracting the known error from all readings The second error is the gain error Gain error is the difference between
10. hat all 4 DAC outputs are updated according to the DAC internal data register of each channel Write access to the DAC Channel Select Register during active DACBUSY status is ignored and sets the ERROR flag in the DAC Status Register AL 0 0 0 0 0 CS1 cso Bit Number Symbol Description Access Reset Value AL Automatic Load after Data Transfer 0 No DAC output update User can update all DAC outputs with a write access to the DAC Load Register or with the next channel selection write with AL bit set to 1 after data transmission 1 All 4 DAC outputs are updated automatically after data transmission to the selected DAC channel R W 6 2 Always read as 0 CS1 CSO Output Channel Selection CS1 CSO Channel 0 Ph 09 ll en 0 1 1 A R W 00 Figure 4 1 CHANSEL DAC Channel Select Register 4 2 Status Register 0x03 Bit Number Description Access Reset Value 7 3 Always read as 0 ERR Error flag Write access to the DAC Channel Select Register or DAC Load Register during active DACBUSY status is ignored and sets this flag to 1 Any write access to the DAC Status Register clears the ERROR flag VR Voltage Range flag Indicates the selected Voltage Range according to the jumper setting for the output voltage ranges Reading as
11. nc assumes no liability for any damages caused by such interference SBS Technologies Inc s products are not authorized for use as critical components in medical applications such as life support equipment without the express consent of the president of SBS Technologies Inc Commercial Group This product has been designed to operate with IndustryPack PCeMIP or PMC modules or carriers and compatible user provided equipment Connection of incompatible hardware is likely to cause serious damage SBS Technologies Inc assumes no liability for any damages caused by such incompatibility Table of Contents PRODUCT DESCRIPTION 2 5 1225251272275 ege ebeheEeE Geiger EbE E E eeE EENEG EGuEeeEeN 5 TECHNICAL SPECIFICATION cscccsscsssscscsssssssccccccscscscsnsccesescesessesescessesceseseseees 6 AW Nb T a i 7 2 2 PrrWenT e 7 2 2 4 DAC Correction Formula for OV to 10V Output Voltage Range seeseeseesseessesseeeereereeee 7 2 2 2 DAC Correction Formula for 10V Output Voltage Range esseeseesseeseeseeeeerrseereerenes 8 ID PROM CONTENTS eese eu naa cts ceca EXER sae sds AXE X EXREEXEN EX RX eX aX XR X EXER N XRn exa n 9 3 1 ID PROM Contents IP OPTODA16CHG eeeeeeeeeeseseseee eee en enne nn nenne nnnm nn nn nna n inta ses nnn nnn 9 xb NIR pto 10 4 1 Channel Select Register 0x01 ueeeeeeee eee eee e eee
12. output voltage range applies to all four DAC channels Jumper Configuration Voltage range OV to 10V J1 1 2 installed Voltage range 10V J1 2 3 installed Industry Pack UO Interface o S E 5 2 o 9 D a E 3 3 Figure 6 1 Jumper Configuration for Output Voltage Range IP OPTODA16CH4 Factory configuration is OV to 10V output voltage range for all DAC channels 7 IP I O connector 7 1 Analog Output Connections Pin Number Signal 01 DAC_OUT1 02 AGND 03 DAC_OUT2 04 AGND 05 DAC_OUT3 06 AGND 07 DAC_OUT4 08 AGND Figure 7 1 Analog Output Connections IP OPTODA16CH4 7 2 Power Input Connections Pin Number Function 44 AGND 45 15V 46 AGND 47 15V 48 AGND 49 5V 50 AGND Figure 7 2 Power Input Connections IP OPTODA16CH4 The power input connections are reserved for special versions of the card without on board DC DC converter Do not supply any voltage to these pins for the IP OPTODA16CH4

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