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SBC610 6U VPX Single Board Computer

1. Table 5 27 PMC XMC Site 2 Signal Availability 2 P16s X12d COM3 6 Option P485 X12d C0M5 6 Option PMC P5 COMs P5 XMC P6 PMC P5 PMC P5 COMs P5 XMC P6 0 Pin Pin 1 0 Pin 1 0 Pin 1 0 Pin P 0 Pin P24 IO 1 El COM3 RX B E5 P2610 A05 EL P24 JO 1 El P24 10 33 9 COM5_RX_B E13 P26 0 A05 E P24 IO 2 B1 COM3RXA D5 P26_10_B05 D1 P24 IO 2 B1 P24 IO 34 B9 COM5 RX A D13 P2610 B05 D1 P24 IO 3 D1 COM3_TX_B B5 P26 0 D05 B1 P24 IO 3 D1 P24 10 35 D9 COM5_TX_B B13 P26_I0_D05 B1 P24 IO 4 Al COM3_TX_A A5 P26 0 E05 Al P24 JO 4 Al P24 1036 A9 COM5_TX_A A13 P261 0 E05 Al P24 IO 5 F2 COM3 CTSB F6 P2610 A07 F2 P24 10 5 F2 P24 IO 37 F10 COM5_CTSB PA P2610 A07 Fe P24 IO 6 C2 COM3CTSA 6 P2610 B07 E2 P24 IO 6 C2 P24 10 38 C10 COM5_CTS_A 14 P2610 B07 E P24 IO 7 E2 COM3_RTS_B C6 P26_10_D07 C2 P24 IO 7 E2 P24 10 39 E10 COM5_RTSB C14 P2610 D07 C2 P24 IO 8 B2 COM3RTSA B6 P260 E07 B2 P24 10 8 B2 P24 1040 B10 COMS_RTS A B14 P26_10_E07 B2 P24 10 9 E3 COM3_RT_B E7 P26_I0 A09 E3 P24 10 9 E3 P24 IO 41 11 COM6_RX_B E15 P26_10_A09 E P24 I0 10 B3 COMSRTA D7 P26_10_B09 D3 P24 1010 B3 P24 1042 B11 COM6_RX_A D15 P261 O B09 D3 P24 1011 D3 COMS3TTB 87 P26 0 D09 B3 P24 1011 D3 P24 1043 D11 COM6 IX B 815 P2610 D09 B3 P24 1012 A3 COMS3TTA A7 P26 0 E09 A3 P24 10 12 A3 P24 1044 All COM6 IX A A15 P26 O0 E09 A3 P24 1013 F4 COM3 ST B F8 P26 0 A15 F4 P24 10 13 F4 P24 I0 45 F12 COM6_CTSB F16 P26_I0_A15 F4 P24 IO 14 C4
2. A f lag 64 J23 2 lea nnnnninnnnnnnnnnnnnnnnnnnnnnnnnij npnnnnnnnnnnnnnnnnnunnnnnnnnnnnil pnnnnnnnannnnnnnnnnnnnnnnnnnnnnil i E 1 es 1 2 64 2 loa pu 2 ON ON eee bed bred Ea TOOT TOMO ETUR MEI o eraf D sea H e Ug Og Ug H sai a d A ENEE EEN EIER ei J24 2 lea J22 2 64 J14 2 164 302 2 ITUR OOO CON 102 SBC610 6U VPX Single Board Computer AO Publication No SBC610 0HH 2 7 1 Backplane Connectors The following sections show the pin assignments of the SBC610 VPX backplane connectors PO to P6 These are shown in the 7 row format as used in the VPX specifications Also provided are the corresponding pinouts for the JO to J6 backplane connectors These are shown in the 9 row format dat NOTE Direction of fabrics is shown such that TX is an output from the SBC610 and RX is an input to the SBC610 7 1 1 PO Table 7 2 PO Pin Assignments Pin A B C D E F G J C Vs2 N C Vs2 N C Vs2 N C N C Vs1 N C Vs1 N C Vs1 2 IC Vs2 N C Vs2 N C Vs2 N C N C Vs1 N C Vs1 N C Vs1 3 5V Vs3 5V Vs3 5V Vs3 N C 5V Vs3 5V Vs3 5V Vs3 4 VMRO SYSRESET GND N12V AUX GND N C SM3 N C SM2 5 SM_DATA SM_CLK GND P3V3_AUX GND GA4 GAP 6 GA0 GA1 GND P12V AUX GND GA2 GA3 T JTAG TRST JTAG_TMS GND JTAG TDI JTAG TDO GND JTAG TCK 8 GND N
3. 3 4 1 AFIX Installation AFIX modules are supplied factory fitted and are a build option see the Product Codes section The current range of AFIX cards includes support for dual MIL STD 1553 interfaces AFIX1553 SCSI and graphics AFIXSG USB Flash memory AFIXM and differential GPIO AFIXDIO1 The AFIX site also allows specific customer requirements to be accommodated more quickly and easily than a modification to the main host board Contact your local GEIP sales representative with any specific requirements For more details on AFIX see the AFIX family manual ON LINKS AFIX Family Product Manual publication number AFIX OHH Publication No SBC610 0HH 2 Configuration 29 4 e Installation and Power Up Reset Review the Safety Notices section before installing the SBC610 The following notices also apply N CAUTION Consult the enclosure documentation to ensure that the SBC610 s power requirements are compatible with those supplied by the backplane 4 1 Power Supply Requirements The SBC625 requires the backplane to provide 5V VS3 and 3V3_AUX supplies Requirements are as follows Table 4 1 Power Supply Requirements Supply Current Requirement VPX Specification Limits VS3 Upto 18A 5 V 5 2 5 P3V3_AUX Up to 100 mA 3 3 V 5 No voltage is required to be supplied on the Vs1 and Vs2 supplies as the SBC610 does not connect to these pins P12V_AUX and N12V_AUX are not
4. Features Details Comments Processor Freescale MPC8641D Contains two e600 PowerPC processing cores 8 1 13GHz RAM d O Dual memory controllers running at 266 MHz 16 MBytes allocated to Boot Flash and the rest to User Flash SH Up to 16Byte Flash memory Advanced sector protection features NOVRAM 128 KBytes Non volatile storage for data that must not be lost when power is removed Power down Autostore functionality Infrastructure PCI Express High bandwidth serial interconnect Non blocking switch architecture Ethernet ports 2 x 10 100 1000BaseT 2 x RS232 debug Serial ports 2 x RS232 422 485 Sync Async ie al Nd cOM2 genugport 2 x RS232 422 485 Async P VME Tundra Tsi148 64 bit VME with 2eSST support Two programmable DMA controllers USB 2 ports USB2 0 capable SATA 2 channels Supports speeds of up to 1 5 Gbps Discrete Digital 0 Up to 19 bits TTL compatible Able to generate edge or level triggered interrupts SRIO Two fixed links two optional Shared with PCI Express PCI Express Two optional links Shared with SRIO PMC XMC Two sites AFIX Site Additional functionality Dual MIL STD 1553 interfaces SCSI Graphics USB Flash Memory USB2 0 routing modules DMA Controllers 4 Available in the MPC8641D for efficiently moving large blocks of data Provided by the MPC8641D Programmable frequency with up to 15 ns resolution Tinere LE Ability to cascade to form larger timers Watchdog timer Two 32 bit ti
5. ettet 95 6 17 Board Interrupt Core O MCP Mask Register Offset OA0189 ettet 96 6 18 Board Interrupt Core 1 MCP Mask Register Offset D 96 6 19 PCI Express Block Configuration Register Offset 0x5000 ettet 96 6 20 PCI Express Block Semaphore Registers Offset 0x5010 to Ob 97 6 21 PCI Express Scratchpad Registers Offsets 0 5020 and 0x5024 ttt 97 6 22 PCI Express Doorbell Assert Register Offset OX5030 ooo 97 6 23 PCI Express Doorbell Clear Register Offset OPO ZA 98 6 24 PCI Express Doorbell Status Register Offset OX5038 ooo 98 6 25 AXIS Timestamp Low and High Value Registers Offsets 0x6000 and 0x6004 1151051111112 99 6 26 AXIS Timer Control Register Offset OX6008 oda 99 6 27 AXIS Semaphore Registers Offsets 0x6020 to 0x603 Clone 99 6 28 FIFO Data Registers Offsets OX6040 to OX60W4Cl cocos 100 6 29 FIFO Status Registers Offsets 0x6050 to KODBC ee 100 psc PGA REJSTES ae iene aa II E UE 101 EIERE me eet 102 Eeer 103 A Sa Sasso cases cccccaayspnncee aataeanneodeaaten ned aaa eannnoteaaa an aiden eee 103 TAS Elle ENEE 103 e TEE 104 AA ius c E 104 FAC LA A E 105 ES ROEDER 105 a aL A 106 EE o nc J c SSS ANN 107 SEENEN 108 71 10 Backplaldeld eese d E 108 E E EIK nS OANE 109 4A T2 Baeckplane IS EAEE 110 Ee NPG eo welsscsescccsissoscsavoosscscccccasusssecsnssasssscconce
6. M 104 DPD M IQ 105 106 A t ERE ERAI SEI ORTI Ye re 108 PO 109 DG eege 111 B 123 FPGA Programming sese 124 Sp 115 BEE 115 jp 116 JAA A heir emi n petes 116 Jp 118 p 125 le M o 123 P22 124 i rta 121 PCI Express Mid Bus Probe 125 PM einet erie N NaS 115 Index 135 C continued Connectors continued Positions 2e inii ere eR ESI ege 102 Signal Descriptions ye a D ee tee 122 AAA n iEn nnn 112 PMC ore eee E 117 AMC noticia lidia 120 Ke 118 Cooling smit potat 18 127 Current Consumption sse 128 D DIMENSIONS ien eter inici 126 Documentation Conventions essen 3 E EEPROM iere Tere eae S 70 Electrical Specification 128 E IT 31 Regulatory Compltance 17 Environmental Dpechfieattons 127 Equipment Number 19 Eterna dida te REF E IO 49 Link Status LEDen 80 ET titi 68 F Bbeatutes rre P ERR ERR TR PE 35 Flammability 1er three rente tnos 17 Blasio RENE INNEREN ees 39 Ee auereeiene ness 40 Control Register EE 91 MAC Address Mirror esee 42 I ul 42 Protection Unlock Lmk sss 24 Redundant Mode esee 42 Sector Proteclion isso 43 RE 41 Write Enabling seriis rirerire 24 FPGAs He E
7. 1 1 5 Heatsink A CAUTION Do not remove the heatsink There are no user alterable components underneath the heatsink so users should have no reason to remove it Users should not attempt reattachment of the heatsink as this requires precise torque on the screws attaching the heatsink to the PCB Over tightening the screws may cause the heatsink to damage components beneath it Removal and re attachment of the heatsink should only be carried out by the factory 18 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 2 Unpacking On receipt of the shipping container if there is any evidence of physical damage the Terms and Conditions of Sale provided with your delivery give information on what to do If you need to return the product contact your local GEIP sales office or agent The SBC610 is sealed into an antistatic bag and housed in a padded cardboard box Failure to use the correct packaging when storing or shipping the board may invalidate the warranty 2 1 Box Contents Checklist 1 SBC610 in antistatic packaging 2 Embedded Software License Agreement GFJ 353 2 2 Identifying Your Board The SBC610 is identified by labels at strategic positions These can be cross checked against the Advice Note provided with your delivery Identification labels similar to the example shown in Figure 2 1 attached to the shipping box and the antistatic bag give identical information product code product descrip
8. LINK A and B Serial RapidlO LINK x Ln Hab LINK Cand D Serial RapidlO or PCI Express depending on the state of links E24 and E25 and Control Register 2 LINK x Ln TXN Backplane fabric transmit outputs These should be connected to the receive inputs of another board to create a link UNKA and B Serial RapidlO LINK_x_Ln_TXP LINK Cand D Serial RapidlO or PCI Express depending on state of links E24 and E25 and Control Register 2 Inter board PSU Sequencing input The SBC610 will not start its on board supplies whilst this signal is driven low This can be PSU SEQ I connected to the PSU SEQ OUT signal of another board to allow the boards to power up in sequence A 500 ms timeout applies in case the preceding board has a fault This pin may be left unconnected if inter board power sequencing is not required Inter board PSU Sequencing output Driven low when the backplane supplies are out of specification and held low until all on PSU SEQ OUT Ee board supplies are in specification SYS CON Pulled low by the backplane to indicate that the module is the VPX System Controller VBAT Battery supply Can be used to power the RTC on the SBC610 max current approximately 1 pA 112 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Signal Description VME A 31 01 VME Address bus VME_ACFAIL AC Failure Can be used by the sys
9. functions e Power Supplies e BIT e e Ethernet links e SATA activity e Reset Status Figure 5 11 LED Positions E Oo Ds DOT DTD D Pi N PA a a A 2 g m DS339 Moss sos D ese ces y ela Bl os318 El E lb DEI EGER ES EEG bes og AE EET e nd HO En enm mm B Ea H 00 nnngnnl H Do he 755155570 d EC n lA ci Sg Se o B a H PEL firm wm e En a Sch voa Dad UE TI npe RR D D a QO CI Ej C EJ 007 E nn UT ES Es bon bag o 000000 TAI a E n oo TIO DEI e Bum Ge a pu E je a Us CETE aum ca e 8 Soe Ej mm 28 ana IH 0r 5 cs mmm M O000000000000 Jo m rmn cy T c q 0S 00000000 DCD C3 cr O T D D D TRES Bal
10. A A S as ci Eo eB MINI Ed EDI MEME DEM III M MM 3 3 1 Core O Boot Area Selection Links E12 and E14 3 3 2 Core 1 Boot Area Selection Links E13 and E14 5 3 RECOVELY Boot LCE ELA T 3 3 4 Boot Flash Write Enable Link E15 and User Flash Write Enable Link E16 nnne 24 3 3 5 Flash Protection Unlock Link E17 3 3 6 NVRAM Write Enable Link E18 3 3 7 SMP Mode Link E19 ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt tbt ttt tatUs 3 5 Mdeewenkiszi 3 3 9 Boot Hold off Link E21 3 3 10 Factory Link E22 oeeessssssssssssssseseessssseeseeusssseeeeeneee 3 3 11 JTAG Scanbridge Output Enable Link E23 3 3 12 PCI Express Selection Links E24 and E25 3 3 13 AFIX Links E26 and E27 5 5 14 Spare Linke lE28 ere 3 4 Mezzanine Instollotion raras 3 4 1 PMC Installation 3 4 2 XMC Installation 3 4 1 AFIX Installation 4 e Installation and Power Up Reset ssssetttttttnn ntt nensis EE EE 4 2 BOATA KEYIN acis o e INT ENE OA AS Board Insta las ld ula 4 4 Connecting to SBC610 AR A El 45 Resetand PO EE EE continued overleaf Publication No SBC610 OHH 2 Contents 7 5 Functional Descrip aaa ina BUF ee ee EEN ENEE A A ele E Eeer Processing COTE EES EE ee Lee E 5 2 5 Processor Power Management Spade M 5 2 5 Memory MODs ne RR RERO ERR RE RE RR RE D ERRORES 5 2 6 L
11. 0 The EEPROM is write protected by default and can be write enabled by clearing the PC EEPROM Write Protect bit in Control Register 1 This bit may only be cleared when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low Publication No SBC610 OHH 2 Functional Description 69 5 17 8 MPC8641D Configuration EEPROM Initial configuration of the processor is performed by driving strapping signals to the correct state during reset An PC EEPROM is provided should further configuration information need to be loaded into the device before software boots The processor s boot sequencer which uses the EEPROM is always enabled and the device must therefore be loaded with valid data including preamble and CRC at all times for the processor to boot correctly If valid data is not read then the device will request a hard reset The EEPROM is write protected by default and can be write enabled by clearing the PC EEPROM Write Protect bit in Control Register 1 This bit may only be cleared when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low The processor can be prevented from accessing the EEPROM in the event that the data becomes corrupted and configures the device such that the EEPROM contents cannot be overwritten by fitting the Recovery Boot Link E14 The EEPROM should then be reprogrammed with a valid ima
12. PMC2 Bridge prevented from configuring from Serial EEPROM e e e 0 PMC1 Bridge allowed to configure from Serial EEPROM i PMCI Bridge Serial EEPROM disable PMC1 Bridge prevented from configuring from Serial EEPROM 6to29 Reserved 0x0000 0 Serial RapidlO 30 Backplane fabric port 4 type 1 PCI Express The default value of this register is defined by the state of link E25 at reset 0 Serial RapidlO 31 Backplane fabric port 3 type 1 PCI Express The default value of this register is defined by the state of li nk E24 at reset a These bits are always set to 1 and are not writeable if the Recovery Boot Link E14 is fitted BOOT RECOVERY signal is active to prevent EEPROM contents being used If the link is not fitted these power up and not following reset If a device needs to be reconfigured witho software and a board reset applied 90 SBC610 6U VPX Single Board Computer registers are sticky They are only cleared at ut its EEPROM these bits can be set by Publication No SBC610 0HH 2 6 8 Flash Control Register Offset 0x001C Table 6 9 Flash Control Register Bits Mode Description Notes 0to15 RO Reserved 0x0000 6 RO Flash bank 3 busy Q Flash barik regy 1 Flash bank busy 0 Flash bank ready 17 RO Flash bank 2 busy 1 Flash bank busy 0 Flash bank ready 18 RO Flash bank 1 busy 1 Flash bank busy 0 Flash bank ready 19 RO Flash bank 0
13. 128 MBytes 128 MBytes 28 MBytes 128 MBytes Bank 1 ANDed Bank 1 ANDed Bank 1 upper 16 bits Bank 1 lower 16 bits 128 MBytes 128 MBytes 128 MBytes 128 MBytes Bank 3 ANDed Bank 3 ANDed Bank 3 upper 16 bits Bank 3 lower 16 bits 128 MBytes 128 MBytes 28 MBytes 128 MBytes Bank 0 ANDed Bank 0 lower 16 bits 128 MBytes 28 MBytes Bank 2 ANDed Bank 2 lower 16 bits 128 MBytes 128 MBytes Bank 1 ANDed Bank 1 lower 16 bits 128 MBytes 28 MBytes Bank 3 ANDed Bank 3 lower 16 bits 128 MBytes 128 MBytes Chip Select 1 Chip Select 2 Chip Select 1 Chip Select 2 1 GByte Flash option 1 GByte Flash option 1 GByte Flash option 1 GByte Flash option 16 bit normal mode 16 bit normal mode 16 bit debug Mode 16 bit debug mode This is feature is part of the Nuclear Event Detection hardware build option 5 4 6 Flash Sector Protection The SBC610 uses Spansion S29GL01GP Flash devices which provide advanced methods of sector protection to ensure the integrity of code data contained in the Flash array Protection is defined on a per sector basis where a sector is 256 KBytes in size Locked sectors cannot be erased or programmed they may only be read No write protection of Flash is provided by hardware Software must be used to configure the Flash devices to protect against corruption of Flash data The following types of protection are provided 1 Persistent sector protection provides non volatile protection that remains in
14. 16 GND Table 7 28 P20 Signal Descriptions Signal Description JTAG CPU TCK Processor JTAG Test Clock JTAG CPU TMS Processor JTAG Test Mode Select JTAG CPU TDI Processor JTAG Test Data In JTAG CPU TDO Processor JTAG Test Data Out JTAG CPU TRST Processor JTAG Test Reset BDM SRESET Soft Reset Input BDM_HRESET_CPU Hard Reset Input CPU CHKSTP IN Checkstop In Forces processor to the Checkstop state CPU CHKSTP OUT Checkstop Out Indicates that processor is in the Checkstop state 3 3V PULL UP Power on status signal to RISCWatch hardware GND Signal ground N C ZN CAUTION No Connection When using this connector ensure that the JTAG Scanbridge is disabled link E23 is not fitted Publication No SBC610 OHH 2 Connectors 123 7 6 FPGA Programming Header P22 P22 is used to access the FPGA JTAG chain for device programming This is for factory use only Table 7 29 P22 Pin Assignments Pin Description 3V3_AUX JTAG TAP6 TDO JTAG TAP6 TDI N C KEYWAY JTAG TAP6 TMS GND JTAG TAP6 TCK Le d Be ZB fa EZ WE CECR NNN d Table 7 30 P22 Signal Descriptions Signal Description JTAG TAP6 TDO FPGA JTAG Test Data Out JTAG TAP6 TDI FPGA JTAG Test Data In JTAG TAP6 TMS FPGA JTAG Test Mode Select JTAG TAP6 TCK FPGA JTAG Test Clock 3 3V_AUX Power indicator to programming hardware GND ZN CAUTION When using this header ensure that the JTAG Scanbridge is dis
15. In RS485 mode the serial controller automatically disables the transmit buffer after transmission is completed The serial ports are intended only to be used by GEIP software drivers See the relevant software manual for details The following COM5 and COM signals are available through the P5 connector under certain I O configuration options Table 5 15 COM5 6 Serial Port Signal Set ius iuis DS Ge SS Input Output P5 Pin DR iin PE G Ee Input Output P5 Pin COM3 TXD COM3 TX A COM3 TX A Output A13 COM4 TXD COMA TXA COMA TXA Output A15 Not Used COM3 TX B COM3 TX B Output B13 Not Used COM4 TXB COMA4 TXB Output B15 COM3_RTS COM3_RTSA COM3_ TTA Output B14 COM4_RTS COM4_RTS A COM4_TT_A Output B16 COM3 DIR COM3 RTS B COM3 TTB Output C14 COM4 DTR COMA RTS B COMA TIT B Output C16 COM3 RKD COM3 RKA COMSRXA Input D13 COM4 RXD COM4 RXA COMARXA Input D15 COM3 DR COM3 RKB COMSRXB Input E15 COM4 DSR COMA RXB COMARXB Input E15 COM3 CIS COM3CTSA COM3_RT_A Input E14 COM4 CTS COMA CTSA COMARTA Input E16 COM3_DCD COM3 CTS B COMSRTB Input F14 COM4 DCD COM4 CTS B COMART B Input F16 52 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 11 USB An NEC uPD720101 device provides five USB ports on the SBC610 and is connected to a 32 bit 33 MHz PCI bus The device is capable of operation at low full or high speed The device contains two OHCI controll
16. KE Core O Main Boot Area OxFFE00000 OxFFCO0000 swapped using OxFFA00000 ore 1 Main Boot Area i i OxFF600000 a register bit OxFF400000 swapped using OxFF200000 OxFFOOOQ000 40 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 The active boot image for each processing core is selected using the appropriate links E12 and E14 for Processing Core 0 and E13 and E14 for Processing Core 1 It may also be affected from the backplane using the BOOT_SWAP0 or BOOT SWAPI inputs These signals are pulled up on board and may be pulled low externally to select an alternate boot image for each processing core Table 5 5 Boot Image Selection E12 EA BOOT SWAPO CoreOActive Boot Image E13 E14 BOOT SWAP1 Core 1 Active Boot Image Out Out 1 Main Out Out 1 Main In Out 1 Alternate n Out 1 Alternate Out In 1 Recovery Out In 1 Recovery In In 1 Extended n In 1 Extended Out Out 0 Alternate Out Out 0 Alternate In Out 0 Main n Out 0 Main Out In 0 Extended Out In 0 Extended In In 0 Recovery n In 0 Recovery Publication No SBC610 0HH 2 The Core 1 boot region is made active by setting the Core 1 Enable bit in the Flash Control Register If a separate boot image is required for Core 1 Core 0 should boot normally from its boot region and then set this bit before allowing Core 1 to boot 5 4 2 User Flash Any Flash that is not used as Boot Flash is designated as User Flash an
17. Table 5 20 GPIO Line Routing GPIO Line P4llnputPin BA Output Dim P6 Pin GPIO Line P4llnputPin BA Output Dim P6 Pin 0 H2 B5 F8 10 H20 A17 E15 1 H3 A6 89 11 H21 A21 E14 2 H5 A8 B10 12 H23 B21 F14 3 H6 A9 F10 13 H24 A22 A15 4 H8 B12 B11 14 H26 A24 B15 5 H9 A13 D11 15 H27 B24 D15 6 H11 B13 E11 16 H29 A25 E15 7 H12 A14 C12 17 H30 B25 B16 8 H14 A16 A13 18 J29 A28 C16 9 H15 B16 813 54 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 When no AFIX is fitted the P6 pinout on rows 7 to 16 is as follows Table 5 21 P6 Pin Assignments No AFIX Fitted Pin A B E D E E G 7 No connection No connection GND No connection o connection GND o connectio 8 GND No connection No connection GND o connection GPIOO GND 9 No connection GPIO1 GND No connection o connection GND o connection 0 GND GPIO2 No connection GND o connection GPIO3 GND 1 Noconnection GPIO4 GND GPIO5 GPIO6 GND o connection 2 GND No connection GPIO7 GND o connection No connection GND 15 GPIO8 GPIO9 GND No connection GPIO10 GND o connection 14 GND No connection No connection GND GPIO11 GPIO12 GND 15 GPIO13 GPIO14 GND GPIO15 GPIO16 GND o connectio 16 GND GPIO17 GPIO18 GND No connection BITFAIL GND 5 14 Off Board Serial Fabrics VITA46 makes provision for four x4 off board serial fabric links from the P1 connector The SBC
18. 0 FIFO normal operation default 27 FIFO reset 1 FIFO reset 0 FIFO not full 28 FIFO full 1 FIFO full 0 FIFO has more than 1 space 29 FIFO almost fulle 1 FIFO has only 1 space 0 FIFO has zero or more than 1 entry e HESPER 1 FIFO has only 1 entry 0 FIFO not empty a PIR empty 1 FIFO empty default on reset a Read only 100 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 6 30 I O FPGA Registers All of the registers concerned with General Purpose I O and control of COMG to COM6 on the SBC610 are contained in the I O FPGA The register definitions are not documented in this manual as they are intended only to be accessed by GEIP software drivers Publication No SBC610 0HH 2 Control and Status Registers 101 7 e Connectors Table 7 1 Connector Functions Connector PO Function VPX utility Connector P21 Function JTAG factory use only P1 P2 VPX P1 VPX P2 P22 P41 FPGA header AFIX P3 VPX P3 J15 J16 XMC site 1 P4 VPX P4 J25 J26 XMC site 2 P5 VPX P5 311 312 318 314 PMC site 1 P6 VPX P6 Jet Jee J2 3 J24 PMC site 2 P20 Figure 7 1 Connector Positions BDM header J29 PCle mid bus probe header factory use only I D F19 E fa J26 d 4 J25 EL F19 Ai D Al J16 F1 F19 E A19 Al d J5 d F19 Fl oo
19. 1 GByte Flash Option 1 GByte Flash Option 5 4 5 Redundant Flash Mode The SBC610 provides an option where the configuration of the Flash width is changed to 16 bit and each data word is stored in two Flash devices in parallel The data read from the Flash is then the logical AND of the data from each device ensuring that any bits that have become unprogrammed in one of the devices due to exposure to radiation for example do not result in a corruption of the data returned In this mode the Flash capacity is halved and access times may be increased Writes to the Flash are sent to both devices in parallel and the software should poll the appropriate busy bit within the Flash Control Register to ensure that the write has completed in both devices before further commands are issued In this mode it is possible to read or write the contents of each device independently by enabling a debug mode within the Flash Control Register This allows BIT or other software to verify each Flash image separately and even correct any errors that are detected 42 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Figure 5 6 Redundant Flash Mode Mapping Bank 0 ANDed Bank 1 ANDed Bank O upper 16 bits Bank 1 upper 16 bits 128 MBytes 128 MBytes 128 MBytes 128 MBytes Bank 2 ANDed Bank 3 ANDed Bank 2 upper 16 bits Bank 3 upper 16 bits
20. 125 GHz The initial configuration of the ports is set by hardware strapping options as follows Table 5 24 SRIO Hardware Strapping Options Port Width LinkTo Lane Reversal Speed Power Down 0 x4 MPC8641D SERDES2 Port No 3 125GHz No 2 xd eat SES iS 3125GHz Yes 4 x4 Backplane Fabric Link 1 o 3 125 GHz Yes 6 x4 Unused o 3 125 GHz Yes 8 x4 Unused o 3 125 GHz Yes 10 x4 ERE HK qe 3125GHz Ves 12 x4 Backplane Fabric Link 2 o 3 125 GHz Yes 14 x4 Unused o 3 125 GHz Yes All SRIO ports are powered down by default by resistor strapping options Any ports that are required to be used must be enabled either by configuration EEPROM or software via PC The default port speed is configured by resistor strapping options to be 3 125 GHz Publication No SBC610 OHH 2 Functional Description 57 An PC configuration EEPROM for the switch is provided on PC Bus 2 to allow initial power up configuration to be performed if required The EEPROM is write protected by default to ensure its contents are not corrupted It may be write enabled by software only when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector DO pin A4 is inactive low The switch can be prevented from accessing the EEPROM under software control if the data becomes corrupted and configures the switch such that it cannot be overwritten This may be done by setting the Tsi578 PC EEPROM Disable bit in Control Register 2 or by fi
21. 5 15 3 PCI Express Mezzanine Cards XMCs Each site also provides Jn5 and Jn6 connectors Jn5 provides a x8 PCIe link to the PEX8548 switch and Jn6 is used to route XMC I O to the backplane 5 15 4 1 0 Routing Rear I O tracking is provided from the Jn4 and Jn6 connectors of both PMC XMC sites to the rear connectors in accordance with VITA 46 9 This can be in one of the following configurations For Site 1 e P64sX12d full 64 PMC signals from J14 and 12 differential XMC signals from J16 e X20d38s 10 PMC signals from J14 full 20 differential and 38 single ended XMC signals from J16 For Site 2 e P64sX12d full 64 PMC signals from J24 and 12 differential XMC signals from J26 e X20d38s 10 PMC signals from J24 full 20 differential and 38 single ended XMC signals from J26 e 16 PMC signals from J24 12 differential XMC signals from J26 COM3 4 5 6 e 48 PMC signals from J24 12 differential XMC signals from J26 COM5 6 The configuration selected can be read from the Board Configuration Register Further custom splits are possible if required to suit a particular mezzanine card The I O from PMC connector Jn4 pins 1 to 48 is tracked as 50Q single ended signals and that from pins 49 to 64 is tracked as 1000 differential pairs 49 and 51 50 and 52 etc The I O from XMC connectors Jn6 pins C1 to C19 and F1 to F19 is tracked as 50O Single Ended signals and that from columns A B D and E is tracked as 1000 differential pairs A01
22. 58 80 PEX8518 PCI Express Switch 70 EO Elapsed Time Indicator 6B D6 PCle Clock Generator 6E DC Bus 2 Tsi578 Serial RapidlO Switch 02 04 RAM Channel 1 Config EEPROM 50 A0 RAM Channel 2 Config EEPROM 51 A2 Tsi578 Config EEPROM 52 A4 5 17 3 Real Time Clock The SBC610 provides an Epson RX8581 RTC which has a minimum of 1 second resolution This device can be powered from the P3V3_AUX supply or the VBAT signal P1 pin G3 when the main power supply is removed The interrupt output of this device can generate an interrupt to either processor core via the Register FPGA 5 17 4 Elapsed Time Indicator A Dallas DS1682 ETI logs the amount of time the SBC610 has been powered and the number of power cycles 5 17 5 Temperature Sensors The SBC610 has two temperate sensors an ADT7461 remotely monitors the MPC8641D core temperature and the ambient temperature and an LM92 monitors the ambient temperature on the PCB The interrupt outputs of these devices can generate interrupts to either processor core via the Register FPGA at two software defined thresholds One of these thresholds can optionally be configured to generate a Machine Check exception 68 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 17 6 Power Manager The SBC610 uses a Lattice ispPAC POWR1014A to monitor and sequence the on board voltages The device provides an PC interface that can be used to access an internal A to D converter to measu
23. 72 Local Bus Control 72 Programming Connector e 124 E M M 72 Front Panel 83 84 See ATSO tee oce edes Chassis Ground Functional Description 34 136 SBC610 6U VPX Single Board Computer G GPIO lana dis 54 H ee eere reete ete ene tentus 18 CALS Wie e O teste tee ette de een 18 Host Processor eee enn nennen 36 Configuration EEPROM sss 70 PCI Express Connechon sese 45 Power Management 37 SMP Mode Selection see 25 et 127 I O Capabilities re ttt enn 49 VO MO Gules culo 132 PO B se8 eras en ter ert e Ee e ree ep diia 67 Addressing acie inmensa ente rient 68 RESC d 67 Identifying Product ue 19 Jnspechon EE E E 22 lacu 74 External cete iere 76 Handling esee tomen mte ies 64 ak 64 jo MM 76 hull 76 Status Register sssssssssssseeeeeete 94 ao AAA 16 J Du lcm TT 78 Scanbridge Output Enable sss 26 Jumpers annee See Configuration Links K Xa pDa 30 L E SR E IAS 19 INDE RM 79 Backplane PCI Express Lane Status 82 BI c UE UE Le tem cs 80 Ethernet Link Status esee 80 PCI Express Link Status sss 81 Reset Sta EUS isaac 81 SATA Activity rte teresa spine 81 TS See Configuration Local Bus tester a 38 Publication No SBC610 0HH 2 M Machine Check Exception cc
24. BIT MODE1 signal high 1 BIT_MODE1 signal low 9 BIT Mode 0 0 BIT MODEO signal high 1 BIT MODEO signal low 20 on Volatile Memory Read Only 0 NVMRO signal high protected 1 NVMRO signal low writeable 21 pare link E28 co 22 MP Mode link E19 23 VRAM Write Enable link E18 co 24 Factory link E20 25 Flash Protection Unlock link E17 Set to 0 if the NVMRO signal is active high 26 User Flash Write Enable link E16 Set to 0 if the NVMRO signal is active high 27 Boot Flash Write Enable link E15 Set to 0 if the NVMRO signal is active high 28 Reserved Ob 29 Recovery Boot link E14 30 Core 1 Boot Area Selection link E14 31 Core 0 Boot Area Selection link E12 88 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 6 6 Control Register 1 Offset 0x0014 Table 6 7 Control Register 1 Bits Description Notes 0 aa 0 BMM PROGRAM EN signal inactive default prog g 1 BMM PROGRAM EN signal active 0 Voltage inactive default 1 BMM programming voltage 1 Voltoge active RE 0 Data line is input default 2 BMM programming data line direction 1 Dato line is output eer 0 Data line input low 3 BMM programming data line input value 1 Data line input high A 0 Data line output low default 4 BM
25. COM3_STA E8 P260 B15 E P24 1014 C4 P24 IO 46 C12 COM6_CTSA 16 P26 O0 B15 E4 P24 10 15 Ei COM4_RX_B E9 P26 0 D15 C4 P24 10 15 Ei P24 1047 E12 COM6_RTS B C16 P2610 D15 C4 P24 10 16 B4 COMA RX A D9 P260 E15 B4 P24 IO 16 B4 P24 1048 B12 COMO RTSA B16 P26 O E15 B4 COMA TX B B9 P260 A17 ER P24 1017 EN P26_10_A17 EN COMA TX A A9 P260 B17 D5 P24 IO 18 B5 P26_10_B17 D5 COM4_CTS_B F10 P2610 D17 B5 P24 I0 19 D5 P26_10_D17 B5 COM4 CTSA E10 P26 IO E17 A5 P24 I0 20 AS P26_10_E17 A5 COM4_RTS_B C10 P26 I0 A19 F6 P24 I0 21 F6 P260 A19 F6 COMA RTSA B10 P2610 B19 6 P24 I0 22 C6 P260 B19 Ep COMA RT B E11 REES e P24 10 23 Ep P2610 D19 C6 COMA RT A D11 P26 O E19 B6 P24 I0 24 B6 P26_10_E19 B6 COMA TT B 811 P24 10 25 Ei COM4_TT_A A11 P24 I0 26 Di COMA ST B F12 P24 10 27 Di COMA ST A E12 P24 10 28 A7 COM RN B E13 P24 10 29 F8 COM5 RN A D13 P24 10 30 C8 COM5_TX_B B13 P24 IO 31 E8 COM5_TX_A A13 P24 IO 32 B8 COM5 CTS B F14 COM5 CTSA 14 COM5 RTSB CA COM5_RTS_A B14 COM6_RX_B E15 COM6_RX_A D15 COM6_TX_B B15 COM6_TX_A A15 COM6_CTS_B F16 COM6 CISA Cp COM6_RTS_B C16 COM6_RTS_A B16 62 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 15 5 AFIX Site An AFIX site is provided This is a proprietary interface allowing additional functionality to be added without taking up a PMC site GEIP s current range of AFIX cards includes support for dual MIL STD 1553 interfaces AFIX1553 SCSI an
26. CON Io 64 12 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Table 5 29 I2C Bus Addresses nano 68 Table 5 30 Power Manager Monitor eet sasen iE EERROR RECECE 69 Table Ze KEREN 69 Table 5 32 BMM Address e E 70 Table 5 33 2 MC G ographie AUS S SS on RR BURN MN RR ORAN 71 Table 5 34 reegelen le 74 Teible 5 35 PCl Interrupt ROtGHON E 77 Table S 36 IMAGA a t ll ener ea ne Ee La ore EL MO 78 Table 5 37 Ethernet Link EE 80 Table BIT EEDS a NoE 80 Table 5 59 Bi Status LED MESA 80 Tdble 5 40 Reset EE 81 Table 5 4 ene TEE 81 el gr O ME eru I EAE 81 Table 5 43 Backplane PCI Express Lane Status LEDS o t dus 82 Table 6 1 Control and Status Ree ee 85 Table 5 2 ege EE 86 Tuble 6 3 Addtess Regis ler de 86 Table 6 4 Board Frequency Ree 86 Table 6 5 Board Config ration Registe rca 87 Table G5 A ARAN EAA N E A R 88 Table 6 7 Control Register ee 89 TADE 5 8 Cont o Bei el cede a NH bebe nex A den hau 90 Table 6 9 EE e e 91 E O O 91 Table 6 11 Board Semaphore Register Osso 92 Table 6 12 Watchdog Control Registel 6 zo a 93 Table 6 13 Watchdog Interrupt Value Register 93 Table 6 14 Board Interrupt Status iaa 94 Table 6 15 Board Interrupt Core 0 INT Mask Register retient epatis sis 95 Table 6 16 PCI Express Block Configuration Register soie o da 96 Table 6 17 PCI Express Block Semaphore Register Offsets ooo 97 Table 6 18 PCI Express Doorbell ASSerbReglSter asso e ENORMES DREAM RUNG Nc EUR 97 Table 6 19 PCI Expr
27. Core 1 Extended boot area Extended boot area 2 MBytes 2 MBytes Core 0 Core 1 Main boot area Main boot area 2 MBytes 2 MBytes Core 0 Core 1 User Flash User Flash Alternate boot area Alternate boot area 256 MBytes 256 MBytes 2 MBytes 2 MBytes User Flash User Flash 248 MBytes 248 MBytes Bank 0 Bank 1 Bank 2 Bank 3 optional optional 5 4 1 Boot Flash The top 8 MBytes of Flash memory on each of the first two Flash banks is used as Boot Flash holding initialization and operating system boot routines Each of the 8 MByte regions are used to hold boot images for one of the processing cores and are divided into four independent 2 MByte boot images When a single core device is used or a separate boot image for Core 1 is not required the second 8 MByte region may be utilized as User Flash The Recovery Boot image contains a 256 KByte factory programmed boot image shared by both processing cores allowing the Flash to be reprogrammed if other boot images become corrupted The Recovery area is protected by hardware and is not writeable by the user The remainder of this 2 MByte area can be used to store BIT results The Boot Flash is accessed using Chip Select 0 on the Local Bus Controller of the MPC8641D and is configured as the default boot location for the PowerPC reset vector OxFFFO 0100 The boot areas are mapped into a 16 MByte window as shown below Figure 5 3 Local Bus CSO Mapping OXFFFFFFFF
28. Flash 20and21 Flash banks 10 4 banks Flash 11 8 banks Flash 00 Reserved da 01 512 Mbit Flash devices 22 and 23 Flash device size O 1 Gbit Flash devices 11 2 Gbit Flash devices 24 to 31 Reserved 0x00 Publication No SBC610 OHH 2 Control and Status Registers 87 6 5 Link Status Register Offset 0x0010 For bits 0 to 11 a set bit shows that the last reset was caused by the corresponding device source For bits 21 to 27 and 29 to 31 a set bit shows that a jumper is fitted on the corresponding link The NVMRO signal is on the PO connector pin A4 Table 6 6 Link Status Register Bits Description 0 Backplane SVSRESET reset 1 8641 Hard Reset Request reset Notes Watchdog 1 reset Watchdog 0 reset Backplane ENT RESET reset mie _ wt N e Front panel switch reset BMM reset BDM header reset PMC2 XMC2 reset O o J o PMC1 XMC1 reset Serial RapidlO Tsi578 Switch reset 0 1 PCI Express PEX8518 Non Transparent Port reset 2 Reserved 3 XMC2 Built In Self Test BIST 4 XMC1 BIST 5 EREADY 6 Boot Swap 1 7 Boot Swap 0 0b 0 XMC2 BIST complete 1 XMC2 BIST in progress 0 XMC2 BIST complete 1 XMC2 BIST in progress 0 PMCs AFIX ready for enumeration 1 PMCs AFIX not ready for enumeration 0 BOOT_SWAP1 signal not asserted 1 BOOT_SWAP1 signal asserted 0 BOOT_SWAPO signal not asserted 1 BOOT_SWAPO signal asserted 8 BIT Mode 1 0
29. GND JTAG TDO GND GND GA0 1 PCIE RKOP PCIE RXO MBIST PCIE RKIP PCIE RXIN VPWR 2 GND GND GA1 GND GND PRESENT 3 PCIELRX2P PCIE RX2 P3V3 AUX PCIE RX3SP PCIE RX3N VPWR 4 GND GND GA2 GND GND SM_DATA 5 PCIE RXAP PCIE RX4 Reserved PCIE_RXSP PCIE RAN VPWR 6 GND GND NVMRO GND GND SM_CLK 7 PCIE RK6P PCIE RX6 Reserved PCIE RX7P PCIE RX7N Reserved 8 GND GND Reserved GND GND Reserved 9 REFCLK P REFCLK N Reserved WAKE ROOT Reserved 118 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 5 2 J16 J26 J16 and J26 are rear I O connectivity for the XMC1 and XMC2 connectors Table 7 23 J16 J26 Pin Assignments Pin A 8 C D E F 1 XMCn O A01 XMCn JO B01 XMCn IO CO1 XMCn_IO_D01 XMCn JO E01 XMCn IO F01 2 GND GND XMCn IO C02 GND GND XMCn IO F02 3 XMCn O A035 XMCn IO B05 XMCn IO C03 XMCn IO D03 XMCn IO E03 XMCn IO F03 4 GND GND XMCn IO C04 GND GND XMCn IO F04 5 XMCn O A05 XMCn IO BUS XMCn IO C05 XMCn JO D05 XMCn IO E05 XMCn IO FOR 6 GND GND XMCn IO C06 GND GND XMCn IO F06 7 XMCn IO A07 XMCn IO B07 XMCn IO C07 XMCn IO D07 XMCn IO E07 XMCn IO FO7 8 GND GND XMCn_I0_C08 GND GND XMCn IO F08 9 XMCn IO A09 XMCn IO B09 XMCn IO C09 XMCn JO D09 XMCn JO E09 XMCn IO F09 0 GND GND XMCn IO C10 GND GND XMCn IO F10 1 XMCn O A11 XMCn IO B11 XMCn IO C11 XMCn_IO_D11 XMCn_IO E11 XMCn IO F11 2 GND GND XMCn_I0_C12 GND GND XMCn IO F12 3 XMCn_IO
30. ICS9FG108 PCI Express Clock Generator System Management Bus P1 Board Management x E m XMC XMC m E wm POWR1014A site 1 site 2 MMC GA PC DIP Power Switch Manager E PC Bus 2 connects to two read only EEPROMs which contain the configuration data for the two DDR2 memory interfaces It also connects to the Tsi578 Serial Rapid IO Switch and its EEPROM All other devices with an PC interface are connected to PC Bus 1 to allow monitoring either by the processor or by an external device via the Board Management Microcontroller Where PC addresses are quoted in the following sections the 8 bit address is the value that would be used to write to the device on the bus i e the 7 bit device address and the LSB set to 0 5 17 1 l C Reset An PC bus may potentially lock up if the reset is applied stopping the PC clock when a slave device without a reset pin is driving out data The Local Bus Control FPGA provides logic to recover both PC buses from this locked up state by clocking the bus during reset until the data line is released Publication No SBC610 OHH 2 Functional Description 67 5 17 2 Addressing Table 5 29 UC Bus Addresses Device 7 Bit Address Hex 8 Bit Address Hex EE Da en Bus 1 PSU Manager 40 80 Board Temp Sensor 48 90 Core Temp Sensor 4C 98 PCA9650 I2C DIP Switch 4E 9C MPC8641D Config EEPROM 50 A0 Real Time Clock 51 A2 PEX8548 PCle Switch
31. Link Setting Setting Meaning Out NVRAM writes disabled In NVRAM writes enabled Le NOTE The VPX backplane Non Volatile Memory Read Only NVMRO signal on connector PO pin A4 must also be set inactive low before the NVRAM can be altered 3 3 7 SMP Mode Link E19 When the two processing cores are running different operating systems or different instance of the same operating system the MPC8641D provides the ability to offset Core 1 accesses to the bottom of RAM by 256 MBytes addresses 0x0000 0000 to 0x1000 0000 are offset to 0x1000 0000 to 0x2000 0000 This allows both processing cores to maintain separate stacks and private memory without any software intervention This is the default mode selected with this link not fitted When the two processors are operating in SMP mode this feature is not desirable as both processors need to share the same memory space Fitting a jumper on this link in this mode disables this feature Table 3 7 E19 Link Setting Setting Function Out AMP Mode Core 1 has 256 MByte memory offset In SMP Mode no offset If a single core MPC8641 processor is fitted the setting of this link has no effect Publication No SBC610 OHH 2 Configuration 25 3 3 8 Factory Link E20 This link is for factory use only It should not be fitted by the user 3 3 9 Boot Hold off Link E21 Fitting a jumper on this link prevents Processing Core 0 from booting and configures the board to allow a PMC fit
32. Notes 0to7 Board ID SBC610 0x2D 8to15 NumberofSemaphores 0x4 16to23 Number of Doorbells 0x4 24to31 NumberofScratchpads 0x2 96 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 6 20 PCI Express Block Semaphore Registers Offset 0x5010 to 0x501C Each register controls one of four semaphores Table 6 17 PCI Express Block Semaphore Register Offsets Offset Semaphore 0x5010 1 0x5014 2 0x5018 3 Ox501C 4 A semaphore is taken by reading the corresponding register e If the value returned is zero then semaphore is currently in use e If the value returned is non zero then the semaphore take is successful The semaphore is released by writing to the corresponding register the value written is not significant The reset value for all semaphore registers is 0x0000 0001 6 21 PCI Express Scratchpad Registers Offsets 0x5020 and 0x5024 These two registers have no effect on the system and are provided for software to store status information or data Their value on reset is 0x0000 0000 6 22 PCI Express Doorbell Assert Register Offset 0x5030 Writing a T to a bit in this register asserts the corresponding doorbell interrupt This register is write only but the doorbell status can be read from the PCI Express Doorbell Status Register Table 6 18 PCI Express Doorbell Assert Register Bits Description Notes 0to27 Reserved 0x0000000 28 Assert Doorbell 3 Write 1 to a
33. PMC if it supports the current bus mode Used to detect the presence of a PMC on the site BUSMODE 4 2 Bus mode Driven by the host to indicate the bus mode On the SBC610 this is always PCI BUSMODE2 is pulled up BUSMODE3 and BUSMODE4 are pulled down to GND RESET IN Reset to the PMC Driven low to reset the PCI bus TRDY Target Ready Driven low by the current target to signal its ability to complete the current data phase PERR Parity Error Driven low by a PCI agent to signal a parity error SERR System Error Driven low by a PCI agent to signal a system error STOP Stop Driven low by a PCI target to signal a disconnect or target abort INT D A Interrupt lines Level sensitive active low interrupt requests rotated between PMC sites CLK Clock All PCI bus signals except RST are synchronous to this clock REQ B A Request Driven low by a PCI agent to request ownership of the PCI bus GNT B A Grant Driven low by the arbiter to grant PCI bus ownership to a PCI agent IDSEL B A Initialization Device Select Device chip select during configuration cycles REQ64 Request 64 Bit Driven low by PCI master to request 64 bit transfer ACK64 Acknowledge 64 Bit Driven low by PCI agent in response to REQ64 EREADY The PMC uses this signal to indicate when it is ready to be enumerated by the PCI software RESET OUT Reset output This signal can be driven by a Monarch PMC to reset the SBC610 MONARCH Monarch mode is not supported on the SBC
34. RTS A Output B10 COM3 DIR COMS RIS B Output C6 COM4 DTR COM4 RTSB Output C10 COM3_RXD COM3 RXA Input D5 COM4 RXD COMA RXA Input D9 COM3 Dep COM RXB Input ES COM4 Dep COMA RXB Input E9 COM3 CTS COM3 CTSA Input E6 COM4 CTS COMACTSA Input E10 COM3 DCH COM3CISB Input F6 COM4 DCH COMA CTS B Input F10 otUsed COM3 TTA Output A7 otUsed COM4TTA Output AU NotUsed COM3 1TB Output 87 otUsed COMATTB Output B11 Not Used COM3_RT_A Input D7 ot Used COM4_RT_A Input D11 NotUsed COM RTB Input E7 otUsed COM4 RTB Input E11 NotUsed COM3 STA Input E8 otUsed COM4 STA Input E12 ot Used COMS3 ST B Input F8 ot Used COMA ST B Input F12 Publication No SBC610 OHH 2 Functional Description 51 5 10 3 COM5 and COM6 COM5 and COM6 are provided by a second ESCC IP Core within the I O FPGA Each channel is able to support synchronous and asynchronous communication protocols though it is intended for use in asynchronous modes only There is no local DMA support within the FPGA for these interfaces so their throughput is dependent on the capability of the software driver and the processor loading The FPGA provides additional Baud Rate Generation capabilities over the original Zilog Z85230 device meaning that a greatly improved range and resolution of baud rates is available The serial ports are driven by ISL41334 bus transceivers and can be configured by software to operate in RS232 RS422 or RS485 modes
35. Table 5 26 PMC XMC Site 2 Signal Availability 1 P64s X12d Option P10s X20d38s Option PMC P5 PMC P5 XMC P6 PMC P5 XMC P6 XMC P6 XMC P6 0 Pi 1 0 Pin 1 0 Pin 1 0 Pin 1 0 Pin 0 Pin 1 0 Pin P24 IO 1 E P24 10 33 E9 P26_I0_A05 EL P24 IO 1 E1 P26 0 C01 Di P26_ 10 A01 E13 P2610 A05 E P24 IO 2 B P24 1034 B9 P26 0 B05 D1 P24 IO 2 B1 P26_I0 F01 A3 P26 0 801 D13 P2610 B05 D1 P24 IO 3 D P24 I0 35 D9 P260 D05 B1 P24 I0 3 D1 P26_10_C02 F4 P JODOI B13 P26_I0_D05 DI P24 IO 4 A P24 10 36 A9 P26 0 E05 Al P24_10_4 Al P26_I0 C03 Ei P26 10 E01 A13 P26l0E05 Al P24 IO 5 F2 P24 IO 37 F10 P26 IO A07 F2 P24 JO 5 F2 P26 0 F02 C4 P2610 A05 PIA P2610A07 Fe P24 IO 6 C2 P241038 C10 P26 I0 807 2 P24 IO 6 C2 P26_I0 F03 B4 P26 0 B03 EA P261 08B07 E2 P24 IO 7 E2 P24 IO 39 E10 P26_10_D07 C2 P24 IO 7 E2 P26_10 C04 5 P2610 D03 C14 P26_10_D07 C2 P24 IO 8 B2 P24 1040 B10 P26 IO E07 B2 P24 JO 8 B2 P2610 C05 D5 P26 0 E035 B14 P26_10_E07 B2 P24 10 9 E3 P24 IO 41 E11 P26 I0 A09 EN P24 10 9 E3 P26_I0 F04 B5 P26 0 A11 E15 P26 O0 A09 E P24 1010 Di P24 IO 42 B11 P2610 B09 D3 P26 IO F05 A5 P26 10 B11 D15 P2610 B09 D3 P24 1011 D3 P2410 43 D11 P26 IO D09 B3 P24 I0 11 D3 P2610 C06 F6 P26 10 D11 B15 P2610 DO9 B3 P24 1012 A3 P24 10 44 All P26 O E09 A3 P26_10_C07 E6 P26 O0 E11 A15 P26 O E09 A3 P24 1013 F4 P2410 45 F1
36. USB and SATA devices are connected to a PEX8114 PCIe to PCI bridge via a 32 bit PCI bus running at 33 MHz The device number mapping for the PCI bus is as follows Table 5 10 PCI Bus Device Number Mapping Device IDSEL Function 0 16 Not implemented 1 17 USB Controller 2 18 SATA Controller 3 19 AFIX Device 0 4 20 AFIX Device 1 5 21 AFIX Device 2 6 22 AFIX Device 3 7t015 23to31 Notimplemented 48 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 8 Input Output The SBC610 has a variety of possible I O connectivity including the following e Ethernet e Serial Ports e USB e Serial ATA e General Purpose I O 5 9 Ethernet The MPC8641D has four on chip enhanced Three Speed Ethernet Controllers eTSECs These incorporate a Media Access Controller MAC that supports 10 100 1000BaseT and half or full duplex operation The eTSECs support several TCP offload features including checksum generation and verification that reduce the amount of software interaction required Jumbo frames are also supported The SBC610 uses two of these controllers to provide external Ethernet interfaces eTSEC1 and eTSEC3 are used as these have independent connections to the platform bus The controllers are connected via a GMII interface to Marvell 88E1111 PHYs The PHYs are isolated from the backplane using transformer coupled magnetics The network MAC addresses of the Ethernet ports are factory config
37. VMELWORD VME D14 GND 8 DND VME D07 VME AM DND VME_DS1 DND VME_AM5 VME D GND 9 DND VME ANA VME AM3 DND VME_DSO DND VME A23 VME_A22 GND O GND VME_A07 VME IRQ7 DND VME_WRITE DND VME_A21 VME_A20 GND 1 GND VMEA06 VME IRQ6 DND VME_DTACK DND VME A19 VME A18 GND 2 GND VMEA05 VME IRQ5 DND VME_AS DND VME A17 VME A16 GND 3 GND VME A04 VME IRQ4 DND VME IACK DND VME_A15 VME A14 GND 4 GND VME A03 VME IRQ3 DND VME IACKIN DND VME_A13 VME A12 GND 15 GND VMEA0O2 VME IRQ2 DND VMEIACKOUT GND VME A11 VME A10 GND 6 GND VMEAO1 VME_IRQ1 DND VME_RETRY DND VME_A09 VME A08 GND Publication No SBC610 OHH 2 Connectors 105 7 1 7 P3 Table 7 8 P3 Pin Assignments Pin A B C D E F G 1 PMC1 IO 04 PMCI IO 02 GND PMC1 IO 03 PMC1 IO 01 GND VME A24 2 GND PMC1 IO 08 PMC1 IO 06 GND PMC1 IO 07 PMC1 IO 05 GND PMC1 IO 12 PMC1 IO 10 S 3 XMCLIO F01 XMC1 10 COl GND PMC1 IO 11 PMC1_10 09 GND VME A25 4 GND PMC1IO 16 PWC IO 14 GND PMC1 IO 15 PMCI IO 13 GND XMC1 IO F05 XMC1 IO F02 XMC1 IO C03 XMC1 IO C02 PMC1 IO 20 PMC1 IO 18 PMC1 IO 19 PMC1 IO 17 a XMC1_10 F05 XMC1_10_F04 oND XMC1_10_C05 XMC1_10_C04 Snp ZS 6 GND PMC1IO AN X PMCI IO 22 GND PMC1 IO 23 MCL IO 21 GND XMC1 IO F07 VMCL IO F06 XMC1 O C07 XMC1 IO C06 PMC1 IO 28 PMCI IO 26 PMC1 IO 27 X PMCI1 IO 25 j XMC1 IO F09 XMC1 IO F08 SNB XMC1 IO C09 XMC1 IO C08 OND
38. Write RO Read Only WO Write Only Publication No SBC610 OHH 2 The following sections provide the definitions for the function of each bit within a register All registers are configured such that bit 0 is the most significant bit and bit 31 is the least significant bit Control and Status Registers 85 6 1 Board ID Register Offset 0x0000 Table 6 2 Board ID Register Bits Description Notes 0to7 Board ID SBC610 0x2D 8t015 PCB revision 1 2 5 etc 16to23 Software board revision A B C etc 24to27 Reserved 0x0 28to31 Register FPGA revision 1 2 3 etc 6 2 Address Register Offset 0x0004 Table 6 3 Address Register Bits Description Notes Oto 21 Reserved 0x000000 0 SBC610 is not VME System Controller ge VME Systemi Controller 1 SBC610 is VME System Controller 23 VPX System Controller 0 SBC610 is not VPX System Controller 1 SBC610 is VPX System Controller 24and 25 Reserved 00b 0 Odd number of bits set 1 Even number of bits set 26 Geographic Address parity Contains the VME Geographic Address bua Geographic Address All bits are inverted to present the actual address a Inverted from backplane signal 6 3 Board Frequency Register Offset 0x0008 Table 6 4 Board Frequency Register Bits Description Notes 0 to 29 Reserved 0x00000000 00 66 666 MHz 01 100 MHz 30and31 SYSCLK frequency 1D Reserved 11 Reserved 86 SBC610 6U VPX Single Board Computer
39. XMC2 IO CO GND GND PMC2 IO 11 PMC2 IO 09 GND GND VME D25 PMC2 IO 16 PMC2 IO 14 PMC2 IO 15 PMC2 IO 13 s GND GND XMC2 IO F03 XMC2_10_FO2 GND BUE XMC2 O C03 XMC2 IO CO2 GND PMC2 IO 20 PMC2 IO 18 PMC2 IO 19 PMC2 IO 17 5 XMC2_10_FO5 XMC2_10_F04 GND GND XMC2_10_C05 XMC2_10_C04 GND GND VME_D26 COM3_TX_A COM3_TX_B COM3_RX_A COM3_RX_B PMC2 IO 24 PMC2 IO 22 PMC2 IO 23 PMC2 IO 21 6 GND GND XMC2 IO F07 XMC2 IO F06 GND GND XMC2_10_C07 XMC2_10_C06 GND COM3 RTS A COM3 RTS B COM3 CTS A COM3 CTS B PMC2 IO 28 PMC2 IO 26 PMC2 IO 27 PMC2 IO 25 7 XMC2 IO F09 XMC2 IO F08 GND GND XMC2_10_C09 XMC2 10 C08 GND GND VME D27 COM3 TT A COM3 TT B COM3 RT A COM3 RT B PMC2 IO 32 PMC2 IO 30 PMC2 IO 31 PMC2 IO 29 8 GND GND XMC21O F11 XMC2 IO F10 GND GND XMC2_10_C11 XMC2_10_C10 GND N C N C COM3 ST A COM3_STB PMC2_10_36 PMC2_10_34 PMC2 IO 35 PMC2 IO 33 9 XMC2_10_F13 XMC21O F12 GND GND XMC2 IO C13 XMC210 C12 GND GND VME D28 COMA TX A COM4 TX B COM4 RY A COM4 RX B PMC2 IO 40 PMC2 IO 291 PMC2 IO 39 PMC2 IO 37 0 GND GND XMC2_10_F15 XMC2 O F14 GND GND XMC2 IO C15 XMC2_10_C14 GND COM4 RTS A COM4 RTS B COM4 CTS A COM4 CTS B PMC2 IO 44 PMC2 IO 42 PMC2 IO 43 PMC2 IO 41 1 XMC21O F17 XMC2_10_F16 GND GND XMC2 IO C17 XMC210 C16 GND GND VME D29 COM4 TT A COM4 TT B COM4 RT A COM4 RT B PMC2 IO 48 PMC2 IO 46 PMC2 IO 47 PMC2 IO 45 2 GND GND XMC2 IO F19 X XMC2 IO F18 GND GND XMC2 IO C19 XMC2 10 C18 GND N C N C COMA ST A C
40. and may provide front panel connection to the module GEIP PMCs are delivered with a full kit of parts for mounting plus fitting instructions 5 25 2 LEDs Five LEDs are visible through the front panel One indicates that all off and on board power supplies are within specification and the other four are software programmable and are used to reflect the status of BIT or other software See the LEDs section for more details 5 25 3 Switches A momentary action toggle switch is fitted through the front panel The switch allows generation of a hard or soft reset With the board inserted vertically into a rack moving the switch to the S position causes a soft reset to the processing cores and moving the switch to the H position causes a hard reset to the board The switch may be disabled under software control via Control Register 1 The switch is enabled following power up Functional Description 83 5 26 Conduction cooled Front Panel Build Levels 4 and 5 Figure 5 13 Conduction cooled Front Panel 5 26 1 PMC Slots There is no access to front I O from PMCs in a conduction cooled environment If you are fitting a non GEIP PMC it must comply with the standard for rugged conduction cooled PMCs VITA20 2001 to ensure that it mates correctly with the SBC610 mechanics GEIP PMCs comply with this standard 5 26 2 LEDs Five LEDs are visible from the front One indicates that all off and on board power suppl
41. as a transmit clock output in RS422 mode selected by UO FPGA COMn RN A Serial port Receive Data input A COMn RX B Serial port Receive Data input B COMn RX B becomes DSR in RS232 mode COMn ST A Serial port Send Timing Transmit Clock In input A COMn ST B Serial port Send Timing Transmit Clock In input B COMn TT A Serial port Transmit Timing Clock Out input A COMn TT B Serial port Transmit Timing Clock Out input B COMn TX A Serial port Transmit Data output A COMn TX B Serial port Transmit Data output B COMn TXD B is unused in RS232 mode P41 xn Rear UO signals from AFIN P41 connector Signal names reflect the pin numbers of this connector NED Nuclear Event Detect input A 12V level applied to this pin will cause all on board supplies to reduce to less than 2096 of their initial value within 300 us EXT RESET External Hard Reset input Pulling this input low will cause a hard reset to the SBC610 Any switch logic should be debounced externally EXT ABORT External Soft Reset input Pulling this input low will cause a soft reset to both processing cores Any switch logic should be debounced externally BITFAIL BIT Fail output Reflects the status of the BIT Fail LED This output is open drain and so may be used to wire OR signals from several cards The output also has a series current limiting resistor and so may be used to drive an LED directly 114 SBC610 6U VPX
42. bridge generates the clock outputs to external PCI PCI X devices It samples the XCAP and M66EN signals to determine the correct operating frequency for the PCI bus and drives the PCI X initialization pattern during reset The current operating frequency of each bus may be ascertained by reading registers within the appropriate PEX8114 The bridge also contains the arbiter for the PCI bus This supports up to four external masters and the priority of each is programmable The bridges are initially configured by hardware strapping but each has a serial EEPROM that can also be used to configure registers within the device if required The EEPROMs are write protected by default and can be write enabled by clearing the Serial EEPROM Write Protect bit in Control Register 1 This bit may only be cleared when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low Each bridge can be prevented from accessing the EEPROM under software control if the data becomes corrupted and configures the device such that the EEPROM contents cannot be overwritten This may be done by setting the relevant Serial EEPROM Disable bit in Control Register 2 or by fitting the Recovery Boot Link E14 The PEX8114 can report any errors detected to the processor via PCIe using legacy interrupt messages or Message Signaled Interrupts 46 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 7 PCI Buses Th
43. cer E E O iu H D o Comm go Omm e Lj Dee gradi o caen B Bn H Ones e B tell D Ing mp cH EE EH jur seint WO ER es a Rnd ard and So H EE Publication No SBC610 0HH 2 Functional Description 79 5 24 1 Ethernet Link Status LEDs DS301 to DS312 Table 5 37 Ethernet Link Status LEDs LED Color Function eaning When Lit DS301 Yellow Ethernet Port 3 Transmit Ethernet traffic being transmitted DS302 Yellow Ethernet Port 3 Receive Ethernet traffic being received DS303 Yellow Ethernet Port 3 Duplex Ethernet port operating in Duplex mode DS304 Yellow Ethernet Port 3 1000BaseT Ethernet port operating in 1000BaseT mode DS305 Yellow EthernetPort3100BaseT Ethernet port operating in 100BaseT mode DS306 Yellow Ethernet Port 3 10BaseT Ethernet port operating in 10BaseT mode DS307 Yellow Ethernet Port 1 Transmit Ethernet traffic being transmitted DS308 Yellow Ethernet Port 1 Receive Ethernet traffic being received DS309 Yellow Ethernet Port 1 Duplex Ethernet port operating in Duplex mode DS310 Yellow Ethernet Port 1 1000BaseT Ethernet port operating in 1000BaseT mode DS311 Yellow Ethernet Port1100B
44. connected directly to the 3 3V supply Do not fit PMCs that use 5V signaling Publication No SBC610 OHH 2 Connectors 115 7 2 2 J13 J23 and J14 J24 Table 7 19 J13 J23 Pin Assignments Table 7 20 J14 J24 Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal 1 N C 2 GND 1 PMCn IO 01 2 PMCn IO 02 3 GND 4 C BE7 3 PMCn IO 03 4 PMCn IO 04 5 C BE6 6 C BE5 5 PMCn IO 05 6 PMCn IO 06 7 C BE4 8 GND PMCn IO 07 8 PMCn IO 08 9 VIO 10 PAR64 9 PMCn IO 09 10 PMCn IO 10 11 AD63 12 AD62 11 PMCn IO 11 12 PMCn IO 12 13 AD61 14 GND 13 PMCn IO 13 14 PMCn IO 14 15 GND 16 AD60 15 PMCn IO 15 16 PMCn IO 16 17 AD59 18 AD58 17 PMCn IO 17 18 PMCn IO 18 19 AD57 20 GND 19 PMCn IO 19 20 PMCn IO 20 21 VIO 22 AD56 21 PMCn IO 21 22 PMCn IO 22 23 AD55 24 AD54 23 PMCn IO 23 24 PMCn IO 24 25 AD53 26 GND 25 PMCn IO 25 26 PMCn IO 26 27 GND 28 AD52 a PMCn IO 27 28 PMCn IO 28 29 AD51 30 AD50 29 PMCn IO 29 30 PMCn IO 30 31 AD49 32 GND SL PMCn IO 31 32 PMCn IO 32 33 GND 34 AD48 33 PMCn IO 33 34 PMCn IO 34 5 AD47 36 AD46 35 PMCn IO 35 36 PMCn IO 36 37 AD45 38 GND 37 PMCn IO 37 38 PMCn IO 38 39 VIO 40 AD44 39 PMCn IO 39 40 PMCn IO 40 41 AD43 42 AD42 41 PMCn IO 41 42 PMCn IO 42 43 AD41 44 GND 43 PMCn IO 43 44 PMCn IO 44 45 GND 46 AD40 45 PMCn IO 45 46 PMCn IO 46 47 AD39 48 AD38 47 PMCn IO 47 48 PMCn IO 48 49 AD37 50 GND 49 PMCn IO 49 50 PMCn IO 50 51 GND 52 AD36 51 PMCn IO 51
45. e Any of the power supplies fall outside specification e The VME SYSRESET signal is asserted e The processor HRESET_REQ output is asserted e Hard reset is selected via the front panel Reset switch when enabled in software e The HRESET signal on the BDM Header is asserted e The reset output of the BMM is asserted e The EXT RESET backplane pin is asserted e The RESET OUT signal from any PMC XMC site is asserted e Either of the two watchdog timers expire e Reset generated by Tsi578 from Serial RapidIO source e Reset generated by PEX8518 from PCI Express Non Transparent backplane port The duration of the internal hard reset signal is at least 10 ms A hard reset may also be initiated by software setting the LRESET LRST or LRSTS bits within the Tsi148 VME Bridge and may be used by other boards with a VME interface to reset the SBC610 The cause of a hard reset event may be determined from the Link Status Register The processing cores may be individually reset by software using the Processor Core Reset Register within the MPC8641D interrupt controller 74 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 21 2 SYSRESET Signal The SYSRESET signal is asserted by hardware under the following conditions e Any of the power supplies fall outside specification e A hard reset event occurs and the board is the VPX System Controller A SYSRESET may also be initiated by software setting the SRESET bit within the Tsi1
46. nei EEEE 86 Board Interrupt Core 0 INT Mask cee 95 Board Interrupt Core 0 MCP Mask 96 Board Interrupt Core 1 INT Mask eee 95 Board Interrupt Core 1 MCP Mask 96 Board Interrupt Status sse 94 Board Semaphore sse 92 Control iii cias 89 Control Zion 90 FIFO Dita doce 100 FIFO Status anni adriana 100 Flash Control eie ondaa 91 VO FP GA namas monada eed 101 Ink Status iac ote meret aE 88 PCI Express Block Configuration 96 PCI Express Block Semaphore 97 PCI Express Doorbell Assert ue 97 PCI Express Doorbell Clear 98 PCI Express Doorbell Status sssssss1sss1ssessee 98 PCI Express Scratchpad ee 97 Scratchpad sssrini 92 Test Pattern nenas anal 91 Watchdog Control 93 Watchdog Interrupt Value sss 93 Related Documents 4 Reliability i terme minitas 129 Resets ee e E a doiten ins ased 88 Sequence and Timing sss 33 DOLE RR 75 Status LEDs ien eiim anc stes 81 Revisi n State uie oie cst rere Se 19 RIC ada 68 ug 32 Index 137 Safety INOtiCes cierre eterna 17 SATA atte oim RUOTE RR ES 54 Activity LEDS REENEN 81 Serial Ports COMI and COM 50 COMS and COML cese ases eise erit rera 51 COMB and COMO voeren iaie 52 elc E Em 127 HZ s 126 Software Support erri 131 SpecificatiOdS T M 126 E
47. normal operation these links are not fitted and the SBC610 boots from the Main boot image The active boot image may also be affected in a deployed system using the BOOT SWAPI backplane input see the Boot Flash section 3 3 3 Recovery Boot Link E14 In addition to selecting the Recovery boot image link E14 also prevents the loading of EEPROM configuration data by any of the devices on the board This is useful in the event that EEPROM data becomes corrupted and needs to be reprogrammed Table 3 3 E14 Link Setting Setting Meaning Out Normal operation In EEPROM load is disabled Publication No SBC610 OHH 2 Configuration 23 3 3 4 Boot Flash Write Enable Link E15 and User Flash Write Enable Link E16 These links tell the software how it should configure the default non persistent sector protection of the Boot and User areas of Flash They are provided for compatibility with previous GEIP hardware where links enabled write accesses to the 8 MByte Boot Area of Flash and the remaining User Flash These links now have no effect on the hardware interface to the Flash devices as all sector protection is controlled by software See the Flash Sector Protection section for further details n NOTES User software may subsequently alter sector protection at any time following the boot sequence Regardless of any link settings for the Flash write protection the Recovery boot area cannot be write enabled Table 3 4 E15 and
48. show how many byte locations are being accessed 1 2 3 or 4 Also VME DS 1 0 during a write cycle the falling edge of the first data strobe shows that valid data is available on the bus On a read cycle the rising edge of the first data strobe shows data has been accepted from the data bus Data Transfer Acknowledge A slave generates this signal The falling edge shows that valid data is available on the data bus VME DTACK during a read cycle or that data has been accepted from the data bus during a write cycle The rising edge shows that the slave has released the data bus at the end of a read cycle nterrupt Acknowledge The interrupt handler uses this to acknowledge an interrupt request It is routed to the IACKIN pin of slot VME_IACK ek j een 1 where it is monitored by the IACK daisy chain driver nterrupt Acknowledge In IACKIN IACKOUT form the interrupt acknowledge daisy chain This tells the board receiving it that VME_IACKIN hat board can respond to the interrupt acknowledge cycle in process or pass it down the daisy chain Interrupt Acknowledge Out A board sends this to tell the next board in the daisy chain that it can respond to the Interrupt VME IACKOUT Acknowledge cycle in progress VME IRQ 7 1 Interrupt Request 1 to 7 Interrupters drive these low to request an interrupt on the corresponding level Longword This is used with DSO DS1 and A01 to select which byte location s within the 4 byte group are accessed d
49. sticky and is only reset at power up It can be used by BIT to indicate its status at last reset c This bit is only writeable when the SBC610 is VPX System Controller d When the COM transceiver is disabled COM2 is used to communicate with the BMM Publication No SBC610 0HH 2 Control and Status Registers 89 6 7 Control Register 2 Offset 0x0018 Table 6 8 Control Register 2 Bits Description Notes Oandi 1 0 FPGA revision select Default 0x0 TEE 0 1 0 FPGA released to configure default 2 Initiate UO FPGA configuration initialization 1 Restart I O FPGA configuration 0 1 0 FPGA configuration in progress 3 1 0 FPGA configuration done read only 1 1 0 FPGA configuration complete 4to8 Reserved 0x00 a 0 Tsi578 allowed to configure from I C EEPROM 2 2 Aa O Tsi578 prevented from configuring from GC EEPROM E 0 PEX8518 allowed to configure from Serial EEPROM 2 EE PEX8518 prevented from configuring from Serial EEPROM f 0 PEX8518 allowed to configure from Serial EEPROM i PEXB548 Serial PERROM disables PEX8518 prevented from configuring from Serial EEPROM 0 AFIX Bridge allowed to configure from Serial EEPROM AFR EERCHEEEE 1 AFIX Bridge prevented from configuring from Serial EEPROM f 0 VME Bridge allowed to configure from Serial EEPROM Dee 1 VME Bridge prevented from configuring from Serial EEPROM e 0 PMC Bridge allowed to configure from Serial EEPROM a NEAR
50. when the NVRAM Write Enable Link E18 is not fitted or if the NVMRO backplane signal on connector PO pin A4 is active high The status of this link and backplane signal may be read back in the Link Status Register 5 6 PCI Express Infrastructure All on board PCI devices and mezzanine sites are connected to the MPC8641D using PCI Express The PCIe and PCI structure of the SBC610 is shown in Figure 5 1 PCIe is a high speed serial point to point interconnect running at 2 5 Gbits second in each direction PCIe links are scalable meaning that multiple lanes can be used between devices to increase the aggregate bandwidth The following table shows a comparison of the bandwidth of PCI Express links with PCI implementations Table 5 6 PCI Bus BusType Bus Width Frequency Bandwidth Notes PCI 32 bit 33 MHz 133 MBytes s PCI 32 bit 66 MHz 266 MBytes s PCI 64 bit 66 MHz 533 MBytes s PCI X 64 bit 133 MHz 1066 MBytes s PCle x1 2 5 Gbps 250MBytes s X Per direction PCIe X4 2 5 Gbps 1000 MBytes s Per direction PCle x8 2 5 Gbps 2000 MBytes s Per direction PCle Bandwidths shown include 8b 10b encoding overheads PCle is a packet based protocol but uses the same address spaces as standard PCI meaning that the software interfaces are backwards compatible PCle to PCI Bridges convert to PCI X or standard PCI where connection to these devices is required The maximum packet payload size for the PCIe sub system is 256 bytes
51. 0 SBG610 EE T H 76 xs Sc OM Pio f 79 tel E pieds rU m 83 Figure 5 13 Conductionscooled Front POIL assises tirer testis deterius prt revisit eben vta iridis 84 Fig re hee 102 Publication No SBC610 0HH 2 List of Figures 15 Le Introduction The GE Intelligent Platforms SBC610 is a member of the VPXtreme6 family of 6U VPX PowerPC based Single Board Computers It uses the Freescale MPC8641D dual core integrated host processor which contains two e600 PowerPC processing cores running at 1 33 GHz with dual memory controllers serial fabric and I O interfaces The SBC610 offers up to 4 GBytes of DDR2 SDRAM with ECC up to 1 GByte of Flash memory two Gigabit Ethernet channels serial USB 2 0 and SATA interfaces Up to four x4 Serial RapidIO ports and up to eight lanes of PCI Express are available on the backplane A VME interface with 2eSST support is also provided for connection to legacy hardware The MPC8641D processor is connected to all on board PCI devices and mezzanine sites using PCI Express through a non blocking switch architecture Two 64 bit PMC sites are provided each supporting PCI X operation at up to 133 MHz allowing for off the shelf or custom mezzanines to be fitted to add further functionality to the SBC610 Both sites also support XMC mezzanine cards supporting a x8 PCI Express link to each site for higher bandwidth connectivity to the host and h
52. 0UT GND VME BERR VME D13 i VME D06 VME AMI DND VME_SYSCLK DND VME LWORD VME D14 8 VME D07 VME AM2 DND VME_DS1 DND VME_AM5 VME D15 9 VME_AM4 VME AM3 DND VME_DSO DND VME A23 VME A22 0 VMEAO7 VME IRQ7 DND VME_WRITE DND VME A21 VME A20 1 VMEA06 VME_IRQ6 DND VME_DTACK DND VME A19 VME A18 2 VME_A05 VME IRQ5 DND VME_AS DND VME A17 VME A16 3 VME_A04 VME IRQ4 DND VME_IACK DND VME A15 VME A14 4 VME_A03 VME IRQ3 DND VME_IACKIN DND VME_A13 VME A12 5 VME_A02 VME_IRQ2 DND VMEIACKOUT GND VMEA11 VME A10 6 VME_A01 VME_IRQ1 DND VME RETRY DND VME A09 VME A08 7 1 6 J2 Backplane Connector ZN CAUTION The SBC610 has been specifically designed for use with 6U VPX backplanes designed to accommodate a single ended pin out on the J2 connector and is not compatible with 6U backplanes where the J2 connector is intended for differential signaling Plugging the SBC610 into such a 6U backplane may cause permanent component damage Table 7 7 J2 Pin Assignments Fin A B C D E F G H 2 DND VME D01 VME BRO GND VME_BCLR GND VME_BG2IN VME D09 GND 3 GND VME D02 VME_BR1 DND VME_BGOIN GND VME BG20UT VME D10 GND 4 GND VME D03 VME BR2 GND VME BGOOUT GND VME BG3IN VME D11 GND 5 DND VME D04 VME BR3 DND VME BGIIN DND VME BG3OUT VME_D12 GND 6 DND VME DOS VME AMO DND VME_BG1OUT GND VME BERR VME D13 GND 7 GND VME Dip VME AM1 DND VME SYSCLK DND
53. 0x603C Each register controls one of eight semaphores Table 6 22 AXIS Semaphore Register Offsets Offset Semaphore Offset Semaphore 0x6020 1 0x6030 5 0x6024 2 0x6034 6 0x6028 3 0x6038 7 Ox602C 4 8 0x603C A semaphore is taken by reading the corresponding register e If the value returned is zero then semaphore is currently in use e If the value returned is non zero then the semaphore take is successful The semaphore is released by writing to the corresponding register the value written is not significant The reset value for all semaphore registers is 0x0001 Publication No SBC610 OHH 2 Control and Status Registers 99 6 28 FIFO Data Registers Offsets 0x6040 to 0x604C These registers form the data path to each FIFO A write access adds the 32 bit message onto the back of the queue and a read access removes the first message from the queue Table 6 23 FIFO Data Register Offset FIFO 0x6040 A 0x6044 B 0x6048 C 0x604C D The default value of these registers is 0x0000 0000 6 29 FIFO Status Registers Offsets 0x6050 to 0x605C These registers contain status information on each FIFO A bit is set if the FIFO is full or empty or has only one message or message space remaining Table 6 24 FIFO Status Register Offsets Offset FIFO 0x6050 A 0x6054 B 0x6058 C Ox605C D Table 6 25 FIFO Status Register Bits Description Notes Oto26 Reserved 0x0000000
54. 14 0x0074 R W jou IP 0x6004 RO Control 2 0x0018 R W Board Semaphore 15 0x0078 R W AXIS Timer Control 0x6008 R W Flash Control 0x001C R W Board Semaphore 16 0x007C R W AXIS Semaphore 1 0x6020 R W Test Pattern 1 0x0020 RO Watchdog 0 Control 0x2000 R W AXIS Semaphore 2 0x6024 R W Test Pattern 2 0x0024 RO Watchdog 0 Interrupt Value 0x2004 R W AXIS Semaphore 3 0x6028 R W Test Pattern 3 0x0028 RO Watchdog 1 Control 0x2010 R W AXIS Semaphore 4 Ox602C R W Scratch 1 0x0030 R W Watchdog 1 Interrupt Value 0x2014 R W AXIS Semaphore 5 0x6030 R W Scratch 2 0x0034 R W Board Interrupt Status 0x4000 RO AXIS Semaphore 6 0x6034 R W Scratch 3 0x0038 R W Board Interrupt Core O INT Mask 0x4010 R W AXIS Semaphore 7 0x6038 R W Scratch 4 0x008C R W Board Interrupt Core 1INT Mask 0x4014 R W AXIS Semaphore 8 0x603C R W BoardSemaphore1 0x0040 R W Ces WESTER 0x4018 R W FIFO Data A Ox6040 R W Board Semaphore Ox0044 R W SC eege OX401C R W FIFO Dota B 0x6044 R W Board Semaphore3 0x0048 R W PCle Block Configuration 0x5000 RO FIFO Data C 0x6048 R W Board Semaphore4 Ox004C R W PCle Semaphore 1 0x5010 R W FIFO Data D 0x604C R W Board Semaphore5 0x0050 R W PCle Semaphore 2 0x5014 R W FIFO Status A 0x6050 R W Board Semaphore6 0x0054 R W PCle Semaphore 3 0x5018 R W FIFO Status B 0x6054 R W Board Semaphore7 0x0058 R W PCle Semaphore 4 Ox501C R W FIFO Status C 0x6058 R W Board Semaphore8 0x005C R W PCle Scratch 1 0x5020 R W FIFO Status D 0x605C R W Where R W Read
55. 1_3N GND 108 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 1 11 P5 Table 7 12 P5 Pin Assignments Pin A B D E F G 1 PMC2 IO 04 PMC2 IO 02 GND PMC2 IO 03 PMC2 IO 01 GND VME D24 2 GND PMC2 IO 08 PMC2 IO 06 GND PMC2 IO 07 PMC2 IO 05 GND PMC2 IO 12 PMC2 IO 10 5 XMC210 F01 XMC2 10 COl GND PMC2 IO 11 PMC2 IO 09 GND VME D25 4 GND PMC2 IO 16 PMC2 IO 14 GND PMC2 IO 15 PMC2 IO 13 GND XMC2 IO F03 XMC2 IO FO2 XMC2 O0 C03 XMC2 IO C02 PMC2 IO 20 PMC2 IO 18 PMC2 IO 19 PMC2 IO 17 5 XMC2 IO F05 XMC2 IO F04 GND XMC2 IO C05 XMC2 IO CO4 GND VME D26 COM3 TX A COMS3 TX B COM3 RX A COM3 RN B PMC2 IO 24 PMC2 IO 22 PMC2 IO 23 PMC2 IO 21 6 GND XMC2 IO F07 XMC2 IO F06 GND XMC2 IO CO7 XMC2 IO C06 GND COM3 RTS A COMS3 RTS B COM3 CTS A COMS3 CTS B PMC2 IO 28 PMC2 IO 26 PMC2 IO 27 PMC2 IO 25 7 XMC2 IO F09 XMC2 IO F08 GND XMC2_10_C09 XMC2 IO CO8 GND VME D27 COMS3 TT A COMS TT B COM3 RT A COM3 RT B PMC2 IO 32 PMC2 IO 30 PMC2 IO 31 PMC2 IO 29 8 GND XMC2_10_F11 XMC2 IO F10 GND XMC2 O0 C11 XMC2 IO C10 GND IC N C COM3 ST A COM3_STB PMC2_10_36 PMC2 IO 34 PMC2 IO 35 PMC2 IO 33 9 XMC2_IO_F13 XMC2_IO F12 GND XMC2_10_C13 XMC2_IO_C12 GND VME D28 COMA TX A COMA TX B COMA4 RX A COMA4 HN B PMC2 IO 40 PMC2_10_38 PMC2_10_
56. 2 A3 P14 10 44 A11 P1610 E09 A3 P1610 C07 E6 P16 O E11 A15 P16 O E09 A3 P14 IO 13 F4 P14 O0 45 F12 P1610 A15 F4 P16 IO F06 C6 P16 0 A13 F16 P1610 A15 F4 P14 IO 14 C4 P14 O0 46 C12 P16 O B15 E4 P1610 C07 B6 P16 O0 B13 E16 P16 O0 B15 4 P14 IO 15 Ei P14 0 47 12 P16 I0 D15 C4 P16_10 C08 Ei P16 0 D13 Op P1610 D15 C4 P14 IO 16 B4 P14 1048 B12 P1610 E15 B4 P1610 C09 Di P16 O E13 B16 P16 O E15 B4 P14 IO 17 EN P14 10 49 E13 P1610 A17 EN P16_10_F08 87 P16_10_A17 EN P14 IO 18 B5 P14 1050 B13 P16 10 B17 D5 P1610 F09 A7 Pie Oi D5 P14 IO 19 D5 P14 10 51 D13 P1610 D17 B5 P16_10 C10 F8 Pa Monir a5 P14 IO 20 AS P14 10 52 A13 P1610 E17 AS P16_10 C11 E8 DISSE A P14 IO 21 F6 P14 0 53 F14 P16 10 A19 F6 P16 O0 F10 C8 P160 A19 F6 P14 10 22 C6 p14 10 54 C14 P1610 B19 Ep P16 O F11 B8 P16 0 B19 Ep P14 IO 23 Ep P14 0 55 E14 P16 10 D19 Cp P1610 C12 E9 P16 0 D19 C6 P14 IO 24 B6 P14 10 56 B14 P16 10 E19 B6 P1610 C13 D9 P16_10_E19 D P14 1025 Ei P14 0 57 EIS P16_10_F12 89 P14 IO 26 B7 P14 1058 B15 P16_10_F13 A9 P14 IO 27 Di P14 l0 59 D15 P1610 C14 F10 P14 IO 28 A7 P14 10 60 A15 P1610 C15 E10 P14 10 29 F8 P14 1061 F16 P1610 F14 C10 P14 IO 30 C8 P14 10 62 C16 P1610 F15 B10 Differential pairs P14 IO 31 ER P14 10 63 E16 P16_10 C16 11 P14 IO 32 B8 P14 l0 64 B16 P1610 C17 D11 P16_10_F16 B11 P1610 F17 All P1610 C18 F12 P1610 C19 E12 P16_10_F18 C12 P16_10_F19 B12 60 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2
57. 2 GBytes 2 128Mx8 266 MHz Configuration information for the RAM attached to each controller is contained within PC EEPROM devices connected to DC Bus 2 The SBC610 supports up to 1 GByte of Flash memory with 512 MBytes fitted as standard The Flash devices are configured as 2 or 4 banks of two 16 bit wide devices accessed as a 32 bit wide device The Flash supports page mode accesses to allow for maximum bus bandwidth and must be written to as 32 bits The Flash is arranged in 256 KByte sectors has an erase capacity of 100 000 cycles per sector and typical data retention of 20 years ZN CAUTION Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle The following table shows the Flash options available for the SBC610 Table 5 4 Flash Options Flash Size Banks Flash Bank Organization 512 MBytes 2 2 x 1024Mbit 1024MBytes 4 2 x 1024Mbit The Flash details can be determined from the Board Configuration Register The Flash is divided into two area types Boot Flash and User Flash The top 8 MBytes of the first two Flash banks are useable as Boot Flash for each of the two processing cores These each hold four 2 MByte boot images that may be selected using hardware links The remainder of the Flash memory is allocated as User Flash Publication No SBC610 OHH 2 Functional Description 39 Figure 5 2 Flash Memory Structure Recovery Area 256 KBytes Spare BIT area Spare BIT area Core 0
58. 2 P26 I0 A15 F4 P26_10_FO6 C6 P2610 A13 F16 P2610 A15 F4 P24 1014 C4 P24 IlO 46 C12 P26 IO B15 E4 P2610 CO7 B6 P26 10 B13 E16 P2610 B15 E4 P24 1015 Ei P2410 47 X E12 P26 I0 D15 C4 P2610 C08 7 P26 10_D13 Op P26_10 D15 C4 P24 1016 B4 P24 IO 48 B12 P26 IO E15 B4 P2610 C09 Di P26_IO_ E13 B16 P26_10 E15 B4 P24 I0 17 EN P24 IO 49 E13 P26 I0 A17 EN P26_I0 F08 Bi P26_I0 A17 EN P24 IO 18 B5 P24 IO 50 B13 P26 IO B17 D5 P2610 F09 A7 P26_10_B17 D5 P24 1019 D5 P241051 D13 P26 IO D17 B5 P26_I0 C10 F8 P260 D17 B5 P24 1020 AS P24 0 52 A13 P26 O0 E17 AS P26_10 C11 E8 P26SIORET EAS P24 10 21 F6 P24 10 53 F14 P26_ 10 A19 F6 P26 0 F10 C8 P260 A19 F6 P24 I0 22 C6 P24 10 54 C14 P26 IO B19 6 P26_10_F11 B8 P26 0 B19 Ep P24 1023 Ep P24 0 55 E14 P2610 D19 Cp P26_10 C12 E9 P26_10_D19 C6 P24 10 24 B6 P2410 56 B14 P26 10 E19 B6 P26_10_C13 D9 P26 0 E19 B6 P24 10 25 Ei P24 I0 57 E15 P26_10_F12 89 P24 IO 26 B7 P2410 58 B15 P26_10_F13 A9 P24 1027 Di P2410 59 D15 P2610 C14 F10 P24 IO 28 A7 P24 I0 60 AIS P26_I0_ C15 E10 P24 10 29 F8 P24 10 61 F16 P2610 F14 C10 P24 1030 C8 P24 1062 C16 P26_10_F15 B10 P24 1031 8 P24 I0 63 E16 P26_I0 C16 11 P24 IO 32 B8 P24 IO 64 B16 P2610 C17 D11 P2610 F16 B11 P2610 F17 All P2610 C18 F12 P26_I0_ C19 12 P26_I0 F18 C12 P26_10_F19 B12 Publication No SBC610 0HH 2 Functional Description 61
59. 3 3V supply Do not fit PMCs that use 5V signaling PMCs supplied by GEIP are delivered with a full kit of parts for mounting them A PMC ordered with an SBC610 can be supplied factory fitted if required ON LINK PMC Installation Note publication number HN4 3 99 LN CAUTION Observe handling and anti static precautions when fitting the PMC It will usually be necessary to install driver software or implement other firmware configuration to achieve full functionality of a PMC see the specific PMC manual for the exact procedure A TIP Where a PMC is not pre installed prove operation of the SBC610 before installing the PMC 3 4 2 XMC Installation XMCs supplied by GEIP are delivered with a full kit of parts for mounting them Fitting is similar to a PMC An XMC ordered with an SBC610 can be supplied factory fitted if required LN CAUTION Observe handling and anti static precautions when fitting the XMC It will usually be necessary to install driver software or implement other firmware configuration to achieve full functionality of an XMC see the specific XMC manual for the exact procedure i TIP Where an XMC is not pre installed prove operation of the SBC610 before installing the XMC 28 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Figure 3 2 Mezzanine Positions oo
60. 3 GND GND GND LOCAL_AD2 RQD PCI_IRDY JC GPIO 1 C PCI AD 12 24 P41_A24 P41 B24 P41 C24 LOCAL AD3 GND PCI STOP GND GPIO 1 GND PCI AD 13 25 P41 A25 P41 B25 P41 C25 GND GNTO GND PCI PERR GND IC GND 26 GND GND GND LOCAL_AD4 GNT1 REQO PCI_SERR GPIO 1 C PCI ADI14 27 P41_A27 P41 B27 P41 C27 LOCAL AD5 P3V3 REQ1 P3V3 GPIO 1 P2V5 PCI AD 15 28 P41 A28 GND P41 C28 P2V5 GNT2 P3V3 PCI DEVSEL P2V5 JC P2V5 29 GND P41 B29 GND LOCAL_AD6 GNT3 REQ2 PCI LOCK GPIO 1 GPIO 18 PCI_AD 16 30 P41_A30 GND P41_C30 LOCAL_AD7 GND REQ3 GND GPIO 1 GND PCI_AD 17 Publication No SBC610 OHH 2 Connectors 121 7 4 1 Signal Descriptions Table 7 26 AFIX Signal Descriptions Signal Description P41_ 1 0 routed from the AFIX module connector to the P6 connector For signal descriptions see the AFIX manual PCI_AD 31 0 AFIX PCI Address Data bus PCI AFIX PCI Bus Control signals see the PMC signal descriptions for more details CLK 3 0 PCI Clock inputs REQ 3 0 PCI Requests from AFIX GNT 3 0 PCI Grants to AFIX IDSEL 3 0 IDSELs to AFIX PCI devices RESET PCI Reset to AFIX EREADY The AFIX uses this signal to indicate when it is ready to be enumerated by the PCI software AFIX FITTED Grounded by the AFIX to indicate to the SBC610 that it is fitted POWER GOOD SBC610 Power Good Signal for any reset logic on AFIX LOCAL ALEN AFIX Local Bus Address Latch Enable LOCAL RD AFIX Local Bus Read St
61. 39 PMC2_10_37 0 GND XMC2_10_F15 XMC2 O F14 GND XMC2_10_C15 XMC2 IO CA GND COM4_RTS_A COM4_RTS_B COMA CTS A COMA CTS B PMC2 IO 44 PMC2 IO 42 PMC2 IO 43 PMC2 IO 41 1 XMC21O F17 XMC21O F16 GND XMC2_10_C17 XMC2 l0 C16 GND VME D29 COMA TT A COMA TT B COMA RT A COMA RT B PMC2 IO 48 PMC2 IO 46 PMC2 IO 47 PMC2 IO 45 2 GND XMC2 O F19 XMC2 O F18 GND XMC2 10 C19 XMC2 IO C18 GND IC N C COMA ST A COMA STB PMC2 IO 52 PMC2 IO 50 PMC2 IO 51 PMC2 IO 49 3 XMC2_10_E01 XMC2_10_D01 GND XMC2_10_B01 XMC2 IO AO01 GND VME D30 COM5 TX A ONS TX B ONS RX A ONS HN B PMC2 IO 56 PMC2 IO 54 PMC2 IO 55 PMC2 IO 53 4 GND XMC2 O E03 XMC2 IO D03 GND XMC2_10_B03 XMC2 IO A03 GND COM5_RTS_A COM5_RTS_B COM5_CTS_A COMS5 CTS B PMC2 IO 60 PMC2 IO 58 PMC2 IO 59 PMC2 IO 57 5 XMC21O E11 XMC2 IO D11 GND XMC2_10_B11 XMC2 IO A11 GND VME D31 COM6 TX A COM6 TX B COM6 RX A COMO HN B PMC2 IO 64 PMC2 IO 62 PMC2 IO 63 PMC2 IO 61 6 GND XMC2 O E13 XMC2 IO D13 GND XMC2 IO B13 XMC2 lO A13 GND COM6 RTS A COM6 RTS B COM6 CTS A COM6 CTS B Publication No SBC610 OHH 2 Connectors 109 7 1 12 Backplane J5 Table 7 13 J5 Pin Assignments Fin A 8 E F 1 PMC2 IO 04 PMC2 IO 02 GND GND PMC2 IO 03 PMC2 IO 01 GND GND VME D24 2 GND GND PMC2 IO 08 PMC2 IO 06 GND GND PMC2 IO 07 PMC2 IO 05 GND PMC2 IO 12 PMC2 IO 10 3 XMC2 10 F01
62. 48 VME Bridge even if the board is not System Controller The duration of the SYSRESET backplane signal is at least 200ms and will be stretched to 200ms if a SYSRESET assertion of 200ms is observed in accordance with VITA46 1 5 21 3 Machine Check Exception When the MCP input to the processing core is asserted it may be configured to take a machine check exception or enter the checkstop state The MCP input to each of the two processing cores can be driven either by interrupts within the interrupt controller within the Register FPGA being enabled by software to drive the MCP0 or MCP1 inputs to the MCP8641D or by software enabling interrupt sources from within the MPC8641D interrupt controller to drive the MCP input to one of the two processing cores Figure 5 9 SBC610 Machine Check Exceptions Register FPGA Interrupt E Interrupt Glot Controller Controller 5 21 4 Soft Reset A soft reset causes the processing core to reach a recoverable state and then branch to either 0x0000 0100 or OxFFFO 0100 depending on the state of the IP bit in the core s Machine State Register No other on board resources are reset A soft reset is initiated on both processing cores when one of the following hardware events occurs e Soft reset is selected via the front panel Reset switch when enabled in software e The SRESET signal on the BDM header is asserted e The EXT ABORT backplane signal is asserted The processing cores may be i
63. 5 24 6 SATA Activity LEDs DS329 and DS330 s 5 24 7 Backplane PCI Express Lane Status LEDs DS331 to DS339 5 25 Air cooled Front Panels Build Levels 1 to 3 tette tenete tttttnntiis 5 26 Conduction cooled Front Panel Build Levels 4 and El 6 9 Control and Status Registers bes een tiende ia 6 1 Board ID Register Offset EE 6 2 Address Register Offset ODDO oeste RI en apa eee Pe he Rd 6 3 Board Frequency Register Offset EE EET RU URN 6 4 Board Configuration Register Offset OX000Cl cocos 6 5 Link Stat s Register Offset ECKE 6 6 Control Register 1 Offset DO TA aeos A NE E 6 7 Control Register 2 Offset O Deen E erte eet 6 9 Test Pattern Registers 1 to 3 Offsets 0x0020 to 0x0028 e tttteeennnnnnnntnnnnnntttcccsatis 6 10 Scratchpad Registers Offsets 0x0030 TOTDOROU 4G ss t UR iso de RR EP EET ripae Um 6 11 Board Semaphore Registers Offsets 0x 0040 to DM 0D ZC 6 12 Watchdog 0 Control Register Offsets 0x2000 and Watchdog 1 Control Register Offsets 0x2010 93 6 13 Watchdog 0 Interrupt Value Register Offsets 0x2004 and Watchdog 0 Interrupt Value Register Offsets 0x2014 EE 93 Publication No SBC610 0HH 2 Contents 9 Ge Control and Status Registers continued 6 14 Board Interrupt Status Register Offset OX 0 aa DEDE EA UR UM Qva 94 6 15 Board Interrupt Core O INT Mask Register Offset OA010 iiit ttti 95 6 16 Board Interrupt Core 1 INT Mask Register Offset 0x4014
64. 52 PMCn IO 52 53 AD35 54 AD34 53 PMCn IO 53 54 PMCn IO 54 55 AD33 56 GND 55 PMCn IO 55 56 PMCn IO 56 57 VIO 58 AD32 57 PMCn IO 57 58 PMCn IO 58 59 N C 60 N C 59 PMCn IO 59 60 PMCn IO 60 61 N C 62 GND 61 PMCn IO 61 62 PMCn IO 62 P 63 GND 64 N C 63 Cn IO 63 64 PMCn IO 64 Where n 1 for J14 and n 2 for J24 116 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 2 3 Signal Descriptions Table 7 21 PMC Signal Descriptions Signal Description AD 63 0 Address Data bits Multiplexed address and data bus CBE 7 0 Command Byte Enables During the address phase these signals specify the type of cycle to carry out on the PCI bus During the data phase the signals are byte enables that specify the active bytes on the bus FRAME Frame Driven low by the current master to signal the start and duration of an access DEVSEL Device Select Driven low by a PCI agent to signal that it has decoded its address as the target of the current access PAR Parity Parity protection bit for AD31 to ADO and BE3 to BEO PAR64 Parity Parity protection bit for AD63 to AD32 IRDY Initiator Ready Driven low by the initiator to signal its ability to complete the current data phase LOCK Lock Driven low to indicate an atomic operation that may require multiple transactions to complete BUSMODE1 Bus Mode 1 Driven low by a
65. 53 100 0x54 101 0x55 110 0x56 EI N A The local processor communicates with the BMM via the COM2 port from the MPC8641D The BMM serial interface is enabled when the COM2 transceiver is disabled using the COM2 Transceiver Enable Bit in Control Register 1 The BMM is connected to on board PC Bus 1 providing access for out of band monitoring of board status information such as on board voltage rail status or board temperatures by any other board in the system The BMM is programmed using bits in Control Register 1 though programming may only be performed when the NVRAM Write Enable Link E18 is fitted The BMM is powered from the P3V3 AUX supply meaning that board configuration information or BIT status can be read out of the device without enabling the main 5V power rail An PC buffer is sited on the on board PC Bus 1 to allow the BMM to access the Power Manager device and XMC Geographic Address PC DIP Switch when the on board supplies are not powered up Publication No SBC610 0HH 2 Functional Description 71 5 18 FPGAs 5 18 1 Local Bus Control FPGA This is a Lattice MachXO1200C that provides the following functions e Local bus address latching and chip select generation for Flash NVRAM e Data bus buffering to Flash NVRAM e AXIS Message Passing Interface 5 18 2 Register FPGA This is a Lattice MachXO1200C device that provides the following functions e Control Status Registers e Reset Logic e Interface to AFIX Parallel B
66. 56 Bytes No Yes Read only SDRAM configuration N A Unprotect and erase EEPROM 32 KBytes Yes Yes Yes Processor configuration board will only boot in Recovery model EEPROM s e lin DIP Switch 6 bits Yes Yes Yes XMC GA configuration Unprotect and set to default ae 10 Bytes No No Read only ETI User EEPROM N A PROM 1 MByte No No No 1 0 FPGA configuration N A Publication No SBC610 OHH 2 Specifications 155 Glossary ON LINK This glossary only features terms special to this manual Explanations of more general terms can be found in the Glossary publication number GLOS1 2eSST Two edge Source Synchronous data Transfer AMP Asymmetric Multi Processing BMM Board Management Microcontroller GEIP GE Intelligent Platforms NVMRO Non Volatile Memory Read Only SMP Symmetric Multi Processing SRIO Serial RapidIO 134 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 A AFIX Connector uictor iere encre eese T 121 Installation orina eer osea 29 AAA cadsasseanceasa eines 27 Signal Descriptions ssssssesseeene 122 vu M 63 Due recocido ca inicias 18 E E 73 B lla 132 BDM Connector arron ll 123 Blind dis 131 EBDSu cuidarla 80 Block Diagram EE 34 BMM santidad da 70 Board Identification sees 19 Board Installation sese 31 Boot Firmware E 131 Boot Flash rn eias 40 C io
67. 610 This signal is pulled high TCK Test Clock Clock for the PMC JTAG TMS Test Mode Select Select Test Mode for PMC JTAG TRST Test Reset Reset any PMC JTAG devices TDI Test Data In Input data for PMC JTAG chain TDO Test Data Out Data from a PMC JTAG chain PSV 5V supply pins P3V3 3 3V supply pins VIO PCI VII O pins Fixed at 3 3V on the SBC610 as 5V signaling is not supported N C 0 connection XCAP PCI X Capability detect Used to determine whether a PMC is PCI X capable N12V AUX 12 V auxiliary supply pins P12V AUX 12 V auxiliary supply pins GND Signal Ground M66EN Used to determine whether a PMC is 66 MHz PCI capable PMCn IO Rear UO connection from PMC site n n 1 or 2 Publication No SBC610 0HH 2 Connectors 117 7 5 XMC Connectors 7 3 1 315 425 J15 and J25 supply the PCI Express interface signals to the XMC1 and XMC2 connectors Table 7 22 J15 J25 Pin Assignments Pin A B E D E F 1 PCIE TXOP PCIE TXO P3V3 PCIE TX1P PCIE TXIN VPWR 2 GND GND JTAG TRST GND GND RESET IN 3 PCIE TX2P PCIE_TX2 P3V3 PCIE TX3P PCIE TX3N VPWR 4 GND GND JTAG_TCK GND GND RESET_OUT 5 PCIE TX4P PCIE TX4 P3V3 PCIE TX5P PCIE TX5N VPWR 6 GND GND JTAG TMS GND GND P12V AUX 7 PCIE TX6P PCIE TX6 P3V3 PCIE TX7P PCIE TX7N VPWR 8 GND GND JTAG TDI GND GND N12V AUX 9 Reserved Reserved Reserved Reserved Reserved VPWR 0 GND
68. 610 provides two fixed SRIO ports and the option to allow the remaining two links to be configured as either SRIO or PCIe Figure 5 7 Backplane Fabric Connectivity P1 Connector Tsi578 Serial RapidlO Switch PEX8518 PCI Express Switch All links shown are 4 lanes wide The fabric to be routed to Backplane Fabric Ports 3 and 4 on the P1 connector is selected by fitting Links E24 and E25 If the links are fitted then PCIe is routed to the connector If they are not fitted then SRIO is routed to the connector The state of these links is reflected in Control Register 2 and may be overridden by software if required Publication No SBC610 OHH 2 Functional Description 55 5 14 1 PCI Express The SBC610 uses a PLX PEX8518 PCIe switch to connect between the PEX8548 PCIe switch and the backplane PCIe ports This device allows flexible port configurations and non transparent ports to be used to meet a variety of customer requirements Up to four backplane ports are available sharing a maximum of 8 lanes Each PCIe port of the PEX8518 appears to software as a PCI to PCI bridge with its own PCI compatible configuration registers Each port is accessed on the internal virtual PCI bus using a device number equal to its port number The port configuration of the switch is initially set up by hardware strapping to use two x4 transparent ports to the backplane as shown below Table 5 22 PCle Port Configuration Port Width Lanes
69. AFIX Links E26 and E27 These links control features of the AFIX module and their function is determined by the module in use See the appropriate AFIX manual for further information Link E26 controls the state of the P41 connector pin D2 and link E27 controls the state of the P41 connector pin D3 On the AFIXSG these links are used to enable SCSI termination as defined below Table 3 11 E26 and E27 Link Settings E26 E27 AFIXSGSCSI Termination Out Out Notermination In Out 8 bit signals terminated Out In 16 bit extension signals terminated In In 8 and 16 bit signals terminated The state of these links is reflected in the Board Configuration Register 3 3 14 Spare Link E28 This link is reserved for future use Publication No SBC610 0HH 2 Configuration 27 3 4 Mezzanine Installation As shown in Figure 3 2 the SBC610 has two mezzanine sites that both support suitably compliant PMCs or XMCs including support for front panel I O The two sites allow for the fitting of two single width PMCs XMCs or one double width PMC XMC One AFIX site is also provided This is a GEIP proprietary interface allowing additional functionality to be added without taking up a mezzanine site The presence of a mezzanine in the various sites can be determined from the Board Configuration Register 3 4 1 PMC Installation NN CAUTION The SBC610 PMC sites are not 5V tolerant VIO pins are connected directly to the
70. AO RXP D7 SATA1 RXP E8 SATAO RAN Ei SATA1 RAN F8 Two activity LEDs are provided on the rear of the board each indicating activity on one of the two Serial ATA channels Publication No SBC610 0HH 2 Functional Description 53 5 13 GPIO The SBC610 supports up to 19 GPIO lines each with interrupt generation capabilities These are 3 3 V single ended signals with 5V tolerance These signals are controlled by the I O FPGA and can be configured as inputs with the ability to generate level or edge triggered interrupts or outputs with totem pole or open drain drivers The GPIO signals are intended only to be used by GEIP software drivers See the relevant software manual for details The GPIO signals are routed to the P6 connector via the AFIX connector P41 and share I O pins with the AFIX site If no AFIX module is fitted then the signals bypass the AFIX site and all 19 GPIO signals are available If an AFIX module is fitted then only the GPIO lines not used for AFIX I O are available To determine the number of GPIO present with a given AFIX see the appropriate AFIX manual Table 5 20 and 5 21 show the GPIO line routing via the AFIX connector which remaps the signals to the P6 connector GPIO lines 17 and 18 can also be used to control the behavior of BIT following reset These signals are readable by software as BIT_MODE 1 0 in the Link Status Register and if used for this purpose should not be driven by the GPIO controller
71. An on board power sequencer monitors the backplane supply voltages and will hold the SBC610 in reset or shut down the on board power supplies if the backplane supplies are not within specified limits The green front panel Power Good LED DS317 is lit when the backplane and all on board supplies are within specification The 5V supply to the mezzanine cards is switched under the control of the power manager device so that the 5V and 3 3V supplies are applied to the mezzanines at approximately the same time The SBC610 supports the PSU SEO IN PSU SEQ OUT power sequencing signals on the P1 connector pins G9 and C11 in line with other GEIP boards When connected in a power sequencing daisy chain the on board power supplies will only power up when SEQ IN pin is asserted or floated high An automatic override function is used which will power up the board if the SEO IN pin has been low for more than 500 ms See the Inter board Sequencing section for more details Publication No SBC610 0HH 2 Installation and Power Up Reset 53 5 e Functional Description Figure 5 1 Block Diagram 34 SBC610 6U VPX Single Board Computer Power and Utility 1 0 4x4 Fabric 2x sRIO only 2x PCI Express or sRIO VME PMC XMC 1 0 XMC I O Gigabit Ethernet SATA USB Serial PMC XMC 1 0 Serial XMC 1 0 AFIX 1 0 GPIO Publication No SBC610 0HH 2 NOTES Due to the increasingly short lifetimes of system components the I O d
72. C RES BUS N C RES BUS GND N C REF CLK N C REF CLK GND 7 1 2 Backplane JO Table 7 3 JO Pin Assignments Fin A B C D E F G H 1 N C Vs2 N C Vs2 NC Vs2 N C Vs2 None N C Mell N C Vs1 N C Vs1 N C Vs1 2 N C Vs2 N C Vs2 NC Vs2 N C Vs2 None N C Vs1 N C Vs1 N C Vs1 N C Vs1 3 5V Vs3 5V Vs3 5V Vs3 5V Vs3 None 5V Vs3 5V Vs3 5V Vs3 5V Vs3 4 GND NVMRO SVSRESET GND N12V AUX GND N C SM3 N C SM2 GND 5 GND SM DATA SM CLK GND P3V3 AUX GND GA4 GAP GND 6 GND GA0 GA1 GND P12V AUX GND GA2 GA3 GND 7 JTAG TRST JTAG TMS GND GND JTAG TDI JTAG_TDO GND GND JTAG TCK 8 GND GND N C RES BUS N C RES BUS GND GND N C REF CLK N C REF_CLK GND Publication No SBC610 OHH 2 Connectors 103 7 1 3 P1 Table 7 4 P1 Pin Assignments Pin A B C D E F G 1 LINK A LO RXP LINK A LO RX GND LINK A LO TXP LINK A LO TX GND N C RSVD S DND LINK A L1 RXP LINK_A_L1_RX GND LINK A L1 TXP LINK A L1 TX GND 3 LINK A L2 RXP UNK A L2 RX GND LINK A L2 TXP LINK A L2 TX GND VBAT 4 GND LINK A L3 RXP LINK A L5 RX GND LINK A L3 TXP LINK A L5 TX GND 5 LINK B LO RXP LINK B LO RX GND LINK B LO TXP LINK B LO TX GND SYS CON 6 GND LINK B L1 RXP LINK B L1 RX GND LINK B L1 TXP LINK B L1 TX GND
73. CRC error checking is performed on each packet transmitted between devices in the system and any corrupted packets are retransmitted End to end error checking can also be performed by the target device to ensure integrity of the received data 5 6 1 PCI Express Power Management All PCIe links support several power management features which are under software control and no hardware support is required The SBC610 does not support the WAKE signal and recovery from a D3cor state under auxiliary power 44 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 6 2 MPC8641D The MPC8641D has two high speed I O ports The SerDes1 port is configured as a x8 PCIe link and is connected to Port 0 of the PCIe Switch The port can operate in x1 x2 x4 or x8 modes This port is normally configured as the system Root Complex but when the Boot Hold off Link E21 is fitted the configuration is changed such that this port becomes a PCIe Endpoint This allows configuration transactions to be accepted to allow programming of the Boot Flash from a PMC The SerDes2 port is configured as a x4 Serial RapidIO port 5 6 3 PCI Express Switch The SBC610 uses a PLX PEX8548 PCIe Switch to connect all of the various PCIe devices together This is a 48 lane non blocking switch that can support up to nine PCIe ports The device also supports cut thru mode to reduce packet latency Each PCIe port of the PEX8548 appears to software as a PCI to PCI b
74. D P41 A30 4 GND GND P41 C17 P41 B18 GND GND er ee GND 5 eom nou nm mm een deor NO GND P C 6 GND GND EC Ge GND GND P41 C28 BITFAIL GND Publication No SBC610 OHH 2 Connectors 111 7 1 15 Signal Definitions Table 7 16 Backplane Connector Signal Definitions Signal Description Vs1 Vs2 VPX Vs1 and Vs2 power inputs Not connected on the SBC610 Vs3 VPX Vs3 5V Power input See the Electrical Specifications section for more details Ecke VPX 12V and 12V DC auxiliary power inputs Connected to the PMC XMC site otherwise unused by the SBC610 P3V3 AUX VPX 3 3 V DC auxiliary power input See the Electrical Specifications section for more details N C No Connection GND The DC voltage reference for the system Non Volatile Memory Read Only When this signal is high all on board non volatile memory is write protected This signal can be NVMRO externally pulled low using a link on the backplane or RTM or driven low under software control by the SBC610 if configured as System Controller SVSRESET System Reset When this is low it causes the system to be reset The SBC610 generates SYSRESET when it is configured as System Controller SM CLK System Management bus 0 clock and data Connects to the BMM via an 12C buffer Allows access to certain on board resources SM DATA from an external 12C master SM2 SM3 System Management bus 1 clock an
75. D P41 B2 P41 C2 GND P41 A5 8 GND P41 A3 P41 C3 GND P41 B4 P41 B5 GPI00 GND 9 P41 C5 P41 A6 GPIO1 GND P41 C6 P41 B7 GND P41 C27 10 GND P41 A8 GPIO2 P41 B8 GND P41 C8 P41 A9 GPIO3 GND 11 P41 C9 P41 B12 GPIO4 GND P41 A13 GPIOS P41 B13 GPIO6 GND P41 B29 12 GND P41 C13 P41 A14 GPIO7 GND P41 C14 P41 B15 GND 3 P41 A16 GPI08 P41 B16 GPIO9 GND P41 C16 P41 A17 GPIO10 GND P41 A30 4 GND P41 C17 P41 B18 GND P41 A21 GPIO11 P41 B21 GPI012 GND 5 P41 A22 GPIO13 P41 A24 GPIO14 GND P41 B24 GPIO15 P41 A25 GPIO16 GND P41 C30 6 GND P41 B25 GPIO17 P41 A28 GPIO18 GND P41 C28 BITFAIL GND 7 1 14 Backplane J6 Table 7 15 J6 Pin Assignments Fn A B C D E F G H 1 XMC2_10_E05 XMC210 D05 GND GND XMC2_10_B05 XMC21O0 A05 GND GND NED 2 GND GND XMC2_10_ 07 XMC210 D07 GND GND XMC2_10_B07 XMC210 A07 GND 3 XMC210 E09 XMC210 D09 GND GND XMC2_10_B09 XMC21O0 A09 GND GND EXT RESET 4 GND GND XMC210 F15 XMC210 D15 GND GND XMC210 B15 XMC2 0 A15 G 5 XMC210 E17 XMC210 D17 GND GND XMC2_10_B17 XMC210 A17 GND GND EXT ABORT 6 GND GND XMC210 F19 XMC210 D19 GND GND XMC2_10_B19 XMC210 A19 GND 7 PAVBI P41 A2 GND GND P41 B2 P41 C2 GND GND P41 A5 8 GND GND P41 A3 P41 C3 GND GND P41 B4 Se GND 9 P41 C5 PATAG GND GND P41 C6 P41 B7 GND GND P41 C27 GPIO1 0 GND GND Ee P41 B8 GND GND P41 C8 EC GND 1 P41 C9 on GND GND at aod GND GND P41 B29 2 GND GND P41 C13 an GND GND P41 C14 P41 B15 GND 3 Eau feted GND GND P41 C16 ipud GND GN
76. D USB2 P USB2 N GND VME D20 10 GND USB1 PWR USB2 PWR GND BOOT SWAP1 BOOT_SWAPO GND 11 COMI TXD COM1 RTS GND COM1 RXD COM1 CTS GND VME_D21 12 GND COM2_TXD COM2_RTS GND COM2_RXD COM2_CTS GND 3 ETHO_OP ETHO_ON GND ETHO_1P ETHO_1N GND VME_D22 4 GND ETHO 2P ETHO 2N GND ETHO 3P ETHO_3N GND 5 ETH10P ETH1 ON GND ETH1 1P ETH1_1N GND VME_D23 6 GND ETH2_2P ETH1_2N GND ETH1_3P ETH1_3N GND 7 1 10 Backplane J4 Table 7 11 J4 Pin Assignments Fin A 8 C D E F G H 1 XMCLIO F05 XMCLIO D05 GND GND VMCL IO B05 XMCiIO A05 GND GND VME D16 2 GND GND XMC1_10_ 07 XMCLIO D07 GND GND HMC IO B07 XMClIO A07 GND 3 XMCLIO E09 XMC1I0_D09 GND GND VMCL IO B09 XMCiIO A09 GND GND VME D17 4 GND GND XMC1IO F15 XMCiIO D15 GND GND XMC110 815 XMC1_IO_A15 GND 5 XMCI_IO_ 17 XMC110_D17 GND GND XMC1_10_B17 XMC110_A17 GND GND VME_D18 6 GND GND XMC1_10_F19 XMC110_D19 GND GND XMC110 B19 XMCLIO A19 GND 7 SATAQ_TXP SATAO_TXN GND GND SATAO RMP SATAORXN GND GND VME D19 8 GND GND SATA1 TXP SATA1 TXN GND GND SATA1 RXP SATA1 RXN GND 9 USBIP USB1 N GND GND USB2 P USB2 N GND GND VME D20 0 GND GND USB1 PWR USB2 PWR GND GND BOOT_SWAP1 BOOT_SWAPO GND 1 COM1_TXD COM1_RTS GND GND COM1_RXD COM1_CTS GND GND VME D i 2 GND GND COM2_TXD COM2_RTS GND GND COM2_RXD COM CTS GND 3 ETHO_OP ETHO_ON GND GND ETHO_1P ETHO_1N GND GND VME_D22 4 GND GND ETHO_2P ETHO_2N GND GND ETHO_3P ETHO_3N GND 5 ETH1_OP ETH1 ON GND GND ETH1 1P ETH1 1N GND GND VME_D23 6 GND GND ETH1 2P ETH1_2N GND GND ETH1_3P ETH
77. E16 Link Setting Setting Meaning Out Boot User Flash sectors are write protected by default In Boot User Flash sectors are write enabled by default LN CAUTION These links provide no write protection in hardware when not fitted All Flash write protection is provided by software 3 3 5 Flash Protection Unlock Link E17 A jumper must be fitted on this link to allow software to alter the Flash persistent sector protection which remains unchanged following a reset or a power cycle If no jumper is fitted the software is prevented from altering any previously configured sector protection See the Flash Sector Protection section for further details Table 3 5 E17 Link Setting Setting Meaning Out Persistent Flash sector protection cannot be altered In Persistent Flash sector protection can be altered NOTE The VPX backplane Non Volatile Memory Read Only NVMRO signal on connector PO pin A4 must also be set inactive low before the Flash sector protection can be altered 24 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 3 3 6 NVRAM Write Enable Link E18 Fitting a jumper on this link enables writes to the NVRAM device It also allows writes to the PC and Serial Configuration EEPROMs to be enabled using Control Register 2 Not fitting a jumper ensures that software cannot corrupt any of the non volatile memory apart from the Flash which must be protected separately during operation Table 3 6 E18
78. IO 04 HMC IO 02 GND GND PMC1 IO 03 C110 01 D GND VME A24 2 GND GND PMC1 IO 08 PMC1 IO 06 GND D C1 IO 07 HMC IO 05 GND 3 i d Geen DND GND PMC1 IO 11 C1 IO 09 D GND VME A25 GND GND wech Al SNP D dnos ai ae SND Boore om GND WEE VE mp GND VME A26 6 GND GND a are ane D E f a RUP a we Op GND MMCLCOM WEE D GND mea 8 GND GND M Ji om D Dama a oa OPS we ie OND GND CE T SNP GND VME A28 O 90 om cas WEE CND o Crocs wO CNO VE EE o GND Wich ii mp GND WE noo 2 om GND HTE T D o Grecs wie CNP wen wer NO GND ET D GND BE GND GND w wt CNP o Gen wo CNO WO wein ug GND I a D GND VMEASI 6 GND om uius WEE CND o cos wan CNO Publication No SBC610 0HH 2 Connectors 107 7 1 9 P4 Table 7 10 P4 Pin Assignments Pin A B C D E F G 1 XMC1 IO E05 XMC1 O D05 GND XMC1_10_B05 XMC1 IO A05 GND VME D16 2 GND XMC1 IO E07 XMC1 IO D07 GND XMC1 IO B07 AMC IO A07 GND j XMC1 IO E09 XMC1_10_D09 GND XMC1_10_B09 XMC1 IO A09 GND VME D17 4 GND VMCL IO E15 XMC1 IO D15 GND XMC1 IO B15 XMC1 IO A15 GND 5 VMCL IO E17 XMC1 O D17 GND XMC1 IO B17 XMC1 IO A17 GND VME D18 6 GND VMCL IO E19 XMC1_10 D19 GND XMC1 IO B19 XMC1 IO A19 GND 7 SATAO TXP SATAO TXN GND SATAO RXP SATAO RXN GND VME D19 8 GND SATA1 TXP SATA1 TXN GND SATA1 RXP SATA1 RAN GND 9 USB1 P USB1 N GN
79. IT aM ARD xD 27 Table 4 1 Power Supply Requirements nica 30 Table 5 1 Processor Specifications uester rmm city re eon rev iyi rev EHE ERE YE 36 Table 5 2 Flash Memory e usas petites tU UND HS E UU SINN NUNC NOE MM NOU DM M MEN E UM UM 38 Table 5 3 ee E a 39 Table 5 4 l c osse E 39 Table 5 5 Boot Image Selection m 41 o PP e UA 44 Table 5 7 PCI Express Switch Par CONO OA usd RE d Hd Ld AA AAA HU Eh RR 45 Table 5 8 PMC PCI ee en e is cicicstecssicS area icici ricer arate doen eerena maw aad ian ondu ated 47 TADES 9I NMEPCLMOP O 47 Table 5 10 PCI Bus Device Number MAIN mii a 48 Table 5 11 E TRATA PAMPA a 49 Table 5 12 COMT 2 Baud Rate Frequency and Divisor Values cnn 50 Table 5 13 COMI COM2 Signal e lity ascsscssscscccsascscssunzascssssenensonccvescncesvavsssasstonescoctenayenseaveyssssnanancheceneyensunqavevssaustonsoceecchanans 50 Table 5 14 COM3 4 Serial Port Signal Set eerste ENEE 51 Table 5 15 COM5 6 Serial Port Signal Set 52 Table 5 16 EtG Biet ein GE 53 Table 5 17 ET AE Ee ie leia ER Tabl 5 18 e USB5 Signal RUI iia 53 TOBE 5 I9 SATA Sigo Ee ee 53 Table 5 20 GPIO e e E 54 Table 5 21 P6 Pin Assignments No AFIX O iii 55 Tabl 5 22 e anb XE OI ssl 56 Table 5 23 Supported PCle Configurations rra crono 56 Table 5 24 SRIO Hardware Strapping Options ad RE UE ERE 57 Table e eege E 60 Table 5 25 PMC XMC Site 2 Signal Availability Ln 61 Table 5 27 PMC XMC Site ei E Te 62 Table 5 28 VMEbus
80. Intelligent Platforms Hardware Reference Manual SBC610 6U VPX Single Board Computer Edition 2 Publication No SBC610 OHH 2 EI c Res See PS SA VIBE THES imagination at work Document History Edition Date Board Artwork Revision First July 2008 Rev1 1DF March 2010 Rebranding only no technical content change 2 October2012 Rev4 Waste Electrical and Electronic Equipment WEEE Returns GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our a customers before August 13 2005 on a case by case basis A WEEE management fee may apply 2 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 About This Manual Conventions Notices This manual uses the following types of notice NOTE Notes call attention to important features or instructions N WARNING Warnings alert you to the risk of severe personal injury ZN CAUTION Cautions alert you to system danger or loss of data A TIP Tips give guidance on procedures that may be tackled in several ways ON LINK Links go to other documents or websites The purple link color may also be used within a body of text or paragraph to indicate a link or hyper
81. Link To Upstream Non Transparent 0 x8 0to7 PEX8548 Port 8 Yes No 1 x4 8to11 Backplane Fabric Port3 No No 2 x4 12to15 Backplane Fabric Port4 No No Port 0 is always configured as the upstream switch port with a width of x8 The configuration of the downstream ports of the switch which are connected to the backplane may be altered to meet specific system requirements The following port configurations are supported Table 5 23 Supported PCle Configurations z 5 ort 0 Width Port 1 Width Port 2 Width Port 3 Width Port 4 Width Upstream x8 x8 Lanes 0 7 Lanes 8 15 x8 x4 x4 Lanes 0 7 Lanes 8 11 Lanes 12 15 x8 x4 x2 x2 Lanes 0 7 Lanes 8 11 Lanes 12 13 Lanes 14 15 x8 x2 x2 x4 Lanes 0 7 Lanes 8 9 Lanes 10 11 Lanes 12 15 x8 x2 x4 x2 Lanes 0 7 Lanes 8 9 Lanes 10 13 Lanes 14 15 x8 x2 x2 x2 x2 Lanes 0 7 Lanes 8 9 Lanes 10 11 Lanes 12 13 Lanes 14 15 Each port is able to negotiate down to smaller link widths if required such as if a fault occurs on any particular lane Port widths of x1 x2 x4 and x8 are supported The PEX8518 also supports a non transparent port which can be set to any one of the downstream ports This feature allows the SBC610 to be connected to another host card with the port providing windows and address translation between the address domains 56 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Any changes to the configuration of
82. M programming data line output value 1 Data line output high 0 Clock line low default 5 BMM programming clock line value 1 Clock line high 6 Reserved Ob 0 BIT not run default b f BiT flag 1 BIT run 0 Switch disabled 8 Front panel Reset switch enable t switehrenabled EE 0 NVMRO backplane signal not driven 2 edad 1 NVMRO backplane signal driven low inactive 0 Serial EEPROMs write enabled Serial EEPROM write protect 1 Serial EEPROMs write protected default a 0 12C EEPROM write enabled i d protect 1 12C EEPROM write protected default 2 BIT Pass LED status SES LED Ii 3 BIT LED 2 status 0 LED off default LED Ii 4 BIT LED 1 status e roman LED Ii EN 0 LED off 5 BIT Fail LED status 1 LED lit default 6to24 Reserved 0x00 0 COM2 loopback disabled default 25 COM2 loopback enable 1 COM loopback enabled 0 COM2 RS422 mode 5 SESCH 1 COM2 RS232 mode default 0 COM transceiver disabled default d 27 COM transceiver enable 1 COM transceiver enabled 28 Reserved Ob 0 COMI loopback disabled default 29 COM1 loopback enable 1 COMI loopback enabled 0 COM1 RS422 mode 5B COMI Ro Se mode 1 COMI RS232 mode default 0 COM1 transceiver disabled default 31 COM1 transceiver enable 1 COM transceiver enabled a This bit is only writeable if the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low b This bit is
83. ND PCI AD 18 GND 2 P41_A2 P41 B2 P41 C2 AFIX LINKO JTAG TRST CLKO JC GPIO PCI_AD 19 PCI ADIO 3 P41 A3 GND P41 C3 AFIX_LINKO PSV CLK1 P5V GPIO PSV PCI_AD 1 4 GND P41 DA GND PSV JTAG TDI P3V3 IC P3V3 PCI AD 20 P3V3 5 P41_A5 P41_B5 P41_C5 INTER_FPGA2 JTAG_TMS CLK2 IC GPIO PCI AD 21 PCI AD 2 6 P41 Ap GND P41 C6 INTER FPGA3 GND CLK3 GND GPIO GND PCI_AD 3 7 GND P41_B7 GND GND JTAG TDO GND USB3 P GND PCI ADI22 GND 8 P41 A8 P41 B8 P41 C8 EREADY PCI M66EN POWER GOOD USB3 N GPIO PCI AD 23 PCI AD 4 9 P41 A9 GND P41 C9 N C P3V3 RESET P3V3 GPIO P3V3 PCI ADR 0 GND P5V GND P3V3 2C CLK P3V3 USBA P P3V3 PC AD 24 P3V3 1 12V AUX GND P12V AUX N C 2C_DATA DSELO USB4_N GPIO PCI_AD 25 PCI_AD 6 2 GND P41 B12 GND N C GND DSEL1 GND GPIO GND PCI_AD 7 3 P41_A13 PA B13 P41 C13 GND DC ACK64 GND PCI_CBEO GND PCI_AD 26 GND 4 P41 A14 GND P41 C14 AFIX FITTED PCI REQ64 IDSEL2 DC CBE GPIO PC AD 27 PCI ADI8 5 GND P41 B15 GND LOCAL ALEN P2V5 DSEL3 P2V5 GPIO P2V5 PCI_ADI9 6 P41Al6 P41 B16 P41 C16 P2V5 PCI_PAR P2V5 PCI_CBE2 P2V5 PCI AD 28 P2V5 7 P41_A17 GND P41 C17 LOCAL RD PCI_PAR64 P3V3 PCI_CBE3 P3V3 PCI_AD 29 P3V3 8 GND P41 B18 GND LOCAL WR GND P3V3 GND P3V3 GND P3V3 9 12V AUX P41 B19 P12V_AUX GND RQA GND USB5 P GND PCI_AD 30 GND 20 GND GND GND LOCAL_ADO RQB PCI FRAME USB5 N GPIO PC AD 31 PCI ADI10 21 P41 A21 P41 B21 P41 C21 LOCAL AD1 P5V PCI TRDY P5V GPIO P5V PCI ADI11 22 P41_A22 P41 B22 P41 C2 P3V3 RQC P3V3 IC P3V3 C P3V3 2
84. NKBLOTXN GND GND SYS_CON 6 GND GND NK BLLRXP LINK BLIRXN GND GND UNK BU Ip LINK BLITXN GND 7 LNKBL2RXP LINK BL2 EaN GND GND LINK B L2 TXP LINK B L2 TXN GND GND JTAG_AUTOWR a 8 GND GND NKB L3 RXP LINK_B_L3 RXN GND GND B L3 TXP BL IN GND 9 NK C LO RXP C LORXN GND GND C LOTXP UNKCLOTXN GND GND PSU SEQ IN 0 GND GND NK CLLRXP LINK CLL RAN GND GND LINK C LL TXP LINK CLL TXN GND 1 UNKCI2RXP LINKCL2 RN GND GND LINK CU TXP LINK C L2 TXN GND GND PSU SEQ OUT 2 GND GND LINK C L3 RXP LINK C L3 RXN GND GND LINK C L3 Ip LINK C L3 TN GND 3 NK DLORXP LINK D LO RN GND GND D LO mp LINK D LO TXN GND GND AXIS TIMER CLK 4 GND GND NK DLL pap LINKD LL EaN GND GND LINK D LL TXP LINK D LL TN GND 5 LNKD L2 Pap LINK D L2 ENN GND GND D L2 TXP LINK D L2 TaN GND GND AXIS TIMER RST 6 GND GND LINK D L3 RAP LINK D L3 RAN GND GND LINK D L3 TXP LINK D L3 IN GND 104 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 1 5 P2 Table 7 6 P2 Pin Assignments Pin A B D E F G 1 VME_D00 VME_SYSFAIL GND VME BBSY DND VME_ACFAIL VME D08 2 VME_D01 VME BRO DND VME_BCLR DND VME BG2IN VME D09 3 VME_D02 VME BR1 DND VME_BGOIN DND VME BG20UT VME D10 4 VME D03 VME BR2 DND VME BGOOUT GND VME BG3IN VME_D11 5 VME D04 VME BR3 DND VME BGI1IN DND VME BG3OUT VME D12 6 VME_D05 VME AMO DND VME BG1
85. None of this volatile memory is capable of write protection Table B 1 Volatile Memory Memory User User Access Type Size odifiable o Data Function Process to Clear SDRAM 2 or 4 GBytes Yes Yes Contains run time data Power off On die processor e shared cache 2 x 32 KBytes 0 No Improved memory performance Power off On die processor shared L2 cache 1 MByte 0 No Improved memory performance Power off SRAM 2 MBytes Yes Yes 1 0 FPGA local data buffering Power off ij Internal 144 KBytes Yes Ves 1 0 FPGA local data buffering Power off Other devices may contain internal RAM used to temporarily buffer data as it passes through the device In all cases a power off will cause the RAM to de energize and the contents to be lost B 2 Non Volatile Memory The SBC610 contains non volatile memory i e memory in which the contents are retained when power is removed Table B 2 Non Volatile Memory EEN Size adl M ur PME Function Process to Clear Type Modifiable to Data Protectable Flash 512 MBytes or Mas Ves Vas Stores operating system Unprotect and erase 16Byte or user data NVRAM 128 KBytes Yes Yes Yes tores ELUR and Unprotect and erase configuration data EEPROM 2x32 KBytes Yes Yes Yes PCle Switch configuration Unprotect and erase EEPROM 4 x 32 KBytes No No Yes PCI to PCle Bridge configuration N A EEPROM 32 KBytes Yes Yes Yes SRIO Switch configuration Unprotect and erase EEPROM 2 x 2
86. OM4 STB PMC2 IO 52 PMC2 IO 50 PMC2 IO 51 PMC2 IO 49 3 XMC2_10_E01 XMC2 1O D01 GND GND XMC2_10_B01 XMC2_I0_A01 GND GND VME_D30 COM5 TX A COM5 TX B COM5 RX A COM5 RX B PMC2 IO 56 PMC2 IO 54 PMC2 IO 55 PMC2 IO 53 4 GND GND XMC2 IO E03 XMC2 IO D03 GND GND XMC2_10_B03 XMC2 IO A03 GND COM5 RTS A COM5 RTS B COM5 CTS A COM5 CTS B PMC2 IO 60 PMC2 IO 58 PMC2 IO 59 PMC2 IO 57 5 XMC2_10_E11 XMC21O D11 GND GND XMC2 10 B11 XMC21O0 ALL GND GND VME D31 COM6 TX A COM6 TX B COM6 RX A COM6 RX B PMC2 IO 64 PMC2 IO 62 PMC2 IO 63 PMC2 IO 61 6 GND GND XMC2_10_E13 XMC2_10_D13 GND GND XMC2_10_B13 XMC2_10_A13 GND COM6_RTS_A COM6_RTS_B COM6_CTS_A COM6_CTS_B 110 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 1 13 P6 Table 7 14 P6 Pin Assignments Pin A 8 3 D F G 1 XMC2 IO E05 XMC2 IO DOS GND XMC2 IO B05 XMC2 IO A05 GND NED 2 GND XMC2 IO E07 XMC2 IO D07 GND XMC2 IO B07 XMC2 IO A07 GND j XMC2 IO E09 XMC2 IO D09 GND XMC2 IO B09 XMC2 IO A09 GND EXT RESET 4 GND XMC2 IO E15 XMC2 IO D15 GND XMC2 IO BIS XMC2 IO A15 GND 5 XMC2 IO E17 XMC2 IO D17 GND XMC2 IO B17 XMC2 IO A17 GND EXT ABORT 6 GND XMC2 IO E19 XMC2 IO D19 GND XMC2 IO B19 XMC2 IO A19 GND T P41 B1 P41 A2 GN
87. Publication No SBC610 0HH 2 6 4 Board Configuration Register Offset 0x000C Table 6 5 Board Configuration Register Bits Description Notes 0 Reserved Ob 000 PMC2 1 64 XMC2 12d P56 P64sx12d 001 PMC2 1 9 11 XMC2 Full P56 X20d385 010 Reserved e 011 Reserved SCH PMC XMC 2 1 0 configuration 109 PMC2 1 16 COM 3 4 5 6 XMC2 12d 101 PMC2 1 48 COM 5 6 XMC2 12d 110 Reserved 111 Reserved 4 Reserved Ob 00 PMC1 1 64 XMC1 12d P34 P64sX12d 01 Reserved 5 and 6 PMC XMC 11 0 configuration i0 Recerv d 11 PMC1 1 9 11 XMC1 Full P34 X20d38s em 0 Reserved 7 Dual Gigabit Ethernet fitted 1 Dual Gigabit Ethernet 0 Normal GPIO GPIO 18 0 routed to I O FPGA a Alternate GPIO configuration 3 _ alternate GPIO GPIO 7 0 routed to Bus Control FPGA 0 AFIN link 1 not fitted 9 AFIX link 1 E27 1 AFIX link 1 fitted 0 AFIN link O not fitted d 1 AFIX link 0 fitted 0 No AFIX fitted f ARA 1 AFIX fitted 0 No XMC fitted 2 XMC fitted in site 2 1 XMC fitted m 0 No XMC fitted d XMC fitted in site 1 1 XMC fitted z D 0 No PMC fitted 4 PMC fitted in site 2 1 PMC fitted 0 No PMC fitted 5 PMC fitted in site 1 1 PMC fitted 0 Intel Flash fitted S Flash type 1 Spansion Flash fitted 7and 18 Reserved 00b 0 32 bit Flash 9 Flash width 1 16 bit Flash 00 1 bank Flash 01 2 banks
88. Single Board Computer Publication No SBC610 0HH 2 7 2 PMC Connectors 7 2 1 J11 J21 and J12 J22 Table 7 17 J11 J21 Pin Assignments Table 7 18 J12 J22 Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal 1 TCK 2 N12V AUX 1 P12V AUX 2 TRST 5 GND 4 INTA 3 TMS 4 TDO 5 INTB 6 INTC 5 TDI 6 GND 7 BUSMODE1 8 PSV 7 GND 8 N C 9 INTD 10 N C 9 N C 10 N C 11 GND 12 N C 11 BUSMODE2 12 P3V3 15 CLK 14 GND 13 RESET IN 14 BUSMODE3 15 GND 16 GNT_A 15 P3V3 16 BUSMODE4 17 REQ_A 18 P5V 17 N C 18 GND 19 VIO 20 AD31 19 AD30 20 AD29 21 AD28 22 AD27 21 GND 22 AD26 23 AD25 24 GND 23 AD24 24 P3V3 25 GND 26 C BE3 25 IDSELA 26 AD23 27 AD22 28 AD21 27 P3V3 28 AD20 29 AD19 30 P5V 29 AD18 30 GND 31 VIO 32 AD17 31 AD16 32 C BE2 ES FRAME 34 GND 33 GND 34 IDSELB 35 GND 36 IRDY 35 TRDY 36 P3V3 3f DEVSEL 38 P5V 37 GND 38 STOP 39 XCAP GND 40 LOCK 39 PERR 40 GND 41 N C 42 N C 41 P3V3 42 SERR 43 PAR 44 GND 43 C BE1 44 GND 45 VIO 46 AD15 45 AD14 46 AD13 47 AD12 48 AD11 47 M66EN 48 AD10 49 ADO9 50 P5V 49 ADO8 50 P3V3 51 GND 52 C BEO 51 AD07 52 REQ_B 53 AD06 54 ADO5 53 P3V3 54 GNT_B 55 ADO4 56 GND 55 N C 56 GND 57 VIO 58 ADO3 57 N C 58 EREADY 59 ADO2 60 ADO1 59 GND 60 RESET OUT 61 ADOO 62 P5V 61 ACK64 62 P3V3 6 GND 64 REQ64 63 GND 64 MONARCH 3 LN CAUTION The SBC610 PMC sites are not 5V tolerant VIO pins are
89. Ze 8 GND PMC1 IO 32 PMC1_10_30 GND PMC1_10_31 PMCI IO 29 GND XMC1 O F11 XMCI1 IO F10 XMC1 O C11 XMC1 IO C10 PMC1 IO 36 PMCI1 IO 34 PMC1 IO 35 PMCI1 IO 33 XMC1 O F13 XMC1 IO F12 GND XMC1_10_C13 XMC1 IO C12 OND ME AES PMC1IO 40 PMCI IO 38 PMC1 IO 39 PMCI IO 37 E ND XMC1_I0_F15 XMCI1 IO F14 i XMC1 O C15 XMC1 IO C14 OND PMC1_10_44 PMCI1 IO 42 PMC1 IO 43 PMC1 IO 41 l XMC1_10 F17 XMC1 IO F16 SNP XMC1 O C17 XMC1 IO C16 SD THEN GND PMC1IO 48 PMCI IO 46 GND PMC1 IO 47 PMC1_I0_45 GND XMC1 IO F19 XMCI1 IO F18 XMC1 O C19 XMC1 IO C18 PMC1 IO 52 PMCI1 IO 50 PMC1 IO 51 PMCI IO 49 g XMC1 IO E01 XMC1 IO DO onp XMC1_I0_B01 XMC1 IO A01 END VME ee 4 GND PMC1 IO 56 PMC1 IO 54 GND PMC1 IO 55 PMC1 IO 53 GND XMC1 IO E03 XMC1 IO D03 XMC1 IO B03 XMC1 IO A03 PMC1 IO 60 PMCI IO 58 PMC1 IO 59 PMC1 IO 57 XMC1 O E11 XMC1 IO D11 OND XMC1 O B11 XMC1 IO A11 OND MULAS PMC1 IO 64 PMC1_10_62 PMC1 IO 63 PMC1 IO 61 S SR XMC1 IO E13 GND XMC1_10_B13 XMC1_10_A13 OND XMC1_10_D13 106 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 1 8 Backplane J3 Table 7 9 J3 Pin Assignments Fn A B C D E H 1 PMC1
90. _A13 XMCn_l0_B13 XMCn IO C13 MO D13 XMCn IO E13 XMCn IO F13 4 GND GND XMCn IO C14 GND GND XMCn IO F14 5 XMCn_IO_A15 XMCn IO B15 XMCn IO C15 XMCn JO D15 XMCn JO E15 XMCn IO F15 6 GND GND XMCn_IO_C16 GND GND XMCn_IO_F16 7 NMCn O A17 XMCn_l0_B17 XMCn_I0_C17 xMCn1O D17 XMCn_IO E17 XMCn IO F17 8 GND GND XMCn IO C18 GND GND XMCn IO F18 9 XMCn O A19 XMCn_l0_B19 XMCn IO C19 XMCn IO D19 XMCn JO E19 XMCn IO F19 Where n 1 for J16 and n 2 for J26 Publication No SBC610 0HH 2 Connectors 119 7 3 3 Signal Descriptions Table 7 24 XMC Signal Descriptions Signal Description PCIE TX 7 0 P N PCI Express Transmit differential pairs from XMC to switch PCIE RX 7 0 P N PCI Express Receive differential pairs from switch to XMC REFCLK P N PCI Express Reference Clock 100 MHz differential clock to XMC PRESENT XMC Present Pulled low by the XMC to allow the SBC610 to detect if an XMC is fitted RESET_IN XMC Reset In Reset driven from the SBC610 to the XMC RESET_OUT XMC Reset Out Reset signal driven by the XMC to the SBC610 from a front panel switch for example SM_DATA System Management Bus Data Data line for a two wire 2C system management bus SM_CLK System Management Bus Clock Clock line for a two wire 12C system management bus MBIST XMC Built in Self Test This signal can be held low
91. abled link E23 is not fitted Signal ground 124 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 7 PCI Express Mid Bus Probe Header J29 This footprint may be used to connect a PCI Express analyzer to monitor traffic between the processor and the PEX8548 switch The analyzer site is in the mezzanine keep out area and is intended for factory use only A retention module is required to be soldered to the board before a mid bus probe may be used Table 7 31 J29 Pin Assignments Pin Signal Pin Signal G1 GND 1 PCIE TX7 2 GND 3 PCIE TX7P 4 PCIE RX7N 5 GND 6 PCIE RX7P 7 PCIE TX6N 8 GND 9 PCIE TX6P 10 PCIE RX6N 11 GND 12 PCIE RX6P 15 PCIE TX5 14 GND 15 PCIETX5P 16 PCIE RX5N 17 GND 18 PCIE_RX5P 19 PCIE TX4 20 GND 21 PCIE TX4P 22 PCIE RXAN 235 GND 24 PCIE_RX4P 25 PCIE TX32N 26 GND 27 PCIE TX3P 28 PCIE RX3N 29 GND 30 PCIE RX3P 31 PCIE T2 32 GND 33 PCIE TX2P 34 PCIE RX2N 5 GND 6 PCIE_RX2P 37 PCIE TXIN 38 GND 39 PCIE TXIP 40 PCIE RXIN 41 GND 42 PCIE_RX1P 45 PCIE_TXO 44 GND 45 PCIE TXOP 46 PCIE RXON 47 GND 48 PCIE_RXOP G2 GND This connector makes use of the lane reversal and polarity inversion features of the PCI Express analyzer Publication No SBC610 OHH 2 Connectors 125 Ae Specifications A 1 Technical Specification Table A 1 Technical Data
92. and B01 D01 and E01 etc Publication No SBC610 OHH 2 Functional Description 59 Table 5 25 PMC XMC Site 1 Signal Availability P64s X12d Option P10s X20d38s Option PMC P3 PMC P3 XMC P4 PMC P3 XMC P3 XMC ES AMC P4 0 Pin 1 0 Pin I O Pin 1 0 Pin 1 0 Pin 0 Pin 1 0 Pin P14 IO 1 El P14 10 33 9 P1610 A05 EL P14 10 1 El P1610 C01 83 P16_10 A01 E13 P1610 A05 E P14 IO 2 B1 P14 10 34 B9 P16 0 B05 D1 P14 IO 2 B1 P16 I0 F01 A3 P1610 B01 D13 P1610 B05 D1 P14 IO 3 D1 P14 1035 D9 P16_I0_ D05 B1 P14 IO 3 D1 P16_10_C02 F4 P16_10 D01 B13 P1610 D05 DI P14 IO 4 Al P14 1036 A9 P1610 E05 Al P14 IO 4 Al P16_10_C03 E4 P16_10_E01 A13 P16IO_E05 Al P14 IO 5 F2 P14 0 37 F10 P16 I0 A07 F2 P14 IO 5 F2 P1610 F02 C4 P16_10 A035 F14 P1610407 F2 P14 IO 6 C2 P14 1038 C10 P16 10 807 2 P14_10 6 C2 P16 IO F03 B4 P16_I0_ 803 E14 P16 0807 E2 P14 IO 7 E2 P14 10 39 E10 P1610 D07 C2 P14 IO 7 E2 P16_10 C04 5 Pa O D03 C14 P1610 D07 C2 P14 IO 8 B2 P14 0 40 B10 P16 10 E07 B2 P14 IO 8 B2 P1610 C05 D5 P1610 E035 B14 P16 10 E07 B2 P14 IO 9 E3 P14 1041 E11 P16 10 A09 EN P14 JO 9 E3 P160 F04 B5 PEO AMI ES Pa OLA E5 P14 IO 10 B3 P14 O0 42 B11 P16 10 809 D3 P16 IO F05 A5 P16 10 B11 D15 P1610 B09 D3 P14 IO 11 D3 P14 1043 D11 P16 O D09 B3 P14 1011 D3 P1610 C06 F6 P16 10 D11 B15 P1610 D09 B3 P14 IO 1
93. applications 85 at the thermal from 15 to 2000 Hz sawtooth 11 varying with high levels of shock and vibration small Rugged interface per MIL STD 810E ms duration temperature space envelope and restricted cooling supplies Conduction Storage 50 to Fig 514 4 8 for high 10 cycles Conformally coated as standard Optional ESS cooled Level 5 4100 240 hours performance aircraft 12g RMS 128 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 A 4 Reliability MTBF The following table shows the predicted values for reliability as Mean Time Between Failures MTBF and failures per million hours fpmh for board artwork revision 3 changes between revision 3 and revision 4 were minor Table A 6 Reliability MTBF Fail Rate RECEN Failures Per Million Hours HESS Ground benign 30 C 4 0453 247 200 Ground fixed 40 C 17 7327 56 393 Ground mobile 45 C 44 8789 22 282 Naval sheltered 40 C 24 5328 41 097 Naval unsheltered 45 C 62 7160 15945 Airborne inhabited cargo 55 C 43 7000 22 883 Airborne inhabited fighter 55 C 60 8378 16 437 Airborne uninhabited cargo 70 C 116 4834 8585 Airborne uninhabited fighter 70 C 153 6293 6509 Airborne rotary wing 55 C 127 8130 7824 Space flight 30 C 3 1293 319 558 The predictions are carried out using MIL HDBK 217F Notice 2 Parts Count method To complement the 217 failure rates some manufacturers data is included where appropriate nQ valu
94. aseT Ethernet port operating in 100BaseT mode DS312 Yellow Ethernet Port 1 10BaseT Ethernet port operating in 10BaseT mode These LEDs are under the control of the 88E1111 PHYs and the descriptions define the default functions of the LED outputs These are under software control however and may be subsequently reassigned 5 24 2 BIT LEDs DS313 to DS316 Table 5 38 BIT LEDs LED Color Function Description DS316 Red BIT Fail DS315 Yellow BITLED1 software controlled LEDs used to show DS314 Yellow BITLED2 the status of BIT or other boot software DS313 Green BIT Pass DS313 to DS316 are used by the software running on the SBC610 e g BIT to indicate its status The BIT Fail LED DS316 is illuminated following reset and must be turned off by software The BIT Pass LED DS313 is used to indicate that the software has completed any power up tests and is running correctly Table 5 39 BIT Status LED Meanings BITFail LED BIT Passed DS316 LED pss1s Status On Off BIT not yet run Reset state or BIT failed Off On BIT complete and passed The yellow BIT LEDs DS314 and DS315 are used to indicate progress through BIT and so may provide information for debugging purposes in the event of failure These LEDs are software programmable via Control Register 1 and may be reassigned for another purpose after BIT has completed The status of the software can also be monitored using the BITFAIL signal on the P6 conne
95. be used to configure registers within the device if required This EEPROM is write protected by default and can be write enabled by clearing the Serial EEPROM Write Protect bit in Control Register 1 This bit may only be cleared when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low The Switch can be prevented from accessing the EEPROM under software control if the data becomes corrupted and configures the switch such that the EEPROM contents cannot be overwritten This may be done by setting the PEX8548 Serial EEPROM Disable bit in Control Register 2 or by fitting the Recovery Boot Link E14 The PEX8548 is connected to on board PC Bus 1 Address 0x58 to allow configuration by the processor and out of band monitoring of link status LEDs on the rear of the board show whether each of the on board PCIe links is active or inactive Further status information number of active lanes etc can be ascertained from registers within the switch 5 6 4 PCle to PCI Bridge Where connection to PCI or PCI X devices is required the SBC610 uses PLX PEX8114 Bridges The bridges can operate in forward PCle to PCI or reverse PCI to PCIe mode they are normally used in forward mode on the SBC610 The bridge has a x4 PCIe interface but can also operate in x1 or x2 mode and supports lane reversal The PCI PCI X interface is 64 bits wide and can operate at frequencies up to 133 MHz The
96. before insertion LN CAUTION 2 The SBC610 has been specifically designed for use with 6U VPX backplanes designed to accommodate a single ended pin out on the J2 connector and is not compatible with 6U backplanes where the J2 connector is intended for differential signaling Plugging the SBC610 into such a 6U backplane may cause permanent component damage Air cooled versions of the SBC610 have injector ejector handles to ensure that the backplane connectors mate properly with the backplane The captive screws at the top and bottom of the front panel allow the board to be tightly secured in position which provides continuity with the chassis ground of the system Conduction cooled versions of the SBC610 have screw driven wedgelocks at the top and bottom of the board to provide the necessary mechanical thermal interface Correct adjustment requires a calibrated torque wrench with a hexagonal head of size 3 32 2 38 mm set to between 0 6 and 0 8 Nm In an air cooled development enclosure when taking I O connections from the backplane connectors use of GEIP I O modules or some equivalent system ensures optimum operation of the SBC610 with regard to EMI See the VPX I O Modules manual for more details ON LINK VPX I O Modules Hardware Reference Manual publication number VPXIOM OHH Publication No SBC610 0HH 2 Installation and Power Up Reset 51 4 4 Connecting to SBC610 To interact with on board firmware requires the SBC610
97. busy 1 Flash bank busy i 0 CS2 top sector accesses Flash bank 1 a A805 A ode enable 1 CS2 top sector accesses Flash bank 0 BANC area default 0 16 bit User Flash read in non ANDed mode a SE ZAND Moue enanle 1 16 bit User Flash read in ANDed mode default 0 Core 0 boot areas reside in Primary boot area 0xFF80 0000 default e ME BOO Selec 1 Core 1 boot areas reside in Primary boot area 0xFF80 0000 0 Flash address derived from local bus Es MAU Paged Modeenable Flash address bits 1 4 derived from registers default 24 RO Reserved 0 When the Paged Mode Enable bit is set these bits provide the MSBs of the 25to27 RW Flash CS2 address bits 2 4 Flash address to select a 128 MByte page default 0x7 When the Page Mode Enable bit is set these bits provide the MSBs of the 28t031 R W Flash CS1 address bits 1 4 Fla hiaadress fo select 4 128 MByte pige If bit 28 is set high the page selected resides in the CS1 area If bit 28 is set low the page selected resides in the CS2 area default OxF 6 9 Test Pattern Registers 1 to 3 Offsets 0x0020 to 0x0028 Registers 1 and 2 normally contain alternating set bit test patterns to verify bit ordering and check for stuck bits When the Flash Protection Unlock Link E17 is fitted and the backplane NVMRO signal on connector DO pin A4 is inactive low the values of these registers change to allow software to alter the Flash sector protection Register 3 contains a tes
98. by the XMC to indicate that it is not yet ready to be enumerated by the root complex GA 2 0 Geographic Address Used to identify the address of the XMC on a shared 12C bus NVMRO Non Volatile Memory Read Only Used to write protect any non volatile memory on the XMC This signal is driven inactive when the NVRAM Write Enable Link E18 is fitted and the VPX backplane NVMRO signal lon connector PO pin A4 is low JTAG TCK JTAG Test Clock Clock for the XMC JTAG JTAG TMS JTAG Test Mode Select Select Test Mode for XMC JTAG JTAG TRST JTAG Test Reset Reset any XMC JTAG devices JTAG TDI JTAG Test Data In Input data for XMC JTAG chain JTAG TDO JTAG Test Data Out Output data from an XMC JTAG chain XMCn IO Rear UO Connection from XMC site n n 1 or 2 P12V AUX 12V auxiliary supply pins N12V AUX 12V auxiliary supply pins VPWR 5V supply pins P3V3 3 3V supply pins P3V3_AUX 3 3V auxiliary supply pins GND Signal Ground WAKE PCle control ROOT PCle control Reserved Reserved by VITA 42 0 or 42 3 specification not connected on the SBC610 120 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 4 AFIX Connector P41 Table 7 25 P41 Pin Assignments Pin A B E D E F G H d K 1 GND P41 B1 GND GND JTAG TCK GND JC D
99. cccesceseeesteteseseseenens 75 Mechanical Specification sss 126 Memory EEPROM cccccssscesssecssscecseecssececscecseeeeseecsseeeenaeens 70 LAS SE 39 Ma pS n 37 SIA EE 44 RAM MPH 39 Volatility Statement sss 133 MPX Bue 37 hn gy 129 N NVRAM EE A4 Write Enabling nere eR 25 O Operating Environment sse 127 Er EENS 130 P PCI Buses To AFIX USB and SATA eee 48 To PME Sites eit eie tees tert neret eR RENE es 47 To VME Bridge etienne inne 47 PCI Express Backplane Lane Status LEDen 82 Infrastructure oococccoonnononcnonnnonnnocnnnnonnnononannnnnronanannnnss 44 Link Status LEDs eee 81 Mid Bus Probe Conpechor 125 Off board Fakte 56 NG RE 46 Power Management 44 Ida MEE 45 PR OCG Sia e tee aen etie i te 16 PM Ces 59 Connectors A aaseactesancsedssebadeses 115 Installation ninio ainia 28 AAA A 59 Signal Descriptions sss 117 EE ee 59 Power ES AAA nii anea EEE 69 SEQUE CI c n 77 Supply Requirements EE 30 Problems Re rire nani 6 Product Codes eere 19 130 Product Idenpfcatpton 19 Prohle esnsnesfesubneD cata 126 Publication No SBC610 0HH 2 R RA Misisipi 39 Registers Ee e 86 AXIS Semaphore serieren 99 AXIS Timer Control 99 Board Configuration sess 87 Board Frequency EE 86 Board MD saevire iseis ristis teei Tes
100. cted to these signals and generates a common timestamp for data passed between them The SBC610 can also act as a master on these signals generating a clock with programmable frequency and asserting the reset under software control Eight hardware semaphores are also provided for use in locking common resources See the AXIS and FIFO register definitions for more details Publication No SBC610 OHH 2 Functional Description 73 5 21 Resets Interrupts and Error Reporting The following table shows the various external interrupt sources to the processor and their relative priorities It also shows whether the previous state of the processor is recoverable Table 5 34 Processor Interrupts Priority Interrupt Cause Recoverability 0 System Reset Power on Hard Reset Input Non recoverable 1 Machine Check MCP Input Non recoverable in most cases 2 System Reset Soft Reset Input Recoverable unless Machine Check occurs 3 System Management Interrupt SMI input Recoverable unless Machine Check or System Reset occurs 4 External Interrupt INT input Recoverable unless Machine Check or System Reset occurs 5 21 1 Hard Reset A hard reset is used to reset the MPC8641D including the processing cores and all other devices on the SBC610 that require resetting When released from reset Processing Core 0 will begin executing from the Boot Flash at address OxFFFO 0100 A hard reset is asserted when any of the following events occur
101. ctor pin F16 80 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 24 3 Power Good LED DS317 When on this green LED indicates on board and off board power supplies are within their specified limits 5 24 4 Reset Status LEDs Table 5 40 Reset Status LEDs LED Color Function Meaning When Lit DS318 Green CPU Ready MPC8641D processor has completed initialization and is not in a sleep mode DS319 Red Reset SBC610 is in hard reset NOTE DS318 is illuminated when the MPC8641D internal initialization is complete but may be extinguished when either of the processing cores is in a low power mode such as nap mode These modes are under software control so the LED may toggle during operation if these modes are in use 5 24 5 PCI Express Link Status LEDs DS320 to DS328 Table 5 41 PCI Express Link Status LEDs LED Color Function eaning When Lit DS320 Green PEX8548PortO Good The PCle link to the MPC8641D is active DS321 Red PEX8548 Fatal Error A fatal error has occurred has been detected by the PEX8548 switch DS322 Green PEX8548Port1Good The PCle link to the AFIX PCle PCI Bridge is active DS323 Green PEX8548Port2 Good The PCle link to the PMC2 PCle PCI Bridge is active DS324 Green PEX8548Port8 Good The PCle link to the PEX8518 PCle Switch is active DS325 Green PEX8548Port9 Good ThePCle link to XMC1 is active DS326 Green PEX8548 Port 12 Good The PCle link to XMC2 is active DS327 Green PEX8548 Port 13 Good The PCle link to
102. d data Not connected on the SBC610 GAP Geographical addressing parity bit input The sum of all GA bits including the parity bit should be an odd number GAI4 0 Geographical Addressing bits JTAG_TCK JTAG TCK input AC terminated and connects directly to the JTS06 Scan bridge device JTAG TDI JTAG TDI input Connects to the JTS06 Scanbridge device JTAG TDO JTAG TDO output Driven by the JTS06 Scanbridge device when selected by the JTAG master JTAG TMS JTAG TMS input Connects to the JTS06 Scanbridge device JTAG TRST JTAG TCK input Connects to the JTS06 Scanbridge device ae VPX REF_CLK and REF CLK Not connected on the SBC610 red VPX RES_BUS and RES BUS Defined by VITA 46 0 as a reserved bus Not connected on the SBC610 AXIS TIMER CLK AXIS TIMER RST JTAG AUTOWR Operates as a clock output in AXIS master mode and a clock input in AXIS slave mode This signal can be bused between multiple boards to provide a common timestamp Active high reset signal driven out in AXIS master mode and used to reset the AXIS timer in AXIS slave mode This signal can be bused between multiple boards to provide a common timestamp AutoWrite signal used by JTAG technologies equipment to accelerate programming of Flash via JTAG Routed to the JTS06 Scanbridge device LINK x Ln RXN Backplane fabric receive inputs These should be connected to the transmit outputs of another board to create a link
103. d graphics AFIXSG USB Flash memory AFIXM and differential GPIO AFIXDIOI This site also allows specific customer requirements to be accommodated more quickly and easily than a modification to the main host board Contact your local sales representative with any specific requirements The AFIX site is connected to a 32 bit 33MHz PCI bus shared with the SATA and USB functions An 8 bit multiplexed address data parallel I O bus is also provided for communication with devices on the AFIX that do not support a PCI interface and to determine the type of AFIX fitted to the board This interface is accessed using Chip Select 5 on the MPC8461D Local Bus interface The AFIX I O is routed to the P6 connector The presence of an AFIX card in the site can be determined from the Board Configuration Register Publication No SBC610 0HH 2 Functional Description 63 5 16 VME The SBC610 uses a Tundra Semiconductors Tsi148 Tempe PCI to VME bridge to provide a full master slave VME interface The Tsi148 is compliant with the following standards e American National Standard for VME64 ANSI VITA 1 0 1994 R2002 e American National Standard for VME64 Extensions ANSI VITA 1 1 1997 e Source Synchronous Transfer 2eSST Standard ANSI VITA 1 5 2003 The Tsi148 features e Support for 2eVME and 2eSST protocols e Full VMEbus system controller functionality e Interrupt and Interrupt handling capability e Two independent DMA control
104. d is intended to hold user application code or data User Flash is accessed using Chip Selects 1 and 2 CS1 and CS2 on the Local Bus Controller of the MPC8641D CS1 is intended for use by Processing Core 0 and may be used to access all areas of Flash as required when using a single core or SMP system CS2 is intended for use by Processing Core 1 and may only access the lower area of Flash When Core 1 is using CS2 to access Flash Core 0 should not normally use CS to access these same areas to ensure private access for Core 1 The 8 MBytes of Boot Flash appears at the top of the User Flash area with the four boot images appearing in their physical locations as shown below unaffected by the state of the Flash Boot Image Select links Figure 5 4 User Flash Chip Select Mapping Core 0 Core 1 Core 0 Core 1 Boot Area 8 MBytes Boot Area 8 MBytes Boot Area 8 MBytes Boot Area 8 MBytes Bank O Bank 1 Bank O Bank 1 User Flash User Flash User Flash User Flash 248 MBytes 248 MBytes 248 MBytes 248 MBytes Core 1 r Bank 2 Bank 3 t EE y User Flash User Flash Bank 1 256 MBytes 256 MBytes User Flash 248 MBytes Core 1 Chip Select 1 Chip Select 2 PAPE AEn E Meic 512 MByte Flash Option 512 MByte Flash Option Bank 1 User Flash 248 MBytes These areas should not be Bante accessed when Core 1 is using Uzer tse Chip Select 2 to access them 256 MBytes Note In a single core system or if both Chi
105. d m 17 18 31 39 Chassis Ground esee 31 Configuration hri 28 Eu Ge da 21 A FIX CONO etico tonterias 27 Boot Flash Write Enable cccccccesceseeeeenes 24 Boot Hold off sese 26 Core 0 Boot Area Selection ssesessseseseeeeeseeeee 22 Core 1 Boot Area Selection s ssssessseseseseereeeee 23 Description ER EE 22 Pie 23 A E E 22 23 E15 and Elo eet ees 24 uv 24 El idonee em t mns 25 IEN BE 25 BQO 26 iu 26 EE 26 E23 ccce ibd tede i une E ee deis 26 Publication No SBC610 0HH 2 Index C continued Configuration continued Link continued E24 and B25 nc 26 E26 and B27 aetema odis 27 E28 creo diae au epi Er GEHE 27 Flash Protection Unlock 24 NVRAM Write Enable ss 25 PCI Express Gelecton sssesssrsseessessesssessessessees 26 POSHLONS cnica tie 21 Recovery Boot EE 23 Scanbridge Output Enable 26 SMP Mode iere rre 25 User Flash Write Enable ue 24 Connecting to SBC610 sss 32 CONTE CONS criticadas il it 102 O Seeds stoeasees tates 121 Backplane en 103 ege 103 A bn N 104 jp aint 105 JB E 107 E eri iei Reds 108 JD ess M A 110 JO idit aeree n diei tenes 111 REN 103 E
106. destruction of components A 2 2 Power Consumption Typical power consumption figures for SBC610 are shown below These are given at cold wall temperatures of 25 C and 85 C in a conduction cooled environment Table A 3 Power Consumption Processor Temperature Nominal Wl Maximum W 25 C 57 5 63 4 8641D 1333 MHz 85 C 718 78 0 25 C 52 2 55 6 8640D 1067 MHz 85 C 66 6 718 25 C 46 3 47 7 8640 1067 MHz 85 C 58 59 9 Nominal consumption was measured with both cores at the VxWorks prompt Maximum consumption was measured with both cores running cache resident Altivec FFT tests NOTE When using XMCs PMCs ensure that they do not cause the specified maximum supply current to be exceeded It may not be possible to support all combinations of XMCs PMCs within this limit Publication No SBC610 0HH 2 Specifications 127 A 3 Environmental Specifications A 3 1 Convection cooled Boards Table A 4 Convection cooled Environmental Specifications Build Style Temperature C Vibration Shock Humidity Comments Operating 0 to 55 Random 20g peak Up to 95 RH Commercial grade cooled by forced air for with airflow of 300 0 0020 Hz from 10 sawtooth use in benign environments and software Standard feet minute e 11ms development applications Optional conformal E to 2000 Hz lopment app ications Optional conforma Level 1 Storage 50 to 100 Sine 2g from 5 duration coating to 500 Hz Opera
107. e Supply Requirements NE 127 Table Aas nt PEI OR DEE 127 Table A 4 Convection cooled Environmental SpecifiCAtions cssssscccccsssssseescscssssssseesssssssssssesesssssssssnessessssssssessseesesssssneeeesees 128 Table A 5 Conduction cooled Environmental Specifications secet 128 Table A 6 Reliability MT BE isnt te tr RR ER REGERE DA REED UAR RR RD MARR DENS 129 TONCA d cl ra Lu cm M e I M 129 Eelere gl 130 TABA Volte Ie e ee M M 133 Table B 2 Non Volatile En 133 14 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 List of Figures Figure LAA eoo 16 Figure 1 2 ESD Label Present on Board Packaging sat 18 Fig re 2 1Prod ctLabel Packaging E 19 Figure 2 2 Predgstisebeli ROO cities it tiim dum idum dn wem dn mte 19 Figure 2 3 Product Label Conduction cooled Product ecssssssssssssssssssssssssssssssssssssssssssssssssssssssssssesesssssssesssssesssesssssesesesesssesesesett 20 pinus e 21 Figure 3 2 Mezzanine POSIIOPIS iris 29 Foire DUBIO DIAO OMi Race SH is io CUIU si 34 Fig re 5 2 Has Memory SERUCBUEG A N 40 Fidis 5 3 Local Bus CSO MOPPING cei UA teen ena mene o 40 Figure 5 4 User Flash Chip Select Mapping iii 41 Fig re 5 5 Flash Paged Access Moderens iaa A EAN NNa 42 Figure 5 6 Redundant Flash Mode Mopplirig casueserererrettrereererrerterereererrer terere erret eerie 43 Figure 5 7 Backplane Ener 55 Figure 5 8 TC ENEE enee 67 Figure 5 9 SBC610 Machine Check EXCBDEOFI aria 75 Figure 5 1
108. e periodic interrupts Each group of 4 timers can be set to operate from a divider of the MPX bus clock divided by 8 16 32 or 64 or from an external 14 318 MHz clock The minimum resolution of each timer is 15ns Each group of timers can be cascaded to form two 63 bit timers one 95 bit timer or one 127 bit timer if required 5 19 1 Watchdog Timers The SBC610 provides two independent programmable 32 bit Watchdog timers These are count down timers and are capable of generating interrupts to the either or both of the two processing cores at a programmable threshold and resetting the board if expired The timers are disabled following reset but once enabled the Watchdog must be serviced periodically to prevent a reset Further details on the operation of the Watchdog can be found in the Watchdog register definitions 5 20 AXIS Support The SBC610 provides hardware features required to support GE s AXIS software suite Four 32 bit wide FIFOs capable of holding 64 messages each are provided to support message passing between the two on board processing nodes or from other nodes in the system to the on board processing nodes An interrupt can be generated to the receiving processing node when a message is received and remains asserted until the message queue is empty The SBC610 supports a 48 bit timer clocked by the external AXIS_TIMER_CLK signal and reset by the AXIS_TIMER_RST signal This allows several boards to be conne
109. echnology inserts The GEIP software strategy ensures that customers can develop market leading products using the O S and development environment best suited to their long term program requirements A 7 1 Boot Firmware The Boot firmware provides a foundation layer to interface between the raw board hardware with its highly programmable device set ups and flexibility and the supported Operating Systems which require a straight forward booting and device interface model The U Boot Firmware includes comprehensive configuration facilities interactive or auto boot sequencing from a range of device types automatic PCI resource allocation at initialization PCI display interrogation utilities and other valuable features for system integrators Memory or other speed and feature enhancements are seamlessly absorbed by the Boot firmware giving the same look and feel to the O S and the user application as the GEIP hardware models advance This allows the constant use of latest technology in required areas without system impact Where particular operating systems define the use of alternate boot methods e g VxWorks bootroms the Boot firmware technology is absorbed into such boot methodology A 7 2 Built In Test BIT probes from the lowest level of discrete on board hardware up to Line Replaceable Unit level within a system ensuring the highest degree of confidence in system integrity BIT includes comprehensive configuration facilities all
110. er The Tsi148 manages the completion of the read transfer on the VMEbus issuing retries on the PCI bus until the transfer is completed This allows other PCI bus masters to use the PCI bus while the VMEbus transfer is in progress VMEbus master write cycles use posted writes Posted writes are acknowledged immediately on the PCI bus allowing the PCI bus to be used by other masters while the VMEbus transfer is in progress The transaction is queued in a write buffer until the VMEbus is available for the data to be transferred If the posted write buffer is full the PCI transaction is retried until there is space available The Tsi148 is able to accept its own transaction on the VMEbus if the address driven by the VME master falls within a VME slave address window 5 16 3 VMEbus Slave Access Eight software programmable VMEbus slave images are available An offset may be applied to translate the VMEbus address to a different address on the PCI bus allowing any VMEbus address to access any on board address The Tsi148 internal registers can be accessed as part of the 512 KByte CR CSR area at an address dependent on its Geographic Address as defined in the VME64 standard Single Cycle Transaction VMEbus slave read accesses cause the VMEbus acknowledgement to be held until the data is received from the PCI bus In the case of block read transfers the VME slave requests a block of data from the PCI bus which is stored in a read buffer until it
111. ercentage error will increase significantly at higher baud rates Different divisors will be required if a different MPX Bus Frequency is used Table 5 12 COM1 2 Baud Rate Frequency and Divisor Values Target Baud MPX Bus Divisor Divisor Actual Baud Error Rate Frequency MHz Decimal Hexadecimal Rate 9600 533 333 3472 0D90 9600 61 0 0063 19200 533 333 1736 06C8 19201 22 0 0063 38400 533 333 868 0364 38402 43 0 0063 57600 533 333 579 0243 57570 52 0 0512 115200 533 333 289 0121 115340 25 0 1217 The actual performance of these ports will be limited by the throughput capability of the software driver The serial ports are driven by ISL41334 bus transceivers and can be individually software configured through Control Register 1 to operate in RS232 or RS422 mode though the flow control signals are not available in RS422 mode The following COM1 and COM2 signals are available through the P4 connector Table 5 13 COM1 COM2 Signal Availability RS232 Signal RS422Signal Input Output P4 Pin RS232 Signal RS422 Signal Input Output P4 Pin COMITXD COM1TXDA Output AU COM2 TXD COM2 DD A Output B12 COMI R4D COMI RXDA Input D11 COM2 RAD COM END A Input E12 COMI RIS COMLTXD_8 Output B11 COM2 RIS COM TXD B Output C12 COMI CTS COMLRXDB Input E11 COM2 CTS COM2_RXD_B Input F12 50 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 10 2 COM3 and COM4 COM3 and COM4 are provided by the I O FPGA This
112. ere are four parallel PCI buses on the SBC610 5 7 1 PCI Buses to PMC Sites Each PMC Site is connected to a PEX8114 PCIe to PCI bridge via a 64 bit PCI PCI X bus capable of running at up to 133 MHz The speed of the bus is based on the capability of the PMC and is determined by the bridge The current operating frequency of each bus may be ascertained by reading registers within the appropriate PEX8114 The device number mapping for the PMC PCI buses are as follows Table 5 8 PMC PCI Device Mapping Device IDSEL Function 0to7 16to23 Notimplemented 8 24 PMC Device A 9 25 PMC Device B 10 26 PEX8114 Bridges l1to15 27to31 Notimplemented a The PEX8114 is connected to an IDSEL only on the PCI bus to PMC site 1 Fitting a jumper to the Boot Hold off Link E21 changes the bridge to PMC site 1 into reverse mode This allows configuration transactions to be forwarded from PMC site 1 to the processor to allow programming of the Flash from a PMC 5 7 2 PCI Bus to VME Bridge The Tsi148 PCI X to VME Bridge is connected to a PEX8114 PCIe to PCI Bridge via a 64 bit PCI X bus running at 133 MHz The device number mapping for the VME PCI bus is as follows Table 5 9 VME PCI Mapping Device IDSEL Function 0 16 Tsi148 VME Bridge 1to7 17to23 Notimplemented 8 24 PEX8114 Bridge 9to15 25to31 Notimplemented Publication No SBC610 OHH 2 Functional Description 47 5 7 3 PCI Bus to AFIX USB and SATA The AFIX site
113. errupt mask 26 Watchdog 0 interrupt mask 27 Watchdog 1 interrupt mask 28 AXIS Message Queue 0 interrupt mask 29 AXIS Message Queue 1 interrupt mask 30 AXIS Message Queue 2 interrupt mask aL AXIS Message Queue 3 interrupt mask 6 16 Board Interrupt Core 1 INT Mask Register Offset 0x4014 A set bit enables an active interrupt from the corresponding device to drive out the 8641D IRQ9 interrupt The bit allocation is as for the Board Interrupt Core 0 INT Mask Register Publication No SBC610 OHH 2 Control and Status Registers 95 6 17 Board Interrupt Core O MCP Mask Register Offset 0x4018 A set bit enables an active interrupt from the corresponding device to drive out the 8641D machine check interrupt to Processing Core 0 The bit allocation is as for the Board Interrupt Core 0 INT Mask Register 6 18 Board Interrupt Core 1 MCP Mask Register Offset 0x401C A set bit enables an active interrupt from the corresponding device to drive out the 8641D Machine Check Interrupt to Processing Core 1 The bit allocation is as for the Board Interrupt Core 0 INT Mask Register 6 19 PCI Express Block Configuration Register Offset 0x5000 This register contains details of the configuration of the PCI Express block This region is intended to be accessible from the PCI Express backplane allowing external boards to interrupt the local processors and lock shared resources Table 6 16 PCI Express Block Configuration Register Bits Description
114. ers for USB1 1 operation and one EHCI controller for USB2 0 operation Alternate ports use a different OCHI controller for USB1 1 operation and all ports share the EHCI controller for USB2 0 operation The internal functions are configured as follows Table 5 16 EHCI Internal Functions Controller PCI Function No Interrupt SBC610 Connection OHCIO 0 INTA USB ports 1 3 and 5 OHCI1 1 INTB USB ports 2 and 4 EHCI 2 INTC USB ports 1 to 5 Two USB ports ports 1 and 2 from the USB device are available on the P4 connector as follows Table 5 17 USB1 USB2 Signal Availability Signal Di Pin Signal P4 Pin USB1 P A9 USB2 P D9 USB1_N B9 USB2 N E9 USB1 PWR B10 USB2 PWR C10 Ports 3 to 5 are routed to the AFIX P41 connector to accommodate USB AFIX modules such as the AFIXM or may be routed to the P6 connector if a module with appropriate I O routing such as the AFIXDIOT is fitted to the site Table 5 18 USB3 to USB5 Signal Routing Signal P41 Pin Signal P41 Pin Signal P41 Pin USB3P G7 USBA P G10 USB5_P 619 USB3N G8 USBAN G11 USB5_N G20 5 12 SATA A Silicon Image Sil3512 device is used to provide two SATA ports from the SBC610 supporting Generation 1 transfer speeds of 1 5Gbits s The device is connected to a 32 bit 33 MHz PCI bus The SATA ports are available on the P4 connector as follows Table 5 19 SATA Signal Availability Signal P4 Pin Signal P4 Pin SATAO TXP A7 SATA1 TXP B8 SATAO TAN B7 SATA1 TAN C8 SAT
115. es have been modified according to the ANSI VITA51 1 Specification These failure rates are based only on the components and connectors fitted to the board at delivery and take no account of user fitted mezzanines A 5 Mechanical Specification A 5 1 Dimensions The air cooled SBC610 is constructed on a multi layer 6U Eurocard and conforms to the dimensions specified in IEEE1101 1 The conduction cooled SBC610 is constructed on a multi layer 6U Eurocard and conforms to the dimensions specified in IEEE 1101 2 A 5 2 Weight The typical weight varies with build level and processor type copper heatsinks are fitted for faster boards at higher build levels as follows Table A 7 Weight Processor Variant Build Level 1 Build Level2 Build Level 3 Build Level A Build Level 5 2 7229 11899 11899 6989 12469 4 722g 722g 1189g 698g 12469 5 722g 722g 1189g 698g 698g 7 722g 722g 1189g 698g 698g See the Product Codes section for more details on the Processor Variant Codes Publication No SBC610 0HH 2 Specifications 129 A 6 Product Codes Table A 8 Product Options SBC610 X X X X X X X X X Mechanics 1 0 8 pitch VITA 46 2 0 85 pitch VITA 46 3 1 pitch VITA 46 6 1 pitch VITA 48 A 0 8 pitch VITA 48 2LM B 0 85 pitch VITA 48 2LM C 1 pitch VITA 48 2LM o AFIX fitted X1553 single channel X1553 dual channel XSG 8 bit SCSI and Graphics XSG 16 bit SCSI and Graphics X1553 single channe
116. ess Doorbell Clear Register o od 98 Table 6 20 PCI Express Doorbell Status Register inc ices neato occa ae aie cca ie aes nen Coan eat 98 tel E ie gea ee 99 Table 6 22 Semaphore e Ee E 99 Td Ra 100 Toble 6 24FFO Status Ee aca isla ATA Ai 100 el E le Eet DEIN RN ABBA NM EA MEAM DR eM 100 Table 7 1 Connector RHBEBOPIS EE 102 Table 7 2 PO Pirt Assignments ee SEEN O O S gt S RERUM 103 TIBERIO PANAS ll O O epe 103 TAELA PA A dedo e 104 Publication No SBC610 OHH 2 List of Tables 13 Table 7 5 J1 Pin C cuc SES en RES UM REQURN ED An m EL NEM E UAE 104 Table 7 6 P2 Pin RS SUCHIN DES SIR REVERSUS USO aii 105 Table 7 7 e lee sco us SERRA UND RUNDE IDA MAMMA MEI MEME 105 TEA Ee Wi 106 TOig reds PI ASSIM A 107 Table 7 10 P4 PIN ASIAN Aaa 108 A A E HER 108 Table VARESE NES ad 109 e EIERE ee Eer 110 Table 7 14 P6 Pin EE 111 A E EE 111 Table 7 16 Backplane Connector Signal Definitions A NEE 112 Table 7 17 411 32 EES 115 Table T8 1121122 Eeler 115 Table 7 1 915 123 P in ASOMO Aa 116 Table 7 20 114 A RU Mu AUS 116 Tapie 21 PMC Signal Desc pios EE 117 ee 118 Table 7223 J16 J 26 Re E 119 ee 120 Table 7 25 P41 Pin ASSIgNMENtS S tete dip nU OR RT ORA DNO MUNDO UM DO UE 121 Table 7 26 AFA Signal eer EE 122 Table 7 27 coe RARO ORA RAO AC UEM E EE NE EE MEE E 123 tele Eet IT e 123 Table 7 29 P22 PIMASSIOAM ENTS o scie d E uses e ME 124 Telble 0 P22 Signal Re le 124 Tobis Re an O udin edi oU 125 Table Al Technical DOR E 126 Table A 2 Voltag
117. ess lane connected to backplane port 4 4 DS337 Green PEX8518Lane14Good This PCI Express lane connected to backplane port 4 lane 3 is active DS338 Green PEX8518 Lane 15 Good This PCI Express lane connected to backplane port 4 lane 4 is active DS339 Red PEX8518 Fatal Error A fatal error has occurred has been detected by the PEX8518 switch 82 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 25 Air cooled Front Panels Build Levels 1 to 3 Figure 5 12 Air cooled Front Panels Publication No SBC610 OHH 2 Y Se Deg e Hu J l o 1inch pitch VITA 48 Ed o 00000 Deg o j l o E 1inch pitch VITA 46 2 n eo O0 E Deg o Jl l o E 0 8 inch pitch VITA 46 5 25 1 PMC Slots The SBC610 front panel has provision for front I O from both PMC XMC sites If PMCs have not been ordered as part of an assembly with the SBC610 then GE will fit a blanking plate in the slot s for EMC protection If you are fitting a non GEIP PMC it must comply with the standard for air cooled mezzanines to ensure that it mates correctly with the SBC610 mechanics GEIP PMCs comply with this standard If you are fitting a PMC yourself before fitting the module remove the corresponding blanking plate from the desired PMC slot The PMC s bezel should fill the slot
118. evices used on the SBC610 are not guaranteed to remain fixed in the future Hardware should be accessed only through mechanisms provided by the Operating System s Board Support Package and not directly by application software If a standard operating system is not being used then it is recommended that applications are written in such a way as to minimize direct access to hardware resources bearing in mind that changes may be necessary to support future iterations of the hardware GEIP supported Operating Systems guarantee compatibility at the application level through hardware independent mechanisms 5 1 Features e Freescale MPC8641D Integrated Host Processor with dual processing cores at 1 33 GHz e Up to 4 GBytes of dual channel DDR2 SDRAM with ECC e Uptol1 GByte of Flash memory with enhanced write protection features e 128 KBytes of Non Volatile RAM with power down AutoStore e PCI Express board interconnect with non blocking switch architecture e Two mezzanine sites supporting PMC and XMC modules Each PMC interface has a 64 bit PCI PCI X interface and can operate at up to 133 MHz Each XMC interface has a x8 PCI Express link e AFIX site accommodating the GEIP range of AFIX expansion modules e Up to four x4 Serial RapidIO backplane ports operating at up to 3 125 GHz e Up to eight lanes of PCI Express backplane ports operating at 2 5 GHz e VME64x interface with 2eSST support e Two 10 100 1000Base T Ethernet ports e Six
119. for the first time leaving your board in the default configuration will enable board operation to be proven before tackling any further configuration issues 3 3 1 Core O Boot Area Selection Links E12 and E14 The Boot Flash for Processing Core 0 is divided into four sections allowing for three different boot images to be loaded into the Flash There is also a factory programmed Recovery boot image These links are used to select which image is used at boot time Table 3 1 E12 and E14 Link Settings E12 Fa Active Boot Image Out Out Main In Out Alternate Out In Recovery In In Extended In normal operation these links are not fitted and the SBC610 boots from the Main boot image The active boot image may also be affected in a deployed system using the BOOT SWAPO backplane input see the Boot Flash section 22 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 3 3 2 Core 1 Boot Area Selection Links E13 and E14 Processing Core 1 may boot either from the same Flash image as Processing Core 0 or from its own Boot Flash which is divided into four sections allowing for three different boot images along with the factory programmed Recovery boot image These links are used to select which of the Core 1 boot images is used at boot time if selected Table 3 2 E13 and E14 Link Settings E P Active Boot Image Out Out Main In Out Alternate Out In Recovery In In Extended In
120. ge 5 17 9 Board Management Microcontroller The SBC610 contains a Board Management Microcontroller BMM which provides a proprietary mechanism to share of BIT results between boards in a system and remote monitoring of board status The BMM is connected to a backplane PC Serial Management bus using the SM CLK and SM DATA connections on the PO connector which is bused between all slots in the system The BMM on each board is addressed based on its Geographic Address as shown in the table below These are the 7 bit device addresses Table 5 32 BMM Address Allocation Slot GA 4 0 12C Address Slot GA 4 0 12C Address Slot GA 4 0 12C Address 1 11110 0x68 8 10111 Ox6F 15 10000 0x77 2 11101 0x69 9 10110 0x70 16 01111 0x78 B 11100 0x6A 10 10101 0x72 17 01110 0x79 4 11011 0x6B 11 10100 0x73 18 01101 0x7A 5 11010 0x6C 12 10011 0x74 19 01100 0x78 6 11001 0x6D 13 10010 0x75 20 01011 0x7C 7 01010 0x7D 11000 Ox6 14 10001 0x76 21 70 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 The system management pins of both XMC sites are also connected to the backplane Serial Management Bus Their addresses are determined by the three Geographic Address pins generated by the PC DIP Switch device as shown in the table below These are the 7 bit device addresses Table 5 33 XMC Geographic Address XMC GA 2 0 12C Address 000 0x50 001 0x51 010 0x52 011 0x
121. gement features of the processing cores such as the programmable power states Doze Nap and Sleep Dynamic Power Management Instruction Cache Throttling and Dynamic Frequency switching are available to the software within the 8641D No external hardware support is required 5 2 4 MPX Bus The MPX bus connecting the processing cores to the host bridge functions is integrated into the MPC8641D and so is able to run at up to 533 MHz more than twice as fast as an external implementation This gives increased memory bandwidth and reduced latency giving a significant performance increase 5 2 5 Memory Map The SBC610 supports a fully programmable memory map defined by the MPC8641D Memory windows are software configured and the hardware does not carry out any configuration of the memory map For this reason no memory maps are provided in this manual Where addresses are provided in this manual they are stated as a fixed offset from a software programmable base address See the applicable software manuals for more information Publication No SBC610 OHH 2 Functional Description 57 5 2 6 Local Bus The MPC8461D local bus is a 32 bit multiplexed address data bus which is used to access the following devices on the SBC610 e Local Bus Control FPGA e Register FPGA e I OFPGA e Flash e NVRAM e AFIX local bus To reduce the loading on the local bus the Flash and NVRAM are connected to separate data and address buses created by t
122. he Local Bus Control FPGA 5 2 7 Local Bus Memory Map The MPC8641D local bus controller provides eight chip selects which are allocated to devices as defined in the table below The minimum possible window size is 32 KBytes Table 5 2 Flash Memory Allocation Chip Select Target Device Width Window Size cso Boot Flash 32 bit 16 MBytes cst User Flash 0 32 bit iene ce e CS2 User Flash 1 32 bito e Urin C53 NVRAM 8 bit 128 KBytes Control Status Registers CS4 Poe ue 32 bit 32 KBytes AXIS Registers CS5 AFIX local Bus 8 bit 32 KBytes 1 0 FPGA CS6 ESCC IP Cores 8 bit 4 MBytes External SRAM 1 0 FPGA cs aD MA UE 32 bit 4 MBytes Internal Dual Port RAM GPIO Controller a 16 bit in Redundant Flash mode 38 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 3 RAM 5 4 Flash The MPC8641D contains dual 64 bit DDR2 memory controllers and has the ability to interleave accesses between the two controllers to further increase the available RAM bandwidth The controllers have full ECC error correction support with the ability to detect multi bit errors and correct single bit errors within a nibble The SBC610 provides up to a total of 4 GBytes of SDRAM split between the two memory controllers The following table shows the possible RAM configurations Table 5 3 RAM Configurations RAM per Banks per Total RAM Controler Controller Device Size Bus Speed 2 GBytes 1 GByte 2 64Mx8 266 MHz 4 GBytes
123. i LINK_B_L2_RXP LINK B L2 RX GND LINK B L2 TXP LINK B L2 TX GND JTAG AUTOWR 8 GND LINK B L5 RXP LINK B L3 RX GND LINK B L3 TXP LINK B L3 TX GND 9 LINK C LO RKP UNK C LO RX GND LINK C LO TXP LINK C LO TX GND PSU SEQ IN 10 GND LINK C L1 RXP LINK C L1 RX GND LINK C L1 TXP LINK C L1 TX GND 11 LINK C L2 RKP LINK C L2 RX GND LINK C L2 TXP LINK C L2 TX GND PSU SEQ OUT 12 GND LINK C L5 RXP UNK C L3 RX GND LINK C L5 TXP LINK C L5 TX GND 3 LINK D LO RKP LINK D LO RX GND LINK D LO TXP LINK D LO TX GND AXIS TIMER CLK 4 GND LINK D L1 RXP LINK D L1 RX GND LINK D L1 TXP LINK D L1 TX GND 5 LINK D L2 RXP LINK D L2 RX GND LINK D L2 TXP LINK D L2 TX GND AXIS TIMER RST 6 GND LINK_D_L3 RXP LINK D L5 RX GND LINK D L3 TXP LINK D L3 TX GND a This pin is reserved in VITA4 6 0 An option is provided to disconnect it from the backplane 7 1 4 Backplane J1 Table 7 5 J1 Pin Assignments Fin A B C D E F G H 1 NK ALORXP LINK A LO RAN GND GND LINK A LO TP LINK A LOTXN GND GND N C RSVD 2 GND GND LINK A LL pap LINKALIRXN GND GND LINK A LITXP LINK ALITXN GND 3 LINKAL2 RXP LINKA L2 ENN GND GND LINK A L2 TXP LINK A L2 TXN GND GND VBAT 4 GND GND NK AL BNP LINKA L3 RAN GND GND LINK A L3 TXP LINK A L3 TXN GND 5 NK B LO RXP B LORXN GND GND pp Ip U
124. ice Table 6 14 Board Interrupt Status Register Bits Oto 14 Description Reserved JS 16 PCI Express Doorbell 3 status PCI Express Doorbell 2 status 17 PCI Express Doorbell 1 status 18 PCI Express Doorbell 0 status 19 RTC interrupt status 20 Temperature interrupt status 21 Temperature Critical interrupt status 22 23 Ethernet PHY1 interrupt status Ethernet PHY3 interrupt status 24 PEX8548 interrupt status 25 151578 interrupt status 26 Watchdog 0 interrupt status er 28 Watchdog 1 interrupt status AXIS Message FIFO A interrupt status 29 30 AXIS Message FIFO B interrupt status AXIS Message FIFO C interrupt status 31 AXIS Message FIFO D interrupt status 94 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 6 15 Board Interrupt Core O INT Mask Register Offset 0x4010 A set bit enables an active interrupt from the corresponding device to drive out the 8641D IROS interrupt Table 6 15 Board Interrupt Core O INT Mask Register Bits Description Oto14 Reserved 15 PCI Express Doorbell 3 mask 16 PCI Express Doorbell 2 mask 17 PCI Express Doorbell 1 mask 18 PCI Express Doorbell 0 mask 19 RTC interrupt mask 20 Temperature interrupt mask 21 Temperature Critical interrupt mask 22 Ethernet PHY1 interrupt mask 23 Ethernet PHY3 interrupt mask 24 PEX8548 interrupt mask 25 TS1578 int
125. ies are within specification and the other four are software programmable and are used to reflect the status of BIT or other software See the LEDs section for more details 5 26 5 Switches There are no switches on the conduction cooled front panel although external reset inputs are available on the backplane connectors 84 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 De Control and Status Registers The SBC610 provides numerous registers for software to control or read the status of the board All registers are accessed using Local Bus Chip Select 4 are configured as 32 bit wide and must be written as a 32 bit word The following table gives the locations of the registers offset from the Chip Select 4 base address which is configured by software and access to the register Table 6 1 Control and Status Registers Register Offset R W Register Offset R W Register Offset R W Board ID 0x0000 RO Board Semaphore 9 0x0060 R W PCle Scratch 2 0x5024 R W Address 0x0004 RO Board Semaphore 10 0x0064 R W PCle Doorbell Assert 0x5030 WO Board Frequency 0x0008 RO Board Semaphore 11 0x0068 R W PCle Doorbell Clear 0x5034 WO Board Configuration Ox000C RO Board Semaphore 12 Ox006C R W PCle Doorbell Status 0x5038 RO Link Status 0x0010 RO Board Semaphore 13 0x0070 R W AXIS Timestamp Low Value 0x6000 RO Control 1 0x0014 R W Board Semaphore
126. igh speed rear I O Expansion capabilities are further extended with the addition of an AFIX module connector This proprietary interface is intended to allow additional functionality such as MIL STD 1553 or Graphics to be added to the host card without taking up a mezzanine site The SBC610 couples familiar software interfaces and reliability with high speed fabric interfaces offering significant increases in inter board bandwidth Figure 1 1 SBC610 General View 16 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 1 1 Safety Notices The following general safety precautions represent warnings of certain dangers of which GE Intelligent Platforms GEIP is aware Failure to comply with these or with specific Warnings and or Cautions elsewhere in this manual violates safety standards of design manufacture and intended use of the equipment GEIP assumes no liability for the user s failure to comply with these requirements Also follow all warning instructions contained in associated system equipment manuals AM WARNINGS Use extreme caution when handling testing and adjusting this equipment This device may operate in an environment containing potentially dangerous voltages Ensure that all power to the system is removed before installing any device To minimize shock hazard connect the equipment chassis and rack enclosure to an electrical ground If AC power is supplied to the rack enclosure the power jack and mat
127. ing plug of the power cable must meet IEC safety standards 1 1 1 Flammability The SBC610 circuit board is made by a UL recognized manufacturer and has a flammability rating of UL94V 1 1 1 2 EMI EMC Regulatory Compliance N CAUTION This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to EMI if not installed and used in a cabinet with adequate EMI protection The SBC610 is designed using good EMC practices and when used in a suitably EMC compliant chassis should maintain the compliance of the total system The SBC610 also complies with EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC Air cooled build levels of the SBC610 are designed for use in systems meeting VDE class B EN and FCC regulations for EMC emissions and susceptibility Conduction cooled build levels of the SBC610 are designed for integration into EMC hardened cabinets boxes Publication No SBC610 OHH 2 Introduction 17 1 1 3 Cooling A CAUTION The SBC610 requires air flow of at least 300 Ifm for build levels 1 and 2 and at least 600 Ifm for build level 3 If a conduction cooled level 4 or 5 SBC610 is operating on an extender card it requires air flow of at least 300 Hm across it and careful monitoring of board temperatures 1 1 4 Handling LN CAUTION Only handle the board by the edges or front panel Figure 1 2 ESD Label Present on Board Packaging
128. interrupts from all PCI devices and mezzanines and routes them directly to the interrupt controller via the Register FPGA bypassing the fabric altogether The MPC8641D PCI Express Root Complex generates internal interrupt signals equivalent to INTA to INTD to the Interrupt Controller which are shared with external interrupt signals INTA with IRQO INTB with IRQ1 etc Mapping the individual device interrupts to the correct external signals allows this mechanism to appear transparent to software This mapping must account for rotation due to the device number of both the switch port and the device on the PCI bus The mapping used is shown in the table below 76 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Table 5 35 PCI Interrupt Rotation nterrupt PEX8518 Device Device Interrupt to MPC8641D IRQ Pin Mapping Source Port Number IROA IRQ B IROC IRQ 3 PMC1 13 8 IRQ 1 IRQ 2 IRQ3 IRQ O PMC2 2 8 IRQ 2 IRQ 3 IRQ O IRQ 1 VME 14 0 IRQ 2 IRQ 3 IRQ O IRQ 1 USB 1 1 IRQ 2 IRQ3 IRQ O SATA 1 2 IRQ 3 AFIX 1 3 IRQ O IRQ 1 IRQ 2 IRQ3 5 21 8 Board Interrupts See the Board Interrupt Status Register and the Board Interrupt Core INT Mask Register for more details 5 22 Power Sequencing 5 22 1 On board Sequencing The SBC610 uses a Lattice ispPAC Power Manager device to sequence the power supplies in the required order for on board devices The Power Manager also monitors the backplane supply voltages and shu
129. is a Virtex 4 device connected to the MPC8641D local bus which contains an IP core based on the Zilog 85230 Enhanced Serial Communications Controller ESCC Each channel supports asynchronous and synchronous communication with features providing support for SDLC and HDLC protocols Data is transferred between the IP core and dual port RAM within the FPGA by dedicated DMA engines allowing for increased throughput and reduced processor loading The FPGA provides additional Baud Rate Generation capabilities over the original Zilog Z85230 device meaning that a greatly improved range and resolution of baud rates is available The serial ports are driven by ISL41334 bus transceivers and can be configured by software to operate in RS232 RS422 or RS485 modes In RS485 mode the serial controller is able to automatically disable the transmit buffer after transmission is completed The serial ports are intended only to be used by GEIP software drivers See the relevant software manual for details The following COM3 and COMA signals are available through the P5 connector under certain I O configuration options Table 5 14 COM3 4 Serial Port Signal Set RS232 Mode RS422Mode Input Output P5 Pin RS232 Mode RS422 Mode Input Output P5 Pin COM3TXD COM3 TXA Output AS COM4 TXD COMA TX A Output A9 NotUsed COM TXB Output B5 NotUsed COMA TXB Output B9 COM3 RIS COM3_RTSA Output B6 COM4 RTS COM4
130. is needed to complete a VMEbus transaction All VMEbus slave write transactions are posted Write data is queued in the write buffer until the PCI bus is available for the data to be transferred The transaction is immediately acknowledged on the VMEbus VMEbus slave Read Modify Write transactions are accepted but cannot be completed as indivisible cycles on the PCI bus as the PCI LOCK signal is not support Publication No SBC610 OHH 2 Functional Description 65 5 16 4 VMEbus Master Block Transfers DMA The Tsi148 has two independent DMA controllers which may be used to transfer data between the PCI and the VMEbus The controllers support 32 or 64 bit burst transfers on the PCI bus and 16 32 or 64 bit transfers on the VMEbus The DMA controllers support both direct and linked list operation modes All DMA operations are passed through buffers in the DMA controller 66 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 17 12C Buses The MPC8641D provides two PC buses Figure 5 8 I C Architecture Memory Memory TSI578 24LC256 Channel 1 Channel 2 Serial TSI578 EEPROM EEPROM RapidlO Configuration read only read only Switch EEPROM IC Bus 2 MPC8641D PEX8548 DS1682 ee PEX8518 PCI Express Elapsed Time AFIX site Set PCI Express Switch Indicator ache Switch FC Bus 1 X 24LC256 MPC8641D Configuration EEPROM LM92 Ambient Temperature Sensor RX8581 Real Time Clock
131. l with side band signals X1553 dual channel with side band signals XM 1GB Flash Memory co S 8 AFIXM GB Flash Memory o AFIXDIO1 Discrete 1 0 e MN A AFIXDIOT USB 3 4 and 5 Routing 9 3 VxWorks SS 4 BIT VxWorks g 5 U Boot D 6 BIT U Boot 1 PMC2 1 0 1 64 XMC2 1 0 12d P56 P64sX12d 2 PMC2 1 0 1 9 11 XMC2 1 0 Full P56 X20d385 A PMC2 1 0 1 16 COM 3 4 5 6 XMC2 1 0 12d B PMC2 1 0 1 48 COM 5 6 XMC2 1 0 12d PMC1 XMC1 I O Options 3 1 PMC11 0 1 64 XMC1 I O 12d P56 P64sX12d E 2 PMC1I 0 1 9 11 XMC11 0 Full P34 X20d38s _ E 2 512MBytes 2 D 3 1GByte w S 2 26GBytes D 4 46GBytes 2 8641D O 1 333 GHz 428641 01 333 GHz 5 8640D O 1 067 GHz 7 8640 1 067 GHz 1 Level 1 2 Level 2 3 Level 3 4 Level 4 5 Level 5 The default product code is SBC610 x23211xx where X value range shown Ruggedization Level 130 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 A 7 Software Support GEIP s software strategy allows fully integrated system level solutions to be realized easily and with confidence Off the shelf layered software modules deliver the most from low level hardware features while exploiting the best high level debug and run time functionality of popular COTS operating systems and communications modules The software products described below build on those available for previous generations of products so providing a common interface for t
132. lectrical anie treten reip Re 128 Environmental seen 127 Mechanical ada ai 126 Technical sais 126 SO ad 57 Storage Environment 127 System Controller rtt 64 System ROM iiandda atan SERRE 39 T Technical Help Contact Details 6 Technical Specification ses 126 Temperature Sensors 68 NEED tien 73 U WPA in Be qiero oe enn 19 USB cei iei n diede i ates 53 User Flash nrbi deiecit es 41 138 SBC610 6U VPX Single Board Computer V Vibration censeret n ne et es 127 VMEbus Compliance iei itte et nnd 64 A ie o 66 Interface 64 Master Po c E E AT M 65 Block Transfer 66 PCI VME bridge ete 64 Slave ACCESS uc aoi e pe a e d 65 Volatility Statement sss 133 Voltage Supply Requirements 128 W Warnings 17 Watchdog Tmerg EE 73 Websites ee rane pr HN 5 Weight iiiter mieten tane 126 X XM CO eir EE EEEE ii 59 CONMECLOLS ereire ies rie aere e RETE eren n 118 Tris tala th Maat ettet tee ar ein 28 Routing udine eret t t ne er UA eerte iud 59 Signal DeScriptiOns sss 120 Mortalidad 59 Publication No SBC610 0HH 2 O 2012 GE Intelligent Platforms Embedded Systems Inc All rights reserved All trademarks are the property of their respective owners Confidential Information This document contains Confidential Proprietary Information of GE Intelligent Platforms Inc and or its suppliers or vendors Distribution or reproduction prohibited withou
133. lers VME System Controller status can be read from the Address Register 5 16 1 VMEbus Compliance Table 5 28 VMEbus Compliance A16 A24 A32 and A64 DO8 EO D16 and D32 Single Cycle Transaction SCT DO8 EO D16 and D32 Read Modify Write Transaction RMW Master D16 and D32 Block Transaction BLT D64 Multiple Block Transaction MBLT D64 2eVME D64 2eSST A16 A24 A32 and A64 DO8 EO D16 and D32 Single Cycle Transaction SCT DOB8 EO D16 and D32 Block Transaction BLT Slave D64 Multiple Block Transaction MBLT D64 2eVME D64 2eSST IH 1 7 Interrupt Handler oa D16 D32 1 1 7 Interrupter D080 VMEbus Arbiter SGL RRS PRI VMEbus Requester ROR RWD FAIR Bus Time out Module Disable 8 16 32 64 128 256 512 1024 2048us IACK Daisy Chain driver Other Slot 1 Functions SYSCLK Driver First Slot Detector Auto Slot ID VME64 specified mode or Geographical Addressing via five row P1 connector 64 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 16 2 VMEbus Master Access Eight software programmable PCI target images are available for master accesses to the VMEbus An offset may be applied to translate the local address to a different address on the VMEbus allowing access to any VMEbus address VMEbus master read cycles use delayed transactions Delayed transactions are used to free the PCI bus from waiting for the potentially long VMEbus arbitration and transf
134. link to a different part of the same document Numbers All numbers are expressed in decimal except addresses and memory or register data which are expressed in hexadecimal Where confusion may occur decimal numbers have a D subscript and binary numbers have a b subscript The prefix 0x shows a hexadecimal number following the C programming language convention Thus One dozen 12 0x0C 1100 The multipliers k M and G have their conventional scientific and engineering meanings of 103 106 and 10 respectively The only exception to this is in the description of the size of memory areas when K M and G mean 21 2 and 29 respectively Le NOTE When describing transfer rates k M and G mean 103 106 and 10 not 219 220 and 230 In PowerPC terminology multiple bit fields are numbered from 0 to n where 0 is the MSB and n the LSB PCI and VME terminology follows the more familiar convention that bit 0 is the LSB and n the MSB Text Signal names ending with a tilde denote active low signals all other signals are active high N and P denote the low and high components of a differential signal respectively Publication No SBC610 OHH 2 About This Manual 5 Further Information GE Intelligent Platforms Documents This document is distributed via the internet You may register for access to all manuals via the website whose link is given
135. mers Programmable interrupt and reset thresholds RTC Time Of Day Calendar 1 second resolution Standby power may be connected from the VBAT pin to maintain data during power down Logs the total accumulated time the board has been powered and the number of power ETI Quarter second resolution Cycles JTAG interface 126 SBC610 6U VPX Single Board Computer On card connectors JTAG headers provided for factory test and software debug purposes Publication No SBC610 0HH 2 A 2 Electrical Specification A 2 1 Voltage Supply Requirements The VPX VS3 5V and P3V3 AUX supplies are required and must remain within the specified limits as defined below If either of these supplies is outside of these specifications at power up then the SBC610 will fail to start If these supplies fall outside of these limits during a powered state then the SBC610 will be held in reset and all on board supplies will be shut down The VPX VS1 and VS2 supplies are not used The VPX 12V AUX supplies are not used on the SBC610 but are connected to the PMC XMC and AFIX sites Table A 2 Voltage Supply Requirements Supply Minimum Nominal Maximum VS3 4 88V 5 0V 5 25V P3V3 AUX 3 14V 3 3V 3 46V P12V AUX 114V 12 0V 12 6V N12V_AUX 114V 12 0V 12 6V VBAT 1 8V 3 3V 5 5V A WARNING Do not exceed the maximum rated input voltages or apply reversed bias to the assembly If such conditions occur toxic fumes may be produced due to the
136. nd 1 respectively Table 6 12 Watchdog Control Registers Bits Description Notes 0 Watchdog enabled Watchdog od 1 Watchdog disabled 0 Watchdog not expired 1 Watchdog expired 1 Watchdog counter expired reset 0 Watchdog interrupt inactive e ll 1 Watchdog interrupt active 3 Reserved 0b 4and5 Service Watchdog Write 01 followed by 10 to these bits to service the Watchdog 6and7 Enable Watchdog Write 01 followed by 10 to these bits to enable disable toggle the Watchdog Bits 8to 31 of the value loaded by the Watchdog counter whenever it is enabled or serviced 8to31 Counter presetvalue Bits 0 to 7 are always OxFF a Read only 6 13 Watchdog 0 Interrupt Value Register Offsets 0x2004 and Watchdog 0 Interrupt Value Register Offsets 0x2014 These registers set the count value when an interrupt is generated for Watchdog 0 and Watchdog 1 respectively Table 6 13 Watchdog Interrupt Value Registers Bits Description Notes Oto7 Reserved 0x00 81031 Interrupt Threshold Bits 0 to 23 of the count threshold at which an interrupt is generated to the interrupt controller Bits 24 to 31 are always 0x00 Publication No SBC610 0HH 2 Control and Status Registers 95 6 14 Board Interrupt Status Register Offset 0x4000 This reflects the status of all on board non PCI interrupt inputs to the Register FPGA A set bit indicates an active interrupt from the corresponding dev
137. ndividually soft reset by software using the Processor Core Initialization Register within the MPC8641D interrupt controller Publication No SBC610 0HH 2 Functional Description 75 5 21 5 System Management Interrupt SMI An SMI interrupt to the processing cores can only be generated by asserting the external SMIO or SMI1 pins on the MPC8641D These pins are unused on the SBC610 5 21 6 External Interrupt INT The processing core external interrupt pin INT is asserted for a pending interrupt from the interrupt controller in the MPC8641D The MCP8641D interrupt controller supports routing of internal and external interrupt sources to one of the two processing cores including programmable priority levels All interrupt routing between source and the processing cores is established by software Figure 5 10 SBC610 Interrupts 1 0 FPGA Internal Interrupt Int Sources e Ei GPIO Controller d zh Interrupt Controller Register FPGA PCI Interrupts Internal Interrupt Sources MPC8641D Board Interrupts Interrupt Controller m 5 21 7 PCI Interrupts PCIe provides a mechanism for passing interrupts from legacy PCI devices through the PCIe fabric to the interrupt controller at the Root Complex using Assert_INTx and Deassert_INTx messages These messages are however subject to the same latency and non determinism as any other PCIe packet To reduce this latency the SBC610 takes the
138. ngle Board Computer Publication No SBC610 0HH 2 5 Functional Description continued 5 17 14G BUCS c M SINNE RESET aneia AA NAE RE a A On UNEA EE 5 17 2 Addressing 5 17 3 Real Time Clock 5 17 4 Elapsed Time Indicator 5 17 5 Temperature Sensors 5 17 6 Power Manager 5 17 7 12C DIP Switch 5 17 8 MPC8641D Configuration EEPROM 5 17 9 Board Management Microcontroller oder M CR p aided rd eA Qe Hte cde d P UR TRE 5491 Woatchdog TIilriers cs Ete t Ree de UR RR RO e UNE E dnd EAR Ee E 5 21 Resets Interrupts and Error Reporting AN 74 pe EL lee 5 2 T 2 SYSRESE A ce ERE ER REIR ERREUR IAS EUR RR REN UR RE EE RES 5 21 3 Machine Check Exception 5 2 14 SOTUReSOL ce eee 5 21 5 System Management Interrupt JEM 76 5 21 6 External Interrupt INT 5 21 7 PCI Interrupts niisiis 5 21 8 Board Interrupts 5 22 Power Sequencing 5 22 LONDON pte t deo tle p tte dated bs atento dee een n d td 5 22 2 Inter board sequencing 5 22 3 Nucle dr Event Detection s ttr e eoe b e E O e e eee et 78 A eie tbe entree dee dae iita htec e ie i d denter 78 ben EDS mer eU MM P M MN 79 5 24 1 Ethernet Link Status LEDs DS301 da eet 80 5 24 2 BIT LEDs DS313 to DS316 5 24 3 Power Good LED DS317 524 re RE RE 5 24 5 PCI Express Link Status EEDS DS320 to DS328 stet eei teh etl ete e RS
139. ocal Bus SUN TER ER D MMC C SANIR E1310 a meses EE I M M TA A AE AIME SE ELSE 5 4 2 User Flash 5 4 3 MAC Address Mirror MOG i er tercie ee Bia 4 Paged Fash Mone nkore ioes ee ettet ON 5 4 5 Redundant Flash Mode 5 4 6 Flash Sector Protection 5 5 Non Volatile RAM NVRAM cc aan Re irersiqUauU rcd M a 5 6 L PGIEXxpress PoweriMandgerrient s s e ee E dp tbe ete eite Ue dt 44 5 6 2 MPC8641D Sous Ee sre ecco M 5 6 4 PCleto jPclBridge ss te ete ete e e NI edet NR IEN 57 X PCI B sesS bor PME ee ete e e RR i b t E te bee cedo 5 7 2 PCI Bus to VME Bridge 5 7 5 PCI Bus to AFIX USB and SATA EE pe DEE 5 10 Serial Communication Portes 5 10 heel Elle O OM EE AO Gelle Kee EE 5 10 3 COM5 and COM6 Gs ERT E A o gs iia 5 IA Off Board Serna e ele 5 l4 DE A 5 142 Serda Rapid Oesen rtt eet E ER Oe st P RE e ERU ER ERREUR EE 515 MeZZGtllies eet A utu ient editae delete ettet eg lee 5 15 2 PCI Mezzanine Cards PMCs 5 15 3 PCI Express Mezzanine Cards XMCs VS AIO el EE 5 15 5 AFIX Site eS EE TE eelere 5 16 2 VMEbus Master Access 516 5 VMEDUS SIAVE SAA eee eere eere ee tere Rete eere eere e NT 5 16 4 VMEbus Master Block Transfers DMA tentent ttt ttt ttt ttt ttt ttt ttt tto scans 66 continued overleaf 8 SBC610 6U VPX Si
140. ode COMn RXD COM1 2 Receive Data input for RS232 mode This signal becomes COMn TX A when either port is used in RS422 mode COMn TXD COM1 2 Transmit Data output for RS232 mode This signal becomes COMn TX A when either port is used in RS422 mode ETHO nN P Gigabit Ethernet channel 0 differential pairs ETH1 nN P Gigabit Ethernet channel 1 differential pairs Publication No SBC610 OHH 2 Connectors 113 Signal Description SATAn RXN P SATA channel n n 0 or 1 Receive input differential pair SATAn TXN P SATA channel n n 0 or 1 Transmit output differential pair USBn N P Universal Serial Bus n n 1 or 2 differential pairs USBn PWR Universal Serial Bus n n 1 or 2 switched power outputs 5V Serial port Clear To Send input A COM5 6 CTS A can alternatively be used as a receive clock input in RS422 mode selected by 1 0 COMn CTS A FPGA Serial port Clear To Send input B COMn_CTS_B becomes DCD in RS232 mode SORTS B COM5 6 CTS B can alternatively be used as a receive clock input in RS422 mode selected by UO FPGA COMn BI A Serial port Receive Timing Clock In input A COMn RT B Serial port Receive Timing Clock In input B Serial port Ready To Send output A COM5 6 CTS A can alternatively be used as a transmit clock output in RS422 mode selected by COMn RIS wore Serial port Ready To Send output B COMn RTS B becomes DTR in RS232 mode SEE COM5 6 RTS B can alternatively be used
141. om For Serial RapidIO Switch and VME Bridge information data NOTE Registration may be required for access to standards h h http www freescale com For MPC8641D processor information h h Publication No SBC610 0HH 2 About This Manual 5 Technical Support Returns Technical assistance contact details can be found on the website Support Locator page The appropriate location is headed DSP SBCs Multiprocessors and Graphics formerly Radstone ON LINK http defense ge ip com support embeddedsupport locator Queries will be logged on the Technical Support database and allocated a unique Service Request SR number for use in future correspondence Alternatively you may also contact GEIP s Technical Support via ON LINK support towcester ip ge com TELEPHONE 44 0 1327 322760 If you need to return a product there is a Return Materials Authorization RMA request form available via the web site Support Locator page ON LINK http defense ge ip com support embeddedsupport locator Do not return products without first contacting the GEIP Repairs facility 6 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Contents A E ee tee 1 1 1 Flammability 1 1 2 EMI EMC Regulatory Compliance ettet ttti ttt ttt ttti 17 ci 1 1 4 Handling He e E ZW VICI e amd 2 BOX Contents ele ee epu I er EE dero e A EE ROMs quaes eio E KE m
142. on VPX VITA46 3 Draft 0 5 Serial RapidIO on VPX VITA46 4 Draft 0 5 PCI Express on VPX ANSI VITA46 9 2010 XMC and PMC User I O Mapping for VPX These are the latest version at time of writing check associated websites for later updates dat NOTE Registration may be required for access to these specifications 4 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Component MPCS8641 and MPC8641D Integrated Host Processor Hardware Specifications Information Freescale Semiconductor MPC8641D Integrated Host Processor Family Reference Manual Freescale Semiconductor PEX8548 Data Book PLX Technology PEX8518 Data Book PLX Technology Tsi578 Serial RapidIO Switch User Manual Tundra Semiconductor Tsi148 PCI X to VME Bus Bridge User Manual Tundra Semiconductor da NOTE Access to these documents may require a Non Disclosure Agreement to be in place with the component vendor Contact the manufacturer for more information GE Website Information regarding all GEIP Mil Aero products can be found on the following website ON LINK http defense ge ip com products family military and aerospace Third Party Websites Manufacturers of many of the devices used on the SBC610 maintain FTP or websites Some useful sites are tp www vita com For VPX VITA 46 standards tp www pcisig org For PCI Bus standards tp www plxtech com For PCI Express Bridge Switch information tp www tundra c
143. on conditions and further prevent oxidation of the connection due to moisture ingress Figure 3 1 Link Positions zs D n n E12 E20 E of uj Elb 1E22 b d E14 E25 n I n 7 T T innnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnl Innnnnnnnnnnnnnnnnnnnnnnnnnnnnnnil 1nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnngn Innnunnnnnnnnnnnnnnnnnnnnnnnnnnnll ES 22 oral rra Barc rra El6 E25 CV Dr eene an Ede Sean occ a DD 0 E ee E E26 ES Ess E18 E27 s Ca ananannnnnnninnn asas ey DUTT IN TOOT LUE EHE TENE OE EN HH NN E JUTTITTTUTUTUUUU UU UT UU TUUUU UU UU UT nnn The diagram above shows standard 2 54 mm pitch headers for general use This manual refers to jumper settings as In or Out Meanings are as follows In jumper fitted Out jumper not fitted 3 Publication No SBC610 0HH 2 Configuration 21 3 2 Inspection The SBC610 is shipped from the factory with no jumpers fitted 3 3 Link Descriptions data NOTES Ordinary operation requires no jumpers to be fitted The state of most of the links can be read from the Link Status Register i TIP If you are about to install your board and power up
144. onal Description 77 5 23 JTAG 5 22 5 Nuclear Event Detection The SBC610 provides the capability to safely crowbar all on board supplies without damage to any on board components to less than 20 of their initial value within 300us of the application of a positive pulse of 12V to the P6 Connector pin G1 This feature is used to prevent the SBC610 from damage during a nuclear event The SBC610 provides JTAG boundary scan facilities for all IEEE1149 1 and IEEE1149 6 compliant devices The JTAG interface is provided by a Firecron JTS06Bu Scanbridge This allows the boundary scan path to be partitioned into smaller chains providing easier fault diagnosis and faster Flash programming The device supports six Test Access Ports TAPs which are allocated as follows Table 5 56 JTAG Access Ports TAP Devices BDM Header MPC8641D processor PEX8548 PCle Switch VME PEX8114 PCIe PCI Bridge Tsi148 PCI VME Bridge PMC1 PEX8114 PCle PCI Bridge PMC2 PEX8114 PCle PCI Bridge AFIX PEX8114 PCle PCI Bridge 88E1111 PHY 1 88E1111 PHY 3 XMC Site 1 PMC Site 1 4 XMC Site 2 PMC Site 2 AFIX Site 5 PEX8518 PCle Switch Tsi578 Serial RapidlO Switch PLD Header Local Bus Control FPGA 6 Register FPGA UO FPGA 1 0 FPGA Configuration PROM I The input to the Scanbridge is driven from the VPX P0 connector The JTAG architecture supports the use of the JTAG Technologies AutoWrite signal to accelerate flash programming via JTAG This signal i
145. overleaf ON LINKS PMC Installation Note publication number HN4 3 99 AFIX Family Product Manual publication number AFIX OHH VPX I O Modules Hardware Reference Manual publication number VPXIOM OHH AXISFlow Programmer s Guide publication number AXISFLOW OHU Radstone Signal Processing Library Manual publication number RSPL OHL Vector Signal and Image Processing Library Manual publication number VSIPL OHL AXISView Applications Software User Guide publication number AXISVIEW OHU NOTE Cross document links are intended for use where the document files are saved under their original file names in the same directory on a server PC hard drive or similar If accessing this document via the GE website cross doc links will not work Third Party Documents Due to the complexity of some of the parts used on the SBC610 it is not possible to include all the detailed data on all such devices in this manual A list of the specifications and data sheets that provide any additional information follows Specifications IEEE 1101 1 1998 IEEE Standard for Mechanical Core Specifications for Microcomputers IEEE 1101 2 1992 Conduction cooled VME mechanics IEEE 1101 10 1996 Additional Mechanical Specifications ANSI VITA 20 2001 Conduction Cooled PMC A A A A NSI VITA 42 0 2008 XMC NSI VITA 42 3 2006 XMC PCI Express Protocol Layer Standard NSI VITA 46 0 2007 VPX Baseline Standard NSI VITA 46 1 2007 VMEbus Signal Mapping
146. owing automatic initialization tests to be defined for the desired mix of system functionality and options Further tests can be invoked interactively giving BIT a valuable role as a field service tool Both object and source code products are available Publication No SBC610 OHH 2 Specifications 151 A 7 3 Background Condition Screening BCS supplements the BIT initialization test coverage with further health screening that can co exist with a standard COTS Operating System In contrast to a traditional BIT style test the intensity and coverage of which makes it destructive to operating systems the configurable BCS package allows functions such as periodic checksumming memory scrubbing and others to be tailored for operation alongside the application in on line conditions Results are stored in Flash in the same format as BIT results Code is available for reading out BIT BCS results under LynxOS and VxWorks A 8 1 0 Modules The Rear Transition Module RTM for the SBC610 is the VPX6UX600 More information about RTMs can be found in the VPX I O Modules manual ON LINK VPX I O Modules Hardware Reference Manual publication number VPXIOM OHH VPX6UX600 Hardware Reference Manual publication number VPX6UX600 0HH 132 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Be Statement of Volatility B 1 Volatile Memory The SBC610 contains volatile memory i e memory in which the contents are lost when power is removed
147. p Select 1 Chip Select 2 processing cores use the same boot area the 1GByte Flash Option 1GByte Flash Option Core 1 Boot Area is used as User Flash Functional Description 41 5 4 3 MAC Address Mirror Mode The Recovery Boot Area is present in User Flash only in the top sector of Flash Bank 0 accessed via CS1 This area also contains the board s serial number and MAC addresses which may be required by Processing Core 1 There is a function to mirror the top sector of Flash Bank 0 to Flash Bank 1 to allow this to be invisible to software This mode is controlled by the Flash Control Register and is enabled by default although it may be disabled as this feature is not desirable in a single processor or SMP mode 5 4 4 Paged Flash Mode Due to limitations on the size of the processor memory map a paged mode is provided where the User Flash area is divided into 128 MByte pages with separate pages selectable for CS1 and CS2 This mode is controlled using the Flash Control Register and is enabled by default with each Chip Select pointing to the top page of Flash Figure 5 5 Flash Paged Access Mode Page No 03 07 11 15 Page No 01 03 05 07 Page No 02 06 10 14 Page No 00 02 04 06 Page No 01 05 Page No 00 04 Chip Select 1 Chip Select 2 512 MByte Flash Option 512 MByte Flash Option These areas should not be accessed when Core 1 is using Chip Select 2 to access them Chip Select 1 Chip Select 2
148. place when a board is power cycled or reset Each Flash sector may be set to be locked write protected or unlocked write enabled by writing to configuration registers within the Flash The configuration of this protection is only possible when the Flash Protection Unlock Link E17 is fitted and the backplane NVMRO signal on connector PO pin A4 is inactive low If these conditions are not met the software is unable to change the sector protection and those sectors that are locked may not be erased or reprogrammed under any circumstances 2 Non persistent protection may also be used In this case sectors locked using Persistent mode may not be erased or reprogrammed but previously unlocked may now be locked However this protection is only present until a power cycle or hardware reset occurs Le NOTE Do not rely on non persistent protection as it may be subsequently altered by software If further protection is required use the Persistent protection method For further details of these protection mechanisms see the S29GL01P 1Gbit page mode Flash data sheet Publication No SBC610 OHH 2 Functional Description 43 5 5 Non Volatile RAM NVRAM The SBC610 has a 128 KByte AutoStore NVRAM for non volatile set up and configuration data storage The NVRAM used is a Simtek STK14CAS which is configured as an 8 bit wide device and is accessed using Chip Select 3 on the Local Bus Controller of the MPC8641D The NVRAM is write protected
149. pt not active interrupt active interrupt not active interrupt active interrupt not active interrupt active interrupt not active interrupt active Publication No SBC610 0HH 2 6 25 AXIS Timestamp Low and High Value Registers Offsets 0x6000 and 0x6004 These registers hold bits 0 to 31 and 32 to 47 respectively of the 48 bit AXIS Timestamp value NOTE Reading the AXIS Timestamp Low Value Register causes the value of the whole timestamp including the high 16 bits to be latched The AXIS Timestamp Low Value Register should therefore always be read before the AXIS Timestamp High Value Register to prevent the reading of stale data 6 26 AXIS Timer Control Register Offset 0x6008 This register contains the control bits for the 48 bit AXIS timer when operating in Master mode Table 6 21 AXIS Timer Control Register Bits Description otes 0to23 Reserved 0x000000 This value determines the frequency of the output clock when in Master mode 3 The clock period is calculated as follows 24to23 Timer Clock Prescaler Period Prescaler 1 Local Bus Clock Period normally 15ns The default is 0x07 nominally a 120ns period This determines the state of the Timer Reset output when in Master mode 30 Timer Reset 0 Timer reset output inactive 1 Timer reset output active 31 Tiner Mater 0 Timer Slave accepts clock and reset 1 Timer Master generates clock and reset 6 27 AXIS Semaphore Registers Offsets 0x6020 to
150. re the value of each of the on board voltage rails as shown below Discrete inputs to and outputs from the device can also be monitored Table 5 30 Power Manager Monitor Points POWR1014A Input Rail Monitored Nominal Voltage VMON1 VCC 5 00V VMON2 P3V3 AUX 3 30V VMON3 P3V3 3 30V VMON4 P2V5 2 50V VMON5 P1V8 1 80V VMON6 P1V5 1 50V VMON7 P1V2 1 20V Rev 1 VBAT 3 00V Optional VMON8 Rev 2 PVDD_PLAT 1 05V 1 05 8641 D VMON9 VCORE 0 95 8640 D VMON10 DIV 1 00 5 17 7 l C DIP Switch The XMC sites each have a 3 bit Geographic Address which is used to access the board information on the System Management bus Due to the number of potential XMC sites in the system this address cannot be derived from the board Geographic Address and must be configured by the user on the sites that are occupied The SBC610 uses a PCA9650 PC DIP Switch device to provide six discrete outputs three to each XMC Site GA from non volatile EEPROM registers within the device These can be configured by the user to suit the system requirements The value of the GA pins is determined by the value of EEPROM Register 0 as shown in the table below Table 5 31 EEPROM Register O Bit Register o C 7 6 5 4 3 2 1 0 XMC XMC XMC XMC XMC XMC EEPROM Register N A N A Site2 X Site2 Site2 Sitel Sitel Sitel GA2 DA GAO GA2 DA GAO The factory default value of all bits in this register is
151. requency MPX Bus Frequency MPC8641D 1333 MHz 533 MHz MPC8640D 1067 MHz 533 MHz The default build of the SBC610 uses the MPC8641D Single processing core and reduced frequency versions of the SBC610 are available for lower power requirements See the Product Codes section 36 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 2 2 Core Interaction The MPC8641D contains two processing cores Following reset Processing Core 1 is prevented from accessing the MPX bus until it is enabled by Core 0 The two processing cores are able to run two different operating systems or two separate instances of the same operating system This is called Asymmetric Multi Processing AMP Mode This mode is aided by the Low Memory Offset Mode of the MPC8641D which is able to apply a 256 MByte address offset to accesses by Core 1 to the bottom of RAM addresses 0x0000 0000 to 0x1000 0000 are offset to 0x1000 0000 to 0x2000 0000 This allows both processing cores to maintain separate stacks and private memory without any software intervention The two processor cores are also able to run a single operating system with tasks divided between them This is called Symmetric Multi Processing SMP mode In this mode the Low Memory Offset feature is not desirable as both processors need to share the same memory space Link E19 can be fitted in this mode to disable the Low Memory Offset feature 5 2 5 Processor Power Management All power mana
152. required for board operation but are used to supply the 12 V pins of the PMC and AFIX mezzanine sites and the auxiliary supplies of the XMC sites The VBAT supply may be used to power the Real Time Clock in isolation when the board is powered down to maintain the time date information This requires up to 1 uA at 3 3 V 15 See the Electrical Specification section for more details 4 2 Board Keying The VPX specification defines three keying pins The keying pin at Position 1 adjacent to the PO connector is used to define the voltage present on the Vs1 and Vs2 supply pins on the backplane JO connector As the SBC610 does not use these supplies the module keying device in this position is of the unkeyed type to allow the board to be fitted to any type of backplane The keying pins at Position 2 adjacent to the P2 connector and Position 3 adjacent to the P6 connector are used to define slot specific keying The SBC610 is delivered with module keying devices of the unkeyed type in these positions to allow the board to be fitted to any backplane slot Contact the factory to discuss any specific keying requirements 30 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 4 3 Board Installation Notes The VPX specification allows for a variety of different backplane pinouts depending on the mix of differential and single ended connectors Take care to ensure that the pinout of the SBC610 matches that of the backplane slot
153. ridge with its own PCI compatible configuration registers Each port is accessed on the internal virtual PCI bus using a device number equal to its port number The port configuration of the switch is initially set up by hardware strapping as follows Table 5 7 PCI Express Switch Port Configurations Port Width Lanes Link To Lane Reversal CO 8 0to7 MPC8641DSerDesPortl No 1 x4 8to 11 AFIX PCle PCI Bridge Yes 2 x4 12to15 PMC2 PCle PCI Bridge Yes 8 x8 16to23 PEX8518 PCI Express Switch Yes 9 x8 24to31 XMCSite1 Yes 12 x8 32t039 XMCSite Yes 15 x4 40 to 43 PMC1PCle PCI Bridge No 14 x4 44to47 VME PCle PCI Bridge Yes Each port is able to negotiate down to smaller link widths if required such as if a fault occurs on any particular lane Port widths of x1 x2 x4 and x8 are supported The PEX8548 also supports the optional PCIe lane reversal feature and the above table highlights where this has been used to aid PCB tracking Where used both the transmit and receive lanes for the link have been reversed Port 0 is connected to the MPC8461D and is usually configured as the upstream port When the Boot Hold off Link E21 is fitted the configuration is changed such that Port 13 is the upstream port This allows configuration transactions to be forwarded from PMC site 1 to the processor to allow programming of the Flash from a PMC Publication No SBC610 OHH 2 Functional Description 45 A serial EEPROM can also
154. robe LOCAL WR AFIX Local Bus Write Strobe LOCAL ADI7 0 AFIX Local Bus Multiplexed Address Data Signals Where this bus is not used the logic levels are set to allow reading of the AFIX board ID AFIX_LINK 1 0 INTER FPGA 3 2 SBC610 links to control AFIX operation connected to E26 and E27 Inter FPGA lines on SBC610 JTAG JTAG interface to AFIX 12C_CLK DATA 12C interface to AFIX USB 3 5 P N USB Port 3 4 and 5 signal pairs to AFIX IRQ D A PCI interrupts GPIO 18 0 GPIO input to AFIX These signals are routed through the AFIX and out on unused I O P41_x pins depending on the AFIX type PSV 5 Volt supply pins P3V3 3 3 Volt supply pins P2V5 2 5 Volt supply pins P12V_AUX 12 Volt auxiliary supply pins N12V_AUX 12 Volt auxiliary supply pins GND Signal Ground N C No Connection 122 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 7 5 BDM Connector P20 P20 is the BDM connector allowing the connection of software debugging tools such as Wind River s VisionProbe or VisionICE using the processor s JTAG port to control the operation of the processor Table 7 27 P20 Pin Assignments Pin Signal Pin Signal 1 JTAG CPU TDO 2 N C QACK 3 JTAG_CPU_TDI 4 JTAG_CPU_TRST 5 NC QREQ 6 43V pull up 7 JTAG CPU TCK 8 CPU CHKSTP IN 9 JTAG CPU TMS 10 NC 11 BDM SRESET 12 N C 13 BDM_HRESET 14 N C KEYWAY 15 CPU CHKSTP OUT
155. s connected to the VPX reserved P1 connector pin G7 and could be disconnected if required The address of the backplane JTAG Scanbridge is derived from the VPX geographic address This is used when operating a bused JTAG system with multiple boards The SBC610 provides a standard BDM header for JTAG access to the 8641D processor The BDM header uses its own isolated JTAG chain A separate FPGA programming header is provided for factory updates to the FPGA code LN CAUTION When using the BDM or FPGA programming headers ensure that the JTAG Scanbridge is disabled link E23 is not fitted 78 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 Mezzanine cards such as PMCs or the AFIX are automatically bypassed using on board buffers when the mezzanine card is not fitted n NOTES The PCI specification requires that if a PMC cannot support JTAG then it must have TDI connected to 5 24 LEDs TDO ensuring that the JTAG chain remains intact The XMC specification VITA 42 0 requires that if an XMC cannot support JTAG then it must have TDI connected to TDO on the XMC and PMC connectors if fitted ensuring that the JTAG chain remains intact It also requires that if both connector sets are present then the XMC connector is used for the JTAG interface and the PMC connector connects TDI to TDO LEDs are mounted on the back of the SBC610 to reflect the status of the following PCI Express links on and off board
156. saausseconevaaasereseceaaassseconcouseeseq ash teareediiaereayreiisaansaarnseeiaeasanrnaeiaansaannneeiaan san nneauaesaennnennnee oe Tee 111 a SA E E 111 ALSO AI ERREUR DA 112 Elle Ee e E 115 E E yt a oe lB E 115 RTR E E 116 Sa RR 117 lee ee 118 7A ta al cce me 118 TEANN SAA S uem m 119 1 35 5 SIOMG DeSCHIDEHOFIS ee ERREUR MEA 120 Te PRS GU Mr E PP 121 LIS eelere lege 122 TS BOM AM eege 123 T6 FPGA Programming Header P22 odisse oo Po n 124 Y PCexpress Mid Bus Probe eeler Ee 125 continued overleaf 10 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 A estu ne eee M te M E S EE A T evel pif ete S DECITIG GUIDE oe oo dd AA Re We LE e E el e m A Ral Mr AMES EE A6 Prod ct O o EE OO E OC KENN RENDUM A T deele ATA a er uo AO A A Ret A 7 3 Background Condition Screening A O A EE NAE Be Statement of VO atlas datada SS LERNTE Publication No SBC610 0HH 2 Contents 11 List of Tables Table 3 1 E12 and NEUE Wo i ec 22 Table 3 2 E15 and ELA Link ne cee eee eee 23 TESEI SETU tt 23 Table 3 4 E15 and E16 Link SEBIDCLS ee res auk aaa 24 Table 3 5 E17 Link Settih a 24 Table 3 6 E18 LINK SEN ser EE 25 Table 3 7 o A OO 25 TARIE SEZ g e EEN 26 TOBE 3 9 E23 LINK SETING sore n HREEVOER DUREE GO A 26 Tale 3 IO E24 Gl E25 EE 26 Table 3 11 E26 and E27 Link e an OR RR pO Ur aer a o dS D
157. serial I O channels two RS232 two RS232 422 485 Async Sync two RS232 422 485 Async only e Up to five USB 2 0 ports e Two SATA disk interfaces up to 1 5 Gbits second e 19 bits of General Purpose I O with interrupt capability e Real Time Clock e Elapsed Time Indicator e Watchdog timers e CPU die and ambient temperature sensors e 6U VPX form factor e Five environmental build levels Publication No SBC610 OHH 2 Functional Description 35 5 2 Integrated Host Processor The SBC610 is based around the Freescale MPC8641D Integrated Host Processor This provides e Dual e600 PowerPC processing cores e Internal MPX bus e Dual DDR2 memory controllers e PCI Express interface e Serial RapidIO interface e Gigabit Ethernet interfaces e Local Bus interface e PC interfaces e Serial I O interfaces e DMA engines e Interrupt controller 5 2 1 PowerPC Processing Cores The MPC8641D contains two e600 high performance 32 bit superscalar PowerPC processing cores as used in the MPC7448 processor clocked at up to 1 33 GHz The e600 processing core implements a fully static architecture and offers sophisticated power management capabilities Each core includes e 32 KByte Level 1 instruction and data caches e 1 MByte Level 2 backside cache with ECC e 36 bit physical addressing e AltiVec Vector Unit e Enhanced branch prediction capabilities e MMU and integral FPU Table 5 1 Processor Specifications Processor Type Core F
158. ssert 29 Assert Doorbell2 Write 1 to assert 30 Assert Doorbell1 Write 1 to assert 31 Assert DoorbellO Write 1 to assert Publication No SBC610 0HH 2 Control and Status Registers 97 6 23 PCI Express Doorbell Clear Register Offset 0x5034 Writing a 1 to a bit in this register clears the corresponding doorbell interrupt This register is write only but the doorbell status can be read from the PCI Express Doorbell Status Register Table 6 19 PCI Express Doorbell Clear Register Bits Description Notes 0to27 Reserved 0x0000000 28 Clear Doorbell3 Write 1 to clear 29 Clear Doorbell2 Write 1 to clear 30 Clear Doorbell 1 Write 1 to clear 51 Clear DoorbellO Write 1 to clear 6 24 PCI Express Doorbell Status Register Offset 0x5038 This register reflects the status of the doorbell interrupts The register is read only The interrupts must be asserted or cleared using the PCI Express Doorbell Assert Clear register Active doorbell interrupts can be routed to processing cores using the Board Interrupt Core x INT Mask Registers Table 6 20 PCI Express Doorbell Status Register Bits Oto 27 28 29 30 31 Description Reserved Doorbel Doorbel Doorbel Doorbel 98 SBC610 6U VPX Single Board Computer 3 Status 2 Status 1Status 0 Status Notes 0x0000000 0 Doorbe Doorbe Doorbe Doorbe Doorbe Doorbe Doorbe Doorbe interru
159. t pattern to check for byte ordering from the FPGA Table 6 10 Test Pattern Registers Register Offset Test Pattern 1 0x0020 OxAAAAAAAA 2 0x0024 0x55555555 3 0x0028 SBC6 0x53424336 Publication No SBC610 OHH 2 Control and Status Registers 91 6 10 Scratchpad Registers Offsets 0x0030 to 0x003C These four registers have no effect on the system and are provided for software to store status information or data Their value on reset is 0x0000 0000 6 11 Board Semaphore Registers Offsets 0x0040 to 0x007C Each register controls one of sixteen semaphores Table 6 11 Board Semaphore Register Offsets Offset Semaphore Offset Semaphore mun 1 en 9 0x0044 2 0x0064 10 0x0048 3 0x0068 11 Ox004C 4 Ox006C 12 0x0050 5 0x0070 13 0x0054 6 0x0074 14 0x0058 7 0x0078 15 0x005C 8 0x007C 16 A semaphore is taken by reading the corresponding register e If the value returned is zero then semaphore is currently in use e If the value returned is non zero then the semaphore take is successful The semaphore is released by writing to the corresponding register the value written is not significant The reset value for all semaphore registers is 0x0000 0001 92 SBC610 6U VPX Single Board Computer Publication No SBC610 OHH 2 6 12 Watchdog 0 Control Register Offsets 0x2000 and Watchdog 1 Control Register Offsets 0x2010 These registers control the operation of Watchdogs Timers 0 a
160. t permission THIS DOCUMENT AND ITS CONTENTS ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FORA PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia Pacific 86 10 6561 1561 Europe Middle East and Africa Germany 49 821 5034 0 UK 44 1327 359444 Additional Resources For more information please visit the GE Intelligent Platforms Embedded Systems web site at defense ge ip com Publication No SBC610 0HH 2
161. ted onto PMC Site 1 to access the MPC8461D and program the Flash This feature may be used to program a blank board Table 3 8 E21 Link Setting Setting Function Out Normal operation In Core 0 boot hold off 3 3 10 Factory Link E22 This link is for factory use only It should not be fitted in normal operation 3 3 11 JTAG Scanbridge Output Enable Link E23 The SBC610 uses a JTAG Scanbridge device to connect all of the JTAG compliant devices on the board This link is provided to enable the Scanbridge during boundary scan It should not normally be fitted in deployed systems and must not be fitted when the BDM Header or PLD Programming Header are in use Table 3 9 E23 Link Setting Setting Function Out Scanbridge disabled In Scanbridge enabled 3 3 12 PCI Express Selection Links E24 and E25 These links are used to control the fabric multiplexer for two of the x4 fabric links on the P1 connector Link E24 controls the selection of Fabric Port 3 and Link E25 controls the selection of Fabric Port 4 If a x8 PCI Express port is required on the backplane both links should be fitted Table 3 10 E24 and E25 Link Settings Setting Function Out Serial RapidlO routed to the backplane In PCI Express routed to the backplane The state of these links is reflected in Control Register 2 and may be overridden by software if required 26 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 3 3 13
162. tem to indicate that the required input voltage levels are not being met VME_AM 5 0 Address Modifier Used to broadcast information such as cycle type VME_AS Address Strobe Driven active when a valid address is placed on the address bus VME_BBSY Bus Busy Driven low by the current bus master to show that the VME bus is in use VME BCLR Bus Clear Driven low by the arbiter to show that there is a higher priority request for the bus Causes the current master to E release the bus VME BERR Bus Error Driven low by the slave or bus timer to indicate that the current transfer did not complete Bus Grant In The BGxIN BGxOUT signals form the bus grant daisy chain i e the BGXOUT of one board forms the BGxIN of VME BGnIN the next board in the daisy chain The arbiter drives these signals low to tell the board receiving them that if it is requesting the bus on the corresponding level then it has been granted use of the bus Otherwise the board should pass the signal down the daisy chain VME BGnOUT Bus Grant Out Requesters drive these signals to tell the next board in the daisy chain that if it is requesting the bus on that level E then it can use the bus Otherwise the board should pass the signal down the daisy chain VME BR 3 0 Bus Request A requester drives a low level on one of these lines shows to request use of the VMEbus VME_D 31 00 Data Bus Used to transfer data between masters and slaves Data Strobes These are used with L WORD and A01 to
163. the PEX8518 number and width of ports and selection of the non transparent port must be set up by software in the serial EEPROM No alternative hardware strapping is provided for these features This EEPROM is write protected by default and can be write enabled by clearing the Serial EEPROM Write Protect bit in Control Register 1 This bit may only be cleared when the NVRAM Write Enable Link E18 is fitted and the backplane NVMRO signal on connector P0 pin A4 is inactive low The switch can be prevented from accessing the EEPROM under software control if the data becomes corrupted and configures the switch such that the EEPROM contents cannot be overwritten This may be done by setting the PEX8518 Serial EEPROM Disable bit in Control Register 2 or by fitting the Recovery Boot Link E14 The PEX8518 is connected to PC Bus 1 Address 0x70 to allow configuration by the processor and out of band monitoring of link status The link status of each of the backplane PCI Express lanes is reflected by LEDs the rear of the PCB The PCI Express register block is intended to be made accessible from the PCI Express backplane allowing external boards to interrupt the local processors and lock shared resources 5 14 2 Serial RapidlO The SBC610 can support up to four off board x4 SRIO links on the P1 connector SRIO on the SBC610 is provided by a Tundra Tsi578 Serial RapidIO switch which has eight x4 SRIO ports capable of operating at 1 25 2 5 and 3
164. the PMC1 PCle PCI Bridge is active DS328 Green PEX8548 Port 14 Good The PCle link to the VME PCle PCI Bridge is active The Port Good LEDs will light if any link has been made between the two devices even if it is of reduced width a x1 link on a x8 connection for example The exact state of each link can only be determined by software interrogation of the device registers 5 24 6 SATA Activity LEDs DS329 and DS330 Table 5 42 SATA Activity LEDs LED Color Function Meaning When Lit DS329 Yellow SATAChO Activity SATA activity on Channel 0 DS330 Yellow SATA Ch1 Activity SATA activity on Channel 1 Publication No SBC610 0HH 2 Functional Description 81 5 24 7 Backplane PCI Express Lane Status LEDs DS331 to DS339 Table 5 43 Backplane PCI Express Lane Status LEDs LED Color Function eaning When Lit DS331 Green PEX8518Lane8Good This PCI Express lane connected to backplane port 3 lane 1 is active DS332 Green PEX8518Lane9Good This PCI Express lane connected to backplane port 3 lane 2 is active DS333 Green PEX8518 Lane 10 Good This PCI Express lane connected to backplane port 3 lane 3 is active DS335 Green PEX8518 Lane 12 Good This PCI Express lane connected to backplane port 4 lane 1 is active lane 2 is active 3 3 3 DS334 Green PEX8518 Lane 11 Good This PCI Express lane connected to backplane port 3 lane 4 is active 4 DS336 Green PEX8518 Lane 13 Good This PCI Expr
165. ting 20 to 65 Random 20g peak Up to 95 RH with As Standard but conformally coated and Extended with airflow of 300 0 002g Hz from 10 sawtooth varying temperature characterized Temperature feet minute to 2000 Hz 11ms emperature Level 2 Storage 50 to 100 Sine 2g from 5 duration 10 cycles to 500 Hz 240 hours Operating 40 to 75 Random 20g peak Up to 9596 RH with Wide temperature rugged cooled by forced with airflow of 600 0 04g2 Hz from 20 sawtooth varying air Conformally coated for additional Rugged Air feet minute to 2000 Hz with a 11ms emperature protection cooled Storage 50 to 100 flat response to duration 10 cycles Level 3 1000 Hz 6db Octave 240 hours roll off from 1000 to 2000 Hz A 3 2 Conduction cooled Boards Table A 5 Conduction cooled Environmental Specifications Build Style Temperature C Vibration Shock Humidity Comments Operating 40 to Random 0 1g2 Hz 40g peak Up to 95 RH with Designed for severe environment applications 75atthethermal from 15 to 2000 Hz sawtooth 11 varying with high levels of shock and vibration small Rugged interface per MIL STD 810E ms duration temperature space envelope and restricted cooling supplies a i Storage 50 to Fig 514 4 8 for high 10 cycles Conformally coated as standard Optional ESS cooled Leve 100 performance aircraft 240 hours 12g RMS Operating 40 to Random 0 19 Hz 40g peak Up to 95 RH with Designed for severe environment
166. tion equipment number and board revision Figure 2 1 Product Label Packaging SBC610 1232A13B1 Ex 6U VPX Single Board Computer Level 1 Equipment No 12345678 It ES Internal Ref ADAC 100004 4 Rev 1A1 Made in the U K Cage K7034 On the board within the antistatic bag there is an identifying label similar to the example shown in Figure 2 2 attached to the PCB Figure 2 2 Product Label Product MADE IN UK ANDES REV 1A1 CAG K7034 SER 12345678 PNR SBC610 1232A13B1 Publication No SBC610 0HH 2 Unpacking 19 On the conduction cooled version of the board build levels 4 and 5 there is also a label similar to the example shown in Figure 2 3 attached to the front panel Figure 2 3 Product Label Conduction cooled Product SBC610 CAGE CODE K7034 o MADE IN UK gt See the Product Codes section in Appendix A for more details on the product code SBC610 xxxxxxxxx 20 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 3 e Configuration 3 1 Link Configuration The SBC610 has push on jumpers included in the standard kit of parts additional jumpers may be obtained on request These are suitable for level 1 to 3 low vibration applications it TIP For Level 4 and 5 products make links by wire wrapping between the pin posts and then cover these wire wrapped links with the same conformal coating as that used on the board This will provide a reliable connection under heavy shock and vibrati
167. to have as a minimum a terminal connection present on the serial COMI port Ethernet and USB connections may also be required depending on Operating System requirements These ports may be accessed through the backplane signals using a Rear Transition Module RTM COMI is configured as DTE with default settings of 9600 baud 8 bits character 1 stop bit parity disabled and no flow control 4 4 1 Rear Transition Module For development systems connection to the Serial and Ethernet I O can be achieved using an RTM This converts the condensed pin out of the backplane connectors to pinouts suitable for use by industry standard connectors The following items are required e The SBC610 e The appropriate RTM VPX6UX600 e Anull modem 9 way D to 9 way D type cable for connecting COM1 to a control terminal or PC running terminal emulation software e For the Ethernet ports a CATS or better straight through patch cable for 10 100 1000BaseTX e For USB the required peripheral with a standard type A connector The VPX I O Modules manual contains more details on fitting RTMs Similar antistatic and safety precautions apply when handling and or installing RTMs as for the SBC610 ON LINKS VPX I O Modules Hardware Reference Manual publication number VPXIOM OHH VPX6UX600 Hardware Reference Manual publication number VPX6UX600 0HH 32 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 4 5 Reset and Power up Sequence
168. ts down the on board supplies if these fall below their specified levels The Power Manager is connected to DC Bus 1 allowing software read out of the voltages of all on and off board supplies The Power Manager will shut down all on board supplies except PSV3 AUX when the BMM asserts the BMM OFF signal The 5V supply to the mezzanine cards is switched under the control of the Power Manager so that the 5V and 3 3V supplies are applied to the mezzanines at approximately the same time 5 22 2 Inter board sequencing The SBC610 supports a proprietary inter board power sequencing mechanism This allows for the sequencing of power between several boards in a system to be controlled limiting overall inrush current This is achieved by the PSU SEO OUT and PSU SEQ IN signals on the P1 connector which can be daisy chained between boards The SBC610 drives the PSU SEQ OUT signal low when the backplane supplies are out of specification and holds it low until all on boards supplies are within specification The PSU SEQ OUT signal is not driven low when the power is removed as a result of the BMM OFF signal being asserted The SBC610 holds off all on board supplies except P3V3_AUX when the PSU SEO IN signal is held low The power on sequence is initiated if the PSU SEQ IN signal remains low 500ms after the off board supplies are within specification which may occur if the previous board in the chain fails Publication No SBC610 0HH 2 Functi
169. tting a jumper on the Recovery Boot Link E14 The Tsi578 is connected to PC Bus 2 address 0x02 to allow it to access its configuration EEPROM be configured by software or provide out of band monitoring of the link status The Tsi578 is able to generate a reset on the SBC610 or an interrupt to a local processor core in response to an internal event or if requested by an external host 5 15 Mezzanines 5 15 1 PMC XMC Sites The SBC610 has two mezzanine sites that both support PMCs or XMCs including support for front panel I O The two mezzanine sites are spaced to allow fitting of a double width PMC XMC if required The presence of a PMC or XMC in a site can be read from the Board Configuration Register 5 15 2 PCI Mezzanine Cards PMCs Each site has Jn1 Jn2 Jn3 and Jn4 connectors to provide a 64 bit PCI bus capable of PCI X operation at frequencies of up to 133 MHz Each PCI bus is connected to a PEX8114 PCle to PCI Bridge which provides frequency negotiation clocks and arbitration for the bus The PEX8114 device is not 5V tolerant and so the SBC610 does not support PMCs which use 5V signaling LN CAUTION The SBC610 PMC site is not 5V tolerant Do not fit PMCs that use 5V signaling Each PMC site has a dedicated PCI bus so fitting a PMC that runs at a lower frequency does not limit the other PMC or the performance of other functions of the SBC610 58 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2
170. ured and may be displayed by software Six status LEDs are provided on the rear of the board to allow the status of each Ethernet interface to be monitored The SBC610 routes the two 10 100 1000BaseT Ethernet ports to the P4 Connector in accordance with VITA46 9 as follows Table 5 11 ETHO ETH1 Pin Mapping Signal Di Pin Signal P4 Pin ETHOQOP a ETHILOP As ETHO ON B13 ETH1 0 B15 ETHO_1P D13 ETH1 1P D15 ETHO IN E13 ETH1 1 E15 ETHO 2P B14 ETH1 2P B16 ETHO 2N C14 ETH1 2 C16 ETHO_3P E14 ETH1 Ap E16 ETHO 3N F14 ETH1 3 F16 Publication No SBC610 OHH 2 Functional Description 49 5 10 Serial Communication Ports The SBC610 has six serial ports which are sourced from different devices and so have different capabilities 5 10 1 COM1 and COM2 COMI and COM2 are provided by the DUART module within the MPC8641D and are intended to operate as debug ports for the two processing cores Each of the two UARTS provides 16 byte FIFOs and is software compatible with the PC16450 and PC16550D UART devices Hardware flow control signals RTS CTS are supported The baud rate is software programmable between and is derived from the MPX bus frequency using the following equation Baud Rate 1 16 MPX Bus Frequency Divisor Value The table below shows the divisors used for some commonly used baud rates and the percentage error associated with the use of an integer divider Note that the p
171. uring the VME LWORD data transfer Retry A slave can assert RETRY together with BERR to postpone a data transfer The master must then attempt the cycle VME RETRY 3 again at a later time The retry cycle prevents deadlock VME SYSCLK System Clock This provides a constant 16 MHz clock signal that is independent of any other bus timing VME SYSFAIL System Fail Shows a failure has occurred in the system Any board in the system can generate this signal VME WRITE Write A master generates this to show whether the data transfer cycle is a read or a write PMC1 IO 64 01 Rear 1 0 Signals from PMC site 1 J14 connector Signal names reflect the pin numbers of this connector PMC2 IO 64 01 Rear I O Signals from PMC site 2 124 connector Signal names reflect the pin numbers of this connector XMC1 IO x 19 01 XMC2 IO x 19 01 Rear UO signals from XMC site 1 J16 connector Signal names reflect the pin numbers of this connector Rear UO Signals from XMC site 1 J26 connector Signal names reflect the pin numbers of this connector BOOT_SWAPn Used to swap the active boot site of Processing Core 0 and Processing Core 1 See the Boot Flash section for more information COMn_CTS COM1 2 Clear To Send input for RS232 mode This signal becomes COMn RX B when either port is used in RS422 mode COMn RTS COM1 2 Ready To Send output for RS232 mode This signal becomes COMn TX B when either port is used in RS422 m
172. us e Secondary interrupt controller 5 18 3 1 0 FPGA This is a Xilinx Virtex 4 LX25 device that provides the following functions e Two ESCC IP cores used to generate COM3 COM4 COM5 and COM6 serial ports e DMA engines for transfer of data between serial ports and internal block RAM used for data buffering COM3 4 only e Enhanced Baud Rate Generation capabilities e General Purpose I O Controller An external SRAM device is connected to the I O FPGA for local buffering of data as required by the application The device fitted is 16 bits wide and has a capacity of 2 MBytes The I O FPGA is configured using a Xilinx parallel configuration PROM XCFO08P The DONE and INIT configuration signals are made available in Control Register 2 This allows software to see when the FPGA is configured or to cause the device to reconfigure if required The SBC610 also has the ability to fit a larger configuration PROM supporting revision control with the active revision selected by the value in Control Register 2 NOTE There is the potential to tailor the functionality of this device to accommodate specific customer requirements Contact your local sales representative for further details 72 SBC610 6U VPX Single Board Computer Publication No SBC610 0HH 2 5 19 Timers The 8641D provides eight 31 bit general purpose timers Each timer is capable of generating interrupts to either or both processing cores and can be programmed to generat

SBC610 6U VPX Single Board Computer

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