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SPARC/CPU-5TE Technical Reference Manual

1. FIGURE 12 Block Diagram of the SPARC CPU 5TE I on m mem SBus Slot 8 16 32 64 Mbyte DRAM L SBus Slot SBus each Module 8 bit USER local bus BOOT k Flash Flash R E MicroSPARC eys Ona RTC 1 4 y N Display NVRAM M T Rotary FPGA E P LEDs SBus b A u N Ethernet 2 AUI 5 E Keyboard Mouse MACIO MACIO L Two Serial 1 0 SLAVIO 1 2 SCST 2 Fl oPPy Switch Matrix Keyboard Mouse Two Serial I O Centronics SCSI 1 0 Ohm SCSI 1 Ethernet 1 TP TP Ethernet 1 AUI Ethernet 2 TP TP The Ethernet 2 SCSI 2 and Centronics devices are only available with the 5 row P2 Connector However the SCSI 2 is available on the 3 row P2 Connector through the use of a switch matrix instead of the floppy interface FORCE COMPUTERS Page 55 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 1 The microSPARC II Processor The microSPARC II CPU chip is at the core of the SPARC CPU STE This chip is realized in a 321 pin CPGA package A Floating Point Unit an Integer Unit an MMU an Instruction Cache and a Data Cache are integrated in the microSPARC II processor Please see the microSPARC II Data Sheet STP1012 for further information 3 1 1 Features of the microSPARC II Processor e microSPARC II chip running at 85 MHz e Integer Unit with 5 stage p
2. Address Reset Size Description Value 7138 0000 XX 8 bit VMEbus Slave Base Register 1 7138 0001 XX 8 bit VMEbus Slave Base Register 2 7138 0002 XX 8 bit VMEbus Slave Base Register 3 7138 0003 XX 8 bit VMEbus Control Register 7138 0004 XX 8 bit VMEbus A32 Map Register 7138 0005 XX 8 bit General Purpose Register 1 7138 0006 XX 8 bit Seven Segment LED Display Register 7138 0007 XX 8 bit General Purpose Register 2 713C 0000 FC 8 bit Network Interface 1 Control and Status Register 713C 0001 FC 8 bit Network Interface 2 Control and Status Register 713C 0002 FC 8 bit USER LED and USER Flash Memory Control and Status Register 713C 0003 3F 8 bit VMEbus Transaction Timeout Control Register 713C 0004 FE 8 bit Reserved 713C 0005 FO 8 bit USER Flash Memory Programming Control Register 713C 0006 XX 8 bit Reserved 713C 0007 XX 8 bit Reserved FORCE COMPUTERS Page 113 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 10 2 vme_slavebasel Register The vme_slavebasel register is for serial loading of the VMEbus slave base address in the Enhanced Slave Mode If you read the 8 bit value from that register you get the U pper boundary of the set VMEbus slave base address bits A27_U A20_U Physical Address Register Name Read Write Access 7138 0000 vme_slavebase1 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO
3. WIN2 wmi wmo Widow Virtual Base 0 0 0 1 Mbyte FFFO 0000 0 0 1 2 Mbyte FFEO 0000 0 1 0 4 Mbyte FFCO 0000 0 1 1 8 Mbyte FF80 0000 1 0 0 16 Mbyte FF00 0000 1 0 1 32 Mbyte FE00 0000 1 1 0 64 Mbyte FC00 0000 1 1 1 transparent 0000 0000 Initialization At reset WIN 2 0 are set to Os Depending on the programmed window size the DVMA window is mapped to the upper virtual address space Additionally the upper table shows the virtual base addresses for the different window sizes NOTE The virtual base address has an offset if the programmed VMEbus slave base address does not have the selected window size boundary In transparent mode Address Bit 27 to Address Bit 0 are transparent This means you can access directly 256 Mbyte EXAMPLE The programmed window size is 64 Mbyte You choose a VMEbus slave base address of 8010 0000 which is not in a 64 Mbyte boundary This would lead to a virtual base address of FC00 0000 10 0000 FC10 0000 The VMEbus slave base address can be programmed anywhere in the 4 Gbyte VMEbus address space The VMEbus slave base address is that address where the VMEbus master can access on board memory of the CPU 5TE For the programming of the VMEbus slave base address please refer to Additional Registers on page 113 Page 92 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 7 4 VMEbus Interrupt Handler and
4. Pin Signal Direction Port Description 1 none none A Not connected 2 TD output A Transmit Data 3 RD input A Receive Data 4 RTS output A Request To Send 5 CTS input A Clear To Send 6 DSR input A Data Set Ready T SG none A Signal Ground 8 DCD input A Data Carrier Detect 9 none none Not connected 10 none none Not connected 11 SDTR output B Secondary Data Terminal Ready 2 SDCD input B Secondary Data Carrier Detect 13 SCTS input B Secondary Clear To Send 4 STD output B Secondary Transmit Data 15 TC input A Transmit Clock DCE Source 6 SRD input B Secondary Receive Data 17 RC input A Receive Clock 8 STC input B Secondary Transmit Clock 19 SRTS output B Secondary Request To Send 20 DTR output A Data Terminal Ready 21 SDSR input B Secondary Data Terminal Ready 22 SRC input B Secondary Receive Clock 23 SSG none B Secondary Signal Ground 24 TC output A Transmit Clock DTE Source 25 STC output B Transmit Clock DTE Source 26 none none Not connected FORCE COMPUTERS Page 39 Installation SPARC CPU 5TE FIGURE 8 Serial Ports A and B Connector Pinout BERRRRRERREEE 5g MEE Page 40 FORCE COMPUTERS SPARC CPU 5TE 2 8 3 Keyboard Mouse Connector Pinout Installation The keyboard and mouse port is available on the front panel via a Mini DIN connector Table 14 Keyboard Mouse Connector Pinout Pin Function 1 GND 2 GND 5VDC Mouse In Keyboard
5. A27_U A26_U A25_U A24_U A23_U A22_U A21_U A20_U NOTE The bits A27_U A20_U are read only 3 10 3 vme_slavebase2 Register If you read the 8 bit value of the vme slavebase2 register you get the L ower boundary of the VMEbus slave base address bits A27_L A20_L Writing any data to that register clears the pending non maskable interrupt of the ABORT switch Physical Madness Register Name Read Write Access 7138 0001 vme_slavebase2 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO A27_L A26_L A25_L A24_L A23_L A22_L A21_L A20_L NOTE The bits A27_L A20_L are read only Page 114 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 4 How to Program the VMEbus Slave Base Address The complete VMEbus slave base address in the enhanced slave mode consists of the following three parts e The 4 bit B ase address this is the address lines A31 A28 e The 8 bit U pper boundary this is the address lines A27 A20 e The 8 bit L ower boundary this is also the address lines A27 A20 To program that complete slave base address exactly 8 bytes must be written to the vme_slavebasel register each containing the following data Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bito Byte l p A28_B A20_L A20 U Byte 2 P A29 B A21_L A21_U Byte 3 3
6. below Physical A Address Register Name Read Write Access 713C 0005 USER FLASH MEMORY r w 8 bit PROGRAMMING CONTROL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO 1 1 1 1 SEL DEV_SEL 2 0 ENA Setting Function SEL_ENA 0 Default CPU 5CE Mode SEL_ENA 1 Enhanced CPU 5TE Mode DEV_SEL 2 0 selects one of the available eight User Flash memory devices The values listed in the table may be used to select a specific User Flash memory device The next page contains a list of the flash memory programming control bits FORCE COMPUTERS Page 81 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 40 Programming Control Bits BT_US FL PAG DEV_SEL 2 0 Programs 1 0 don t care Boot EPROM Dev 1 with 256 KB 1 1 don t care Boot EPROM Dev 2 with 256 KB 1 0 don t care Boot EPROM Dev 1 with 512 KB 1 1 don t care Boot EPROM Dev 2 with 512 KB 0 0 000 User EPROM first 512 KB of Dev 1 0 1 000 User EPROM second 512 KB of Dev 1 0 0 001 User EPROM first 512 KB of Dev 2 0 1 001 User EPROM second 512 KB of Dev 2 0 0 010 User EPROM first 512 KB of Dev 3 0 1 010 User EPROM second 512 KB of Dev 3 0 0 O11 User EPROM first 512 KB of Dev 4 0 1 O11 User EPROM second 512 KB of Dev 4 0 0 100 User EPROM first 512 KB of Dev 5 0 1 100 User EPROM second 512 KB of Dev 5 0 0 101 User EPROM first 512 KB of Dev 6 0 1 101 User EPROM second 512 KB of D
7. Manufacturer Part Function Location Type Number Ethernet 1 Front Panel RJ 45 AMP 555131 1 Twisted Pair Ethernet 2 Front Panel RJ 45 AMP 555131 1 Twisted Pair Serial Port A B Front Panel 26 pin Fine Pitch AMP 749831 2 SCSI Front Panel 50 pin Fine Pitch AMP 749831 5 Keyboard Mouse Front Panel 8 pin Mini DIN AMP 749232 1 SBus Slot2 P3 96 pin SMD FUJITSU FCN 234J096 G V SBus Slave Select 1 SBus Slot3 P4 96 pin SMD FUJITSU FCN 234J096 G V SBus Slave Select 2 VMEbus P1 P1 96 pin VGA Various VMEbus P2 P2 96 pin VGA Various The following pages show the pinouts of the connectors FORCE COMPUTERS Page 37 Installation SPARC CPU 5TE 2 8 1 Twisted Pair Ethernet Connector Pinout The following table shows the pinout of the twisted pair Ethernet connector The pinout for both of the connectors is identical Table 12 Twisted Pair Ethernet Connector Pinout Pin Signal Number Name 1 TPEO 2 TPE1 3 TPE2 4 N C 5 N C 6 TPE3 7 N C 8 N C FIGURE 7 Twisted Pair Ethernet 12 345678 RJ45 Page 38 FORCE COMPUTERS SPARC CPU 5TE Installation 2 8 2 Serial Port A and B Connector Pinout The following table is a pinout of the serial port connector The figure on the next page shows the serial port connector and location of the pin numbers Table 13 Serial Port A and B Connector Pinout
8. Setting Function WNMIP 0 No Watchdog NMI pending WNMIP 1 Watchdog NMI pending FORCE COMPUTERS Page 109 Hardware Description The appropriate interrupt handler has to reset the pending non maskable interrupt This is done with the WNMIR bit Watchdog NMI Reset in the gen_purpose2 register It must be set to one to reset the Watchdog NMI In addition the Power Fail Detect bit in the Aux 2 register of the NCR89C105 must be set to clear the interrupt Please refer to the NCR SBus I O Chipset Data Manual for the Aux 2 register SPARC CPU S5TE Technical Reference Manual Bit7 WNMIR Physical Register Ad ress Nanie Read Write Access 7138 0007 gen_purpose2 r w 8 bit Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 ACSTAT ACNMIR ACNMIP DVMA_ IRQI5_ US_DEV BT_US ENA ENA NOTE WNMIR is a write only bit FORCE COMPUTERS Page 110 SPARC CPU 5TE Technical Reference Manual 3 9 2 Rotary Switch Hardware Description The CPU STE provides an additional rotary switch for user selectable settings See Diagram of the CPU 5TE Bottom View on page 13 for the position of the rotary switch on the board It is a hexadecimal rotary switch decoded with 4 bits The status of the rotary switch can be read in the gen_purpose register Physical Register Address Name Read Write Access 7138
9. A30_B A22_L A22_U Byte 4 A31_B A23_L A23_U Byte 5 1 A24 L A24 _U Byte 6 1 A25_L A25_U Byte 7 2 1 A26_L A26_U Byte 8 1 A27_L A27 _U NOTE means don t care FORCE COMPUTERS Page 115 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 10 5 If you read the 8 bit value of the vme slavebase3 register you get the 256 Mbyte boundary vme_slavebase3 Register B ase address of the VMEbus slave base address bits A31_B A28_B Writing any data to that register clears the pending non maskable interrupt of the VME SYSFAIL signal Physical Address Register Name Read Write Access 7138 0002 vme_slavebase3 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO 1 1 1 1 A31_B A30_B A29_B A28_B NOTE The bits A31_B A28_B are read only Bits 7 4 are always read as ones if the program algorithm for the serial loading of the VMEbus slave base address is used This is described in the vme_slavebasel Register on page 114 Page 116 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 6 vme_ctl Register The vme_ctl register is used for settings concerning the VMEbus master and slave interface Physical Register Aadress Name Read Write Access 7138 0003 vme_ctl r w 8 bit Bit7 B
10. vaddr returns the virtual address vaddr of the S4 s Bus Locker Register s4 intr monitor vaddr returns the virtual address vaddr of the S4 s Interrupt Monitor Register s4 mbox intr level vaddr returns the virtual address vaddr of the S4 s Mailbox Interrupt Level Register s4 mbox ctrl vaddr returns the virtual address vaddr of the S4 s Mail Box Regis ter s4 intr ena vaddr returns the virtual address vaddr of the S4 s Interrupt Enable Register s4 a32map vaddr returns the virtual address vaddr of the S4 s A32 Map Register Page 140 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements s4 slavemap vaddr returns the virtual address vaddr of the S4 s Slave Map Regis ter s4 iack cycle level vaddr returns the virtual address vaddr of the S4 s IACK Cycle Register associated with the given level The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VME bus interrupt request levels Only the least significant three bits of level are considered and when level is zero then the command treats it as if the value one has been passed to the command vme slavebasel vaddr returns the virtual address vaddr of the VMEbus interface s VMEbus Slave Base Register 1 vme Slavebase2 vaddr returns the virtual address vaddr of the VMEbus interface s V
11. value one 1 in the example specifies the separation between FCode byte in general Because the bn dload command loads the FCode into on board memory the spacing is one 1 Binary Executables Executable binary programs to be loaded with bn dload must be in the a out format To execute the binary program the go command has to be used as follows ok go When the program should be started again the commands listed below have to be used ok init program go FORCE COMPUTERS Page 193 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 8 7 Booting from a Solaris SunOS BusNet Server When Solaris SunOS is loaded and executed from a Solaris SunOS BusNet server the boot command has to be used as follows ok boot busnet In this case OpenBoot will load the appropriate primary booter from the server using the Trivial File Transfer Protocol TFTP and start execution of the loaded image When the Solaris SunOS is loaded and executed automatically after each system reset the NVRAM configuration parameter auto boot must be set to t rue and depending on the state of the configuration parameter diag switch either boot device or diag device must be set When the diagnostic mode is disabled the configuration parameter boot device must be set as follows ok setenv boot device busnet And in the case that the diagnostic mode is enabled the configuration parameter diag device must be set as described in the followi
12. 2 4 5 Front Panel SCSI 1 Termination Please note how the SCSI 1 termination works on the front panel Termination for the SCSI 1 interface is disabled when SW7 1 is ON When switch SW7 1 is OFF the termination is set to automatic termination mode Automatic termination mode means the respective termination is disabled when you connect a standard SCSI cable to the connector 2 4 6 P2 SCSI Termination Termination for the P2 SCSI 1 is disabled when SW5 4 is ON and this is the default setting Termination for the P2 SCSI 2 is enabled when SW5 3 is OFF and this is the default setting FIGURE 4 SCSI Termination Vv M E B F SWS5 3 controls SCSI 2 termination on P2 u R OFF Enable s O ON Disabled N MACIO P T Termination 2 SCSI 2 2 P A C N o E baited n L SW7 1 controls peat termination for Front Panel SW5 4 controls SCSI 1 n OFF Automatic Sas termination on P2 e ON Disabled OFF Enable E MACIO ON Disabled t 1 o Termination Termination r SCSI 1 SCSI 1 FORCE COMPUTERS Page 21 Installation SPARC CPU 5TE 2 4 7 Boot Flash EPROM Write Protection Both Boot Flash EPROMs are write protected via the switch SW13 2 When SW 13 2 is OFF the devices are write protected and this is the default setting 2 4 8 User Flash EPROM Write Protection The optional User Flash EPROMs are write protected via SW13 1 When SW13 1 is OF
13. 2 5 OpenBoot Firmware This chapter describes the use of OpenBoot firmware Specifically you will read how to perform the following tasks Boot the System Run Diagnostics Display System Information Reset the System OpenBoot Help For detailed information concerning OpenBoot please see the OPEN BOOT PROM 2 0 MANUAL SET This manual is included in the SPARC CPU 5TE Technical Reference Manual Set 2 5 1 Boot the System The most important function of OpenBoot firmware is booting the system Booting is the process of loading and executing a stand alone program such as the operating system After it is powered on the system usually boots automatically after it has passed the Power On SelfTest POST This occurs without user intervention If necessary you can explicitly initiate the boot process from the OpenBoot command interpreter Automatic booting uses the default boot device specified in nonvolatile RAM NVRAM user initiated booting uses either the default boot device or one specified by the user To boot the system from the default boot device type the following command at the Forth Monitor prompt ok boot or if you are at the Restricted Monitor Prompt you have to type the following gt b FORCE COMPUTERS Page 25 Installation SPARC CPU 5TE The boot command has the following format boot device specifier filename ah The optional parameters are described as foll
14. Floppy Interface or SCSI 2 Availability on P2 on page 23 FIGURE 11 The IOBP DS t a Serial Ethernet ee 4 SCSI2 SCSI 1 Cem Keyboard The pinouts of the connectors are shown in the following tables CAUTION This IOBP 10 back panel and the IOBP DS are especially designed for the SPARC CPU STE Do not use any other I O back panels on the SPARC CPU STE for example the IOBP 1 Page 48 FORCE COMPUTERS SPARC CPU 5TE 2 9 2 IOBP DS P2 Connector Pinout Pin Signal Signal a a x Row A Row B i signals 1 SCSI 1 D0 5V SCSI 2 D0 2 SCSI 1 D1 GND SCSI 2 D1 3 SCSI 1 D2 N C SCSI 2 D2 4 SCSI 1 D3 N C SCSI 2 D3 5 SCSI 1 D4 N C SCSI 2 D4 6 SCSI 1 D5 N C SCSI 2 D5 7 SCSI 1 D6 N C SCSI 2 D6 8 SCSI 1 D7 N C SCSI 2 D7 9 SCSI 1 DP N C SCSI 2 DP 10 GND N C SCSI 2 ATTN 11 GND N C SCSI 2 BSY 12 GND GND SCSI 2 ACK 13 TERMPWR 1 5V SCSI 2 RST 14 GND N C SCSI 2 MSG 15 GND N C SCSI 2 SEL 16 SCSI 1 ATTN N C SCSI 2 CD 17 GND N C SCSI 2 REQ 18 SCSI 1 BSY N C SCSI 2 IO 19 SCSI 1 ACK N C ETH 1_POW 20 SCSI 1 RST N C TERMPWR 2 21 SCSI 1 MSG N C GND 22 SCSI 1 SEL GND ETH 1_REC 23 SCSI 1 CD N C ETH 1_REC 24 SCSI 1 REQ N C ETH 1_TRA 25 SCSI 1 IO N C ETH 1_TRA 26 MOUSEIN N C ETH 1_COL 27 TXD_KBD N C ETH 1_COL 28 RXD_KBD N C GND 29 TXD_A N C TXD_B 30 RXD_A N C RXD_B 31 DTR_A GND
15. When a non maskable interrupt occurred due to the assertion of the ACFAIL signal then the appropriate interrupt handler increments the variable acfail asserted by one to report the occurrence of such an interrupt The state of this variable is obtained by ok acfail asserted 2 ok And the variable is cleared set to zero by ok acfail asserted off ok Page 176 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 5 4 ABORT Interrupt OpenBoot for the SPARC CPU STE already includes an interrupt handler to serve the non maskable interrupt generated by pressing the front panel abort switch This handler does not need to be installed because it is already installed by OpenBoot By default the interrupt that will be emitted when the abort switch has been pressed is disabled and has to be enabled by ok abort nmi ena ok which enables the generation of a non maskable interrupt whenever the abort switch is pressed When a non maskable interrupt occurred due to pressing the abort switch then the appropriate interrupt handler increments the variable abort occurred by one to report the occurrence of such an interrupt The state of both variables are obtained by ok abort occurred 7 ok And these variables are cleared set to zero by ok abort occurred off ok Besides the effects described above the pressing of the abort switch has the same effect as giving the Stop A keyboar
16. allows the VMEbus interface to generate an inter Page 150 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements rupt upon the assertion of the VMEbus ACFAIL signal vme acfail assert irq dis disables the interrupt to be generated upon the assertion of the VMEbus ACFAIL signal vme acfail l assert ip true false checks whether an interrupt is pending due to the assertion of the VMEbus ACFAIL signal and returns a flag set according to the appropriate interrupt pending flag The flag is true when the interrupt is pending oth erwise its value is false reset acfail irg clears a pending non maskable interrupt generated by the asser tion of the VMEbus ACFAIL signal FORCE COMPUTERS Page 151 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 2 8 VMEbus Master Interface The commands listed below are available to control the VMEbus master interface vme supervisor true false selects the mode in which the VMEbus is being accessed When the value true is passed to the command the VMEbus is accessed in privileged mode Otherwise the value false is passed to the command the VME bus is accessed in non privileged mode vme a32map page returns the number of the 256 Mbyte page page which is being addressed when the VMEbus is being accessed within the extended address space A32 vme a32map page
17. 2 and 3 Memory connector for memory module 2 supports banks 4 5 6 and 7 Memory modules with up to 4 memory banks can be used As shown in the table below the memory bank structure is organized so that memory modules with a bank count from 1 to 4 if available can be used in any combination Each module has up to 4 banks only up to 8 banks in total are allowed A memory module can contain bank A or banks A and B or banks A B and C or bank A B C and D Table 27 Bank Selection Bank Module on Connector 1 Module on Connector 2 Select from Processor Bank A Bank B Bank C Bank D Bank A Bank B Bank C Bank D 0 x 1 x 2 x The shaded area above shows an example of how the banks are selected by the processor In other words the processor can select bank D of the module on connector 1 by its own bank select 3 CAUTION Bank A of memory module on connector 1 must be assembled Page 58 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual 3 3 Memory Module MEM 5 Hardware Description The MEM 5 provides 16 or 64 Mbyte DRAM There are 4 Mbit devices used to realize 16 Mbytes and there are 16 Mbit devices to realize 64 Mbytes The table below shows the board memory capacity and the memory banks used on the microSPARC II In order to understand the structure of the memory make sure you read The Shared Memory on page 58 Table 2
18. Page 13 FORCE COMPUTERS Installation 2 3 Before Powering Up Before powering up please make sure that the default switch settings are all set according to the table below Check these switch settings before powering up the SPARC CPU S5TE because the board is configured for power up according to these default settings For the SPARC CPU 5TE position of the switches on the board please see the diagrams on the previous two pages 2 3 1 Default Switch Settings Table 5 Default Switch Settings f Default Diagram of Switch Switches A Function Setting SW4 1 OFF reserved must be OFF ON 1 7 ko SW4 2 ON reserved must be ON 20 am SW5 1 OFF Test Switch must be OFF ON SW5 2 ON Test Switch must be ON 1 T i 20 gt SW5 3 OFF SCSI Termination for SCSI 2 on P2 3a OFF Enable ON Disable 4o on SW5 4 ON SCSI Termination for SCSI 1 on P2 OFF Enable ON Disable SW6 1 ON Reset Key Control ON Reset Key enable OFF Reset Key disable ON 1 2 SW6 2 ON Abort Key Control ON Abort Key enable OFF Abort Key disable Page 14 FORCE COMPUTERS SPARC CPU 5TE Installation Table 5 Default Switch Settings cont i Default Diagram of Switch Switches 3 Function Setting SW7 1 OFF SCSI 1 termination for Front Panel OFF Automatic When a co
19. They are realized via two MACIO NCR89C100 chips MACIO 1 and MACIO 2 The NCR89C100 has on chip 48 mA drivers and therefore provides direct drive of single ended SCSI bus The SCSI core is a superset of the industry standard NCR53C90A which has been modified to support fast SCSI The SCSI interface is single ended and supports TERMPWR The NCR89C100 DMA2 core is able to transfer the data to and from the shared main memory All signals of the SCSI 1 interface are routed to the VME P2 connector and the front panel All signals of the SCSI 2 interface are routed to the VME P2 connector The connection of SCSI 1 on P1 is compatible to the CPU 2CE CPU 3CE and CPU 5CE The SCSI signals on the VME P2 connector are shown in the table VME P2 Connector Pinout on page 42 3 5 3 SCSI Termination Please note how the SCSI 1 termination works on the front panel Termination for the SCSI 1 interface is disabled when SW7 1 is ON When switch SW7 1 is OFF the termination is set to automatic termination mode Automatic termination mode means the respective termination is disabled when you connect a standard SCSI cable to the connector Termination for the P2 SCSI 1 is disabled when SW5 4 is ON and this is the default setting Termination for the P2 SCSI 2 is enabled when SW5 3 is OFF and this is the default setting FIGURE 13 SCSI Termination V M SWS5 3 controls SCSI 2 termination on P2 E F Off Enable d
20. fl us bo sel sel sel sel sel ash vpp on turns the programming voltage on ash vpp off turns the programming voltage off erprom select page page makes a page one of eight possible 512 KB pages of a USER flash memory available in the flash memory programming window otprom select page page makes a page one of eight possible 512 KB pages of a BOOT flash memory available in the flash memory programming window ect bootprom 1 makes the first BOOT flash memory device available in the flash memory programming window ect bootprom 2 makes the second BOOT flash memory device available in the flash memory programming window ect bootprom device number makes a BOOT flash memory device identified by its device number available in the flash memory programming window The devices are numbered beginning from zero 0 ect userprom 1 makes the first USER flash memory device available in the flash memory programming window ect userprom 2 makes the second USER flash memory device available in the flash memory programming window FORCE COMPUTERS Page 173 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual select userprom device makes a USER flash memory device identified by its device number available in the flash memory programming window The devices are numbered beginning from
21. ni2 csr vaddr returns the virtual address vaddr of the Network Interface 2 Control and Status Register led flash csr vaddr returns the virtual address vaddr of the USER LED and USER Flash Memory Control and Status Register xchg macio ctrl vaddr returns the virtual address vaddr of the Exchange MACIO Control Register flash prg ctrl vaddr returns the virtual address vaddr of the USER Flash Mem ory Programming Control Register hw id vaddr returns the virtual address vaddr of the Hardware Identification Regis ter lca id vaddr returns the virtual address vaddr of the LCA Identification Register 5 2 3 Register Accesses The FORTH words described below are used to read data from and to store data in specific registers of the S4 and VMEbus interface control and status registers s4 bus locker byte returns the contents an 8 bit data of the S4 s Bus Locker Register s4 bus locker byte stores the 8 bit data byte in the S4 s Bus Locker Register s4 intr monitor byte returns the contents an 8 bit data of the S4 s Inter rupt Monitor Register s4 intr monitor byte stores the 8 bit data byte in the S4 s Interrupt Monitor Register s4 mbox intr level byte returns the contents an 8 bit data of the S4 s Mailbox Interrupt Level Register s4 mbox intr level byte stores the 8 bit data byte in the S4
22. s Bus Locker Register when the VMEbus interface is initialised default 0 9 vme fair req specifies whether the VMEbus requester operates in the fair mode when requesting the VMEbus When the value of the configuration parameter is t rue the VMEbus requester operates in the fair mode Otherwise the value of the configura tion parameter is false the requester does not operate in the fair mode default true FORCE COMPUTERS Page 161 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 2 11 Mailboxes The commands described below are available to control the mailbox as well as to retrieve information about the state of the mailbox vme mailbox byte returns the contents an 8 bit data of the S4 s Mail Box Register vme mailbox byte stores the 8 bit data byte in the S4 s Mail Box Register vme mailintr mapping returns the value mapping that indicates the output pin being asserted when the mailbox is accessed from the VMEbus The value of mapping may be one of the values in the range of zero through seven Each value specifies one of the eight S4 interrupt request lines The table below contains a list of all valid mappings and the associated output pin interrupt request line vme mailintr mapping selects the ouput specified by the parameter mapping which is asserted by the S4 when the mailbox is accessed from the VMEbus The value of mapping may be o
23. 0005 gen_purpose1 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO SYSSTAT SYSVME SYSNMIP ABNMIP ROT 3 0 The table on the next page shows the rotary switch settings and the corresponding values of the bits ROT 3 0 which you can read from the gen_purpose1 register FORCE COMPUTERS Page 111 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 60 Rotary Switch Settings Setting ROT 3 ROT 2 ROT 1 ROTO 0 1 1 1 1 1 1 1 1 0 2 1 1 0 1 3 1 1 0 0 4 1 0 1 1 5 1 0 1 0 6 1 0 0 1 7 1 0 0 0 8 0 1 1 1 9 0 1 1 0 A 0 1 0 1 B 0 1 0 0 C 0 0 1 1 D 0 0 1 0 E 0 0 0 1 F 0 0 0 0 Page 112 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 Additional Registers The following additional registers are provided on the CPU STE to increase functionality They are used to control the VMEbus interface the diagnostic LED on the front panel the hardware watchdog timer and flash memories These additional registers are also used to handle level 15 interrupts caused by the Abort key VME SYSFAIL and VME ACFAIL This information on the following pages gives a summary of all additional registers on the CPU STE 3 10 1 Map of Additional Registers The following table shows the register mapping of the additional registers and their reset values
24. 2 is selected FORCE COMPUTERS Page 179 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual In the case that the value of macio is neither one nor two as mentioned above the command assumes that the first MACIO device is selected macio selected macio returns the number of the NCR89105 MACIO device that is currently accessible at the predefined addresses within the SBus slot 5 The NVRAM configuration parameter is available to control which of the two available MACIO devices is available at the predefined addresses within the SBus slot 5 after reset use second macio controls whether the second NCR 89105 MACIO device is acces sible at the predefined addresses within the SBus slot 5 When the value of this config uration parameter is t rue the second MACIO device is accessible at the predefined addresses within the SBus slot 5 Otherwise the value of the configuration parame ter is false the first MACIO device is accessible at the predefined addresses default false tpe link test controls whether to enable or disable the link test capability of the first on board 10baseT ethernet interface TPE When the value of this configuration parameter is t rue the link test capability is enabled Otherwise the value of the configuration parameter is false the link test capability is disabled default true tpe link 2 test controls whether to enable or disable the link test capability o
25. 7 0 These 3 bytes always remain Specific Machine These 2 bytes are 0016 8016 4216 0B for SPARC consecutively CPU STE numbered The 32 bit 4 byte host ID Byte 3 2 1 0 8 0 Y Y Y Y Y Y 32 25 24 16 15 8 7 0 These 8 bits identify The least significant 24 bits contain the the architecture type sum of 8B 7000 machine specific base value and the rightmost 2 bytes of the board s Ethernet address Page 54 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual SECTION 3 3 Board Components Hardware Description HARDWARE DESCRIPTION As is shown in the diagram below the microSPARC II chip interfaces directly to a 64 bit wide DRAM on the one side and to the SBus on the other side The SPARC CPU STE is available with 16 or 64 Mbytes of DRAM modules MEM 5 The shared DRAM is 64 bit wide with 2 bit parity The SPARC CPU STE utilizes the Sun S4 VME chip to provide a complete 32 bit VMEbus interface Using SBus modules the board becomes a VMEbus two slot solution The SCSI 1 the Ethernet 1 and the parallel port are realized via one NCR89C100 MACIO 1 The SCSI 2 and the Ethernet 2 are realized via another NCR89C100 MACIO 2 The floppy disk interface two serial I O ports the keyboard mouse interface are provided by the NCR89C105 chip SLAVIO which additionally controls the boot EPROM the RTC and NVRAM and a user EPROM via its 8 bit expansion port
26. 8 0 19 vme a32map contains the 8 bit data to be stored in the VMEbus interface s VMEbus A32 Map Register when the VMEbus interface is initialised default 19 vme slavemap contains the 8 bit data to be stored in the S4 s Slave Map Register when the VMEbus interface is initialised default 0 9 vme rerun contains the number of VMEbus rerun cycles to be selected Only the least sig nificant five bits of the configuration parameter are considered default 019 vme intena contains the 8 bit data to be stored in the S4 s Interrupt Enable Register when the VMEbus interface is initialised default fe j vme mailintr contains the number of the interrupt level that is asserted when the mailbox is being access from the VMEbus The value of this configuration parameter may range from zero through seven The values one through seven correspond to the seven SBus interrupt request levels 1 to 7 The value zero indicates generation of either a reset or a non maskable interrupt depending on the state of a hardware switch on the SPARC CPU STE Please see Default Switch Settings on page 14 for informa tion about the switches vme mailbox contains the 8 bit data to be stored in the S4 s Mailbox Control Register when the VMEbus interface is initialised default 019 Page 160 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements vme buslock contains the 8 bit data to be stored in the S4
27. BOOT DOCUMENTATION CPU 5TE Technical Reference Manual Page 200 FORCE COMPUTERS Product Error Report PRODUCT SERIAL NO DATE OF PURCHASE ORIGINATOR COMPANY POINT OF CONTACT TEL EXT ADDRESS PRESENT DATE AFFECTED PRODUCT AFFECTED DOCUMENTATION Li HARDWARE I SOFTWARE U1 SYSTEMS LJ HARDWARE LJ SOFTWARE LJ SYSTEMS ERROR DESCRIPTION THIS AREA TO BE COMPLETED BY FORCE COMPUTERS DATE PR RESPONSIBLE DEPT L MARKETING LJ PRODUCTION ENGINEERING LJ BOARD UO SYSTEMS Please send this report to one of our headquarters listed on the back of the title page
28. CD 47 GND 48 SCSI 2 REQ 49 GND 50 SCSI 2 IO FORCE COMPUTERS Installation Page 51 Installation SPARC CPU 5TE Table 23 IOBP DS J3 Pinout Ethernet 1 AUD Pin Function 1 GND 2 Collision 3 Transmit Data 4 GND 5 Receive Data 6 GND 7 N C 8 GND 9 Collision 10 Transmit Data 11 GND 12 Receive Data 13 12VDC 14 GND 15 N C Page 52 FORCE COMPUTERS SPARC CPU 5TE Table 24 IOBP DS J4 Pinout Serial A and B Signal Signal 1 RESERVED 2 RESERVED 3 RESERVED 4 RESERVED 5 TxD Port B 6 TxD Port A 7 RxD Port B 8 RxD Port A 9 RTS Port B 10 RTS Port A 11 CTS Port B 12 CTS Port A 13 GND 14 GND Table 25 IOBP DS J5 Pinout Keyboard Mouse Pin Function 1 GND GND 5VDC Mouse In Keyboard Out Keyboard In N C 5VDC FORCE COMPUTERS Installation Page 53 Installation SPARC CPU 5TE 2 10 How to Determine the Ethernet Address and Host ID In order to see the Ethernet address and host ID type the following command at the prompt ok banner The information below explains how the SPARC CPU STE Ethernet address and the host ID are determined The 48 bit 6 byte Ethernet address Byte 5 4 3 2 1 0 0 0 8 0 4 2 0 B X X X X 47 40 39 32 31 24 23 16 15 8
29. MailBox Interrupt Function A VMEbus interrupt handler supports all interrupt levels These are enabled via bit 4 of the gen_purposez2 register and also via the interrupt enable register within the S4 VME chip Bit 4 in the gen_purpose2 register always overwrites the interrupt enable register if the interrupts should be disabled Writing a zero to bit 4 of the gen_purpose2 register disables the VMEbus interrupts regardless of the contents in the respective S4 VME register This is the value after reset To enable the VMEbus interrupts both registers must be set to enable For a detailed description of the gen_purpose 2 register please see Additional Registers on page 113 A mailbox interrupt function allows other VMEbus participants to interrupt the CPU 5TE This mailbox interrupt can be generated with accesses to the specific A16 address space The mailbox control register and the mailbox interrupt level register in the S4 VME chip controls this interrupt feature The mailbox interrupt can be set in the mailbox interrupt level register to generate either any level of SBus interrupts or an interrupt at the MB_IRQ pin of the S4 VME chip If the mailbox interrupt is gated to the MB_IRQ pin of the S4 VME chip a board reset would result Please refer to Register Accesses to the S4 VME Chip on page 95 and to the data sheet of the S4 VME chip for the detailed description of the interrupt handler and the mailbox interrupt function FOR
30. Manual 3 6 4 RS 232 Hardware Configuration Hardware Description The serial ports A and B are assembled by default for RS 232 operation The following individual I O signals are available for serial ports A and B on the front panel connectors Table 33 Serial Ports A and B Pinout List RS 232 Pin Transmitted Signals Pin Received Signals 2 14 TXD Transmit Data 3 16 RXD Receive Data 4 19 RTS Request to Send 5 13 CTS Clear to Send 7 23 Ground 6 21 SYNC 20 11 DTR Data Terminal Ready 8 12 DCD Data Carrier Detect 24 25 TRXC DTE Transmit Clock 15 18 TRXD DCE Transmit Clock 17 22 RTXC DCE Receive Clock The pinout for serial port A is shown in the white area and the pinout for serial port B is shown in the grey area The table on the next page shows the switch settings for each port FORCE COMPUTERS Page 71 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 34 Switch Settings for Ports A and B RS 232 Port A PortB Default Function for RS 232 SW8 3 SW8 2 ON TRXC is available on front panel connectors pin 24 SW12 4 SW8 1 OFF Off for RS 232 SW9 4 SW8 4 OFF Off for RS 232 SW9 3 SW9 2 ON RTS is available on front panel connectors pin 4 SW12 2 SW9 1 ON CTS is available on front panel connectors pin 5 SW12 3 SW12 1 OFF Off for RS 232 CAUTION To avoid damaging the serial ports please consider the fo
31. a particular pattern The number of bytes to be programmed in the flash memory is given by count erase flash device number erases a flash memory device identified by its device number The devices are numbered beginning from zero 0 c flash byte addr stores the byte at the location within the selected flash memory identified by addr w flash half word addr stores the half word 16 bits at the location within the selected flash memory identified by addr 1 flash word addr stores the word 32 bits at the location within the selected flash memory identified by addr The USER flash memory is prepared for programming by ok select flash USER USER flash memory is selected for programming Flash memory programming window at Sffe98000 size 512 Kbyte 512 Kbyte BOOT flash memory is available at S ffe58000 2048 Kbyte USER flash memory is available ok As shown above the word se lect f lash informs the user that the USER flash memory has been made accessible through the flash memory programming window It displays the base address virtual address of the window and its size The total amount of the available BOOT flash memory and USER flash memory is displayed too After the USER flash memory has been prepared for programming all commands described above operate on the USER flash memory And the BOOT flash memory is only read and programmed by these commands when the BOOT flash memory
32. a24mode true false selects the address range by which the VMEbus slave interface is accessible from the VMEbus When the value true is passed to the com mand the VMEbus slave interface is accessible within the standard address range A24 Otherwise the value false is passed to the command the VMEbus slave interface is accessible within the extended address range A32 vme enhanced mode true false selects the operating mode of the VMEbus inter face When the value true is passed to the command the VMEbus slave interface oper ates in the enhanced mode Otherwise the value false is passed to the command the VMEbus slave interface operates in the default mode vme dvma enable true false checks whether the VMEbus slave interface is ena bled or disabled When the value true is returned the VMEbus slave interface is ena bled Otherwise the value false is returned the VMEbus slave interface is disabled vme dvma enable true false enables or disables the VMEbus slave interface When the value true is passed to the command the VMEbus slave interface is enabled Otherwise the value false is passed to the command the VMEbus slave interface is disabled The following commands require that the NVRAM configuration parameter use new vme is set to false set vme slave def size addr initialises the VMEbus interface to operate in the default slave mode In this mode
33. after and a short description The on line help of the Forth Monitor is located in the boot PROM so there is not an on line help for all forth words Page 34 FORCE COMPUTERS SPARC CPU 5TE Installation 2 6 Front Panel FIGURE 6 Diagram of the Front Panel Wt gt rnw Hnnn le denb OWA ies T 4 ac N Fy FS ies T 4 ac FORCE COMPUTERS Page 35 Installation 2 6 1 Features of the Front Panel Reset and Abort key Status LEDs on the front panel Hex display on the front panel SPARC CPU 5TE These features are described in detail in Section 3 of the SPARC CPU STE Technical Reference Manual 2 7 Page 36 Front Panel Layout Device Function Name Switch Reset RESET Switch Abort ABORT HEX Display Diagnostic DIAG Rotary Switch Diagnostic MODE LED LED Run Halt RUN VME BM SYSFAIL BM LED LED Slavio SYS LED SYS User LED UL Mini DIN Connector Keyboard Mouse KBD Serial Connector Serial Interface A and B SERIAL A B SCSI Connector SCSI Interface SCSI RJ45 Connector Ethernet Interface ETH 2 RJ45 Connector Ethernet Interface ETH 1 FORCE COMPUTERS SPARC CPU 5TE Installation 2 8 SPARC CPU 5TE Connectors The connectors on the SPARC CPU STE are listed in the following table Table 11 SPARC CPU 5TE Connectors
34. command vme free virtual removes the VMEbus area which has been made available previously from the processor s virtual address space vme memmap offset space size vaddr initializes the VMEbus master interface accord ing to the parameters offset and space and returns the virtual address vaddr to be used to access the specified VMEbus area The parameters space and offset describe the VMEbus address area in detail offset specifies the physical VMEbus address of the area to be accessed and space specifies the address space where the VMEbus area is located in The size of the VMEbus area is given by size Page 136 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements Example Assumed a memory board is accessible within the extended A32 VMEbus address space beginning at address 8800 000016 and ranging to 880F FFFF16 1 MByte as shown in the figure below FIGURE 18 Mapping a VMEbus area to the processor s virtual address space VMEbus address space offset 8800 000016 Space vmea32d32 Master window size 1 MByte In order to make this VMEbus area available to the processor s virtual address space the commands listed below have to be used ok O value vme ram ok h 8800 0000 vmea32d32 1Meg vme memmap is vme ram ok The first command defines a variable vme ram which is later used to store the virtual address of the VMEbus area The second command listed above makes 1
35. diag switch is false boot device and boot file are used Otherwise the OpenBoot firmware uses diag device and diag file for booting For a detailed description of all NVRAM configuration parameters please refer to the OPEN BOOT PROM 2 0 MANUAL SET Page 28 FORCE COMPUTERS SPARC CPU 5TE Installation 2 5 3 Diagnostics At power on or after reset the OpenBoot firmware executes POST If the NVRAM configuration parameter diag switch is true for each test a message is displayed on a terminal connected to the first serial port In case the system is not working correctly error messages indicating the problem are displayed After POST the OpenBoot firmware boots an operating system or enters the Forth Monitor if the NVRAM configuration parameter auto boot is false The Forth Monitor includes several diagnostic routines These on board tests let you check devices such as network controller SCSI devices floppy disk system memory clock and installed SBus cards User installed devices can be tested if their firmware includes a selftest routine The table below lists several diagnostic routines Table 9 Diagnostic Routines Command Description probe scsi Identify devices connected to the on board SCSI bus probe scsi all device path Perform probe scsi on all SCSI buses installed in the system below the specified device tree node If device path is omitted the root node is used test device specifier Execute the
36. eesssseesesesesreesrseresresseseresrenss 55 Figure 13 SCST Vermin at On ae a a aan lee Sh ghee e i vee Sade 63 Figure 14 Floppy or SCSI 2 Availability on P2 oe eeeeeseeeseeceseeeseeeeneeesaeenes 74 Figure 15 Front Panelen iernii en eel aa e aa i seS 102 Figure 16 Segments of the Hex Display seeeseeeeesesessesessessresressersrreresserseesressressese 107 Figure 17 Address translation master microSPARC SBus VMEbus 136 Figure 18 Mapping a VMEbus area to the processor s virtualaddress space 137 Figure 19 Address translation slave VMEbus SBus microSPARC 138 Page vi FORCE COMPUTERS CPU 5TE Technical Reference Manual Table of Contents List of Tables Table 1 Specifications of the SPARC CPU STE sige tea titinaiiledeGeaaictieess 4 Table 2 Pr d ct N menclat re eh Seca ee asec ces eeeneted vaca a a a n i 6 Table 3 Ordering Informations icssciciyseesseccsdsacdsscccsseadaass desoaanssdascd a 7 Table 4 Histoty OF Manalo hsrs a e a Ea aa 9 Table 5 Default Switch Settings cisc ccsecassccscsasvackaetsegsacteasncdeve tesceteasveduedesnaenernneesdans 14 Table 6 VME Slot 1 Device Switch Setting ic ste one hae ee ak wees lu vavand stuns 19 Table 7 Device Alias DennitiOns s oiccccks tod cade coeneesiecoindetaianasee 27 Table 8 Setting Configuration Parameters ccesceeseeseecseceseeeseeeescecsaeeneessees 28 Table 9 Diagnostic ROUDES geans t erns leccadedetanacastuactawsahesa
37. has been prepared for these operations by ok select flash BOOT BOOT flash memory is selected for programming Flash memory programming window at Sffe98000 size 512 Kbyte 512 Kbyte BOOT flash memory is available at S ffe58000 2048 Kbyte USER flash memory is available ok To read data from the selected flash memory in the current context from the USER flash memory the command flash gt move is used as follows ok flash va h 10 0000 h 20 0000 flash gt move ok Page 168 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements The contents of the entire USER flash memory is copied to main memory beginning at address 1000001 A specific area within the selected flash memory is read by ok flash va h 6 8000 h 10 0000 h 5 8c00 flash gt move ok and copies 363520 bytes beginning from address flash va 68000 to main memory address beginning at 10000046 FORCE COMPUTERS Page 169 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 4 2 Flash Memory Device The device tree of OpenBoot for the SPARC CPU STE contains a device node associated with the USER flash memories Thus it is possible to load an executable image stored in the available USER flash into memory and start such an executable The device is called flash memory 0 71300000 and is attached to the device node obio The device alias flash is available as an abbreviated representation of the flash me
38. i Default i Diagram of Switch Switches f Function Setting SW13 1 OFF User Flash EPROM write protection ON disable OFF enable ON SW13 2 OFF Boot Flash EPROM write protection 1 ON disable OFF enable 20 SW13 3 OFF ON No function 30 4o SW13 4 OFF ON No function CAUTION To avoid damaging the serial ports please consider the following regarding Switch 8 Switch 9 and Switch 12 Do not set the switches SW8 3 and SW12 4 or SW9 4 and SW9 3 or SW12 2 and SW12 3 to ON at the same time and do not set the switches SW8 2 and SW8 1 or SW8 4 and SW9 2 or SW9 1 and SW12 1 to ON at the same time FORCE COMPUTERS Page 17 Installation SPARC CPU 5TE 2 3 2 Memory Module MEM 5 It is necessary to install the memory module on the board before powering up For instructions on installing the MEM 5 please see the document How to Install MEM 5 Memory Module 1 must be installed for power up because it holds configuration information for booting the board Memory module 2 is optional for increasing memory capacity For the location of the memory module connectors on the board please see Diagram of the CPU 5TE Top View on page 12 Page 18 FORCE COMPUTERS SPARC CPU 5TE Installation 2 4 Powering Up The initial power up can easily be done by connecting a terminal to ttya serial port A The advantage of using a terminal is that no frame buffer monitor or keyboard is used for initial
39. name or alias of the BusNet boot device The OpenBoot provides the following device alias definitions associated with this Page 182 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements device Alias Boot Path Description busnet Aiommu VME BusNet tftp TFTP is used to load program busnet tftp Aommu VME BusNet tftp TFTP is used to load program busnet raw fommu VME BusNet raw pure binary data is loaded raw device NOTE Many commands like boot and test that require a device name accept either a full device path name or a device alias In this documentation the term device specifier is used to indicate that either a device path or a device alias is acceptable for such commands 5 8 3 The BusNet Device The BusNet device is a packet oriented device capable of sending and receiving packets The BusNet device available in OpenBoot is called BusNet and is attached to the device path iommu VME 5 8 3 1 Device Properties Device properties identify the characteristics of the package and its associated physical device The BusNet device is characterized by the properties described below these properties are static name property identifies the package The BusNet package is identified by the string bus net device_type declares the type of the device As the BusNet device is intended for booting across a network VMEbus its device type is declared as network address
40. parameter is zero 0 The set env command is used to set this configuration parameter as shown below ok setenv bn p ip addr 0x83030002 In the example the Internet address 131 3 0 2 83030002 is assigned to the NVRAM configuration parameter bn master en adadr specifies the Ethernet address of the master The Ethernet address is represented by an ASCII string in the following format XX XX XX XX XX XX where XX is a hexadecimal number The setenv command is used to set this config uration parameter as shown below ok setenv bn master en addr 0 80 42 b 10 ac FORCE COMPUTERS Page 195 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual bn p en adadr specifies the Ethernet address of the participant The Ethernet address is represented by an ASCII string in the following format XX XX XX XX XX XX where XX is a hexadecimal number The setenv command is used to set this config uration parameter as shown below ok setenv bn p en addr 0 80 42 b 10 ad Assuming the participant s Ethernet and Internet address are 0 80 42 b 10 ad and 131 3 0 2 and the VxWorks servers Ethernet and Internet address are 0 80 42 b 10 ac and 131 3 0 1 then the NVRAM configuration parameters listed above must be set as described below ok setenv bn master en addr 0 80 42 b 10 ac ok setenv bn master ip addr 0x83030001 ok setenv bn p en addr 0 80 42 b 10 ad ok setenv bn p ip addr 0x83030002 ok setenv bn r
41. program Both aliases contain the argument string t ftp which informs the BusNet device to use the Trivial File Transfer Protocol TFTP to load the program and the BusNet driver replaces the medium access layer MAC which usually is Ethernet ok boot busnet tftp open dev is ihandle load ihandle call method catch ihandle close dev parent device VME The methods available in the VMEbus driver are called from within the BusNet driver especially the methods to map in map out dma alloc etc parent device current device child package 1 For more and detailed information about the boot command and the associated NVRAM configura tion parameters refer to the OpenBoot Command Reference Page 190 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements When the boot command is called as shown in the figure above OpenBoot tries to locate the specified device in its device tree and opens each node of the device tree in turn starting at the top until the BusNetBusNet device is reached Assuming the TFTP protocol is used to load the program the BusNet driver tries to open the package obp tftp provided by OpenBoot and returns control to the boot command after the execution of its open method is complete In the next step the boot command calls the BusNet driver s Load method which in turn calls the load method of the TFTP package to load the program During the time the progr
42. tape drive SCSI ID 4 tapeO iommu sbus espdma esp st 4 0 First tape drive SCSI ID 4 tapel iommu sbus espdma esp st 5 0 Second tape drive SCSI ID 5 cdrom iommu sbus espdma esp sd 6 0 d CD ROM partition d SCSI ID 6 net iommu sbus ledma le Ethernet floppy obio SUNW fdtwo Floppy drive FORCE COMPUTERS Page 27 Installation SPARC CPU 5TE 2 5 2 NVRAM Boot Parameters The OpenBoot firmware holds configuration parameters in NVRAM At the Forth Monitor prompt type printenv to see a list of all available configuration parameters The OpenBoot command setenv may be used to set these parameters setenv configuration parameter value This information refers only to those configuration parameters which are involved in the boot process The following table lists these parameters Table 8 Setting Configuration Parameters Parameter Default Value Description auto boot true If true boot automatically after power on or reset boot device disk Device from which to boot boot file empty string File to boot diag switch false If true run in diagnostic mode diag device net Device from which to boot in diagnostic mode diag file empty string File to boot in diagnostic mode When booting an operating system or another stand alone program and neither a boot device nor a filename is supplied the boot command of the Forth Monitor takes the omitted values from the NVRAM configuration parameters If the parameter
43. that the S4 asserts its FORCE COMPUTERS Page 159 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual SBus interrupt request line 5 when a VMEbus interrupt request level 5 occurs Only the least significant three bits of this value are considered default 2559 vme intr controls whether the VMEbus interrupt request level 6 has to be enabled When this flag is 255 then the VMEbus interrupt request level 6 is not enabled In the case that the value is six 6 the corresponding interrupt handler is activated and the VME bus interrupt request level 6 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 6 when a VMEbus interrupt request level 6 occurs Only the least significant three bits of this value are considered default 25519 vme intr7 controls whether the VMEbus interrupt request level 7 has to be enabled When this flag is 255 then the VMEbus interrupt request level 7 is not enabled In the case that the value is seven 7 the corresponding interrupt handler is activated and the VMEbus interrupt request level 7 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 7 when a VMEbus interrupt request level 7 occurs Only the least significant three bits of this value are considered default 25519 vme control contains the 8 bit data to be stored in the VMEbus interface s VMEbus Con trol Register when the VMEbus interface is initialised default
44. the command treats it as if the value one has been passed to the command install vme intr handler mapping level installs the interrupt service routine dealing with the given VMEbus interrupt level The parameter mapping defines the interrupt request line asserted by the S4 when a certain VMEbus interrupt request level is asserted The value of mapping may be one of the values in the range of one through seven Each value specifies one of the seven S4 interrupt request lines The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VMEbus interrupt request levels The address of the interrupt service routine currently in effect is preserved Only the least significant three bits of mapping and level are considered and when level is zero then the command treats it as if the value one has been passed to the command Because the VMEbus interface on the SPARC CPU STE does not allow to map a VMEbus interrupt to any SBus interrupt level the values of mapping and level passed to the command must be the same To enable the VMEbus interrupt request level 2 the parameters listed in the example below have to be passed to the command ok 2 2 install vme intr handler ok uninstall vme intr handler level removes the interrupt service routine deal ing with the given VMEbus interrupt level and installs the old interrupt service routine The value of level may be one of t
45. the particular word The OpenBoot ported to the SPARC CPU STE is based upon the OpenBoot 2 15 obtained from Sun Microsystems FORCE COMPUTERS Page 133 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 1 Controlling the VMEbus Master and Slave Interface The descriptions in the following require that the NVRAM configuration parameter use new vme is set to true 5 1 1 VMEbus addressing The VMEbus has a number of distinct address spaces represented by a subset of the 64 possible values encoded by the 6 address modifier bits The size of the address space depends on the particular address space for example the standard A24 address space is limited to 16 MByte whereas the extended A32 address space allows to address 4 GByte An additional bit which corresponds with the VMEbus LWORD signal is used to select between 16 bit and 32 bit data A physical VMEbus address is represented numerically by the pair phys high also called space and phys low also called offset The phys high consists of the 6 address modifier bits AMO through AM5 corresponding with bit 0 through 5 and the data width bit LWORD 0 16 bit data 1 32 bit data in bit 6 OpenBoot provides a number of constants combining the information mentioned above These constants are called AML constants AML is the combination of the first letters of the words Address Modifier and LWORD Each AML constant specifies a unique address space
46. the value false is returned Page 166 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 4 Flash Memory Support 5 4 1 Flash Memory Programming The commands listed below are available to access and program the flash memories available on the SPARC CPU STE flash messages vaddr returns the virtual address of the variable flash messages The state of this variable controls whether the words to erase and program the flash memories will display messages while erasing or programming the flash memories Messages will not be displayed after turning off this variable by flash messages off They are displayed after turning on this variable by flash messages on flash va vaddr returns the virtual base address vaddr of the flash memory programming window The virtual address returned is only valid when the flash memories have been previously prepared for access using the se lect flash word boot flash va vaddr returns the virtual base address vaddr of the BOOT flash memory user flash va vaddr returns the virtual base address vaddr of the USER flash memory When the USER flash memory is not accessible directly but only through the flash memory programming window then the address returned is zero On the SPARC CPU STE the USER flash memory is accessible only through the flash memory programming window Thus the commands described above have to be used to access the USER flash me
47. zero 0 5 5 On board Interrupts Besides the interrupt handlers already available in the standard OpenBoot the OpenBoot of the SPARC CPU STE provides additional handlers that deal with the interrupts generated by the following e one of the VMEbus interrupt levels one to seven e the assertion and negation of the SYSFAIL signal e the assertion of the ACFAIL signal e pressing the ABORT switch e the watchdog timer when half the time has expired 5 5 1 VMEbus Interrupts The interrupt handlers for any VMEbus interrupt are not installed automatically by OpenBoot however appropriate words are available to activate and deactivate an interrupt handler serving a specific VMEbus interrupt Such an interrupt handler is activated by ok 0 pil ok 3 5 install vme intr handler ok The pil command decreases the processor interrupt level to allow the processor to respond to all interrupts By default OpenBoot sets the mask to 13 and allows the processor to respond to interrupts above interrupt level 13 The second command installs the interrupt handler that deals with the VMEbus interrupt level 5 Furthermore this command specifies that an SBus interrupt level 3 will be generated upon the occurrence of a VMEbus interrupt 5 Any of the seven SBus interrupt levels may be specified to be generated upon a VMEbus interrupt OpenBoot maintains seven variables called vme intr 1 2 3 4 5 6 7 vector which are modified by the VMEbus interrupt hand
48. 1 0 Min Typical Max Default BERR 00 1 4 ms 1 5 ms 1 6 ms 7 BERR 01 190 us 200 us 210 us BERR 10 48 us 52 us 60 us BERR 11 10 us 13 us 15 us 3 7 10 VMEbus Transaction Timeout Control Register Physical Address Register Name Read Write Access 713C 0003 Timeout Control r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TIMEOUT 1 0 1 1 1 1 1 1 When the S4 operates as system controller the VMEbus transaction timer 2 4 us of the S4 supersedes the transaction timer of the LCA Page 100 FORCE COMPUTERS SPARC CPU STE Technical Reference Manual Hardware Description 3 8 Front Panel The figure on the next page shows a diagram of the front panel The connectors which are listed below are described in Section 2 Installation The Reset and Abort functions are described on the following pages Table 57 Features of the Front Panel Device Function Name Switch Reset RESET Switch Abort ABORT HEX Display Diagnostic DIAG Rotary Switch Diagnostic MODE LED LED Run Halt RUN VME BM SYSFAIL BM LED LED Slavio SYS LED SYS User LED UL Mini DIN Connector Keyboard Mouse KBD Serial Connector Serial Interface A SERIAL A B and B SCSI Connector SCSI 1 Interface SCSI RJ45 Connector Ethernet Interface ETH TP 2 RJ45 Connector Ethernet Interface ETH TP 1 FORCE COMPUTERS Page 101 Hardware Description SPARC CPU S5TE Technical Reference Manual FIGURE 15 Fr
49. 138 0004 vme_a32map r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bit0 FL_PAG VPPCTL WTENA WNMIP VME _A 31 28 FORCE COMPUTERS Page 79 Hardware Description SPARC CPU S5TE Technical Reference Manual The next page contains a list of the flash memory programming control bits Table 39 Flash Memory Programming Control Bits BT_US FL PAG US_DEV Programs 1 0 don t care Boot EPROM Dev 1 with 256 KB 1 1 don t care Boot EPROM Dev 2 with 256 KB 1 0 don t care Boot EPROM Dev 1 with 512 KB 1 1 don t care Boot EPROM Dev 2 with 512 KB 0 0 0 User EPROM first 512 KB of Dev 1 0 1 0 User EPROM second 512 KB of Dev 1 0 0 1 User EPROM first 512 KB of Dev 2 0 1 1 User EPROM second 512 KB of Dev 2 Initialization BT_US FL_PAG and US_DEV are all cleared to Os after reset For the detailed description of all additional register bits on the CPU STE please also read the chapter Additional Registers on page 113 Page 80 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual 3 6 12 2 Enhanced CPU 5TE Mode Hardware Description On the CPU 5TE you can decide whether you want to access the User Flash memory in default CPU 5CE mode or enhanced CPU 5TE mode When enhanced the CPU 5TE mode is chosen DEV_SEL 2 0 selects one of the eight User Flash memory devices as is shown in the table
50. 2 r w 8 bit and Status Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bit0 1 1 1 1 1 1 TP2 TP2 STAT TEST NOTE TP2_STAT is a read only bit Setting Function TP2_STAT 1 Link is up for Ethernet 2 for twisted pair TP2_STAT 0 Link is down for Ethernet 2 for twisted pair if TP2_TENA is set 1 Setting Function TP2_TENA 1 Link Test is enabled for Ethernet 2 for twisted pair TP2_TENA 0 Link Test is disabled for Ethernet 2 for twisted pair FORCE COMPUTERS Page 127 Hardware Description 3 10 13 SPARC CPU S5TE Technical Reference Manual User LED and User Flash Memory Control and Status Register This register is used to control the User LED and to query the status of the User Flash memory It is also possible to check whether the Floppy Disk Interface or SCSI is available on VME P2 Physical f A Address Register Name Read Write Access 713C 0002 User LED and r w 8 bit User Flash Memory Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 1 1 1 FLASH FDD COLOUR 1 0 RDY SCSI NOTE FLASH RDY and FDD SCSI are read only bits Setting Function FLASH_RDY 1 User Flash memory ready for programming FLASH_RDY 0 Last programming or erasure command has to be finished before a new command can be sent Setting Function FDD_SCSI 1 SCSI bus of the second MACIO is available on VME P2 FDD_SCSI 0 Fl
51. 3c ss05 8 hi tiesse Beside esheets aoa Asad nie 43 2 8 5 1 Jumper Setting for IOBP 10 00 ec eeeeecseeceeeseecaecaecaecaeeeesseeeeens 43 VORA JOBR DS ok chit asd ees scaets sheets E ee eee kent Me tA sets toed eae St 48 2 9 1 Jumper Setting for IOBP DS oo ee eee eeeeeeeeeeeseecaeesaecaecsaecaecaeeeeseseeseeeeeeseneeeas 48 2 9 2 TOBP DS P2 Connector Pinout seenior E aE EEE aE aE EEE e 49 2 10 How to Determine the Ethernet Address and Host D cecccccsccesssceceesececeneeeecseeeeeseeeessaeeees 54 SECTION 3 HARDWARE DESCRIPTION eeesesseseserecsesosoesesesocoesosorsesesosoesosorsesesese D 331 The microS PARC Proces SOL je retien ere aE e a e ENE a a E E E ah coos ES 56 3 1 1 Features of the microSPARC II Processor oo eee cecesceceseeeeceseeeeeeseeeeeeseeenessaeeaeenaes 56 3 1 2 Address Mapping for microOSPARC I oo eee ce ceseceeceseeeeeeseeeeeeseeeeeeseecaecsaeeaeenaes 57 3 2 The Shared Memory ois ic cc 3s55 eds csapssssuacheshosstssas sgeusescyasssdbsseastaspes seuss sE OE stan teesdesbas ssensesvsashenensessesy 58 3 3 Memory Module MEM S ieena e r Se EEES EE scutes EEE EE SEEE E 59 3 4 S Bus Participants o re eiea a EEE aE E E E E ET EE er EEE E EE 60 3 4 1 Address Mapping for SBus Slots on the SPARC CPU STE seseseseeeeerererererssreeesree 60 3 5 NCR89C100 MACIO 1 and MACIO 2 oon eee eeceeeceeceeeeeeceeeeceecaeeeeecaeesaecaaesaesnecnseensesees 61 3 5 1 Features of the NCR89C100 on the SPARC CPU STE uo ecee
52. 5TE Technical Reference Manual OpenBoot Enhancements bn p mbox access specifies the access mode of the participant s mailbox The property s size is 32 bits integer bn p mbox intr specifies the interrupt generated when the participant s mailbox is being accessed from the bus The property s size is 32 bits integer bn p mbox specifies whether the participant provides a mailbox When the value of this property is true then the participant provides a mailbox Otherwise the participant does not provide a mailbox 5 8 3 2 Device Methods The BusNet device intended for use by OpenBoot implements the methods described below open ok prepares the device for subsequent use The value t rue is returned upon suc cessful completion otherwise the value false is returned to indicate a failure When open is called the parent instance chain has already been opened and this method may call its parent s methods Typically the device builds up its BusNet region makes this region available to the VMEbus address space and tries to connect with the BusNet master for registering close restores the device to its not in use state Typically it informs all known BusNet participants about its intention to withdraw from the protocol and disables its VME bus slave interface to prevent it from being accessed by other BusNet participants reset puts the device into its quiescent state and afterwards starts to register with
53. 8 MEM 5 Memory Banks at Memory Banks ee A and B are Used Capacity 16 Mbytes X 64 Mbytes X How to install a memory module on the CPU STE is described in the document How to Install MEM S which is available from FORCE COMPUTERS FORCE COMPUTERS Page 59 Hardware Description 3 4 SBus Participants SPARC CPU S5TE Technical Reference Manual There are two SBus slots located on the component side of the board SBus Slot 1 is located at connector P3 and SBus Slot 2 is located at connector P4 For the position of the slots on the board please see the Diagram of the CPU 5TE Top View on page 12 The microSPARC II chip supports up to 5 SBus slots plus an additional master only slot The SBus controller is inside the microSPARC II chip The following table shows the microSPARC II physical address map including all of its SBus slots and their functions on the SPARC CPU STE 3 4 1 Address Mapping for SBus Slots on the SPARC CPU 5TE The table below shows the physical memory map of SBus on the SPARC CPU STE Table 29 Physical Memory Map of SBus on SPARC CPU 5TE SBus Slave Select Addresses Function Number 30000000 gt SBus slave select 0 Not usable 37FFFFFF 38000000 gt SBus slave select 0 NCR89C100 MACIO 2 3BFFFFFF chip 3C000000 gt SBus slave select 0 Not usable 3FDFFFFF 3FE00000 gt SBus slave select 0 S4 VME Chip Registers 3FFF FFF
54. Adds Name Read Write Access 7138 0006 led_display w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 DP SEG_G SEG_F SEG_E SEG_D SEG_C SEG_B SEG_A FORCE COMPUTERS Page 123 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 10 10 gen_purpose2 Register The gen_purpose2 register combines various functions such as controlling the programming of the flash memories VME ACFAIL control hardware watchdog support NMI level 15 enable VMEbus DVMA enable Physical Register Address Name Read Write Access 7138 0007 gen_purpose2 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bit0 WNMIR ACSTAT ACNMIR ACNMIP DVMA_ENA IRQI5_ENA US_DEV BT_US Initialization Bits 4 0 are cleared to Os at reset Description BT_US and US_DEV supports in conjunction with FL_PAG of the gen_purpose register the programming of the flash memory devices They select a 512 Kbyte page within the Boot EPROM area or the User EPROM area Please refer to chapter Programming Control Bits for Flash Memory Devices on page 79 for the settings of BT_US and US_DEV IRQ15_ENA controls the capability to generate a non maskable interrupt with level 15 by the Abort Key SYSFAIL ACFAIL and the Hardware Watchdog Timer Setting Function IRQ15_ENA 0 Disables NMI capability of Abort Key SYSFAIL ACFAIL and the Hardware Watchdog Timer IRQ15_ENA 1 Ena
55. Before installing the SPARC CPU STE in a miniforce chassis please first disable the VMEbus System Controller function by setting switch SW10 2 to OFF FORCE COMPUTERS Page 19 Installation SPARC CPU 5TE 2 4 2 VMEbus SYSRESET 2 4 2 1 SYSRESET Input A SYSRESET received from VMEbus generates an on board RESET if switch SW11 1 is ON default setting When SW11 1 is OFF the SYSRESET received from the VMEbus does not generate an on board RESET 2 4 2 2 SYSRESET Output There are several possible ways for the CPU 5TE to generate a SYSRESET signal to the VMEbus One way is when the CPU 5TE is a VMEbus slot 1 device and an on board local SBus reset occurs then the CPU 5TE generates the SYSRESET signal to the VMEbus A second way for the SYSRESET signal to be generated is by power up reset Power up reset occurs by switching on the power Power up Reset also occurs when the power monitor detects power fail or the front panel reset key is toggled This SYSRESET signal can be disabled by setting the switch SW11 2 to OFF 2 4 3 Serial Ports By default both serial ports are configured as RS 232 interfaces The chapter Default Switch Settings on page 14 shows the necessary switch settings for RS 232 operation Page 20 FORCE COMPUTERS SPARC CPU 5TE Installation 2 4 4 RESET and ABORT Key Enable To enable the RESET and the ABORT functions on the front panel set switches SW6 1 RESET and SW6 2 ABORT to ON This is the default setting
56. Bit3 Bit2 Bitl BitO 1 1 1 1 1 1 TP2 TP2 STAT TENA Table 31 Network Interface 2 Control And Status Register Read Setting Write Function TP2_TENA 0 r w Link Test enabled TP2_TENA 1 r w Link Test disabled TP2_STAT 0 T AUI 2 selected or LinkTest 2 disabled or Link for TP 2 failed TP2_STAT 1 r TP 2 selected LinkTest enabled and Link for TP 2 succeeded 3 5 6 Parallel Port The availability of the parallel port is dependent upon the availability of a 5 row P2 connector When using a 3 row P2 connector the parallel port is not available Page 66 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Hardware Description 3 6 NCR89C105 SLAVIO The NCR89C105 SBus slave integrates most of the 8 bit system I O functions including two dual channel 8530 compatible serial controllers a high speed 8277AA 1 compatible floppy disk controller counter timers interrupt controllers and system reset logic It also provides an SBus interface for several other byte wide peripherals through an external expansion bus The primary serial controller is 8530 compatible and can be used as two general purpose serial ports The second serial controller is subset of the 8530 standard and is dedicated for the keyboard mouse connection The 8277AA 1 compatible floppy disk controller supports up to 1 Mbit sec data transfer rate To reduce part count and system cost a g
57. CE COMPUTERS Page 93 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 7 5 VMEbus System Controller The SPARC CPU STE can be plugged into any VMEbus slot however the default configuration automatically detects that the board is a VME slot 1 device which functions as VME System Controller To configure your CPU STE so it is not a VME slot 1 device the default configuration must be changed so that SW10 2 is OFF Features of the VMEbus System Controller e Single level or round robin arbitration with bus arbiter timer e IACK Daisy Chain driver e SYSCLK Clock driver e SYSRESET driver Please refer to the data sheet of the S4 VME chip for additional information about the S4 VME system controller CAUTION Before installing the SPARC CPU STE in a miniforce chassis please first disable the VMEbus System Controller function by setting switch SW10 2 to OFF Page 94 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 7 6 Register Accesses to the S4 VME Chip All registers of the S4 VME chip are located in the SBus Slave Select 0 address range starting with the physical base address shown in the next table Table 50 S4 VME Chip Physical Address Map Physical Base Address Name Function 3FE0 0000 SBus Slave S4 VME Chip Registers Select 0 For the offsets of all S4 VME chip registers please refer to the S4 VME chip data sheet NOTE The physical address descri
58. CPU STE bottom view showing the position of five of the on board switches FORCE COMPUTERS Page 11 Installation SPARC CPU 5TE FIGURE 2 Diagram of the CPU 5TE Top View J 124 SW10 amin HEF e e Lowers Reset e es e id 3 Twit Boot Flash Abort of bd gt Memor SPARC II a2 8 See erz J peemient 2 ft SH Display xz e e e Tatu e a J125 e Rotary e Status LEDs e User LEDs s aannam er A g ses jeo Mouse z Z 2 s4vME Ei fee 3 Z FEHER 3 gt E jeooo Q iS Z m z m eee 2 g e x a EE e A and B 5 bls 5 Ueancencauecovcaenncanocarannannt HIRE UU S m N Serial Port z 7 lt B2 B3 B1 S f A PBI e B10 B9 B8 LEU AEE z A H SW11 c are the sockets for Seis 5 SCSI 2 Floppy iS S Switch Matrix Ei z NCR89C105 B28381 8 ae BE sw7 SLAVIO e TT oY A SCSI 1 ANABDOADONDEOOL OONDE IAD IOONE DC TTAN MN F k AE h sj Z lelele NCR89C100 Z 5 E Bist MACIO Z Piia 8 8 2 Eig Twisted E Pair MACAOAONOOSOROODOOTCONEODE TIONG FA Ethernet 2 wtona B10 B988 E ON xe im A E a H Twisted NCR89C100 B i E oe macao B He Ethernet 1 1 gt Page 12 FORCE COMPUTERS Installation SPARC CPU 5TE Diagram of the CPU 5TE Bottom View FIGURE 3 t eee eee s e
59. DTR_B 32 DCD_A 5V DCD_B FORCE COMPUTERS Installation Page 49 Installation Page 50 Table 21 IOBP DS J1 Pinout SCSI 1 any Signal oy Signal 1 GND 2 SCSI 1 Data 0 3 GND 4 SCSI 1 Data 1 5 GND 6 SCSI 1 Data 2 7 GND 8 SCSI 1 Data 3 9 GND 10 SCSI 1 Data 4 11 GND 12 SCSI 1 Data 5 13 GND 14 SCSI 1 Data 6 15 GND 16 SCSI 1 Data 7 17 GND 18 SCSI 1 DP 19 GND 20 GND 21 GND 22 GND 23 GND 24 GND 25 N C 26 TERMPWR 1 27 GND 28 GND 29 GND 30 GND 31 GND 32 SCSI 1 ATN 33 GND 34 GND 35 GND 36 SCSI 1 BSY 37 GND 38 SCSI 1 ACK 39 GND 40 SCSI 1 RST 41 GND 42 SCSI 1 MSG 43 GND 44 SCSI 1 SEL 45 GND 46 SCSI 1 CD 47 GND 48 SCSI 1 REQ 49 GND 50 SCSI 1 IO SPARC CPU 5TE FORCE COMPUTERS SPARC CPU 5TE Table 22 IOBP DS J2 Pinout SCSI 2 Signal Signal 1 GND 2 SCSI 2 Data 0 3 GND 4 SCSI 2 Data 1 5 GND 6 SCSI 2 Data 2 7 GND 8 SCSI 2 Data 3 9 GND 10 SCSI 2 Data 4 11 GND 12 SCSI 2 Data 5 13 GND 14 SCSI 2 Data 6 15 GND 16 SCSI 2 Data 7 17 GND 18 SCSI 2 DP 19 GND 20 GND 21 GND 22 GND 23 GND 24 GND 25 N C 26 TERMPWR 2 27 GND 28 GND 29 GND 30 GND 31 GND 32 SCSI 2 ATN 33 GND 34 GND 35 GND 36 SCSI 2 BSY 37 GND 38 SCSI 2 ACK 39 GND 40 SCSI 2 RST 41 GND 42 SCSI 2 MSG 43 GND 44 SCSI 2 SEL 45 GND 46 SCSI 2
60. E Interrupt Handler e Programmable Mailbox Interrupt Level e VMEbus Bus Timer 3 7 2 Master Interface The VME master interface allows A32 A24 and A16 mode addressing with D8 even odd D16 and D32 mode data transfers A full 4 Gbyte address range is available by mapping a 256 Mbyte SBus slot window Unaligned transfers and block mode transfers are not supported 3 7 2 1 VMEbus Master Address Implementation The VMEbus master interface is physically located in the SBus Slave Select 3 address range FORCE COMPUTERS Page 83 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 41 VMEbus Master Interface Physical Address Map Physical A Address Name Function 6000 0000 SBus Slave VMEbus Master 6FFF FFFF Select 3 Interface The 4 bit base address for the 256 Mbyte boundary is set in the vme_a32map register The four upper VMEbus address lines A31 A28 can be programmed in that register Physical Register Adare Namie Read Write Access 7138 0004 vme_a32map r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO FL_PAG VPPCTL WTENA WNMIP VME _A 31 28 Initialization At reset VME_A 31 28 are cleared to Os CAUTION The vme_a32map register is not identical with the A32_map register of the S4 VME chip For the programming of the VMEbus master address the A32_map register of the S4 VME chip is not used Pa
61. EES EEE PENEN R ESS 148 5 21 VMEb s Status Signals sin eneses eee ceeecesceseeeeceseeeeeeseeeaeeseecaecsaecaecsaesaecsaeesesnseeseesees 150 5 2 8 VMEbus Master Interface asire rosne a eE E NEE EREA KERNE 152 5 2 9 VMEbus Slave Interface sieners sestese Ti esot ers beresi esise ep aTa rs T EEs 154 5 210 VMEbus Device Node e si cdeecischestescbeai Sissies crete ie de p E EEKE EAE E EEEE EA 157 5 211 Mar lbOxes sre aiie aaa e E EE E aE AE a uel ATRE ESS 162 5 3 System Contig tration e008 hos p ees BSR AEG BES adie SI EA ek 163 33E WatehdO ge TIME cps Sevee dis eubogis oases segues E E E RE aE E n eeo R EES n 163 D32 Abort SM E e E a ae 165 5 3 3 Seven Segment LED Display and Rotary Switch essesssseeeessreessseesrerserrrrserersreersreee 165 SRR R ERTE ia Er EEEE EE TN 166 3 4 Flash Memory Support e er serete r E E E E E EE O EEE R 167 S41 Flash Memory Programming sissen nid aes a aae a E ess 167 5 4 3 Loading and Executing Programs from USER Flash Memory ce eeeeeeeeeeeee 172 5 4 4 Controlling the Flash Memory Interface o oo eee cree eeecneeeaeceseesececesecesenseeeeees 173 5 3 On board Interrupts si eeaeee aae E eE E EEEE oe SEE Te EE aSa te 174 2 1 VMEbus Interrupts csn reniet otesi EE cic EA EE EA EE 174 5 3 2 SYSFAIL Tnterrupt ireen ria aesae hci heroas e EEA E Eoas oni 175 D3 ACFAIL Interrupt n n e a eG a ee ae ANRE 176 Page iv FORCE COMPUTERS CPU S5TE Technical Reference Manual Table of Conten
62. F 4000 0000 gt SBus slave select 1 SBus Slot 1 4FFF FFFF 5000 0000 gt SBus slave select 2 SBus Slot 2 5FFF FFFF 6000 0000 gt SBus slave select 3 VMEbus Interface 6FFF FFFF 7000 0000 gt SBus slave select 4 NCR89C105 SLAVIO chip 77FF FFFF 7800 0000 gt SBus slave select 4 NCR89C100 MACIO 1 7FFF FFFF chip Page 60 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 5 NCR89C100 MACIO 1 and MACIO 2 There are two MACIO NCR89C100 chips on the CPU S5TE MACIO 1 is located on SBus Slave Select 4 at physical address 7800 0000 This chip drives the SCSI 1 Ethernet 1 and Centronics parallel port MACIO 2 is located on SBus Slave Select 0 at physical address 3800 0000 This chip drives the SCSI 2 and Ethernet 2 The NCR89C100 SBus master integrates high performance I O macrocells and logic including an Ethernet controller core a fast 53C9X SCSI core a high speed parallel port a DMA2 controller and an SBus interface The Ethernet core is compatible with the industry standard 7990 Ethernet controller The SCSI core is a superset of the industry standard NCR53C90A which has been modified to support fast SCSI The uni bi directional parallel port is Centronics compliant and can operate in either programmed I O or DMA mode The DMA2 block comprises the logic used to interface each of these functions to the SBus It provides buffering for each of the functions Buffer
63. F the User Flash EPROMsS are write protected and this is the default setting 2 4 9 Reserved Switches SW5 1 SW5 2 SW7 2 SW8 1 SW10 1 and SW 12 4 are reserved for test purposes SW5 1 SW7 2 SW8 1 SW10 1 and SW12 4 should always be OFF SW5 2 should always be ON Page 22 FORCE COMPUTERS SPARC CPU 5TE Installation 2 4 10 Floppy Interface or SCSI 2 Availability on P2 It is important to understand that the availability of both the floppy and SCSI 2 devices at the same time is dependent upon the availability of a 5 row P2 connector When using a 3 row P2 connector you have the choice of either the floppy or the SCSI 2 on P2 The following describes how to configure the board for floppy or SCSI 2 Via a 24 pin configuration switch matrix it is possible for either the floppy interface or the SCSI 2 to be available on the VME P2 connector on row C The default setting enables the floppy interface via the VME P2 connector with the configuration switch matrix plugged into B2 B3 and B10 B9 This means of course that by default the SCSI 2 is not available via the VMEbus P2 connector on row C To enable the SCSC 2 via the VME P2 connector plug the configuration switch matrix in sockets B3 B1 and B9 B8 FIGURE 5 Floppy or SCSI 2 Availability on P2 B2 B3 B1 This 3 piece configuration switch matrix is used for choosing either the floppy interface or SCSI 2 a Plug the interface into sockets B2 B3 and B10 B9 for the
64. GND SCSI 1 RST GND TERMPWR 2 SCSI 2 REQ 21 CENTR BSY SCSI 1 MSG GND GND SCSI 2 IO 22 GND SCSI 1 SEL ETH REC ETH 1_REC CENTR SLCTIN 23 CENTR PE SCSI 1 CD ETH 1_REC ETH 1_REC MOUSEOUT 24 GND SCSI 1 REQ ETH 1_TRA ETH 1_TRA ETH 2_POW 25 CENTR AF SCSI 1 IO ETH 1_TRA ETH 1_TRA ETH 2_REC 26 GND MOUSEIN ETH 1_COL ETH 1_COL ETH 2_REC 27 CENTR INIT TXD_KBD ETH 1_COL ETH 1_COL ETH 2_TRA 28 GND RXD_KBD GND GND ETH 2_TRA 29 CENTR ERR TXD_A TXD_B TXD_B ETH 2_COL 30 GND RXD_A RXD_B RXD_B ETH 2_COL 31 CENTR SLCT DTR_A DTR_B DTR_B NC 32 GND DCD_A DCD_B DCD_B NC Page 42 FORCE COMPUTERS SPARC CPU 5TE Installation 2 8 5 The IOBP 10 Connectors The IOBP 10 is an I O back panel on VMEbus P2 with flat cable connectors for SCSI serial I O Centronics floppy interface and a micro D Sub connector for the Ethernet 1 interface The Centronics interface on the IOBP 10 is not supported by the CPU 5TE This back panel can be plugged into the VMEbus P2 connector The diagram below shows all the connectors The IOBP 10 back panel and the IOBP DS are especially designed for the SPARC CPU STE Do not use any other I O back panels on the SPARC CPU STE for example the IOBP 1 2 8 5 1 Jumper Setting for IOBP 10 Please make sure that the configuration switch matrix is plugged into sockets B2 B3 and B10 B9 that is the configuration for floppy interface on P2 This is described in chapter Floppy Interface or SCSI 2 Availability
65. MByte beginning at physical address 8800 000016 within the extended A32 VMEbus address space available to the processor s virtual address space The virtual address returned by the command is stored in the variable vme ram which has been defined by the first command value The variable vme ram may be used later to access this VMEbus area vme free virtual vaddr size removes the VMEbus area associated with the vir tual address vaddr from the processor s virtual address space The VMEbus area previously made available to the processor s virtual address space is removed from the virtual address space using the vme free virtual command as shown below ok vme ram 1Meg vme free virtual ok FORCE COMPUTERS Page 137 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 1 3 VMEbus Slave Interface As shown in the figure below the VMEbus interface responds to unique VMEbus addresses and translates these addresses to virtual SBus addresses The IOMMU translates these virtual SBus addresses to physical addresses which address a certain area within the on board memory FIGURE 19 Address translation slave VMEbus SBus microSPARC VMEbus address space VMEbus SBus addresses addresses Slave VMEbus window interface Physical addresses Virtual addresses Processor microSPARC I II processor The processor accesses the same on board memory by applying vir
66. MEbus Slave Base Register 2 vme slavebase3 vaddr returns the virtual address vaddr of the VMEbus interface s VMEbus Slave Base Register 3 vme ctril vaddr returns the virtual address vaddr of the VMEbus interface s VME bus Control Register vme a32 map vaddr returns the virtual address vaddr of the VMEbus interface s VMEbus A32 Map Register vme gpr1 vaddr returns the virtual address vaddr of the VMEbus interface s VME bus General Purpose Register 1 vme gpr2 vaddr returns the virtual address vaddr of the VMEbus interface s VME bus General Purpose Register 2 The commands described below are used to obtain the virtual addresses of specific system configuration registers abort ctrl vaddr returns the virtual address vaddr of the ABORT Control Regis ter flash wdt csr vaddr returns the virtual address vaddr of the FLASH Memory and Watchdog Timer Control and Status Register led display vaddr returns the virtual address vaddr of the Seven Segment Display Control Register gpr1 vaddr returns the virtual address vaddr of the General Purpose Register 1 FORCE COMPUTERS Page 141 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual gpr2 vaddr returns the virtual address vaddr of the General Purpose Register 2 nil csr vaddr returns the virtual address vaddr of the Network Interface 1 Control and Status Register
67. MEbus generates an on board RESET if switch SW11 1 is ON default setting When SW11 1 is OFF the SYSRESET received from the VMEbus does not generate an on board RESET 3 7 8 2 SYSRESET Output There are several possible ways for the CPU 5TE to generate a SYSRESET signal to the VMEbus One way is when the CPU 5TE is a VMEbus slot 1 device and an on board local SBus reset occurs then the CPU 5TE generates the SYSRESET signal to the VMEbus A second way for the SYSRESET signal to be generated is by power up reset Power up reset occurs by switching on the power Power up Reset also occurs when the power monitor detects power fail or the front panel reset key is toggled This SYSRESET signal can be disabled by setting the switch SW11 2 to OFF Please see the Diagram of the CPU 5TE Top View on page 12 to see the position of the switches on the board FORCE COMPUTERS Page 99 Hardware Description 3 7 9 VMEbus Bus Timer SPARC CPU S5TE Technical Reference Manual The VMEBus bus timer monitors all bus activities on the VMEbus and generates a BERR signal if the current cycle is not terminated in time The bus timer works regardless of whether or not the CPU STE is a VMEbus slot 1 device The table below shows the timeout values of the bus timer depending on the Timeout Control register Table 56 VMEbus Bus Timer Bus Timer TIME I 7 Generates OUT
68. ORCE COMPUTERS Page 129 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 10 15 User Flash Memory Programming Control Register This register is used to set the access mode for the User Flash memory and in case of the enhanced CPU 5TE mode you can select the User Flash device with this register Rene Register Name Read Write Access 713C 0005 User Flash Memory r w 8 bit Programming Control Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 SEL DEV_SEL 2 0 ENA Setting Function SEL_ENA 1 Enhanced CPU 5TE mode SEL_ENA 0 Default CPU 5CE mode Setting Function DEV_SEL 2 0 000 User Flash 0 selected DEV_SEL 2 0 001 User Flash 1 selected DEV_SEL 2 0 010 User Flash 2 selected DEV_SEL 2 0 011 User Flash 3 selected DEV_SEL 2 0 100 User Flash 4 selected DEV_SEL 2 0 101 User Flash 5 selected DEV_SEL 2 0 110 User Flash 6 selected DEV_SEL 2 0 111 User Flash 7 selected Page 130 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Circuit Schematics SECTION 4 CIRCUIT SCHEMATICS 4 General Index to the CPU 5TE Schematics Copies of the CPU 5TE schematics are found on the next page The first page of the schematics includes the index FORCE COMPUTERS Page 131 Circuit Schematics CPU 5TE Technical Reference Manual Page 132 FORCE COMPUTERS SPARC CPU S5TE Tec
69. Out Keyboard In Mouse Out 5VDC FIGURE 9 Keyboard Mouse Connector FORCE COMPUTERS Page 41 Installation 2 8 4 VME P2 Connector Pinout SPARC CPU 5TE The SCSI 2 interface is an alternative to the FDC interface The signals for rows Z and D are only available on the 5 row P2 Connector Table 15 VME P2 Connector Pinout Pin Signal Row Z Signal Row A pera beeen Signal Row D 1 CENTR DS SCSI 1 D0O FPY DENSEL SCSI 2 D0 NC 2 GND SCSI 1 D1 FPY DENSENS SCSI 2 D1 NC 3 CENTR DO SCSI 1 D2 N C SCSI 2 D2 SCSI 2 D0 4 GND SCSI 1 D3 FPY INDEX SCSI 2 D3 SCSI 2 D1 5 CENTR D1 SCSI 1 D4 FPY DRVSEL SCSI 2 D4 SCSI 2 D2 6 GND SCSI 1 D5 N C SCSI 2 D5 SCSI 2 D3 7 CENTR D2 SCSI 1 D6 N C SCSI 2 D6 SCSI 2 D4 8 GND SCSI 1 D7 FPY MOTEN SCSI 2 D7 SCSI 2 D5 9 CENTR D3 SCSI 1 DP FPY DIR SCSI 2 DP SCSI 2 D6 10 GND GND FPY STEP SCSI 2 ATTN SCSI 2 D7 11 CENTR D4 GND FPY WRDATA SCSI 2 BSY SCSI 2 DP 12 GND GND FPY WRGATE SCSI 2 ACK TERMPWR 2 13 CENTR D5 TERMPWR 1 FPY TRACKO SCSI 2 RST SCSI 2 ATTN 14 GND GND FPY WRPROT SCSI 2 MSG SCSI 2 BSY 15 CENTR D6 GND FPY RDDATA SCSI 2 SEL SCSI 2 ACK 16 GND SCSI 1 ATTN FPY HEADSEL SCSI 2 CD SCSI 2 RST 17 CENTR D7 GND FPY DISKCHG SCSI 2 REQ SCSI 2 MSG 18 GND SCSI 1 BSY FPY EJECT SCSI 2 IO SCSI 2 SEL 19 CENTR ACK SCSI 1 ACK 12VDC ETH 1_POW SCSI 2 CD 20
70. PPCTL 0 VPPCTL 1 Flash EPROM pro gramming possible FL_PAG supports in conjuction with BT_US and US_DEV of the gen_purpose2 register the programming of the flash memory devices It selects a 512 Kbyte page within the Boot EPROM area or the User EPROM area Please refer to chapter Programming the On board Flash Memories on page 78 for the settings of FL_PAG Page 120 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 8 gen_purposel Register The gen_purposel register combines various functions such as reading the rotary switch setting VME SYSFAIL control and ABORT key support Physical Register i Address Namit Read Write Access 7138 0005 gen_purposel r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 SYSSTAT SYSVME SYSNMIP ABNMIP ROT 3 0 Initialization Bits 6 4 are cleared to Os at reset Description ROTT 3 0 reflect the status of the rotary switch setting Please refer to Rotary Switch on page 111 for all possible bit variations ABNMIP reflects the abort key non maskable interrupt pending signal which is active if the Abort key was toggled ABNMIP directly generates a non maskable interrupt level 15 interrupt if the IRQI5_ENA bit in the gen_purpose2 register is set to enable ABNMIP is a read only bit Setting Function ABNMIP 0 No Abort Key NMI pending ABNMIP 1 A
71. RC trap types version Display version and date of the Boot PROM show devs Display a list of all device tree nodes devalias Display a list of all device aliases Page 32 FORCE COMPUTERS SPARC CPU 5TE Installation 2 5 5 Reset the System If your system needs to be reset you either press the reset button on the front panel or if you are in the Forth Monitor type reset on the command line ok reset The system immediately begins executing the Power On SelfTest POST and initialization procedures Once the POST finishes the system either boots automatically or enters the Forth Monitor just as it would have done after a power on cycle 2 5 6 OpenBoot Help The Forth Monitor contains an on line help To get this type ok help Enter help command name or help category name for more help Use ONLY the first word of a category description Examples help select or help line Main categories are File download and boot Resume execution Diag diagnostic routines Power on reset gt prompt Floppy eject Select I O devices Ethernet System and boot configuration parameters Line editor Tools memory numbers new commands loops Assembly debugging breakpoints registers disassembly symbolic Sync synchronize disk data Nvramrc making new commands permanent ok A list of all available help categories is displayed These categories may also contain subcategorie
72. SCE A SOLECTRON SUBSIDIARY SPARC CPU STE Technical Reference Manual Edition No 2 1 November 1997 P N 203738 FORCE COMPUTERS Inc GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS CPU S5TE Technical Reference Manual Table of Contents Table of Contents SECTION 1 INTRODUCTION cctsscassisssvesesisecuasesvunddesaved seuss ceccedtsesicecnstedsessssustoansseeecdel 1 1 The SPARC CPU STE Technical Reference Manual Seto cece ceeeceeceseeeeceseeeeceeeeeeeeeeeeeeeas 1 122 Terminology arien e E aan vesvows binicsses dow lews exuactes aut O RE A A REE REE 1 1 3 Summary of the SPARC CPU STE sic ssccsess seniiti castes ssutcecuctasssonevcescnssbassbbstesyssoseesseestatness bactoes 2 L4 Board Components cose ee Sei och sas a r oacs ep choca tonics dbase E sul EE EEE EN E ES 3 I 5 Specifications ses rre aea Eo TE eE E eves eau EE E E ERE EEE IEE 4 1 6 Product Nom nclat te nsnsi ene a ee e ae E E E A A R 6 LEGT Ordering WLOrmMatonissees oe csvesesaesss ces eesdsck sees Seecksogewel tesccasseeats aeesep stent eeep a EEEE E ea ERSE 6 1 7 History of the Manyalo peno e cok eave tae ee ee eee aed 9 SECTION 2 INSTALLATION cossescicsstvesciestediaussicessesieuastussnieccdougsduessbedbescaneususugscbsccoie L QD CATON PANEN EE EEE poate E A E A 11 2 2 Location Diagram of the SPARC CPU STE Board c
73. SEL 33 GND 34 FPY DISKCHG SPARC CPU 5TE FORCE COMPUTERS SPARC CPU 5TE Table 19 IOBP 10 P5 Pinout Serial Signal Signal 1 GND 2 RESERVED 3 RESERVED 4 RESERVED 5 TxD Port B 6 TxD Port A 7 RxD Port B 8 RxD Port A 9 RTS Port B 10 RTS Port A 11 CTS Port B 12 CTS Port A 13 GND 14 GND FORCE COMPUTERS Table 20 IOBP 10 Pinout Ethernet 1 Pin Function 1 GND Collision Transmit Data GND Receive Data GND N C N C Collision 10 Transmit Data 11 GND 12 Receive Data 13 12VDC 14 GND 15 N C Installation Page 47 Installation SPARC CPU 5TE 2 9 IOBP DS The IOBP DS is an I O back panel on VMEbus P2 with flat cable connectors for SCSI 1 SCSI 2 serial I O keyboard mouse and a micro D Sub connector for the Ethernet 1 interface AUI This back panel can be plugged into the VMEbus P2 connector The diagram below shows all the connectors The IOBP I O back panel and the IOBP DS are especially designed for the SPARC CPU STE Do not use any other I O back panels on the SPARC CPU STE for example the IOBP 1 2 9 1 Jumper Setting for IOBP DS Please make sure that the configuration switch matrix is plugged into sockets B3 B1 and B9 B8 that is the configuration for dual SCSI interface on P2 3 row connector This is described in chapter
74. T ACNMIR ACNMIP DVMA_ENA IRQIS5_ENA US_DEV BT_US The relevant bits are described on the next page FORCE COMPUTERS Page 97 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 54 ACFAIL Non Maskable Interrupt Pending Bit Setting Function ACNMIP 0 No ACFAIL NMI Pending ACNMIP 1 ACFAIL NMI Pending NOTE ACNMIP is a read only bit for the ACFAIL interrupt function Writing that bit enables disables the VMEbus interrupts This is described in the chapter VMEbus Interrupt Handler and MailBox Interrupt Function on page 93 The appropriate interrupt handler has to reset the pending non maskable interrupt This can be done with writing a one to the ACNMIR ACFAIL Non Maskable Interrupt Reset bit in the gen_purpose2 register This bit is a write only In addition the Power Fail Detect bit in the Aux 2 Register of the NCR89C105 must be set to clear the interrupt Please refer to the NCR SBus I O Chipset Data Manual for the Aux 2 Register The actual status of the VMEbus ACFAIL signal can be read in the gen_purpose2 register in bit ACSTAT Table 55 ACFAIL Status Bit Setting Function ACSTAT 0 ACFAIL active on VMEbus ACSTAT 1 ACFAIL inactive on VMEbus Page 98 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Hardware Description 3 7 8 VMEbus SYSRESET Enable Disable 3 7 8 1 SYSRESET Input A SYSRESET received from V
75. TH COL 27 RESERVED 27 N C 27 ETH COL 28 RESERVED 28 N C 28 GND 29 TxD Port A 29 N C 29 TxD Port B 30 RxD Port A 30 N C 30 RxD Port B 31 RTS Port A 31 GND 31 RTS Port B 32 CTS Port A 32 N C 32 CTS Port B Page 44 FORCE COMPUTERS SPARC CPU 5TE Table 17 IOBP 10 P2 Pinout SCSI 1 oe Signal Signal 1 GND 2 SCSI 1 Data 0 3 GND 4 SCSI 1 Data 1 5 GND 6 SCSI 1 Data 2 7 GND 8 SCSI 1 Data 3 9 GND 10 SCSI 1 Data 4 11 GND 12 SCSI 1 Data 5 13 GND 14 SCSI 1 Data 6 15 GND 16 SCSI 1 Data 7 17 GND 18 SCSI 1 DP 19 GND 20 GND 21 GND 22 GND 23 GND 24 GND 25 N C 26 TERMPWR 1 27 GND 28 GND 29 GND 30 GND 31 GND 32 SCSI 1 ATN 33 GND 34 GND 35 GND 36 SCSI 1 BSY 37 GND 38 SCSI 1 ACK 39 GND 40 SCSI 1 RST 41 GND 42 SCSI 1 MSG 43 GND 44 SCSI 1 SEL 45 GND 46 SCSI 1 CD 47 GND 48 SCSI 1 REQ 49 GND 50 SCSI 1 IO FORCE COMPUTERS Installation Page 45 Installation Page 46 Table 18 IOBP 10 P3 Pinout Floppy Signal oy Signal 1 FPY EJECT 2 FPY DENSEL 3 GND 4 FPY DENSENS 5 GND 6 N C 7 GND 8 FPY INDEX 9 GND 10 FPY DRVSEL 11 GND 12 N C 13 GND 14 N C 15 GND 16 FPY MOTEN 17 GND 18 FPY DIR 19 GND 20 FPY STEP 21 GND 22 FPY WRDATA 23 GND 24 FPY WRGATE 25 GND 26 FPY TRACKO 27 N C 28 FPY WRPROT 29 GND 30 FPY RDDATA 31 GND 32 FPY HEAD
76. TTYA DATA Port 7120 0000 gt RTC NVRAM B H W 712F FFFF 7130 0000 gt Boot EPROM and User EPROM Programming B 7137 FFFF 7138 0000 gt Additional Registers B 713F FFFF 7140 0000 gt Floppy Controller B 714F FFFF 7140 0002 Digital Output Register DOR 7140 0004 Main Status Register MSR Read Only 7140 0004 Datarate Select Register DSR Write Only 7140 0005 FIFO 7140 0006 Reserved Test mode select 7140 0007 Digital Input Register DIR Read Only 7140 0007 Configuration Control Register CCR Write Only 7150 0000 gt Reserved 717F FFFF 7180 0000 89C105 Configuration Register B 7190 0000 gt Auxiliary I O Registers B 719F FFFF 7190 0000 Aux Register Miscellaneous System Functions 7191 0000 Aux 2 Register Software Power down Control FORCE COMPUTERS SPARC CPU STE Technical Reference Manual Hardware Description Table 32 NCR89C105 Chip Address Map cont Physical i y Device Access Address 71A0 0000 Diagnostic Message Register B 71B0 0000 Modem Register B 71C0 0000 gt Reserved 71CF FFFF 71D0 0000 gt Counter Timers W D 71DF FFFF 71D0 0000 Processor Counter Limit Register or User Timer MSW 71D0 0004 Processor Counter Register or User Timer LSW 71D0 0008 Processor Counter Limit Register non resetting port 71D0 000C Processor Counter User Timer Start Stop Register 71D1 0000 System Limit Register Level 10 Interrupt 71D1 0004 System Counter Regist
77. The SPARC CPU STE is a single board computer combining workstation performance and functionality with the ruggedness and expandability of an industry standard 6U VMEbus card Page 2 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Introduction FIGURE 1 Block Diagram of the SPARC CPU 5TE m SBus Slot 8 16 32 64 Mbyte DRAM SBus Slot SBus each Module 8 bit USER local bus BOOT T Flash Flash R g MicroSPARC eys o gt RTC S4 v N Display NVRAM M T Rotary FPGA E P LEDs SBus b A r N Ethernet 2 AUD E Keyboard Mouse MACIO MACIO L Two Serial O SLAVIO 1 2 SCST 2 Fl oppy Switch Matrix Keyboard Mouse Two Serial I O Centronics SCSI 1 0 Ohm SCSI 1 Ethernet 1 TP TP Ethernet 1 AUD Ethernet 2 TP TP The Ethernet 2 SCSI 2 and Centronics devices are only available with the 5 row P2 Connector However the SCSI 2 is available on the 3 row P2 Connector through the use of a switch matrix instead of the floppy interface 1 4 Board Components As is shown in the above diagram the microSPARC II chip interfaces directly to a 64 bit wide DRAM on the one side and to the SBus on the other side The SPARC CPU STE is available with 16 or 64 Mbytes of DRAM modules MEM 5 The shared DRAM i
78. VMEbus Interrupt Handler and MailBox Interrupt Function ee eeeeeeeeeee 93 3 7 5 VMEbus System Controllers s co ccscccsssccssacsetts copebesbivseuacavhssyeassas sss epoca oei oop sbedaesestes 94 3 7 6 Register Accesses to the S4 VME Chip oo eee ceceseceeceseeseeeseeeeceseeseeeseeeaecsaeeaeenaes 95 3 7 VMEbus Utility FUNCHON Ss espns opene eeren eoa npea e po iE SRE o EES ipea EERE 95 3 7 7 1 genzpurpose Register e200 cit Ga enc ain es 96 3 7 8 VMEbus SYSRESET Enable Disable wee ce cece ceeceseeeeeeseeeeceseeeseeseeenecsaeeaeenaes 99 3 7 8 1 SYSRESET Inputs ccsccc25 5s5ccbsecussssteessescisges Meabsovcousesssatsectesh spss sasasoessssgetcenscs 99 378 2 S YSRESE T Outputcis os neien e r E eit ER E EE EEEE ees 99 32 9 NMMEb s Bus TIME neee cb een E T E E E E E A T 100 3 7 10 VMEbus Transaction Timeout Control Register eee ceeeeeceeeeeeeeeeeeeseeeeneeens 100 3 8 Front Pane beere eaea o areare eree OT e e ER RE R e 101 3 8 1 RESET and ABORT KeySonic tee eren u eoa EE S ens oee S oeie p CESTNE AREEN 103 3 811 The RESET Key irrin ennerien iea a a EE EE aE 103 3 81 2 The ABORT Key e ssscsceissssstsssts beasts casthcedsbachpucotsh soba scbbsdeshassaienstabeasectvens 103 3 8 2 Front Panel Status EDS inc u niee e e aE coeh ensues de sobs ceungsoonstunceseub necvuresbengeate 105 3 8 3 Diagnostic LED Hex Display ersero eiro e n asians tethers 107 3 9 Additional Features nni e e a e a aaa eiae iE a ria aE iai 108 39 1 Hardwa
79. a1l6d32 vme user 69 ok vme programnm phys high data phys high program converts the numeric representation of any VMEbus AML constant in data transaction form to its program form ok vmea32d16 vme program e ok The offset specifies the VMEbus address of an area within the selected address space The value of the offset depends on the address space For example the standard A24 address space is limited to 16 MByte 24 bit addresses ranging from 00 000016 to FF FFFF16 whereas the extended A32 address space allows to address 4 GByte 32 bit addresses ranging from 0000 000016 to FFFF FFFF1 6 and the short A16 address space is limited to 64 KByte 16 bit addresses ranging from 000016 to FFFF16 Example The example below shows how to specify the address of a VMEbus board that is accessible within the extended A32 address space vmea32d32 beginning at off set 4080 000016 ok h 4080 0000 vmea32d32 The first part represents the offset phys low and the second part represents the space phys high 5 1 2 VMEbus Master Interface As shown in the figure below the processor emits virtual addresses during a data transfer cycle which are translated to physical addresses by the MMU Within a microSPARC I II environment the VMEbus is connected with the SBus and the VMEbus interface responds to unique physical SBus addresses and executes the appropriate VMEbus transfer Depending on the physical addresses and the state of specifi
80. ability to be generated when half of the watchdog time has expired wd nmi clear clears a pending interrupt caused by the watchdog timer when half of the watchdog time has expired wd ip true false checks whether an interrupt is pending due to an interrupt gener ated by the watchdog timer when half of the watchdog time has expired The value true is returned when the interrupt is pending otherwise the value false is returned wd restart resets the watchdog timer and starts a new time count reset wd resets the watchdog timer and starts a new time count The watchdog timer is started by the commands listed below ok wd nmi ena ok wd ena ok In the example above a non maskable interrupt is generated whenever half of the watchdog time has expired The OpenBoot already contains an interrupt handler dealing with the interrupt generated by the watchdog timer This interrupt handler increments an internal variable by one whenever the watchdog timer emits an interrupt The state of this variable is determined by ok wdnmi occurred 6 FORCE COMPUTERS Page 163 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual ok This variable is cleared set to zero by ok wdnmi occurred off ok Page 164 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 3 2 Abort Switch The commands described below are available to control the abort switch as well as to retr
81. able interrupt WNMIP to give software a chance to react by retriggering the timer There will be a board reset if the timer is not retriggered during the times indicated in the table below RESET times Signal Min Time Typ Time Max Time WNMIP 830 ms 840 ms 850 ms RESET 3 3 s 3 45 s 3 68 The hardware watchdog timer is enabled with the WTENA bit in the vme_a32map register This bit is also used to retrigger the timer To start the timer again write a one to that bit Physical Register Adare Name Read Write Access 7138 0004 vme_a32map r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FL_PAG VPPCTL WTENA WNMIP VME _A 31 28 The settings of the respective bits are found on the next page Page 108 FORCE COMPUTERS SPARC CPU STE Technical Reference Manual Hardware Description Setting Function WTENA 0 Watchdog disabled WTENA 1 Watchdog enabled to retrigger write a one NOTE Once the timer is enabled it can t be disabled anymore Initialization At reset the WTENA bit is cleared which disables the watchdog timer Description The WNMIP bit in the vme_a32map register is active when there is a watchdog NMI pending that is when the first timeout of the watchdog timer occurs WNMIP directly generates a non maskable interrupt level 15 interrupt This bit is read only
82. ad base specifies the address where the data loaded from the available flash memory are stored when the load or boot command provided by OpenBoot Page 170 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements is used to load an image from the flash memory When this parameter is set to 1 which is the parameter s default value then the image loaded from the flash memory is stored beginning at the address addr But when the value of the configuration parameter differs from 1 then the image loaded from the flash memory is stored beginning at the address specified by the configuration parameter boot flash load base The same address is stored in the variable load base maintained by OpenBoot The methods listed below are available in the vocabulary of the flash memory device open true prepares the package for subsequent use The value true is returned when the device has been opened successfully otherwise the value false is returned Usu ally the fail state is indicated when the NVRAM configuration parameters boot flash megs and boot flash devices are not consistent close frees all resources allocated by open reset puts the flash memory device into quiet state selftest error number always returns the value zero read addr lenth actual reads at most length bytes from the flash memory device into memory beginning at address addr If actual is zero or neg
83. aeedagnnegsshaseinntoeaadty 29 Table 10 Commands to Display System Information sesesseessseeeesseesseessesseessees 32 Table 11 SPARC CPU 5TE Connectors essessesssesesssessssssrssesserseeeseessessessessseseessees 37 Table 12 Twisted Pair Ethernet Connector Pinout s ssssesessseseseseesseesseesseesseeeseee 38 Table 13 Serial Port A and B Connector Pinout ssseseeeeeeeseeeesseesseessersseresseesssees 39 Table 14 Keyboard Mouse Connector Pinout sessseeseeseeesseressessresresseesresrersersresees 41 Table 15 VME P2 Connector Pinout ssesesseeesesseseseesreseeesressesrreseesrrseresresseseresreses 42 Table 16 TOBP 10 PI Pi outi nonnisi gi 44 Table 17 IOBP 10 P2 Pinout SCSI 1 ca cies sues cagsialae tcceanteuaetacassadaaeiaqets eet 45 Table 18 TOBP 10 P3 Pinout Floppy seirian Meloy ee iar ete 46 Table 19 IOBP 10 P5 Pinout Serial cc ecccccssssscececcceceesessesececececeesessrseaeeeeees 47 Table 20 IOBP 10 Pinout Ethernet 1 0 00ecccccsscceccccceeeesessseceeececeeesssnseeeeeeees 47 Table 21 IOBP DS J1 Pinout SCSI 1 jicccansicnctedssavestaadenwacadeveassassaaganse weesaaevestses 50 Table 22 IOBP DS J2 Pinout SCSI 2 iis csiticsnsvcceseassgeniteaavaecasiscueiserdacdatsdaengensess 51 Table 23 IOBP DS J3 Pinout Ethernet 1 AUD 0 eee eceeeceseeeeceeeeeeeeaceeneees 52 Table 24 IOBP DS J4 Pinout Serial A and B ou ccccccesssssssecececeeeesesssseceeeeees 53 Table 25 IOBP DS J5 Pino
84. al devices When the configuration parameter is false the capability to generate a non maskable interrupt by the sources listed above is disabled default t rue wd ena controls whether the watchdog timer has to be started When the flag is t rue then the watchdog timer is started after it has been initialised according to the configuration parameter wd timeout If the flag is false the watchdog timer is not started but the watchdog timer registers are initialised according to the configuration parameter wd timeout default false vme intr1 controls whether the VMEbus interrupt request level 1 has to be enabled When this flag is 255 then the VMEbus interrupt request level 1 is not enabled In the case that the value is one 1 the corresponding interrupt handler is activated and the VME bus interrupt request level 1 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 1 when a VMEbus interrupt request level 1 occurs Only the least significant three bits of this value are considered default 25519 vme intr2 controls whether the VMEbus interrupt request level 2 has to be enabled When this flag is 255 then the VMEbus interrupt request level 2 is not enabled In the case that the value is two 2 the corresponding interrupt handler is activated and the VME bus interrupt request level 2 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 2 when a VMEbus interrupt r
85. am is loaded the TFTP package controls operation and calls the methods read and write of its parent device the BusNet device to receive and transmit packets across the network Once the program has been loaded the control is passed back to the BusNet device and the boot command The latter calls the close method of the BusNet device which in turn calls the close method of the TFTP package Finally control is returned to the boot command The BusNet device calls the methods of its parent device that is the VMEbus device Typically the BusNet driver calls the methods to make its BusNet region available to the VMEbus address space and to map this region to the processor s virtual address space 5 8 5 How to Use BusNet The busnet demo package is available in OpenBoot to demonstrate how to operate the BusNet driver in the raw mode In this mode pure binary data are sent across the network from one BusNet participant to another participant The following two definitions are available to initiate the transmission and receipt of data demo send data src addr size dest p sends the amount of data specified by size and stored beginning at the address src addr to the participant identified by its logical BusNet address dest p demo receive data dest addr size src p receives as much data as specified by size from the participant identified by its logical BusNet address dest p and stores it beginning at the addr
86. andler to serve the non maskable interrupt generated upon the assertion and negation of the SYSFAIL signal This handler does not need to be installed because it is already installed by OpenBoot By default the interrupts that will be emitted by a status change of the SYSFAIL signal are disabled and have to be enabled by ok vme sysfail assert irq ena ok which enables the generation of a non maskable interrupt whenever the SYSFAIL signal is asserted and negated When a non maskable interrupt occurs due to the assertion of the SYSFAIL signal then the FORCE COMPUTERS Page 175 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual appropriate interrupt handler increments the variable sysfail asserted by one to report the occurrence of such an interrupt The state of the variable is obtained by ok sysfail asserted 0 ok And the variable is cleared set to zero by ok sysfail asserted off ok 5 5 3 ACFAIL Interrupt OpenBoot for the SPARC CPU STE already includes an interrupt handler to serve the non maskable interrupt generated upon the assertion of the ACFAIL signal This handler does not need to be installed because it is already installed by OpenBoot By default the interrupt that will be emitted by asserting the ACFAIL signal is disabled and has to be enabled by ok vme acfail assert irq ena ok which enables the generation of a non maskable interrupt whenever the ACFAIL signal is asserted
87. arameter colour defines the colour of the LED The following constants are defined to specify the colour black green red and yellow When the colour black is specified the LED is turned off The following example allows the user LED to shine red ok red led ok FORCE COMPUTERS Page 165 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual led on turns the user LED on The user LED is shining yellow led off turns the user LED off led true false determines the state of the LED and returns either true or false to indi cate if the LED is turned on or off When the LED is turned on then the value true is returned otherwise the value false is returned toggle led determines the state of the user LED and turns the LED on or off The LED is turned on when it was turned off before and vice versa rotary switch byte returns the current state of the rotary switch The value of byte may be one of the values in the range of zero through 15 The value zero corresponds to the position 0 of the rotary switch the value one corresponds to position 1 and so forth 5 3 4 Miscellanea flash rdy true false determines the status of the internal Write State Machine of the USER flash memory devices When the USER flash memories are ready for pro gramming or erasure the value true is returned In the case that the USER flash mem ory devices are not ready for additional commands
88. are Description SPARC CPU S5TE Technical Reference Manual Physical Register Adda Name Read Write Access 7138 0005 gen_purpose1 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 SYSSTAT SYSVME SYSNMIP ABNMIP ROT 3 0 NOTE ABNMIP is a read only bit Initialization At reset ABNMIP is cleared to 0 The appropriate interrupt handler has to reset the pending non maskable interrupt This is done with a write access to the vme_slavebase Register Please refer to the chapter Additional Registers on page 113 In addition the Power Fail Detect bit in the Aux 2 register of the NCR89C105 must be set to clear the interrupt Please refer to the NCR SBus I O Chipset Data Manual for the Aux 2 register To reset the ABNMIP bit you can write any data to that register Table 58 Abort Non Maskable Interrupt Pending Bit Setting Function ABNMIP 0 No Abort NMI Pending ABNMIP 1 Abort NMI Pending Page 104 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Hardware Description 3 8 2 Front Panel Status LEDs There are two double LEDs on the front panel e RUN RESET LED and VME BM SYSFAIL LED e SYS LED and USER LED The RUN RESET LED is either red or green This LED is red when any reset signal on the board is active In all other cases this LED is green The BM LED reflects all VMEbus master activities on
89. arp true After these NVRAM configuration parameters have been set the OpenBoot BusNet driver scrutinizes every outgoing packet that carries an Ethernet frame and verifies whether the Ethernet frame contains an RARP request If so the BusNet driver resolves the RARP request using the information contained by the configuration parameters mentioned above and passes the response internally to the receiving part of the BusNet driver All other packets are sent across the network After this the boot load or bn dload command can be used to load an executable image from the VxWorks server In case of the first two commands the name of the image being loaded is always the name of the primary booter e g 83030002 SUN4 Page 196 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 8 9 Setting NVRAM Configuration Parameters The CPU STE are equipped with the S4 VMEbus Interface Chip which provides a mailbox register located in the short address space A16 of the VMEbus To enable the mailbox the following NVRAM configuration parameters must be set in addition to the NVRAM configu ration parameters listed in the table below vme ibox addr must be set to YOOZ where Y is one of the values 0 4 8 or Cj and Z is one of the values 0 2 4 Cy6 or E46 vme ibox ena must be set to true use new vme must be set to true to operate the VMEbus driver in the new mode This configuration parame
90. ative the read failed The value of length may not always be a multiple of the device s normal block size write addr length actual discards the information passed to the command and always returns zero to indicate that the device does not support this function seek offset file error seek to byte offset within the file identified by file The flash memory device package maintains an internal position counter that is updated when ever a method to read data from or to store data in the flash memories is called If off set and file are both zero then the internal position counter is reset to offset zero otherwise the value of offset is assigned to the internal position counter and a subse quent access to the flash memories starts at the offset selected Because the flash memory device does not support any file system the parameter file is ignored except in the case mentioned above When the seek succeeded the value of error is zero otherwise the value 1 is return rned to indicate the fail state read blocks addr block blocks read reads the number of blocks identified by blocks of length block size bytes each from the device beginning at the device block block into memory at address addr It returns the number of blocks actually read read FORCE COMPUTERS Page 171 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual write blocks addr block blocks written discards the info
91. bed in the S4 VME chip is the address seen by the chip itself but the user sees the chip internal registers in the above described SBus Slave Select 0 range 3 7 7 VMEbus Utility Functions The CPU 5TE handles the VMEbus signals SYSFAIL and ACFAIL SYSFAIL and ACFAIL are monitored and their high to low edges are capable of generating a level 15 non maskable interrupt A non maskable interrupt is only generated if the IRQI5_ENA bit in the gen_purpose2 register is set to enable The SYSFAIL signal can also be driven by the SPARC CPU STE The pending non maskable interrupt generated by the VMEbus SYSFAIL is readable in the gen_purposel register This bit is called SYSNMIP SYSfail Non Maskable Interrupt Pen ding The gen_purpose register and relevant bits are shown on the next page FORCE COMPUTERS Page 95 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 7 7 1 gen_purpose Register Physical Register Addres Name Read Write Access 7138 0005 gen_purpose1 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO SYSSTAT SYSVME SYSNMIP ABNMIP ROT 3 0 Table 51 SYSFAIL Non Maskable Interrupt Pending Bit Setting Function SYSNMIP 0 No SYSFAIL NMI Pending SYSNMIP 1 SYSFAIL NMI Pending NOTE SYSNMIP is a read only bit Initialization At reset SYSNMIP is cleared to 0 The appropriate interru
92. bits specifies the number of address bits necessary to address this device on its net work Typically the BusNet address consists of 32 bits but only the least significant five bits are important All remaining bits must be cleared 0 Therefore the property address bits is set to 32 The property s size is 32 bits integer reg property describes the VMEbus address ranges which are accessible by the BusNet device driver The information given by this property is crucial for the operating of the operat ing system s own BusNet device driver The register property is declared as follows h 0000 0000 vmeal6d32 h 0001 0000 VMEbus A16 space h 0000 0000 vmea24d32 h OO0ff 0000 VMEbus A24 space h 0000 0000 vmea32d32 h ff00 0000 VMEbus A32 space FORCE COMPUTERS Page 183 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual The properties listed below are created dynamically whenever the device is opened for subsequent accesses bn packet size specifies the size of a BusNet packet including the BusNet packet header The value of this property depends on the value of the NVRAM configuration parame ter bn packet size When the value of the configuration parameter is below the minimum of 2048 bytes the property s value is set to 2048 In the case that the value of the configuration parameter is not a multiple of 64 bytes the value of the property is downsized to the next 64 byte boundary The property s size i
93. ble 42 VMEbus Address Ranges iia fcutseastitsnaiessagesomaticalecstivateasvatacceistauaeaoans 85 Table 43 Supported Address Modifier Codes eecceessceceseeecseeeeceeeeeesteeeeseeeeaees 85 Table 44 Address Modifier Supervisory Bit ccceecccesesccecesececeseceeseeeeesseeeesaeeeenes 86 Table 45 VMEbus Master Interface Transfer Cycles 00 eeecceeeseceesseceesseceesteeeeees 87 Table 46 AVS DVN e ESI ooh cy Gece cuatro aces n a 88 Table 47 DVMA E able Bites i tsa cane dnd oa a Leah OS OO lati ie 89 Table 48 Shave Address Mod Bit 5 des exes ayes gees ssoi iessen iis 90 Table 49 Window Size Bits ici esehanols eens cia eee eed 92 Table 50 S4 VME Chip Physical Address Map ceecccesececsececesecesseeeeenteeeeaees 95 Table 51 SYSFAIL Non Maskable Interrupt Pending Bit eee eeeteeeeneee 96 Table 52 SYSFAIL to VMEbus Bit us icnu top aise E 97 Table 53 SDAS ETS CaS Dii AEAEE E E EE ETE 97 Table 54 ACFAIL Non Maskable Interrupt Pending Bit eee eee eeeteeeesteeeeeee 98 Table 55 ACFAI Status Bit faranno a a i i 98 Table 56 VMEb S SUS Fimer 2s os aca n ae nate eel te IENE 100 Table 57 Feat res Or he Front Pama ogists ce dan elastcitevah Saqsteaetue va eeu uasaasaw aes 101 Table 58 Abort Non Maskable Interrupt Pending Bit eee eeeseeeesseeeenteeees 104 Table 59 LED Bitisisiseccicgasvadaeisivalcisnacaseiseviaaievceselsaiedaaia sad E A a iE 105 Table 60 Rotary SWiteh Settings serceto err
94. bles NMI capability of Abort Key SYSFAIL ACFAIL and the Hardware Watchdog Timer Page 124 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description DVMA_ENA enables the VMEbus slave accesses Setting Function DVMA_ENA 0 Disables VME slave accesses DVMA_ENA 1 Enables VME slave accesses ACNMIP is a double functional bit Reading the ACNMIP bit reflects the VMEbus ACFAIL non maskable interrupt signal which becomes active if the VMEbus ACFAIL signal is asserted It only becomes active with a high to low rising edge of ACFAIL The ACNMIP directly generates a non maskable interrupt level 15 interrupt if the IRQ15_ENA bit is set to enable Writing the ACNMIP bit enables or disables the VMEbus interrupt lines treated by the on board interrupt handler Setting Function Read ACNMP 0 No ACFAIL NMI pending Read ACNMP 1 ACFAIL NMI pending Write ACNMIP 0 Disable all VMEbus interrupts Write ACNMIP 1 Enable all VMEbus interrupts ACNMIR clears the pending non maskable interrupt which was initiated by the VMEbus ACFAIL signal To reset the pending NMI write a one to that bit ACNMIR is a write only bit ACSTAT reflects the status of the VMEbus ACFAIL signal It is a read only bit Setting Function ACSTAT 0 ACFAIL active on VMEbus ACSTAT 1 ACFAIL inactive on VMEbus WNMIR clears the pending non maskable interrupt which was in
95. bn rarp are set to true bn master en adadr specifies the Ethernet address of the master The Ethernet address is represented by an ASCII string in the following format XX XX XX XX XX XX where XX is a hexadecimal number The setenv command is used to set this config uration parameter as shown below ok setenv bn master en addr 0 80 42 b 10 ac This configuration parameter must be set when one of the configuration parameters bn arp and bn rarp are setto true bn p en addr specifies the Ethernet address of the participant The Ethernet address is represented by an ASCII string in the following format XX XX XX XX XX XX where XX is a hexadecimal number The setenv command is used to set this config uration parameter as shown below ok setenv bn p en addr 0 80 42 b 10 ad This configuration parameter must be set when one of the configuration parameters bn arp andbn rarp are set to true FORCE COMPUTERS Page 189 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 8 4 Device Operation In general OpenBoot provides the boot command to load a program through a communication channel into memory The device specifier specifies the physical device that is attached to the communication channel A program is loaded across the VMEbus using the BusNet protocol by ok boot busnet or ok boot busnet tftp The device aliases busnet and busnet t ftp specify the BusNet device used to load the
96. bort Key NMI pending FORCE COMPUTERS Page 121 Hardware Description SPARC CPU S5TE Technical Reference Manual SYSNMIP reflects the VMEbus SYSFAIL non maskable interrupt signal which becomes active if either the CPU STE generates a SYSFAIL signal or another VMEbus partner causes it to be active It only becomes active with a high to low rising edge of SYSFAIL The SYSNMIP directly generates a non maskable interrupt level 15 interrupt if the IRQ15_ENA bit in the gen_purpose2 register is set to enable SYSNMIP is a read only bit Setting Function SYSNMIP 0 No SYSFAIL NMI pending SYSNMIP 1 SYSFAIL NMI pend ing SYSVME is directly output to the VMEbus SYSFAIL signal and therefore can assert negate the VMEbus SYSFAIL Setting Function SYSVME 0 Asserts SYSFAIL on VMEbus SYSVME 1 Negates SYSFAIL on VMEbus SYSSTAT reflects the status of the VMEbus SYSFAIL signal It is a read only bit Page 122 Setting Function SYSSTAT 0 SYSEAIL active on VMEbus SYSSTAT 1 SYSEAIL inactive on VMEbus FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 9 led_display Register The ed_display register directly controls the front panel diagnostic LED display Please refer to the chapter Diagnostic LED Hex Display on page 107 for the settings of that register Physical Register
97. c registers within the VMEbus interface the interface addresses a specific VMEbus address space FORCE COMPUTERS Page 135 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual FIGURE 17 Address translation master microSPARC SBus VMEbus VMEbus address space microSPARC I II processor VMEbus addresses Virtual Physical addresses addresses Processor EE MMU VMEbus interface Before the processor may access a specific area within one of the VMEbus address spaces the steps described below must be taken e The VMEbus interface has to be set up to respond to specific physical SBus addresses to forward the access to a certain VMEbus address space e The contents of the MMU table are modified to make the SBus address range available to the processor s address range and thus allowing accesses to the specific VMEbus area using virtual addresses In general this means that the VMEbus area is made available to the processor s virtual address space e The VMEbus interface has to be enabled in order to allow accesses to the VMEbus address space OpenBoot provides commands to make VMEbus areas available to the processor s virtual address space and to remove these VMEbus areas from the processor s virtual address space The command vme memmap performs all steps to make specified VMEbus areas available to the processor s virtual address space The
98. called and the value false is passed to it vme bus captured true false determines whether the VMEbus interface gains the ownership of the bus The value true is returned when the VMEbus interface gains the ownership of the VMEbus Otherwise the value false is returned to indicate that the VMEbus interface has not gained the ownership of the bus In general this command is called immediately after a capture and hold cycle has been initiated as shown in the example below ok true vme bus capture ok begin vme bus captured until ok false vme bus capture FORCE COMPUTERS Page 149 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 2 7 VMEbus Status Signals The commands listed below are available to access and control the VMEbus status signals vme sysfail set asserts sets the VMEbus SYSFAIL signal vme sysfail clear negates clears the VMEbus SYSFAIL signal vme sysfail true false asserts or negates the VMEbus SYSFAIL signal When the value true is passed to the command the VMEbus SYSFAIL signal is asserted Otherwise the value false is passed to the command the VMEbus SYSFAIL signal is negated vme sysfail true false determines the state of the VMEbus SYSFAIL signal and returns a flag set according to the signal s state When the SYSFAIL signal is asserted the flag returned is true otherwise its value is false vme sysfail byte r
99. ceseeseenseeseeneees 194 5 8 8 Booting from a VxWorks BusNet Server c cee eceseesseseeesecseecaecsseesecnaeeecesenseensees 195 5 8 9 Setting NVRAM Configuration Parameters eee cseeseceeeeseceseesecneceeensenseeeeees 197 SECTION 6 SUN OPEN BOOT DOCUMENTATION cscssssssssssssssssssscssesees 199 SECTION Product Error Report esssessocessecssocesoossooseooeesoccssocesoossoosessessseceseeesssee 20L FORCE COMPUTERS Page v Table of Contents CPU 5TE Technical Reference Manual List of Figures Figure 1 Block Diagram of the SPARC CPU STE 0 eee ceecceeneeescecnseceeeeseeeeneees 3 Figure 2 Diagram of the CPU STE Top View 0 cee cescesceeeseecsseceseeeseeesneeeaeenes 12 Figure 3 Diagram of the CPU STE Bottom View cceeceesecsseceeeeeseeeeneeesaeenes 13 Figure 4 SCSI Termination para ata E deere A poet Amiens 21 Figure 5 Floppy or SCSI 2 Availability on P2 oo eeeeeseecsseceneeeeeeeeneeenaeenee 23 Figure 6 Diagram of the Front Patiel s2 05 2464 ck Lees celine 35 Figure 7 TWwisted Pair Ethernet oien se e ai RE a E REIRES 38 Figure 8 Serial Ports A and B Connector Pinout eseeeeeseeeeseeereereesersrerrerserereses 40 Figure 9 Keyboard Mouse Connector essesseeeessrsesesresseseresressesererressessresrersersresees 41 Figure 10 The TOBP JQnrensnerisndnuniinnnucsnmenetnnaininiun i nar 43 Figure 11 The EC BD DS pee ae dace tics nae E a act 48 Figure 12 Block Diagram of the SPARC CPU S5TE
100. d command The program currently running is aborted and the FORTH interpreter appears immediately 5 5 5 Watchdog Timer Interrupt OpenBoot for the SPARC CPU STE already includes an interrupt handler to serve the non maskable interrupt generated by the watchdog timer when half of the time has expired This handler does not need to be installed because it is already installed by OpenBoot By default the interrupt that will be emitted by the watchdog timer is disabled the watchdog timer is disabled and has to be enabled by ok wd nmi ena ok wd ena ok In this example a non maskable interrupt is generated whenever half of the watchdog time has expired The interrupt handler included in OpenBoot restarts the watchdog timer to ensure that the watchdog time will not expire and cause a reset Additionally the interrupt handler FORCE COMPUTERS Page 177 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual increments the variable wanmi occurred by one whenever the watchdog timer emits an interrupt The state of this variable is determined by ok wdnmi occurred 6 ok This variable is cleared set to zero by ok wdnmi occurred off ok 5 6 Further Commands The command listed below is available to provide miscellaneous services not cachable vaddr size disables cachability of an address range identified by its virtual base address addr and its size Page 178 FORCE COMPUTERS SPARC CPU S5TE Tec
101. d provide the capability to load and execute boot an executable image via the VMEbus backplane using the BusNet protocol 5 8 1 Limitations Due to the fact that OpenBoot is a simple booter rather than an operating system the limitations listed below apply to the BusNet protocol implementation e The OpenBoot support for the BusNet protocol only allows a participant to operate as a Slave e The network management services are currently not supported Every received packet containing such a request is refused by the BusNet driver e The OpenBoot provides only single buffering mode which means that only one buffer is provided for every participant e In general OpenBoot does not use any interrupt mechanism while loading an image from the boot device Therefore OpenBoot will not enable a mailbox available on the machine even if the NVRAM configuration parameters allow the use of a mail box 5 8 2 Loading Programs The OpenBoot provides several methods for loading and executing a program on the machine These methods load a file from a remote machine across the communication channel into memory and support execution of FORTH FCode and binary executable programs An executable program is loaded across the VMEbus using the BusNet protocol with the following two command provided by OpenBoot boot device specifier argument or load device specifier argument The parameter device specifier represents the name full path
102. documentation references to the Dual 10base T Ethernet Interfaces on the SPARC CPU STE board occur frequently This is referred to in the manual both as TPE Twisted Pair Ethernet and TP Twisted Pair For an overview of the Ethernet structure please see the Block Diagram of the SPARC CPU STE on page 3 FORCE COMPUTERS Page 1 Introduction SPARC CPU S5TE Technical Reference Manual 1 3 Summary of the SPARC CPU 5TE The SPARC CPU STE is a VMEbus board based on the microSPARC II CPU chip which is a highly integrated implementation of the SPARC RISC microprocessor Through a combination of powerful processing power with a full set of I O interfaces including two fast SCSI devices two Ethernet devices floppy disk serial I O Centronics compliant parallel I O and keyboard mouse ports the SPARC CPU S5TE becomes a high performance cost effective solution for embedded applications A full 32 bit IEEE 1014 VMEbus interface and two industry standard SBus sockets enable the expansion of memory I O and processing performance via a broad range of off the shelf solutions Every SPARC CPU STE includes an EPROM based monitor debugger called OpenBoot which provides the functionality of the boot device as well as the setup for the VMEbus interface The software support for the SPARC CPU STE ranges from Solaris the most popular implementation of the UNIX operating system to sophisticated hard real time operating systems such as VxWorks
103. e diagrams of switch in table 5 Default Switch Settings on page 14 have been cor rected Table 32 NCR89C105 Chip Address Map on page 68 has been completed Editorial changes have been made November 1997 FORCE COMPUTERS Page 9 Introduction SPARC CPU S5TE Technical Reference Manual Page 10 FORCE COMPUTERS SPARC CPU 5TE Installation SECTION 2 INSTALLATION 2 Introduction This Installation Section provides guidelines for powering up the SPARC CPU STE board The Installation Section which you have in your hand now appears both as Section 2 of the SPARC CPU STE Technical Reference Manual and as a stand alone Installation Guide This stand alone Installation Guide is delivered by FORCE COMPUTERS with every board The SPARC CPU STE Technical Reference Manual provides a comprehensive hardware and software guide to your board and is intended for those persons who require complete information 2 1 Caution Please read this Installation Section before installing the board Take a moment to examine the Table of Contents to see how this documentation is structured This will be of value to you when looking for specific information in the future CAUTION Do not plug or remove board under power 2 2 Location Diagram of the SPARC CPU 5TE Board A location diagram showing the important components on the CPU STE top view appears on the following page On the page next to it there is a location diagram of the
104. e write protected via hardware switch SW13 1 When SW13 1 is ON write accesses are possible When SW13 1 is OFF the devices are write protected The on board programming of the User Flash EPROM devices requires setting some bits in the vme_a32map register and the gen_purpose2 register This is described in the chapter Programming the On board Flash Memories on page 78 FORCE COMPUTERS Page 77 Hardware Description 3 6 11 SPARC CPU S5TE Technical Reference Manual Programming the On board Flash Memories Both areas of flash memories the Boot EPROM area and the User EPROM area can be reprogrammed on board To enable the programming of the flash memory devices the 12V programming voltage must be switched ON This is done by setting bit VPPCTL in the vme_a32map register Physical Register eee Name Read Write Access 7138 0004 vme_a32map r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 FL_PAG VPPCTL WTENA WNMIP VME _A 31 28 Table 38 12V Programming Voltage Control Bit Setting Function VPPCTL 0 No flash EPROM programming possible VPPCTL 1 Flash EPROM programming possible Initialization VPPCTL is cleared on reset This inhibits the programming of the flash EPROMSs Page 78 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Hardware Description 3 6 12 Programming Control Bits for Flash M
105. ec Centronics compatible Uni or bidirectional I O on 5 row P2 connector SCSI 2 with DMA to SBus NCR89C100 MACIO 2 10 Mbytes sec 53C90A superset I O on on 3 row and 5 row P2 Connector T O on P2 via switch matrix instead of Floppy Interface Ethernet 2 with DMA to SBus NCR89C100 MACIO 2 10 Mbits sec AM7990 compatible T O on front panel as Twisted Pair and on 5 row P2 connector as AUI Page 4 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Table 1 Specifications of the SPARC CPU 5TE cont Introduction Floppy Disk Interface NCR89C105 250 300 500 Kbytes sec and 1 Mbytes sec 82077AA 1 compatible T O on P2 via switch matrix Serial I O NCR89C105 Two ports with RS 232 configuration 8530 compatible T O on front panel or P2 Keyboard Mouse Port Sun compatible on front panel or P2 Counters Timers Two 22 bit programmable Boot Flash Memory 512 Kbyte 1 Mbyte Option On board programmable Hardware write protection User Flash Memory 8 Mbyte optional On board programmable Hardware write protection RTC NVRAM Battery M48T08 Usable Memory 8 Kbyte VMEbus Interface 32 bit master slave IEEE 1014 Additional Features Reset and Abort switches 4 Status LEDs on the front panel HEX display on the front panel Watchdog timer Firmware OpenBoot with diagnostics Power consumption 5V 5 2 A No SBus Module installed 12V 0 7A 12V 0 2A Environ
106. eeeeeeeeeeeeeeeeeeeeene 126 3 10 12 Network Interface 2 Control and Status Register 0 0 0 eee ceeeeeceeeeeeeeeeeeeeeeeeseeene 127 3 10 13 User LED and User Flash Memory Control and Status Register 0 0 eee 128 3 10 14 VMEbus Transaction Timeout Control Register eee ce ceeeceeeeeeeeeeeeeeeneeneeees 129 3 10 15 User Flash Memory Programming Control Register eee ce eeceeeeeeeeeeeeeeeeeeeeeene 130 SECTION 4 CIRCUIT SCHEMATICS sccscsscccssdsseunssectictacessacccsedesesdseetsccdeecssousssenseee LOL SECTION 5 OPENBOOT ENHANCEMENTS cccscssssssssssssssssssssssssssssessseseesees 133 5 1 Controlling the VMEbus Master and Slave Interface eee cee cseceeceeceseeeeceseeeecneeeeeeeeeees 134 5 1 1 VMEbus addressing s 3 5 c3sceuistisees caps tate esssas a as opake E a EE Ss 134 5 1 2 WMEbus Master Interface vecsie aeioeaio E arie E 135 5 1 3 VMEbus Slave Interiace s csssscss sssscesescuscsstssssescsogedseuschanioade aces scesdashensseasaseaa stones sni 138 3 27 NMEbus Intertace 22 3 3 c aiina oa ne hae a ee ae 140 S251 Generic Information nanes n e ai sd haut E E E nee ete ions 140 5 22 Register Addresses i glee hi ae eth Gai negates edhe oa Ae aioe 140 D 2 3 _ Register ACCESSES kooien ere er e EE E EEEE E EE EEKE EE EESE OESIE 142 5 2 4 VMEbus Interrupt Handler ceee insiet ne paene as 146 5 29 MMEb s Arbiter eseon sieved ited E a EEE K A AEEA santa nies 148 520 VMEbus REQUESTER reoeo one is neonne A E E EN P
107. eeeeeeeeneeees 23 2 4 11 Network Interface Selection NIS for Ethernet 0 ccc ececcceesseeeeeeceesseecseeeeeseseeenees 24 24 12 Parallel Port serene ceo AEE E ease teens ded E E A donee EE EEES 24 25 Open Boot Birm ware sve ieee En ia Roe a Ara E N ete REK E EE cag tude vous laser teed 25 FORCE COMPUTERS Page i Table of Contents CPU 5TE Technical Reference Manual 2 5 1 A Bootthe System eunoe nenen aie EEE N EEE EEE 25 23 27 NVRAM Boot Par MEIE S E ra e shat e e E R EE RE E RETE 28 2553 Dja phost S n o r E E E ET SRG E E E E E 29 25 4 Display System Informatigt ssis eesinsh ikae ass 32 29 5 Reset the System r GRE ee RIS AM ee es 33 2 9 6 Open Boot Helpe ereere or e E EE E ees ep a rE Sret ae apo EE Se 33 2 6 Pron Panela inte iii ee ek I Ae a a A ees 35 2 6 1 Features of the Front Patiel 1 3 0 sc ncn acceacdctviectell iii cbs arn encase Se 36 2 8 SPARC CPU 5TE Connectors 3 s0 43 Skid wuiainiNie hin duaA atti Aiea es 37 2 8 1 Twisted Pair Ethernet Connector Pinout ccccecssecesseceesseeceeseeeceeeecesececnsseeessseeensas 38 2 8 2 Serial Port A and B Connector Pinout cccecceccecesseeceecceessseecseseeeceseecesseecneeeeesseeeensas 39 2 8 3 Keyboard Mouse Connector Pinout 0 eee eceeeeeeeseeceecesecoecaeeseceseesecnseeeeseeeeeeseneeees 41 2 8 4 VME P2 Connector Pinout 0 cccceccssecessceeessecesesseeceeccessaeecseaaeeceeeeesesaeecsseeeesseeeenees 42 28 0 The OBP O Connectors
108. eeseseeeeecneeeneenees 62 35 2 SOS s cake teaver tention E KEE Aphis attain wicks hes Races Ata oaania needa 63 3 53 SCSI Termimationl ss oeiee rese eetarea sce acaihescuetssachscheshepeotsessbasdetedachsskaadevanssscesds chats 63 JDA Ethernet e eer e na E EE E E T ESE EE EE E EE E EN ET 64 3 5 5 Network Interface Selection NIS for Ethernet 0 cceesccecessecesseceeesseceeeeeeessseeessnees 64 3 5 5 1 Network Interface 1 Control And Status Register essseeeseeeeeesereeseeeereees 65 3 5 5 2 Network Interface 2 Control And Status Register eesseeeseeeeeesereeseeeeseees 66 3 5 0 Parallel Portesson reais pana Tae E aE aE TE EEA EEEE ue EEES 66 3 6 NCR89CTOS SLA VIO nra t aain o a ARs hee KEE aa E EE EESE 67 3 6 1 Features of the NCR89C105 on the SPARC CPU STE essseesseeesererrersereresreresreersreee 67 3 6 2 Address Map of Local I O Devices on SPARC CPU S5TE ssseeseseeseeeeereerersererrereersree 68 3 6 3 4 Senal T O POTIS sn ae A N E E R S E E 70 3 6 4 RS 232 Hardware Configuration cece cesceseceecesecesceseeseeeseseeeeseseeeeseeesecseeeaeenaes 71 3 6 5 Keyboard and Mouse Port sienties aas e RE EE EEE e EREE a EEY 72 Page ii FORCE COMPUTERS CPU S5TE Technical Reference Manual Table of Contents 3 0 6 Floppy Interface senene sdegosrtesstesteages E E E N R R 73 3 6 7 Floppy Interface or SCSI 2 Availability on P2 eee ceceeeeeeceeeeeeeseecaecneeeaeenaes 73 3 6 8 8 Bit Local I O Devices N
109. efault B R On Disabled u O MACIO s N Termination 2 SCSI 2 a T P lt 2 P A N SW7 1 controls SCSI 1 termination for Front Panel SW5 4 controls SCSI 1 E Off Automatic default ape a P2 L On Disabled termination on 2 Off Enable MACIO On Disabled default 1 Termination Termination SCSI 1 SCSI 1 moro oc BB OQ FORCE COMPUTERS Page 63 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 5 4 Ethernet The Ethernet 1 device is realized via the NCR89C100 MACIO 1 The Ethernet 2 is realized via the NCR89C100 MACIO 2 For both Ethernet interfaces there is one Ethernet address This means that you don t have to connect both interfaces to one physical cable The NCR89C100 DMA controller enables the Ethernet interface to transfer data to and from the shared main memory The Ethernet core is register level compatible with the AMD Am7990 Revision F standard Ethernet controller which is capable of transferring Ethernet data up to 10 Mbit sec 3 5 5 Network Interface Selection NIS for Ethernet It is important to understand that the Ethernet is selected either via the twisted pair connector or the AUI Attachment Unit Interface When you boot your system and a connection exists with an AUI network then the AUI is automatically selected In other words when you have a successful connection with a network the AUI is used When you have no connection with the AUI network t
110. emory Devices The address range in which the flash EPROMs can be programmed is located in a 512 Kbyte page programming window of the Generic Port area of the NCR89C105 SLAVIO The physical address range is 7130 0000 7137 FFFF On the CPU S5TE there is a maximum of 9 Mbyte flash memory available 1 Mbyte Boot EPROM and 8 Mbyte User EPROM To program these areas they have to be divided into 2 or 16 512 Kbyte pages which will fit into the programming window The flash memories can only be programmed in the programming window In the default CPU S5CE Mode you can program the Boot EPROMs and the first 2 Mbytes of User EPROM in the same way as you program on the CPU 5CE and the CPU 3CE In the enhanced CPU 5TE Mode you can program the Boot EPROMs and up to 8 MBytes User EPROM 3 6 12 1 Default CPU 5CE Mode In order to decide which area is to be mapped to the programming window the following three bits are used to control this The relevant three bits are BT_US and US_DEV in the gen_purpose2 register and FL_PAG in the vme_a32map register Physical Register Address Nam Read Write Access 7138 0007 gen_purpose2 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 WNMIR ACSTAT ACNMIR ACNMIP DVMA_ IRQI5_ US_DEV BT_US ENA ENA Physical Register Address Name Read Write Access 7
111. equest level 2 occurs Only the least significant three bits of this value are considered default 25519 vme intr3 controls whether the VMEbus interrupt request level 3 has to be enabled When this flag is 255 then the VMEbus interrupt request level 3 is not enabled In the case that the value is three 3 the corresponding interrupt handler is activated and the VMEbus interrupt request level 3 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 3 when a VMEbus interrupt request level 3 occurs Only the least significant three bits of this value are considered default 25510 vme intr4 controls whether the VMEbus interrupt request level 4 has to be enabled When this flag is 255 then the VMEbus interrupt request level 4 is not enabled In the case that the value is four 4 the corresponding interrupt handler is activated and the VMEbus interrupt request level 4 is enabled The value one specifies that the S4 asserts its SBus interrupt request line 4 when a VMEbus interrupt request level 4 occurs Only the least significant three bits of this value are considered default 25549 vme intr5 controls whether the VMEbus interrupt request level 5 has to be enabled When this flag is 255 then the VMEbus interrupt request level 5 is not enabled In the case that the value is five 5 the corresponding interrupt handler is activated and the VME bus interrupt request level 5 is enabled The value one specifies
112. er 71D1 0008 System Limit Register non resetting port 71D1 000C Reserved 71D1 0010 Timer Configuration Register 71E0 0000 gt Interrupt Controller WwW 71EF FFFF 71E0 0000 Processor Interrupt Pending Register 71E0 0004 Processor Clear Pending Pseudo Register 71E0 0008 Processor Set Soft Interrupt Pseudo Register 71E1 0000 System Interrupt Pending Register 71E1 0004 Interrupt Target Mask Register 71E1 0008 Interrupt Target Mask Clear Pseudo Register 71E0 000C Interrupt Target Mask Set Pseudo Register 71E0 0010 Interrupt Target Register Reads as 0 Write has no effect 71F0 0000 System Control Status Register WwW FORCE COMPUTERS Page 69 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 6 3 Serial I O Ports The two serial I O ports are available on the front panel via one 26 pin shielded connector which is compatible to the CPU 5V Both of the two ports are available via the VMEbus P2 connector each with four signals RXD TXD RTS CTS Each of the two serial I O ports are independent full duplex ports The 8530 SCC block is functionally compatible with the standard NMOS 8530 and therefore provides two fully independent full duplex ports The physical address map for the serial ports is shown in NCR89C105 Chip Address Map on page 68 Both RS 232 and RS 422 are supported via assembly options By default the RS 232 standard is used Page 70 FORCE COMPUTERS SPARC CPU 5TE Technical Reference
113. erved SMODE SUPV SAMODE reserved WIN2 WINI WINO Table 44 Address Modifier Supervisory Bit Setting Function SUPV 0 Non Privileged Address Mode SUPV 1 Supervisory Address Mode Initialization At reset the SUPV is cleared to 0 Page 86 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 7 2 2 Data Bus Sizes The SPARC CPU 5TE VMEbus master interface supports the data size modes D8 even odd D16 and D32 Block mode transfers and unaligned transfers are not supported The following table illustrates the supported VMEbus transfer cycles Table 45 VMEbus Master Interface Transfer Cycles E D31 D24 D23 D16 D15 D08 D07 D00 8 bit 8 bit X 16 bit X A 32 bit X X X NOTE The X shows the active byte portion Please also refer to Section 5 OpenBoot Enhancements for VMEbus master interface accessing methods FORCE COMPUTERS Page 87 Hardware Description 3 7 3 Access to the SPARC CPU STE on board DRAM is allowed to a 1 Mbyte page within a 16 Mbyte area in the Default Slave Mode In the Enhanced Slave Mode the accessible window is not restricted to the 1 Mbyte page and the base address is variable for Extended Address Mode A32 Eight different window sizes are possible from 1 Mbyte to 64 Mbyte In both modes the VMEbus address space is always mapped to the upper virtual address space The
114. eseeeecesceeeceeeeseeeeeeeeeenseseeeneesaesaes 11 2 3 Before POWer ine UD ienne eee bes eevee wise snes cdesh verse cv ooh soeedeb aa somee hee evens ee EEEa Penn SAn ie 14 2 331 Default Switch Settings isc sessissces chs sc cih sp ssesceests chess cpus sce sbscepuepueadvenssbencessessty shesssbvassbeeses 14 2 3 2 Memory Module MEM 0000 cecceececeeeeeeceeceeseeseecaeesaecaeceaecnecsaeeseeeseeeseeeeeeeeneeegs 18 2A Powering UP t rieo ierse aas eE a E ra EEEIEE IEE re OSEE EES ESAs EIEEE EEES taessucleseices 19 2 4 1 VME Slot 1 Device Special Considerations essesssessesesessessessserreersrseresersreserssrese 19 24 27 lt VMEbUS SYSRESET ne a E a aE a a EEn e 20 242 1 SYSRESELMp t enie n ea scene E E a iia 20 2422 SYSRESET OUUTE EEE EE AERE E E RTE 20 24 3 N o T E1 E 0 SAA E A A EEA 20 2 4 4 RESET and ABORT Key Enable ou ce ceeeseeesecesseceececeeecsaeceaeeceeeeeaaeeeeeeaeeeeeeeeees 21 2 4 5 Front Panel SCSI 1 Termination 0 ccc ceccesccsssseecsssceessneecneseeeceeeecssseecsseeeeeseeeenees 21 2 46 P2 SCSI Termination enee incline tase ha eae Sas 21 2 4 7 Boot Flash EPROM Write Protection ccccccccesseecsssecessneecnsseeeceeeeenseeecsseeeesneeeenas 22 2 4 8 User Flash EPROM Write Protection ccccccccccsssecssseceesseecseseeeceneecnseeeceseeeesneeeenas 22 24 9 Reserved Switches seid chet E Aiea ee lg SIS 22 2 4 10 Floppy Interface or SCSI 2 Availability on P20 eee cee ceeceseeeeceseeeee
115. esent the size of the slave win dow that has been made available to the VMEbus Thus lower encodes the lower boundary of the slave window address bits A27 to A20 and upper encodes the upper boundary of the slave window address bits A27 to A20 vme slavewin base lower upper sets the VMEbus interface s Slave Base Registers The address of the slave window is represented by the triple base lower and upper The value of base represents the VMEbus address bits A31 to A28 one of 16 possible 256 Mbyte pages The value of Jower and upper represent the size of the slave win dow that has been made available to the VMEbus Thus lower encodes the lower boundary of the slave window address bits A27 to A20 and upper encodes the upper boundary of the slave window address bits A27 to A20 vme slavewin size size code sets the size of the slave window The value of size code may be one of the values zero through six Each value specifies one of the seven slave window sizes as stated in the table below size code Window Size Oo Movie 2 Mbyte 4 Mbyte 8 Mbyte 16 Mbyte 32 Mbyte 64 Mbyte O a A O N vme slavemap byte returns the contents an 8 bit data of the S4 s Slave Map Register vme slavemap byte stores the 8 bit data byte in the S4 s Slave Map Register Page 154 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements vme
116. ess dest addr NOTE When these commands are used to exchange data between two participants running OpenBoot then a third participant must be available which provides BusNet master function ality This is necessary because OpenBoot does not provide BusNet master functionality As shown in the figure below three participants take part in communicating across the network using the BusNet protocol The logical address of the participants are zero seven and five The participants Po and P are executing OpenBoot and the participant P runs an operating system which is capable of providing BusNet master functionality for example Solaris SunOS or VxWorks FORCE COMPUTERS Page 191 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual ok 4000 1meg 5 demo send data ok 4000 1lmeg 0 demo receive data Po P7 P5 Transmitter BusNet Receiver Master When a certain amount of data located in the on board memory of the participant zero P the transmitter should be transfered to the participant five P the receiver then the following command must be used on the transmitter ok 4000 1lmeg 5 demo send data This command initiates a transmission of 1 Mbyte of data located at address 4000 in the transmitter s on board memory to the receiver To enable the receiver to receive the data the following command must be used ok 4000 1lmeg 0 demo receive data This command initiates the receipt of da
117. ess space The vir tual address returned by the command is stored in the variable my mem which has been defined by the first command value The variable my mem may be used later to access the on board memory reset vme slave vaddr size resets the VMEbus slave interface associated with the virtual address vaddr and destroys all mappings which were necessary to make the memory available to VMEbus ok my mem 1Meg reset vme slave ok FORCE COMPUTERS Page 139 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 2 VMEbus Interface The VMEbus interface on the SPARC CPU STE consists of the S4 chip and additional circuitry 5 2 1 Generic Information The commands described below are used to retrieve generic information about the VMEbus interface s4 va vaddr returns the virtual base address vaddr of the registers included in the S4 vmect 1 va vaddr returns the virtual base address vaddr of additional control and sta tus registers included in the VMEbus interface s4 ct1 vaddr returns the virtual base address vaddr of the registers included in the S4 vmect1 vaddr returns the virtual base address vaddr of additional control and status registers included in the VMEbus interface 5 2 2 Register Addresses The commands described below are used to obtain the virtual addresses of specific registers in the S4 and the additional VMEbus Interface Register s4 bus locker
118. eturns the contents an 8 bit data of the VMEbus Inter face s General Purpose Register 1 The state of the most significant three bits SYS STAT bit 7 SYSVME bit 6 and SYSNMIP bit 5 are preserved but the least significant five bits are cleared 0 vme sysfail assert irq ena allows the VMEbus interface to generate an interrupt upon the assertion of the VMEbus SYSFAIL signal vme sysfail assert irq dis disables the interrupt to be generated upon the assertion of the VMEbus SYSFAIL signal vme sysfail assert ip true false checks whether an interrupt is pending due to the assertion of the VMEbus SYSFAIL signal and returns a flag set according to the appropriate interrupt pending flag The flag is true when the interrupt is pending otherwise its value is false reset sysfail irg clears a pending non maskable interrupt generated by the assertion of the VMEbus SYSFAIL signal vme acfail true false determines the state of the VMEbus ACFAIL signal and returns a flag set according to the signal s state When the ACFAIL signal is asserted the flag returned is true otherwise it is false vme acfail byte returns the contents an 8 bit data of the VMEbus interface s General Purpose Register 2 The state of the bit ACSTAT bit 6 and ACNMIP bit 4 are preserved but all other bits are cleared 0 vme acfail assert irq ena
119. ev 6 0 0 110 User EPROM first 512 KB of Dev 7 0 1 110 User EPROM second 512 KB of Dev 7 0 0 111 User EPROM first 512 KB of Dev 8 0 1 111 User EPROM second 512 KB of Dev 8 Page 82 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 6 13 RTC NVRAM The MK48T08 combines an 8 K x 8 full CMOS SRAM a bytewide accessible Real Time Clock a crystal and a long life lithium carbon monofluoride battery all in a single plastic DIP package The MK48T08 is a nonvolatile pin and functionally equivalent to any Jedec standard 8 K x 8 SRAM For a detailed description of the RTC NVRAM please see the respective data sheet 3 7 VMEbus Interface The CPU STE utilizes the Sun S4 VME chip to provide a complete 32 bit VMEbus interface Supported functions include master and slave data transfer capabilities VMEbus interrupt handling and arbitration functions Additional VMEbus utility functions and a special loop back cycle for stand alone testing of the interface are provided 3 7 1 Features of the SPARC CPU 5TE VMEbus Interface e A32 A24 A16 Master and A24 A32 Slave DVMA device as SBus Master device e Full 4 Gigabyte VME addressing with mapping register e Enhanced Slave Mode with programmable slave base address and slave window size e System Controller Functions e Single level or round robin arbitration with bus arbiter timer e TACK Daisy Chain driver e SYSCLK Clock driver e SYSRESET driver e VM
120. ew Addresses 0 cccccscccesssecessecesescecesseceesseeceseeceessseeenenaes 75 3 0 9 Boot EPROM ss 3 sccssssehstsaveussatisoussseasies eraras Oaa aaa SE E EES EEEE S 76 3 06 10 User Flash EPROM ont E EE E AE EES 77 3 6 11 Programming the On board Flash Memories 0 00 ce eeeeceseeeeceeeeeeceeeeeeeeneeeeeeneesaeenees 78 3 6 12 Programming Control Bits for Flash Memory DevViceS ssseeceecseeseeeeceeeeeneeseens 79 3 6 12 1 Default CPU 5CE Modes assener cseeseecseessecneceseceeceseeseeeseeseceaeeeeseaeeees 79 3 6 12 2 Enhanced CPU 5TE Mode 3 3 2 ccsscstsccscssgessseassessovsnsssatsaesess spshsasssenssssgescteics 81 3 6 13 RTCNV RAM 925 fe c5s a E oie S Seiad E E E E ee 83 3 1 MMEDUS Interac areen a r e a E a aa A RE 83 3 7 1 Features of the SPARC CPU 5TE VMEbus Interface esseseseseseeeeeeeeersreereseerrsreresreee 83 37 2 M ster Interac E ae e o toes e a eea T EE TN ea 83 3 7 2 1 VMEbus Master Address Implementation 0 0 eee eeeeceeceeeceeeeeeeeneeees 83 S722 Data Bus SIZES stedscice s amp ves cions cossneust r eE K ites EE EES NE 87 ZLI Slave nterf enra n a cashed A d otek EE bees a A E EE aa AAEE ARA 88 3 7 3 1 VMEbus Slave Address Modes ceccescesssecececerceencceeeeesseceeeeceeeeaeeeeeeeee 90 3 7 3 2 VMEbus Default Slave Mode cceccssessecsceeeceecesecesceseeeeceeeeeeeeseeneeeaeeess 91 3 7 3 3 VMEbus Slave Enhanced Mode cece cseceseceeceseeeeceseeeseeeeeseeeaeeees 91 3 7 4
121. f the second on board 10baseT Ethernet Interface TPE When the value of this configura tion parameter is t rue the link test capability is enabled Otherwise the value of the configuration parameter is false the link test capability is disabled default true Page 180 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 7 2 Device Aliases The following device aliases are provided by the OpenBoot for the SPARC CPU STE to identify a certain device associated with the second MACIO disk20 iommu sbus espdma l1 8400000 esp 1 8800000 sd 0 0 disk21 iommu sbus espdma l1 8400000 esp 1 8800000 sd 1 0 disk22 iommu sbus espdma l1 8400000 esp 1 8800000 sd 2 0 disk23 iommu sbus espdma l1 8400000 esp 1 8800000 sd 3 0 tape21 iommu sbus espdma l1 8400000 esp 1 8800000 st 5 0 tape20 iommu sbus espdma l1 8400000 esp 1 8800000 st 4 0 tape2 iommu sbus espdma l1 8400000 esp 1 8800000 ste4 0 cdrom2 iommu sbus espdma l 8400000 esp 1 8800000 sd 6 0 d disk 2 iommu sbus espdma l1 8400000 esp 1 8800000 sd 3 0 net2 iommu sbus ledma 1 8400010 le 1 8c00000 net2 tpe iommu sbus ledma 1 8400010 tpe le 1 8c00000 net2 aul iommu sbus ledma 1 8400010 aui le 1 8c00000 scsi2 iommu sbus espdma l1 8400000 esp 1 8800000 FORCE COMPUTERS Page 181 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 8 BusNet Support In general the OpenBoot shoul
122. fff 8000 set vme master ok The particular VMEbus area can be accessed using the standard commands available in OpenBoot to read and store data The virtual base address to access the VMEbus is stored in the variable vmebus The example shown below reads a single byte from the VMEbus through the VMEbus interface which has been prepared for accessing the VMEbus using one of the three examples mentioned above ok vmebus c ok The command set vme master modifies the contents of the following two variables vme dpr vaddr returns the virtual address vaddr of the memory which has been made available to the VMEbus my vme base paddr returns the physical address paddr of the memory which is accessible from the VMEbus free vme mem releases all virtual and physical memory allocated by the command vme set master and allocated by the commands to setup the VMEbus slave interface FORCE COMPUTERS Page 153 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual 5 2 9 VMEbus Slave Interface The commands listed below are available to control the VMEbus slave interface vme slavewin base lower upper returns the current contents of the VMEbus inter face Slave Base Registers The address of the slave window is represented by the triple base lower and upper The value of base represents the VMEbus address bits A31 to A28 one of 16 possible 256 Mbyte pages The value of Jower and upper repr
123. floppy interface ere eel eee aie a Or Plug the interface into sockets B3 B1 and B9 B8 for the SCSI 2 interface a EOI B10 B9 B8 CAUTION If you use an IOBP DS the switch matrix must be located on B3 B1 and B9 B8 in order to route SCSI 2 to P2 row C If you use an IOBP 10 the switch matrix must be located on B2 B3 and B10 B9 in order to route the floppy interface to P2 row C FORCE COMPUTERS Page 23 Installation SPARC CPU 5TE 2 4 11 Network Interface Selection NIS for Ethernet It is important to understand that the Ethernet is selected either via the twisted pair connector or the AUI Attachment Unit Interface When you boot your system and a connection exists with an AUI network then the AUI is automatically selected In other words when you have a successful connection with a network the AUI is used When you have no connection with the network then the twisted pair is selected This is valid for both Ethernet 1 and Ethernet 2 The Ethernet 1 channel and the Ethernet 2 channel function independently of each other For both Ethernet interfaces there is one Ethernet address This means that you don t have to connect both interfaces to one physical cable 2 4 12 Parallel Port The availability of the parallel port is dependent upon the availability of a 5 row P2 connector When using a 3 row P2 connector parallel port is not available Page 24 FORCE COMPUTERS SPARC CPU 5TE Installation
124. ge 84 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Hardware Description The VMEbus master interface allows the following three address ranges Table 42 VMEbus Address Ranges Address Offset Mode Lines Short Form Physical Used Address Extended A01 A31 A32 0000 0000 Addressing Standard AO1 A24 A24 FF00 0000 Addressing Short AO1 A15 A16 FFFF 0000 Addressing CAUTION In order to access the A16 or the A24 VMEbus address range the VME_A 28 bit of the above described vme_a32map register must be set All supported address modifier combinations are shown in the next table Table 43 Supported Address Modifier Codes TRA Pen Transfer Mode 2D A16 Short Supervisory Access 29 A16 Short Non Privileged Access 3D A24 Standard Supervisory Data Access 39 A24 Standard Non Privileged Data Access 0D A32 Extended Supervisory Data Access 09 A32 Extended Non Privileged Data Access FORCE COMPUTERS Page 85 Hardware Description SPARC CPU S5TE Technical Reference Manual To choose the access mode Supervisory or Non Privileged a software controlled bit called SUPV SUPerVisory mode in the vme_ctl register directly reflects the Address Modifier Bit 2 Physical Register Address Namie Read Write Access 7138 0003 vme_ctl r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 res
125. ge with Right To Use license VMEbus driver on tape Solaris 1 x OLDS CPU STE Solaris 1 x package with Right To Use license Online DiskSuite for Solaris 1 x VMEbus driver on tape FORCE COMPUTERS Page 7 Introduction SPARC CPU S5TE Technical Reference Manual Table 3 Ordering Information cont Catalog Name Product Description Solaris 1 x CPU S5TE RTU Solaris 1 x Right To Use license Without media Solaris 1 x CPU 5TE RTU Solaris 1 x multiuser Right To Use license Without media Solaris 1 x UM Solaris 1 x Operating System User Manual VxWorks DEV SPARC VxWorks development package for SPARC host and target Products VxWorks BSP CPU 5TE VxWorks board support package for CPU 5TE Page 8 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual 1 7 History of the Manual Introduction Below is a description of the publication history of this SPARC CPU 5TE Technical Reference Manual Table 4 History of Manual Edition No Description Date of Last Change First Print June 1995 VME P2 and IOBP DS Connector Pinout has been corrected The default switch setting of SW4 1 and the description of the memory module MEM 5 have been corrected Description of the Ethernet address and host ID has been updated The 2 sections Controlling the VMEbus Mas ter and Slave Interface and BusNet Support have been added November 1996 2 1 Th
126. he twisted pair is selected This is valid for both Ethernet 1 and Ethernet 2 The Ethernet 1 and the Ethernet 2 channels function independently of each other Page 64 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual 3 5 5 1 Hardware Description Network Interface 1 Control And Status Register The Network Interface 1 Control and Status Register is used for the twisted pair network of Ethernet 1 Physical Register Addres NANE Read Write Access 713C 0000 Network r w 8 bit Interface 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 1 1 1 1 1 1 TP1 TP1 STAT TENA Table 30 Network Interface 1 Control And Status Register Read Setting Write Function TP1_TENA 0 r w Link Test enabled for Ethernet 1 TP TP1_TENA 1 r w Link Test disabled for Ethernet 1 TP TP1_STAT 0 T AUI 1 selected or LinkTest 1 disabled or Link for TP 1 failed TP1 STAT 1 r TP 1 selected LinkTest 1 enabled and Link for TP 1 succeeded FORCE COMPUTERS Page 65 Hardware Description 3 5 5 2 The Network Interface 2 Control And Status Register is used for twisted pair network of SPARC CPU 5TE Technical Reference Manual Network Interface 2 Control And Status Register Ethernet 2 Physical Register Addres NANE Read Write Access 713C 0001 Network r w 8 bit Interface 2 Bit7 Bit6 Bit5 Bit4
127. he values in the range of one through seven Each value specifies one of the seven VMEbus interrupt request levels Only the least significant three bits of level are considered and when level is zero then the command treats it as if the value one has been passed to the command vme vectors displays the VMEbus interrupt vectors received during the last inter rupt acknowledge cycle OpenBoot maintains seven variables called vme intr 1 2 3 4 5 6 7 vec FORCE COMPUTERS Page 147 OpenBoot Enhancements SPARC CPU 5TE Technical Reference Manual tor which are modified by the VMEbus interrupt handlers In general the interrupt handlers store the vector obtained during an interrupt acknowledge cycle in the appro priate variable 5 2 5 VMEbus Arbiter The commands described below are available to control the VMEbus arbiter as well as to retrieve information about the state of the VMEbus arbiter vme arb mode mode returns the mode the arbiter is currently operating in The value of mode may range from zero to one Each value specifies a particular mode the value zero indicates that the arbiter is operating in the priority mode which means that the arbiter is operating as a single level arbiter at level 3 The value one specifies the round robin mode vme arb mode mode selects the arbiter mode specified by mode The value of mode may range from zero to one Each value specifies a particular mode the val
128. hnical Reference Manual OpenBoot Enhancements 5 7 Second SCSI and Ethernet Interface 5 7 1 Additional Commands to Control the Network Interfaces ni test true false ni enables or disables the twisted pair network interface s link test capability The network number ni which specifies the proper network interface may be one or two Each value specifies one of the two available network interfaces The value one specifies the first network interface and the value two specifies the sec ond network interface In the case that the value of ni is neither one nor two the com mand assumes that the first network interface is specified When the value true is passed to the command then the network interface s test capa bility is enabled Otherwise the value false is passed to the command the net work interface s test capability is disabled ni test ena ni enables the twisted pair network interface s link test capability The network number ni which specifies the proper network interface may be one or two Each value specifies one of the two available network interfaces The value one speci fies the first network interface and the value two specifies the second network inter face In the case that the value of ni is neither one nor two the command assumes that the first network interface is specified ni test dis ni disables the twisted pair network interface s link test capability The network
129. hnical Reference Manual OpenBoot Enhancements SECTION 5 OPENBOOT ENHANCEMENTS 5 OpenBoot This section describes the enhancements to the standard OpenBoot firmware that have been done for the SPARC CPU STE For a description of standard OpenBoot firmware features please see the OPEN BOOT PROM 2 0 MANUAL SET Besides the commands already provided by the standard OpenBoot firmware the OpenBoot firmware available on the SPARC CPU STE includes additional words for the following e accessing and controlling the VMEbus interface e accessing and programming available flash memories e controlling the operating mode of the Watchdog Timer and e making use of the Diagnostics The following subsections describe these words in detail and examples are given when it seems necessary to convey the usage of a particular or a group of words In general each word is described using the notation stated below name stack comment description The name field identifies the name of the word being described The stack parameters passed to and returned from a word are described by the stack comment notation enclosed in parentheses and show the effect of the word on the evaluation stack The notation used is parameters before execution parameters after execution The parameters passed and returned to the word are separated by the dash The description body describes the semantics of the word and conveys the purpose and effect of
130. iari ate i gies 112 Table 61 Interrupt Mapping occa sassaasccesdcacisnssea uss coaatasegndeceaved cave a Ra a n 162 Page viii FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual Introduction SECTION 1 INTRODUCTION 1 Getting Started This SPARC CPU STE Technical Reference Manual provides a comprehensive guide to the SPARC CPU STE board you purchased from FORCE COMPUTERS In addition each board delivered by FORCE includes an Installation Guide Please take a moment to examine the Table of Contents of the SPARC CPU STE Technical Reference Manual to see how this documentation is structured This will be of value to you when looking for information in the future 1 1 The SPARC CPU 5TE Technical Reference Manual Set When purchased from FORCE this set includes the SPARC CPU STE Technical Reference Manual as well as three additional books These three books are listed here microSPARC II STP1012PGA User s Manual Set of Data Sheets for the SPARC CPU 5TE OPEN BOOT PROM 2 0 MANUAL SET The Set of Data Sheets for the SPARC CPU STE contains the following data sheets NCR SBus I O Chipset Data Manual Sun Microsystems S4 Chip Set Rev 4 SGS THOMSON M48T08 AMD Flash EPROM AM28F020 T7213 Dual Interface Station Chip Intel Flash Memory 28FO08SA L The OPEN BOOT PROM 2 0 MANUAL SET contains the following three sections Open Boot 2 0 Quick Reference FCODE Programs Open Boot 2 0 Command Reference 1 2 Terminology Throughout this
131. ice Recognition This depends on SW10 2 2a setting If SW10 2 is Off the Not Slot 1 Device is selected and if SW10 2 is ON the Automatic Slot 1 Device Recognition is selected See also VME Slot 1 Device Special Consider ations on page 19 SW10 2 ON VMEbus Slot 1 Device ON Automatic Slot 1 Device Recognition OFF Not Slot 1 Device If SW10 1 is On this switch is don t care See also VME Slot 1 Device Special Consider ations on page 19 SWITCH 11 SW11 1 ON SYSRESET received from VMEbus ON VMEbus SYSRESET generates on board ON RESET OFF VMEbus SYSRESET does not generate on board RESET i 0 0 SW11 2 ON VMEbus SYSRESET Generation ON SYSRESET is driven to VMEbus if board is Slot 1 Device or during power up reset OFF SYSRESET is not driven to VMEbus SWITCH 12 SW12 1 OFF RTXC on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port B ON 1 SW12 2 ON CTS on Front Panel Connector for RS 232 or CTS on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port A N 0000 SW12 3 OFF RTXC on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port A SW12 4 OFF Test Switch must be OFF Page 16 FORCE COMPUTERS SPARC CPU 5TE Installation Table 5 Default Switch Settings cont
132. ieve information about the state of the abort switch abort nmi ena allows an interrupt to be generated when the abort switch is pressed abort nmi dis disables the interrupt s ability to be generated when the abort switch is being pressed abort ip true false checks whether an interrupt is pending because the abort switch has been pressed The value true is returned when the interrupt is pending oth erwise the value false is returned abort irgq pending true false checks whether an interrupt is pending because the abort switch has been pressed The value true is returned when the interrupt is pending otherwise the vallue false is returned abort nmi clear clears a pending interrupt caused by pressing the abort switch reset abort irq clears a pending interrupt caused by pressing the abort switch 5 3 3 Seven Segment LED Display and Rotary Switch The commands described below are available to control the seven segment LED display as well as to retrieve information about the state of the rotary switch diag led byte stores the data byte passed to the command in the register used to control the seven segment display gt 7 seg code u 7 seg code converts the value u to its corresponding seven segment code 7 seg code Only the least significant four bits of the value u are considered led colour controls the user LED identified The p
133. ing takes the form of a 64 byte data cache and 16 bit wide buffer for the Ethernet channel and a 64 byte FIFO for both the SCSI channel and the parallel port The DMA2 incorporates an improved cache and FIFO draining algorithm which allows better SBus utilization than previous DMA implementations FORCE COMPUTERS Page 61 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 5 1 Features of the NCR89C100 on the SPARC CPU 5TE e Fast 8 bit SCSI e Supports fast SCSI mode e Backward compatible to 53C90A e 7990 compatible Ethernet e Parallel Port 1 0 or DMA programmable modes e Centronics compatibility e LS64854 compatible DMA2 Controller e Glueless SBus Interface clocked with 21 25 MHz 85 MHz processor frequency e Concurrently supports e 10 MB sec SCSI transfers e 3 4 MB sec parallel port transfers e 1 25 MB sec Ethernet transfers e 64 byte FIFO for SCSI and parallel port data e Supports SBus burst modes e 4 word 8 word and no burst e Packaged in 160 pin PQFP For further information about the NCR89100 please see NCR SBus I O Chipset Data Manual Page 62 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 5 2 SCSI The SCSI interface provides a standard interface to a wide variety of mass storage devices such as hard disks tapes and CD ROMs The SCSI transfers up to 10 Mbytes per second The SPARC CPU STE board has two independent SCSI interfaces SCSI 1 and SCSI 2
134. interrupt request level and returns a flag When an interrupt is pending the flag is true otherwise it is false The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VMEbus interrupt request levels Only the least significant three bits of level are considered and when level is zero then the command treats it as if the value one has been passed to the command The command verifies the state of the bit in the VMEbus Interrupt Status Register associated with the given level When the corresponding status bit is set then no VMEbus interrupt is pending and the command returns false Otherwise the status bit is cleared the value true is returned vme iack level vector initiates an interrupt acknowledge cycle at the given VMEbus interrupt request level and returns the obtained 8 bit vector The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VMEbus interrupt request levels Typically the vector returned is within the range of 0 through 255 However when no interrupt is pending and consequently no interrupt has to be acknowledged then the value 1 is returned Only the least significant three bits of level are considered and when level is zero then the command treats it as if the value one has been passed to the command vme intr ena mapping level enables the interrupt to be generated
135. ipeline e Floating Point Unit e SPARC Reference Memory Management Unit e A 16 Kbyte instruction cache and an 8 Kbyte data cache directly mapped e Memory interface which supports up to 256 Mbyte DRAM e SBus controller supports up to five SBus slots plus one master only slot Page 56 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual 3 1 2 Address Mapping for microSPARC II Hardware Description The table below lists the physical addresses of the microSPARC II processor Table 26 Physical Memory Map of microSPARC II FORCE COMPUTERS Address Function 0000 0000 gt User Memory OFFF FFFF 1000 0000 gt Control Space 1FFF FFFF 2000 0000 gt AFX Frame Buffer 2FFF FFFF 3000 0000 gt SBus Slave Select 0 3FFF FFFF 4000 0000 gt SBus Slave Select 1 4FFF FFFF 5000 0000 gt 5FFF FFFF SBus Slave Select 2 6000 0000 gt 6FFF FFFF SBus Slave Select 3 7000 0000 gt 7FFF FFFF SBus Slave Select 4 Page 57 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 2 The Shared Memory The microSPARC I chip interfaces directly to a 64 bit wide DRAM on one side and to the SBus on the other side The microSPARC II chip supports up to eight memory banks bank 0 to bank 7 The signals for all the memory banks are routed to the memory module connectors for module 1 and module 2 Memory connector for memory module 1 supports banks 0 1
136. it6 Bit5 Bit4 Bit3 Bit2 Bitl BitO Reserved SMODE SUPV SAMODE Reserved WIN2 WINI WINO Initialization All bits are cleared to Os at reset Description WIN2 WINO set the VMEbus slave window size if the enhanced slave mode is selected wmn2 wini wmo Window Size 0 0 0 1 Mbyte 0 0 1 2 Mbyte 0 1 0 4 Mbyte 0 1 1 8 Mbyte 1 0 0 16 Mbyte 1 0 1 32 Mbyte 1 1 0 64 Mbyte 1 1 1 transparent FORCE COMPUTERS Page 117 Hardware Description SPARC CPU S5TE Technical Reference Manual SAMODE sets the VMEbus Slave Address mode Setting Function SAMODE 0 VME Extended A32 Mode SAMODE 1 VME Standard A24 Mode SUPV distinguishes between non privileged and supervisory mode in the VMEbus master interface Setting Function SUPV 0 Non privileged Address Mode SUPV 1 Supervisory Address Mode SMODE sets the VMEbus Slave mode There is a default mode which is a compatible mode to the SPARC CPU 2CE and there is an enhanced mode which has improved features regarding the VMEbus slave window Setting Function SMODE 0 Enhanced Mode SMODE 1 Default Mode Page 118 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 7 vme_a32map Register The vme_a32map register integrates the programming of the four upper VMEbus master address bits as well a
137. itiated by the hardware watchdog timer To reset the pending NMI write a one to that bit WNMIR is a write only bit FORCE COMPUTERS Page 125 Hardware Description 3 10 11 The Network Interface 1 Control and Status register is used to control the twisted pair SPARC CPU S5TE Technical Reference Manual Network Interface 1 Control and Status Register connection for Ethernet 1 Network Physical A Address Register Name Read Write Access 713C 0000 Network Interface 1 r w 8 bit and Status Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO 1 1 1 1 1 1 TP1 TP1 STAT TENA Page 126 NOTE TP1_STAT is a read only bit Setting Function TP1_STAT 1 Link is up for Ethernet 1 for twisted pair TP1_STAT 0 Link is down for Ethernet 1 for twisted pair if TP1_TENA is set 1 Setting Function TP1_ TENA 1 Link Test is enabled for Ethernet 1 for twisted pair TP1_TENA 0 Link Test is disabled for Ethernet 1 for twisted pair FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 10 12 Network Interface 2 Control and Status Register The Network Interface 2 Control and Status register is used to control the twisted pair connection for Ethernet 2 Network Physical P Address Register Name Read Write Access 713C 0001 Network Interface
138. lers In general the interrupt handlers store the vector obtained during an interrupt acknowledge cycle in the appropriate variable The state of these variables is displayed by ok vwme vectors Jrg ae Digs om Bee SS Are E 5 3 3 6 gt mie aa ok By default the value 1 t rue is assigned to these variables to indicate that no VMEbus Page 174 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 29 interrupt occurred So the word vme vectors as shown above will display indicating that no interrupt occurred otherwise it shows the vector obtained a value in the range of 0 to FFj Another way to display the state of a variable used to store the interrupt vector is ok vme intr5 vector 33 ok and the variable is set to 1 t rue by ok vme intr5 vector on ok An interrupt handler is removed and the corresponding interrupt is disabled by ok 5 uninstall vme intr handler ok All interrupt handlers serving all VMEbus interrupts are installed by ok 0 pil ok 8 1 do i i install vme intr handler loop ok In this case all interrupt handlers are installed and the VMEbus interrupt to SBus interrupt mapping is as follows SBus interrupt level 1 is generated upon the occurrence of a VMEbus interrupt 1 SBus interrupt level 2 is generated upon the occurrence of a VMEbus interrupt 2 and so forth 5 5 2 SYSEFAIL Interrupt OpenBoot for the SPARC CPU STE already includes an interrupt h
139. llowing regarding switches Do not set the switches SW8 3 and SW12 4 or SW9 4 and SW9 3 or SW12 2 and SW12 3 to ON at the same time and do not set the switches SW8 2 and SW8 1 or SW8 4 and SW9 2 or SW9 1 and SW12 1 to ON at the same time Please see the Diagram of the CPU 5TE Bottom View on page 13 for the location of the switches on the board 3 6 5 Keyboard and Mouse Port The keyboard and mouse port is available on the front panel via an 8 pin Mini DIN connector and on the VME P2 Connector The serial port controller used for the keyboard and mouse port is compatible with the NMOS 8530 controller The pinout of the keyboard and mouse port is described in Section 2 Installation The physical address for the keyboard and mouse port is shown in NCR89C105 Chip Address Map on page 68 Page 72 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 6 6 Floppy Interface The floppy disk interface is 82077AA 1 compatible It is able to transfer data rates of 250 300 500 Kbytes sec and 1 Mbyte sec The floppy disk controller block is functionally compatible with the Intel 82077AA 1 It integrates drivers receivers data separator and a 16 byte bidirectional FIFO The floppy disk controller supports all standard disk formats typically 720 K and 1 44 M floppies It is also compatible with the 2 88 MB floppy format 3 6 7 Floppy Interface or SCSI 2 Availability on P2 It is imp
140. lowing local I O devices are interfaced via the NCR89C105 Table 35 8 Bit Local I O Devices S Physical Base Function IRQ y Address Boot Flash EPROM No 7000 0000 gt Device 1 7003 FFFF 256 Kbyte default Boot Flash EPROM No 7004 0000 gt Device 2 7007 FFFF 256 Kbyte default User Flash EPROM No 7010 0000 gt 1 Mbyte Device 1 701F FFFF User Flash EPROM No 7020 0000 gt 1 Mbyte Device 2 702F FFFF User Flash EPROM No 7030 0000 gt 1 Mbyte Device 3 703F FFFF User Flash EPROM No 7040 0000 gt 1 Mbyte Device 4 704F FFFF User Flash EPROM No 7050 0000 gt 1 Mbyte Device 5 705F FFFF User Flash EPROM No 7060 0000 gt 1 Mbyte Device 6 706F FFFF User Flash EPROM No 7070 0000 gt 1 Mbyte Device 7 707F FFFF User Flash EPROM No 70800000 gt 1 Mbyte Device 8 708F0000 RTC NVRAM No 7120 0000 gt 712F FFFF Flash EPROM Programming Area No 7130 0000 gt 7137 FFFF Additional Registers No 7138 0000 gt 713F FFFF FORCE COMPUTERS Page 75 Hardware Description SPARC CPU S5TE Technical Reference Manual 3 6 9 Boot EPROM The Boot EPROM consists of two 2 Mbit or 4 Mbit flash memory devices In the default configuration there are two 2 Mbit devices installed The 4 Mbit devices are an additional assembly option The Boot EPROM devices can be reprogrammed on board and can also be write protected via hardware swi
141. lueless interface to the SBus is provided The slave I O also includes an 8 bit expansion bus with control to support RTC NVRAM EPROM and generic 8 bit devices externally 3 6 1 Features of the NCR89C105 on the SPARC CPU 5TE e Dual channel serial ports 8530 compatible e Keyboard mouse port e 82077AA 1 floppy disk controller e 8 bit expansion bus for EPROM TOD NVRAM e Glueless SBus interface clocked with 21 25 MHz 85 MHz processor frequency e Interrupt controller e System reset control e Programmable 22 bit counters amp timers e Auxiliary I O registers e Packaged in 160 pin PQFP For further information about the NCR89105 please refer to the NCR SBus I O Chipset Data Manual FORCE COMPUTERS Page 67 Hardware Description 3 6 2 The following table lists the physical addresses for all local I O devices and the accesses Address Map of Local I O Devices on SPARC CPU 5TE SPARC CPU S5TE Technical Reference Manual permitted 7 B yte H alf Word and W ord Page 68 Table 32 NCR89C105 Chip Address Map Physical i y Device Access Address 7000 0000 gt Boot EPROM and User EPROM B H W 70FF FFFF 7100 0000 gt Keyboard Mouse and Serial Ports B 711F FFFF 7100 0000 Mouse Control Port 7100 0002 Mouse Data Port 7100 0004 Keyboard Control Port 7100 0006 Keyboard Data Port 7110 0000 TTYB Control Port 7110 0002 TTYB Data Port 7110 0004 TTYA Control Port 7110 0006
142. mental Conditions Temperature Operating Temperature Storage 0 C to 50 C 40 C to 85 C Humidity 0 to 95 noncondensing Board Size Single Slot 6U VMEbus 160 00 x 233 35 mm 6 29 x 9 18 inches FORCE COMPUTERS Page 5 Introduction SPARC CPU S5TE Technical Reference Manual 1 6 Product Nomenclature FORCE COMPUTERS SPARC CPU STE is available in several memory and speed options Consult your local sales representative to confirm availability of specific combinations The table below explains the product nomenclature Table 2 Product Nomenclature CPU 5TE 16 85 0 85 MHz microSPARC II CPU board with 16 Mbyte DRAM memory module 1 free memory expansion slot dual SCSI 2 dual Ethernet floppy disk keyboard mouse port 2 serial I O prots 32 bit VMEbus interface 2 SBus slots OpenBoot firm ware Installation guide included CPU 5TE 64 85 0 Same as above except 64 Mbyte DRAM MEM 5 16 16 Mbyte mezzanine memory module for use on the SPARC CPU STE MEM 5 64 64 Mbyte mezzanine memory module for use on the SPARC CPU STE 1 6 1 Ordering Information The next page contains a list of the product names and their descriptions Page 6 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Table 3 Ordering Information Introduction Catalog Name Product Description SBus Modules SBus GX Color 2 D and 3 D wireframe graphics accelerator 1152
143. mmand set vme slave performs all steps to make a specified amount of memory available at a specific VMEbus address space The command reset vme slave removes the on board memory from the VMEbus address space set vme slave offset space size vaddr initializes the VMEbus slave interface according to the parameters passed to the command and returns the virtual address vaddr of the memory which has been made available to the VMEbus OpenBoot pro vides all necessary mappings MMU and IOMMU to access the memory from the processor and the VMEbus The parameters space and offset specify where the slave interface is accessible within the VMEbus address range The parameter offset specifies the physical base address of the slave interface within the particular address space The size of the memory that should be made available to the VMEbus is given by size Example Assumed that 1 MByte of on board memory should be made available to the extended A32 address space of the VMEbus beginning at the VMEbus address 4080 000016 the commands listed below have to be used ok 0 value my mem ok 4080 0000 vmea32d32 1lmeg set vme slave is my mem ok The first command defines a variable my mem which is later used to store the virtual address of the on board memory which has been made available to the VMEbus The second command listed above makes 1 MByte beginning at physical address 4080 000016 available within the extended A32 VMEbus addr
144. mory select flash USER lt eol gt BOOT lt eol gt prepares either the BOOT flash memories or the USER flash memories for programming In detail the number and size of the available flash memories are determined as well as the size of the flash memory programming window The flash memory programming window is mapped and the virtual base address of the window is stored internally and may be obtained by using the word flash va user flash true false checks whether the BOOT flash memory or the USER flash memory is accessible through the flash memory programming window It returns true in the case that the USER flash memory is accessible through the programming window otherwise it returns false move gt flash source addr dest addr count programs the selected flash memory beginning at dest addr with a number of bytes specified by count stored at source addr flash gt move source addr dest addr count copies a number of bytes specified by count from the selected flash memory beginning at source addr to dest addr The flash memory is accessed through the flash memory programming window for reading data from the memory Thus the flash memory has to be prepared for access using the FORCE COMPUTERS Page 167 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual command select flash fill flash dest addr count pattern fills the selected flash memory beginning at dest addr with
145. mory The executable image to be loaded has to be either a binary image a out format a FORTH program or a FCode program As mentioned at the beginning of this section the device alias flash is available as an abbreviated representation of the flash memory device The command listed below is used to explicitly load and execute an image from the flash memory ok boot flash The following NVRAM configuration parameters can be modified to determine whether or not the system will load an executable image automatically after a power up cycle or system reset e auto boot e boot device Assuming that the SPARC CPU STE is equipped with one USER flash memory device the Page 172 FORCE COMPUTERS SP ARC CPU 5TE Technical Reference Manual OpenBoot Enhancements size of which is 1Mbyte then the following commands have to be used to load and execute an image from the flash memory automatically after a power up cycle or system reset ok setenv boot flash devices 1 bootflash devices ok setenv boot flash megs 1 bootflash megs ok setenv boot device flash boot device flash ok setenv auto boot true auto boot true ok reset 5 4 4 Controlling the Flash Memory Interface The commands listed below are available to control the flash memory interface These commands are used to make a specific flash memory device available in the flash memory programming window and to control the flash memory programming voltage fl
146. mory device path The vocabulary of the flash memory device includes the standard commands recommended for a byte device The words of this vocabulary are only available when the flash memory device has been selected as shown below ok ed flash ok words close open selftest reset load write blocks read blocks seek write read max transfer block size ok selftest O ok device end ok The example listed above selects the flash memory device and makes it the current node The word words displays the names of the methods of the VMEbus device The third command calls the method selftest and the value returned by this method is displayed The last command unselects the current device node leaving no node selected When the command select dev is used to select the flash memory device the NVRAM configuration parameters boot flash megs and boot flash devices have to be set properly before the device can be selected The NVRAM configuration parameters listed below are available to control the loading of an image from the USER flash memory The current state of these configuration parameters is displayed using the print env command It is modified using either the set env or the set default command provided by OpenBoot bootflash megs specifies the amount of available USER flash memory in megabyte default 0 Megabyte bootflash devices specifies the number of available USER flash memory devices default no devices boot flash lo
147. n below ok cd vme ok words selftest reset close open list of additional methods of the device node ok selftest O ok device end ok The example listed above selects the VMEbus device and makes it the current node The word words displays the names of the methods of the VMEbus device And the third command calls the method selftest and the value returned by this method is displayed The last command unselects the current device node leaving no node selected The following methods are defined in the vocabulary of the VMEbus device open true prepares the package for subsequent use The value true is always returned close frees all resources allocated by open reset puts the VMEbus interface into quiet state selftest error number performs a test of the VMEbus interface and returns an error number to report the course of the test In the case that the device has been tested successfully the value zero is returned otherwise it returns a specific error number to indicate a certain fail state decode unit addr len low high converts the addr and len a text string representa tion to low and high which is a numerical representation of a physical address within the address space defined by the package map in low high size vaddr creates a mapping that associates the range of physical address beginning at low extending for size bytes within the package s physical address s
148. n p mbox intr specifies the interrupt generated when the participant s mailbox is being accessed from the bus The default value of this 32 bit configuration parameter depends on the hardware capabilities of the specific machine bn p mbox specifies whether the participant provides a mailbox When this configuration parameter is t rue then the participant provides a mailbox Otherwise the participant does not provide a mailbox The default value of this configuration parameter depends on the hardware capabilities of the specific machine bn packet size specifies the size of a BusNet packet The minimum packet size allowed by the BusNet protocol is 2 Kbytes The default value of this configuration parameter is 2 Kbytes If set to another value it must be a multiple of 64 bytes The BusNet protocol does not permit participants to use different packet buffer sizes during intitialization The default value of this 32 bit configuration parameter is 2048 9 A participant is designated as master when the following pairs of configuration parameters bn master space bn p space and bn master offset bn p offset are identical When these configuration parameters are different the participant is designated as slave However OpenBoot does not support the master operation of a participant FORCE COMPUTERS Page 187 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual NOTE The default values of some described NVRAM configuratio
149. n page 27 The response depends on the selftest of the device node To test a group of installed devices type ok test all All devices below the root node of the device tree are tested The response depends on the devices that have a selftest routine If a device specifier option is supplied at the command line all devices below the specified device tree node are tested When you use the memory testing routine the system tests the number of megabytes of memory specified in the NVRAM configuration parameter selftest megs If the NVRAM configuration parameter diag switch is true all memory is tested ok test memory testing 32 megs of memory at addr 0 27 ok The command test memory is equivalent to test memory In the example above the first number 0 is the base address of the memory bank to be tested the second number 27 is the number of megabytes remaining If the CPU board is working correctly the memory is erased Page 30 FORCE COMPUTERS SPARC CPU 5TE Installation and tested and you will receive the ok prompt If the PROM or the on board memory is not working you receive one of a number of possible error messages indicating the problem To test the clock function type ok watch clock Watching the seconds register of the real time clock chip It should be ticking once a second Type any key to stop 22 ok The system responds by incrementing a number once a seco
150. n parameters may vary depending on the VMEbus interface of the particualar machine S4 MVIC FGA 5000 especially the parameters describing the mailbox of the participant The state of the NVRAM configuration parameters listed below are only considered when the Trivial File Transfer Protocol TFTP is used to load and execute an image across the network using the BusNet protocol bn arp specifies whether the BusNet driver should scrutinize all outgoing packets and ver ifies whether an Ethernet frame carries an ARP request When the flag is t rue the BusNet driver checks whether an Ethernet frame contains an ARP request and if so it resolves the request and passes the response to the receiv ing part of the BusNet driver automatically The Ethernet frame is not sent across the network The BusNet driver uses the contents of the NVRAM configuration parameters bn master ip addr bn p ip addr bn master en addr and bn p en addr to build up the appropriate response In the case that the flag is false it sends all Ethernet frames without any further ver ification across the network default false bn rarp specifies whether the BusNet driver should scrutinize all outgoing packets and verifies whether an Ethernet frame carries an RARP request When the flag is t rue the BusNet driver checks whether an Ethernet frame contains a RARP request and if so it resolves the request and passes the response to the receiv ing part of the BusNet drive
151. nd Press any key to stop the test To monitor the network connection type ok watch net Using AUI Ethernet Interface Lance register test succeeded Internal loopback test succeeded External loopback test succeeded Looking for Ethernet packets is a good packet X is a bad packet Type any key to stop Sista Xo ies Ree aa Depa A ties ok oo 99 The system monitors the network traffic displaying each time it receives a valid packet and displaying X each time it receives a packet with an error that can be detected by the network hardware interface FORCE COMPUTERS Page 31 Installation SPARC CPU 5TE 2 5 4 Display System Information The Forth Monitor provides several commands to display system information These commands let you display the system banner the Ethernet address for the Ethernet controller the contents of the ID PROM and the version number of the OpenBoot firmware The ID PROM contains information specific to each individual machine including the serial number date of manufacture and assigned Ethernet address The following table lists these commands Table 10 Commands to Display System Information Command Description banner Display system banner show sbus Display list of installed and probed SBus devices enet addr Display current Ethernet address idprom Display ID PROM contents formatted traps Display a list of SPA
152. ne of the values in the range of zero through seven Each value specifies one of the eight S4 interrupt request lines The table below contains a list of all valid mappings and the associated output pin interrupt request line mapping Interrupt Generated by S4 0 MB_IRQ connected with non maskable interrupt B_IRQ1 connected with SBus IRQ1 B_IRQ2 connected with SBus IRQ2 B_IRQ3 connected with SBus IRQ3 B_IRQ4 connected with SBus IRQ4 B_IRQ5 connected with SBus IRQ5 B_IRQ6 connected with SBus IRQ6 B_IRQ7 connected with SBus IRQ7 NI O Or By OJN xww a a l a Table 61 Interrupt Mapping Page 162 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 3 System Configuration 5 3 1 Watchdog Timer The commands described below are available to control the watchdog timer as well as to retrieve information about the state of the watchdog timer wd ena enables and starts the watchdog timer wd enable true false starts or stops the watchdog timer When the value true is passed to the command the watchdog timer is started Otherwise the value false is passed to the command the watchdog timer is stopped Once enabled the watchdog timer on the SPARC CPU STE cannot be stopped wd nmi ena allows an interrupt to be generated when half of the watchdog time has expired wd nmi dis disables the interrupt s
153. ng ok setenv diag device busnet Page 194 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 8 8 Booting from a VxWorks BusNet Server Because VxWorks currently is not capable of resolving RARP requests the NVRAM configuration parameters listed below must be set prior to loading an executable image bn rarp specifies whether the BusNet driver should scrutinize all outgoing packets and verifies whether an Ethernet frame carries an RARP request The flag must be set to t rue to enable the BusNet driver to check whether an Ether net frame contains a RARP request and if so it resolves the request and passes the response to the receiving part of the BusNet driver automatically The Ethernet frame is not sent across the network The BusNet driver uses the contents of the NVRAM configuration parameters bn master ip addr bn p ip addr bn master en addr and bn p en addr to build up the appropriate response bn master ip addr specifies the Internet Protocol IP Address of the master The default value of this 32 bit configuration parameter is zero 0 The setenv com mand is used to set this configuration parameter as shown below ok setenv bn master ip addr 0x83030001 In the example the Internet address 131 3 0 1 8303000146 is assigned to the NVRAM configuration parameter bn p ip addr specifies the Internet Protocol IP Address of the participant The default value of this 32 bit configuration
154. nnector is plugged ON into the front panel SCSI connector then termi gt nation is disabled When no connector is 1 ion plugged into the front panel SCSI connector 2a lt D then termination is enabled ON disabled SW7 2 OFF Test Switch must be OFF SW38 1 OFF Test Switch must be OFF ON SW8 2 ON TRXC on Front Panel Connector for RS 232 1 ON Available OFF Not Available 2 Serial Port B 3 SW8 3 ON TRXC on Front Panel Connector for RS 232 4 ON Available OFF Not Available Serial Port A SW8 4 OFF TRXC on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port B SW9 1 ON CTS on Front Panel Connector for RS 232 or CTS on Front Panel Connector for RS 422 ON ON Available OFF Not Available Serial Port B 1 2 SW9 2 ON RTS on Front Panel Connector for RS 232 or 3 RTS on Front Panel Connector for RS 422 4 ON Available OFF Not Available Serial Port B SW9 3 ON RTS on Front Panel Connector for RS 232 or RTS on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port A SW9 4 OFF TRXC on Front Panel Connector for RS 422 ON Available OFF Not Available Serial Port A FORCE COMPUTERS Page 15 Installation SPARC CPU 5TE Table 5 Default Switch Settings cont Diagram of Switch Switches Default Function Setting SWITCH 10 SW10 1 OFF VMEbus Slot 1 Device ON Slot 1 Device gt OFF Not Slot 1 Device OR Automatic Slot 1 1 on Dev
155. number ni which specifies the proper network interface may be one or two Each value specifies one of the two available network interfaces The value one specifies the first network interface and the value two specifies the second network interface In the case that the value of ni is neither one nor two the command assumes that the first network interface is specified ni stat ni true false determines the state of the twisted pair network interface specified by the network number ni The network number ni may be one or two and specifies one of the two available network interfaces Each value specifies one of the two available network interfaces The value one specifies the first network interface and the value two specifies the second network interface In the case that the value of ni is neither one nor two the command assumes that the first network interface is specified When the network link is up the value true is returned otherwise the value false is returned to indicate that the network link is down select macio macio selects the NCR89105 MACIO device that will be accessi ble at the predefined addresses within the SBus slot 5 The MACIO s device number macio may be one or two Each value specifies one of the two available MACIO devices When the value one is passed to the command the first MACIO device MACIO 1 is selected and if the value two is passed to the command the second MACIO device MACIO
156. o 0 Page 90 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 7 3 2 VMEbus Default Slave Mode The Default Slave Mode allows access to a 1 Mbyte page within a 16 Mbyte area of the SPARC CPU STE on board memory This 1 Mbyte window is always mapped to the upper virtual address space resulting ina DVMA address space of FFFO 0000 FFFF FFFF The 1 Mbyte window within the 16 Mbyte area is selected in the slave map register of the S4 VME chip Please refer to Register Accesses to the S4 VME Chip on page 95 and to the data sheet of the S4 VME chip for a detailed description of the S4 VME registers 3 7 3 3 VMEbus Slave Enhanced Mode In the Enhanced Slave Mode the DVMA window is not restricted to the 1 Mbyte size and to the 16 Mbyte area There are eight different windows supported which are from 1 Mbyte to 64 Mbyte The window size can be programmed in the vme_ctl register The Enhanced Slave Mode is only available with A32 address mode Physical Register R Address NAHE Read Write Access 7138 0003 vme_ctl r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO reserved SMODE SUPV SAMODE reserved WIN2 WINI WINO The table on the next page shows the setting for WIN 2 0 FORCE COMPUTERS Page 91 Hardware Description SPARC CPU S5TE Technical Reference Manual Table 49 Window Size Bits
157. ol the VMEbus interface The current state of these configuration parameters is displayed using the printenv command and is modified using either the setenv or the set default command provided by OpenBoot vme sysfail clear when the value of the configuration parameter is true the SYS FAIL signal will be cleared by OpenBoot In the case that the configuration parame ter is false OpenBoot will not clear the SYSFAIL signal The operating system which is loaded has to clear it default t rue vme init controls whether the VMEbus interface is initialised by OpenBoot When this flag is t rue the VMEbus interface is initialised according to the state of the NVRAM parameter listed below In the case that the flag is false the VMEbus interface is not initialised The VMEbus interface is initialised after OpenBoot set up the main mem ory default t rue level 15 intr ena controls whether the capabilities to generate a non maskable inter rupt by the watchdog timer by pressing the abort switch and by the assertion of the VMEbus signals SYSFAIL and ACFAIL are enabled or disabled In the case that the configuration parameter is t rue OpenBoot will enable the capability to generate a non maskable interrupt by the sources mentioned above This is done after the on Page 158 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements board memory has been probed and before the SBus is being probed for addition
158. on P2 on page 23 FIGURE 10 The IOBP 10 P4 ABC LE 1 2 AUDIO SERIAL FLOPPY she al 8 15 ETHERNET CENTRONICS 32 SCSI ae The pinouts of the connectors P1 P6 are shown in the following tables CAUTION This IOBP 10 back panel and the IOBP DS are especially designed for the SPARC CPU STE Do not use any other I O back panels on the SPARC CPU STE for example the IOBP 1 FORCE COMPUTERS Page 43 Installation Table 16 IOBP 10 P1 Pinout SPARC CPU 5TE ROW A Signal ROW B Signal ROW C Signal 1 SCSI Data 0 1 N C 1 FPY DENSEL 2 SCSI Data 1 2 GND 2 FPY DENSENS 3 SCSI Data 2 3 N C 3 N C 4 SCSI Data 3 4 N C 4 FPY INDEX 5 SCSI Data 4 5 N C 5 FPY DRVSEL 6 SCSI Data 5 6 N C 6 N C 7 SCSI Data 6 7 N C 7 N C 8 SCSI Data 7 8 N C 8 FPY MOTEN 9 SCSI DP 9 N C 9 FPY DIR 10 GND 10 N C 10 FPY STEP 11 GND 11 N C 11 FPY WRDATA 12 GND 12 GND 12 FPY WRGATE 13 TERMPWR 13 N C 13 FPY TRACKO 14 GND 14 N C 14 FPY WRPROT 15 GND 15 N C 15 FPY RDDATA 16 SCSI ATN 16 N C 16 FPY HEADSEL 17 GND 17 N C 17 FPY DISKCHG 18 SCSI BSY 18 N C 18 FPY EJECT 19 SCSI ACK 19 N C 19 12VDC 20 SCSI RST 20 N C 20 GND 21 SCSI MSG 21 N C 21 GND 22 SCSI SEL 22 GND 22 ETH REC 23 SCSI CD 23 N C 23 ETH REC 24 SCSI REQ 24 N C 24 ETH TRA 25 SCSIIO 25 N C 25 ETH TRA 26 RESERVED 26 N C 26 E
159. ont Panel SPARC CPU STE RESET ABORT H L Q OOK Wt gt rnw ola NO dem p mun est T 4 5 N EJE Page 102 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description 3 8 1 RESET and ABORT Keys The front panel on the SPARC CPU S5TE has two mechanical switches which directly influence the system Please see the Diagram of the CPU 5TE Top View on page 12 for the position of the switches 3 8 1 1 The RESET Key The RESET key enables the user to reset the whole board If the board is VMEbus system controller slot 1 device the SYSRESET signal of the VMEbus also becomes active with the RESET key This resets the complete VMEbus system With on board switch SW6 1 it is possible to deactivate the RESET key When SW6 1 is ON the RESET key works and when SW6 1 is OFF toggling the RESET key has no effect 3 8 1 2 The ABORT Key The ABORT key on the front panel can be used to generate a non maskable interrupt level 15 The ABORT key function is controlled by switch SW6 2 When SW6 2 is ON the key works and when SW6 2 is OFF toggling the ABORT key has no effect If the ABORT key produces a non maskable interrupt the pending signal can be read in the gen_purposel register The tables on the next page show the relevant bits in the gen_purpose register FORCE COMPUTERS Page 103 Hardw
160. oppy Disk Interface is availa bel on VME P2 r Page 128 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description COLOUR 1 0 these two bits are used to turn the User LED on or off and to control the col our of the LED The table below lists all possible values Setting Function COLOUR 1 0 00 User LED is turned off COLOUR 1 0 01 User LED is turned on and shines green COLOUR 1 0 10 User LED is turned on and shines red COLOUR 1 0 11 User LED is turned on and shines yellow 3 10 14 VMEbus Transaction Timeout Control Register With the VMEbus Transaction Timeout Control register you can set the time after which the VMEbus error occurs Physical d Nalcors Register Name Read Write Access 713C 0003 VMEbus Transaction r w 8 bit Timeout Control Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 TIMEOUT 1 0 1 1 1 1 1 1 In the case where a VMEbus cycle lasts longer than the allowed time shown in the table below a BERR is driven from the CPU 5TE board However this occurs only when the board is NOT a slot 1 device In the case where the CPU STE is a slot 1 device the bus error occurs after 2 4 us Setting Function Timeout 1 0 00 VMEbus Error after 1 5 ms Timeout 1 0 01 VMEbus Error after 200 us Timeout 1 0 10 VMEbus Error after 52 us Timeout 1 0 11 VMEBus Error after 13 us F
161. ortant to understand that the availability of both the floppy and SCSI 2 devices at the same time is dependent upon the availability of a 5 row P2 connector When using a 3 row P2 connector you have the choice of either the floppy or the SCSI 2 on P2 Via a 24 pin configuration switch matrix it is possible for either the floppy interface or the SCSI 2 to be available on the VME P2 connector on row C The default setting enables the floppy interface via the VME P2 connector with the configuration switch matrix plugged into B2 B3 and B10 B9 This means of course that by default the SCSI 2 is not available via the VMEbus P2 connector on row C To enable the SCSI 2 via the VME P2 connector plug the configuration switch matrix in sockets B3 B1 and B9 B8 The figure on the next page describes how to configure the board for floppy or SCSI 2 FORCE COMPUTERS Page 73 Hardware Description SPARC CPU S5TE Technical Reference Manual FIGURE 14 Floppy or SCSI 2 Availability on P2 B2 B3 B1 This 3 piece configuration switch matrix is used for choosing either the floppy interface or SCSI 2 a Plug the interface into sockets B2 B3 and B10 B9 for the floppy interface Or Plug the interface into sockets B3 B1 and B9 B8 for the SCSI interface iii hon en a B9 B8 Page 74 FORCE COMPUTERS SPARC CPU STE Technical Reference Manual Hardware Description 3 6 8 8 Bit Local I O Devices New Addresses The fol
162. ow are used to read data from and to store data in specific system configuration registers abort ctrl byte stores the 8 bit data byte in the ABORT Control Register flash wdt csr byte returns the contents an 8 bit data of the FLASH Mem ory and Watchdog Timer Control and Status Register flash wdt csr byte stores the 8 bit data byte in the FLASH Memory and Watch dog Timer Control and Status Register led display byte stores the 8 bit data byte in the Seven Segment Display Control Register gprl byte returns the contents an 8 bit data of the General Purpose Register 1 gpr1 byte stores the 8 bit data byte in the General Purpose Register 1 gpr2 byte returns the contents an 8 bit data of the General Purpose Register 2 gpr2 byte stores the 8 bit data byte in the General Purpose Register 2 Page 144 FORCE COMPUTERS SPARC CPU STE Technical Reference Manual OpenBoot Enhancements nil csr byte returns the contents an 8 bit data of the Network Interface 1 Control and Status Register nil csr byte stores the 8 bit data byte in the Network Interfacel Control and Status Register ni2 csr byte returns the contents an 8 bit data of the Network Interface 2 Control and Status Register ni2 csr byte stores the 8 bit data byte in the Network Interface 2 Control and Status Register led fla
163. ows device specifier The name full path or alias of the boot device Typical values are cdrom disk floppy net or tape filename The name of the program to be booted filename is relative to the root of the selected device If no filename is specified the boot command uses the value of boot file NVRAM parameter The NVRAM parameters used for booting are described in the following chapter a a prompt interactively for the device and name of the boot file h h halt after loading the program NOTE These options are specific to the operating system and may differ from system to system To explicitly boot from the internal disk type ok boot disk or at the Restricted Monitor prompt gt b disk Page 26 FORCE COMPUTERS SPARC CPU 5TE Installation To retrieve a list of all device alias definitions type devalias at the Forth Monitor command prompt The following table lists some typical device aliases Table 7 Device Alias Definitions Alias Boot Path Description disk iommu sbus espdma esp sd 3 0 Default disk 1st internal SCSI ID 3 disk3 iommu sbus espdma esp sd 3 0 First internal disk SCSI ID 3 disk2 iommu sbus espdma esp sd 2 0 Additional internal disk SCSI ID 2 disk1 iommu sbus espdma esp sd 1 0 External disk SCSI ID 1 diskO iommu sbus espdma esp sd 0 0 External disk SCSI ID 0 tape iommu sbus espdma esp st 4 0 First
164. pace with a processor virtual address vaddr FORCE COMPUTERS Page 157 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual map out vaddr size destroys the mapping set by map in at the given virtual address vaddr of length size dma alloc size vaddr allocates a virtual address range of length size bytes that is suit able for direct memory access by a bus master device The memory is allocated according to the most stringent alignment requirements for the bus The address of the acquired virtual memory vaddr is returned via the stack dma free vaddr size releases a given virtual memory identified by its address vaddr and size previously acquired by dma alloc dma map in vaddr size cachable devaddr converts a given virtual address range specified by vaddr and size into an address devaddr suitable for direct memory access on the bus The virtual memory must be allocated already by dma alloc The SPARC CPU STE does not support caching Thus the cachable flag is ignored dma map out vaddr devaddr size removes the direct memory access mapping previ ously created by dma map in dma sync vaddr devaddr size synchronizes memory caches associated with a given direct memory access mapping specified by its virtual address vaddr the devaddr and specified by its size that has been established by dma map in The NVRAM configuration parameters listed below are available to contr
165. power up which facilitates a simple startup Please see the chapter Boot the System on page 25 for more detailed information on booting the system 2 4 1 VME Slot 1 Device Special Considerations The SPARC CPU STE can be plugged into any VMEbus slot however the default configuration automatically detects that the board is a VME slot 1 device which functions as VME system controller To configure your CPU STE so it is not a VME slot 1 device the default configuration must be changed so that SW10 2 is OFF An additional consideration concerning the VMEbus slot 1 selection is shown in the following table It is important to see that Switch 10 1 and Switch 10 2 function together Table 6 VME Slot 1 Device Switch Setting SW10 1 SW10 2 Function Default On Don t Care Slot 1 Device either On or Off Off On Automatic Slot 1 Device Detection See Note below Off Off Not Slot 1 Device NOTE When the automatic slot 1 device detection method is used to enable VMEbus slot 1 device functionality the VME SYSCLOCK is not driven during RESET Normally this presents no problem However in the case that a VMEbus participant needs this SYSCLOCK signal you must use only the slot 1 device method and not the automatic slot 1 device detection method to enable the VMEbus slot 1 device functionality By setting SW10 1 to On the slot 1 device method and not automatic slot 1 detection is selected CAUTION
166. pt handler has to reset the pending non maskable interrupt This can be done with a write access to the vme_slavebase2 register To reset the SYSNMIP bit write any data to that register In addition the Power Fail Detect bit in the Aux 2 Register of the NCR89C105 must be set to clear the interrupt Please refer to the NCR SBus I O Chipset Data Manual for the Aux 2 Register In order to drive the VMEbus SYSFAIL bit SYSVME in the gen_purpose register has to be manipulated Page 96 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual Hardware Description Table 52 SYSFAIL to VMEbus Bit Setting Function SYSVME 0 Active SYSFAIL to VMEbus SYSVME 1 No SYSFAIL to VMEbus Initialization At reset SYSVME is cleared to 0 The actual status of the VMEbus SYSFAIL signal can be read in the gen_purpose register in bit SYSSTAT Table 53 SYSFAIL Status Bit Function Setting SYSSTAT 0 SYSSTAT 1 SYSFAIL active on VMEbus SYSFAIL inactive on VMEbus NOTE SYSSTAT is a read only bit The pending non maskable interrupt generated by the VMEbus ACFAIL is readable in the gen_purpose2 register This bit is called ACNMIP ACFAIL Non Maskable Interrupt Pen ding Physical Register Addres Name Read Write Access 7138 0007 gen_purpose2 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 WNMIR ACSTA
167. r automatically The Ethernet frame is not send across the network The BusNet driver uses the contents of the NVRAM configuration parameters bn master ip addr bn p ip addr bn master en addr and bn p en addr to build up the appropriate response In the case that the flag is false it sends all Ethernet frames without any further ver ification across the network default false bn master ip addr specifies the Internet Protocol IP Address of the master The default value of this 32 bit configuration parameter is zero 0 The setenv com mand is used to set this configuration parameter as shown below ok setenv bn master ip addr 0x83030001 In the example the Internet address 131 3 0 1 83030001 is assigned to the NVRAM configuration parameter This configuration parameter must be set when one of the two configuration parame ters bn arp or bn rarp are set to true Page 188 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements bn p ip addr specifies the Internet Protocol IP Address of the participant The default value of this 32 bit configuration parameter is zero 0 The set env command is used to set this configuration parameter as shown below ok setenv bn p ip addr 0x83030002 In the example the Internet address 131 3 0 2 83030002 is assigned to the NVRAM configuration parameter This configuration parameter must be set when one of the two configuration parame ters bn arp or
168. re Watchdog Timer sosisini pepes bes peee peesopeceeseeseeaueteesth svete ot skee i NSn 108 3 9 2 Rotary S WitChs cshciscsssscsshisusssessthons spschiss iesvah itis ees EA AEE EEEE EEE TEE EEE AES 111 3 10 Additional Registers a ici8 6 anneer ori e teeta KEE Ades adie aS e aaee ens 113 3 10 1 Map of Additional Registers eee eee csesecseesseceecesecneceseeseceseeeceseeeeeeaseneseneeeeseae 113 3 10 2 ve cslavebase Register s csccisceseessteseecoveecussecotcuentvesaacensevssssuecsesssesdsvscceoesarinseovanseeds 114 3 10 3 vmexslavebase REGISter sce ciivccsctcohtieceeesesctverivanevbas cued eossvarnd tdivereemnstinoetanecetaseonteaes 114 3 10 4 How to Program the VMEbus Slave Base Address 00 0 0 cece ceeeeceeeeeeeeeeeeseeeeeeeene 115 3 10 3D vine sslave DaSES RESISTEL ene ae an E E A E deed tevenncenre 116 FORCE COMPUTERS Page iii Table of Contents CPU 5TE Technical Reference Manual 310 6 lt vime ctl RE SISTER nean E E EEE E REEERE EEE EEREN 117 3 10 7 vie a3d2map Register s sccssc sssscesigsstassssactaves sogiecsesdsesesdecheshonssdsusepsodeisdvebasbassnavapetantvess 119 340 8 gen purpose l REGISTER aneren A r la ag denna hago lec E EE 121 3 10 9 Jed display Register sss csissssscsssseussssabiisentavag divin cosekssh dacs S E TRETE E R ES 123 3 10 10 gen_purpose2 Register vnissperierioceer ieies ei ir nenese orero eiserne etis ossee KEren ienie aes 124 3 10 11 Network Interface 1 Control and Status Register eee ce cess ce
169. re is a software controlled bit to select one of these modes This bit is called SMODE Slave MODE Slave Interface in the vme_ctl register SPARC CPU S5TE Technical Reference Manual Initialization At reset the SMODE bit is cleared to 0 The VMEbus slave interface only works if it is enabled via the DVMA_ENA DVMA ENAbIle bit in the gen_purpose2 register The gen_purpose2 register is shown on the next page Page 88 FORCE COMPUTERS Physical Register Addres Name Read Write Access 7138 0003 vme_ctl r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 reserved SMODE SUPV SAMODE reserved WIN2 WINI1 WINO Table 46 Slave Mode Bit Setting Function SMODE 0 VMEbus Enhanced Slave Mode SMODE 1 VMEbus Default Slave Mode SPARC CPU 5TE Technical Reference Manual Hardware Description Initialization At reset the DVMA_ENA bit is cleared to 0 Physical Register Address Name Read Write Access 7138 0007 gen_purpose2 r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 WNMIR ACSTAT ACNMIR ACNMIP DVMA_ IRQI5_ US_DEV BT_US ENA ENA Table 47 DVMA Enable Bit Setting Function DVMA_ENA 0 VMEbus Slave Mode disabled DVMA_ENA 1 VMEbus Slave Mode enabled NOTE This bit is not identical with the DVMA bit in the
170. rmation passed to the command and always returns zero to indicate that the device does not support this function block size bytes returns the size in bytes bytes of a block which is always the size of the flash memory programming window max transfer bytes returns the size in bytes bytes of the largest single transfer the device can perform The command returns a multiple of block size load addr length reads a stand alone program from the flash memory beginning at off set 0 6 and stores it beginning at address addr It returns the number of bytes length read from the flash memory This method considers the state of the NVRAM configuration parameter boot flash load base when this parameter is set to 1 which is the parameter s default value then the image loaded from the flash memory is stored beginning at the address addr But when the value of the configuration parameter differs from 1 then the image loaded from the flash memory is stored beginning at the address speci fied by the configuration parameter bootflash load base And the same address is stored in the variable load base maintained by OpenBoot 5 4 3 Loading and Executing Programs from USER Flash Memory Besides the ability to load and execute an executable image from disk or via network or other components the OpenBoot for the SPARC CPU STE provides a convenient way to load and execute an executable image from the available USER flash me
171. s To get help for special forth words or subcategories just type help name An example is shown on the next page FORCE COMPUTERS Page 33 Installation SPARC CPU 5TE An example of how to get help for special forth words or subcategories ok help tools Category Tools memory numbers new commands loops Sub categories are Memory access Arithmetic Radix number base conversions Numeric output Defining new commands Repeated loops ok ok help memory Category Memory access dump addr length display memory at addr for length bytes fill addr length byte fill memory starting at addr with byte move src dest length copy length bytes from src to dest address map vaddr show memory map information for the virtual address 1 addr display the 32 bit number from location addr w addr display the 16 bit number from location addr c addr display the 8 bit number from location addr 1 addr n place on the stack the 32 bit data at location addr w addr n place on the stack the 16 bit data at location addr c addr n place on the stack the 8 bit data at location addr 1 n addr store the 32 bit value n at location addr w n addr store the 16 bit value n at location addr c n addr store the 8 bit value n at location addr ok The on line help shows you the forth word the parameter stack before and after execution of the forth word before
172. s 32 bits integer max frame size indicates the maximum allowable size of a packet in bytes This property is created dynamically when the BusNet device is opened and depends on the property bn packet size The property s size is 32 bits integer bn master offset specifies the physical address of the participant designated as master The property s size is 32 bits integer bn master space specifies the space in which the master s BusNet region is accessible The property s size is 32 bits integer bn master access specifies the access mode of the master s BusNet region The property s size is 32 bits integer bn p offset specifies the physical address of the participant s own BusNet region The property s size is 32 bits integer bn p space specifies the space in which the participant s own BusNet region is accessible The property s size is 32 bits integer bn p access specifies the access mode of the participant s own BusNet region The property s size is 32 bits integer bn logical addr specifies the logical address assigned to the participant The property s size is 32 bits integer bn p mbox offset specifies the physical address of the participant s mailbox The property s size is 32 bits integer bn p mbox space specifies the space in which the mailbox of the participant is accessible The property s size is 32 bits integer Page 184 FORCE COMPUTERS SPARC CPU S
173. s 64 bit wide with 2 bit parity The SPARC CPU STE utilizes the Sun S4 VME chip to provide a complete 32 bit VMEbus interface Using SBus modules the board becomes a VMEbus two slot solution The SCSI 1 the Ethernet 1 and the parallal port are realized via the NCR89C100 MACIO 1 The SCSI 2 and the Ethernet 2 are realized via the NCR89C100 MACIO 2 The floppy disk interface two serial I O ports the keyboard mouse interface are provided by the NCR89C105 chip SLAVIO which additionally controls the boot EPROM the RTC and NVRAM and a user EPROM via its 8 bit expansion port FORCE COMPUTERS Page 3 Introduction SPARC CPU S5TE Technical Reference Manual 1 5 Specifications Below is a table outlining the specifications of the SPARC CPU STE board Table 1 Specifications of the SPARC CPU 5TE Processor microSPARC IT Clock Frequency 85 MHz SPECint92 64 0 SPECfp92 54 6 MIPS 112 5 MFLOPS 14 9 Memory Management Unit SPARC Reference MMU Data Instruction Cache 8 Kbyte 16 Kbyte Shared Main Memory 8 or 64 Mbyte DRAM Upgradable to 128 Mbyte SBus Slots 2 mechanically compatible to CPU 2CE CPU 3CE and CPU 5CE SCSI 1 with DMA to SBus NCR89C100 MACIO 1 10 Mbytes sec 53C90A superset T O on front panel and P2 Ethernet 1 with DMA to SBus NCR89C100 MACIO 1 10 Mbits sec AM7990 compatible T O on front panel as Twisted Pair and on P2 as AUI Parallel port with DMA to SBus NCR89C100 MACIO 1 3 4 Mbytes s
174. s Mailbox Interrupt Level Register Page 142 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements s4 mbox ctrl byte returns the contents an 8 bit data of the S4 s Mail Box Register s4 mbox ctrl1 byte stores the 8 bit data byte in the S4 s Mail Box Register s4 intr ena byte returns the contents an 8 bit data of the S4 s Interrupt Ena ble Register s4 intr ena byte stores the 8 bit data byte in the S4 s Interrupt Enable Register s4 a32map byte returns the contents an 8 bit data of the S4 s A32 Map Reg ister s4 a32map byte stores the 8 bit data byte in the S4 s A32 Map Register s4 slavemap byte returns the contents an 8 bit data of the S4 s Slave Map Register s4 slavemap byte stores the 8 bit data byte in the S4 s Slave Map Register s4 iack cycle level vector Only the least significant three bits of level are considered and when level is zero then the command treats it as if the value one has been passed to the command vme slavebasel byte returns the contents an 8 bit data of the VMEbus interface s VMEbus Slave Base Register 1 vme slavebasel byte stores the 8 bit data byte in the VMEbus interface s VMEbus Slave Base Register 1 vme slavebase2 byte returns the contents an 8 bit data of the VMEbus in
175. s all possible values Setting Function COLOUR 1 0 00 USER LED is turned off COLOUR 1 0 01 USER LED is turned on and shines green COLOUR 1 0 10 USER LED is turned on and shines red COLOUR 1 0 11 USER LED is turned on and shines yellow Page 106 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual 3 8 3 Diagnostic LED Hex Display Hardware Description A freely programmable LED display on the front panel provides diagnostic features It can be accessed via the ed_display register Physical Register Address Nanie Read Write Access 7138 0006 led_display W 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 DP SEG_G SEG_F SEG_E SEG_D SEG_C SEG_B SEG_A The following figure shows the hex display with the segments named in accordance to their bits in the ed_display register To switch a specific segment on the corresponding bit must be set to one FIGURE 16 Segments of the Hex Display FORCE COMPUTERS Page 107 Hardware Description 3 9 3 9 1 Additional Features SPARC CPU S5TE Technical Reference Manual Hardware Watchdog Timer In addition to the two programmable 22 bit counters timers in the NCR89C105 SLAVIO there is a hardware watchdog timer for system control functions It is used to inhibit system deadlock In such system deadlock cases the timer if enabled will first generate a non mask
176. s other functions Physical Register Address Nanie Read Write Access 7138 0004 vme_a32map r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 FL_PAG VPPCTL WTENA WNMIP VME_ A 31 28 Initialization All bits are cleared to Os at reset Description VME_A 31 28 are the four upper VMEbus address lines at a VME master access WMMIP reflects the watchdog non maskable interrupt pending signal which is active if the hardware watchdog timer reaches its first timeout WNMIP directly generates a non maskable interrupt level 15 interrupt if the IRQI5_ENA bit in the gen_purpose2 register is set to enable WNMIP is a read only bit Setting Function WNMIP 0 No Watchdog NMI pending WNMIP 1 Watchdog NMI pending FORCE COMPUTERS Page 119 Hardware Description SPARC CPU S5TE Technical Reference Manual WTENA enables the hardware watchdog timer This bit is also used to retrigger the watchdog timer so that it can not reach the timeout NOTE When the watchdog timer is enabled once it can t be disabled anymore Setting Function WTENA 0 Watchdog disabled WTENA 1 Watchdog enabled to retrigger write a one VPPCTL controls the 12V programming voltage for all flash memory devices that is for the Boot EPROM area and the User EPROM area Function No flash EPROM programming possi ble Setting V
177. sets the number of the 256 Mbyte page page which will be addressed when the VMEbus is being accessed within the extended address space A32 Before the command selects the new page it reads the actual contents of the VMEbus interface s VMEbus A32 Map Register in order to keep the state of the other bits in this register But the WTENA bit 5 and WNMIP bit 4 bits are cleared to prevent the watchdog timer from being started unintentionally The following commands require that the NVRAM configuration parameter use new vme is set to false set vme master size addr initialises the VMEbus interface to access an address range specified by the size and the address addr of the VMEbus The example below shows how to prepare the VMEbus interface to access the VME bus in the extended address range A32 beginning at address 40800000 6 and ranging to address 408FFFFF j ok 1Meg h 4080 0000 set vme master ok The next example shows how to prepare the VMEbus interface to access the VMEbus in the standard address range A24 beginning at address 900000 6 and ranging to address 91FFFF ok h 2 0000 h 90 0000 set vme master ok To prepare the VMEbus interface to access the address range 800046 through 8FFF j within the short address range A16 of the VMEbus the command listed below has to be used Page 152 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements ok h 1000 h f
178. sh csr byte returns the contents an 8 bit data of the USER LED and USER Flash Memory Control and Status Register led flash csr byte stores the 8 bit data byte in the USER LED and USER Flash Memory Control and Status Register xchg macio ctr1 byte returns the contents an 8 bit data of the Exchange MACIO Control Register xchg macio ctr1 byte stores the 8 bit data byte in the Exchange MACIO Control Register flash prg ctrl1 byte returns the contents an 8 bit data of the USER Flash Memory Programming Control Register flash prg ctrl1 byte stores the 8 bit data byte in the USER Flash Memory Pro gramming Control Register hw id byte returns the contents an 8 bit data of the Hardware Identification Register lca id byte returns the contents an 8 bit data of the LCA Identification Regis ter FORCE COMPUTERS Page 145 OpenBoot Enhancements SPARC CPU 5TE Technical Reference Manual 5 2 4 VMEbus Interrupt Handler vme intr byte returns the contents an 8 bit data of the S4 s Interrupt Monitor Register vme intena byte returns the contents an 8 bit data of the S4 s Interrupt Ena ble Register vme intena byte stores the 8 bit data byte in the S4 s Interrupt Enable Register vme intr pending level true false checks whether an interrupt is pending on a given
179. slave map register of the S4 VME chip The function is the same however the DVMA bit of the S4 VME chip enables the slave mode after reset The DVMA_ENA bit in the gen_purpose2 register overwrites the DVMA S4 VME bit This means that when DVMA_ENA 0 the slave mode is always disabled independent of the S4 VME bit Addressing is recognized for 32 bit extended accesses with 16 bit accesses reserved for the mailbox interrupt Unaligned slave accesses and block mode transfers are not supported FORCE COMPUTERS Page 89 Hardware Description 3 7 3 1 The CPU 5TE VMEbus slave interface can handle A32 A24 and A16 mode The A16 address space is only acknowledged for the mailbox interrupt functions which are described in VMEbus Interrupt Handler and MailBox Interrupt Function on page 93 To distinguish A32 and A24 addressing mode a software controlled bit called SAMODE Slave Address MODE is provided in the vme_ctl register SPARC CPU S5TE Technical Reference Manual VMEbus Slave Address Modes Physical Register Adiresi Name Read Write Access 7138 0003 vme_ctl r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO reserved SMODE SUPV SAMODE reserved WIN2 WINI WINO Table 48 Slave Address Mode Bit Setting Function SAMODE 0 VME Extended A32 Mode SAMODE 1 VME Standard A24 Mode Initialization At reset the SAMODE bit is cleared t
180. specified device s selftest method device specifier may be a device path name or a device alias For example test net test network connection test memory test number of megabytes specified in the selftest megs NVRAM parameter or test all of memory if diag switch is true test all device specifier Test all devices that have a built in selftest method below the specified device tree node If device path is omitted the root node is used watch clock Monitor the clock function watch net Monitor network connection To check the on board SCSI bus for connected devices type ok probe scsi Target 3 Unit 0 Disk MICROP 1684 07MB1036511AS0C1684 ok FORCE COMPUTERS Page 29 Installation SPARC CPU 5TE To test all the SCSI buses installed in the system type ok probe scsi all Aiommu 0 10000000 sbus 0 1000 1000 esp 2 100000 Target 6 Unit 0 Disk Removable Read Only Device SONY CD ROM CDU 8012 3 1la Aiommu 0 10000000 sbus 0 10001000 espdma 4 8400000 esp 4 8800000 Target 3 Unit 0 Disk MICROP 1684 07MB 103651 1AS0C1684 ok The actual response depends on the devices on the SCSI buses To test a single installed device type ok test device specifier This executes the device method name selftest of the specified device node device specifier may be a device path name or a device alias as described in Table 7 Device Alias Definitions o
181. ta from the participant zero and stores the data beginning at address 400046 in the receiver s on board memory NOTE To ensure proper operation of the data exchange the size applied to the commands on the receiver and transmitter must be the same Page 192 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 8 6 Using bn dload to Load from the Backplane The command bn dload loads a file across the network and stores it at a specific address as shown in the example below ok 4000 bn dload filename The filename must be relative to the server s root and the contents of the file are stored beginning at address 4000 within the on board memory The command bn d1load uses the Trivial File Transfer Protocol TFTP to load the file FORTH Programs FORTH programs to be loaded with bn dload must be ASCII files beginning with the two characters backslash immediately followed by a space To execute the loaded FORTH program the eval command has to be used as follows ok 4000 file size eval The variable file size contains the size of the loaded file FCode Programs FCode programs to be loaded with bn dload must be in the a out format To execute the loaded FORTH program the byt e Load command has to be used as follows ok 4000 1 byte load The command byte load is used by OpenBoot to interpret FCode programs on expansion boards such as SBus cards The second argument passed to this command
182. tch SW13 2 When SW13 2 is OFF the devices are write protected and this is the default setting The Boot EPROM devices are installed in sockets at location J124 and J125 This permits programming them in a standard programmer This may be necessary if the power fails during reprogramming In this case the contents of the Boot EPROM would be lost and the board would not be able to boot Table 36 Boot EPROM Capacity Devices Count Capacity Default 256K 8 2 512 Kbyte X 512 K 8 2 1 Mbyte The on board programming of the Boot EPROM devices requires setting some bits in the vme_a32map register and gen_purpose2 register Page 76 FORCE COMPUTERS SPARC CPU STE Technical Reference Manual Hardware Description 3 6 10 User Flash EPROM The User Flash EPROM area consists of a maximum of eight 8 Mbit flash memory devices providing a capacity of 8 Mbytes The capacity of User Flash EPROMS is outlined in the product nomenclature which can be seen in the table Product Nomenclature on page 6 This area can be used to store ROMable operating systems as well as application specific code Table 37 User Flash EPROM Capacity Devices Count Capacity IM 8 0 0 Mbyte IM 8 1 1 Mbyte IM 8 2 2 Mbytes IM 8 3 3 Mbytes IM 8 4 4 Mbytes IM 8 5 5 Mbytes IM 8 6 6 Mbytes IM 8 7 7 Mbytes 1M 8 8 8 Mbytes The User Flash EPROM devices can be reprogrammed on board and can also b
183. ter has been added to provide a compatibility with the existing definitions that use the VMEbus device driver methods To make the BusNet driver portable across a number of systems it was necessary to modify the methods The state of this configuration parameter controls the operation of the VMEbus device driver s methods map in map out dma map in and dma map out Because these methods are used by the commands set vme slave def set vm slave enh and free vme mem these commands are only executed properly when the configuration parameter is false NVRAM Configuration Default Value Description Parameter bn master offset 0000000046 bn master spac 3D46 privileged standard A24 address range bn master access 3246 read write D32 bn p offset 0000000016 bn p space 3Di privileged standard A24 address range bn p access 3246 read write D32 bn p mbox true mailbox available S4 Mailbox bn p mbox offset 000016 same as vme ibox addr bn p mbox spac 2D46 privileged short A16 address range bn p mbox access 1046 read D8 bn p mbox intr 5 SBus interrupt level 5 is asserted upon a mailbox FORCE COMPUTERS Page 197 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual Page 198 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual SUN OPEN BOOT DOCUMENTATION SECTION 6 SUN OPEN BOOT DOCUMENTATION 6 Insert your OPEN BOOT 2 0 PROM MANUAL SET here FORCE COMPUTERS Page 199 SUN OPEN
184. terface s VMEbus Slave Base Register 2 vme slavebase2 byte stores the 8 bit data byte in the VMEbus interface s VMEbus Slave Base Register 2 vme slavebase3 byte returns the contents an 8 bit data of the VMEbus interface s VMEbus Slave Base Register 3 vme slavebase3 byte stores the 8 bit data byte in the VMEbus interface s VMEbus Slave Base Register 3 FORCE COMPUTERS Page 143 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual vme ctrl byte returns the contents an 8 bit data of the VMEbus interface s Control Register vme ctrl byte stores the 8 bit data byte in the VMEbus interface s Control Register vme a32 map byte returns the contents an 8 bit data of the VMEbus inter face s VMEbus A32 Map Register vme a32 map byte stores the 8 bit data byte in the VMEbus interface s VMEbus A32 Map Register vme gpr1 byte returns the contents an 8 bit data of the VMEbus interface s VMEbus General Purpose Register 1 vme gprl byte stores the 8 bit data byte in the VMEbus interface s VMEbus General Purpose Register 1 vme gpr2 byte returns the contents an 8 bit data of the VMEbus interface s VMEbus General Purpose Register 2 vme gpr2 byte stores the 8 bit data byte in the VMEbus interface s VMEbus General Purpose Register 2 The commands described bel
185. the master again In particular the reset method executes the close and immediately afterwards the open method selftest error normally tests the package and returns an error number error which identifies a specific failure But the BusNet device provides this method only for com pleteness and returns the value zero when the method is called The value zero is returned to indicate that no failure has been detected load addr length reads the default stand alone program into memory starting at addr using the network booting protocol The ength parameter returned specifies the size in bytes of the image loaded FORCE COMPUTERS Page 185 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual read addr length actual receives a network packet and stores at most the first length bytes in memory beginning at address addr It returns the actual number of bytes received not the number copied or it returns zero if no packet is currently available The BusNet device driver copies only the data contained in the BusNet packet into memory and discards all information related to the BusNet protocol write addr length actual transmits the network packet of size length stored in memory beginning at address addr and returns the number of bytes actually transmitted or zero if the packet has not been transmitted due to a failure The BusNet device driver copies the data into the data field of a BusNet packet and
186. the CPU 5TE When the board accesses the VMEbus the BM LED lights up green If SYSFAIL was detected the BM LED lights up red If SYSFAII was detected and the board accesses VME the LED shines yellow An additional SYS LED is a freely programmable LED which is controlled by accessing a register in the NCR89C105 SLAVIO Bit 0 LED of the Aux 1 register controls the STATUS LED with following settings Physical Register Addes Name Read Write Access 7190 0000 Aux 1 Register r w 8 bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 R D R E M T LED Table 59 LED Bit Setting Function LED 0 SYS LED OFF LED 1 SYS LED ON Please refer to the NCR SBus I O Chipset Data Manual for a detailed description of the Aux 1 register FORCE COMPUTERS Page 105 Hardware Description The USER LED is a freely programmable LED which is controlled by accessing bit 0 and bit 1 SPARC CPU S5TE Technical Reference Manual of the USER LED and User Flash Memory register Physical Register Address Name Read Write Access 713C 0002 USER LED r w 8 bit and USER Flash Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO 1 1 1 1 FLASH IRQI5_ COLOUR 1 0 RDY ENA COLOUR 0 1 RW these two bits are used to turn the USER LED on or off and to control the colour of the LED The table below list
187. the VMEbus slave interface is accessible within the standard address range A24 of the VMEbus The base address and the size of the slave window are specified by the size and the addr The size of the slave window in the default mode is limited to one Mbyte The base address of the slave window is given as an index rather than an absolute address within the standard address range The value of addr may be one of the values in the range of zero through 15 Each value specifies one of the one Mbyte ranges in the standard address range The example below shows how to make one Mbyte available to the standard address range of the VMEbus beginning at the physical address 90000046 ok 1Meg 9 set vme slave def ok set vme slav nh size a3l a28 a27 a20 lower a27 a20 upper initialises the VMEbus interface to operate in the enhanced slave mode In this mode the VMEbus slave interface is accessible within the extended address range A32 of the VMEbus The base address and the size of the slave window are specified by the size and the FORCE COMPUTERS Page 155 OpenBoot Enhancements SPARC CPU S5TE Technical Reference Manual address specified by a31 a28 a27 a20 lower and a27 a20 upper The size of the slave window in the enhanced mode is limited to one Mbyte The base address of the slave window is specified by the following three values a3 a28 specifies the 256 Mbyte page in which the slave window is accessible a27 a20 lower and a27 a20
188. this configuration parameter identifies one of the address spaces available in the address range of the bus The default value of this 32 bit configuration parameter is D privileged standard address space 09 Page 186 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements bn p access specifies the access mode of the participant s own BusNet region The default value of this 32 bit configuration parameter is 324 D32 read write no LOCKed cycles are supported bn logical adadr specifies the logical address assigned to the participant The value of this configuration parameter may be in the range zero through 31 The default value of this 32 bit configuration parameter is zero bn p mbox offset specifies the physical address of the participant s mailbox The default value of this 32 bit configuration parameter depends on the hardware capabili ties of the specific machine lbn p mbox space specifies the space in which the participant s mailbox is accessible Typically this configuration parameter identifies one of the address spaces available in the address range of the bus The default value of this 32 bit configuration parameter depends on the hardware capabilities of the specific machine bn p mbox access specifies the access mode of the participant s mailbox The default value of this 32 bit configuration parameter depends on the hardware capabilities of the specific machine b
189. transmits the packet to the specified recipient seek poslow poshigh 1 operation is invalid and the method therefore always returns 1 to indicate the failure 5 8 3 3 NVRAM Configuration Parameters The OpenBoot provides the NVRAM configuration parameters as defined by the BusNet Protocol Specification 1 4 2 The NVRAM configuration parameters may be modified using the set default or setenv commands provided by OpenBoot The actual state of the NVRAM configuration parameters are displayed by the printenv command bn master offset specifies the physical address of the participant designated as master The default value of this 32 bit configuration parameter is zero bn master space specifies the space in which the master s BusNet region is accessible Typically this configuration parameter identifies one of the address spaces available in the address range of the bus The default value of this 32 bit configuration parameter is D privileged standard address space 09 bn master access specifies the access mode of the master s BusNet region The default value of this 32 bit configuration parameter is 324 D32 read write no LOCKed cycles are supported bn p offset specifies the physical address of the participant s own BusNet region The default value of this 32 bit configuration parameter is zero bn p space specifies the space in which the participant s own BusNet region is accessible Typically
190. ts 3 3 4 ABORT Interrupt de a adi aati aaa ities RE E 177 5 5 5 Watchdogs Timer Interrupt i s cscciscssssssiscetsbssseedssassscgedssascheuts sceschasebiedsssasveestevsbassasivens 177 5 0 Further Command S neier eset es E EEEE Sines teba lives otters E E EER 178 5 7 Second SCSI and Ethernet Interface eee ee eeeeeeeeeeceeeseecaeesaecaeceaecseceseeeesseeseseeeeeeeeeeees 179 5 7 1 Additional Commands to Control the Network Interfaces 00 0 eee eee eeeeeeeeeees 179 X2 DEVICE AT ASES 222 ccvisecvcs nen chat cnsdssheceigcdgsecepeedeutescectagecsapeeste euotbers EER 181 5 8 BusNet Support ninaa yc th e hed ed eh te eek a 182 58 1 Leimitatlons assis thes Akard hada Satins widens hate aoc EEEE E ES 182 5 8 2 Loading Programs iss sscsssec sssesstacss ss tsceieevasssstsiseestasged aoi EES SoSo seeedashessheatasvysshoees sens 182 5 8 3 The BusNet Devier innreise ne eroas E EE fear deen E EE EEE REEE 183 X831 Device Properties Aten E a E tier ee 183 9 8 3 2 Deyi ce Methods 2i e c sc cs a hich E ce deh EEE E 185 5 8 3 3 NWVRAM Configuration Parameters 0 cee eececeeeseeeeeeeeeseeseeeseeseecneenaes 186 5 84 Device Operations issiro ae aE ea E EE EER EE T Ea aE pE ethene 190 2 8 5 Howto Use BusNet i 2cnc5acearcd scasn Sevtla nheitiesas cies Ri EE E EE sees 191 5 8 6 Using bn d1load to Load from the Backplane cee eesesceseteneeseneeeeeeseeeeseers 193 5 8 7 Booting from a Solaris SunOS BusNet Server ese cseceeceeeee
191. tual addresses to the MMU which are translated to the appropriate physical addresses Before another VMEbus master may access the on board memory the following steps have to be taken to make a certain amount of on board memory available to one of the VMEbus address spaces e g standard A24 or extended A32 address space e A certain amount of the available on board memory has to be allocated to make it available to one of the VMEbus address spaces e The VMEbus interface has to be set up to respond to specific addresses within the selected VMEbus address spaces In general registers within the VMEbus interface are modi fied to accomplish this e The contents of the IOMMU table are modified to associate the virtual SBus addresses which are emitted by the VMEbus interface during a slave access with the physical addresses of the allocated memory Furthermore the contents of the MMU table are Page 138 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements modified to associate the virtual addresses which are emitted by the processor during accesses to the on board memory with the physical addresses of the allocated mem ory e The VMEbus interface has to be enabled in order to allow accesses from the VMEbus to the on board memory OpenBoot provides commands to make the on board memory available to one of the VMEbus address spaces and to remove the on board memory from these VMEbus address spaces The co
192. ue zero indicates that the arbiter operates in the priority mode which means that the arbiter is operating as a single level arbiter at level 3 The value one specifies the round robin mode Two constants are available to specify one of the two arbiter modes pri Qj9 and rro io 5 2 6 VMEbus Requester The commands described below are available to control the VMEbus requester as well as to retrieve information about the state of the VMEbus requester vme buslock byte returns the contents an 8 bit data of the S4 s Bus Locker Register vme buslock byte stores the 8 bit data byte in the S s Bus Locker Register vme bus request mode mode returns the VMEbus request mode in use when the VMEbus interface tries to gain the ownership of the VMEbus vme bus request mode mode selects the bus request mode to be used when the VMEbus is being accessed Two constants are available to specify one of the two request modes fair Oj and unfair 14 vme bus capture true false enables or disables the bus capture and hold capa Page 148 FORCE COMPUTERS SPARC CPU 5TE Technical Reference Manual OpenBoot Enhancements bility of the S4 If the value true is passed to the command the VMEbus interface starts to capture the bus and when it gains the ownership of the bus it holds owner ship as long as the bus is released The bus is released when the command is
193. upon the receipt of a VMEbus interrupt at level The parameter mapping defines the interrupt asserted by the S4 when a certain VMEbus interrupt request level is asserted The value of mapping may be one of the values in the range of one through seven Each value spec ifies one of the seven S4 interrupt request lines The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VME bus interrupt request levels Only the least significant three bits of mapping and level are considered and when level is zero then the command treats it as if the value one has been passed to the command Because the VMEbus interface on the SPARC CPU STE does not allow to map a VMEbus interrupt to any SBus interrupt level the values of mapping and level passed Page 146 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements to the command must be the same To enable the VMEbus interrupt request level 5 the parameters listed in the example below have to be passed to the command ok 5 5 vme intr ena ok vme intr dis level disables the interrupt to be generated when the specified VME bus interrupt request at level is asserted The value of level may be one of the values in the range of one through seven Each value specifies one of the seven VMEbus inter rupt request levels Only the least significant three bits of level are considered and when level is zero then
194. upper specify the boundaries of the slave window within the 256 Mbyte page The example below shows how to make one Mbyte available to the extended address range of the VMEbus beginning at the physical address 23400000 1 ok 1Meg 2 34 35 set vme slave enh ok The two commands described above modify the contents of the following two variables vme dpr vaddr returns the virtual address vaddr of the memory which has been made available to the VMEbus my vme base paddr returns the physical address paddr of the memory which is accessible from the VMEbus free vme mem releases all virtual and physical memory allocated by the commands set vme slave def and set vme slav nh and allocated by the com mands to set up the VMEbus master interface Page 156 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements 5 2 10 VMEbus Device Node The OpenBoot device tree contains the device node for the VMEbus interface and is called VME It is a Child device of the device node i ommu The full pathname of the VMEbus interface device node is displayed by the command show devs The device alias vme is available as an abbreviated representation of the VMEbus interface device path The vocabulary of the VMEbus device includes the standard commands recommended for a hierarchical device The words of this vocabulary are only available when the VMEbus device has been selected as show
195. ut Keyboard Mouse cscceeescceesseceeseeeeesteeeeneeeenes 53 Table 26 Physical Memory Map of microSPARC ssseseeeeeeeseseeesrsereeresseseresreess 57 Table 27 Bank Selection a 3ci2t sc 220 Aisa esee nd giiadliield e a asi 58 Table 28 MEMES Memory Banksin reisseri Ea Ea 59 Table 29 Physical Memory Map of SBus on SPARC CPU S5TE seese 60 Table 30 Network Interface 1 Control And Status Register eeeeeeeeeeeeteeeeeee 65 Table 31 Network Interface 2 Control And Status Register eeeeeeseeeesteeeeees 66 Table 32 NCR89C105 Chip Address Map cs s cccsssscessccassaccevatecssuteavesactusdeceesaseaveats 68 Table 33 Serial Ports A and B Pinout List RS 232 cccccsscccccccceceesesseceeeseeeeeeees 71 Table 34 Switch Settings for Ports A and B RS 232 wo eee eeeeeseeeeneecnseeeneeeeees 72 Table 35 B BiL Local O DEVICES annae a e E A R 75 Table 36 Boot EPROM C pacty enn a a n r a a 76 Table 37 User Flash EPROM Capacity cc sssccicsasccsaeasuanacisdenccacasncsadencesdactecsteaaeecandants 77 Table 38 12V Programming Voltage Control Bit eee eeeeeceseceesteceeeteeeeseeeenes 78 Table 39 Flash Memory Programming Control Bits 0 0 ceeeceeeseceeeseceeeneeeeneeeenee 80 FORCE COMPUTERS Page vii Table of Contents CPU 5TE Technical Reference Manual Table 40 Programming Control Bitsi1e tac55 asks ae nl bien eek 82 Table 41 VMEbus Master Interface Physical Address Map cesscceesseeeesteeeeeee 84 Ta
196. vmeal6d16 h 2d returns the AML constant 2D16 identifying the privileged short A16 address space with 16 bit data transfers vmeal6d32 h 6d returns the AML constant 6D16 identifying the privileged short A16 address space with 32 bit data transfers vmea24d16 h 3d returns the AML constant 3D 16 identifying the privileged standard A24 address space with 16 bit data transfers vmea24d32 h 7d returns the AML constant 7D1 6 identifying the privileged standard A24 address space with 32 bit data transfers vmea32d16 h Od returns the AML constant 0D16 identifying the privileged extended A32 address space with 16 bit data transfers vmea32d32 h 4d returns the AML constant 4D1 6 identifying the privileged extended A32 address space with 32 bit data transfers The AML modifiers described below are available to modify the AML in such a way that additional VMEbus address spaces may be identified burst phys high single phys high burst converts the numeric representation of any VMEbus AML constant in single transaction form to its burst transaction BLT form Page 134 FORCE COMPUTERS SPARC CPU S5TE Technical Reference Manual OpenBoot Enhancements ok vmea24d32 burst 3f ok vme user phys high privileged phys high non privileged converts the numeric repre sentation of any VMEbus AML constant in privileged form to its non privileged user mode form ok vme
197. x900 8 bits per pixel single SBus slot SBus TGX Color 2 D and 3 D wireframe high performance graphics accelerator up to 1152x900 1 Mbyte VRAM 8 bits per pixel single SBus slot SBus TGX Color 2 D and 3 D wire frame high performance graphics accelerator up to 1600 x 1280 4 Mbyte VRAM 8 bits per pixel double buffering single SBus slot SBus FP 6U Front panel for up to 2 SBus cards Accessories CPU 5TE TM SPARC CPU STE Technical Reference Manual set including OpenBoot User s Manual and a Set of Data Sheets IOBP DS T O back panel on VMEbus P2 with micro D sub connector for one AUI Ethernet 8 pin mini circular DIN connector for key board mouse flat cable connectors for dual SCSI and two serial I O interfaces For use with the CPU 5TE Serial 2CE Adapter cable for one serial port 26 pin microHD to 25 pin D sub For use with CPU 5TE Software Solaris 2 x CPU 5TE Solaris 2 x package with Desktop Right To Use license VME bus driver on tape Solaris 2 x OLDS CPU 5TE Solaris 2 x package with Desktop Right To Use license Online DiskSuite for Solaris 2 x VMEbus driver on tape Solaris 2 x CPU 5TE Client RTU Solaris 2 x Desktop Right To Use license Without media Solaris 2 x CPU 5TE Server RTU up Solaris 2 x Desktop to Workgroup Server Right To Use upgrade license Without media Solaris 2 x UM Solaris 2 x Operating System User s Manual Solaris 1 x CPU 5TE Solaris 1 x packa

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