ST7570 - STMicroelectronics
Contents
1. que Or heel ed qd d da T ide piss 14 5 4 Current and voltage control 15 5 5 Thermal shutdown and temperature 16 56 A Zero crossing PLL and delay compensation 16 6 Power 17 7 Clock management 18 8 Functional overview 18 8 1 gigs mm rm 19 9 Physical layer uae aacra da a xo e qo Ue EROR AR eae 20 9 1 S FSK principles 2 e ES 20 9 2 ul ahus ua 21 9 3 Frame structure at physical level 22 9 4 Frame timing and time slot synchronization 22 10 Package mechanical data 23 11 Revision history 25 2 26 Doc ID 17526 Rev 2 ky 517570 Device overview Device overview Realized using a multi power technology with state of the art VLSI CMOS lithography the ST7570 is based on dual digital core architecture a PHY processor engine and a protocol controller core to guarantee outstanding communication performance with a high level of flexibility and programmability The on chip analog front end featuring analog to digital and digital to analog conversion and auto2. i i AM02511v1 The absolute frequency deviation 1 1 is at least 10 KHz in order to reduce the probability that a narrow band interferer could corrupt both carriers at the same time fo and f can be set at any value in CENELEC bands A B D Figure 12 S FSK waveform frequency domain Ifo f gt 10kHz AM02512v1 Doc ID 17526 Rev 2 ky 517570 Physical layer 9 2 Bit timing The data communication is synchronized to the mains zero crossing through an internal PLL The bit time is dynamically adapted in order to have always 24 or 48 bits in each mains cycle according to the desired configuration Figure 13 The resulting bit rate is thus dependent on the instantaneous mains frequency With a nominal frequency of 50 Hz the resulting bit rate is 1200 bps in the case of 24 bit mains cycle while 2400 bps in the case of 48 bit mains cycle Figure 13 Bittiming Mains cycle Seg Mains waveform 50 Hz or 60 Hz Zero crossing Zero crossing 24 bit mains cycle 1200 bps at50 Hz 1440 bps at60 Hz 48 bit mains cycle 2400 bps at50 Hz 2880 bps at60 Hz AM02513v1 Doc ID 17526 Rev 2 21 26 Physical layer ST7570 9 3 9 4 22 26 Frame structure at physical level The frame at physical level is compliant with the IEC61334 5 1 and is composed of 45 bytes 360 bits as follows 2 byte preamble PRE AAAAh 2 byte start
3. 11 4 Revision history Table 10 Document revision history Date Revision Changes 27 May 2010 1 Initial release Added specifications about ErDF Linky requirements in features introduction in the coverpage and functional specifications in 24 Sep 2012 2 Chapter 8 Updated pinout in Table 2 Electrical values in Table 5 Doc ID 17526 Rev 2 25 26 ST7570 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever
4. ky ST7570 S FSK power line networking system on chip Features m Fully integrated narrow band power line networking system on chip m High performing PHY processor with embedded turn key firmware for spread frequency shift keying S FSK modulation Programmable bit rate up to 2 4 Kbps 50 Hz 1Hz step programmable carriers up to 148 5 kHz Signal to noise ratio estimation Received signal strength indication m Protocol engine embedding EC61334 5 1 PHY and MAC layers Alarm management Repeater Call procedure Intelligent search initiator process m On chip peripherals Host controller UART interface Fully integrated analog front end ADC and DAC PGA with automatic gain control for high receiving sensitivity High linearity modulated signal generation m Fully integrated single ended power amplifier for line driving Upto1 Arms 14 V output Configurable Active filtering topology Very high linearity Datasheet production data VFQFPN 7x7x1 0 48L pitch 0 50 m Suitable for EN50065 and FCC part 15 compliant applications VFQFPN48 package with exposed pad m 40 C to 85 C temperature range Applications m Smart metering applications Street lighting control Command and control networking Description The ST7570 is a powerful power line networking system on chip It combines a high performance PHY processor core and a protoco
5. 50 Hz V RX IN MIN Receiver input sensitivity BER 10 3 SNR 45 m 20 dB 10 26 Doc ID 17526 Rev 2 ky 517570 Electrical characteristics Table 5 Electrical characteristics continued Symbol Parameter Note Min Typ Max Unit PGA_MIN PGA minimum gain 18 dB PGA_MAX PGA maximum gain 30 dB Oscillator V XIN Oscillator input voltage swing Clock frequency 1 88 VDDIO V p p supplied externally V XIN TH Oscillator input voltage threshold 0 8 0 9 1 V f XIN Crystal oscillator frequency 8 MHz XIN TOL External quartz crystal frequency 150 150 ppm tolerance ESR External quartz crystal ESR value 100 Q External quartz crystal load 16 20 pF capacitance Internal frequency of the analog front 8 MHz Internal frequency of the protocol 28 MHz Ctrl core fo_k_PHY_proces Internal frequency of the PHY 56 MHz sor processor core Temperature sensor T_TH Temperature threshold 1 63 70 77 C T_TH gt Temperature threshold 2 90 100 110 C Temperature threshold 3 112 125 138 C Temperature threshold 4 153 170 187 C Zero crossing comparator V ZC_IN_A MAX Zero crossing analog input voltage 10 Vp p range V ZC_IN_A TL Zero crossing analog input low 40 30 20 mV threshold V ZC_IN_A TH Zero crossing analog input high 30 40 50 mV threshold V ZC_IN_A Zero crossing analog input HYS
6. 3 V V RX_IN RX_IN voltage range VCCA 0 3 VCC 0 3 V V ZC IN A 7 A voltage range VCCA 0 3 VCCA 0 3 V V TX_OUT CL TX_OUT CL voltage range VSSA 0 3 VCCA 0 3 V V XIN XIN voltage range GND 0 3 VDDIO 0 3 V OUT 27 output non repetitive peak 5 A peak OUT p uem output non repetitive rms 14 A tris Tamb Operating ambient temperature 40 85 C Tstg Storage temperature 50 150 C Maximum withstanding voltage range V ESD 2 CDF AEC Q100 002 Human P 42 kV Acceptance criteria Normal Performance Thermal data Table 4 Thermal characteristics Symbol Parameter Value Unit RihJA1 Maximum thermal resistance junction ambient steady state 1 50 C W RinJA2 Maximum thermal resistance junction ambient steady state 2 42 C W 1 Mounted on 2 side vias PCB with a ground dissipating area on the bottom side 2 Same conditions as in Note 1 with maximum transmission duration limited to 100 s Doc ID 17526 Rev 2 X 517570 Electrical characteristics 4 Electrical characteristics 40 to 85 C Ty lt 125 C Voc 18 V unless otherwise specified Table 5 Electrical characteristics Symbol Parameter Note Min Typ Max Unit Power supply VCC Power supply voltage 8 13 18 V RX Power supply current Rx mode VEGA externally 0 35 0 5 mA supplied VCC TX Power supply
7. Equation 1 Equation 1 Output attenuation A dB vs TX GAIN A dB TX GAIN 31 TX_GAIN ToL Power amplifier The integrated power amplifier is characterized by very high linearity required to be compliant with the different international regulations CENELEC FCC etc limiting the spurious conducted emissions on the mains and a current capability of 1 A rms that allows the amplifier driving even very low impedance points of the network All the pins of the power amplifier are accessible making it possible to build an active filter network to increase the linearity of the output signal Doc ID 17526 Rev 2 ky 517570 Analog front AFE 5 4 Current and voltage control The power amplifier output current sensing is performed by mirroring a fraction of the output current and making it flow through a resistor Rc connected between the C pin and VSS The following relationship can be established between V CL Equation 2 V CL vs OUT CL RATIO The voltage level V CL is compared with the internal threshold CL TH When the V CL exceeds the TH level the V TX OUT voltage is decreased by one TX GAIN step at a time until V CL goes below the CL TH threshold The current sense circuit is depicted in Figure 6 Figure 7 OUT current sense circuit VCC I PA_OUT f CL PA_OUT CL_RATIO AM02507v1 The Re value to
8. get the desired output current limit I PA_OUT LIM be calculated according to Equation 3 Equation 3 Rc calculation LTH ____ CL CL RATIO Note that is expressed as current so the corresponding rms current value shall be calculated according to the transmitted signal waveform The Re value to get 1 A rms output current limit calculated with typical values for and CL RATIO parameters is indicated in Table 7 Table 7 CL resistor typical values Parameter Description Value Unit Resistor value for OUT MAX 1 A rms 1 41 A peak Doc ID 17526 Rev 2 15 26 Analog front end AFE ST7570 5 5 5 6 16 26 Thermal shutdown and temperature control The ST7570 performs an automatic shutdown of the power amplifier circuitry when the internal temperature exceeds After a thermal shutdown event the temperature must get below THs before the ST7570 power amplifier comes back to operation Moreover a digital thermometer is embedded to identify the internal temperature among four zones as indicated in Table 8 Table 8 Temperature zones Temperature zone Temperature value 1 T T TH 2 T TH T T 3 T THa T T 4 T T Zero crossing PLL and delay compensation In operating mode ST7570 needs to be synchronized with an external signal period through zero crossing detection The user can
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10. select among two input pins for the external zero crossing reference e Analog input ZC IN A it requires a bipolar analog input signal which is internally squared through a Schmidt Trigger comparator with symmetrical thresholds e Digital input ZC D it requires a 50 duty cycle square wave digital signal with two levels The desired input can be selected by accessing a dedicated management information base MIB object The ST7570 embeds a phase locked loop PLL to generate the internal reference based on the external zero crossing In case of delay due to external zero crossing coupling circuits i e based on optocouplers or to improve interoperability it is possible to introduce delay compensation through a dedicated MIB object Figure 8 Zero crossing detection ZC IN D Internal Reference ZC IN A Trigger ZC IN D configuration bit MIB object AMO2508v1 Doc ID 17526 Rev 2 ky 517570 Power management 6 Power management Figure 9 shows the power supply structure for the ST7570 device The ST7570 operates from two external supply voltages e VCC 8 to 18 V for the power amplifier and the analog section VDDIO 3 3 or 5 V for interface lines and digital blocks Two internal linear regulators provide the remaining required voltages 5V analog front end supply generated from the VCC voltage and connected to the VCCA pin 1 8V digital core supply generated from the VDD
11. subframe delimiter SSD 54C7h 38 byte physical service data unit P_sdu 3 byte for pause or alarm The bytes are sent from the most significant byte MSB to the least significant byte LSB Bits within the byte are packed with the same order msb to Isb Figure 14 Physical frame format 38 bytes Preamble Start P_sdu Pause Alarm PRE Delimiter SSD PHY Frame AM02514v1 Frame timing and time slot synchronization The IEC61334 5 1 protocol specifies a master slave network with time division medium access in order to properly communicate all the nodes belonging to a network must share the same slot synchronization The time division is fixed through the use of time slots corresponding to a physical frame length of 45 bytes i e 360 bits with a total duration equal to e 15mains cycles at the 1200 bps operating speed at 50 Hz 7 5 mains cycles at the 2400 bps operating speed at 50 Hz The slot synchronization is first achieved by the master i e ST7570 modem in Client mode setting the time slot starting at the mains zero crossing instant The frames transmitted by the master will enable the slot synchronization of all other slave nodes i e ST7570 working in Server mode the reception of the sequence composed by PRE and SSD will allow all the Server nodes aligning their time slots to the Client s time slot Doc ID 17526 Rev 2 ky 517570 Package mechanical d
12. IO voltage and connected to VDD_REG_1V8 direct regulator output and VDD pins The VDD_PLL pin supplying the internal clock PLL must be externally connected to VDD All supply voltages must be properly filtered to their respective ground using external capacitors close to each supply pin in accordance to the supply scheme depicted in Figure 9 Note that the internal regulators connected to VDD_REG_1V8 and to VCCA are not designed to supply external circuitry their outputs are externally accessible for filtering purpose only Figure 9 Power supply internal scheme VCC PA AFE vss VCCA VSSA VDDIO DIGITAL INTERFACES DIGITAL CORE GND VDD_REG_1V8 GND T VDD VDD PLL INTERNAL PLL VSSA AM02509v1 Doc ID 17526 Rev 2 17 26 Clock management ST7570 7 18 26 Clock management The main clock source is an 8 MHz crystal connected to the internal oscillator through XIN XOUT pins Both XIN and XOUT pins have a 32 pF integrated capacitor in order to drive a crystal having a load capacitance of 16 pF with no additional components Alternatively an 8 MHz external clock can be directly supplied to XIN pin leaving XOUT floating A PLL internally connected to the output of the oscillator generates the required by the PHY processor block is then scaled down by two to obtain required by the protocol controller Function
13. T hysteresis 62 70 1e ZC_IN_D d c Zero crossing digital input duty 50 cycle Digital section Digital I O ID 17526 Rev 2 11 26 Electrical characteristics ST7570 Table 5 Electrical characteristics continued Symbol Parameter Note Min Typ Max Unit VDDIO 3 3 V 66 R nternal pull up resistors cad VDDIO 5 V 41 ko 0 65 V VDDIO VIH High logic level input voltage DDIO 10 3 V 0 35 V VIL Low logic level input voltage 0 3 DDIO V VOH High logic level output voltage 4 mA ox V VOL Low logic level output voltage IOL 4 mA 0 4 V UART interface 1 5 57600 1 5 x 1 5 38400 1 5 Baud rate 1 5 19200 1 5 p 1 5 9600 1 5 os Reset and power on tRESETN Minimum valid reset pulse duration 1 us Start up time at power on or after a sTARTUP reset event 89 is 1 Referred to T4 40 C 2 This parameter does not include the tolerance of external components 3 Guaranteed by design Figure 4 Power amplifier test circuit R1 R2 V V 4k 15k rvcc rvcc 7R3 PA IN 330k 2 PA_OUT gt l c1 1p SIGNAL SOURCE PA IN 10n R LOAD R4 50 330k 02504 1 12 26 ID 17526 Rev 2 ky ST7570 Analog front end AFE 5 Analog front end AFE 5 1 Reception path Figure 4 shows the
14. V PA_OUT HD2 Larmonic distortion V PA_OUT 14 V p Bor V PA_OUT HD3 Power amplifier output 3rd BIAS VCC 2 66 63 dBc harmonic distortion Ri oAp 509 T 25 See Figure 3 v PA_ouT THD Fower amplifier output total 01 015 9 harmonic distortion IN vs VSS 0 10 pF C PA IN Power amplifier input capacitance AA lt 3 PA IN vs VSS 9 10 pF 50 Hz 100 dB PSRR Power supply rejection ratio 1 kHz 93 dB 100 kHz 70 dB CL TH in sense high threshold on CL 225 2 35 24 V CL RATIO Ratio between PA OUT and CL 80 output current Transmitter V TX OUT BIAS Transmitter output bias voltage Rx VCCA V mode 2 V TX_OUT MAX Transmitter output maximum TX_GAIN 31 No 48 4 95 VCCA Vp p voltage swing load TX_GAIN Transmitter output digital gain range 0 31 TX GAIN TOL Transmitter output digital gain 0 35 0 35 dB tolerance R TX_OUT Transmitter output resistance 1 V TX_OUT HD2 Transmitter output 2nd harmonic 72 55 dBc distortion OUT 4 5 V TX_OUT HD3 ansmitter output 3rd harmonic Vpkpk typ no load 70 67 dBc distortion 25 V TX_OUT THD Transmitter output Total harmonic 04 02 distortion Receiver V RX_IN MAX Receiver input maximum voltage VCC 18 V 16 V p p V RX_IN BIAS Receiver input bias voltage sa V Z RX_IN Receiver input Impedance 10 Bit rate 1200 bps I
15. VDD 11 26 PA OUT 12 25 VSS 13 14 15 16 17 18 19 20 21 22 23 24 28 32352204 O0 9 12 2x O T gt gt 1 lt x gt N AMO2503v1 4 26 Doc ID 17526 Rev 2 ky 577570 Pin connection 2 1 Pin description Table 2 Pin description Pin Name Type Reset state Pull up Description 1 TXD Digital output HighZ Disabled 2 b napis sai 2 RXD Digital input High Z Disabled UART data in 3 VDDIO Power 3 3 V 5 V I O external supply 4 TRSTN Digital input Input Enabled System JTAG interface reset active low 5 TMS Digital input Input Enabled System JTAG interface mode select 6 GND Power Digital ground 7 TCK Digital input HighZ Disabled 54222 8 Digital output HighZ Disabled System JTAG interface data out 9 TDI Digital input Input Enabled System JTAG interface data in 10 RESETN Digital input Input Disabled System reset active low 1 8 V digital supply 11 VDD Power Internally connected to VDD_REG_1V8 Externally accessible for filtering purposes only 12 XIN Analog Crystal oscillator input external clock input Crystal oscillator output 13 XOUT Analog if external clock supplied XIN XOUT must be left floating 14 GND Power Digital ground 15 VSSA Power Analog ground w rower 17 VCCA Pow r _ _ 5 V analog supply internal regulator output Externally accessible for fil
16. al overview The ST7570 embeds complete physical PHY and a medium access control MAC protocol layers and services compliant with the open standard IEC61334 5 1 mainly developed for smart metering applications but suitable also for other command and control applications and remote load management in CENELEC B and D bands A local port UART is available for communication with an external host exporting all the functions and services required to configure and control the device and its protocol stack Below a list of the protocol layers and functions embedded in the ST7570 Figure 10 e Physical layer implemented in the PHY processor and exporting all the primitive functions listed in the international standard document IEC61334 5 1 plus additional services for configuration alarm management signal and noise amplitude estimation phase detection statistical information e MAC layer implemented on the protocol controller and exporting all the primitive functions listed in the international standard document IEC61334 5 1 Repeater Call and Intelligent search initiator process together with additional services e Management information base MIB an information database with all the data required for proper configuration of the system at both PHY and MAC layer e Hostinterface all the services of the PHY MAC and MIB are exported to an external host through the local UART port Doc ID 17526 Rev 2 ky 577570 Functional overvi
17. ata 10 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of packages depending their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark The ST7570 is hosted in a 48 pin thermally enhanced very thin fine pitch quad flat package no lead VFQFPN with exposed pad which allows the device dissipating the heat that is generated by the operation of the two linear regulators and the power amplifier A mechanical drawing of the VFQFPN48 package is included in Figure 15 Table 9 48 7 x 7 x 1 0 mm package mechanical data mm Dim Min Typ Max A 0 80 0 90 1 00 1 0 02 0 05 2 0 65 1 00 0 25 0 18 0 23 0 30 D 6 85 7 00 7 15 D2 4 95 5 10 5 25 E 6 85 7 00 7 15 E2 4 95 5 10 5 25 e 0 45 0 50 0 55 L 0 30 0 40 0 50 ddd 0 08 ky Doc ID 17526 Rev 2 23 26 Package mechanical data ST7570 Figure 15 48 7 x 7 x 1 0 mm package outline SEATING PLANE Pp add A3 A UVUUUUUUUUUU E2 nnnannannmf f BOTTOM VIEW 24 26 Doc ID 17526 Rev 2 ky 517570 Revision history
18. block diagram of the ST7570 input receiving path The main blocks are a wide input range analog programmable gain amplifier PGA and the analog to digital converter ADC Figure 5 reception path block diagram 02505 1 is controlled by embedded loop algorithm adapting the PGA gain to amplify or attenuate the input signal according to the input voltage range for the ADC The PGA gain ranges from 18 dB up to 30 dB with steps of 6 dB typ as described in Table 5 Table 6 PGA gain table PGA code PGA gain typ dB RX_IN max range V p p 0 18 16 1 12 8 2 6 4 3 0 2 4 6 1 5 12 0 500 6 18 0 250 7 24 0 125 8 30 0 0625 5 2 Transmission path Figure 5 shows the transmission path block diagram it is mainly based on a digital to analog converter DAC capable to generate a linear signal up to its full scale output A gain control block before the DAC gives the possibility to scale down the output signal to match the desired transmission level Doc ID 17526 Rev 2 13 26 Analog front end AFE ST7570 5 3 14 26 Figure6 Transmission path block diagram AM02506v1 The amplitude of the transmitted signal can be set on a 32 step logarithmic scale through the TX_GAIN parameter introducing an attenuation ranging from 0 dB typ corresponding to the TX_OUT full range down to 31 dB typ The attenuation set by the TX_GAIN parameter can be calculated using the formula of
19. current Tx mode no VCCA externally 22 30 mA load supplied VCC UVLO TL VCC under voltage lock out low 6 1 6 5 6 95 V threshold VCC UVLO TH VCC under voltage lock out high 6 8 72 75 V threshold VCC VCC under voltage lock out 1 UVLO HYST _ hysteresis 299 09 i RX Analog supply current Rx mode 5 6 mA TX Analog supply current Tx mode V TX_OUT 5 V p p 8 10 mA No load I VDD Digital core supply current 35 41 mA Digital core supply current in I VDD RESET RESET state 8 mA VDD_PLL PLL supply voltage VDD V PLL supply current 0 4 0 45 mA VDDIO Digital supply voltage Externally supplied 10 3 30r5 10 V VDDIO UVLO TL VDDIO under voltage lock out low 22 24 26 V threshold VDDIOUVLO TH VDDIO under voltage lock out high 245 2 65 2 85 V threshold VDDIO VDDIO under voltage lock out UVLO HYST _ hysteresis 180 240 my Analog front end Power amplifier V PA_OUT BIAS Power amplifier output bias voltage VCC 2 V Rx mode GBWP Power amplifier gain bandwidth 100 MHz product MAX Power amplifier maximum output 1000 mA current rms ID 17526 Rev 2 9 26 Electrical characteristics ST7570 Table 5 Electrical characteristics continued Symbol Parameter Note Min Typ Max Unit V PA_OUT TOL Power amplifier output tolerance 2 3 3 Power amplifier output 2nd VCC 18 V _
20. ero crossing input 37 ZC_IN_D Digital input High Z Disabled Pull up to VDDIO if not used 38 T_REQ Digital input High Z Disabled UART communication control line 39 BR1 Digital input High Z Disabled UART baud rate selection 40 BRO Digital input High Z__ Disabled Sampled after each reset event see Table 3 41 RESERVEDO Connect to GND 42 RESERVED1 Pull up to VDDIO 43 RESERVED2 Pull up to VDDIO 44 RESERVED3 Pull up to VDDIO 45 GND Power Digital ground 1 8 V digital supply 46 VDD Power Internally connected to VDD REG 1V8 Externally accessible for filtering purposes only 47 RESERVED4 Connect to VDDIO 48 RESERVED5 Pull up to VDDIO 6 26 Doc ID 17526 Rev 2 ky 517570 Pin connection Table 3 UART baud rate selection BR1 BR0 Baud rate 0 0 9600 0 1 19200 1 0 38400 1 1 57600 Doc ID 17526 Rev 2 7 26 Maximum ratings ST7570 3 3 1 3 2 8 26 Maximum ratings Absolute maximum ratings Figure 3 Absolute maximum ratings Value Symbol Parameter Unit Min Max VCC Power supply voltage 0 3 20 V VSSA GND Voltage between VSSA and GND 0 3 0 3 V VDDIO supply voltage 0 3 5 5 V VI Digital input voltage GND 0 3 VDDIO 0 3 V vo Digital output voltage GND 0 3 VDDIO 0 3 V V PA IN PA inputs voltage range VSS 0 3 VCC 0 3 V V PA_OUT PA OUT voltage range VSS 0 3 VCC 0
21. ew Figure 10 Functional overview ST7570 HOST Interface External MAC Layer HOST PHY Layer 2 O 2 o 2 o Processor 02510 1 8 1 References Additional information regarding the PHY and MAC layers the MIB and the HOST interface including a detailed description of all services extended functionalities and commands can be found in the following documents 1 ST7570 user manual www st com powerline 2 International standard CEI IEC 61334 5 1 ky Doc ID 17526 Rev 2 19 26 Physical layer ST7570 9 9 1 20 26 Physical layer The ST7570 embeds a IEC 61334 5 1 PHY layer which is based on the S FSK spread FSK modulation technique S FSK principles The S FSK modulation technique is aimed at strengthening the classical FSK by adding higher robustness against narrow band interferers typical of a spread spectrum approach Non return to zero NRZ coding is used to map the binary data 0 or 1 to sinusoidal carriers at frequencies fo and f4 Figure 11 Figure 11 S FSK waveform time domain B i 1 0 1 1 0 sequence i I 1 i 4 1 i i FA A A A A A Wi a i Time AWETYA IVa EA AM Transmission 1 j BUB V V M V V V V V V J AVV V V Vi
22. l controller core with a fully integrated analog front end AFE and line driver The ST7570 features allow the most cost effective single chip power line communication solution based on 61334 5 1 S FSK standard Embedded temperature sensor Table 1 Device summary Current control feature Order codes Package Packaging m 8to 18 V power amplifier suppl wa p pp y ST7570 Tube m 3 3 Vor5 V digital I O supply VFQFPN48 ST7570TR Tape and reel m Integrated 5 V and 1 8 V linear regulators for AFE and digital core supply m Mains zero crossing synchronization September 2012 Doc ID 17526 Rev 2 1 26 This is information on a product in full production www st com Contents ST7570 Contents 1 Device overview 3 2 Pin CONNGCUON sa ucc acad OR D RC RR CR e e CR C 4 2 1 Pin descriptlOn 22 555 do Xd RR dx RR RE XU EI E 5 3 Maximum lt 8 3 1 Absolute maximum 05 8 3 2 Thiermal dala asss siapakah PEDRO EA EN aaa 8 4 Electrical characteristics 9 5 Analog front end AFE 13 5 1 Reception path 13 5 2 Transmission path 1 3 qaku 13 5 3 Power armplilet 32 455
23. matic receiver gain control plus the integrated Power Amplifier delivering up to 1Arms output current makes the ST7570 the first complete system on chip for power line communication Line coupling network design is also simplified leading to a very low cost BOM Safe and performing operations are guaranteed while keeping power consumption and distortion levels very low thus making ST7570 an ideal platform for the most stringent application requirements and regulatory standards compliance Figure 1 Block diagram PALIN PA IN cL Thermal H Management PA_OUT H Output Current Memories H T Control _ 1 Line Driver Memories WAT CHDOG m 9 TIMERS Protocol Controller PHY Processor TXD PRESLOT ZC TS BIT VCC 8180 Power Management 22209 Zero Crossing Detection Clock Management bog VDD ZC INA ZC IND VDD PLL XIN 5V 1 89 1 8V AMO02502v1 Doc ID 17526 Rev 2 3 26 Pin connection ST7570 2 Pin connection Figure2 Pin out top view RESERVEDO RESERVED5 RESERVED4 RESERVED3 RESERVED2 RESERVED1 ZC IN D B A B A B A A N B B o w w 1 36 PRESLOT ZC TS BIT RD 2 35 VSSA VDDIO 3 VDDIO TRSTN 4 GND TMS 5 32 NC GND 6 31 RESERVED6 7 30 NC TDO 8 29 NC TDI 9 28 VDDIO RESETN 10 27 VDD REG 1V8
24. rademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 26 26 Doc ID 17526 Rev 2 ky
25. tering purposes only 18 ZC_IN_A Analog input Analog zero crossing input 19 RX IN Analog input Reception analog input 20 TX OUT Analog output Transmission analog output 21 PA Analog input 2 0 22 IN Analog input 23 CL Analog input Current limit sense input 24 VCC Power Power supply 25 VSS Power Power ground 1 Doc ID 17526 Rev 2 5 26 Pin connection ST7570 Table 2 Pin description continued Pin Name Type Reset state Pull up Description 26 PA_OUT Analog output Power amplifier output 27 VDD_REG_1V8 Power _ _ 1 8 V digital supply interne regulator output Externally accessible for filtering purposes only 28 VDDIO Power 3 3 V 5 V I O external supply 29 NC Not used leave floating 30 NC Not used leave floating 31 RESERVED6 Pull up to VDDIO 32 NC Not used leave floating 33 GND Power Digital ground 34 VDDIO Power 3 3 V 5 V I O supply 35 VSSA Power Analog ground Configurable digital output Slot synchronization PRESLOT Zero Crossing ZC PRESLOT x 36 Digital output High Z Disabled Bit synchronization BIT ZC TS BIT 221242 Transmission progress Reception progress RXP Transmission or Reception in progress TXRXP If not used this pin can be left floating AAT Digital z
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