design review
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1. optional Figure 2 1 FT232R Block Diagram Features e Single chip USB to asynchronous serial data transfer interface e Entire USB protocol handled on the chip No USB specific firmware programming required e Fully integrated 1024 bit EEPROM storing device descriptors and CBUS I O configuration e Fully integrated USB termination resistors e Fully integrated clock generation with no external crystal required plus optional clock output selection enabling a glue less interface to external MCU or FPGA e Data transfer rates from 300 baud to 3 Mbaud RS422 RS485 RS232 at TTL levels e 128 byte receive buffer and 256 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput e FTDI s royalty free Virtual Com Port VCP and Direct D2XX drivers eliminate the requirement for USB driver development in most cases e UART interface support for 7 or 8 data bits 1 or 2 stop bits and odd even mark space no parity e FIFO receive and transmit buffers for high data throughput Microchip PIC24 32 from reference manual PIC24FJ192 http www microchip com pagehandler en us family 1 6bit architecture pic24f html e Driver Controller for USB A port Oasistek tof 2481BE N 7 Segment Display http www oasistek com tw en pro led php e Common cathode multiplexed displays2. Note For all instrutions maximum clock rate is 33 MHz or approximately 30 nsec SMSC LAN8710Ai EZK Small Footprint MII RMII 10 100 Ethernet Transceiver with HP Auto MDIX and flexPWR Technology http www smsc com LAN8710 LAN8710A LAN8710Ai Figure 1 1 System Block Diagram MODEJO TXP TXN RXP RXN RMIIS non TXEN XTAL1 CLKIN XTAL2 niNT RXCLK BD LEDI CRS LED2 COUCRS DV oe E eK a F MDIO PHYAD 0 4N8710A LAN8710Ai Figure 1 2 Architectural Overview TXER TXCLK RXDIO 3 RXDV RXER Features e Single Chip Ethernet Physical Layer Transceiver PHY e HP Auto MDIX support e Small footprint 32 pin QFN lead free RoHS compliant package 5 x 5 x 0 9mm height e High Performance 10 100 Ethernet Transceiver o Compliant with IEEE802 3 802 3u Fast Ethernet Compliant with ISO 802 3 IEEE 802 3 LOBASE T Loop back modes Auto negotiation Automatic polarity detection and correction Link status change wake up detection Vendor specific register functions Supports both MII and the reduced pin count RMII interfaces O O0 U O Cypress CY7C68013A 56 EZ USB FX2LP USB Microcontroller High Speed USB Peripheral Controller http www cypress com mpn CY7C68014A 56PVXC Logic Block Diagram High performance micro 24 MHz using standard tools Ext XTA with lower power options 4 8051 Core 12 24 48 MHz four clocks cycie Abundant I O including two USARTs Data 8 General
3. programmable I F to ASIC DSP or bus standards such as ATAPI EPP etc 2 N ee sS O N i Integrated fuil speed and high speed XCVR Up to 96 MBytes s burst rate Enhanced USB core Soft Configuration FIFO and endpoint memory Simplifies 8051 code Easy firmware changes master or slave operation Features e USB 2 0 USB IF high speed certified TID 40460272 e Single chip integrated USB 2 0 transceiver smart SIE and enhanced 8051 microprocessor e Ultra low power Icc No more than 85 mA in any mode e 16KB of on chip code data RAM e Four integrated FIFOs e Four programmable BULK INTERRUPT and ISOCHRONOUS endpoints e 8 bit or 16 bit external data interface e Smart media standard ECC generation e Integrated industry standard enhanced 8051 Microchip 24AA128 128K C CMOS Serial EEPROM http www microchip com wwwproducts Devices aspx dDocName en010781 e programming for USB FTDI FT232R USB UART IC http www ftdichip com Products ICs FT232R htm vec SLEEP Baud Rate Generator 3 3 Volt 3V30UT LDO FIFO RX 9 Buffer DBUSO DBUS 1 DBUS2 DBUS3 gt DBUS4 USBDP i UART Controller DBUSS Serial Interface USB UART with DBUS6G i Programmable DBUS7 Protocol Engine FIFO Controller Signal Inversion USBDM cCBUSO CBUS1 CBUS2 CBUS3 EEPROM CBUS4 3V30UT FIFO TX Buffer Osco optional pom x4 Cloci aai RESETS Multiplier Generator aeu Cusiiistar To USB Transeiver Cell lt 4
4. 0 A23 HS Yas P30 DQ13 P30 A22 m P30 DQ12 P30 A21 P30 A20 P30 Al9 P30 Al8 P30 Al P30 Al6 P30 A15 P30 Al4 P30 Al3 P30 Al2 P30 All i P30 DQ11 P30 DQ10 P30 DOS P30 DO P30 DQ7 P30 DO E P30 DQ5 P30 DC P30 DQ3 P30 DQ2 VCC3V3 Oe wy 7 t TTY b yaz X X Y V W v x r X j X U tT aay X y y y X Y r x r y bi Ai r x A 9 BIDE 8 T P30 DQ1 P30 A10 ss R145 R146 R148 P30 A9 15K 915K 47K P30 AS8 B3 P30 A7 A3 P30 A6 Q P30 A5 P30 A4 D2 D10 P30 A3 DI P30 AD CI oy Baca P30 Al BI PROG re CDBUOI30L c31 R218 1 5K from Nexys 3 Schematic command sequences used by NOR type Flash An internal write state machine WSM automatically executes the algorithms and timings necessary for BLOCK ERASE and WRITE Each emulated BLOCK ERASE operation results in the contents of the addressed block being written to all Is Data can be programmed in word or buffer increments Erase suspend enables system software to pause an ERASE command so it can read or program data in another block PROGRAM SUSPEND enables system software to pause programming so it can read from other locations within the device The status register indicates when the WSM s BLOCK ERASE or PROGRAM operation is finished A 64 byte 32 word write buffer 1s also included to enable optimum write performance Using the write buffer data is overwritten or programme
5. AM to CellularRAM Power Consumption While CellularRAM is based on DRAM technology the power consumption 1s comparable to SRAM devices Innovative Interface The CellularRAM family supports asynchronous page modes as well as an innovative burst interface that is fully compatible with the low power Flash interface Performance The asynchronous page version access time target is 70ns CellularRAM with burst access mode will support a burst rate of up to 133 MHz Cost The price bit of CellularRAM will be significantly lower than an SRAM device with a corresponding density and technology node http www cellularram com about index html Micron PSRAM CelluarRAM Merging the Best of DRAM and SRAM CellularRAM memory is a pseudo static DRAM PSRAM device that features an SRAM like architecture hidden refresh operation and SRAM pin compatibility This hybrid memory delivers the best of SRAM and DRAM features combining low power consumption and high speed read and write functions Because CellularRAM memory also offers synchronous operations fast access and variable latency initial burst access you get high throughput and excellent performance It s an ideal solution for low power space limited designs like MCPs as well as mobile and industrial applications http www micron com products dram psram cellularram Figure 1 PSRAM DRAM Core Designs with SRAM Interface SRAM gt g P DRAM 6T cell architecture PSRAM 1T cell archit
6. Digilent A Spartan 6 FPGA Poari Notes http IC Xilinx Spartan 6 FPGA XC6LX16 CS324 Programming Digilent USB2 port providing board power programming amp data transfers Connector s Digilent USB2 port USB 2 0 port High speed 40 pin VHDC expansion connector Four 12 pin Pmod connectors VGA and 10 100 Ethernet Board Features 1O00MHz fixed frequency oscillator Xilinx Spartan6 XC6LX16 CS324 16Mbyte Micron Cellular RAM 16Mbyte Micron Parallel PCM 16Mbyte Micron Quad mode SPI PCM 10 100 SMSC LAN8710 PHY 8 slide switches 5 push buttons 4 digit 7seg display 8 LEDs Type A USB host for mouse keyboard or memory stick USB UART Digilent Adept USB port for power programming amp data transfers 8 bit VGA Four double wide Pmod connectors one VHDC connector CellularRAM http www cellularram com The Technology CellularRAM is a multi generation family of low power pseudo static RAM PSRAM for wireless handsets CellularRAM memory is designed to meet the growing memory and bandwidth demands of future handset designs In addition to offering a lower cost bit ratio than current solutions this type of Pseudo SRAM features a SRAM pin compatibility refresh free operation and a low power design Compatibility Asynchronous CellularRAM devices are backward compatible with standard SRAM devices They have the same voltage range package and ball assignment Designers will have a smooth transition from SR
7. E oe Notes 1 Latency is the number of clock cycles from the initiation of a burst operation until data appears Data is transferred on the next clock cycle Figure 22 Latency Counter Variable Initial Latency No Refresh Collision cak iH rmy F FY PF fy Vy Vg A 22 0 i ADV DQ 15 0 DQ 15 0 y Y Don t Care B Undefined Table 6 Fixed Latency Configuration Codes Sows cee cede tatone oo ew aor o a F010 2B docks 33 30ns 33 80ns 33 G0ns 20 50ns ait 3 dock aetea 3 tas rsa rts oe 66 15ns 66 15ns 66 T5ns 40 25ns 100 Ya Seok or ees s is smag 5 0 3 2 mo fega O e oaeen 000 elocks E a E 104 9 625 Others Resev f Cd UN UT Figure 23 Latency Counter Fixed Latency N 1 Cycles Cycle N CLK A 22 0 ADV CE DQ 15 0 READ tsp tp ponso Ym ao mom ve a pcg te Don t Care Re Undefined We have 70XX XX 1 I think Therefore 701 above and CLK gt 100 MHz From starting to look at configurations I believe the clock is not being used connected to ground Timing diagrams start on page 41 Tables for the timing values start on page 37 Phase Change Memory htt www micron com roducts hase change memor Our P8P phase change memory PCM combines the best traits of traditional memory technologies into a single nonvolatile device with a performance boosting parallel interface Ideal for high end high performa
8. b sectors ERASE emulated o Legacy Flash PAGE PROGRAM o Bit alterable page WRITEs o PAGE PROGRAM on all 1s PRESET WRITEs e Write protections protected area size defined by four nonvolatile bits BPO BP1 BP2 and BP3 e JEDEC standard two byte signature DA18h e Uniform 128Kb sectors Flash emulation e 128Mb density with SOIC16 package e More than 1 000 000 WRITE cycles e Phase change memory PCM Chalcogenide phase change storage element VCC3V3 C41 GND 0 luF i scx i SOIC16 package not s VCC3V3 100 100 R136 100 R139 NPSOISALSESCOE GND Nexys 3 User s Manual Signal Names Table 1 Signal Names Serial clock Serial clock Serial data Serial data I O ss data I O input Serial data output Ce a a ooro Hoa moa Hoia input Seria data vo Me E SSCS Ms S Notes 1 Serves as an input during DUAL INPUT FAST PROGRAM DIFP and QUAD INPUT FAST PRO GRAM QIFP instructions Serves as an output during DUAL OUTPUT FAST READ DOFR and QUAD OUTPUT FAST READ QOFR instructions http www micron com media Documents Products Data 20Sheet PCM p5q 32 64 128Mb serial pem ds pdf Notice The board is operating in Quad mode 4 bit I O for each IC Figure 6 WRITE ENABLE WREN Instruction Sequence Figure 8 READ IDENTIFICATION RDID Instruction Sequence and Data Out Sequence s 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 c N Command DQO W
9. d in buffer increments This feature improves system program performance more than 20 times over independent byte writes Timing diagrams start on page 50 Tables for the timing values start on page 49 WE appears to write configuration and then the data to be stored Phase Change Memory http www micron com products phase change memor The P5Q PCM is purpose built to meet the memory requirements of embedded systems delivering multiple I O capability and compatibility via familiar SPI NOR interfaces P5Q improves overall performance and enables software simplification using byte alterability overwrite capability It also increases system level reliability by delivering million write cycle endurance compared to 100 000 for NOR flash http www micron com products phase change memory serial pcm Micron NP5Q128A 13E 128Mb P5Q Serial Phase Change Memory PCM http www micron com parts pcm serial pcm np5q128al3esfc0e pc DE63C83A B049 44B6 8424 1963A6B75C54 Features e SPI bus compatible serial interface e Maximum clock frequency 66 MHz 0 C to 70 C or 33 MHz 30 C to 85 C e Supports legacy SPI protocol and new quad I O or dual I O SPI protocol e Quad I O frequency of 50 MHz resulting in an equivalent clock frequency up to 200 MHz e Dual I O frequency of 66 MHz resulting in an equivalent clock frequency up to 132 MHz e Continuous READ of entire memory via single instruction e WRITE operations o 128K
10. ecture 1T 2T cell architecture Broadside addressing A MAX 0 Dynamic hidden refresh Multiplexed addressing row column Broadside addressing A MAX 0 Static no refresh Dynamic explicit refresh High power High bandwidth Low power Low power High bandwidth Low bandwidth Asynchronous access Synchronous access Asynchronous access Synchronous access http www micron com media Documents Products Technical 20Note DRAM tn4530 psram 101 pdf Review in class Technical Note PSRAM 101 An Introduction to Micron CellularRAM and PSRAM http www micron com media Documents Products Technical 20Note DRAM tn4530_psram_101 pdf Configurations e Figures 2 Async Page Functional Block Diagram e Figure 3 Async Page Burst Functional Block Diagram and e Figure 4 Burst AD Mux Functional Block Diagram Storage Cell Comparison e Figure 5 SRAM Storage Cell e Figure 6 The 1T 1C DRAM Storage Cell Array e Figure 7 DRAM Sense Amp e Figure 8 1T 1C Illustration e Figure 10 2T 2C Sensing Scheme Basic Operations for Broadside Parallel Addressing p 10 13 Setting the Configuration Registers p 19 Two basic methods are available to access the configuration registers configuration register access using CRE and software access Technical Note Variable vs Fixed Latency CellularRAM Operation http www micron com media Documents Products Technical 20Note DRAM tn4522 pdf Also useful Micr
11. nce embedded applications second generation P8P products increase performance improve endurance and simplify software management http www micron com products phase change memory parallel pcm Comparison of High Density Memory Technologies Attributes DRAM PCM NAND MIC NAND HDD Nonvolatile No Yes Yes Yes Yes Erase Required Bit Bit Block Block Sector Software Simple Simple Complex Very Complex Simple Power W GB 100 500 mW die 100 mW die 100 mW die 10W Write Bandwidth GB s 1 100 MB s die 10 100 MB s die 10 MB s die 200 400 MB s Write Latency 20 50ns lps 100ps 800us 10ms Write Energy O 1nJ b lt 1 nJ b 0 1 1 nJ b lt 1 nJ b gt 10 nJ b Read Latency SOns 50 100 ns 10 25 ps 25 50 ps 10ms Read Energy O 1nJ b lt lt 1 nJ b lt lt 1 nJ b lt lt 1 nJ b gt 10 nJ b Idle Power W GB lt lt 0 1W lt lt 0 1W lt lt 0 1W lt 10W Endurance 10 10 10 10 Data Retention ms Not f cycles f cycles f cycles Not f cycles http www micron com media Documents Products White 20Paper pcm _enables_new memory usage models pdf Marketing Information on use and application The Evolution of Phase Change Memory Why PCM is Ready for Prime Time as a Next Generation Nonvolatile Memory http www micron com media Documents Products White 20Paper evolution_of phase_change_memory pdf Micron np8p128a13t1760 128 Mbit P8P Parallel Phase Change Memory PCM http www micron com parts pcm parallel pcm np8p128a13t1760e Fig
12. on mt45w8mwl6obex 8 Meg x 16 128 Mbit PSRAM CelluarRAM http www micron com parts psram cellularram mt45w8 amp mw 1 6bex 701 it Figure 2 Functional Block Diagram 8 Meg x 16 A 22 0 Address Decode Logic gt 8 192K x 16 Input C DOJ7 0 Output ieee MIX and KED DQI15 8 EY Buffers Notes 1 Functional block diagrams Illustrate simplified device operation See ball descriptions Table 1 on page 7 bus operations table Table 2 on page 8 and timing diagrams for detailed information Features e Single device supports asynchronous page and burst operations e Random access time 70ns e Burst mode READ and WRITE access e 4 8 16 or 32 words or continuous burst e Burst wrap or sequential e MAX clock rate 133 MHz tCLK 7 5ns e Burst initial latency 35ns 5 clocks at 133 MHz e tACLK 5 5ns at 133 MHz e Page mode READ access e Sixteen word page size e Interpage READ access 70ns e Intrapage READ access 20ns e Low power consumption e Low power features e On chip temperature compensated refresh TCR e Partial array refresh PAR e Deep power down DPD mode Data sheet review http www micron com products dram psram cellularram fullPart amp 236 3 Bus Operating Modes p 10 14 Registers p 17 23 Initial Access Latency BCR 14 Default Variable Table 5 Variable Latency ro Codes input CLK Frequency 0M Bensan tatan cnt cose S T po a enso 66 5 a E S Tots Oro 5e 6 aeas a H 09 oe
13. ooo High Z Manufacturer identification Device identification bal 15X14X13X A3X2X1X0 SPI Data Transfer Example http www micron com media Documents Products Data 20Sheet PCM p5q_32 64 128Mb serial pem ds pdf Figure 14 QUAD OUTPUT FAST READ Instruction Sequence s N _ oO 0123 4 56 78 9 10 28 29 30 31 32 33 34 35 36 37 BW 39 40 41 42 43 44 45 46 47 c LULU l I I 1 Command 6Bh 24 bit address 8 dummy cycles VO switches from input to output DQO y K3X22X21X K3 X2 X1 X0 D00000 0O CNE i i i Don t Care Mo 4 5X1 X5X1X5 KOX ii Don t Car vo oa oaoo oa arim 1 I o DOTTOR Byte 1 Byte 2 Byte 3 Byte 4 Quad SPI Data Transfer Example http www micron com media Documents Products Data 20Sheet PCM p5q 32 64 128Mb serial pem ds pdf Figure 17 QIFP Instruction Sequence 012 3 4 5 617 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Data in Data in Data in Data in Data in Data in 1 2 3 4 5 6 Don t Care pag ___________1_ Don t Care _ 0000000200208 Don t Ca pas 7S Cae PODANADARODS MSB MSB MSB MSB MSB IMS Notes 1 After 32h is recognized W and HOLD functionality is automatically disabled Quad SPI Data Transfer Example http www micron com media Documents Products Data 20Sheet PCM p5q_32 64 128Mb serial pem ds pdf Timing diagrams start on page 38 Tables for the timing values start on page 37
14. ure 3 56 Lead TSOP Pinout 128Mb Features Al co 56 a Q A15 co 55 A17 Als 3 _ 54 DOTS A13 c 4 3 gm DQ A12 co 52 ea OO All 51 DQE Ald c 0 e DQT3 As co 6s DOF A23 C 48 eE DQI An 46 D Vas ka 12 amp 5 pa C Wire E 4 DOT A20 cz 16 41 DQI A19 cj 40 a DQ10 Als 38 ea 002 Aa co 323 VCCO AT c 20 37 00S aS 2 36 m DQI AS S22 35 DOB a2 34 Ee DQO A3 oe g 33 Ver A2 c 25 32 p OEA HOLD NC 26 31 F V SERIAL cz 27 30 p CESS Ton View e High performance READ 115ns initial READ access 135ns initial READ access 25ns 8 word asynchronous page READ e Architecture Asymmetrically blocked architecture Four 32KB parameter blocks with top or bottom configuration 128KB main blocks Serial peripheral interface SPI to enable lower pin count on board programming e Phase change memory PCM Chalcogenide phase change storage element Bit alterable WRITE operation e Simplified software management No block erase or cleanup required Bit twiddle in either direction 1 0 0 1 35us TYP PROGRAM SUSPEND 35us TYP ERASE SUSPEND Flash data integrator optimized Scalable command set and extended command set compatible Common Flash interface capable Data Sheet P8P parallel PCM provides a set of commands that are compatible with industry standard VCC3V3 R143 yocp VCCI1VS8 VCC3V3 VCC3V3 oo FY x P30 A25 a E7 P30 DQ15 P30 A24 BE a P30 DQ14 P3
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