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Xilinx FPGA user manual - PALMS

1. 104 105 DO NOT EDIT BELOW THIS LINE 106 Bus protocol parameters do not add to or delete 107 C_DWIDTH integer s 32 108 C_NUM_CE integer z 1 Figure 5 4 user_logic vhd Template File Wherever user information is required in the two template files lt ip core name gt vhd and user_logic vhd you will find comments indicating the type of information required and where to place it Because the templates create CoreConnect compliant structures you will not add any additional logic to your Test Drive project However it would be a good idea to view the bare interface setup and operation for future understanding Intellectual Property Bus Functional Model Simulation Optional but Recommended Note If you made no selections in the wizard screen for BFM simulation see Peripheral Simulation Support page 39 skip to the test drive section Running the CIP Wizard to Re import test_ip into Your XPS Project page 47 The best thing you can do to understand BFM Simulation options is to explore the BFM project created for you by the CIP Wizard So let s take another test drive im Test Drive Note lf in the CIP Wizard you selected the check box to create the BFMs you must close your XPS project before proceeding with the following steps If you elected to create the BFMs the CIP Wizard created a sub directory to your pcores test_ip_v1_00_a dev1 directory called bfmsim in w
2. 0005 13 Before State sessi rud nee ERE ene tho ele E sh 4 EER E E E E AD arse 14 Installation Requirements What You Need to Run EDK Tools 05 14 Chapter 2 Creating a New Project The Base System Builder BSB 0 0 0 cece eee eee 17 Why Shotild TUse BSB csccnceesccetuenetsnt mie cigincndes e EE E E EE wigiln gable abe etna gud 17 What You Can Do in the BSB Wizard 0 0 0 0c eee eens 17 Creating Your Top level Project File xmp File 0 0 0 eee ee eee 17 Selecting a Board Type sssi vias eee d d dee dee cee Seca decal vans 18 Selecting and Configuring a Processor 1 6 6c eee eens 18 Selecting and Configuring Multiple I O Interfaces nunun nnan eee eee 18 Adding Internal Peripherals 1 2 0 0 ccc eet ee eens 18 Setting Up SOMW ALC acai ser secee baad a bea acaba Seated ete aed weet E 19 Viewing a System Summary Page 2 6 cece ee eee eens 19 Test Drive iy cenaa i ele oe ares ed a ee JA es ahaa ee aw ee ES ae 19 What s Next 545 054000ied aint ocued EEEE e bE coset meducs ade a eE 21 Chapter 3 Xilinx Platform Studio XPS What 18 XPS ease ta eis ee Baa eee ee eee cn ea aes ene 23 The XPS GW ios h2 shh tes oh ah tiene eed Sib adele TENIO EREEREER ERER OEERR R 23 The Project Information Panel 0 66 24 The Project Tabes sehera raana i a E A EE AE EA A EE 25 TheApplications Tab 00 ccocsesteweaesa deba aeaa a e eke send 25 ThelPCatalos abs cxic
3. System Assembly View Output Warnings Simulation Model Generator Simgen 44 7 Figure 5 5 XPS BFM User PCORE Simulation Project Select Project gt Project Options and click the HDL and Simulation tab Select the HDL format in which you would like to simulate For this example VHDL default is chosen Select the simulator you are using either ModelSim or NCSim This guide uses ModelSim You should have your EDK simulation libraries compiled and pointing to the proper locations a Ifso enter the location for the EDK and ISE libraries b Ifyou have not compiled these click Simulation gt Compile Simulation Libraries and follow the steps given in the Simulation Library Compilation Wizard For more information regarding simulation library compilation refer to the XPS Help topic Procedures for Embedded Processor Design gt Simulation gt Compiling Simulation Libraries in XPS BFM only offers Behavioral Simulation so leave the Simulation Model selection set to its default Select OK when your have finished setting up the simulation options Select Simulation gt Generate Simulation HDL Files to run the Simulation Model Generator Simgen for this test project www xilinx com EDK Concepts Tools and Techniques P N XTPO13 v 9 1i The Create and Import Peripheral CIP Wizard XILINX Simgen creates a simulation behavioral directory structure under the bfmsim directory The behavi
4. Figure 6 1 Elements and Stages of ELF File Generation The Platform Studio Software Development Kit 50 The Platform Studio Software Development Kit SDK was designed to facilitate the development of embedded software application projects SDK has its own GUI and is based on the Eclipse open source tool suite The Platform Studio SDK is a complementary program to XPS that is from SDK you can develop the software that the peripherals and processor s elements connected in XPS use You must create an SDK project for each software application The project directory contains your C C source files executable output file and associated utility files such as the make files used to build the project Each SDK project directory is typically located under the XPS project directory tree for the embedded system that the application targets Each SDK project produces just one executable file lt project_name gt e1f Therefore you may have more than one SDK project targeting a single XPS embedded system www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Platform Studio Software Development Kit XILINX im Test Drive In XPS Generate the BSP and Run Libgen Library Generator Libgen 2 When SDK opens the Application Wizard appears to assist in creating a software application project If the wizard not open automatically click Xilinx Tools gt Launch Application Wizard In the wizard dialog box se
5. BRAM memory peripherals that you can initialize with your embedded software Executable and Linkable Format ELF file EDK can generate your choice of e A behavioral model based on your hardware platform specification alone e A post synthesis structural model e Acomplete post place and route timing accurate model Verification through behavioral structural and timing simulation can be performed at specific points in your design process as illustrated in the figure below The simulation model generation tool Simgen creates and configures specified HDL design files Design Design Synthesis Netlist Design Implementation Implemented Design Netlist Simulation Structural Simulation Figure 7 1 FPGA Design Simulation Stages UG111_01_051005 The simulators that support EDK require you to compile the HDL libraries before you can use them for design simulation The advantages of compiling HDL libraries include speed of execution and efficient use of memory It is assumed that your libraries are compiled at this point If not see Before Starting in Chapter 1 of this book For additional information about simulation including descriptions of behavioral structural and timing simulation see the Simulation Model Generator Simgen chapter of the Embedded System Tools Reference Manual at http www xilinx com ise embedded edk_docs htm Simulation Considerations When simulating your des
6. IP2Bus_Ack IP2Bus_Retry IP2Bus_Error RFIFO2IP_WrAck RFIFO2IP_AlmostFull RFIFO2IP_Full WFIFO2IP_RdAck WFIFO2IP_AlmostEmpty WFIFO2IP_Empty WFIFO2IP_Data IP2FIFO_Data IP2Bus_ToutSup IP2RFIFO_WrReq IP2WFIFO_RdReq IP2Bus_IntrEvent test_ip vhd OPB_ABus OPB_DBus OPB_BE SI_DBus Sl_errAck OPB_Clk Sl_retry OPB_Rst OPB_RNW OPB_select OPB_seqAddr Sl_toutSup SI_xferAck IP2INTC_Irpt X10513 Figure 5 3 user_logic vhd and test_ip vhd Block Diagrams Create and Import Peripheral Wizard Template Files This brief discussion of the interface provides the background you need to create some usable proprietary logic Let s take a test drive to review the template files the Wizard has created for you pr Test Drive In XPS select File gt Open and navigate to the pcores test_ip_v1_00_a hdl vhd1 directory Here you will find two files as listed in Figure 5 2 page 41 the test_ip vhd file and the user_logic vhd file Open the user_logic vhd file Search for the value entity user_logic and find the occurrence that appears as shown in the figure below www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Create and Import Peripheral CIP Wizard XILINX 98 entity user_logic is 99 generic 100 101 ADD USER GENERICS BELOW THIS LINE 102 USER generics added here Zi Insert USER value 103 ADD USER GENERICS ABOVE THIS LINE
7. Top Down Design Method Begin your design development in ISE Project Navigator Use the following procedure to create an embedded processor subsystem in your ISE design and begin designing in XPS Select the ISE Project in Project Navigator and launch XPS 1 If necessary open the ISE Project Navigator and create or open an ISE project for your top level FPGA design 2 If you intend to target a specific development board in BSB select the same Device Package and Speed Grade as is used on the targeted board 3 Select Project gt New Source The New Source window appears Note You may or may not already have a top level Hardware Description Language HDL source file added to your ISE project at this time In the New Source window select Embedded Processor as the source type In the File Name field enter a name for your XPS project This will also be the component name of the embedded submodule in your top level design By default your XPS project is created in a subfolder of your ISE project and the folder name is the same as the project name Click Next 7 Review the specifications for the new source and click Finish ISE automatically launches XPS so you can create your new embedded processor project Develop Your Embedded Hardware Platform Design 1 A prompt appears in XPS asking whether you want to use BSB This is recommended especially if you are using a development board supported by BSB 2 BSB allows you to
8. You can use this template to copy component declaration and instantiation samples into your top level HDL design 1 In Project Navigator select your embedded processor source in the Sources for Synthesis Implementation pane 2 Inthe Processes panel run the View HDL Instantiation Template to open the template in the Project Navigator editor pane 3 Copy the component declaration for the embedded system VHDL and paste it into your top level design architecture 4 Copy the instantiation sample of the embedded system into your top level design and provide net name connections as necessary Connecting the Embedded Submodule You can connect output ports in your embedded submodule to output ports and to other loads in your top level design You can drive input ports in your embedded design from input ports or other logic in your top level design The component port interface of the embedded submodule has a one to one correspondence with the External Ports in the MHS file EDK Concepts Tools and Techniques www xilinx com 87 P N XTPO13 v 9 1i X XILINX 88 Appendix A Embedded Submodule Design with ISE To facilitate the copying of pinout constraints if you targeted a specific development board in BSB use the same port names in your top level design as BSB generated on the embedded submodule component Copying Constraints to Your ISE Project Whenever you run the BSB in XPS it generates a UCF lt projectname gt u
9. 9 1i Conventions Preface About This Guide This document uses the following conventions An example illustrates each convention Typographical This document uses the following typographical conventions Convention Courier font Meaning or Use Messages prompts and program files that the system displays Example speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name Helvetica bold Commands that you select from a menu File gt Open Keyboard shortcuts Cirl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Horizontal ellipsis Vertical ellipsis ae i ene aey Repetitive material that has p i 7 i been omitted Repetitive material that has allow block block_name been omitted loc1 lo
10. Because this file is machine generated there is not much need to review the sample do file other than to note that there is a 1 6 translation roughly that occurs from the BFL input commands to the resulting output simulation command file The benefit to you a substantial time savings compared to manual entry of the simulator commands www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Glossary Appendix C B BBD file BFL BFM BIT File Bitlnit block RAM BMM file BSB EDK Concepts Tools and Techniques P N XTP013 v 9 1i Black Box Definition file The BBD file lists the netlist files used by a peripheral Bus Functional Language Bus Functional Model Xilinx Integrated Software Environment ISE Bitstream file The Bitstream Initializer tool It initializes the instruction memory of processors on the FPGA and stores the instruction memory in BlockRAMs in the FPGA A block of random access memory built into a device as distinguished from distributed LUT based random access memory Block Memory Map file A Block Memory Map file is a text file that has syntactic descriptions of how individual Block RAMs constitute a contiguous logical data space Data2MEM uses BMM files to direct the translation of data into the proper initialization form Since a BMM file is a text file it is directly editable Base System Builder A wizard for creating a complete ED
11. Concepts Tools and Techniques P N XTP013 v 9 1i Platform Debug 10 2 XILINX In the Value column reset the values as follows OPB_ABUS 5000_0XXxX OPB_DBUS 3022 _XXxXxX TRIG_IN X_FFFF_C3B8 Click the Add button on the left side of the trigger section of the Trigger Setup pane two more times to add additional trigger conditions Set them as follows TriggerConditionO M1 TriggerConditionl M2 TriggerCondition2 M3 Set the trigger position equal to 250 The trigger setup looks similar to that shown in the figure below Trigger Setup DEV 2 MyDevice2 MC4VFX12 UNIT 0 MyiBA ooo Bd Match Unit Function Value Radix Counter Uae 4 gt MO TRIGO OPB_CTRL gt M1 TRIG1 OPB_ABUS Step 8 p Step 9 M2 TRIG2 OPB_DBUS gt M3 TRIG3 TRIG_IN Bu amden 11 Disabled Storage Qualification All Data Figure 9 7 ChipScope Pro Logic Analyzer Trigger Setup With TriggerCondition0 selected as the active trigger click the Apply Settings and Arm Trigger toolbar icon p 12 Activate TriggerCondition1 and TriggerCondition2 Notice the instructions being executed by the processor You can observe these in the C40 5DBGWBIAR values given in the ChipScope Pro logic analyzer and correlate this to the disassembled code present in the SDK Debug perspective Platform Debug Hardware Triggering Control 1 T
12. TestApp_Memory application and deselect Mark to Initialize BRAMs You re going to have the Project TestApp_Peripheral application take care of this 3 Make sure XPS is enabled to manage the data with which BRAMs are initialized in the TestApp_Peripheral project The TestApp_Peripheral project was created in SDK and XPS assumes that you are now actively managing this project from SDK To work with the TestApp_Peripheral project XPS will ask you to change it to an ELF only project a Double click Project TestApp_Peripheral to open the dialog box as shown in the figure below Resolve Stale Application This application is being managed in SDK In order to resolve potential conflicts please make one of the following choices Convert XPS application into an ELF only appication Recommended XPS can be used for download if required Delete the application in XPS Application settings are no longer retained Source files are not deleted Make application inactive in XPS Application settings retained Source files are not deleted Cancel out of this dialog if you want to delete the application in SDK XPS can then be used to manage the application Figure 6 6 XPS ELF File Management Option b Select the radio button option Convert XPS application into an ELF only application When you click OK XPS continues to manage the data with which BRAM is initialized but it turns the software project management function over
13. and customizing IP are discussed in Chapter 5 Creating Your Own Intellectual Property IP Generating Your Hardware Platform To generate the hardware platform you first tell XPS to generate a netlist and then issue the command to generate the bitstream This operation will be part of a future Test Drive exercise In the meantime you probably want to know what happens when the netlist and bitstream are created so a quick synopsis is provided below Netlist Generation When you tell XPS to generate the netlist it invokes the platform building tool Platgen which does the following Reads the design platform configuration MHS file Generates an HDL representation of the MHS file written to system vhd v along with a system_stub vhd v The system file is your MHS description 34 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i What s Next XILINX written in HDL format This is for designs that are processor centric and developed solely in XPS The file system_stub is a top level HDL template file instantiation of the embedded system created as a starting point for FPGA centric designs FPGA centric designs are those in which the embedded system is a sub module in a larger design Synthesizes the design using Xilinx Synthesis Technology XST Produces a netlist file More information about PlatGen is available in the Platform Generator PlatGen chapter in the Embed
14. bus to expand it Remove TRIG_IN 32 from the bus When you are finished collapse the bus by double clicking the bus name C405DBGWBIAR 5 Drag TRIG_IN 32 from the Signals window in ChipScope to the Waveform window Rename it as C4OSDBGSTOPACK EDK Concepts Tools and Techniques www xilinx com 79 P N XTPO13 v 9 1i XILINX 80 Chapter 9 Debugging the Design Your completed waveform window looks similar to the figure below 3 Waveform DEV 2 MyDevice2 Bus Signal xX 0 gt OPB_ABUS OPB_DBUS C405DBGNWBIAR C405DBGSTOPACK 0j 0 Figure 9 6 ChipScope Pro Logic Analyzer Waveform Setup With this basic configuration setup click the Trigger Now icon T in the ChipScope Pro toolbar This 1 instructs the ChipScope Pro Logic analyzer to sample system data for the previously configured signals and 2 provides a quick check that the ChipScope Pro logic analyzer the ChipScope Pro IP elements and the JTAG connection between these two items is capturing data Without closing ChipScope open SDK In disassembly view find the module identification register test by searching for the value of 0x30220301 Note the instruction value ffffc3b8 Return to ChipScope Now we ll be a little more specific regarding the data that should be captured In the Trigger Setup window find the Radix column and change each line item value to Hexadecimal by clicking it and resetting the value www xilinx com EDK
15. connection symbols indicate mastership of the IP core bus interface A hollow connector represents a connection that you can make and a filled connector represents a connection made To create or disable a connection click the connector symbol EDK Concepts Tools and Techniques P N XTPO13 v 9 1i www xilinx com 27 XILINX Chapter 3 Xilinx Platform Studio XPS Information Viewing and Sorting To allow you to sort information and revise your design more easily the System Assembly Panel provides two view options hierarchical view and flat view Hierarchical and Flat Views Hierarchical view is the default in the System Assembly Panel In the hierarchical view the information about your design is based on the IP core instances in your hardware platform and organized in an expandable or collapsible tree structure When you click the directory structure icon circled in Figure 3 5 the ports are displayed either hierarchically or in a flattened or flat view The flat view allows you to sort information in the System Assembly Panel alphanumerically by any column Expanded or Collapsed Nodes The icon also circled expands or collapses all nets or buses associated with an IP This allows quick association of a net with the IP elements im Test Drive In the System Assembly Panel e Click the Ports radio button located at the top of the System Assembly Panel Expand the External Ports category to vi
16. is defined As with the hardware assembly XPS allows you to specify all aspects of your software platform and manage your software applications The Applications tab in XPS contains the tools and commands you need For a reminder on how to find the Applications tab see Figure 3 3 page 25 The MSS File and Other Software Platform Elements Microprocessor Software Specification MSS The hardware portion of your Test Drive project uses the MHS file to describe the hardware elements in a high level form XPS maintains an analogous software system description in the Microprocessor Software Specification MSS file The MSS file together with your software applications are the principal source files representing the software elements of your embedded system This collection of files used in conjunction with EDK installed libraries and drivers and any custom libraries and drivers for custom peripherals you provide allows XPS to compile your applications The compiled software routines are available as an Executable and Linkable Format ELF file The ELF file is the binary ones and zeros that are run on the processor hardware The figure below shows the files and flow stages that generate the ELF file EDK Concepts Tools and Techniques www xilinx com 49 P N XTPO13 v 9 1i X XILINX Chapter 6 The Software Platform and SDK Object Files obj tween Executable and Linkable Format file elf X10589
17. memory size EDK Concepts Tools and Techniques www xilinx com 19 P N XTPO13 v 9 1i X XILINX Chapter 2 Creating a New Project Wizard Screens System Property Setting to Use for Your Test Drive Software Setup e Software setup e Select your STDIN OUT device s In the BSB software setup Be sure the RS232_Uart peripheral is one of these dialog boxes you specify how you would like to use your system BSB can also set up any software tests you would like to create e Boot memory e plb_bram_if_cntlr_1 e Memory and peripheral e Use default application tests tests The software tests send or receive information to selected peripherals The microprocessor interprets the status of the peripherals and reports it via the STDIN STDOUT peripheral Configure Memory Test Instruction Data and For the purposes of this project place these in Application Stack Heap memory plb_bram_if_cntlr_1 Configure Peripheral locations This specifies that the program code operates out of the Test Application block RAM contained in the FPGA p1b_bram using the BRAM controller _if_cnt1r_1 System Created System summary page After you have selected and configured all your system components BSB displays an overview of the system which allows you to verify your selections At this point you have an opportunity to go back to any previous wizard dialog box and make revisions When the
18. more on the powerpc eabi obj dump routine see the GNU Utilities appendix in the Embedded System Tools Reference Manual at http www xilinx com ise embedded edk_docs htm Specific information about the switches that powerpc eabi obj dump supports can be found by running powerpc eabi objdump H on the command line In XPS click Simulation gt Launch HDL Simulator Providing you have an EDK supported simulator installed it appears with the system_setup do file invoked The simulator is now ready to compile and load your design Assuming you are using ModelSim at the prompt enter the following commands c Compile the designs s Load the design w Set up the waveform window rst Toggle the reset port and set the clock frequency to 100 MHz run 3ms Run simulation at 3 ms While your simulation is running launch SDK and open the test_ip_selftest c file located in your SDK_projects TestApp_Peripheral directory In the file find the second interaction between the processor and the custom IP you developed This code tells the system to read the interrupt register value of test_ip as shown in the figure below You must locate the second interaction between the processor and the peripheral because of the processor request for the slave to respond with some information EDK Concepts Tools and Techniques www xilinx com 61 P N XTPO13 v 9 1i EZ XILINX Chapter 7 Introduction to Simulation in XPS G test_ip_sel
19. of the fluid nature of the hardware platform and the rich Xilinx and Xilinx third party partner support you may create several software platforms for each of your hardware platforms Serial Peripheral Interface Standalone BSP SVF File EDK Concepts Tools and Techniques P N XTP013 v 9 1i Standalone Board Support Package A set of software modules that access processor specific functions The Standalone BSP is designed for use when an application accesses board or processor features directly without an intervening OS layer Serial Vector Format file www xilinx com 99 X XILINX U UART UCF VHDL VP VPgen XBD File XCL Xilkernel XMD XMK 100 Appendix C Glossary Universal Asynchronous Receiver Transmitter User Constraints File VHSIC Hardware Description Language Virtual Platform The Virtual Platform Generator sub component of the Platform Studio technology Xilinx Board Definition file Xilinx CacheLink A high performance external memory cache interface available on the MicroBlaze processor The Xilinx Embedded Kernel shipped with EDK A small extremely modular and configurable RTOS for the Xilinx embedded software platform Xilinx Microprocessor Debugger Xilinx Microkernel The entity representing the collective software system comprising the standard C libraries Xilkernel Standalone BSP LibXil Net LibXil MFS LibXil File and LibXil Drivers ww
20. peii a i a eta EER E eee 26 est DAVE lerarekin ted ate he SE oe Bk a a a ORE E a ea 26 The System Assembly Panel escris niran ie a EER EE E 27 Bus Interface Ports and Address Filters 0 ccc cece cee eee eens 27 The Connectivity Paneles cgi sates sett aii dete ante titan eee setae 27 Information Viewing and Sorting 0 0 0 ce eee ene 28 EDK Concepts Tools and Techniques www xilinx com P N XTPO13 v 9 1i X XILINX Test DAVE 5 deceit E E E E a hab a bead thea dea dees 28 The Platform Studio Tab 0 ce eee eee nett teen nee 28 Test Dive te sicg eid cc chose esd cecein ded ab Behe Rae econ ine Ses ake oA 29 The Console Panel 0 00 0c ccc ee eee ee eee eee e een eees 29 PST ONS i sonic acc atest Sette Bi tie este ett ata Pectin Pectetn y EA 30 a SS tl oh 3a Oe O A G 30 XPS Directory Structure lt lt ccc stevens decried ew hivei ber eeb sents ea tienies 30 Directores ereere ree Gries ecb a ee a tee en cee a a a a eE Dataset 30 Test Drivel oirean ue hd hee a whee ee a Gade ded ee adeeb ave a as 31 Whats Next soi ccec cnn cde abe patent ata naetenh peach natanscn neta EEEN KARERE RENEA NA 31 Chapter 4 The Embedded Hardware Platform What s in a Hardware Platform 00 ccc eee 33 Hardware Platform Development in Xilinx Platform Studio 33 The MHS Pile scse4cegte oten be ead toads dee eked eee pede E EAE 33 Test Driyel cant oi psd ie a pana big seed nse ead EA E
21. such as the XPS Software Development Kit SDK to download your program to the board The complete EDK program flow is shown in the figure below 68 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Netlist Generation Review system mhs Platgen Synthesis System IP ll mpd Il EDIF IP Netlists Hardware gt ei Generate Netlist ISE XFlow Bit File bitstream bit Hardware gt Generate Bitstream Executable and Linkable Format file Data2MEM system bit GCC Linker elf X XILINX MSS File system mss Hardware X10585 Figure 8 4 Elements and Stages of XPS and EDK Leading to FPGA Configuration d Test Drive 1 At this point your design netlists are generated the software is configured in the TestApp_Peripheral project and the executable ELF file is selected to initialize BRAMs As a quick sanity check use the Software gt Get Program Size menu command to ensure that the compiled TestApp_Peripheral code fits into the BRAMs for this design If you recall you specified 16 KB BRAM memory in the first test drive 2 Select Device Configuration gt Update Bitstream to merge the FPGA bitstream and ELF files into a single bitstream file 3 Ensure the serial and JTAG cables are connected the development board is powered on and a serial terminal is connected properly and set to the 9600 baud rate EDK Concepts
22. system summary looks correct click Generate Finish During design generation When you click Finish XPS is populated with the the directory structure of system you just created your system is created The HDL and other files are populated with the choices you made earlier and connections between the processor busses and peripherals are handled along with any additional logic being instantiated 20 www xilinx com EDK Concepts Tools and Techniques P N XTPO13 v 9 1i What s Next What s Next 2 XILINX In the next chapter you will learn how you can view and modify the characteristics of your new project in XPS Creating Your BSB Variant Creating a custom board library involves creating a Xilinx Board Description file xbd and placing it in the XILINX_EDK board location For more information on this topic see the Xilinx Board Description XBD chapter of the Platform Specification Format Reference Manual available at http www xilinx com ise embedded edk_docs htm EDK Concepts Tools and Techniques www xilinx com 21 P N XTPO13 v 9 1i XILINX Chapter 2 Creating a New Project 22 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 3 Xilinx Platform Studio XPS What is XPS The XPS GUI Now that you have created a baseline project with BSB it s time to take a look at the options available to you in Xilinx Platfor
23. the instruction are 0 To get the address of the current instruction the two lower bits must be appended to Current instruction C405DBGWBIAR Therefore C405DBGWBIAR and 0b00 is the current instruction address address For the ChipScope Analyzer to display the address of the current instruction correctly these last two zero 0 bits must be appended Also notice that the output from the IBA core is connected to the DBGC40 5UNCONDDEBUGEVENT input on the PowerPC core A high logic level on this signal stops the processor These are the signals and connections required to create the hardware software cross ChipScope processor triggering capability mentioned earlier stop C405DBGSTOPACK Indicates the PowerPC is in debug halt mode EDK Concepts Tools and Techniques www xilinx com 77 P N XTPO13 v 9 11 XILINX Chapter 9 Debugging the Design C405DBGWBIAR 0 29 The address of the current instruction in the PowerPC write back pipeline stage DBGC405UNCONDDEBUGEVENT Indicates that external debug logic is causing an unconditional debug event Generate the Bitstream in XPS and Observe Platform Debugging 1 After adding the two new cores you must create a new hardware bitstream Select the Hardware gt Generate Bitstream menu option 2 In SDK to observe the Platform debugging operat
24. the hardware logic in your processor subsystem Such customization is not possible using standard off the shelf microprocessor or controller chips Hardware platform is a term that describes the flexible embedded processing subsystem you are creating with Xilinx technology for your application needs Hardware Description Language Integrated Bus Analyzer Integrated Design Environment www xilinx com 95 X XILINX 96 ILA ILMB IOPB IPIC IPIF ISA ISC ISS JTAG Libgen Appendix C Glossary Integrated Logic Analyzer Instruction side Local Memory Bus See also LMB Instruction side On chip Peripheral Bus See also OPB Intellectual Property Interconnect Intellectual Property Interface Instruction Set Architecture The ISA describes how aspects of the processor including the instruction set registers interrupts exceptions and addresses are visible to the programmer Interrupt Source Controller Instruction Set Simulator Joint Test Action Group Library Generator sub component of the Xilinx Platform Studio technology LibXil Standard C Libraries EDK libraries and device drivers provide standard C library functions as well as functions to access peripherals Libgen automatically configures the EDK libraries for every project based on the MSS file www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i X XILINX LibXil File A module that p
25. would like to modify the BFM for your own purposes 3 Bein data S devl O bfmsim ao Xps blkdiagram data etc H O peores O scripts E sample bfl El run do El sample do E wave do Figure B 1 BFM Directory and Files XPS created the sample bf 1 file as part of the Create and Import Peripheral CIP Wizard process described in Chapter 5 Creating Your Own Intellectual Property IP As the name implies sample bf1 is a sample bus functional language BFL script file The sample bf1 file is the one you modify or recreate as another file for your own uses With this understanding open the sample bf1 file in a text editor to review what has been created for you Again this file contains some initial alias commands for human readability Look for them in the BFL file in the order shown below 1 Byte enable aliases 2 Unit Under Test UUT aliases These correspond to the same values given in the drivers test_ip_v1_00_a src test_ip h file This file was also created as part of the CIP Wizard process Note that although the base address may be different EDK Concepts Tools and Techniques www xilinx com 91 P N XTPO13 v 9 1i X XILINX 92 Appendix B More About BFM Simulation from the one in your actual system the various register interrupt and FIFO address values are the same because they are all set relative to the base address in the test_ip h file 3 Data aliases create readable val
26. Ape eee Gia 87 Appendix B More About BFM Simulation Appendix C Glossary 6 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i gt XILINX Preface About This Guide This guide explains the basics of the EDK embedded design flow tools architecture and concepts behind the EDK design process It also provides an opportunity for you try out the EDK tools by taking them for a test drive following a sample project Specifications for the sample project are provided Guide contents include Chapter 1 Introduction Chapter 2 Creating a New Project Chapter 3 Xilinx Platform Studio XPS Chapter 4 The Embedded Hardware Platform Chapter 5 Creating Your Own Intellectual Property IP Chapter 6 The Software Platform and SDK Chapter 7 Introduction to Simulation in XPS Chapter 8 Implementing and Downloading Your Design Chapter 9 Debugging the Design Appendix A Embedded Submodule Design with ISE Appendix B More About BFM Simulation Additional Resources To find additional EDK documentation see the Xilinx Website at http www xilinx com ise embedded edk_docs htm To search the Answer Database for silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx Website at http www xilinx com support EDK Concepts Tools and Techniques www xilinx com 7 P N XTP013 v
27. Class Sensitivity IPA p Pat a San dem_modue 1 00 E D doom ban bram _block 1 0 E Sivon ban bram_block 1 0C S banow l bram_block 10c E Preset dock pIOc_sys_reset 1 00 E gt SRAM 256082 _ vat uti _bus_spit 1 00 BR Dob ban oxi 1 pb_bram_ cri 0 f ob_uartite 1 00 INTERRUPT EDGE_RISING Bus Interface Potts Addresses Name Address Base Address HighAdcess Sie Lock pb bridge il u o 1405 vintend 1 01 a DSOCM Oe7OS8CHO0 Ox TOIT 16k o 4 102 ISOCM Qval308000 OwNINbiNi 16k Ov v20 1 1 MOCR IDOR U oO em_v10 20t SDCA U o im_vi0 20 SDCR DCR uU ap ppc_ontk 200 Push Buttons Position SOPB Or6Q000800 OxsODOHtt 6k o em 0 SOPB avsosooeeo Oos KOO jam_t_onik aor plb_bram iter SPLE c _baseaddrc_highadd Ovi f 16k O paas ce SRAM_256Kx32 SPLE MEMO OODI OOUE w vo gt SPLE RNGO Onh2000800 Ovttiiiit S124 Oo SPLE ANGI 1c Figure 3 5 System Assembly Panel Views The Connectivity Panel With the Bus Interface filter selected you ll see the Connectivity Panel highlighted by the dashed line in Figure 3 5 The Connectivity Panel is a graphical representation of the hardware platform interconnects A vertical line represents a bus and a horizontal line represents a bus interface to an IP core If a compatible connection can be made a connector is displayed at the intersection between the bus and IP core bus interface The lines and connectors are color coded to show the compatibility Differently shaped
28. EA Guedes E AEA A whee 34 Viewing the Hardware Platform from the System Assembly Panel 34 Generating Your Hardware Platform 2 1 sussana sannur nner rannan 34 What s Next ica leak vee bY ee EPR EEN e RE Hee ae 35 Chapter 5 Creating Your Own Intellectual Property IP IP Creation Overview 0 0 0 00 cece cette enn nee eeas 37 How to Do It Use the CIP Wizard 0 ccc eee nee nee 38 The Create and Import Peripheral CIP Wizard 05 38 What You Need to Know Before Running the CIP Wizard 5 38 CoreConnect Compliant Peripherals 0 0 0 cece eens 38 Fest Drivel Sales se so ae de teed dh eee Mera sca bas eRe a as ete dan a esse ee aaea a 39 What Just Happened 0 6 6 eee en nee 40 Intellectual Property Interface IPIF 0 cece eens 40 Create and Import Peripheral Wizard Template Files 0 000000 e eae 42 Fest Bc eee on eee a ee O S 42 Intellectual Property Bus Functional Model Simulation Optional but Recommended 43 Fest Drivel rosses ianea E ets a a cd ths we ON ee es aes Aah aide Sie ain bk de 43 What Just Happened ix eers asami i vda ee Pde wa eee ae 45 How Can I Modify IP Created with the CIP Wizard 0 0 6 0 cece eee 46 Test Drivel rreiie eee ia gd Gad ea has Had Rk Se ee eg eg had da ee ed Bd 46 Adding User IP to Your Processor System 6 6 cee eens 46 Test Driiy leon jess eps 8 es aves esa a B ee ole aL Goad Gis bw O
29. EDK Concepts Tools and Techniques A Hands on Guide to Effective Embedded System Design P N XTP013 Version 9 1i XILINX 7 XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in c
30. H SS bog da 8 47 Running the CIP Wizard to Re import test_ip into Your XPS Project 47 Updating User Repositories to Include test_ip cece eee eee eee 48 Wihat s Next cc 6a5steassctea ceeds esd naeedoete a atoawerde ated eaaa Ea aa 48 Chapter 6 The Software Platform and SDK The Board Support Package BSP 0 cece cece eee ee eee een ee 49 The MSS File and Other Software Platform Elements 49 4 www xilinx com EDK Concepts Tools and Techniques P N XTPO13 v 9 1i 2 XILINX The Platform Studio Software Development Kit 04 50 TESE Bc aroi Pen SO eo er ee a 51 In XPS Generate the BSP and Run Libgen 0 6 eee eee ee 51 Launch SDK and Import Your Test Applications 0 2 0 60 cee eee ee eee 51 Add Some Test Software for Your Custom IP 1 0 ccc cc eens 52 MS SEMI VG taste coesn Gisse Reda ds a a a a ee oe eae seg ve cade hoe cabs a ergy ae drome 52 Locating and Importing the Software Test Files 0 2 c cee eee ee 52 Editing the test_app_peripheral c File 0 cece cece eee 52 Rebuilding Your Projects 20 lt 42 lt 80500 sete eenean teenie ede ieee eee 53 Returning to XPS to Complete Your Project 0 0 e eee 54 Test Drivel esor eed Geese tee ee eee ga Rae Bd ee 55 Whats Nexte oct reee e eea pete WS ero im ease etn neste ected ae eae teams 56 Chapter 7 Introduction to Simulation in XPS Befo
31. K design BSB is also the file type used in the Base System Builder www xilinx com 93 2 XILINX BSP DCM DCR DLMB DMA DOPB DRC EDIF file EDK ELF file EMC EST 94 Appendix C Glossary See Standalone BSP Digital Clock Manager Device Control Register Data side Local Memory Bus See also LMB Direct Memory Access Data side On chip Peripheral Bus See also OPB Design Rule Check Electronic Data Interchange Format file An industry standard file format for specifying a design netlist Embedded Development Kit Executable and Linkable Format file Enclosure Management Controller Embedded System Tools www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX FATfs XilFATfs FPGA FSL GDB GPIO LibXil FATFile System The XilFATfs file system access library provides read write access to files stored on a Xilinx System ACE CompactFlash or IBM microdrive device Field Programmable Gate Array MicroBlaze Fast Simplex Link Unidirectional point to point data streaming interfaces ideal for hardware acceleration The MicroBlaze processor has FSL interfaces directly to the processor GNU Debugger General Purpose Input and Output A 32 bit peripheral that attaches to the on chip peripheral bus Hardware Platform HDL IBA IDE EDK Concepts Tools and Techniques P N XTP013 v 9 1i Xilinx FPGA technology allows you to customize
32. Level Implementation XPS HDL VHDL Sim Model BEHAVIORAL Reference Files Log Files Synthesis Report Files Figure 3 2 Project Information Area Project Tab Project IP Catalog Project E m Software Projects WEJ dd Software Application Project F Default ppc405_0_bootloop 4 Y Project TestApp_Memory a F Project TestApp_Peripheral Compiler Options Informatio Applications Processor ppe405_0 Generated Header ppc405_O include xparameters h Executable C Data designs xps91 j12_isim qsqg Test4pp_Per Linker Script C Data designs xps91 j12_isim gsg T esty Mode EXECUTABLE Stack Size Heap Size Sources C Data designs xps91 jl 2_isim gsq T est4pp_Peripheral C Data designs xps91 j12_isim gsg T est4pp_Peripheral Headers Test4pp_Peripheral src gpio_header h Figure 3 3 Project Information Area Applications Tab 25 XILINX Chapter 3 Xilinx Platform Studio XPS The IP Catalog Tab The IP Catalog tab lists all the EDK IP cores and any custom IP cores you Project Information Area Project Applications IP Catalog created If a project is open only the IP cores Description IP Version IP Type compatible with the target Xilinx Analog device architecture are displayed The ime catalog lists information about the IP Bus Bridge cores including release version status Control 4 Communicatio
33. Platform Deb g koe rh ie ook eo oe A ho aR PRE E EEK a 74 Ov rvieW css 65 a bad r ieiet i ek e ee E A G RE EEE EE EREE 74 Hardware and Software Co Debug 6 66 eens 76 MestDnve ss c 2 c es eee wih ho woe Bag dokd a Gah Se Pes ae dae ede bah eae ge as 76 Run the Debug Configuration Wizard in XPS 1 ee ee eee 76 Review the Results 2 0 eee eee eect ene eee eeee II Generate the Bitstream in XPS and Observe Platform Debugging 78 Download the Bitstream and Run Debug in SDK 2 2 6 eee 78 Set Up ChipScop Prous seyss e tyst ee de idle di ade eevee Ea 78 Wayeform Window Setup sirati aaa Ea aa EAE E R EEEE AE A A EE 79 EDK Concepts Tools and Techniques www xilinx com 5 P N XTP013 v 9 1i X XILINX Platform Debug Hardware Triggering Control 0 2 usss s cece eee 81 Platform Debug Software Triggering Control 6 0 eee eee 82 Appendix A Embedded Submodule Design with ISE Why Would an Embedded Design Be a Submodule in ISE 85 What is Involved in Creating an Embedded Submodule Design 85 The Top Down Method Described 06 66 e cece eee 85 The Bottom Up Method Described 6 0 0 85 TESE DIVE aprds e m E Gens dp an aan beaeteadde tacesda uh dul eae hottie r E S 86 Adding an Embedded Submodule to ISE n on eee eee 86 Top Down Design Method sis ccc caw eee dee ee pa be E He de 86 Bottom Up Design Method ws saeco daa she pede ela
34. Tools and Techniques P N XTP013 v 9 1i www xilinx com 69 XILINX Chapter 8 Implementing and Downloading Your Design 4 Click Device Configuration gt Download Bitstream to download the combined hardware and software bitstream 5 After the bitstream is loaded to the board an output on your serial terminal window shows the testing status of the peripherals included in your design An output result from the shell test_ip peripheral you created earlier is included also Entering main Running GpioInputExample for Push_Buttons_Position GpioInputExample PASSED Read data 0x0 kkxkkxkxkxkxkxkxkkxkxkxkkkkkxkkkkkxk xkkkkk kxxk User Peripheral Self Test kkkkkkkkxkkkkkkxkkxkxkxkkxkxkkxkkxkkkxkx k RST MIR test write 0x0000000A to software reset register read 0x30220301 expected from module identification register RST MIR write read passed User logic slave module test write 1 to slave register 0 read 1 from register 0 slave register write read passed Packet FIFO test reset write packet FIFO to initial state reset read packet FIFO to initial state push data to write packet FIFO 0x00000000 0x00000001 0x00000002 0x00000003 write packet FIFO is not full number of entries is expected 4 pop data out from read packet FIFO 0x00000000 0x00000001 0x00000002 0x00000003 read packet FIFO is empty number of entries is expected 0 write read packet FIFO passed Int
35. and stimulus to this file Now that you have a general understanding of how the BFM project can be used and of its associated control files it s time to add the validated PCORE to the overall system Close the BFM project and reopen the original project XMP file Next you will add the new IP to the previously created embedded system Adding User IP to Your Processor System Not having generated any additional logic you haven t changed the peripheral top level interface This guide will treat the test_ip core as if additional user ports were added Why Because additional logic signals are more often than not required for use of the PCORE With the assumption that you have added user ports you should now re run the CIP Wizard in the import mode to re generate the correct EDK interface files MPD and PAO Doing this includes the newly added user ports and ensures that the test_ip peripheral can be used in XPS www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Create and Import Peripheral CIP Wizard XILINX iim Test Drive Before getting started let s do a quick review of where we are in the IP creation process The first time you ran the CIP wizard you created the test_ip peripheral set up the bus interface and generated template files for it Then if you opted to do so you ran BFM simulation to verify the basic design of your new peripheral Now you will add test_ip to your proje
36. ast could overwrite the other designer s work To avoid this situation XPS identifies the potential conflict and creates a stable file condition that can be used going forward Because SDK is the preferred software project manager XPS only needs to know the location of the ELF file so that it can be merged with the FPGA bitstream later on Notice that in the XPS Applications tab in addition to the software project you just worked on there are other projects Quickly confirm that the following are present in your project before taking the next Test Drive e The default ppc405_0_bootloop project The bootloop project boots the processor and sends it the jump to address command needed to find external memory The bootloop project should not be enabled to initialize BRAMs You re going to have the Project Test_App_Peripheral application take care of this e Projects created by the BSB Wizard including Project TestApp_Memory and Project TestApp Peripheral You may recall that in the BSB Wizard you chose to test both memory and other peripherals selected as part of the BSB process You ll perform the steps below to select and configure the software so it can be simulated or downloaded to the FPGA or board memory device 54 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Returning to XPS to Complete Your Project XILINX Test Drive In XPS select the Applications tab 2 Right click the Project
37. ation Wizard has done a lot of work for you It has made connections appropriate to your design which you can view in XPS and in your Microprocessor Hardware Specification MHS file 1 Select the Ports filter in the System Assembly Panel and notice the two new cores chipscope_opb_iba_0 and chipscope_icon_0 If you expand the ports associated with these cores you ll see that the Debug Configuration Wizard made the necessary connections for you These are illustrated in the figure below ICON Core chipscope_opb_iba JTAG Boundary Scan Signals iba_trig_out PPC DBGC405UNCONDDEBUGEVENT PPC C405DBGSTOPACK PPC C405DBGWBIAR 29 0 00 29 sys_clk_s X10588 Figure 9 4 Debug Configuration Wizard Automatic Connections 2 If you click the Projects tab and open the MHS file you will find that the wizard also added the chipscope_opb_iba statement PORT chipscope_icon_control chipscope_opb_iba_0_icon_control PORT OPB_Clk sys_clk_s PORT iba_trig_out ppc405_0_DBGC405UNCONDDEBUGEVENT_chipscope PORT iba_trig_in ppc405_0_C405DBGSTOPACK chipscope amp ppc405_0_C405DBGWBIAR_chipscope amp 0b00 Notice in Figure 9 4 and in the MHS code snippet above that the C40 5DBGSTOPACK along with the C405DBGWBIAR are trigger inputs iba_trig_in to the IBA core C405DBGWBIAR is considered the address of the current instruction because the instruction address continually advances by four as a result the last two bits of
38. automated the process for you Invariably however you will want to add some degree of customization to achieve your design goals But this doesn t mean the process has to become hopelessly complex and slow even when customizing a system XPS gives you the opportunity to automate many steps that would otherwise be error prone and time consuming That said adding some custom logic IP to your Test Drive system would be a good next step Let s get into some real design IP Creation Overview Processor Local Bus PLB On chip Peripheral Bus OPB If you think back to the XPS overview see in particular Figure 3 1 page 24 and Figure 3 5 page 27 the bus interface filter in the System Assembly Panel shows connections among busses processor and IP Any piece of IP you create must be compliant with the system that is in place To ensure compliance the following must occur 1 The interface required by your IP must be determined The bus to which your custom peripheral will attach must be identified For example a Processor Local Bus PLB The PLB provides a high speed interface between the processor and high performance peripherals b On chip Peripheral Bus OPB The OPB allows processor access to low speed low performance system resources For more information on these two primary processor busses along with other interconnects available refer to the PowerPC 405 Processor Block Reference Guide available at http www xilinx c
39. bedded processor system for a while e Are in the process of installing the Xilinx EDK tools e Would like a quick reference while designing a processor system Note This guide is written based on Windows operating system behavior Linux and Solaris behavior or graphical user interface GUI display may vary slightly im Take a Test Drive Because the best way to learn a software tool is to use it this document provides opportunities for you to work with Test Drive the tools under discussion Specifications for a sample project are given in the Test Drive sections and the reasons for their use are explained Information about what happens when you run automated functions is also described Test Drives are indicated by the car icon as indicated in the heading above Additional Documentation More detailed documentation on EDK is available on the Xilinx web page http www xilinx com ise embedded edk_docs html Documentation on the Xilinx Integrated Software Environment ISE is available on the Xilinx web page http www xilinx com support software_manuals htm EDK Concepts Tools and Techniques www xilinx com 11 P N XTP013 v 9 11 XILINX Chapter 1 Introduction How EDK Simplifies Embedded Processor Design Embedded systems are complex Getting the hardware and software portions of an embedded design to work are projects in themselves Merging the two design components so they function as one system create
40. c2 locn www xilinx com EDK Concepts Tools and Techniques P N XTPO13 v 9 1i Conventions Online Document The following conventions are used in this document lt XILINX Convention Meaning or Use Example See the section Additional Cross reference link to a Resources for details Blue text location in the current decument Refer to Title Formats in Chapter 1 for details ee Cross reference link to a See Figure 2 5 in the location in another document Virtex II Handbook Blue underlined text Hyperlink to a Website URL Go to http www xilinx com for the latest speed files EDK Concepts Tools and Techniques P N XTPO13 v 9 1i www xilinx com XILINX Preface About This Guide 10 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 1 Introduction Welcome The Xilinx Embedded Development Kit EDK is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx Field Programmable Gate Array FPGA device This guide describes the design flow for developing a custom embedded processing system using EDK Some background information is provided but the main focus is on the features of EDK and their use during the design process Read this document if you e Need an introduction to EDK and its utilities e Have not designed an em
41. cf located in the data subfolder of your XPS project The UCF contains a few basic timing constraints representing your selected processor reference clock frequency If you have selected a specific development board in BSB the UCF also contains a complete pinout specification for the on board peripherals you included in your design The UCF might also include I O constraints such as IOSTANDARD for some pins Copying BSB Generated Constraints into an Existing UCF If you already have a UCF source file added to your top level ISE project you can copy the BSB generated constraints into it If any embedded submodule ports referenced in the BSB generated constraints connect to top level ports of a different name you must edit the net names in the constraints accordingly Alternatively you can use the Constraints Editor available in ISE to import the pinout constraints from the BSB generated UCF into your ISE project constraints file This works only if all the embedded submodule ports referenced in the BSB generated pinout constraints connect to top level ports of the same name Re Using the BSB Generated UCF for Your Top Level Design If you do not already have a UCF for your top level design you can add a copy of the BSB generated UCF to use as a starting point Implementing an FPGA Design Containing an Embedded Submodule After you enter your embedded hardware platform design using XPS and your top level FPGA design and its ass
42. ct again using the CIP wizard In the process test_ip will be imported to an XPS appropriate directory and the Platform Format Specification files MPD and PAO will be generated For more information platform specification format files see the Platform Specification Format Reference Manual at http www xilinx com ise embedded edk_docs htm Running the CIP Wizard to Re import test_ip into Your XPS Project Open the CIP Wizard Hardware gt Create or Import Peripheral and click Next Value to Enter when in doubt select the default Wizard Screen value Peripheral Flow Select Import existing peripheral Repository or Project Select To an XPS project Name and version Select the test_ip option from the drop down list Enable the Use version checkbox and accept 1 00 a If the peripheral already exists a dialog pops up asking if you would like to overwrite it Click Yes Source File Types Indicate the types of files that make up the peripheral Enable the HDL source files checkbox HDL Source Files Use existing Peripheral Analysis Order file pao as the way to specify the HDL source files Browse to the test_ip_v1_00_a data test_ip_v1_1_0 pao file location open the file HDL Analysis Information This panel shows you all the dependent library files and HDL source files needed to compile your peripheral as well as corresponding logical libraries into which those files will be compiled Click the Add Files
43. d Il Hardware gt Generate Netlist MHS File system mhs EDIF IP Netlists TCE 4 Figure 8 1 Elements and Stages X10516 of Generating a Hardware Netlist For your general reference the resulting NGC files reside at lt project name gt hd1 implementation files Note that you don t need to change these XPS uses the NGC netlist files during design implementation which occurs when you invoke the Hardware gt Generate Bitstream menu command The figure below shows the bitstream generation stages EDIF IP Netlists NOC Hardware gt Generate Bitstream ISE XFlow Bit File bitstream bit X10583 Figure 8 2 Elements and Stages of Generating a Hardware Bitstream www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Netlist Generation Review XILINX The NGC files are processed along with the system constraints through the remaining Xilinx Integrated Software Environment ISE tools NGDBuild MAP PAR and TRACE when XPS invokes the XFlow command line program XFlow reads an input design file a flow file and an option file to generate the FPGA bitstream While you do not normally have to adjust the flow or the input design files you might wish to adjust the constraints file If you are not familiar with FPGA design the use of design constraints enables the tools to identify and satisfy real
44. ded System Tools Reference Manual available at http www xilinx com ise embedded edk_docs htm Bitstream Generation When you command XPS to generate the bitstream Platgen verifies the presence of an updated netlist On successful completion of the Platgen process the ISE implementation tools run from batch mode The ISE implementation tools read the netlist created and in conjunction with a user constraints file UCF they produce a BIT file containing your hardware design Software patterns if any are not included If you used the BSB Wizard to create your initial hardware platform it will have generated a UCF in the XPS project data folder For more information on the UCF and its implementation look for the XPS Help topic Procedures for Embedded Processor Design gt Adding Hardware Design Elements gt Implementing the Hardware Platform What s Next Now you can start to customize your design In the next chapter you ll add your own IP to the Test Drive project EDK Concepts Tools and Techniques www xilinx com 35 P N XTP013 v 9 1i XILINX Chapter 4 The Embedded Hardware Platform 36 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Creating Chapter 5 Your Own Intellectual Property IP So far it has been fairly easy to develop an embedded system using XPS Everything you have done up to this point has amounted to a series of mouse clicks because XPS has
45. ds the external memory and I O devices available on your predefined board and allows you to select the following as appropriate to a given device e Which devices to use e Baudrate bps e Peripheral type e Number of data bits e Parity e Whether or not to use interrupts For your convenience data sheets for external memory and I O devices can be opened from within the wizard Adding Internal Peripherals 18 BSB allows you to add additional peripherals of your choice There is a caveat the peripherals are supported by the selected board and FPGA device architecture For a custom board certain peripherals are available for general selection and automatic system connection www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Base System Builder BSB XILINX Setting Up Software Standard input and output devices can be specified in BSB and you can select sample C applications that you would like XPS to generate Each application includes a linker script The sample applications from which you can select include a memory test peripheral test or both Viewing a System Summary Page After you have made your selections in the wizard BSB displays a system summary page You can choose to generate the project or you can go back to any previous wizard dialog box and revise the settings d Test Drive Run the BSB Wizard to begin your Test Drive The wizard opens when you launch XPS Or if XPS i
46. e Note the ELF file location You ll need it for the test drive later in this chapter The C C Build configuration settings allow control over the type of project you are building For more information in SDK click Help gt Help Contents and navigate to C C Development User Guide gt Reference gt C C Project Properties gt Managed Make Projects gt C C Build gt Build Settings This concludes the work you need to do in SDK EDK Concepts Tools and Techniques www xilinx com 53 P N XTPO13 v 9 1i XILINX Chapter 6 The Software Platform and SDK Returning to XPS to Complete Your Project This guide takes your Test Drive system through simulation To set up for and to run simulation you ll need to return to XPS so we ll continue the test drive from there after providing a little background information Having completed some software development work using SDK you must specify a few things about project management in XPS e The application you wish use for BRAM initialization must be specified for use by the tools The Applications tab provides this capability e Working with Test_App_Peripheral XPS looks for potential project management conflicts It will find one in your Test Drive project because you are now using SDK to manage this software project A problem that could arise suppose two designers are working on this XPS project one using XPS and another using SDK The designer who saves the project l
47. e test n r 82 xil_printf write 1 to slave register O n r 83 TEST IP mriteSlaveRegO baseaddr 1 84 Reg 2Value TEST_IP_mReadSlaveRegO baseaddr 85 xil_printf read d from register O n r Reg32Value Figure 9 8 Setting a Software Breakpoint in SDK 3 Select the Breakpoints tab and look for a box with a check mark identifying the setting and location of the breakpoint Deselect the box as show in the figure below X Bo Cc Dataidesig riMyTestApp_Peripheralisrcitest_ip_selftest c line 84 Variables Registers XMD Console Memory Figure 9 9 Enabling Breakpoints in SDK Click the Resume icon f gt again to start program operation 5 Return to the ChipScope application and reset the M3 Trig3 TRIG_IN 1_XXXX_XXXX Activate the third trigger condition TriggerCondition2 Click the Apply the Settings and Arm Trigger toolbar icon to capture the hardware state The ChipScope analyzer then waits to upload the samples it is gathering 6 InSDK reset the breakpoint that was created in step 3 When this breakpoint is encountered ChipScope displays the hardware states preceding it 7 Note the low high transition that occurs on the C405DBGSTOPACK signal 82 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Platform Debug XILINX This concludes the hardware and software debug exercise as well as this version of the EDK Concepts Tools and Tec
48. ent board or FPGA to your host computer using an appropriate download cable run the Configure Device IMPACT process under the Generate Programming File group This downloads the combined hardware and software bitstream to your FPGA When finished the embedded processor in the FPGA begins executing your software program To modify your embedded processor design or to debug an application on your configured FPGA run the Manage Processor Design process in Project Navigator to reopen XPS with your embedded project loaded EDK Concepts Tools and Techniques www xilinx com 89 P N XTPO13 v 9 1i XILINX Appendix A Embedded Submodule Design with ISE 90 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Appendix B More About BFM Simulation When you took the Bus Functional Model BFM Simulation Test Drive in Chapter 5 Creating Your Own Intellectual Property IP you were asked to click User Command Button 1 The tools then ran through several make file scripts which resulted in the simulation shown in Figure 5 6 page 45 This appendix provides a more detailed look at what happened as well as information on how you can modify the routines for your own purposes Use a file explorer tool and navigate to the lt project_name gt pcores test_ip_v1_00_a devl bfmsim scripts directory shown in the figure below Here you ll find a few scripts with which you should become familiar if you
49. errupt controller test IP user logic interrupt status 0x00000000 clear IP user logic interrupt status register Device peripheral interrupt status 0x00000000 clear Device peripheral interrupt status register enable all possible interrupt s write read interrupt register passed Exiting main 70 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 9 Debugging the Design So far the test drive system we are designing has been fairly simple As additional IP elements are added and more software is written however the system inevitably becomes more complex In addition because the system elements are encapsulated inside the FPGA and because the signals necessary for sufficient design analysis are inaccessible debug could potentially become a challenge But Xilinx has anticipated these difficulties and offers several methods and tools that allow you good visibility into both the hardware and software portions of your design e Hardware debug capability using the Xilinx Microprocessor Debugger XMD e Platform Studio Software Development Kit SDK software debugger communicates to the target processor through the XMD interface e The ChipScope Pro tool which uses integrated logic analyzer hardware cores to communicate with the target design inside most Xilinx devices The Xilinx debug capabilities associated with Platform Studio tend to see the grea
50. ettings You can choose between either Basic or Advanced debug control features The Console Window As shown by callout number 3 in Figure 9 3 the Console Window displays output warning error and information messages from the Debug Configuration wizard Basic Advanced Virtual input Signal to monitor Virtual output Signal to control Push_Buttons_Position_GPIO2_in_to_c K Notes Add ChipScope Peripheral Delete ChipScope Peripheral Information Available Ports on Instance Virtual IOs help you debug the system in the same way as LEDs push buttons and switches except that they are virtual Select the signals that you want to monitor virtual input and or control virtual output ppe405_0 APUFCMDECODED APUFCMDECUDI APUFCMDECUDIVALID APUFCMENDIAN si lt Add Remove Available Ports on Instance ppe405_0 v Add BRAMDSOCMCLK Connected to sy BRAMDSOCMRDDBUS BRAMISOCMCLK Connected to sys BRAMISOCMDCRRDDBUS lt i i Remove gt a iN For each IP instance only its output ports can be monitored and only its input ports can be controlled Number of BRAMs being used 8 Figure 9 3 Debug Configuration Wizard EDK Concepts Tools and Techniques P N XTPO13 v 9 1i www xilinx com 75 XILINX 76 Chapter 9 Debugging the Design Hardware and Software Co Debug The Debug Configu
51. everal utilities that are integrated into a single application e ChipScope Pro Analyzer provides device configuration trigger setup and trace display for ChipScope Pro cores e ChipScope Pro Cores hardware debugging is accomplished through bus and arbitrary signal value monitoring along with discrete control of inputs and output using the JTAG connection The available cores include Integrated Controller Pro ICON Provides a communication path between the JTAG port of the target FPGA and up to 15 other cores IBA VIO ATC2 or MTC2 Integrated Logic Analyzer ILA A customizable logic analyzer core that monitors any internal signal in your design Integrated Bus Analyzer IBA A specialized logic analyzer core designed to debug embedded systems that contain IBM CoreConnect bus interconnects either On Chip Peripheral Bus OPB or Processor Local Bus PLB Virtual Input Output VIO A core that can both monitor and drive internal FPGA signals in real time Agilent Trace Core 2 ATC2 A debug capture core specifically designed to work with the latest generation Agilent logic analyzers This core provides external logic analyzer access to an internal FPGA net For more detailed information about features benefits and core description associated with ChipScope Pro Tools see the ChipScope Pro Software and Cores User Guide available at http www xilinx com literature literature chipscope htm Platform Debug Used i
52. ew the signals that are present outside the FPGA device Note the names of the signals in the Net column and find the signals related to the RS232_Uart You may need to drag the right side of the Net column header to see its entire contents These are referenced in the next step Collapse this category when finished Find the RS232_Uart peripheral and expand it Note the Net names and how they correspond to the names that were present as external signals The RX and TX net from the UART are name associated with the external ports Double click the RS232_Uart peripheral icon to launch the RS232_Uart opb_uartlite_v1_00_b parameters dialog box You can use the parameters dialog box for any peripheral to adjust various settings available for the IP Take a moment and observe what happens when you hover the cursor over a parameter name Note the three top buttons and the tabs available for this core Close this box when finished Click the directories icon circled in Figure 3 5 and switch between the hierarchical and flat views The Platform Studio Tab In the same space as the System Assembly Panel there is a tab labeled Platform Studio The Platform Studio tab display shown in the figure below provides an embedded design flow diagram with links to related help topics If at any point you are not sure what to do next or need more information on how to perform a process you can refer to this diagram for a quick update 28 www x
53. ftest c 10 ffffc3d4 xil printf Reg32Value if Reg32Value xil_printt xil_printt else xil_printt xil_printt return XST_F write Ox306x to software reset register n r IPIF_RESET TEST IP mReadMIR baseaddr 0x30220301 read Ox 08x expected from module identification regist RST MIR write read passed n n r read Ox 08x unexpected from module identification regi RST MIR write read failed n n r AILURE Figure 7 2 test_ip_selftest c Resetting the test_ip Peripheral Use a text editor to open the TestApp_Peripheral dis file and search for the same line of code TEST_IP_mReadMIR baseaddr There you ll find assembly code that appears similar to the following actual address values may vary Reg32Value TEST_IP_mReadMIR baseaddr C C Source Code ffffc3d8 48 00 if Reg32Value 0x30220301 C C Source Code ffffc3dc ffffc3e0 60 00 Memory Address Machine for Code Execution Execution 7f a3 eb 78 mr 43 29 3c 00 30 22 lis 4r0 12322 12 3d bl ffffd614 lt XIo_In32 gt 03 oT ori r4r0 r0 769 Code Assembly Operands Values 11 In your simulator perform a signal search on FFFC3D4 or the value applicable to your design Using the PowerPC Internal Register exeaddr signal name for the FFFFC3D4 12 value allows you to zoom in on a location at which to begin looking for proper reset operation of the test_ip peripheral in the s
54. fying the simulation launch and compilation process to a single button click How Can Modify IP Created with the CIP Wizard The next logical question is how to make future adjustments given that you will not be developing IP blocks without additional logic for very long So let s try making some alterations to your test IP pE Test Drive 2 In XPS select File gt Open navigate to the lt project name gt pcores test_ip_v1_00_a devl bfmsim scripts directory and display all files Open the sample bf1 file Roughly the first 140 or so lines of code set command aliases making the command lines more human readable Source and destination memory is populated and the various core features are tested You can add or subtract commands to various sections as your core requires or create a completely new BFL command file Note f you create a new BFL file you must adjust the bfm_sim_xps make file under the bfmsim directory to reflect your desired command file For more information on the BFL commands look in your EDK install area for the file XILINX_EDK third_party doc xxxToolkit pdf where xxx corresponds to a desired bus In addition to the BFL file the CIP Wizard creates a corresponding PCORES directory under the BFMSIM project Here you ll find a template for the BFM testbench You can add to the template testbench as your core logic requires This guide doesn t go into description on how to add testbench signals
55. g 5 z EXO Bus Interface Ports Addresses B Fiters Applied Ee Name Bus Connection IP Type iP Version Description IP Version Drob plb_v34 1 02a Analg D ond opb_v20 1 10 c Arithenetic E tagope_crtr 2 00 a Bus lt resat_biock proc_sys reset 1 00 a Bus Bridge Dim cnt isbeam_f_cnth 3 00 b Clock Control socm_dran bram_block 1 00 4 Cornenunecation High Speed D ocem ent dsbeam_f_cnth 3 00 b Coenenurrcstion Low Speed D dsocm_ biam bram_block 1 00 4 Qi OPS IIC Interface D pb2Z0p6 plb2opb_bidge 1 01 a OPB SPI Intertace AS232_Van opb_uartite 1 00 b OPE LAAT 16550 style SOFB System Assembly IPB UART Lte Connectivity Panel 7 Panel E PIR LART MARANehdel 1 Me i O om ata re eee eee Legend Master O Slave Master Slave Target lt Initiator O Connected Unconnected Platform Studio ih System Assembly View Block Diagram Deba Project Information MA ve Panel Generating Block Diagram C Data designs xps91 j17 test_drive blkdiagram system html Generated system svg Block diaqram qenerated lt Console Panel Oupt Wamng Eror Figure 3 1 Xilinx Platform Studio GUI The Project Information Panel The Project Information panel offers control over and information about your project The Project Information panel provides Project Applications and IP Catalog tabs 24 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The XPS GUI EDK Concepts Tool
56. gures libraries device drivers file systems and interrupt handlers for the embedded processor system creating a software platform Click Software gt Generate Libraries and BSPs to start Libgen Xilinx Platform Studio Software Development Kit SDK is a complementary interface to XPS and provides a development environment for software application projects To open SDK click Software gt Launch Platform Studio SDK For your convenience SDK has its own user interface which expedites software design tasks im Test Drive Take a look at the options available under the Hardware Software and Simulation menu items XPS Directory Structure The BSB has automated the project directory structure setup and started what can be considered a simple but complete project The time savings that BSB provides during platform configuration can be negated however if you don t understand what the tools are doing behind the scenes Let s take a look at the directory structure that was created and see how it could be useful as project development progresses 30 Directories BSB creates four primary directories automatically These are shown in Figure 3 7 xps Contains intermediate files generated by XPS and other tools for internal project management You will not use this directory data Contains the user constraints file UCF For more information on this file and how to use it see the ISE UCF help topics at http www xilinx com suppo
57. he BSB Wizard you can create your project file choose a board select and configure a processor and I O interfaces add internal peripherals set up software and generate a system summary report BSB recognizes the system components and configurations as you build it and provides the options appropriate to your selections Creating Your Top level Project File xmp File File creation includes the option to apply settings from another project you have created with the BSB A Xilinx Microprocessor Project XMP file is the top level file description of the embedded system under development All XPS project information is saved in the XMP file including The Xilinx the location of the Microprocessor Hardware Specification MHS and Microprocessor Microprocessor Software Specification MSS files The MHS and MSS files are described in detail later Project xmp file i E i The XMP file also contains information about C source and header files that XPS is to compile as well as any executable files that the Software Development Kit SDK compiles The project also includes the FPGA architecture family and the device type for which the hardware tool flow must be run EDK Concepts Tools and Techniques www xilinx com 17 P N XTP013 v 9 1i X XILINX Chapter 2 Creating a New Project Selecting a Board Type Base System Builder BSB BSB allows you to select a board type from a list or to create a custom board Suppo
58. he Bus Interface and IPIF Services Panels the CIP Wizard asked you to define the target bus and what services the IP would need The purpose here was to determine the IPIF elements your IP would require The IPIF is a verified optimized and highly parameterizeable interface It also gives youa set of simplified bus protocols This is called IP Interconnect IPIC which is much easier to work with when compared to operating on the OPB or PLB bus protocol directly Using the IPIF module with parameterization that suits your needs greatly reduces your design and test effort because you don t have to re invent the wheel The figure below illustrates the relationship between the bus IPIF IPIC and your user logic B aan a Master i tiach ent BasCoreHW Eus Attachment i O independent 3 f Layer Figure 5 1 Using the IPIF Module in Your Custom Peripheral Now to draw the parallels between what the wizard created and the boxes in the figure above The CIP Wizard created two template files that assist in IP connection The top level file is given the name you entered test_ip vhd The second file user_logic wvhd is where your custom logic is to be connected www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Create and Import Peripheral CIP Wizard XILINX A review of the directory structure and files that were created by the wizard reveals where the above mentioned and other
59. hich it saved the XPS BFM simulation project called bfm_system xmp EDK Concepts Tools and Techniques www xilinx com 43 P N XTPO13 v 9 1i XILINX Chapter 5 Creating Your Own Intellectual Property IP Open the project from XPS What you see will be similar to what is shown in the figure below Xilinx Platform Studio C Data designs xps82_test gsg pcores test_sp1_v1_00_a devl bimsim bim _system xmp S te i 10 xj File Edit view Project Hardware Software Device Configuration Debug Simulation Window Help 18 x 0e Bli m mio a y BE mM le ell a Sila AR Allana A las g l z x Filters Project Applications IP Catalog Bus Interface Ports Addresses Er Connection Filters Name Bus Connection _ IP Type E Project Files GI opb_bus opb_v20 1 10 c MHS File bfm_system mhs A bim_processor opb_device_bfm 1 00 a MSS File bfm_system mss em MSOPB opb_bus UCF File data bfm_system ucf ES bim_memory opb_device_bfm 1 00 4 iMPACT Command File etc download cmd i MSOPB opb_bus Implementation Options File etc fast_runtime opt bim_monitor opb_monitor_bfm 1 00 4 A Bitgen Options File etc bitgen ut i MON_OPB opb_bus Project Options A my_core test_sp1_tb 1 00 4 pe Device xc2vp4fg456 6 SOPB opb_bus Netlist TopLevel synch_bus bfm_synch 1 00 a Implementation XPS Sim Model BEHAVIORAL
60. hniques guide We hope you have found this guide useful as you progressed from the beginning stages of XPS project development through simulation device download and finally into both hardware and software debug EDK Concepts Tools and Techniques www xilinx com 83 P N XTPO13 v 9 1i XILINX Chapter 9 Debugging the Design 84 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i gt XILINX Appendix A Embedded Submodule Design with ISE Why Would an Embedded Design Be a Submodule in ISE The situations in which you would use the Xilinx Integrated Software Environment ISE Project Navigator to implement your FPGA design with your embedded processor system as a submodule within the top level FPGA design source are e Your FPGA design comprises a combination of an embedded processor system and other custom logic in which case you must use Project Navigator to develop the custom logic portion of your design and to implement the top level FPGA design e Your FPGA design comprises an embedded processor system and you elect to use Project Navigator for implementation Project Navigator gives you access to other tools provided by ISE such as constraint editors What is Involved in Creating an Embedded Submodule Design The methods for using the XPS and ISE tools to process your embedded submodule design are called top down and bottom up Both allow you access to the same set of to
61. ick the Open Cable Search JTAG Chain icon circled in the figure below 78 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Platform Debug ChipScope CDC file 2 XILINX Ret ChipScope Pro Analyzer ne File View JTAG Chain New Project JTAG Chain Figure 9 5 Open Cable Search JTAG Chain Icon A dialog box appears asking you to select the device you wish to monitor Select the FPGA device containing the test drive design Assuming you are using the ML403 board this is the XC4FX12 The File gt Import menu option launches the Signal Import dialog box Click the Select New File button and browse to your lt project directory gt implementation chipscope_opb_iba_0_wrapper directory location Here you will find a CDC file called cs_coregen_chipscope_opb_iba_0 cdc Open this in the ChipScope Logic Analyzer Waveform Window Setup The ChipScope Logic Analyzer contains four main windows labeled New Project Signals DEV 2 Unit 0 Trigger Setup and Waveform In the following steps you will work in the Waveform window 1 Inthe Waveform window select the first signal and using the shift key select the last signal in the list to highlight all signals Right click and select the Remove from Viewer option 2 Drag the OPB_ABUS signal from the Signals pane to the Waveform pane Do the same with the OPB_DBUS and TRIG_IN signals Right click the TRIG_IN bus and rename it C40 5DBGWBIAR Double click on this
62. ign keep the following points in mind e You must ensure certain system values are specified e Itis advantageous to change some settings to improve the simulation runtime Global Settings to Specify Global reset tristate nets and clock signals all must be set to some value Xilinx Integrated Software Environment ISE tools provide detailed information on how to simulate your VHDL or Verilog design Refer to the Simulating Your Design chapter in the ISE Synthesis and Verification Design Guide for more information A PDF version of this 58 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Helper Scripts X XILINX document is located at http www xilinx com support sw_manuals xilinx9 index htm System Behavior and Improving Simulation Times You should also be aware of system behavior HDL simulation is slow when compared with a design running on hardware To improve the simulation runtime you can adjust some parameters for simulation only purposes For example our Test Drive system contains an RS232_UART In the Test Drive section of this chapter you ll see how to improve simulation time by increasing the baud rate for this peripheral Helper Scripts Restrictions Xilinx has put a good deal of effort into making system simulation easier to perform The tools understand how your system is connected and how all the HDL design files relate behind the scenes The tools also have the abilit
63. ilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The XPS GUI XILINX Select desired text for more information gt Documentation Examples Tech Tips Starting your project O N Software Development Hardware Development Configuring and generating the Begin by using the Base System Builder software platform i Creating custom peripherals Developing your software applications Populating and connecting your Using XPS Lo hardware design Debugging using XMD and GDB implementing your hardware platform Profiling Simulating your embedded sub system Using SDK Debugging hardware using ChipScope Pro XY A l Generating the hardware bitstream Downloading the complete system bitstream Initializing FPGA on chip memory with embedded software gt Writing embedded software to a flash PROM aa optional advanced topics Figure 3 6 Platform Studio Startup Flow Diagram im Test Drive Note If you can t see the Platform Studio tab click Help gt View Startup Flow Diagram e With the Platform Studio tab selected try clicking the Software Development Hardware Development and FPGA Device Configuration headings You may find it interesting to read the help topics overviews for these parts of the design flow e Try clicking the Hardware Development topic Begin by using the Base System Builder Th
64. imulation Zoom in on this location in the simulation You will notice there is a bus transition on the s1_dbus The value present on the s1_dbus signal should be 0x30220301 which is what the software expects as shown in the figure below 62 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Restrictions XILINX FE_OFFFFDe14 E OD LJ J IFASEB7S 44 A 14E 800020 10 A0 l 410 JI J0 FF JFFFFCS3D8 FF JFFFFD BIC 10 J00000000 CFF J IFFFFC3D4 JO 130220000 AA J IFFFFC3D4 10000323 1 A 100007857 mi m ee ee Value appears here a Figure 7 3 Simulation Output Results for test_ip Armed with the disassembled source and the simulation waveform output you ll be better able to continue stepping through the design and better able to understand its internal operation as well as the hardware and software interaction EDK Concepts Tools and Techniques www xilinx com P N XTP013 v 9 11 63 XILINX Chapter 7 Introduction to Simulation in XPS 64 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 8 Implementing and Downloading Your Design Implementing the Design Having completed the design entry phase you can now implement your design in hardware We touched on this subject in Chapter 4 The Embedded Hardware Platform and as part of the earlier test drives you ge
65. ion add a while 1 statement to your TestApp_Peripheral application so the function runs continuously a Open the TestApp_Peripheral c file b Inthe file look for the int main void statement on line 45 c Add the following code to the file shown in bold type int main void while 1 print Entering main r n d Locate the print Exiting main r n statement near the end of the file e Add the closing bracket as follows print Exiting main r n return 0 f Save your file Download the Bitstream and Run Debug in SDK Note You must have a board connected to perform the following steps 1 InSDK select Device Configuration gt Program Hardware to download the bitstream 2 Ensure that your TestApp_Peripheral project is selected From the Run menu select the Debug option This launches the Debug Configuration dialog box 3 Click the New button at the bottom of the dialog box TestApp_Peripheral is automatically populated for the project type and the C C application can be found at Debug TestApp_Peripheral elf 4 Select the Debug button at the bottom of the dialog box to download the design to the board and switch to the Debug Perspective 5 Inthe Debug Perspective click on the Resume icon jj and observe the output in the serial terminal window The software routine runs in a continuous loop Set Up ChipScope Pro 1 Launch ChipScope Pro Analyzer 2 Cl
66. ion behavioral directory structure Use a file browser to locate and view the contents of the behavioral directory Here you find two primary file types DO files and VHDL files a Open the system vhd file in a text editor This is your top level file for the device under test It contains all the signals and port mappings that comprise the design you are working with at this point Scan through and familiarize yourself with the content of this file When finished close the file b Open the system_setup do file This macro file automates many of the steps executed during simulation You see the results of this file after completing just a few steps Note that the alias commands call additional Do files You could add your own aliases to this file as well for custom simulation operations Note the w alias for calling the do system_wave do file You will be asked to edit this file next When finished with system_setup do close this file and open system_wave do next c The system_wave do file displays the signals in your design Many signals are generated by this file To provide a little more focus for our simulation comment out using the pound sign the following lines of code HE do iocm_wave do do docm_wave do do plb_wave do do plb2opb_wave do do ppc405_0_wave do do reset_block_wave do do isocm_bram_wave do do dsocm_bram_wave do do plb_bram_if_cntlr_1_ bram_wave do do sram_256kx32_util_bus_split_0_wave do do dcm_0_
67. is presents material with which you might now be familiar after reading Chapter 2 Creating a New Project The Console Panel The Console panel shown in Figure 3 1 page 24 provides feedback from the tools invoked during runtime Notice the three tabs Output Warning and Error EDK Concepts Tools and Techniques www xilinx com 29 P N XTPO13 v 9 1i XILINX XPS Tools Chapter 3 Xilinx Platform Studio XPS In addition to the GUI XPS includes all the underlying tools needed to develop the hardware and software components of an embedded processor system These include Base System Builder BSB Wizard for creating new projects The BSB dialog box that appears on XPS start up is also available from the toolbar Click File gt New Project Hardware Platform Generation tool Platgen for generating the embedded processor system To start Platgen click Hardware gt Generate Netlist Simulation Model Generation tool Simgen generates simulation models of your embedded hardware system based either on your original embedded hardware design behavioral or finished FPGA implementation timing accurate Click Simulation gt Generate Simulation HDL Files to start Simgen Create and Import Peripheral Wizard helps you create your own peripherals and import them into EDK compliant repositories or XPS projects To start the wizard click Hardware gt Create or Import Peripheral Library Generation tool Libgen confi
68. key files reside See the pcores directory in your example project directory shown in the figure below S O test_ip_v1_00_a O data E test_ip_v2_1_O mpd E test_ip_v2_1_0 pao _ gt S O devl E O bfmsim Optional a O projnav _ Bitest_ip isce ISE project fle D synthesis a hdl O vhdl iltest_p vhd gt _Toplevel VHDL template uujuser_logic vhd User logic VHDL template EDK Interface Files Figure 5 2 Directory Structure Generated by the CIP Wizard Our attention will now focus on the two VHDL template files created by the wizard test_ip vhd and user_logic vhd shown in the figure above The user_logic file makes the connection to the OPB bus via the IPIF core configured in test_ip vhd The user_logic vhd file is equivalent to the Custom Functionality block and the test_ip vhd file is equivalent to the IPIF block both blocks are shown in Figure 5 1 page 40 EDK Concepts Tools and Techniques www xilinx com 41 P N XTP013 v 9 1i X XILINX 42 Chapter 5 Creating Your Own Intellectual Property IP In this Test Drive example the user_logic vhd block diagram appears as shown in the figure below The IPIF core connection to the OPB bus is made in test_ip vhd and shown in the figure below What is still lacking from both files is your proprietary logic Bus2IP_Data Bus2IP_BE Bus2IP_RdCE Bus2IP_WrCE Bus2 IP_Clk Bus2IP_Reset user_logic vhd FIFO Signals IP2Bus_Data
69. l life support or weapons systems High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2007 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners EDK Concepts Tools and Techniques www xilinx com P N XTPO13 v 9 1i Table of Contents Preface About This Guide Additional Resources 00 cece cece cece cnn e nee ene eeneneeee 7 CONVETIEIONS eere euere eean eR david be baed hed bb Fare bE ow dade when bu pai 8 Bag 03 072462 0 0 6 Opec rer ear cea Term De aE RC ee a e 8 Online Documentos e oh0 b end ek de ewe Gs VA Ga Ste WP ek a ek edb es 9 Chapter 1 Introduction Welcome oi ci2i200sss0kehen sesso bigeadenages be eaa eaaa peeled aiaa iaa 11 Take a Test Diye ac aetia neinean e ral dugg orden bode al obs WEG Ea ia ye baal ant tend 11 Additional Documentation 0 0 00 cece ce cence ene een EEEN 11 How EDK Simplifies Embedded Processor Design 12 The Integrated Software Environment ISE 000 e cee eee eee eee 12 The Embedded Development Kit EDK 0 0 0 c cece eee eee eee 12 How Do the Tools Expedite the Design Process
70. lect Import XPS Application Projects and click Next Note For future reference notice that you could also choose to create a new SDK application Application Wizard Select a Wizard Inport an XPS Application Project using source fie inks not copies and transfer come er Import XPS Application Projects to SDK Ei impet an Existing SOK AOC The creates Fh for source ies and imports the compte The following sppication projects are avadable in XPS Design C Dataldesigns yps82_testlasglsystem xmp Appication Project Name Processor I TestApp_Memory pectos_0 M Testapp Peripheral pect0s_0 Figure 6 2 Platform Studio SDK Project Creation Wizard 3 The projects available in XPS are listed with check boxes for importation Select TestApp Peripheral and click Finish EDK Concepts Tools and Techniques www xilinx com 51 P N XTPO13 v 9 1i 1 2 Even though you will use default software platform settings for this example project click Software gt Software Platform Settings It s a good idea to acquaint yourself with the options available here Note the processor parameters on the Software Platform page This is where you can set extra compiler flags if needed On the OS and Libraries page you can specify your stdin and stdout peripherals When you re ready select Cancel to exit from the dialog box Next you must generate the BSP Click Software gt Generate Libraries and BSPs When you do this XPS invokes the library genera
71. m Studio XPS Using XPS you will be able to build on the project you created with BSB This chapter takes you on a tour of XPS Subsequent chapters in the document discuss how to use XPS to modify your design Note Taking the tour of XPS provided in this chapter is recommended It will enable you to more easily follow the rest of this book and other documentation on XPS XPS includes a graphical user interface GUI along with a set of tools that aid in project design This chapter describes the XPS GUI and some of the most commonly implemented tools From the XPS GUI you can design a complete embedded processor system for implementation within a Xilinx FPGA device The XPS main window is shown in the figure below Note that the XPS main window is divided into three areas e The Project Information Panel e The System Assembly Panel e The Console Panel Optional test drives are provided in this chapter so you can explore the information and tools available in each of the XPS main window areas EDK Concepts Tools and Techniques www xilinx com 23 P N XTPO13 v 9 1i XILINX Chapter 3 Xilinx Platform Studio XPS Xilinx Platform Studio C Data designs xps91 j17 test_drive system np System Assembly View1 I File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help OPES 2 20EH BP AN BK we WR it te DHOBHD Piqect information Area 5 Fikers Project Applications IP Catalo
72. mulation Note If either of the two conditions below is not met skip this step Select an EDK capable simulator ModelSim PE SE or NCSim e You must have the BFM toolkit installed or you won t be able to select the BFM checkbox e You must have ModelSim or NCSim installed Peripheral Implementation Support Peripheral implementation support Use defaults Finish Create Peripheral Finish Review the details contained in the wizard screen text box Note the interrupt address range given Click Finish Note For additional information about the Create and Import Peripheral Wizards see the XPS help system topic set at Procedures for Embedded Processor Design gt Creating and Importing Peripherals The Xilinx web provides IP interface documentation at http www xilinx com ise embedded edk_ip htm EDK Concepts Tools and Techniques P N XTPO13 v 9 1i www xilinx com 39 2 XILINX Chapter 5 Creating Your Own Intellectual Property IP What Just Happened The wizard worked But you re probably not sure what it really produced Let s stop for a moment and examine some concepts and the resulting output Intellectual Property Interface IPIF Intellectual Property Interface IPIF Library amp IP Interconnect IPIC 40 EDK uses what is called an Intellectual Property Interface IPIF library to implement common functionality among various processor peripherals In t
73. n High S peer active early access or deprecated ae Communication Low Speed lock not licensed locked or 2 OFB IIC Interface 1 02 a opb_ic unlocked processor support and a OPB SPI Interface 1 00e opb_spi short description a OPB UART 16550 style 1 00 d opb_uartl6550 OPB UART Lite 1 00 b opb_uartite Additional details about the IP core PLB UART 16550 style 1 00 c plb_uart16550 including the version change history aoe E data sheet and Microprocessor General Purpose 10 Z Peripheral Description MPD file are K3 i gt available in the right click menu Figure 3 4 Project Information Area By default the IP cores are grouped IP Catalog Tab hierarchically by function im Test Drive e Click the Project tab Notice that right clicking a project file lets you open it in XPS and that a right click on an item under Project Options allows you to open the Project Options dialog box e Click the Applications tab Collapse the Project TestApp_Memory using the box Expand the four sub headers below Project TestApp_Peripheral Under Processor ppc405_0 note the xparameters h file which will be referenced later in this guide The xparameters h file contains the system address map and is an integral part of the Board Support Package BSP If you have been following the previous test drive steps the BSP has not been generated yet so this file is unavailable Under Compiler Options and Sources n
74. nction with other utilities such as the XPS GUI Typically XMD connects to the target processor through a JTAG connection to the device under test Communication and control are achieved using the TCP IP protocol In the images above depending on the microprocessor you have selected PowerPC or MicroBlaze and on how you configured the system XMD passes information from the device under test to the GUI SDK about its status XMD also controls the operation of the processor based on the requests you entered in SDK For more information about XMD refer to the XMD chapter of the Embedded System Tools Reference Manual available at http www xilinx com ise embedded edk_docs htm Software Development Kit SDK Software Debugger Platform Studio SDK presents an integrated environment for seamlessly debugging embedded targets Both MicroBlaze and PowerPC Executable and Linkable Format ELF files can be debugged with SDK Software debuggers such as the one provided in SDK enable you to monitor the execution of a program by controlling it through start stop and pause breakpoint operations The software debugger may also allow some run time control over the program s operation through monitoring and adjustment capabilities of the memory and or variable values EDK Concepts Tools and Techniques www xilinx com 73 P N XTPO13 v 9 1i X XILINX Chapter 9 Debugging the Design ChipScope Pro Tools ChipScope Pro tools include s
75. ndividually you can see that the utilities described in the last several sections of this chapter are certainly helpful When combined however these tools provide an even greater advantage they give you a simultaneous and complete picture of both the hardware and software interactions within your embedded design This ability is crucial to isolating the source of a bug 74 Overview The Platform Studio Debug Configuration Wizard in XPS automates hardware and software debug configuration tasks common to most designs To open the Debug Configuration Wizard select Debug gt Debug Configuration The wizard has the following primary viewing panes e The System Explorer On the left side of the wizard main window as shown by callout number 1 in Figure 9 3 are options that allow you to select the debug utility that you would like to configure Use these options to navigate through and configure debug features for the available ChipScope cores and processors www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Platform Debug XILINX Debug Configuration System Monitor Hardware Signals chipscope_ila_0 chipscope_opb_iba_0 chipscope_plb_iba_0 scope_vio_0 RK Debug Software Application ppc405_0 A Miscellaneous JTAG UART The Configuration Pane As shown by callout number 2 in Figure 9 3 the Configuration Panel contains information about desired operations as well as selected core s
76. nerated your hardware netlist see Simulation Setup page 59 Asa result XPS did most of the essential work required for implementation To take the design from concept to reality you must perform a few additional steps This chapter provides information on what the tools have automated and on how to adjust those settings to suit your final design needs Netlist Generation Review The MPD file contains all available ports and hardware parameters for a peripheral Earlier you were prompted to select the Hardware gt Generate Netlist menu item This command causes the XPS Platform Generator Platgen utility to read the design platform information contained in the Microprocessor Hardware Specification MHS file along with the IP attribute settings available from the respective Microprocessor Peripheral Definition MPD files The output files from Platgen are Hardware Description Language HDL files which can be found at lt project name gt hdl lt hd1 lang gt More information on the MPD file can be found in the Platform Specification Format Reference Manual available at http www xilinx com ise embedded edk_docs htm Xilinx Synthesis Technology XST synthesizes these HDL design files to produce IP netlist NGC files as shown in the figure below EDK Concepts Tools and Techniques www xilinx com 65 P N XTPO13 v 9 1i X XILINX 66 Chapter 8 Implementing and Downloading Your Design System IP ll mp
77. nstraints file The NGC file is a netlist file that contains both logical design data and constraints This file replaces both EDIF and NCF files Native Generic Database file The NGD file is a netlist file that represents the entire design A Xilinx specific format binary file containing a logical description of the design in terms of its original components and hierarchy Xilinx Integrated Software Environment ISE Project Navigator project file On Chip Memory On chip Peripheral Bus Pinout and Area Constraints Editor Peripheral Analyze Order file The PAO file defines the ordered list of HDL files needed for synthesis and simulation Processor Block Diagram file www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Platgen PLB PROM PSF SDF file SDK Simgen X XILINX Hardware Platform Generator sub component of the Platform Studio technology Processor Local Bus Programmable ROM Platform Specification Format The specification for the set of data files that drive the EDK tools Standard Data Format file A data format that uses fields of fixed length to transfer data between multiple programs Software Development Kit The Simulation Generator sub component of the Platform Studio technology Software Platform SPI A software platform is a collection of software drivers and optionally the operating system on which to build your application Because
78. o enable visibility into the operation of test_ip adjust the trigger setting of Trigl OPB_ABUS to 5000_01Xx the point at which a request is made of the test_ip software reset register see test_ip h Adjust the trigger position value so it appears late in the sampling window say 500 samples into it This captures a large number of samples before the trigger condition occurs allowing you to see what the processor system status was EDK Concepts Tools and Techniques www xilinx com 81 P N XTPO13 v 9 1i XILINX Chapter 9 Debugging the Design 3 Setthe TriggerCondition0O Output Enableto Pulse high As described earlier in Figure 9 4 page 77 when the trigger condition is encountered the DBGC4 0 5UNCONDDEBUGEVENT signal is pulsed high which stops the processor 4 Use the Apply the Settings and Arm Trigger toolbar icon p to capture the hardware state 5 In SDK click the Resume icon jj and observe where the software stops Platform Debug Software Triggering Control 1 InSDK open the test_ip_selftest c file and find the TEST_IP_mReadSlaveReg0 function call Software execution should be stopped close to this point 2 Double click the margin between the test_ip_selftest c frame boundary and the line number to set a breakpoint See the line of code circled in the figure below 78 79 Write to user logic slave module register s and read back 80 wf 61 xil_printf User logic slave modul
79. ociated UCF using Project Navigator you are ready to implement your complete FPGA hardware design In Project Navigator 1 Select your top level design module in the Sources for Synthesis implementation pane 2 Run the Synthesize process to Synthesize the embedded submodule netlist if you have not already done so Note Xilinx recommends running the Generate Netlist command in XPS to synthesize your embedded submodule design In so doing you can address any problems found in the embedded system before exiting XPS Synthesize the top level design and any other custom logic submodules in your design 3 Run the Implement Design process This runs place and route for your targeted FPGA At this point you can perform design timing analysis or timing simulation 4 Run the Generate Programming File process This creates a bitmap file for your complete FPGA design hardware 5 Run the Update Bitstream with Processor Data process This adds your embedded software object code to the bitstream created in step four for all software sections mapped to on chip memory blocks If necessary the XPS software tools are called www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i What is Involved in Creating an Embedded Submodule Design XILINX automatically to generate your Board Support Package BSP and to compile the software application you marked to include in your bitstream After connecting your developm
80. ols and capabilities including the Base System Builder BSB The Top Down Method Described In the top down method XPS automatically inherits the FPGA device selected in ISE To implement the top down method you invoke ISE and create a top level project Then you create a new embedded processor source to include in the top level design This automatically invokes XPS where you develop your embedded submodule The Bottom Up Method Described In the bottom up method you must select the same FPGA architecture in both XPS and ISE To implement the bottom up method you invoke XPS and develop your embedded processor design Later you invoke ISE and add the embedded submodule as a source to include in your top level ISE project Note Only the Xilinx Microprocessor Project XMP file must be added as the source file The Block Memory Map BMM file should not be added to the ISE project EDK Concepts Tools and Techniques www xilinx com 85 P N XTPO13 v 9 1i XILINX Appendix A Embedded Submodule Design with ISE d Test Drive Adding an Embedded Submodule to ISE Use ISE Project Navigator to create or include an embedded submodule XMP file as a source in your top level FPGA design For complete information about using Project Navigator refer to the Project Navigator online help You can only add one embedded submodule source to an ISE project The embedded submodule source can in turn contain multiple microprocessors
81. om ise embedded edk_docs htm 2 Functionality must be implemented and verified Your custom functionality must be implemented and verified with awareness that common functionality available from the EDK peripherals library can be reused Your stand alone core must be verified Isolating the core ensures easier debug in the future 3 The IP must be imported to EDK Your peripheral must be copied to an EDK appropriate directory and the Platform Specification Format PSF interface files MPD and PAO must be created so other EDK tools can recognize your peripheral 4 Your peripheral must be added to the processor system created in XPS EDK Concepts Tools and Techniques www xilinx com 37 P N XTPO13 v 9 1i XILINX Chapter 5 Creating Your Own Intellectual Property IP How to Do It Use the CIP Wizard You are probably saying to yourself This sounds complicated How do I use XPS to make all this happen Fortunately XPS offers another useful wizard the Create and Import Peripheral CIP Wizard The CIP Wizard assists with steps two and three above by walking you through the IP creation process It sets up a number of templates for you to populate with proprietary logic In addition to creating HDL templates the CIP Wizard creates a peripheral core pcore verification project for Bus Functional Model BFM verification The templates and the BFM project creation are great for jump starting your IP development as
82. onnection with the Design THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX INCONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic contro
83. or Add Library button if you need to add more files For this custom peripheral the wizard automatically infers all files required based on the PAO file Click Next to continue Bus Interfaces Check OPB Slave SOPB SOPB Port This panel allows you to specify additional connections to the SOPB Bus Connector If it were necessary to connect additional signals you would do it here Because this template design is still empty click Next The SOPB Parameter This panel defines any special bus interface parameters for your peripheral Click Next EDK Concepts Tools and Techniques www xilinx com 47 P N XTP013 v 9 1i XILINX Chapter 5 Creating Your Own Intellectual Property IP Wizard Screen Identify Interrupt Signals In this panel you can specify any additional interrupts Value to Enter when in doubt select the default value your core will use along with their signal characteristics Again accept the defaults specified and click Next until you reach the final page of the wizard Finish Click Finish to close the wizard Updating User Repositories to Include test_ip What s Next 48 1 6 Select Project gt Rescan User Repositories After XPS completes the scan a Project Peripheral Repository category appears in the IP Catalog Expand the Project Peripheral Repository listing in the IP catalog and double click the TEST_IP peripheral core to add it to
84. oral directory contains the HDL wrapper files along with the DO script files needed to run a behavioral simulation 8 Click Custom Button 1 in the XPS GUI toolbar The CIP Wizard configures this toolbar button when it creates the BFM simulation project Custom Button 1 initiates the following a Launches a bash shell to run a make file Bus Functional b Using the previously set simulation options properly calls the CoreConnect Bus Compiler BFC Functional Compiler BFC to operate on a sample bf1 file see lt project name gt pcores test_ip_v1_00_a devl bfmsim scripts sample bfl for more detail c Invokes the simulator with the BFC output command files INCLUDE or DO files depending on the simulator to execute the commands in the sample bf1 file The simulator waveform result will be similar to the figure below Results of this simulation are explained in Appendix B More About BFM Simulation at the end of this guide TM wave delad Figure 5 6 BFM Waveform Simulation Results for sample bfl t 640 ns What Just Happened The XPS tools just automated a lot of steps for you Assuming this is your first time through the process however it may seem confusing Let s quickly review what just happened 1 The CIP Wizard created a set of HDL template files in the lt project_name gt pcores test_ip_v1_00_a hd1 vhdl directory 2 The CIP Wizard created a test p
85. orm Studio SDK is an integrated development environment complimentary to XPS that is used for C C embedded software application creation and verification SDK is built on the Eclipse open source framework Because many other software development tools are being built on the Eclipse infrastructure this software development tool might already be familiar to you or members of your design team Other EDK Components EDK includes other elements such as e Hardware IP for the Xilinx embedded processors e Drivers and libraries for embedded software development e GNU Compiler and debugger for C C software development targeting the MicroBlaze and PowerPC processors e Documentation e Sample projects The utilities provided with EDK are designed to assist in all phases of the embedded design process 12 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i How Do the Tools Expedite the Design Process XILINX How Do the Tools Expedite the Design Process The diagram below shows the simplified flow for an embedded design I Xilinx Platform Studio XPS Software Software Hardware Development Development Development Kit SDK Verification External Simulator Configuration ISE X10506 Figure 1 1 Basic Embedded Design Process Flow e Typically the ISE FPGA development software runs behind the scenes The XPS tools make function calls to the utilities provided b
86. ote that both a linker script and test application sources were automatically created by the BSB Wizard as part of creating the selected test applications e Click the IP Catalog tab Find the Communication Low Speed IP category and expand it Locate the OPB_UART Lite peripheral and right click to review the available options Note the option to select a flat or hierarchical view Click the directories icon circled in Figure 3 4 above to switch between the two views 26 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The XPS GUI XILINX The System Assembly Panel The System Assembly Panel is where you view and configure system block elements If the System Assembly Panel is not already maximized in the main window click the System Assembly tab at the bottom of the pane to open it Bus Interface Ports and Address Filters XPS provides Bus Interface Ports and Addresses radio buttons in the System Assembly Panel shown in the figure below which organize information about your design and allow you to edit your hardware platform more easily r Fikers Be ime rat At Name Poo o Lec C Bus Connection IP Type IP Version a B BM M 4 Samo dem_modue 1004 H don dsoom_v10 206 D Sbon owt dsbeam_it_crth 300e H Pdo bam bram_block 10 G T 2 Svon ow Fiters ESen MED tame For O hate E o a Pb Net IP Type
87. platform XPS maintains your hardware platform description in a high level form known as the Microprocessor Hardware Specification MHS file The MHS an editable text file is the principal source file representing the hardware component of your embedded system XPS synthesizes the MHS source file into Hardware Description Language HDL netlists ready for FPGA place and route The MHS File The MHS file is integral to your design process It contains all peripherals along with their parameters The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture peripherals processor connectivity and address space For more detailed information on the MHS file refer to the Microprocessor Hardware Specification MHS chapter of the Platform Specification Format Reference Manual available at http www xilinx com ise embedded edk_docs htm Because of its importance let s take a quick tour of the MHS file that was created when you ran the BSB Wizard EDK Concepts Tools and Techniques www xilinx com 33 P N XTPO13 v 9 1i XILINX Chapter 4 The Embedded Hardware Platform iim Test Drive 1 Select the Project tab in the Project Information Area Look under the Project Files heading to find MHS File system mhs as shown in the figure below Double click the file name to open it IP Catalog Project Applications Platform Project Files i i MHS File
88. ps below take you through the entire process im Test Drive Locating and Importing the Software Test Files 1 Click the C C Projects tab in the upper left of the SDK main window 2 Inthe C C Projects Panel right click the TestApp_Peripheral project name and select Import In the Import dialog box select File system and click Next Browse to the drivers directory under your top level project and locate the test_ip_v1_00_a src directory This is where the CIP Wizard created a few C files and a header file for your test_ip core as shown in the figure below Oe sr OS makefile C test_ip_selftest c G test_ip c test_ip h Figure 6 3 Importing test_ip Software Files 5 Enable the check boxes for all the source files test_ to select them and click Finish Editing the test_app_peripheral c File 1 In the C C Projects tab on the left side of the SDK main window locate the test_ip_selftest c file Double click the file name to open it 52 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Platform Studio Software Development Kit XILINX The test_ip_selftest c file contains the function definition for a TEST_IP_SelfTest routine as shown in the figure below Notice the parameters this routine requires 36 note ag must be turned off for this function to work 37 Anote est may fail if data memory an ice are not on the same bus 38 39 40 41 XStatu
89. r select Hardware gt Create or Import Peripheral XILINX Create your new peripheral so that it has the characteristics described in the table below Wizard Screen Wizard Requested Input Value to Enter when in doubt select default value Peripheral Flow Set the wizard to createanew Select the Create templates for a new peripheral peripheral radio button to begin creating your new IP Store the peripheral in your XPS project Both steps are default options Repository or Project Specify the location to which Select the To an XPS Project option and browse you want to save the peripheral the location of the current project This may be pre selected Name and version Peripheral name and version number Give the new peripheral the name test_ip Use the default version 1_00_a Bus Interface Bus type Select OPB default IPIF Services IPIF services requested Select all basic services as well as a FIFO under the advanced services FIFO Services FIFO services requested Use default values for FIFO and for Interrupt services Interrupt Service Configure interrupt Use defaults handling User S W Register Software register Use defaults configuration IP Interconnect IPIC IP interconnect IPIC Use defaults signals Note Click a signal name to view additional information about a signal you might wish to adjust Peripheral Simulation Support Bus functional model si
90. r example if you are installing EDK v 9 1i you must also install ISE v 9 1i Installation Requirements for Simulation To perform simulation using the EDK tools you must have the following steps completed 1 ASmartModel capable simulator ModelSim PE SE or NCSim is required for the simulation steps MXE will not work for SmartModels 2 Install the CoreConnect Toolkit CoreConnect is a free utility provided by IBM You can download CoreConnect from the Xilinx website at http www xilinx com xInx xebiz designResources ip_product_details jsp key d r_pcentral_coreconnect After you make the appropriate selections on the web page to order and register you will have access to the download 3 If you haven t already done so compile the simulation libraries following the procedure outlined in the EDK help system available in XPS or on the Xilinx web page under Xilinx Platform Studio Help Topics at http www xilinx com ise embedded edk_docs htm a Ifyou are opening the help from XPS select Help gt Help Topics b Navigate to Procedures for Embedded Processor Design gt Simulation gt Compiling Simulation Libraries in XPS gt Compiling Simulation Libraries in XPS 14 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i How Do the Tools Expedite the Design Process XILINX 4 To be sure your simulator is set up to handle SmartModels refer to the help system From the contents list
91. race buffer is limited by the amount of on chip BRAM available Let s take another Test Drive and put these concepts into practice d Test Drive Run the Debug Configuration Wizard in XPS 1 To Launch the Debug Configuration Wizard in XPS click Debug gt Debug Configuration In the wizard click the Add ChipScope Peripheral button below the System Explorer pane The Add New ChipScope Peripheral dialog box appears In the dialog box select the radio button To monitor OPB bus signals adding OPB IBA to add a ChipScope integrated bus analyzer core for the OPB bus and click OK The configuration pane changes so you can specify the core configuration a Ensure the core is set up to monitor the OPB bus control address and data signals b Select the check box to Enable Hardware Software Co debug c Accept a default value of 512 samples Click the Advanced tab in the Debug Configuration pane Review the options available These provide finer control over what the ChipScope logic analyzer monitors and on what it will trigger For more information on how to use these features and parameters refer to the ChipScope Pro Software and Cores User Guide available at http www xilinx com literature literature chipscope htm Click OK to close the Debug Configuration wizard www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Platform Debug XILINX Review the Results Notice that the Debug Configur
92. ration Wizard facilitates hardware and software co debug which accomplishes the following Connects IBA trig_out to the processor stop signal so the IBA can place the processor in the debug Halt mode In short this ChipScope signal stops processor execution Whenever the processor is halted the software debugger registers the state of the processor when it was stopped allowing a hardware trigger to be correlated to the activity in software Depending on the bus in use the delay between the processor stop time and the registration of this eventin the debugger can be as short as 11 clock cycles As a result it is highly likely that the software has stopped during the same subroutine that caused the hardware trigger event Connects the processor halted signal to IBA trig_in so that the halting of the processor can trigger the IBA to record samples This condition registers with the bus analyzer any time the processor stops its execution A debug event such as a breakpoint occurrence forces the processor to halt its execution When this occurs the bus analyzer registers the condition and presents all samples gathered up to that point allowing you to correlate a software event to a state in hardware Connects the processor instruction signal to IBA trig_in so that the IBA can record the sequence of instructions The processor and clock must operate at the same clock frequency With this setting a trace review is possible The depth of the t
93. re VOU Begin crer hie PAVE R A E ARGAE EE earned 57 Why Simulate an Embedded Design uunnnanunnanunrr anrr ra eee 57 EDK Simulation Basics a e eeaeee erreneren errereen 58 Simulation Considerations uussa nusus eases ranun eunbeydinsaeene se 58 Global Settings to Specify espes csrincrrasereem nee e RADA mEnE 58 System Behavior and Improving Simulation Times 000000005 59 Helper Scripts recia rt eh a E E a Le ea tha ye beeedd 59 RGGUICHOUS os 52c455s4 ene nedeeseesexeiakereee eg beeen eee eden gsn aana 59 Test DIVE Ys ce cceGeSe ad ee ShG0R PERO E E R Gere Pe Re Sean eEeeeageeses 59 Simulation Setup 2 lt cesqiet oe ciathiaeas eaea oheedased Med seeders ges 59 Running Simulation 0 6666 eee nee 60 Chapter 8 Implementing and Downloading Your Design Implementing the Design 0 0 cece eee ees 65 Netlist Generation Review 0 0 0 00 ccc ccc eee unar eee eens 65 BT id eR Ae E E E a e e e 67 Generating the Netlist and Bitstream sasssa erria eee eee 67 FRGA C onfig uration te dis0 0 setts aE ety E ETE eaten 67 Test DIVE borer aee a a Badu lg tote torte Die view tole Gabe Alls iets te his Stee Sees 69 Chapter 9 Debugging the Design Xilinx MicroProcessor Debugger XMD 0 0 000 c cece eee ee 72 Software Development Kit SDK Software Debugger 73 ChipScope Pro Tools vi cic ete ee eb obee he eee hee ee bien eee eet Owes ewer es 74
94. ries and Files Created When You Run the BSB Wizard im Test Drive What s Next Using a file explorer utility navigate to the top level directory for your project Open the various subdirectories and become familiar with the basic file set Now that you know your way around XPS you re ready to begin working with the project you started in Chapter 2 Creating a New Project We will begin with the hardware platform EDK Concepts Tools and Techniques www xilinx com 31 P N XTPO13 v 9 1i XILINX Chapter 3 Xilinx Platform Studio XPS 32 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 4 The Embedded Hardware Platform What s in a Hardware Platform The embedded hardware platform includes one or more processors along with a variety of peripherals and memory blocks These blocks of IP use an interconnect network to communicate Additional ports connect to the outside world The behavior of each processor or peripheral core can be customized Various optional features are controlled through implementation parameters which specify what is ultimately implemented in the FPGA The implementation parameters also define the addresses for your system Hardware Platform Development in Xilinx Platform Studio Microprocessor Hardware Specification MHS XPS provides an interactive development environment that allows you to specify all aspects of your hardware
95. roject which isolates your PCORE and allows you to verify its functionality with the bus before hooking it to a larger system This project resides in the lt project_name gt pcores test_ip_v1_00_a devl bfmsim directory This test project makes use of several BFMs supplied by the CoreConnect ToolKit In this case there is a model of the processor bus memory and bus monitor all connected to your core under development The clear benefit is that you not only avoided having to create these models yourself but XPS also made all the correct connections automatically This saved you considerable time 3 After generating the simulation platform you can use Custom Button 1 to automate Custom Button option several otherwise tedious steps in the simulation process These steps run the sample bf1 through the CoreConnect Bus Functional Compiler and must be performed to generate the command file the simulator uses To find more information EDK Concepts Tools and Techniques www xilinx com 45 P N XTPO13 v 9 1i X XILINX Bus Functional Language BFL BFM Script files 46 Chapter 5 Creating Your Own Intellectual Property IP associated with these buttons select Project Options gt Customize Buttons and use the F1 help on the topic The location of the make file used is given below In addition to compiling the BFL the make file executed by Custom Button 1 calls the simulator with the command files to start simulation simpli
96. rovides block access to files and devices The LibXil File module provides standard routines such as open close read and write LibXil Net The network library for embedded processors LibXil Profile A software intrusive profile library that generates call graph and histogram information of any program running on a board LMB Local Memory Bus A low latency synchronous bus primarily used to access on chip block RAM The MicroBlaze processor contains an instruction LMB bus and a data LMB bus M MDD file Microprocessor Driver Description file MDM Microprocessor Debug Module MFS LibXil Memory File System The MFS provides user capability to manage program memory in the form of file handles MHS file Microprocessor Hardware Specification file The MHS file defines the configuration of the embedded processor system including buses peripherals processors connectivity and address space MLD file Microprocessor Library Definition file MPD file Microprocessor Peripheral Definition file The MPD file contains all of the available ports and hardware parameters for a peripheral MSS file Microprocessor Software Specification file EDK Concepts Tools and Techniques www xilinx com 97 P N XTP013 v 9 1i XILINX 98 MVS file NCF file NGC file NGD file NGO File NPL File OCM OPB PACE PAO file PBD file Appendix C Glossary Microprocessor Verification Specification file Netlist Co
97. rt software_manuals htm www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i What s Next X XILINX etc Contains files that capture the options used to run various tools This directory is empty because no actions outside of BSB have been performed pcores Used for including custom hardware peripherals There are two directories that contain the BSB generated test application C source code header files and linker scripts which were explored in an earlier Test Drive Underneath the main project directory you will also find a few files Those of interest are shown in the figure below and are described as follows system xmp This is the top level project design file XPS reads this file and graphically displays its contents in the XPS user interface system mhs The system microprocessor hardware specification or MHS file captures textually the system elements their parameters and connectivity The MHS file is the hardware foundation for your project system mss The system microprocessor software specification or MSS file captures the software portion of the design describing textually the system elements and various software parameters associated with the peripheral The MSS file is the software foundation for your project a B test_drive system xmp E system mbhs E system mss a O xps 9 blkdiagram data D etc O pcores H O TestApp_Memory 4 O TestApp_Peripheral Figure 3 7 Directo
98. rted Boards If you are targeting one of the supported embedded processor development boards available from Xilinx or from one of our partners BSB lets you choose from the peripherals available on that board automatically match the FPGA pinout to the board and create a completed platform and test application ready to download and run on the board Each option has functional default values that are pre selected in XPS This base level project can be further enhanced in XPS or it can be implemented using the Xilinx implementation utilities provided by ISE Custom Boards If you are developing a design for a custom board BSB lets you select and interconnect one of the available processor cores MicroBlaze or PowerPC depending on your selected target FPGA device with a variety of compatible and commonly used peripheral cores from the IP library This gives you a hardware system to use as a starting point You can add more processors and peripherals if needed The utilities provided in XPS assist with this including the creation of custom peripherals Selecting and Configuring a Processor You can choose a MicroBlaze or PowerPC processor and select e Architecture type e Processor bus clock frequency e Device type e Reset polarity e Package e Processor configuration for debug e Speed grade e Cache setup e Reference clock frequency e Floating Point Unit FPU setting Selecting and Configuring Multiple I O Interfaces BSB understan
99. s and Techniques P N XTP013 v 9 1i The Project Tab The Project Tab lists references to project related files Information is grouped in the following general categories e Project Files All project specific files such as the Microprocessor Hardware Specification MHS files Microprocessor Software Specification MSS files User Constraints File UCF files IMPACT Command files Implementation Option files and Bitgen Option files e Project Options All project specific options such as Device Netlist Implementation Hardware Description Language HDL and Sim Model options e Reference Files All log and output files produced by the XPS implementation processes The Applications Tab The Applications tab lists all software application option settings header files and source files associated with each application project With this tab selected you can e Create and add a software application project build the project and load it to the block RAM e Set compiler options e Add source and header files to the project www xilinx com 2 XILINX Project Information Area IP Catalog Project Applications Platform 2 Project Files MHS File system mhs MSS File system mss UCF File data system uct iMPACT Command File etc download cmd Implementation Options File etc fast_runtime op Bitgen Options File etc bitgen ut Project Options Device xc4vix1 2ff668 10 Netlist Top
100. s TEST IP SelfTest void baseaddr p Figure 6 4 Sample Software Template Created by the CIP Wizard 2 As you can see the TEST_IP_SelfTest routine requires a base address pointer which you must provide You can find the TEST_IP base address value in the xparameters h file as follows a In the C C Projects tab open the ppc405_0_sw_platform ppc405_0 include directory to display the xparameters h file Double click xparameters h to open it in the editing window Search for TEST_IP_0_BASEADDR You now have the base address definition information necessary to add the function to the TestApp_Peripheral c file 3 Inthe TestApp_Peripheral c file insert the following line of code before the final print statement TEST IP SelfTest KPAR_ TEST IP 0 BASEADDR Your TestApp_Peripheral c file will now look similar to the screen shot in the figure below 71 72 73 74 75 print Exiting main r n TEST IP SelfTest XPaR TEST IP O BASEADDR Figure 6 5 Code Insertion for TestApp_Peripheral c File Rebuilding Your Projects If the Build automatically option in the toolbar under Project is selected your projects are updated when you save the TestApp_Peripheral c file If not select Project gt Build Project After the build is complete note the creation of the Debug directory under the TestApp_Peripheral project For now your working ELF file for the project resides her
101. s additional challenges Add an FPGA design project to the mix and the situation has the potential to become very confusing indeed To simplify the design process Xilinx offers several sets of tools It is a good idea to get to know the basic tool names project file names and acronyms for these To make this easier for you see the Glossary of EDK specific terms provided at the back of this document The Integrated Software Environment ISE ISE is the foundation for Xilinx FPGA logic design Because FPGA design can be an involved process Xilinx has provided software development tools that allow the designer to circumvent some of this complexity Various utilities such as constraints entry timing analysis logic placement and routing and device programming have all been integrated into ISE For information on how to use the ISE tools for FPGA design refer to the Xilinx web page http www xilinx com support software_manuals htm The Embedded Development Kit EDK EDK is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx FPGA device To run EDK ISE must be installed as well Think of it as an umbrella covering all things related to embedded processor systems and their design Xilinx Platform Studio XPS XPS is the development environment or GUI used for designing the hardware portion of your embedded processor system Software Development Kit SDK Platf
102. s already open select File gt New Project and choose BSB from the resulting dialog box Build a project that has the following characteristics Wizard Screens System Property Setting to Use for Your Test Drive Create New XPS Project Project name Name your project system xmp Be sure to create a Using BSB Wizard new directory for the project Welcome Project type Select the option to create a new project Select Board Board vendor and name Choose Xilinx as your board vendor and select the Virtex 4 ML403 Evaluation Platform The ML403 board contains a Virtex 4 FX device which means BSB allows you to select either a MicroBlaze or PowerPC soft processor core Select Processor Processor Select PowerPC Configure PowerPC e Clock frequencies e Use defaults e Processor Debug e Use default FPGA JTAG Interface Debug I F This means that the JTAG pins will also be used for Configuration processor debug e On chip memory e Use 16 KB of data and instruction BRAM Configure IO Interfaces Xilinx provided IP Select at a minimum RS 232_Uart four screens selections Push_Buttons_Position SRAM_256Kx32 Add any additional IP if you wish to do so Any IP that must be purchased is displayed with an accompanying lock symbol You can evaluate the IP for a period of time but it must be purchased to continue working in your design Add Internal Default is Use default Peripherals plb_bram_if_cntlr_1 with 16 KB
103. select Procedures for Embedded Processor Design gt Simulation gt Setting Up SmartModels For additional details on the installation process see Getting Started with the Embedded Development Kit EDK at http www xilinx com ise embedded edk_docs htm EDK Concepts Tools and Techniques www xilinx com 15 P N XTP013 v 9 1i XILINX Chapter 1 Introduction 16 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 2 Creating a New Project Now that you ve been introduced to EDK let s begin looking at how you use the tools to develop an embedded system The Base System Builder BSB BSB is a wizard that quickly and efficiently establishes a working design which you can then customize At the end of this section you will have the opportunity to begin your test drive using BSB to create a project Why Should Use BSB Xilinx recommends using the BSB Wizard to create at minimum a foundation for any new embedded design project BSB may be all you need to create your design but if more customization is required BSB can save you a lot of time because it automates basic hardware and software platform configuration tasks common to most processor designs After running the wizard you have a working project that contains all the basic elements needed to build a more customized or complex system should that be necessary What You Can Do in the BSB Wizard Using t
104. select only those boards that contain the same FPGA device you specified for your ISE project Otherwise you can target a custom board 3 Proceed with development of your embedded hardware platform design in XPS Before returning to Project Navigator do one of the following to address any problems found in the embedded system If you plan to simulate the design run Simulation gt Compile Simulation Libraries and Simulation gt Generate Simulation HDL Files If you plan to implement the design directly run Simulation gt Generate Netlist 5 After returning to Project Navigator you can instantiate and connect the embedded subsystem to your top level FPGA design Note Your XPS submodule appears under the ISE top level HDL source in the hierarchy tree after you instantiate the submodule in your top level source You can select the XMP source and then run 86 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i What is Involved in Creating an Embedded Submodule Design XILINX the View HDL Instantiation Template process to generate a sample HDL instantiation template The HDL snippet in the template can be copied and pasted into your top level HDL source file If you must modify anything in your embedded submodule design you can run the Manage Processor Design process in Project Navigator to reopen XPS with your embedded project loaded Bottom Up Design Method If you have already created an embedded
105. submodule design using XPS you can add the embedded submodule to your top level design as follows 1 Open ISE Project Navigator 2 Create or open an ISE project for your top level FPGA design 3 Select the same FPGA Device Family package and speed grade for your ISE project as you specified for your embedded submodule in XPS Select Project gt Add Source to open the Add Existing Sources window In the Add Existing Sources dialog box browse to and select the XPS project file in XMP format for the embedded submodule Your XPS submodule appears under Sources in the Project pane Note The XPS submodule appears under your ISE top level source in the hierarchy tree only after you instantiate the submodule in your top level source You can select the XMP source and run the View HDL Instantiation Template process to generate a sample HDL instantiation template The HDL snippet in this instantiation template can be copied and pasted into your top level HDL source file Including an Embedded Submodule in Your Top Level Design In your top level FPGA design you must instantiate and connect the embedded processor system You must also copy and sometimes modify any design constraints generated by XPS into the User Constraints File UCF in your ISE project Instantiating the Embedded Submodule ISE provides a Hardware Description Language HDL instantiation template file that represents a top level design containing the embedded submodule
106. system mhs MSS File system mss i UCF File data system uct m iMPACT Command File etc download cmd Implementation Options File etc fast_runtime opt Bitgen Options File etc bitgen ut Figure 4 1 MHS File 2 Search for opb_uartlite in the system mhs file Notice how the peripherals their ports and their parameters are configured in the MHS file Take some time to review other IP cores in your design 4 When you are finished close the system mhs file Viewing the Hardware Platform from the System Assembly Panel The System Assembly Panel area in XPS displays all hardware platform IP instances using an expandable tree and table format The first thing to notice is comments which are preceded by a pound sign Next you will see global ports These are called global because they reside outside of a begin end block XPS provides extensive display customization sorting and data filtering capability so you can easily review your embedded design The IP elements their ports properties and parameters which are configurable in the System Assembly Panel are written directly to the MHS file Editing a port name or setting a parameter takes effect when you press Enter or click OK respectively XPS automatically writes the system modification to the hardware database which is contained in the MHS file The recommended method for editing the MHS file is to use the System Assembly Panel views Note Adding deleting
107. test level of use but may be the least understood This chapter provides you with insight into this crucial function EDK Concepts Tools and Techniques www xilinx com 71 P N XTP013 v 9 1i XILINX Chapter 9 Debugging the Design Xilinx MicroProcessor Debugger XMD XMD is a design software utility that facilitates debugging software programs you create XMD also helps you verify systems that use the microprocessors offered by Xilinx You can use XMD to debug programs that run on a hardware board or that use the Cycle Accurate Instruction Set Simulator ISS Figure 9 1 and Figure 9 2 show how XMD interacts with the target processor and the debug host software in use Tcl Terminal Interface i GDB Host Software Remote Host Software Protocol lt lt J _ _ _ _ powerpc eabi gdb TCP IP I l SSS a a a a aaa aa a I I I PPC405 Debug Port i PowerPC System I I I I X10586 Figure 9 1 XMD PowerPC System Connection 72 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Software Development Kit SDK Software Debugger XILINX Tcl Terminal Interface GDB Host Software Remote Host Software l XMD Protocol I MB Cycle Accurate I JTAG e e oa ae JTAG MDM l UART l OPB Bus i l J X10587 Figure 9 2 XMD MicroBlaze System Connection Note that XMD doesn t stand on its own but is used in conju
108. the read only MPD file in XPS 4 When the netlist generation process is complete select Hardware gt Generate Bitstream While XPS generates the bitstream open the system ucf file by double clicking the UCF File option in Project Files area of the Project tab Note the pinout constraints and the rudimentary clocking constraints XPS has created as part of the BSB setup FPGA Configuration To boot up an embedded processor system both hardware and software system components must be downloaded to the FPGA and program memory respectively The process is illustrated in the figure below EDK Concepts Tools and Techniques www xilinx com 67 P N XTPO13 v 9 1i XILINX Chapter 8 Implementing and Downloading Your Design Executable and Linkable Format file elf Bit File bitstream bit Hardware X10584 system bit Figure 8 3 Elements and Stages of Generating the Embedded System Bitstream During the prototyping or development phase you can download the hardware bitstream and software Executable and Linkable Format ELF file images by connecting a JTAG cable from your host computer to the JTAG port on your development board The Device Configuration gt Download Bitstream menu command in XPS programs the FPGA with the bitstream For software downloading you can initialize software into the bitstream if it fits inside FPGA internal block RAM BRAM memory or you can use the software debug tools
109. the system With the Bus Interface filter selected in the System Assembly Panel click the hollow bus connection symbol to complete the connection to the OPB bus Click the Addresses filter radio button in the System Assembly Panel With the peripheral addresses present find the test_ip_0 line item Double click the test_ip_0 peripheral to launch a core configuration dialog box and adjust the C_ BASEADDR and C_HIGHADDR values to 0x50000000 and 0x5000ffff respectively Click OK Now you can generate the system netlist Click Hardware gt Generate Netlist This completes the hardware portion of adding IP to your system You are now ready to create your software platform The next chapter explains how EDK handles the software elements of your system and what files it uses to manage and store data about your embedded applications www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 6 The Software Platform and SDK The Board Support Package BSP The BSP is a collection of files that defines for each processor the hardware elements of your system The BSP contains the various embedded software elements such as software driver files selected libraries standard I O devices interrupt handler routines and other related features Consequently it is easiest to have XPS generate the BSP after the hardware system is populated with its processors and peripherals and after the address map
110. ties You can choose whether or not to use this structure because the file ELF location can be reassigned at anytime Remember that if you do reassign the build property you must adjust the ELF file location in XPS as well Now that the software and hardware elements are created they must be tested This can be accomplished by downloading to a demo board or through simulation Because our system and software application are relatively small and because not everyone will be using the same demo board this guide takes an opportunity to describe the simulation process www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XILINX Chapter 7 Introduction to Simulation in XPS Before You Begin Reiterating the simulation requirements from the installation section be sure the following conditions are satisfied e A SmartModel capable simulator ModelSim PE SE or NCSim is required for the simulation steps MXE does not work for SmartModels In this chapter we will use the PPC405 SmartModel e You should already have compiled the simulation libraries If you haven t just follow the procedure outlined in the XPS help system To view this help section 1 Select Help gt Help Topics 2 From the resulting HTML page navigate through Procedures for Embedded Processor Design gt Simulation gt Compiling Simulation Libraries in XPS gt Compiling Simulation Libraries in XPS Note The XPS help system is also a
111. to SDK Right click this project to select it as the project to initialize BRAMs as was done in the previous step Now you should see a check mark beside Mark to Initialize BRAMs in the right click menu Your Applications tab will look similar to the screen shot in the figure below EDK Concepts Tools and Techniques P N XTP013 v 9 1i www xilinx com 55 XILINX Debug and production ELF file locations What s Next 56 Chapter 6 The Software Platform and SDK IP Catalog Project Applications Software Projects El dd Software Application Project W Default ppc405_0_bootloop Project TestApp_Memory amp Processor ppc405_0 Executable C Data designs xps82_test gsg T estApp_Memory exec amp Compiler Options amp Sources Headers FF 4 Project TestApp_Peripheral Z Mark to Initialize BRAMs Processor ppc405_0 Executable C Data designs xps8i Delete Project 2 Make Project Inactive Figure 6 7 Appropriate Project Setting for BRAM Initialization 4 Inthe Applications tab right click the Executable option in the TestApp_Peripheral project Browse to your SDK created ELF file in the SDK_projects TestApp_Peripheral Debug directory Note A few steps earlier in the Test Drive the SDK tool placed the ELF file in a Debug directory which is for development When your design moves to a release phase a different directory Release can be used depending on the C C Build Project Proper
112. to observe the hardware and software response of the recently created IP block to requests it receives Simulation Setup For the RS232_UART peripheral simulating at a 9600 baud rate requires extended simulation times during most of which there is little happening Accelerating the baud rate by a factor of 100 reduces the time spent simulating by a similar amount It also condenses the area in which data is transitioning allowing you to asses the simulated behavior of the system more easily EDK Concepts Tools and Techniques www xilinx com 59 P N XTPO13 v 9 1i X XILINX Chapter 7 Introduction to Simulation in XPS To accelerate the UART baud rate 1 In XPS System Assembly View double click the RS232_Uart peripheral to open its core configuration dialog box Look for a line item identifying the UART Lite Baud Rate From the drop down box select the highest value possible 921600 and click OK To commit this new value to your design you must generate the netlist From the toolbar click Hardware gt Generate Netlist Running Simulation 1 60 Under the Project tab verify that your Project Options gt Sim Model is set to BEHAVIORAL If not change it by double clicking this option Select Simulation gt Generate Simulation HDL Files to launch the Simgen tool and generate the simulation HDL files and helper scripts When you invoke the command to generate the simulation HDL files XPS creates the simulat
113. tor tool Libgen At this point you might want to take a another look at Figure 6 1 to see where you are in the process Launch SDK and Import Your Test Applications For this project you ll import the applications created earlier when you ran the BSB Wizard 1 Click Software gt Launch Platform Studio SDK to open SDK XILINX Chapter 6 The Software Platform and SDK SDK manages Note The associated XMP file top level XPS project file tells SDK which processors are present in software the hardware platform and provides a pointer to the libraries for each processor SDK only manages applications XPS your applications XPS manages the libraries and drivers that make up your software platform manages libraries and drivers Add Some Test Software for Your Custom IP Next you must add some test software for the custom peripheral test_ip you created earlier This entails Locating the software test files for the core Importing them into your TestApp_Peripheral application project Editing the test_ip_selftest c file to identify the base address for the test_ip core because the TEST_IP_SelfTest routine requires a base address pointer To obtain this information you must refer to the xparameters h file Does this seem confusing Don t worry you ll see how it works when you perform the steps below Rebuilding your projects SDK can be set to do this automatically The ste
114. ues for numbers that may be used as part of the BFL 4 Communication aliases are assigned for common operations in the BFL With the aliases set sample bf1 begins to initialize various elements with the following type of command set_device path string device_type string 5 The set_device command selects an On chip Peripheral Bus OPB device model to initialize 6 The path string is based on the various _wrapper files created as part of the BEM structure The string specifies the path of the model within the BFM system and test bench hierarchy 7 The device_type specifies the type of model being initialized p1lb or opb _device or __arbiter designations Having specified this information memory is initialized using the mem_init command With memory values initialized testing of the UUT can be begin The sample bf1 systematically tests the various elements you selected to include as part of the Create and Import Peripheral CIP Wizard process The resultant wave forms first appear at approximately 640 ns in the BFM simulation output See Figure 5 6 page 45 With this understanding of the BFL it should be fairly easy to see the connection between the sample bf1 and the sample do files 8 As part of the make file script which was run when User Command Button 1 was invoked earlier the BFL file is passed through the Bus Functional Compiler BFC 9 The BFC translates the input BFL into a simulator command file
115. v 9 1i XILINX Chapter 1 Introduction Before Starting Before discussing the tools in depth it would be a good idea to make sure they are installed properly and that the environments you have set up match those you will need to follow the Test Drive sections in this document Installation Requirements What You Need to Run EDK Tools ISE Several utilities in EDK use functionality delivered with tools contained in ISE So to use the EDK tools you first need to have the ISE tools installed Be sure you have also installed the latest ISE service packs as well For information go to http www xilinx com From there choose the download link in the upper right corner Bash Shell for Linux or Solaris If you are running EDK ona Linux or Solaris platform you need a bash shell Also be sure to check out the supported platforms covered in the Xilinx document Getting Started with the Embedded Development Kit EDK available at http www xilinx com ise embedded edk_docs htm Software Registration ID You ll need a software registration ID to install EDK You can get one online at http www xilinx com ise embedded register htm EDK Installation Xilinx distributes EDK as a single media installable DVD image Insert the DVD into your PC The installer launches automatically For more information online http www xilinx com ise embedded edk_docs htm Note ISE and EDK major versions must be the same Fo
116. vailable online at http www xilinx com ise embedded edk_docs htm Why Simulate an Embedded Design e Using simulation you don t have to wait for hardware to be complete before testing your software The result facilitated software development which allows you meet more aggressive project deadlines e Simulation provides insight into the internal workings of your system Signals and register values are more accessible in a simulated system than they are once a design is in hardware e Simulation also allows you complete control of your system Conditions that may be difficult to create in a hardware setting are relatively easy to simulate As you have seen throughout this guide XPS automates many mundane design details So you probably won t be surprised to learn that it does an excellent job of creating the simulation scripts and Hardware Description Language HDL files For software designers however it may not be clear how to make use of the final simulated project data so this chapter takes you on a test drive through the simulation process EDK Concepts Tools and Techniques www xilinx com 57 P N XTPO13 v 9 1i XILINX Chapter 7 Introduction to Simulation in XPS EDK Simulation Basics EDK supports simulation of your embedded system on ModelSim or NCSim logic simulators Simulation is accomplished by exporting VHDL or Verilog HDL models of your embedded hardware platform design The models include block RAM
117. w xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i XMP File XPS XST ZBT EDK Concepts Tools and Techniques P N XTPO13 v 9 1i X XILINX Xilinx Microprocessor Project file This is the top level project file for an EDK design Xilinx Platform Studio The GUI environment in which you can develop your embedded design Xilinx Synthesis Technology Zero Bus Turnaround www xilinx com 101 XILINX Appendix C Glossary 102 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i
118. wave do do jtagppc_0_wave do do iocm_cntlr_wave do do docm_cntlr_wave do do push_buttons_position_wave do do sram_256kx32_wave do do plb_bram_if_cntlr_1 wave do 4E Sh FE Sh SE SE FE SE FE SE OSE OE H OE EH When you re finished with these modifications save and close this file www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i Restrictions Disassembly command powerpc eabi objdump 2 XILINX Before starting simulation it would be helpful to know more about the actual software implementation that will occur A quick disassembly of the previously generated ELF file provides information about the executable address and assembly instructions that run the code In XPS select Project gt Launch EDK Shell The EDK shell is a cygwin based command window you can use to run EDK specific commands At the EDK shell command prompt change your directory cd SDK_projects TestApp_Peripheral Debug This is where your ELF file resides Tip Use the tab key for automatic completion of the path To perform the disassembly enter the following command powerpc eabi objdump S TestApp Peripheral elf gt gt TestApp Peripheral dis This command calls the PowerPC object file display routine powerpc eabi obj dump with intermixed source and disassembly information The output is sent to the TestApp_Peripheral dis file When the process is complete close the EDK shell and return to XPS For
119. well as ensuring your IP will comply with the system you created or will create The Create and Import Peripheral CIP Wizard By asking a few simple questions the CIP Wizard greatly simplifies your custom peripheral creation process Let s walk through creating a blank template for a piece of proprietary IP that you will design For simplicity most steps will accept default values but you will have a chance to see all the possible selections you can make What You Need to Know Before Running the CIP Wizard CoreConnect Compliant Peripherals The wizard can create four types of CoreConnect compliant peripherals using predefined IP interface IPIF libraries These are e OPB slave only peripheral e OPB master slave combo peripheral e PLB slave only peripheral e PLB master slave combo peripheral To learn more about the CoreConnect interface review the following documents appropriate to the bus to which your IP will connect OPB Bus SXILINX_EDK doc usenglish opb_ipif_arch pdf SXILINX_EDK doc usenglish opb_usage pdf PLB Bus SXILINX_EDK doc usenglish plb_usage pdf Data Sheets An easy way to find data sheets for a given element PLB or OPB Bus in the IP catalog Right click the IP element and select View PDF Datasheet 38 www xilinx com EDK Concepts Tools and Techniques P N XTP013 v 9 1i The Create and Import Peripheral CIP Wizard i Test Drive In the XPS toolba
120. world limitations Example constraints could be as simple as clock information or pin placement or they could be complex placement and timing parameters that satisfy critical logic paths The Test Drive project provided in this book is a processor centric design that is it consists only of the embedded processor platform There is no external logic unassociated with the processor system Therefore only a few constraints need to be added before bitstream generation You already have a User Constraints File UCF because when you ran the BSB Wizard you selected a small set of constraints based on the board you chose On completing the Base System Builder BSB Wizard steps the constraints were generated automatically The UCF is located in the directory lt project name gt data More information about constraints can be found in the ISE tools documentation Constraints Guide available at http www xilinx com support software_manuals htm im Test Drive Generating the Netlist and Bitstream 1 In System Assembly View find the RS 232_UART peripheral Opening its attributes double click resets the baud rate to 9600 if necessary 2 Select Hardware gt Generate Netlist to allow the baud rate changes to take effect 3 While netlist generation and synthesis is taking place locate the Project Peripheral Repository category in the IP Catalog tab and right click the test_ip peripheral which you created earlier Select View MPD Review
121. y the ISE software e You use XPS primarily for embedded processor hardware system development Specification of the microprocessor peripherals and the interconnection of these components along with their respective property assignments takes place in XPS e Simple software development can be accomplished from within XPS but for more complex application development and debug Xilinx recommends using the SDK tool e Verifying the correct functionality of your hardware platform can be accomplished by running the design through a Hardware Description Language HDL simulator XPS facilitates three types of simulation Behavioral Structural Timing accurate The verification process structure including HDL files for simulation is set up automatically by XPS You will only have to enter clock timing and reset stimulus information along with any application code Simulation will be covered in greater detail later in this guide e After you have completed your design you can click a menu item in XPS to download the FPGA bitstream along with the software Executable and Linkable Format file ELF which enables you to configure your target device For more information on the embedded design process as it relates to XPS see the Design Process Overview in the Embedded Systems Tools Reference Manual available at http www xilinx com ise embedded edk_docs htm EDK Concepts Tools and Techniques www xilinx com 13 P N XTPO13
122. y to create simulator instruction files for the design under test When you initiate the XPS toolbar command Simulation gt Generate Simulation HDL Files all this capability is enabled automatically In addition to this XPS includes Helper scripts to simplify simulator usage Helper scripts are generated at the test harness or testbench level to set up the simulation When run the Helper script performs initialization functions and displays usage instructions for creating waveform and list ModelSim only windows using waveform and list scripts The top level scripts invoke instance specific scripts Under the simulation lt simulation type gt directory you will find several command scripts for running simulation The system_setup do file is the starting point from which all other scripts are called Commands in the scripts can be customized as desired Editing the top level waveform system_wave do or list scripts allows you to select signals for inclusion or exclusion They are all shown by default For timing simulations only top level ports are displayed The simulation utility Simgen does not provide simulation models for external memories and it does not have automated support for simulation models External memory models must be instantiated and connected in the simulation testbench and initialized according to the model specifications iai Test Drive This test drive takes you through simulating your system and allows you

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