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ChipScope ILA Software and Cores User Manual

1. Bus Signal x oO ap E M San Signal 0 0 0 Signal_1 0 0 Signal 2 o lio Signal_3 oo Signal 4 o fio Signal 5 11 NENNEN Signal 6 olo Signal 7 1 i L _ Sinal_5 6 eke 63 Eras a dy dd i s new waveform x b x oh ab Figure 4 30 Viewing the On Trigger Capture Mode Waveform Running and Stopping the Trigger Running Arming the Trigger After setting up the trigger select Run Stop Run to arm it The trigger stays armed until the trigger condition is satisfied or the user disarms the trigger Once the trigger condition is satisfied the trigger automatically disarms and the captured data appears in the waveform window To force the trigger select Run Stop Trigger Immediate This causes the ILA unit to ignore the trigger condition and trigger immediately After the sample buffer fills with data the trigger disarms and the captured data appears in the waveform window Stopping Disarming the Trigger To disarm the trigger select Run Stop Stop Acquisition If the trigger condition has been satisfied at least once before the acquisition is stopped the ChipScope program disarms the trigger and displays the captured data Subsequent selections of Run Stop Run cause the trigger to re arm Using Buses and Signals Grouping Signals Into a Bus You can group up to 64 signals to form a bus
2. X0 Signal 0 o Wa IRLUUFLLULTLIELLTUIUIUTI DA Fit Window Signal_1 oo mmn ToggleTime State Display Signal 2 1 jj 0 nnnnnnnnnnnmn Set Clock Period Signal 3 010 LILILITLITVTILI PlotValues Signal 4 1 iio TJT LI LL Demo Waveform Signal_5 l 0 Signal 5 Signal 7 171 NUILLA MISMAS eee eee RESTE Signal 8 1 jo ee Signal 9 oo E PeT Toad Peper Tor prea eer ETF E ECPI SPER SET ST NTEETL TOTTI ICE CDEN SECUS Signal_10 0 il Signal_11 Signal 12 i i Signal 13 0 Signal 14 al 1 Signal 15 1 L CE r Figure 4 43 Zooming in to the Center of the Waveform Display UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 25 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX You can also zoom in to a specific place in the waveform For example select Data Zoom In To X Marker to zoom in to the X cursor location Figure 4 44 Other zoom locations include the O cursor and first trigger position that is data sample 0 To zoom in to a specific area of the waveform select Data Zoom Area then click the left mouse button and drag to select an area of the waveform display Using this method the waveform display zooms in to the selected area ChipScope Analyzer demo Unit 0 x File Communication Configure OA Window Help Trigger Setup Go To Zoom In To Zoom In O Marker
3. Bra Signal 13 Signal 14 1 il _ Signal_15 E EI REGENS MIGNE I MAMMA UM MEC PP d dd dd d jd m new waveform ix 52 alel 0 res EH A X 0 717 Ud MEET Figure 4 46 Fitting the Waveform Display in the Window Toggling Time State Display The x axis of the waveform can be displayed as the sample number relative to the trigger event default or by a time unit per sample starting at the first sample captured By default the time unit is 5ns sample Setting a Sample Clock Period When the waveform is viewed with the x axis in time units the sample clock period can be modified with this option Units are always in ns Plot Values This option brings up a separate window with a bus or buses plotted in an x y format Two line types can be chosen a scatter plot which plots a single dot at each data point and a line plot which connects all the data points together with a line Separate buses are displayed in separate colors see Figure 4 47 with line graph chosen XY Plot x Line Type rope A Bus Selection v Bus v Busi 51 1000 795 591 386 181 24 228 433 638 842 1047 Done Figure 4 47 Example of X Y Plot UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 27 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Main Toolbar Features XILINX Generating a Demo Waveform To generate a sample waveform for trying out various ChipSc
4. Zoom Out Trigger Bus Signal xo DORAE quen B3 Zoom Area Signal 0 o 1 inmunnmnmnnmnn Eit Window Signal 1 00 mannm Toggle Time State Display Signal 2 l1 fo nnnnnnnnnnnn Set Clock Period Signal_3 010 ULU LU LULT UO Plot Values Signal 4 1 oa TJT LT LT L Demo Waveform Signal_5 110 St Era Siete a tere assumi eevee Lassus Eea is Signal_6 oo OO o ee ee Signal 7 1 fj SPCC SAEs EI Signal_8 1 fo nc MM CE Signal 8 o io EAE O E AA a E EU DNEME SEE TXEEN Signal_10 0 al Signal_11 0 Signal_12 il 1 Signal_13 0 Signal 14 i 1 Signal 15 1 1 PEPE ____ _ _ _ _ Figure 4 44 Zooming in to the X Marker of the Waveform Display To zoom out from a waveform use Data Zoom Out Figure 4 45 ChipScope Analyzer demo Unit 0 fel ES File Communication Configure Bus Signal Run Stop SEEM Window Help 5 gt m tl Sale ejej 5 Trigger Setup wo zxxxx ooo wrF z xxxxkxxx 220 M1 wimn Coum Trigger Condition boolean p zii n w Capture One Shot On Trigger Position 0 2047 6 Zoom OQ ut ULL Bus Signal X 0 HERNE ed 2 Zoom Area d Mera Signal 0 o 1 gqewannnnmnnmnn A Eit Window a Signal_1 oo LUT TeggleTime State Display Signal 2 1 0 nnnnnnnnnnrnn Set Clock Period Signal_3 M NU UU U Ur Lr U Plot Values Signal_4 1 iio T LI LI BemoWaveform Signal 5 il 0 Signal_6 0 0 Signal 7 T 1l Signal_8 1 jlo SS nS eS Signal 9 o 0 ER BIS SEAS S
5. pne Chain Device Order nae Name Device Name m Length Device ID UserID Reve ACE 0a001093 10610083 om 01028083 JTAG Chain Transactions Starttransactions in Run Testildle End in Run Testidle Default C Starttransactions in Test Logic Reset End in Run Testildle Setting may matter when multiple applications take turn accessing the JTAG chain OK Read User IDs Figure 4 12 Advanced Boundary Scan Parameters Setup Window UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 7 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Device Configuration The ChipScope Analyzer is able to configure target FPGA devices using MultiLINX Parallel Cable III or Parallel Cable IV cables in JTAG mode only Note Slave Serial configuration mode is no longer supported If the target device is to be programmed using the MultiLINX or Parallel Cable III download cable by way of the JTAG port select Configure JTag Mode Figure 4 13 Cm ChipScope Analyzer Untitled Device 0 Unit 0 BB File Communication eiipibiiem Bus Signal Run Stop Data Window Help E 5 gt Boundary Scan Setup P ala JTAG Configuration Ini x Show IDCODE Show USRCODE A NA hip Successfully opened Parallel Cable port LPT1 C Scope Figure 4 13 Configuring JTAG Mode Window After selecting the
6. Analyzer Menu Features XILINX MultiLINX cable diagnostic information See the sample dialog in Figure 4 9 for the MultiLINX cable information EE ChipScope Analyzer Device x G MultiLIINX Information wHardwareversion 0001 WE irmwareVersion 0100 wFPGAVaersian 000C wAlgarithm ersion 0000 dwhermorSize 00040000 wPastError 0000 dwPastData 00000000 dwPastData2 CCCCOOO0 Cable Diagnostics Test Successful Figure 4 9 Getting Cable Information Opening a Parallel Cable Connection ChipScope supports the Parallel Cable III and Parallel Cable IV To open a connection to the Parallel Cable make sure the cable is connected to one of the computer s parallel ports Select Comnunication Parallel Cable Figure 4 10 ChipScope prompts you for the port name Type the printer port name in the port selection box usually the default LPT1 is correct and click OK If successful ChipScope queries the Boundary Scan chain to determine its composition see Setting Up the Boundary Scan Chain page 4 6 If ChipScope returns the error message Failed to Open Communication Port verify that the Parallel Cable III or Parallel Cable IV is connected to the correct LPT port If you have not installed the Parallel Cable III or Parallel Cable IV driver follow the instructions in Note 2 page 1 10 in Chapter 1 to install the required device driver software Lhip5 cope Analyzer demo ChipScope Unit File Memini Confi
7. mif zxxxx exxx m Mi width Count Trigger Capture ons Shot On Trigger Po Tou ey hii Be Ungroup From Bus Move Up Move Down Rename Show As L Bus Bit Ordering E Channel Numbers l l Bignal 4 Import Signal Mames l dna Color ale 5 Load Tokens H gnal_ B 1l Yea ssec si em ChipScope Analyzer demo Unit 0 File Communication Configure Bu S rim T wile we s xxxx xxx mt Mi width Count Trigger Col Capture One Shot On Trigger Positi Bus 5ignal aignal Signal Bignal 2 oro os ore oops Bignal 3 SMAI eeu ees heal Figure 4 32 Ungrouping Signals from a Bus Moving Buses and Signals To move buses and signals up and down in the display highlight a signal or bus then select Bus Signal Move Up or Bus Signal Move Down When the position of a signal in a bus is changed the bus values are recalculated and the new values appear in the wave display window Figure 4 33 Buses and signals can also be moved by dragging and dropping them in the left hand signal pane ChipScope Analyzer demo Unit 0 File Communication Configure MEISETIPSIPHEIMS RuniStop Dat amp Bignal 4 Bignal 5 Signal _ amp wo lk x xxx x x x m1 Mi width Count Trigger Capture ons Shot On Trigger Po hou ey hii BIET pjat Ungroup From Bus
8. ChipScope ILA Software and Cores User Manual ChipScope Software v4 2 UG005 PN 0401884 v4 2 March 22 2002 XILINX gt XILINX The Xilinx logo shown above is a registered trademark of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc Xilinx and the Xilinx logo are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 XC5210 are registered Trademarks of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX Nano Blaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI Rocket I O Selectl O SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx X
9. Sample Buffer FILL Bus Signal x Address B f l L 8ignal 0 i Signal io Bignal 2 o ilo A Signal 3 l Signal 4 i Figure 4 40 Selecting a Waveform Color UGOO5 PN 0401884 v4 2 March 22 2002 www xilinx com ChipScope ILA Software and Cores User Manual 1 800 255 7778 4 23 Analyzer Menu Features XILINX Signal Name Importing Signal names can be directly imported from a ChipScope Core Inserter Project file To import the names select Bus Signal Import Signal Names and a dialogue box opens for navigating to the Core Inserter Project cdc file Select the file then click Open to populate the waveform with the signal names from the project Figure 4 41 LE ChipScope Analyzer mine Unit 0 File Communication Configure Run Stop Da roe E Trio hati Bue Wave Op ove aw Trigger Condition boolean M Sample Buffer FULL Eenanie Sry rae bus sigmal ES Irene aignal L 1l l P Channel Numbers Egal 1 oO pol D wala v Signal_2 os BE Load makens Signal 3 T IUE Import Signal Names Import Signal Names EES Look in E3 bin HE File name cde Files af tupe A Files Cancel Figure 4 41 Importing Signal Names a Jes r9 UGOO5 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 4 24 Analyzer Menu Fe
10. The waveform display in the ChipScope window now contains the imported waveform You can export a waveform file in a similar fashion To export the waveform to a VCD file select File Export Waveform VCD Export To export the waveform to a FBDF file select File Export Waveform FBDF Export To export the waveform to an ASCII file select File Export Waveform ASCII Export In each case a dialog box opens and you can browse for the desired storage folder location After finding the target location and entering the waveform filename click Save The waveform is now stored in the desired format Closing and Exiting ChipScope To close a ChipScope window select File Close To exit the ChipScope program select File Exit In both cases if you have not stored the waveform a dialog box opens asking if you want to store the current waveform before closing exiting If you select Yes another dialog box opens from which you can save the waveform The difference between closing and exiting is closing closes the current ChipScope window exiting closes all ChipScope windows and ends the program However if only one ChipScope window is open closing and exiting have the same effect Opening and Closing a MultiLINX Connection You can connect the MultiLINX cable to the host computer by using a serial communications port e g COM1 the USB Universal Serial Bus port connection or both However only one connection to th
11. n Tm Color OE i Signals A i 7 Figure 4 34 Changing Bus and Signal Names Bus Radix Display Buses can be configured individually to display different radixes in the wave display window Available bus display options are hexadecimal binary signed decimal unsigned decimal octal ASCII and Token By default bus values are displayed in hexadecimal ASCII is only available when the bus specified is exactly 8 bits wide To set the radix for a bus select a bus in the Bus Signal panel then select Bus Signal Show As The menu popup Figure 4 35 allows you to choose from the available bus radix options ChipScope Analyzer demo Unit 0 iix File Communication Configure EITSEIPHEIB Run Stop Data Window Help 5 gt B T Q Croup nig Bus Ungroup From Bus Move Up Move Down we eK x x xx x x x mts M1 width Count fi Triggei Capture One Shot On Trigger Pa Rename Bus Bit Ordering SES Channel Numbers Signed Decimal VN Color Unsigned Decimal signal d x Load Tokens Octal Signal 6 iyi Import Signal Names ASII Signal 7 00 p Token Signal_8 0 Signal 8 I il Signal_10 l A Sianal 11 z rT di E 2 new waveform x o 0 o A X 0 o a 3 AMEN TEN Figure 4 35 Changing Bus Display Radix UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 20 Chi
12. Analyzer Menu Features XILINX New ILA Unit Device m Device m Unit n where m is the target device number n is the ILA unit number Note that the ILA unit number corresponds to the control port number of the ICON unit to which the ILA component is connected or the Unit number in the case of Core Insertion Figure 4 2 shows how to select ILA Unit 0 in target Device 1 If the trigger setup toolbar is not present in the current ChipScope window then selecting a new ILA unit using this method simply refocuses the current window to the new ILA unit However if you select a new ILA unit after you have set up the trigger for the current one a new ChipScope window opens This feature allows you to view the waveforms of multiple ILA units at the same time ChipScope Analyzer demo Unit 0 Fg Multivinx Configure Bus Signal Run Stop Data Window Help PE oeieo of 5 Open Project Save Project Device 1 Unit 1 Save Project As Device 1 Unit 2 Import Waveform Device 1 Unit 3 EXHBGTEVAVEERGITITUE Device 1 Unit 4 Close Device 1 Unit 5 Exit Device 1 Unit 6 Device 1 Unit 7 Device 1 Unit 8 Device 1 Unit 9 Device 1 Unit 10 Device 1 Unit 11 Device 1 Unit 12 Device 1 Unit 13 Device 1 Unit 14 Tag Chain Info Figure 4 2 Selecting New ILA Unit in Target Device 1 New ILA units are displayed in their own window and the Device Unit for a particular window is displayed in the title bar All the ILA units
13. Spartan IIE Cores generated for this family will work for all Virtex Virtex E Virtex II Virtex II Pro Spartan II and Spartan IIE devices Cores generated for the Virtex II Virtex II Pro family will only work for Virtex II and Virtex II Pro devices The Use SRL16 s check box is used to select whether or not the cores will be generated using SRL16 and SRL16E components If the check box is not selected the SRL16 components are replaced with flip flops and multiplexers The replacement of SRL16 components with flop flops and multiplexers will affect the size and performance of the generated cores The Use SRL16 s check box is checked by default in order to generate cores that use the optimized SRL16 technology When this step is completed click Next UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 3 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX Choosing ICON Options The first options that need to be specified are for the ICON core The ICON core is the controller core that connects all ILA units to the JTAG boundary scan chain The ICON core has the options parameters shown in Figure 3 3 Enable External Trigger Input Enabling the external trigger input causes a PAD to be added to the design the pin location specified in Figure 3 3 is added in the NCF file that is automatically generated for the ICON core This signal is a logical OR d condition of all th
14. Virtex Virte E Spartan Il Spartan IIE wl 6 Use 56168 Figure 3 1 Blank Core Inserter Project When the ChipScope Core Inserter is first opened all the relevant fields are completely blank Using the command File New also results in this condition Figure 3 1 UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 1 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX Opening an Existing Project To open an existing project select it from the list of recently opened projects or select File Open Project and Browse to the project location When the desired project is located double click on it or click Open Saving Projects If a project has changed during the course of a session the user will be prompted to save the project upon exiting the Core Inserter A project can also be saved by selecting File gt Save To rename the current project or save it to another filename select File gt Save As type in the new name and click Save Refreshing the Netlist The Core Inserter automatically reloads the design netlist if it detects that the netlist has changed since the last time it was loaded However the Core Inserter can be forced to refresh the netlist by selecting File Refresh Netlist Inserting and Removing ILA Units New ILA units can be inserted into the project by selecting Edit New ILA Unit An ILA unit can be removed by
15. port signals to a control port of only one ILA core instance in the design e Do not leave any unused CONTROL ports of the ICON core unconnected as this will cause the implementation tools to report an error Instead use an ICON core with the same number of CONTROL ports as you have ILA cores Generating an ILA Core The ChipScope Core Generator allows users to define and generate a customized ILA capture core to use with VHDL and Verilog designs Users can customize the maximum number of data sample words stored by the ILA core the width of the data sample words and the width of the trigger word if different from the data word After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file nc and example code specific to the synthesis tool used Users can easily generate the netlist and code examples for use in normal Virtex Virtex E Virtex IL Virtex Pro and Spartan II and Spartan IIE design flows The first screen in the Core Generator offers the choice to generate either an ICON or ILA core Select ILA Integrated Logic Analyzer and click Next Choosing the File Destination The destination for the ILA EDIF ila edn is displayed in the Output Netlist field The default directory is the Core Generator install path To change it the user can either type a new path in the field or choose Browse to navigate to a new destination The user can select fro
16. 2 Browse for ChipScope V Ri pc exe 3 Choose Run 4 Follow the install wizard instructions Notes 1 The ChipScope Analyzer can be installed separately from the ChipScope Core Inserter and ChipScope Core Generator tools by performing a Custom installation 2 The Parallel Cable III IV driver can be installed by performing a Custom installation Installing the Java Run time Environment for Windows NT 98 2000 The Java Run time Environment JRE version 1 3 1 used by the ChipScope 4 2i tools is automatically included under the ChipScope 4 2i installation directory Installing MultiLINX USB Driver for Windows 98 2000 If you need to install the MultiLINX cable under Windows 98 or Windows 2000 for USB 1 Make sure that the PWR and GND wires of the MultiLINX cable are connected to power and ground sources respectively 2 Plug the cable into the USB port of the host computer An installation dialog box opens Select Have Disk 4 Browse the ChipScope Tools installation for the m1t1nx inf file This is typically installed in folder C NProgram Files Xilinx ChipScope data 5 Click OK and follow the installation wizard instructions Installing ChipScope Software for Solaris 2 6 2 7 and 2 8 The ChipScope Core Generator and ChipScope Core Inserter tools for Solaris 2 6 2 7 and 2 8 e Java Run time Environment 1 3 1 included in download file e Solaris operating system patches for more details refer to the READ
17. 2 March 22 2002 www xilinx com 2 4 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ILA Core XILINX Selecting the Trigger Match Unit Type An ILA core trigger unit comprises one or more match units that contribute to the overall trigger condition by looking for a specific pattern on the trigger input The types of patterns and their occurrence over time that are looked for depend on the type of the match unit The ChipScope core generator handles basic and extended trigger match units The basic trigger match unit e Finds only one occurrence of an exact match of a trigger value or edge e Can be used in conjunction with other trigger match units to build the trigger condition Boolean equation using AND OR The extended trigger match unit e Finds one or more occurrences of an exact match of a trigger value or edge e Finds one or more occurrences of a range of trigger values e Detects contiguous pulse width or non contiguous event count trigger match conditions over a number of clock cycles e Can be used in conjunction with other trigger match units to build the trigger condition Boolean equation using AND OR e Can be used in conjunction with other trigger match units to build the trigger condition macro equation using IF THEN For the ILA core that is being generated the Trigger Match Unit Type is selected for all match units at the same time Selecting the Number of Trigger Match Units Sel
18. 4 19 Viewing the Trigger Setup Toolbar UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 10 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX setting Up the Trigger The trigger mechanism inside each ILA core can be modified at run time without having to re compile the design The following sections describe how to modify the various components that make up the trigger mechanism Basic Match Unit Comparison Values The match units are called Mn where n is 0 or 1 depending on the number of trigger match units in the ILA core and can be one of two types basic or extended If the match units are basic then you can change only the comparison value Figure 4 20 You can set each bit of the match unit to one of the following values e X Any value logical zero or logical one e 0 Logical zero only e l Logical one only e R Rising edge only e F Falling edge only e B Both edges rising edge or falling edge You can set match word values by clicking on each bit until the desired value appears or by clicking on the bit value and typing the desired value Moving the cursor over but not clicking on a bit in the match word causes a tool tip window to appear that indicates the bit position and current match value Note If you have imported signal names using the Bus Signal gt Import Signal Names menu option then the tool tip for each match unit value bit will display the
19. AND OR e Enabling usage in conjunction with other trigger match units to build the trigger condition macro equation using IF THEN Basic Matching If Extended Matching is not checked a subset of the above features are available for all match units saving CLB usage of the ILA core These options include e Finding only one occurrence of an exact match of a trigger value or edge e Enabling usage in conjunction with other trigger match units to build trigger condition boolean equation using AND OR Match Units The number of match units can be set to one or two Selecting two units allows a more flexible trigger condition equation to be a combination of both match units Selecting one match unit conserves resources while allowing some flexibility in triggering Choosing Net Connections for ILA Signals The Net Connections panel see Figure 3 5 under the Match Settings allows the user to choose the signals to connect to the ILA core If trigger is separate from data then Clock Trigger and Data must be specified When trigger equals data only Clock and Trigger Data must be specified Double click on the Clock Net label or click on the plus sign next to it to expand as shown in Figure 3 5 only the Net Connections panel is shown et Connections EILA UNIT CLOCK NET E TRIGGER NETS DATA NETS Figure 3 5 ILA Core Clock Specification UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 7 ChipScope ILA Softwa
20. Capture ons Shot On Trigger Po Rename show As pi Sj Bus Bit Ordering Channel Numbers i Bignal 4 T ii es Color gnal_5 il 1l laad Tabane sa D Width Count f 1g nur ADIT Sample Buffer FUL Li v Battom MSB To ToprL SB TopiMSB To BattarniL SB Figure 4 38 Changing Bus Bit Ordering Signal Channel Number Display Channel number display can be toggled to identify which of the ILA core data channels is connected to each of the signals in the waveform display To toggle the display select Bus Signal Channel Numbers By default channel number display is turned off Figure 4 39 ChipScope Analyzer demo Unit 0 Bus 5ignal aignal 4 Bignal 5 Bignal 8 icr Figure 4 39 File Communication Configure xxxx o ooo n Mi width Count Trigger Capture one Shot On Trigger Pc Run Stop Dal Chou ey hi Be Ungroup From Bus hove Lp Move Down Rename show As li Bus Bit Ordering Channel Numbers Color Load Tokens Import Signal Mames ChipScope Analyzer demo Unit 0 File Communication Configure Bu se f pl mT IF Capture One Shot On Trigger Positi Bus Signal x oO DCH4 Signal 4 i i EZ a HH c AS Signal 5 il 1l zz CHB Signal 8 104 IESS Enabling Signal Channel Number Display UGO005 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www
21. Controller ICON Core and the Integrated Logic Analyzer ILA Core Once the cores are generated users can use the instantiation templates that are provided to quickly and easily insert the cores into their VHDL or Verilog design After completing the instantiation and running synthesis users implement the design using the Xilinx implementation tools Generating an ICON Core The Core Generator gives users the ability to define and generate a customized Integrated Controller ICON unit to use with one or more Integrated Logic Analyzer ILA units in VHDL and Verilog designs Users can customize control ports the number of ILA cores to be connected to the ICON Core and control whether to use USER2 Boundary Scan port signals After the Core Generator validates the user defined parameters it generates an EDIF netlist edn a netlist constraint file ncf and example code in VHDL and Verilog specific to the synthesis tool used Users can easily generate the netlist and code examples for use in normal Virtex Virtex E Virtex II Virtex Pro Spartan II and Spartan IIE design flows The first screen in the Core Generator offers the choice to generate either an ICON core or an ILA core Select ICON Integrated Controller Core and click Next Choosing the File Destination The destination for the ICON EDIF file icon edn is displayed in the Output Netlist field The default directory is the Core Generator install path To ch
22. Extended Match Comparison Type and Value The possible comparison types are e equal to e lt gt not equal to e gt greater than e gt greater than or equal to e lt less than e lt less than or equal to The possible match comparison bit values depend on the comparison type For instance when the comparison type is set to you can set each bit of the comparison value to one of the following e X Any value logical zero or logical one e 0 Logical zero only e 1 Logical one only e KR Rising edge only e F Falling edge only e B Both edges rising edge or falling edge uo nn If the comparison type is set to something other than comparison to one of the following then you can set each bit of the e 0 Logical zero only e 1 Logical one only You can set the match word values by clicking on each bit until the desired value appears or by clicking on the bit value and typing the desired value If you move the cursor over a bit in the match word and do not click a tool tip dialog box opens displaying the bit position and current match value UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 12 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Setting Up Pulse Width and Event Count You can configure an extended match unit to find matches that occur over one or more clock cycles contiguously in a row or non contiguously not neces
23. FOCUS sinan E muocanseoeeenanenias 4 28 Vaeume PICT TEA 0S i vitu toI bn otto aude a pa eM qu Mom t m eU E 4 28 ChipScope Main Toolbar Features eerte 4 28 UGO005 PN 0401884 v4 2 March 1 2002 www xilinx com vi ChipScope ILA Software and Cores User Guide 1 800 255 7778 XILINX Chapter 1 Introduction ChipScope ILA Tools Overview As the density of FPGA devices increases so does the impracticality of attaching test equipment probes to these devices under test The ChipScope ILA tools integrate key logic analyzer hardware components with the target design inside the Virtex device The ChipScope ILA tools communicate with these components and provide the designer with a complete logic analyzer without the need for cumbersome probes or expensive test equipment ChipScope ILA Tools Description Table 1 1 ChipScope ILA Tools Description Tool Description ChipScope Core Generator Provides netlists and instantiation templates for the Integrated CONtroller ICON core and the Integrated Logic Analyzer ILA core ChipScope Core Inserter Automatically inserts the ICON core and the ILA core into the user s synthesized design ChipScope Analyzer Allows setup and trace display for the ILA core The ILA core provides the trigger and trace capture capability The ICON core communicates to the dedicated Boundary Scan pins The ChipScope Analyzer supports the Xilinx MultiLINX Pa
24. Move Lp Rename show As Bus Bit Ordering Channel Numbers Color Load Tokens Irnnnrt Sianal Blameac ChipScope Analyzer demo Unit 0 File Communication Configure Bu e io FL mI Sys mk kx xx kxxx Mi Mi Width Count Trigger CUOI Capture One Shot On Trigger Positic Bus 5ignal aignal 4 Bignal 5 nam Bignal 8 Figure 4 83 Moving Buses and Signals UGOO5 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 4 19 Analyzer Menu Features XILINX Changing Bus and Signal Names To rename buses and signals anytime for easy identification click on the bus or signal to rename then select Bus Signal Rename A text input box Figure 4 34 opens prompting for the new name Names must be unique and may contain letters numbers or underscores Type the new name then click Enter Chip5 cope Analyzer demo Unit 0 ChipScope Analyzer demo Unit L File Communication Configure Bsr Runistop Dat File Communication Configure BL Tou ey i BNE F ajjaj gt aft gt mo Ibex xf xxx Capture one Shot On Trigger Positi Ungroup From Bus Move Lp Move Down Mi width Count i Trigger Capture One Shot On Trigger Pc show As Load Tokens Bus Bit Ordering Bus Signal x iio p Signal 4 ET VUE i 5 annel Numbers
25. Names v Show Source Component Types MV Show Base Net Driver Types Preference Options Reset all values to installation defaults Reset OK Cancel Figure 3 10 Core Inserter Miscellaneous Preference Settings The Tools section contains settings for the command line arguments used by the Core Inserter to launch the Edif2Ned tool UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 10 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Using Core Inserter 4 2i with Command Line Implementation XILINX The ISE Integration section contains settings that affect how the Core Inserter integrates with the Xilinx ISE Foundation 4 2i Project Navigator tool When ISE integration is enabled by default the Core Inserter automatically searches through the current working directory for ISE 4 2i temporary netlist directory called ngo If a valid ISE 4 21 ngo directory is found the Core Inserter project will be set up automatically to overwrite the intermediate NGD files of the ISE project with those produced by the Core Inserter The ISE Integration preferences can be set by the user to prompt the user before overwriting any intermediate NGD files The Miscellaneous preferences section contains other settings that affect how the Core Inserter operates For instance the Core Inserter can be set up by the user to display the net names of PAD components in the Select Net dialog box Also the Core I
26. enables the tokens for that particular bus If the bus is wider than the tokens specify such as choosing 4 bit tokens for an 8 bit bus the upper bits are assumed 0 for the tokens to apply Figure 4 37 shows such a waveform with the example file in Figure 4 36 applied to a 5 bit bus PII EI ChipScope Analyzer demo Unit 0 File Communication Configure BusiSignal Run Stop Data Window Help sa f 5 k m T SIS l E we exxspeeo wsf zhexxzpxrz mn wanfeesif x Os l 1 f E o ig x uir xzEROY One X Two THREEY FOUR X FIVE E Signal 5 1 f Bignal B l Figure 4 37 Example Waveform with Tokens UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 21 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Bus Bit Ordering The bits in each bus can be ordered top to bottom or bottom to top when computing their value in the wave display window To place the most significant bit at the bottom select Bus Signal Bus Bit Ordering Bottom MSB To Top LSB To place the most significant bit at the top select Bus Signal Bus Bit Ordering Top MSB To Bottom LSB The default bit ordering is bottom to top Figure 4 38 ChipScope Analyzer demo Unit 0 File Communication Configure MEITESEIPHEIM Run Stop Data Window Help f e kim T a Gaup ito Bus Ungroup From Bus Move Lp Mi width Count f Trigger Move Down
27. name of the net that is attached to the corresponding ILA trigger input in addition to the bit position and current match value ChipScope Analyzer demo Unit 0 IDE Xx File Communication Configure Bus Signal Run Stop Data Window Help IE s r leje s sle 2 M0 x x x x o 0 o 9 Trigger Condition mojem Capture One Shot on Trigger Position 0 2047 1000 Ext Out Sample Butter rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 basic Figure 4 20 Setting the Basic Match Comparison Value UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 11 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Extended Match Unit Comparison Value If the match unit Mn where n is 0 or 1 depending on the number of trigger match units in the ILA core is an extended match unit then you can configure both the comparison type and value during trigger setup Figure 4 21 ChipScope Analyzer demo Unit 0 par at Ea File Communication Configure Bus Signal Run Stop Data Window Help HE s i Mo xx x x o o o o 0 0 0 0 Trigger Condition Capture One Shot On Trigger Position 0 2047 1 000 Ext Out T Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 basic Figure 4 21 Setting the
28. ro SN E pesoatas ae steso beens pesotnase E meee oeneseaetee 4 3 porine and POPON sosmeses rna cer rreeeerert etre cer rece tere ere cere r cere 4 4 Closing and Fring Ap 96 OC serasa AE e aE 4 4 Opening and Closing a MultiLINX Connection ssssssessessesesesresesreserersersreseseesessrseeeeses 4 4 Onpnenme a Sotal Port IWIN Xe CONHCOLOR sirere orn an Ran E E S eR Cur tado one uana aan 4 4 OUenme a USB Port MuliLINX C ORHOGEON ssrsriip EISE HEIDI ONU 0000000 NE ENARA 4 5 Cosm TOP Mu LINK CONNECTION ireira rora um E E EUMD ds 4 5 Get nie MULINA Cable Ng OA ON nm 4 5 Opening a Parallel Cable COnneCHON rererere iea E PARU Tox ne Ei eue d amd en io pEE 4 6 ConBegurine the Target DEVICE S amet uuo P NIIS Ipaq ain 4 6 SU Up the Borudary Sgar C HALT serrit Era non a Gud UID D MEM MID M MM dI 4 6 IB ee a Olu 3 plea 7 NE 4 8 Obsercmc Conn onra lon P TOT CSS srna P Snp io pica nies E 4 9 TIS DUA 1 GE 4 9 Openine the T eser Setup IO0 DBE reee E E 4 10 vicinae UP E FON Em 4 11 Basie March Unii COmnpar SOM VATES isaedet Ur htm EES 4 11 UGO005 PN 0401884 v4 2 March 1 2002 www xilinx com V ChipScope ILA Software and Cores User Guide 1 800 255 7778 XILINX Extended Match Unit Comparison Val We secscascdsesdpeneie een eben cosene be odcos ana enia 4 12 Seno Up Pulse Width and Event COUMD usse etas edu os ue bdtep urn ne cUa SPFaE ERU IH Ode PU URS aea Edo US 4 13 Setline Upa Boolean Te
29. small dialog box Figure 4 17 ChipScope Unit X LM 1 IDCODE 80620093 Figure 4 17 Viewing User Defined ID Code Opening the Trigger Setup Toolbar To set up the trigger for a device that has already been configured with a design containing an ILA core select Data Trigger Setup Figure 4 18 ChipScope Analyzer demo Unit 0 File Communication Configure Bus Signal RuniStop PITE window Help z Ha Sislel ae pri Te p Jere In SS TS e am Wt GOTT Alea A 3 CO YD Ye ipe FI VITTHGYY fj WOOGIE ihe ertet STET By SPL WoC Pehoo Mot alles Demo Waveform Successfully opened Parallel Cable port LPT1 Figure 4 18 Opening the Trigger Setup Toolbar After you select Trigger Setup the ChipScope program queries the ILA unit to determine the proper settings for the trigger setup If the device has just been configured then it is queried and the Trigger Setup toolbar appears automatically The parameters associated with the ILA unit appear at the bottom of the ChipScope Analyzer window see Figure 4 19 for example of Trigger Width 8 Signal Count 16 Data Depth 2048 ILA Core Version 1 1 extended match units The Trigger Width Signal Count Data Depth and Extended Features parameters correspond to the ILA core parameters used when the core is generated rigger width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure
30. the ILA will be generated using SRL16 and SRL16E components If the check box is not selected the SRL16 components are replaced with flip flops and multiplexers Note that the default target device family is Virtex Virtex E Spartan II Spartan IIE ILA cores generated for this family will work for all Virtex Virtex E Virtex II Virtex II Pro Spartan II and Spartan HE devices Cores generated for the Virtex II Virtex II Pro family will only work for Virtex II and Virtex II Pro devices selecting the Clock Edge The ILA unit can use either edge of the CLK signal to trigger and store data This option is used to select either the rising or falling edge of the CLK signal as the clock source for the ILA core Selecting the Trigger Type To generate the first part of the ILA core select one of the following trigger types e Trigger separate from data The trigger word is completely independent of the data word e Trigger same as data The trigger and data words are identical This mode is very common in most logic analyzers since users can trigger on any bit in the data word being collected If this selection is made then the TRIG input port of the ILA core can be left unconnected The DATA input port is used as both data and trigger input to the ILA core This mode also conserves CLB and routing resources in the ILA core but limits the data sample word width to the maximum trigger width of 64 bits UGO005 PN 0401884 v4
31. the design Analyzer Menu Features Selecting a Device ILA Unit A single target device i e Virtex Virtex E Virtex II Virtex II Pro Spartan II or Spartan IIE device can contain up to 15 ILA units The host communicates through a separate ChipScope Analyzer window for each ILA unit You can select the current ILA unit only after you connect to the download cable and detect the Boundary Scan chain Select File New ILA Unit Unit n where n is the ILA unit number to choose a specific ILA unit Note that the ILA unit number corresponds to the control port the ILA core is connected to in the case of instantiation or the Unit number in the case of Core Insertion Figure 4 1 shows how ILA Unit 1 is selected ChipScope Analyzer demo Unit 0 B X BE communication Configure Bus Signal Run Stop Data Window Help New ILA Unit d unito alej S ei Save Project As Import Waveform Unit 2 EXO vvaveronn i Unit 3 Close Unit 4 Exit Unit 5 it Unit 7 Unit 8 Unit 9 Unit 10 Unit 11 Unit 12 Unit 13 Unit 14 Successfully opened Parallel Cable port LPT1 Figure 4 1 Selecting a New ILA Unit If the Boundary Scan chain contains multiple devices that can serve as ILA targets then select communication to one of the 15 possible ILA units in the target device using File gt UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 1 ChipScope ILA Software and Cores User Manual 1 800 255 7778
32. unit then logically ORs all of the external trigger output signals and drives them to a single output pin on the device Users can enable each ILA core component to drive each respective external trigger output signal to the ICON core component without resynthesizing the design Capture Modes Each ILA core can capture data independently from all other ILA cores in the design Also the ILA core can capture data using one of two capture modes one shot and on trigger The one shot capture mode uses a single trigger event such as a Boolean or macro combination of the individual trigger match unit events to collect enough data to fill the sample buffer up to 4096 samples The trigger position can be set to the beginning of the sample buffer trigger first then collect the end of the sample buffer collect until the trigger event or anywhere in between The on trigger capture mode uses multiple trigger events to perform repetitive measurements on the design under test Each trigger event can cause a capture of 1 to 16 data samples These repetitive measurements can continue until the captured data fills the sample buffer UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 5 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Tools Description XILINX ILA and ICON Core Resource Usage Tables 1 4 1 5 1 6 and 1 7 show the ILA core and ICON core resource usage Table 1 4 ICON and ILA Core CLB Resource
33. xilinx com 1 800 255 7778 4 22 Analyzer Menu Features XILINX Bus and Signal Coloring Separate colors can be assigned to each bus and signal in the waveform display To choose a color highlight the signal or bus then select Bus Signal Color A color palette opens from which a discrete or customer color can be chosen in a variety of ways A bus and its component signals can have different colors Figure 4 40 ChipScope Analyzer demo Unit 0 File Communication Configure Beet Run Stop Date E EJ gt B T i Group nto Buis Doron erari Bme mof zkxxx kxxz mi Trigger Condition boolean Sample Buffer FULL Bus Signal j Address Move Lp Move Down Rename STOVE li BUS BIET Channel Numbers Signal oad mre E muhal a Import Signal Names 2 hegignal_a _Signal_4 ee Choose Color Swatches HsB Ren 253 8 185 6 E ee ts a 5 Fe et e rs 6n F6 e d 69 3 S69 el GN PSI UR mo RR RR RR SURE 1 17 17117717 mie TES RU ee 71717171717 1 SRS 1315715315313 1 1 ma E ES II _ JS E lees _ PRRs CNN pee eee Te Pe mE Pere Eee eee eee eee dtd dt eee See m B Sample Text Sample Text E EI L Sample Text Sample Text ChipScope Analyzer demo Unit 0 File Communication Configure BusiSignal Run Stop Data Window m 2 eleje Trigger Condition boolean AND SND Capture One
34. 1884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 1 4 ChipScope ILA Tools Description XILINX Trigger Settings The ILA core has two trigger modes basic and extended The basic trigger mode provides up to two trigger match units capable of detecting a single exact match for every trigger condition The extended trigger mode adds the ability to do range matching trigger pulse width duration measurement trigger event counting and if then trigger macros Table 1 3 compares the basic and extended trigger modes Table 1 3 Basic and Extended ILA Trigger Modes Trigger Mode Feature Basic Mode Extended Mode Up to two match units Yes Yes Trigger function combining all match units Yes Yes Match value and edge comparison Yes Yes Match range comparison such as gt 2 lt lt No Yes Trigger pulse duration measurement No Yes Trigger event count measurement No Yes If then trigger macros No Yes External Trigger Description The ChipScope Analyzer software can accept a trigger input signal and generate a trigger output signal for use with external test equipment An external trigger input signal must enter the device on a normal input pin connected to the ICON core unit where it is distributed to each of 15 possible ILA components in the design Similarly each ILA core unit can generate an output signal that is connected to the ICON unit The ICON
35. 2 XILINX The ChipScope Analyzer contains many features that Xilinx FPGA designers need for thoroughly verifying their logic Table 1 2 User selectable data channels range from 1 to 256 and the number of sample sizes ranges from 256 to 16384 effectively doubling any FPGA logic analysis capability on the market today Users can change the triggers in real time without affecting their logic The easy to use ChipScope Analyzer leads designers through the process of modifying triggers and analyzing the data ChipScope ILA Tools Description Table 1 2 ChipScope Features and Benefits Feature to 256 user selectable data channels Benefit Accurately captures wide data bus functionality User selectable sample buffers ranging in size from 256 to 16384 samples Large sample size increases accuracy and probability of capturing infrequent events Separate bus trigger with user selectable width of 1 64 bits Separate trigger bus reduces need for sample storage All data and trigger operations are synchronous to the user clock up to 155 MHz Capable of high speed data capture Trigger conditions are in system changeable without affecting the user logic No need to single step or stop a design for logic analysis Can write waveforms to VCD FBDF and ASCII formats Compatible with Agilent Technologies and other waveform viewers Easy to use graphical interface Guides users through selecting the c
36. B Port MultiLINX Connection If the MultiLINX cable connects to the host computer by way of the USB port then select Communication Open USB Port Figure 4 8 When the connection opens a success message appears in the status bar at the bottom of the ChipScope window At this point ChipScope queries the Boundary Scan chain to determine its composition see Setting Up the Boundary Scan Chain page 4 6 If the MultiLINX connection fails to open a dialog box opens notifying you of the problem ChipScope Analyzer demo ioj x File MenuniuuDEH Configure Bus Signal Run Stop Data Window Help Galele elelel m Reading project file C Program FilestxiliniChipScope Betaidemo cpj Figure 4 8 Opening a USB Connection to MultiLINX Closing the MultiLINX Connection Select Communication Close Port to close the connection to the MultiLINX cable You must re establish a connection to the MultiLINX cable before any communication between the ChipScope program and the ILA units in the target device can resume Getting MultiLINX Cable Information You can upload information pertaining to the MultiLINX cable such as the hardware version memory size etc by selecting Communication Get Cable Information This menu option will also flash the LED on the MultiLINX cable five times and will report UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 5 ChipScope ILA Software and Cores User Manual 1 800 255 7778
37. Cer OPINION aoattersioedtei suia anian anui ultr parb s uUo bod ra SUED OUS 4 14 Setting Up a Macro Trigger CORUILIOM scscsatessessuent siqua bauen pk bsec SY Pelo sime s t UR UE RA UE PaES rat PH NER 4 14 Selechng One Shor CAD Te IOUS ssc cara saet eee escencta taupe battu adbuc bu Ua Dat E ea ene 4 15 Selecting On Trigger Capture Mode NE 4 16 Enone Eana TOO OU PU HN m 4 16 Capture Stalus pg P 4 17 Rimming and Stopping the Tti e sesta esee oerte Udo prone av apasn dvo aha uv ne Uds 4 18 Rirn Armins ihe TREF MR ME OP 4 18 Stoppin e Drar mune Me TTR COT Mu 4 18 Using Buses a d SICIIANGS cswesstsquengasswasvartgeasomtonsy aovet eespabssesa agseantongcanvassevunassenaovsemers inom ranes 4 18 GOT Ie H1 1 LII E aaa UN can peer cus ae a tueaeiaeaaeE 4 18 TOD ie IT FOMO DUS RR rm 4 19 Mooni Buses and SOTA Saer RM 4 19 Changing Bus and Signal Names RR 4 20 DUS DG D1 Men 4 20 IUE arcana ss 4 21 BES RE OATS mM A 4 22 SoTa CMe N UON TI PIAU NEP 4 22 DUS D E a a T S E A E O 4 23 Suo mU LINE TOTS E RR UOI UN BOO NUN BS ONE SICUTI NBI EMEND PUDOR NN ents 4 24 Navigating the Waveform Window 3 usen obucispes tetro st bro era Sent bU Meer RUrEo td Upeqes 4 25 MEUSE EI epi gH Um 4 25 ZOOS TID GG OUT E 4 25 goles ical vri hia E EU 4 27 DOU Tro iiis COC S O MUNERE NEN 4 27 2030 7 M 4 27 Cee rae AMO Trier NN 4 28 Chancmv WOO Window
38. DTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Logic Company is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no rep resentation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of mer chantability or fitness for a particular purpose Xilinx assumes no obligation to correct any errors contained h
39. Hold down the shift key and use the mouse to select one or more ungrouped signals in the Bus Signal display then select Bus Signal Group Into Bus When the text input box opens enter a name for the UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 18 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX new bus then click Enter Names must be unique and may contain only letters numbers and underscores Figure 4 31 ChipScope Analyzer demo Unit 0 File Communication Configure MEISETPITHREIMS Run Stop Data e kimiT 5 T rrr enr BITE wok sRerspeoo us i Ma Width count f Trigger Mare Morsi Capture One Shot On Trigger sa Eename STOVE BUS BIET Channel Numbers Color baad tokens Import Signal Mames Signal 5 idi Se ChipScope Analyzer demo Unit 0 File Communication Configure Bu zaj 5 LMT Sys mo gt Ibex xf xxx of Capture one Shot On Trigger Positi Bus Signal X amp Radress EN 2 Signal_4 1 1 Mean Figure 4 31 Grouping Signals into a Bus Ungrouping Signals From a Bus To ungroup a signal from a bus highlight a bus in the Bus Signal display window then select Bus Signal Ungroup From Bus This removes the bus and places all its signals in the root level Figure 4 32 ChipScope Analyzer demo Unit 0 File Communication Configure MEINESPSPHEIMS RuniStop Da aex e PL MIT S
40. IEI SISA E ORE SANT IEU S AS ASRS ODS APES ONS HPS Signal_10 i Signal 11 0 0 Signal_12 il il Signal 13 0 0 Signal 14 al 1 Signal_15 1 il VTRTEIHIMUEIHINUEMIHIEUTUEIIATCISENEIRYTE S ETR RE CAE I CIE v REN EEI I NER Ter AE E RE EE SJE BEE er LL m new waveform x 5 4 9 6s 4 A x 0 717 had MEE HEN Figure 4 45 Zooming out from the Waveform Display UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 26 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX To view the entire waveform display select Data Fit Window Figure 4 46 ChipScope Analyzer demo Unit 0 ile E3 File Communication Configure Bus Signal Run Stop Window Help zz f m T SISl S 2 5 Trigger Setup Zoom In To gt M1 Width Count Trigger Condition boolean Zoom In Capture One Shot On Trigger Position 0 2047 16 Zoom Out Bus Signal x 0 ROME Led Zoom Area E Signal_0 01 nmm mun E Signal 1 oo nnn ToggleTime State Display Signal 2 1 jo nnnnnnnnnnnn SetClock Period Signal_3 oo UU Ur Ur LF Plot Values Signal_4 1 jo LJ LT L Demo Waveform Signal 5 igo I peces EHE Signal B o ja NENNEN us MEE o ES Signal 7 1 fil E IEEE Signal 8 10 c D sm a Signal 8 o ifo TET TEE Signal 10 al Signal_11 0 Signal 12 TIME
41. ME sparc file found in the installation archive After downloading the tools in the form of a compressed tape archive file e g ChipScope_V_Ri_sol tgz or ChipScope_V_Ri_sol zip 1 Make sure that the gzip and tar programs are in your executable path 2 Change directory to the directory that will contain the ChipScope files 3 Un zip and un tar the ChipScope V Ri sol tgz file using the following command Gzip cd ChipScope V Ri sOl tgz tar xvi This will create a chipscope directory under the current working directory 4 Setup the CHIPSCOPE environment variable to point to the chipscope installation For csh UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 10 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Software Installation XILINX setenv CHIPSCOPE path to chipscope parent chipscope For sh gt set CHIPSCOPE path to chipscope parent chipscope gt export CHIPSCOPE 5 Run the ChipScope Core Inserter and ChipScope Core Generator tools ChipScope Core Inserter SCHIPSCOPE inserter bin inserter sh ChipScope Core Generator SCHIPSCOPE inserter bin gengui sh UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 11 ChipScope ILA Software and Cores User Manual 1 800 255 7778 XILINX Chapter 2 Using the ChipScope Core Generator Core Generator Overview The ChipScope Core Generator tool offers is a graphical user interface to generate the Integrated
42. N Options UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 4 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features Choosing ILA Parameters and Options Notice in Figure 3 3 that a new ILA unit has been created in the device hierarchy on the left The next step is to set up the ILA unit Figure 3 4 shows a sample of the ILA options and parameters Clock Settings DEBES Select Integrated Logic Analyzer Options r Clock Settings Sample On Rising Edge Of Clock Trigger Settings Trigger Same As Data Trigger Width fe r Data Settings Data Depth 2048 Data Width 116 m r Match Settings Extended Matching Match Units Figure 3 4 ILA Options and Parameters XILINX The ILA unit can use either edge of the CLK signal to trigger and store data This option is used to select either the rising or falling edge of the CLK signal as the clock source for the ILA core Trigger Settings Trigger Same as Data Use this option when the signals that you want to trigger on are exactly the same signals that you want captured This option also conserves CLB and routing resources in the ILA core but limits the data sample word width to the maximum trigger width of 64 bits This is the common mode with most logic analyzers Notice that when this option is checked the Data Width field disappears and Trigger Width is renamed to
43. OTES secessit ttencem eee 2 3 Choose tbe Pile Destination uses a etitm Sra eU ans n En O PEU ENR 2 9 Selecting the Target Device Family oasis una ORE pvS e e DIM a 2 4 Delse mp Hec locks EO DEus ten e fen ent rere en rer s PM DESEE E MEME 2 4 De lect The THIS SOIT DES eed eei qeptiod dS a M UE 2 4 5eleche the Tigger Match Umt Ty DO oissersiihtoes tust paioseust inea Eve bbn tere RER Dre Ecos EO teu OUS 2 5 Selecting the Number of Trigger Match Units sese 2 5 ve Senda Data Depienne R RER 2 5 Eoee the A Guu a a E E ee eer etree TROU PIDEN DEDE 2 6 belecHun the T2585 Sor Widi D eee enn a QUUM rene DER DUDEN at D NOn pu UU cm 2 6 Selecting the Instanhaton Te miplateu sei Mop ESHBI Pop ORI pU DUM BEN NETS tS cH DUN a 2 6 Generar THO a a endete sinu CDM oig MUN UN edP M NIU 2 7 e tied o m ipo m 2 7 UGO005 PN 0401884 v4 2 March 1 2002 www xilinx com ChipScope ILA Software and Cores User Guide 1 800 255 7778 XILINX Chapter 3 Using the ChipScope Core Inserter Core Inserter OVeEVIP W socera etna dti dois uma een ad CUN Met DE 3 1 ChipScope Core Inserter Menu Features see 3 1 WV OER WE Te OJ CUS quasiment o DN san E A ean OH he o DS MEN UNDER M 3 1 Qu iari Een VIII ea uu OFC E NNT A oyeneseanabeuaiess 9 2 US TIO Co D 3 2 P N T e E MEER 3 2 Taertino and SOOO ILA Ssenari EE E A N 3 2 OG a a A E A A 3 2 Trn EC O ar E E E E E E E Some bau ipe 3 2 E E CO T TET 3 2 Specifying npu utand Output FileS
44. Supported synthesis tools are e Exemplar LeonardoSpectrum e Synopsys FPGA Compiler e Synopsys FPGA Compiler II e Synopsys FPGA Express e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the ILA core without any example files deselect the Generate Example Files check box UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 2 6 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ILA Core XILINX Generating the Core After entering the ILA core parameters click Generate Core to create the netlist and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process The user can select to either go back and specify different options or Start Over Using the ILA Core To instantiate the example ILA core HDL files into your design use the following guidelines to connect the ILA core port signals to various signals in your design e Connect the ILA core s CONTROL port signal to an unused control port of the ICON core instance in the design e Connect all unused bits of the ILA core s data and trigger port signals to 1 This prevents the mapper from removing the unused trigger and or data signals and also avoids any DRC errors during the implementation
45. To O Marker same as Data Go To gt O Marker e Go To Trigger same as Data gt Go To Trigger e Zoom In same as Data Zoom In e Zoom Out same as Data Zoom Out e Zoom Area same as Data Zoom Area e Fit Window same as Data Fit Window UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 28 ChipScope ILA Software and Cores User Manual 1 800 255 7778
46. Trigger Data Width Trigger Width This specifies the width of the trigger bus or the width of the Trigger Data bus when trigger is the same as data Valid numbers are even integers from 2 to 64 UG005 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 3 5 ChipScope Core Inserter Menu Features XILINX Data Settings Data Depth The maximum number of data sample words that the ILA core can store is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit For the Virtex Virtex E Spartan IL and Spartan IIE device families you can set the data depth to one of five values shown in Table 3 1 Table 3 1 Maximum Data Widths Virtex Virtex E Spartan II Spartan IIE Devices Depth Depth Depth Depth Depth 256 512 1024 2048 4096 1 block RAM 16 8 4 2 1 2 block RAMs 32 16 8 4 2 4 block RAMs 64 32 16 8 4 8 block RAMs 128 64 32 16 8 16 block RAMs 256 128 64 32 16 32 block RAMs 256 128 64 32 64 block RAMs 256 128 64 128 block RAMs 256 128 256 block RAMs 256 For the Virtex II and Virtex II Pro device families you can set the data depth to one of six values shown in Table 3 2 Table 3 2 Maximum Data Widths Virtex II and Virtex II Pro Devices Depth Depth Depth Dept
47. Usage in Virtex II Virtex II Pro Devices Trigger Data Width LUTs Flip Flops 8 108 168 16 120 200 32 144 264 Note A single ILA core with trigger same as data a single basic match unit and 512 data samples was used in this example Table 1 5 ICON and ILA Core Block RAM Resource Usage in Virtex II Virtex II Pro Devices Trigger Data Samples Data Width 512 1024 2048 4096 8192 16384 s8 i1 13 a3 2 2 s8 16 1 1 2 4 8 16 32 1 2 4 8 16 32 64 2 4 8 16 32 64 Table 1 6 ICON and ILA Core CLB Resource Usage in Virtex Virtex E Spartan II Spartan IIE Devices Trigger Data Width LUTs Flip Flops 8 106 197 16 118 229 32 145 295 64 194 425 Note A single ILA core with trigger same as data a single basic match unit and 256 data samples was used in this example UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 6 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Tools Description XILINX Table 1 7 ICON and ILA Core Block RAM Resource Usage in Virtex Virtex E Spartan II Devices Trigger Data Samples Data Width 256 512 1024 2048 4096 8 1 1 2 4 8 16 1 2 4 8 16 32 2 4 8 16 32 64 4 8 16 32 64 oynthesis Insertion Requirements Users can modify many options in the ILA and ICON cores without resynthesizing in the case of the Co
48. ange it the user can either type a new path in the field or choose Browse to navigate to a new destination Selecting the Target Device Family The default target device family is Virtex Virtex E Spartan II Spartan IIE ICON cores generated for this family will work for all Virtex Virtex E Virtex II Virtex II Pro Spartan II and Spartan IIE devices Cores generated for the Virtex II Virtex II Pro family will only work for Virtex II and Virtex II Pro devices UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 2 1 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ICON Core XILINX Entering the Number of Control Ports The ICON core can communicate with up to 15 ILA core units at any given time However no ILA core unit can share its control port with any other ILA unit Therefore the ICON core needs up to 15 distinct control ports to handle this requirement Users can select the number of control ports from the Number of Control Ports pull down list Enabling the External Triggers Users can configure the ICON core to implement an external trigger input and an external trigger output i e two separate pins to trigger external test equipment To enable instantiation of the external input and output trigger pins select the appropriate Enable External Trigger Input and Enable External Trigger Output check box If external trigger input or output pins are enabled then the pin locations that ar
49. atures XILINX Navigating the Waveform Window s Centering the Waveform Center the waveform display around a specific point in the waveform by selecting Data Go To then centering the waveform display around the X and O markers as well as the first trigger position Figure 4 42 ChipScope Analyzer demo Unit 0 OF XI File Communication Configure Bus Signal Run Stop Window Help e S Trigger Setup Zoom In To b o O Marker M1 aen E EE boolean Zoom in oe Capture One Shot On Trigger Position 0 2047 1 fe e Zoom Out Bus Signal x o EEan pues 9i Zoom Area Signal_0 o 1 ATMA 2 Eitvindow Signal_1 o jio LIU TeggleTime State Display Signal_2 1 fo nnnnnnnnnnnn Set Clock Period Signal_3 oio SES Signal_4 1 0 dpa ipm e a Signal 5 1g4o p e i uem Signal 5 0 10 LEE IND ONT sx MES Signal 7 il 1 Signal_8 140 E G Signal 8 0 10 EE E EE ET EIE LER E EEA Signal_10 0 1 Signal_11 Signal 12 al i1 Signal 13 0 0 Signal_14 al I Signal 15 il l S EE VEE IE _ _ lt Figure 4 42 Centering the Waveform Display Zooming In and Out Select Data Zoom In to zoom in to the center of the waveform display Figure 4 43 ChipScope Analyzer demo Unit 0 EST x File Communication Configure LE Window Help Trigger Setup P Zoom Out Bus Signal 320 Zoom Area
50. be MO then not EXT Figure 4 25 do the following e Click the third button four times to select EXT i e not EXT e Click the first button one time to select MO e The middle button is automatically set to THEN UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 14 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Clicking the first and or third button until it is blank effectively removes the match condition or external trigger input from the macro equation However use the boolean equation if neither condition in the macro equation is used ChipScope Analyzer demo Unit 0 i BI XI File Communication Configure Bus Signal ee Data Window Help Capture One Shot On 000 Ext Out Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 extended Figure 4 25 Selecting the Macro Trigger Condition Selecting One Shot Capture Mode The One Shot capture mode captures an entire sample buffer of data once the trigger condition is satisfied This capture method allows you to capture data both before and after the trigger condition is satisfied Click One Shot in the trigger toolbar Figure 4 26 to select the One Shot capture mode During the One Shot capture mode you can set the trigger position to anywhere from the beginning of the capture buffer Posi
51. cable e If using the MultiLINX download cable Vcc 2 5 5 0V and GND headers must be available for powering the MultiLINX cable e If using the Parallel Cable III download cable Vcc 2 5 3 3V and GND headers must be available for powering the Parallel Cable III cable e If using the Parallel Cable III download cable VREF 2 5 3 V and GND headers must be available for connecting to the Parallel Cable IV cable UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 8 ChipScope ILA Software and Cores User Manual 1 800 255 7778 System Requirements XILINX Host System Requirements for Windows NT 98 2000 The ChipScope Analyzer and ChipScope Core Generator tools run on PC systems that meet the requirements outlined in Table 1 10 Table 1 10 Analyzer and Core Generator PC System Requirements Supported Ports OS Memory Environment For MultiLinx or Parallel Cable Ill or IV Windows NT 4 0 64 MB RS 232 Parallel Java Run time Envi t Windows 98 32MB RS 232 or USB Parallel puso aaah dir E 1 3 1 automatically Windows98SE 32MB RS 232 or USB Parallel included in ChipScope 4 21 software Windows 2000 32 MB RS 232 or USB Parallel installation Notes 1 Tousethe MultiLINX USB interface under Windows 98 Second Edition or Windows 2000 the correct driver must be used The updated driver is included in all versions of Xilinx software beginning with 3 1i Service Pack 1 In addition to t
52. configuration mode the Configuration Selection dialog box Figure 4 14 opens This dialog reflects the configuration choice and defaults to a blank entry for the configuration file ChipScope supports MCS BIT and RBT files as inputs ChipScope Unit 0 Configuration ade TAG configuration File Directory Select Mew File Figure 4 14 Selecting a Part UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 8 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX To select the BIT file to download click on Select New File The Open Configuration File dialog box Figure 4 15 opens Using the browser select the device file you want to use to configure the target device It is important to select a BIT file generated with the proper BitGen settings For example if the target device is configured using the JTAG port then use the BitGen option g StartupClk JtagClk when creating the configuration file Once you locate and select the proper device file click Open to return to the Configuration Selection dialog Open Configuration File Look in E simplicity EN e ila v3UL jtag mces File name la 300 mes Files of type all Files Cancel Figure 4 15 Opening a Configuration File Once the mode and BIT file have been chosen click OK to configure the device Observing Configuration Progress While the device is being configure
53. d the status of the configuration is displayed at the bottom of the ChipScope window If using the MultiLINX cable first the cable is initialized for JTAG configuration download Next the progress of the bitstream download is displayed If the DONE status is not displayed a dialog box opens explaining the problem encountered during configuration If the download is successful the target device is automatically queried for the ILA core and the Trigger Setup toolbar is displayed Displaying JTAG ID Codes One method of verifying that the target device was configured correctly is to upload the device and user defined ID codes from the target device For instance to upload and display the user defined ID code i e the 8 digit hexadecimal code that can be set using the BitGen option g UserID select Configure Show USERCODE Figure 4 16 Use Configure Show IDCODE to display the fixed device ID code ChipScope Analyzer demo Unit 0 OF x File Communication IPMN eusisignal Run Stop Data Window Help ajs 5 gt Boundary Scan Setup ale JTAG Configuration Jave g We sendal sonia Show IDCODE Successfully opened Parallel Cable port LPT1 DONE Figure 4 16 Uploading User Defined ID Code UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 9 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX The ID codes are displayed in a
54. e MultiLINX cable is supported at a time Opening a Serial Port MultiLINX Connection If the MultiLINX cable connects to the host computer by way of the serial port then select Communication Open Serial Port Figure 4 6 ChipScope Analyzer demo OF xi File Mein Configure Bus Signal Run Stop Data Window Help USB MultiLINX Cable Parallel Cable Hose Pon Sei abe iiotniauon Reading project file C Program FilesXilinaChipScope Betaidemo cpj Figure 4 6 Opening a Serial Port Connection to MultiLINX UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 4 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX After you select Communication Open Serial Port a small dialog box opens Figure 4 7 Enter the proper serial port name select the baud rate for the serial port connected to the MultiLINX cable then click OK Make sure you select a port that is not in use by another resource Chip5cope p ow Serial Port Selection Port COM Baud Rate Auto Figure 4 7 Selecting a Serial Port When the connection opens a success message appears in the status bar at the bottom of the ChipScope window At this point ChipScope queries the Boundary Scan chain to determine its composition see Figure 4 11 page 4 7 If the MultiLINX connection fails to open a dialog box opens notifying you of the problem Opening a US
55. e entered in the corresponding text boxes are written to the NCF constraint file of the ICON core If the design does not require external triggers or if there are no usable pins for triggers do not check these boxes Disabling JTAG Clock BUFG Insertion Disabling the JTAG clock BUFG insertion causes the implementation tools to route the JTAG clock using normal routing resources instead of global clock routing resources By default this clock is placed on a global clock resource BUFG To disable this BUFG insertion check select the Disable JTAG Clock BUFG Insertion check box This should only be done if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew Make sure the design is adequately constrained to minimize this skew Including Boundary Scan Ports The BSCAN_VIRTEX primitive has two sets of ports USER1 and USER2 These provide an interface to the Boundary Scan TAP controller of the Virtex or Virtex E device Since the ICON core uses only the USERI port for communication purposes the USER2 port signals are available To use the USER2 interface to the BBCAN VIRTEX primitive select the Include Boundary Scan Ports check box Note The Boundary Scan ports should be included only if the design needs them If they are included and not used some synthesis tools do not connect the ICON core properly causing errors during the synthesis and implementation stages of dev
56. e trigger states of all ILA cores in the design Enable External Trigger Output Enabling the external trigger output causes a PAD to be added to the design the pin location specified in Figure 3 3 is added in the NCF file that is automatically generated for the ICON core This signal can be used in the ChipScope Analyzer to trigger the ILA cores Disable JTAG Clock BUFG Insertion Disabling the JTAG clock BUFG insertion causes the implementation tools to route the JIAG clock using normal routing resources instead of global clock routing resources By default this clock is placed on a global clock resource BUFG To disable this BUFG insertion check select the Disable JTAG Clock BUFG Insertion check box This should only be done if global resources are very scarce placing the JTAG clock on regular routing even high speed backbone routing introduces skew Make sure the design is adequately constrained to minimize this skew After selecting the desired ICON options Figure 3 3 click Next CE ChipScope Core Inserter base cdc n loj x File Edit Insert Help Dux id so kk 9 I DEVICE A Select Integrated Controller Options Parameters UNITO ILA V Enable External Trigger Input Pin Location T 54 v Enable External Trigger Output Pin Location 7 Disable JTAG Clock BUFG Insertion Previous Next gt NewiLAUnit essages Read Project File E projects la usage testibase cdc I s Fa Figure 3 3 ICO
57. ecting one match unit conserves resources while still allowing some flexibility in triggering The number of Trigger Match Units can be set to either one or two Selecting two trigger match units allows a more flexible trigger condition equation to be a combination of both match units Selecting the Data Depth The maximum number of data sample words that the ILA core can store is called the data depth The data depth determines the number of data width bits contributed by each block RAM unit used by the ILA unit For the Virtex Virtex E Spartan II and Spartan IIE device families you can set the data depth to one of five values as shown in Table 2 2 Table 2 2 Maximum Data Widths Virtex Virtex E Spartan II Spartan IIE Devices Depth Depth Depth Depth Depth 256 512 1024 2048 4096 1 block RAM 16 8 4 2 1 2 block RAMs 32 16 8 4 2 4 block RAMs 64 OZ 16 8 4 8 block RAMs 128 64 32 16 8 16 block RAMs 256 128 64 92 16 32 block RAMs 256 128 64 32 64 block RAMs 256 128 64 128 block RAMs 256 128 256 block RAMs 256 UG0O05 PN 0401884 v4 2 March 22 2002 www xilinx com 2 5 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ILA Core XILINX For the Virtex II and Virtex II Pro device families you can set the data depth to one of six values as shown in Table 2 3 Table 2 3 Maximum Data Widths Virtex II Virtex II Pr
58. elopment selecting the Instantiation Template After selecting the parameters for the ICON core you can construct an instantiation template Click Next to view the Sample Code Generation Options then select which synthesis tool and language to use The synthesis tools supported are e Exemplar LeonardoSpectrum e Synopsys FPGA Compiler e Synopsys FPGA Compiler II M e Synopsys FPGA Express e Synplicity Synplify e XST Xilinx Synthesis Technology Specifically tailored attributes and options are embedded in the HDL instantiation template for the various synthesis tools To generate the ICON core without any example files deselect the Generate Example Files check box UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 2 2 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ILA Core XILINX Generating the Core After entering the ICON core parameters click Generate Core to create the EDIF netlist NCF constraint file and applicable code examples A message window opens the progress information appears and the CORE GENERATION COMPLETE message signals the end of the process The user can then either go back and respecity different options or Start Over Using the ICON Core To instantiate the example ICON core HDL files into your design use the following guidelines to connect the ICON core port signals to various signals in your design e Connect one of the ICON core s unused CONTROL
59. emo Unit 0 Ol xi File Communication Configure Bus Signal Run Stop Data Window Help Plait 9 MoO X X X X X X X X Trigger Condition E Capture One Shot _On Trigger Position 0 2047 0 Ext Out 7 Sample Buffer EMPTY External Trigger Output rigger Immediate DONE Figure 4 28 Enabling the External Trigger Output UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 16 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Capture Status Window After you arm the trigger by selecting Run Stop Run the status of the ILA unit appears in the Sample Buffer display area with one of the following values e ARMED The trigger is currently armed and waiting for an occurrence of the trigger condition e value A number value between 1 and Sample Depth 1 that represents how many data samples have currently been captured e FULL The capture storage is full and the capture process has ended e STOPPED The ILA unit has been halted by the act of stopping the acquisition During One Shot capture mode once the ILA unit progresses from the ARMED state to the FULL state ChipScope program automatically displays the captured data in the waveform window Figure 4 29 Note that the X axis of the waveform is measured in number of data samples Data sample 0 is always at the location of the t
60. erein or to advise any user of this text of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited Copyright 2002 Xilinx Inc All Rights Reserved UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Software and Cores User Manual UG005 PN 0401884 v4 2 March 22 2002 The following table shows the revision history for this document Version Revision 03 06 00 1 0 Initial Xilinx release 06 30 00 1 1 Deleted ILA Core 0 5 and Earlier section Added Parallel Cable III references 12 15 00 20 Removed Tutorial old Chapter 4 Added Using the ChipScope Analyzer new Chapter 4 Defined ChipScope Tools and its components 08 10 01 3 0 Imported manual into FrameMaker v6 0 Added Signal Name Importing section added Software Requirements section added Project Level Parameters section added Refresing the Netlist section replaced Installing ChipScope Tools section with ChipScope Software Installation section replaced Host System Requirements with two new sections 1 Requirements for Host 5ystems Running Windows and 2 Requirement
61. for the ICON and ILA cores in the ngo directory Save the project before exiting the Core Inserter 5 Rerunthe Translate step When you return to Xilinx ISE Foundation 4 2i you should see that the green check mark by the Translate step has disappeared Double click Translate or right click Translate and select Run The RUN command will start with the new NGO files Note DO NOT select Rerun All as this will rerun Synthesis and the first portion of Translate which will undo the Core Insertion that was just performed 6 Continue with Implementation Make sure to specify the ChipScope Core Inserter bitstream generation options JTAG clock when required enable Readback when creating the bitstream You must follow all of these steps after making any modifications to the HDL source or after deleting any of the implementation data Simply running through the standard ISE flow will not insert the ChipScope cores into the design UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 12 ChipScope ILA Software and Cores User Manual 1 800 255 7778 XILINX Chapter 4 Using the ChipScope Analyzer Analyzer Overview The ChipScope Analyzer tool interfaces directly to the ILA and ICON cores Users can configure their device choose triggers and view the results of the capture on the fly The waveforms and triggers can be manipulated in many ways providing an easy and intuitive interface to determine the functionality of
62. gure DEM Serial MultiLINX Cable 7 Parehe Pui a Fort OE DSTI TG TET E ET USB MultiLIMX Cable i Cancel RU BUE e ETE E SS Parallel Cable Figure 4 10 Opening a Parallel Cable Ill Connection electian LPT Eose Emt Configuring the Target Device s You can use ChipScope software with one or more target devices Virtex Virtex E Virtex IL Virtex II Pro Spartan II or Spartan IIE device families The first step is to set up all of the devices in the Boundary Scan chain Setting Up the Boundary Scan Chain Once ChipScope has successfully communicated with a download cable it automatically queries the JTAG chain to find its composition All Xilinx Virtex E EM 7 II Spartan II IIE Spartan XL 9500 XL XV 4000XL XLA 18V00 CoolRunner CoolRunner II and System ACE devices are automatically detected The entire IDCODE can be verified for Virtex Virtex E Virtex EM Virtex II Virtex II Pro Spartan IIE and Spartan II devices To view the chain composition select Configure Boundary Scan Setup A dialog appears with all detected devices in order For devices that are not automatically detected the IR Instruction Register length must be specified to insure proper communication to UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 6 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX the ILA and ICON cores This information can be fou
63. gure 3 3 and clicking the New ILA Unit button Parameters for the additional ILA units are set up using the same procedure as above Inserting Cores into Netlist The core insertion step can be invoked by selecting the Insert Insert Core menu option or by clicking on the Insert Core button on the toolbar UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 9 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX Managing Project Preferences The preference settings are organized into three categories Tools ISE Integration and Miscellaneous These preference settings are shown in Figure 3 8 Figure 3 9 and Figure 3 10 respectively CR Edit Preferences External Tool Configuration ISE Integration Miscellaneous rEdif2Ngd Command edir2nod Browse Arguments OK Cancel Figure 3 8 Core Inserter Tools Preference Settings PITT GG WF 80000000 0 p Tools Xilinx Foundation ISE Integration Options a OE Integration Miscellaneous M Enable Foundation ISE 4 1i Project Navigator Integration When Replacing ISE NGD File C Promptthen Backup Backup but Do Not Prompt Cancel Figure 3 9 Core Inserter ISE Integration Preference Settings Cm Edit Preferences Tools Miscellaneous Options ISE Integration 1 Net Browser iscellaneous Show Nets attached to PADS v Show Source Component Instance
64. h Depth Depth 512 1024 2048 4096 8192 16384 1 block RAM 32 16 8 4 2 1 2 block RAMs 64 32 16 8 4 2 4 block RAMs 128 64 32 16 8 4 8 block RAMs 256 128 64 32 16 8 16 block RAMs 256 128 64 32 16 32 block RAMs 256 128 64 32 64 block RAMs 256 128 64 128 block RAMs 256 128 144 block RAMs 144 Data Width if necessary The data width field allows you to specify the width of each data sample stored by the ILA core If the data and trigger words are independent from each other the maximum allowable data width depends on the target device type and data depth with a maximum of 256 However if trigger data the data trigger width must be an even number between 2 and 64 UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 6 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX Match Settings Extended Matching Check the Extended Matching check box if you want to enable a complete set of match options The match options include e Finding one or more occurrences of an exact match of a trigger value or edge e Finding one or more occurrences of a range of trigger values e Detecting contiguous pulse width or non contiguous event count trigger match conditions over a number of clock cycles e Enabling usage in conjunction with other trigger match units to build the trigger condition boolean equation using
65. he requirements outlined in Table 1 10 the ChipScope Core Inserter requires that Xilinx ISE Alliance 4 2i or later or Xilinx ISE Foundation 4 2i or later implementation tools reside on the system Note The Core Inserter is not compatible with the WebPack implementation tools Host System Requirements for Solaris 2 6 2 7 and 2 8 The ChipScope Core Inserter and ChipScope Core Generator tools run on SPARC workstations that meet these minimum requirements e Solaris 2 6 27 or 2 8 operating system capable of running Sun Java 1 3 See the README sparc file in the ChipScope Core Inserter installation directory for more details e Xilinx ISE Alliance 42i or later or Xilinx ISE Foundation 4 2i or later implementation tools e LD_LIBRARY_PATH environment variable must point to the Xilinx shared libraries e XILINX environment variable must point to the Xilinx tool installation path e Path variable must include XILINX bin sol directory Note The Xilinx WebPACK implementation tools are not supported by the ChipScope 4 21 software UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 9 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Software Installation XILINX ChipScope ILA Software Installation Installing ChipScope ILA Software for Windows NT 98 2000 After downloading the ChipScope Tools in the form of a self extracting executable file 1 e ChipScope V Ri pc exe 1 Choose Start Run
66. iine ueris aus UMP ia 1 8 Dposre NOS mete kc asso opt II S AI Um DE UVP nU ete EUN PUEDE UU 1 8 Host System Requirements for Windows NT 98 2000 eese 1 9 Host System Requirements for Solaris 2 6 2 7 and 2 8 sssssssssssssssseeee 1 9 ChipScope ILA Software Installation see 1 10 Installing ChipScope ILA Software for Windows NT 98 72000 ss 1 10 Installing the Java Run time Environment for Windows NT 98 2000 1 10 Installing MultiLINX USB Driver for Windows 98 2000 eee 1 10 Installing ChipScope Software for Solaris 2 6 2 7 and 2 8 sss 1 10 Chapter 2 Using the ChipScope Core Generator Core Generator C Vebyle Woo sossnaseneaeddityndasetuRstte di pnu imet ceperint ceptbU i ooaenhs 2 1 Generating an ICON Core sse 2 1 Choosing The File Destination oos Sn eas nyar a VE eae US FLUR hes equi uto eU M URN CH UU US 2 1 Selecting the Target Device Family esses eene 2 1 Entemie the Number Of Control POEIS esp esteso eate ttr eedem tutti Peur tems arais 2 2 Enabling th External Lig gers sssrinin aaa FUNEM UE ente PN oar qas 2 2 Disabling JTAG Clock BUFG Insertion eese nennen 2 2 Including Boundary Scan Ports eese eene 2 2 pelecting the Instantiation Template ioter buo testor eo a 2 2 Guia do x M 2 3 Uae d GE Gro cm 2 3 Generating an ILA C
67. ion Trigger Event Count automatically resets after the match condition is satisfied ChipScope Analyzer demo Unit 0 IDE XI File Communication eae DEMN unae Data Window Help SERE a ar a AND CT Width Count f1 Trigger Condition boolean MO Trigger Event Count Capture one Shot On Trigger Position 0 204 7 0 o Est Out v Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure 4 23 Selecting the Trigger Event Count UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 13 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX setting Up a Boolean Trigger Condition The Trigger Condition field describes how the match units MO M1 and the external trigger input EXT can be combined to form an overall trigger condition Both basic and extended trigger match units can build boolean equations from the available match units and the external trigger input to form the overall trigger condition Select the boolean trigger condition type by choosing Boolean from the pull down menu not available in the basic trigger match type case To designate the equation click the buttons to the immediate right of the Trigger Condition field in the trigger setup toolbar For instance if you want the trigger condition boolean equation to be not MO or EXT Figu
68. ipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 3 8 ChipScope Core Inserter Menu Features XILINX The Clock Data and Trigger inputs of the ILA core appear in the tabbed panel at the upper right of the Select Net dialog box Nets that are selected at a given level of hierarchy can be connected to inputs of the ILA core by following these steps 1 In the lower left table of the Select Net dialog box select the net s that you want to connect to the ILA core Note You can select multiple nets to connect to an equivalent number of ILA core input connections Hold down the Shift key and use the left mouse button to select contiguous nets Use a combination of the Ct r1 key and left mouse button to select non contiguous nets 2 Inthe upper right tabbed panel of the Select Net dialog box the desired ILA core input category Clock Trigger Data or Trigger Data if trigger is same as data 3 Inthe right hand table of ILA core inputs select the channel s that you want to connect to the selected net s Note You can select multiple ILA core inputs to connect to an equivalent number of nets Hold down the Shift key and use the left mouse button to select contiguous ILA core inputs Use a combination of the Ct r1 key and left mouse button to select non contiguous ILA core inputs 4 In the lower right part of the Select Net dialog box click on the Make Connections button to make a connection between
69. lyzer tool can use either the MultiLINX Parallel Cable III or Parallel Cable IV cables to communicate with the target devices in the Boundary Scan chain of the board under test Table 1 9 Download Cable Description Download Cable Features MultiLINX e Uses the USB port found on newer PCs e Downloads at speeds up to 12 Mb s throughput e Supports communication through the PC s RS 232 serial port at speeds up to 57 6 kb s e Contains an adjustable voltage interface that enables it to communicate with systems and I Os operating at 5V 3 3V or 2 5V Parallel Cable III or IV e Uses the parallel port i e printer port to communicate with the Boundary Scan chain of the board under test Note The MultiLINX Parallel Cable III and Parallel Cable IV cables are available from Silicon Xpresso Cafe from www xilinx com choose Buy Online Programming Cables Board Requirements For the ChipScope Analyzer and download cable to work properly with the board under test the following board level requirements must be met e One or more Virtex Virtex E Virtex II Virtex II Pro Spartan II Spartan IIE target devices must be connected to a JTAG header that contains the TDI TMS TCK and TDO pins e If another device would normally drive the TDI TMS or TDI pins of the JTAG chain containing the target device s then jumpers on these signals are required to disable these sources preventing contention with the download
70. m three types of names a long name in which the options are specified in the component name a short name ila edn or a custom name for the netlist the component name will be changed accordingly Either a long name or a custom name should be chosen if multiple ILA cores with different parameters are used in the design The long filename indicates the various parameters specified for the ILA core Table 2 1 shows the meaning of the abbreviations in a long filename Table 2 1 A Long Filename Abbreviations Abbreviation Meaning ddx Data Depth of size x dwx Data Width of size x twx Trigger Width of size x teqd Trigger Equals Data ex or bx Extended or Basic Matching with x Units UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 2 3 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Generating an ILA Core XILINX Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ILA core is optimized for the selected device family Use the pull down selection to change the device family to the desired architecture Note that the default target device family is Virtex Virtex E Spartan II ILA cores generated for this family will work for all Virtex Virtex E Virtex II and Spartan II devices Cores generated for the Virtex II family will only work for Virtex II devices The Use SRL16 s check box is used to select whether or not
71. may be triggered at the same time by configuring each trigger in turn There is no current way to combine the waveform display or trigger setup amongst separate ILA units Working with Projects Projects hold important information about the ChipScope program state such as signal naming signal ordering bus configurations and trigger conditions They allow you to conveniently store and retrieve this information between Analyzer sessions When you first run the ChipScope Analyzer tool the Select Project dialog box Figure 4 3 opens allowing you to create a new project or open an existing project ChipScope Ea Select Project Open an Existing Project More Projects ciila example Create a new Project Figure 4 3 Selecting a Project UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 2 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Creating A New Project To create a new project select Create a new Project Figure 4 3 and click OK In the Choose New Project File dialog box Figure 4 4 enter a new project filename name using the cpj extension and click Open ChipScope Choose New Project File EES Look in Ej example E a Counter 6 cpi Files of type all Files Cancel Figure 4 4 Creating a New Project Opening An Existing Project To open an existing project select it from the list of recently opened pr
72. nd in the device s BSDL file The following example has a System ACE controller XCV50 Virtex FPGA and XC2V1000 Virtex II FPGA in a chain see Figure 4 11 UserID s can be read out of the ILA target devices only the XCV50 and XC2V1000 devices in this example by selecting Read User IDs ChipScope Analyzer E x mJTAG Chain Device Order xCV50 lora 0083 XC2V1000 TEE Index Name Device Name _ Length Device ID User ID D System_ACE 0a001093 1 2 Advanced gt gt gt i Read User IDs Figure 4 11 Boundary Scan Setup Window The ChipScope Analyzer tool automatically keeps track of the TAP state of the devices in the Boundary Scan chain by default If the ChipScope Analyzer is used in conjunction with other Boundary Scan controllers such as the System ACE CF controller or processor debug tools then the actual TAP state of the target devices can differ from the tracking copy of the ChipScope Analyzer In this case the ChipScope Analyzer should always put the TAP controllers into a known state e g the Test Logic Reset state before starting any Boundary Scan transaction sequences Clicking on the Advanced button on the Boundary Scan Setup dialog box reveals the parameters that control the start and end states of Boundary Scan transactions see Figure 4 12 Use the second parameter if the Boundary Scan chain is shared with other Boundary Scan controllers ChipScope Analyzer E x
73. nserter can be set up by the user to disable the display of source component instance names source component types and base net driver types in the Select Net dialog box The Core Inserter project preferences can also be reset by the user to the installation defaults by clicking on the Reset button Using Core Inserter 4 2i with Command Line Implementation Since the Core Inserter generates a file of a different format than synthesis an NGO file instead of an EDIF or XST netlist the implementation flow is slightly different If you use the command line use the NGO file produced by the Core Inserter instead of the EDIF or XST netlist For JTAG configuration ngdbuild sd netlist path p part type base ila ngo map base ila par ol 5 w base ila base ila bitgen w g UserID user ID g StartupClk JTAGClk base ila base ila Using Core Inserter 4 2i with Xilinx ISE Foundation 4 21 The Core Inserter 4 2i with Xilinx ISE Foundation 4 2i implementation tools require some flow manipulation to ensure the correct files are implemented To insert ChipScope cores via the ChipScope Core Inserter into a design processed by Xilinx ISE Foundation 4 2i follow these steps 1l Synthesize and Translate the design After creating a project and adding the HDL or EDIF XST source files Synthesize if required for the selected flow and Translate the design by double clicking Translate under Implement Design 2 Runthe ChipScope Core Inser
74. o Devices Depth Depth Depth Depth Depth Depth 512 1024 2048 4096 8192 16384 1 block RAM 32 16 8 4 2 1 2 block RAMs 64 32 16 8 4 2 4 block RAMs 128 64 32 16 8 4 8 block RAMs 256 128 64 32 16 8 16 block RAMs 256 128 64 32 16 32 block RAMs 256 128 64 32 64 block RAMs 256 128 64 128 block RAMs 256 128 144 block RAMs 144 Entering the Data Width The width of each data sample word stored by the ILA core is called the data width If the data and trigger words are independent from each other then the maximum allowable data width depends on the target device type and data depth However if the data and trigger words are the same then the data trigger width must be any even number in the ranging from 2 to 64 Selecting the Trigger Width The width of the trigger word used by the ILA core is called the trigger width If the data and trigger words are independent from each other then the trigger width can be any even integer in the range of 2 to 64 However if the data and trigger words are the same then both the data and trigger widths must be set to any even integer value in the range of 2 to 64 Selecting the Instantiation Template After selecting the parameters for the ILA core you can construct an instantiation template Click Next to view the Sample Code Generation Options then select which synthesis tool and language to use
75. ojects To browse through all available project files select More Projects When you locate the desired project click Open Saving Projects Projects are automatically saved when you exit the ChipScope software To rename the current project or to save a copy to another filename select File Save Project As Figure 4 5 type the new name in the dialog box and click Save ChipS cope Analyzer ChipScope Analyzer Save Project As EES HIE Communication Save irr test t c E Ell New ILA Unit li Save Project As Import Waveform Export WWaveF orm M aignal Bignal 1 Bignal 2 IE W Save as type A Files Cancel Figure 4 5 Saving a Project UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 3 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Importing and Exporting Only VCD waveforms can be imported You can import the waveform display from a VCD file and export to VCD FBDF and ASCII files The VCD format is a common waveform viewer file format and the FBDF format is compatible with the Agilent Technologies 16700 Series logic analyzers The ASCII format is a text only list format that is well suited to a script parser or spreadsheet import To import a waveform select File Import Waveform A dialog box opens allowing you to browse for waveform files After locating and selecting the desired file click Open
76. ope features without using actual hardware select Data Demo Waveform Changing Waveform Window Focus If more than one ILA unit ChipScope window is open use Window Unit n where n is the ILA unit number to change focus between the windows Viewing the Help Pages The ChipScope help pages contain only the currently opened versions of the ChipScope software and each of the ILA core units Selecting Help About ChipScope Software displays the version of the ChipScope software Selecting Help About ILA Core displays the versions of all of the open ILA units ChipScope Main Toolbar Features In addition to the menu options other ChipScope commands are available on a toolbar residing directly below the ChipScope menu Figure 4 48 ChipScope demo Unit 0 Oy x File Communication Configure Busfsignal Run Stop Data Window Help Figure 4 48 Main ChipScope Toolbar Display The toolbar buttons from left to right correspond to the following equivalent menu options e Open Cable Search JTAG Chain automatically detects the cable and queries the JTAG chain to find its composition e Configure with Last Used Settings same as Configure JTAG Configuration e Trigger Setup same as Data Trigger Setup e Run same as Run Stop Run F5 e Stop same as Run Stop Stop F9 e Trigger Immediate same as Run Stop Trigger Immediate Ctrl F5 e Go To X Marker same as Data Go To X Marker e Go
77. orrect options Up to 15 independent ILA capture cores per device Can segment logic and test smaller sections of a large design for greater accuracy Multiple trigger settings Records duration and number of events along with matches and ranges for greater accuracy and flexibility Downloadable from the Xilinx Web site Tools are easily accessible from the ChipScope Suite UGO005 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 1 3 ChipScope ILA Tools Description Design Flow XILINX The ChipScope Tools design flow Figure 1 2 merges easily with any standard FPGA design flow that uses a standard HDL synthesis tool and the Xilinx ISE Alliance 4 2i or later or Xilinx ISE Foundation 4 2i or later implementation tools ChipScope Core Generator Generale ICON or ILA cores Synthesize design using ICON or ILA cores Instantiate ICON or ILA cores into HDL source Or Connect buses and internal signals Alliance Foundation Implement design Select bitstream Set trigger View waveform ChipScope Analyzer Synthesize design without instantiating ICON or ILA cores ChipScope Core Inserter Insert ICON or ILA cores into synthesized design EDIF netlist CS_ILA_flow_0827 01 Figure 1 2 ChipScope Tools Design Flow UGO005 PN 040
78. pScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Using Tokens Tokens are string labels that can be assigned to a particular bus value These labels can be very useful in such applications as address decoding and state machines Tokens are defined in a separate ASCII file and loaded into the ChipScope Analyzer when appropriate The token file itself tok extension has a very simple format and can be created or edited in any text editor An example token file is provided in the token directory in the ChipScope install path Figure 4 36 token_sample tok Notepad Iof x File Edit Search Help ChipScope Example Token File P Tokens are in the form NAME VALUE where NAHE is the token name and URLUE is the token value hex binary or decimal Ualues are hex by default To specify a radix for the value append b binary u unsigned decimal h hex to the value So valid token definitions would be HEM WURITE c5Xh HEM RERD 1181 Xb TEETH TEHTEIETETETEHTETETETETETETEHETETEHETETETETETETETERETETEHETETETETETETETERETETETETETETETETETETEHETETETETETETETERETETEHETETETE TETTE TomGkiizumzux 3aFILE VERSION 1 6 6 Begin token definitions Figure 4 36 Example Token File Tokens are chosen by selecting a bus then choosing Bus Signal Load Tokens A dialog opens and the user can choose the token file Once the tokens are loaded selecting Bus Signal Show As Token
79. process e fTrigger Same As Data is selected connect the data trigger signal s to the ILA core s DATA port signal The ILA core s TRIG port signal is disconnected in this case In the source code this port can be connected to the same bus as the DATA port or to all 1 s e Make sure the data and trigger source signals are synchronous to the ILA clock signal UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 2 7 ChipScope ILA Software and Cores User Manual 1 800 255 7778 XILINX Chapter 3 Using the ChipScope Core Inserter Core Inserter Overview The ChipScope Core Inserter is a post synthesis tool used to generate a netlist that includes the user design as well as ICON and ILA cores parameterized accordingly The Core Inserter gives users the flexibility to quickly and easily use the ILA functionality to an already synchronized design and without any HDL instantiation ChipScope Core Inserter Menu Features Working with Projects Projects saved in the Core Inserter hold all relevant information about source files destination files core parameters and core settings This allows the user to store and retrieve information about core insertion between sessions CE ChipScope Core Inserter File Edit Insert Help Dee oco g Select Device Options esign Files Input Design Netlist Browse Output Design Netlist Browse Output Directory Browse evice Settings Device Family Selection
80. project with input and output files specified Cm ChipScope Core Inserter Bl x File Edit Insert Help Dea oo 7 DEVICE E Select Device Options Design Files Input Design Netlist E projectstilausage testhase ngc Output Design Netlist E projectsulausage testlbase ila ngc Browse Output Directory E wrojectstilauusage te st ngo Browse Device Settings Device Family Selection Virtex J Virte E Spartan Il Spartan lIE Iv Use SERIES ISE Project Detected Assigning ISE design parameters to project essages KI Figure 3 2 Core inserter Project with Files Specified Project Level Parameters Two project level parameters must be specified for every project Due to the increased depth of Virtex II device block RAM different cores can be generated to take advantage of these deeper RAMs Choose either Virtex Virtex E Spartan II or Virtex II Virtex II Pro depending on the device targeted Also it is possible to generate cores that do not use the SRL16 Shift Register LUT components to do so uncheck the Use SRL16 s check box Selecting the Target Device Family The target FPGA device family is displayed in the Device Family field The structure of the ICON and ILA cores are optimized for the selected device family Use the pull down selection to change the device family to the desired architecture The default target device family is Virtex Virtex E Spartan II
81. rallel Cable III and Parallel Cable IV download cables for communication between the PC and FPGA s The MultiLINX cable supports both USB Windows 98 and Windows 2000 and RS 232 serial communication from the PC see Figure 1 1 page 2 The Parallel Cable III and Parallel Cable IV cables support only parallel port communication from the PC to the Boundary Scan chain UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 1 1 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope ILA Tools Description XILINX Target FPGA with ILA Cores User User Function Function PC with ChipScope Tools ChipScope Analyzer User Function JTAG gt e Figure 1 1 MultiLINX or Parallel Cable Ill ChipScope Block Diagram cs 01 082701 Users can place the ILA and ICON cores into their design in one of two ways e By generating the cores with the ChipScope Core Generator and instantiating them into the source HDL code e By inserting the cores into the post synthesis EDIF netlist using the ChipScope Core Inserter The design is then placed and routed using the Xilinx ISE Alliance 4 2i or later or Xilinx ISE Foundation 4 2i or later implementation tools Next the user downloads the bitstream and analyzes the design with the ChipScope Analyzer software UGO005 PN 0401884 v4 2 March 22 2002 ChipScope ILA Software and Cores User Manual www xilinx com 1 800 255 7778 1
82. re 4 24 do the following e Click twice on the first button to select MO i e not MO e Click once on the third button to select EXT e Click once on the middle button that reads AND to select OR Clicking the button until it is blank effectively removes the match condition or external trigger input out of the boolean equation ChipScope Analyzer demo Unit 0 Iof xi File Communication Configure Bus Signal Run Stop Data Window Help 4 S p m jT ISIS ALel a e mo 1 0 1 ofo o o o Trigger Condition info an EXT Capture One Shot On Trigger Position 0 2047 o Ext Out Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 basic Figure 4 24 Selecting the Boolean Trigger Condition setting Up a Macro Trigger Condition Only the extended trigger match units can build if then macro equations out of the available match units and the external trigger input to form the overall trigger condition Select the macro trigger condition type by selecting the macro type from the pull down menu An example of the if then macro condition is if MO is satisfied and then EXT is satisfied then the overall trigger condition is satisfied To designate the macro equation click on the buttons to the immediate right of the Trigger Condition field in the trigger setup toolbar For instance if you want the trigger condition boolean equation to
83. re Generator or reinserting in the case of the Core Inserter However after changing selectable parameters such as width of the data port or the depth of the sample buffer the design must be resynthesized either with new cores or with the cores reinserted Table 1 8 describes which design changes require this Table 1 8 Design Parameter Changes Requiring Resynthesis Design Parameter Change Resynthesis or Re Insertion Required Change trigger pattern No Running and stopping the trigger No Enabling the external triggers No Changing the trigger signal source No Changing the data signal source No Changing the ILA clock signal Yes Changing the sample buffer depth Yes 1 The ability to change existing trigger and or data signal source is supported by the Xilinx ISE Alliance 4 2i or later FPGA Editor or Xilinx ISE Foundation 4 2i or later FPGA Editor UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com ChipScope ILA Software and Cores User Manual 1 800 255 7778 1 7 System Requirements XILINX System Requirements ooftware Tools Requirements The ChipScope Core Generator and the ChipScope Core Inserter require that Xilinx ISE Alliance 4 2i or later or Xilinx ISE Foundation 4 2i or later implementation tools be installed on your system Note The Xilinx WebPACK implementation tools are not supported by the ChipScope 4 2i software Communications Requirements The ChipScope Ana
84. re and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX The Clock Net connection can be modified by double clicking on the CHO label or highlighting it and clicking Modify Connections The Select Net dialog box now appears see Figure 3 6 Sg Select Net Structure Nets Net Selections ES 4 A clock Trigger Data nt Channel Clock Net Net Name Net Name Y Pattern Filter a Source Instance Source Component Base Type clk c clk_ibuf BUF GP BUF GP cnt 0 cnt obuf 0 OBUF OBUF cnt 1 icnt obuf OBUF OBUF cnt 2 icnt obuf 2 IOBUF OBUF cnt 3 cnt obuf 3 OBUF IOBUF counter 0 icounter 0 FD FD counter 1 counter 1 FD FD counter 2 counter 2 FD FD counter 3 counter 3 FD FD counter 4 lcounter 4 FD FD counter 5 icounter 5 IFD FD counter B icounter 6 FD FD counter 7 counter 7 FD FD counter 8 counter 8 FD FD counter 3 icounter 8 FD FD counter 1 0 counter 1 0 IFD FD counter 11 counter 1 FD FD ra cn 4 ra s mem em nil OK Cancel A i 4e Move Nets Up Remove Connections 4 Move Nets Down Figure 3 6 Select Net Dialog Box This dialog box provides an easy interface to choose nets to connect to the ILA core The hierarchical structure of the design can be traversed using
85. rigger condition ChipScope Analyzer demo Unit 0 mjel E File Communication Configure Bus Signal Run Stop Data Window Help o E Mo zl o1 ofo oo 0 m f xxxx xxxx wo wisn coun M1 width Count fi Trigger Condition boolean mo 210 E Capture One Shot On Trigger Position 0 2047 o Ext Out v Sample Buffer FULL Signal Signal 1 Signal 2 Signal 3 Signal 4 Signal 5 Signal B Signal 7 Ginnal 2 new waveform A X 0 fio Upload DONE Figure 4 29 Viewing the One Shot Capture Mode Waveform UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 17 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX During On Trigger capture mode once the ILA unit progresses from the ARMED state to the FULL state the ChipScope program automatically displays the captured data in the waveform window Figure 4 30 Data sample 0 is always at the location of the first trigger condition ChipScope Analyzer demo Unit 0 IDE x File Communication Configure Bus Signal Run Stop Data Window Help 5 gt u T e cum ejaz mo zf o1 ofo ooo mtf xxxx xxxx Mo WidthfCounth M4 Widthf Counti Trigger Condition boolean mo 10 Capture One Shot On Trigger Position 0 2047 m Ext Out Sample Buffer FULL
86. s for Host Systems Running Solaris 5 6 updated System Requirements section updated Software Installation section updated screen shots 08 27 01 3 1 Added software version to title page miscellaneous non technical text edits 10 19 01 4 0 Changed Alliance Series 3 11 to Xilinx ISE 4 1i Changed Xilinx Foundation Series 3 11 to Xilinx ISE Foundation 4 1i In Chapters 2 and 3 converted Data Depth section text to tables Added Fig 4 11 and Fig 4 12 Replaced Fig 4 13 Miscellaneous edits for clarification 03 22 02 4 2 Updated text graphics and screen shots from 4 1i to 4 2i compatibility UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com ChipScope ILA Software and Cores User Manual 1 800 255 7778 Contents Chapter 1 Introduction Chipseope IL A Tools OVeEvIeW accoeuexonte eM RII eee tee 1 1 ChipScope ILA Tools Description eerte 1 1 Jp cor deo E M 1 4 TGS Ch SUIS a M TA 1 5 Extena To oer DESPON PR n GSGG X 1 5 Ca SIG SS a A stacens sept teases era end cists ne og sau coaseeteomeeteaans eepmeatads 1 5 ILS and ICON Core ResO tree Usage rayses Aa 1 6 Synthesis Insertion IRC GUL CINEINS cocco osse derent inea aN pneus se e uei tedio 1 7 System Requirements 2 essent tnentn entente ennt 1 8 DoIbware FOOLS BOSQUE CPP BIS eee E aa paalo diocl n ibupiibeer i Dom epu Pat DEE 1 8 Communications ReqUIEeIIerite us ceo eit ii dterden Iste D evableS veg
87. sarily in a row If the match conditions must remain satisfied during a specific number of contiguous clock cycles then the match Pulse Width Duration must be measured If it only needs to occur for a specific number of clock cycles not necessarily in a row then the Match Event Count must be measured To measure the Pulse Width Duration click Width Figure 4 22 The match condition is true only if the match condition value is detected for at least n clock cycles in a row where r can be any value from 1 to 65 536 For a subsequent occurrence of the match condition to become satisfied the match condition pulse must return to its non active state in order to reset the Pulse Width Duration detection logic ChipScope Analyzer demo Unit 0 IDE Xx File Communication Configure Bus Signal Run Stop Data Window Help Sr o pi um Sr Gin mo at counfi Mi idih f Counti Trigger Condition boolean oE a an Capture One Shot On Trigger Position 0 2047 i000 Ext Out Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 1 extended Figure 4 22 Selecting the Pulse Width Duration To measure the Trigger Event Count click Count Figure 4 23 The match condition is true only if the match condition value is detected for at least n clock cycles not necessarily in a row where n can be any value from 1 to 65 536 The match condit
88. selecting Edit Remove Unit after choosing which ILA unit to delete Setting Preferences Several ChipScope Core Inserter project settings can be customized by selecting Edit Preferences he preference settings are organized into three categories Tools ISE Integration and Miscellaneous Refer to the Managing Project Preferences page 10 section of this chapter for more information about setting these preferences Inserting the Cores ICON and ILA cores are inserted when the flow is completed or by selecting Insert Insert Core If all channels of all the ILA cores are not connected to valid signals an error message results Exiting the Core Inserter To exit the ChipScope Core Inserter select File Exit Specifying Input and Output Files The ChipScope Core Inserter works in a step by step process The first screen you see Figure 3 1 shows what needs to be specified first the input design netlist Click Browse to navigate to the directory where the netlist resides The Core Inserter will not overwrite the netlist specified Instead a new netlist will be created with the _ila extension appended by default The Output Design Netlist and Output Directory fields are automatically filled UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 2 ChipScope ILA Software and Cores User Manual 1 800 255 7778 ChipScope Core Inserter Menu Features XILINX in however you can modify them as needed Figure 3 2 shows a
89. sisssenimenranio a eine senes 3 2 Project Level ParamietetS Loosnsbesmsmastbiotaptmdb na Ea ER a EE UMS UN MM 3 3 5elecine the Tarzet Device EAE y sresrinesieircairiue n E 3 3 Choosing ICON OPHONS soriire i a E Ei 3 4 Enable TOI TOT TPU aroi E N EE 3 4 Enable External TASI OUP UE CER 3 4 usable JTAG Clock BUFG Toer OM soie tv este iro a aE S sepa ees 3 4 Choosing ILA Parameters and Options sese 3 5 VOC dois mr U 3 5 VE Dr Roc MR E 3 5 B a MM E oie 3 6 A CTI e E E E E E E E E E 3 7 Choosing Net Connections for ILA Signals sese 3 7 Addas IA UN M 3 9 ise Ge Cores Tto DNO US ecrane pu cde aec sesto dubbed diio d premat 3 0 Managing Project Preferences seio vesci sev ttti oep i uev St d vis EOS QUARUM SIM MENU DAE 3 10 Using Core Inserter 4 21 with Command Line Implementation 3 11 Using Core Inserter 4 21 with Xilinx ISE Foundation 4 2i 3 11 Chapter 4 Using the ChipScope Analyzer ura eig ls e 4 1 Analyzer Menu Features eget eee eee M ME 4 1 celleci a Devices DL Ae CUBE eomaenae ome rer rer cement cre re ener ee d dM 4 1 WY Omi WA LUO o EU 4 2 CPA AA INCU 110 BED teasesqncesvasea orti M EIER EENENEI ICM EPRO MUNI MM MEI 4 3 DEBIDA ERISEICUDTOICOE E E DIES NIBSU NOU DOSU ESL PONE UdUaMUE 4 3 WII
90. ter Launch the Core Inserter from Start Programs ChipScope 4 2i ChipScope Core Inserter Note ChipScope Core Inserter version 4 1i and earlier cannot be used with ISE 4 2i 3 Browse for the top level design to fill in the Input Design Netlist Verify the following parameters are set under the Device tab e For Exemplar Synopsys and Synplicity designs Input Design Netlist lt ProjectDir gt lt design gt edf edn Output Design Netlist lt ProjectDir gt _ngo lt design gt ngo Output Directory lt ProjectDir gt _ngo e For XST designs Input Design Netlist lt ProjectDir gt lt design gt ngc Output Design Netlist lt ProjectDir gt lt design gt ngc Output Directory lt ProjectDir gt _ngo UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 3 11 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Using Core Inserter 4 2i with Xilinx ISE Foundation 4 2i XILINX Browse for the input design edf design edn or design ngc file The Core Inserter will detect the presence of the ISE project when it finds the ngo directory and the two output fields will be filled in automatically This can be done only after the Translate step has been run at least once 4 Complete ICON and ILA core insertion in the ChipScope Core Inserter Define ChipScope Core parameters and connect all signals then insert the cores The Core Inserter places new NGO files for the top level as well as
91. the Structure panel on the upper left of the Select Net dialog box AII the design s nets of the selected structure hierarchy level appear in the table on the lower left panel of the Select Net dialog box The following net information is displayed in this table e Net Name The name of the net as it appears in the EDIF netlist The net name may be different than the corresponding signal name in the HDL source due to renaming and other optimizations during synthesis e Source Instance The instance name of the lower level hierarchical component from which the net at the current level of hierarchy is driven The source instance does not necessarily describe the originating driver of the net e Source Component The type of the component described by the Source Instance e Base Type The type of the lowest level driving component of the net The base type is either a primitive or black box component All of the net identifiers described above can be filtered for key phrases using the Pattern text box and Filter button Also nets can be sorted in ascending and descending order based on the various net identifiers by selecting the appropriate net identifier button in the column headers of the net selection table Note the net names are sorted in alpha numeric or bus element order whenever possible Common delimeters such as etc are used to identify possible bus element nets UGOO5 PN 0401884 v4 2 March 22 2002 Ch
92. the selected nets and ILA core inputs Use the Remove Connections button to remove any existing connections Use the Move Up and Move Down buttons to reorder the position of any selected connection Once the desired net connections have been made click the OK button to return to the main Core Inserter window All the nets for Trigger and Data must be chosen in this fashion After you have chosen all the nets for a given bus the ILA bus name changes from red to black see Figure 3 7 Net Connections CLOCK NET CHO clk c TRIGGER NETS CI DATA NETS CHO counter 8 CH1 counter 8 e H2 CH3 counter 11 oe CH4 CHS CHE CHT E Figure 3 7 Specifying Data Connections After specifying the Clock Trigger and Data nets click Next A dialog box appears asking if you want to proceed with Core Insertion If Yes the cores are generated inserted into the netlist and an NGO file is created by running the edif2ngd program Details of this process can be viewed in the Messages panel at the bottom of the window A Core Generation Complete message in the Messages panel indicates successful insertion of ChipScope cores Adding ILA Units Each device can support up to 15 ILA units depending on block RAM availability and ILA unit parameters To add another ILA unit to the project select Edit New ILA Unit or going to the ICON Options window by clicking on ICON in the tree on the left panel see Fi
93. tion 0 to the end of the capture buffer Position Sample Depth 1 To set the trigger position click inside the box to the right of the Position setting on the trigger toolbar Figure 4 26 For example if the trigger position is set to 1000 then the 1000 data samples captured before the trigger condition is satisfied are displayed along with 1047 samples captured after the trigger ChipScope Analyzer demo Unit 0 File Communication Configure Bus Signal Run Stop Data Window Help me 111 0fo 000 mo TOWEEI Trigger Condition macro Capture One Shot On IUEDCUICTN 000 _ Ext Out Sample Buffer rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 extended Figure 4 26 Selecting One Shot Capture Mode UGO005 PN 0401884 v4 2 March 22 2002 www xilinx com 4 15 ChipScope ILA Software and Cores User Manual 1 800 255 7778 Analyzer Menu Features XILINX Selecting On Trigger Capture Mode The On Trigger capture mode continues capturing data after each trigger condition is satisfied until the entire sample buffer is full You can set the number of samples captured per trigger to any value from 1 to 16 To select this mode click On Trigger in the trigger toolbar Figure 4 27 Select the number of samples per trigger from the Samples per Capture scrolling list box on the trigger toolbar Figure 4 27 For e
94. xample if you select the trigger position 8 then 8 data samples are captured after each occurrence of the trigger condition until the ILA unit s capture storage resources are completely full In some cases the last occurrence of the trigger condition might result in fewer samples stored depending on the value of the Samples per Capture setting and the sample depth of the ILA unit ChipScope Analyzer demo Unit 0 pat FS File Communication Configure Bus Signal Run Stop Data Window Help 22 f amp m T Vie v 5 BpB wef s iersposo mo wanfan Trigger Condition boolean no an Capture One Shot On Trigger Samples per Capture 1 z Ext Out Sample Buffer l rigger Width 8 Signal Count 16 Sample Depth 2048 ILA Core Version 1 2 extended Figure 4 27 Selecting On Trigger Capture Mode Window Enabling External Trigger Output Each ILA unit can drive out its overall trigger condition as an external trigger output to the ICON unit There it is logically OR ed with the external trigger output of all the other ILA units in the target device However you can disable the ILA unit from driving out its overall trigger condition and drive a logical 0 instead by deselecting the Ext Out field in the trigger setup toolbar Selecting the Ext Out field enables the ILA unit s individual external trigger output Figure 4 28 ChipScope Analyzer d

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