SCOC3 - ESA Microelectronics Section
Contents
1. SYSCLK 96 Mhz max ptt os ckesp CSDRCLK 7 CKCPUON fe 0 80 MHZ 10 Max s ormo ccu aria okapu gt CPU CKMCTL AST_GATING_CKMCTL ckmctl en CKSIFV AST_GATING_CKSIFV cksifv_en i CKSIFO AST_GATING_CKSIFO cksifo_en J sysclk_not 2 ee a lIOSDRCLK 0 5 7 AM 48 MHZ 10 max Ton gt 10 CPUMEMRATIO interna CKIO a AST_GATING_CKIO ckio en CKCONF1 2 lt CPUIORATIO internal AST_GATING_CKI53 a CKI53 J cki53_en 5 gt CLKDIVRATIO internal lt gt 14 A a rae SYSCLKDIV 1S 48 MHZ 10 max N Me 2 5 he CLK1553 16 MHZ 10 max ByPass CLK16 16 mHz i CLKSPW a J 160 MHZ max 132 Feedback ow 126 TENMCLK N divider p MHZ 10 max SPWCLKIN D eee TBD j ama BITCLK_PTME BITCLKI a 12 gt IN 3 64 MHZ 10 max Figure 2 SCOC3 clock tree This document is the property of Astrium It shall not be communicated to third parties without prior written agreement Its content shall not be disclosed EADS Astrium Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 Issue 1 Rev 0 Date 2013 01 15 Page 16 3 2 2 SCOC3 gate level simulations Gate level s2. M47 to M50 DSU Instruction trace buffer M51 to M54 DSU AHB trace buffer M55 TC On Chip memory M56 to M57 TM On Chip memory HKPF Context RAM HADMA FIFO IPMON Trace buffer IPMON Stat mem CCSDS CAN 1553 EADS Astrium Ref R amp D SCOC3 RP 01377 E ASTR L DLU SCOC3 a mane i Page 21 The gate level simulations 3 2 2 have been re run successfully on the post layout netlist The final gate level characteristics of SCOC3 are e Matrix size 13x13 169 mm e Occupied area in the matrix 57 7 mm o 17 7 mm for the memories o 0 236 mm for the PLL o 12 24 mm for the pads o 27 79 mm for the logic e Number of logic gates 1 8 Mgates e Number of DFFs 55000 e Number of memory bits 2 2 Mbits equivalent to 1 8 Mgates A picture of aSCOC3 ASIC prototype packaged and mounted on a board is shown in Figure 8 a 0 9398928 a a Set w amp ores Figure 8 SCOC3 ASIC mounted on a board This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR astrium SCOC3 Sehun Date 2013 01 15 Page 22 3 4 ASIC VALIDATION SCOC3 validation consisted in testing the ASIC prototypes and performing measurements on them in otder to verify that the SCOC3 ASICs contain the functionali
3. Jyvaskyla Finland on 5 7 Sept 2012 It was an Heavy Ions Testing The test board used for the test is shown below Figure 12 SCOC3 test board under the radiative beam The detailed results are presented in the Radiation Test Report As expected SCOC3 is insensitive to SEL and to Electrical Failure tested up to 65 Mev cm2 mg This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR astrium SCOC3 e Date 2013 01 15 Page 27 The actual SEU rates resulting from the test are also lower than the rates estimated prior to the test This is detailed in the Radiation Test Report 4 FOLLOW UP ACTIVITIES A SW activity is currently undertaken by a SW house with ESA support to expand the scope of the current Basic SW as well as its validation level This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR Q ASTRIUM SCOC3 ee ise Page 28 5 CONCLUSION The result of the SCOC series of activities is a powerful processor and spacecraft controller in the form of a highly integrated System on Chip SCOC3 This ASIC greatly reduces cost power and mass of on board computers SCOC3 is fully validated and
4. Page 19 32 MHz Input ene at T 0 Output sampling at T 31 ns SYSCLK CPUCLK internal before layout estimate CPUIO internal before layout estimate SPWCLKIN SPWCLKTX internal before layout estimate SPWRX input SPWRxX internal before layout estimate CLK16 CLK16 internal before layout estimate BITCLKI BITCLKDIV internal before layout estimate Figure 5 Clock definition for the functional foundry test program The JTAG test program activates all the states of the TAP controller It captures the inputs and forces the outputs It must be avoided that all the outputs are switching simultaneously otherwise supply problem may be encountered on ATMEL tester The BIST test program is used to activate the self test of each memory block and to verify that no errors are found during the memory test The ATPG program is generated by Tetramax from Synopsys Its fault coverage is 97 42 which is a beyond the 95 required by Atmel Transition delay fault TDF ATPG was not used The test program is generated in STIL format and interface between STIL and the tester is custom developed by Atmel In the past the transfer to tester had not always been smooth but for SCOC3 no problems were encountered 3 3 LAYOUT AND MANUFACTURING The layout and manufacturing of the SCOC3 ASIC have been performed by ATMEL The final layout is shown in Figure 7 ATMEL has optimized the memory floorplan p
5. 9 ASTRIUM C TRP and GSTP activity Spacecraft Controller On a Chip SCOC3 ASIC Manufacturing Test and Validation EXECUTIVE SUMMARY EUROPEAN SPACE AGENCY CONTRACT REPORT The work described in this report was done under ESA contract Responsibility for the content resides in the author or the organisation that prepared it ESTEC Contract No 22358 09 NL JK Prepared by Aur lien LEFEVRE EADS Astrium 1 boulevard Jean Moulin ZAC de la Clef Saint Pierre CS 30503 78997 Elancourt Cedex FRANCE This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed ESA STUDY CONTRACT REPORT No ESA study Contract Report will be accepted unless this sheet is inserted at the beginning of each volume of the Report ESA Contract No SUBJECT CONTRACTOR 22358 09 NL JK Spacecraft Controller on Chip SCOC3 ASIC Astrium SAS Manufacturing and Test ESA CR N No of Volumes 1 CONTRACTOR S REFERENCE R amp D SCOC3 RP 01377 E AS TR Issue 0 Rev 1 This is volume n 1 ABSTRACT The goal of the Spacecraft Controller on Chip SCOC3 ASIC Manufacturing and Test contract was to perform the gate level design layout manufacturing and validation of the SCOC3 ASIC to produce a first level of basic SW and to prepare SCOC3 commercialisation SCOC3 was developed with a very high level of integration of functions t
6. Wafer Most Significant Bit Non Return to Zero On Board Computer On Board Data Handling Personal Computer Phase Locked Loop Processor Module Programmable Read Only Memory Packet Telecommand Decoder Packet TeleMetry Encoder Quaternary Phase Shift Keying Readable Writable Random Access Memory Reference Document RX Host Interface ReMote Access Protocol Read Modify Write Read Only Memory Reed Solomon ReSeT Remote Terminal Register Transfer Language Sub Address 1553 context SpaceCraft Elapsed Time Spacecraft Controller On a Chip Spacecraft Controller On a Chip 1 based on LEON1 Spacecraft Controller On a Chip 3 based on LEON3 FT SCOC3 CCSDS Time Manager Synchronous Dynamic Random Access Memory Single Effect Transient SafeGuard Memory Service InterFace System In Package Segment Layer System on Chip SOF Tware Scalable Processor ARChitecture SpaceWire SpaceWire Remote Memory Access Protocol Static Random Access Memory Standard Test Interface Language SCOC3 PTME SoftWare SWitch MAtrix International Atomic Time Temps Atomique International in French Test Access Port TeleCommand This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed ASTRIUM TCDD TCL TCR THI TMTC TT UART USO USTM UTC VASI VCA VCID VCM VHDL XSTR Ref R amp D SCOC3 RP 01377 E A
7. 7 33 Test Tx and Rx at maximum frequency 3 7 34 Test of the SPW EDAC 3 7 38 1553 ynchro IT n Hz 1553 2 7 2 RT nominal behaviour 3 6 5 BC Nominal behaviour 3 6 6 CAN AN 3 26 UARTs Proper instantiation and connection 3 28 1 SCTM IOs and interconnections 2 5 1 2 5 3 3 12 2 amp 3 12 3 FPU WD Properimplementation 2 1 4 Registers amp Outputs init values and R W operations 5 2 a ICTL1 amp ICTL2 nterrupt routing 3 29 1 Switch matrix witch matrix 3 15 2 witch matrix in TMTC Only 3 15 3 ion 3 27 1 OK xe O xe O e oO O e j ted 3 a O e l Q w e GPIO MISC nputs Outputs 3 31 1 LL locked unlocked 3 31 2 FCTRL os amp programmation 3 36 1 Clocks amp ratios nput Output connection and configuration 3 17 4 sdram nput Output connection and configuration 3 17 4 sram HBR HADMA and clock ratios 8 17 5 ahbr HBR HADMA and clock ratios 3 17 5 hadm a Endurance 0 MBit s TM output rate 3 25 1 3 25 2 U OK OK ANIAINAINIANINI A ANININ NIA A A ALALALAIALALAIALALALALALA ALA LA ALA ALALTALALTALALA ALALALTALALA ALA ALA M W o eo fa xe v oO O Of Of Of Of OF OF CO OF CF OF O O O Of Of Of OJ O Of C O OO OOF OJ OF OJ O C O OF OF OJ OF OF OJ O O Of OF OF OF OC OJ OF O ALA ALAA ALA ALALALA A A ALALALAILALALAIALALALALALA ALALA ALA ALALTALALTALALA ALALA
8. Combined with services such as technical support this forms a complete offer around the SCOC3 ASIC to best serve our customers The work described in this report was done under ESA contract Responsibility for the contents resides in the author or organisation that prepared it Names of authors Aur lien LEFEVRE EADS Astrium ESA STUDY MANAGER ESA BUDGET HEADING TRP activity T701 099ED budget line D TEC ESTEC E 0901 DIV Data Systems Division 1 6171000 E 0901 01 K 01 09J12 TEC EDM GSTP activity G603 35ES budget line DIRECTORATE Technical D TEC ESTEC E 0904 and Quality Management 04 6171000 E 0904 01 K 01 09J17 Mr Roland WEIGAND Section to be completed by ESA This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR Issue 1 Rev 0 Date 2013 01 15 Page 3 ESA R amp D n 22358 09 NL JK spacecraft Controller on Chip SCOC3 ASIC Manufacturing and Test SCOC3 Executive Summary Report Aur lien LEFEVRE SCOC3 Design Manager Prepared by A odb Jean Paul BLANCHE Iha pprov Y ASIC Quality Assurance Zol 3 0 2 0012 ST ee ES Marc SOUYRI ASIC FPGA Design Expert Franck KOEBEL Product manager This document is the property of Astrium It shall not be communi
9. DSP communication e Data Management Systems composed of elementary ASICs designed by the industrials or bought as ASSP after their development under an ESA contract These functions can be integrated together with the microprocessor into a System on Chip to reduce the power and mass budget of on board computers Data Management Systems are built around a microprocessor backplane bus interface external serial bus interfaces TM TC functions positioning functions such as GPS The first SCOC contract proved that it was possible to integrate most of these functions on a single die The objective of the SCOC series of This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR astrium SCOC3 Sehun Date 2013 01 15 Page 12 activities was to produce an ASIC available as an off the shelf component to the European Industry which simplifies the architecture of future on board control and data handling OBDH systems SCOC3 functionality is comprehensive such as to satisfy a large variety of requirements yet it is scalable such as to be able to work in systems not using all of the features at reduced power consumption As a key asset SCOC3 includes CCSDS telecommand and telemetry interface While it has been demonstrated that the reliability of an integrated solution is be
10. F hao Page 13 3 MAIN TOPICS 3 1 SCOC3 DEVELOPMENT FLOW The SCOC3 development flow is presented in Figure 1 Thanks to a structured methodology the SoC integration and verification has been fast and smooth The present contract covers the activities from gate level simulations to prototype validation plus the development of a first level of basic SW the commercialisation of SCOC3 and a radiation test Kick off Sept 2006 y POA SCOC3 Development Flow Prototype Board July 2007 Feasibility incl architecture Development of New IPs coding synthesis IP level verification SoC Integration A May 2007 Logic Review Sept 2008 y SoC Verification RTL simulations Gate level Design Review simulations HW verif on FPGA Dec 2008 SW verif on FPGA breadboard V ASIC prototypes a May 2009 eae level ay ott May 2009 Prototype eae approval Oct 2009 v Flight Models May 2010 y Prototype Validation 19 months Flight Models production Figure 1 SCOC3 Development Flow This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR Q ASTRIUM SCOC3 ee soe Page 14 3 22 GATE LEVEL DESIGN Gate level design also termed detailed design in ECSS Q60 02A was composed of the following act
11. LALA ALALALA Figure 4 Status of the gate level simulations This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 be maons Page 18 3 2 3 SCOC3 formal proof To confirm and secure the results of the gate level simulations a formal proof of SCOC3 has been performed with the FormalPro tool from Mentor LEON3 FT was not included in the check since it was provided as a netlist The modules that are coded classically were checked without problem But the tool had some difficulties with modules using complex VHDL structures such as the PIME module that largely uses generics and records 3 2 4 SCOC3 preliminary floorplan The SCOC3 preliminary floorplan has been defined by Astrium see Figure 6 Coloured boxes represent the memory blocks that are placed on the die Their location has been defined depending on the pads The figure depicts the location proposed by Astrium ATMEL had the possibility to translate flip or rotate them No floorplan of each function was required by ATMEL Only LEON was placed by ATMEL in a given area The 8 larger pink blocks are the LEON3 cache memories The two orange blocks are the TM memories and the yellow one beside is the TC memory It has been verified that the empty space left on the die by memories is largely sufficient to
12. STR SCOC3 Issue 1 Rev 0 Date 2013 01 15 Page 10 TeleCommand Decoder Divas Tool Command Language TeleCommand Redundant module TX Host Interface Telemetry TeleMetry and TeleCommand Trap Type Universal Asynchronous Receiver Transmitter Ultra Stable Oscillator USer TeleMetry Coordinated Universal Time Very Advanced Sparc Interface ERC32 Companion Chip Virtual Channel Access Virtual Channel ID Virtual Channel Multiplexer Very High Speed Integrated Circuit Hardware Description Language Cross STRapping This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 be maons Page 11 2 DESIGN OBJECTIVES AND CONSTRAINTS 2 1 BACKGROUND The telecommunication satellite constellation market and the small satellite market drive to dramatically decrease spacecraft equipment weight consumption budget and recurrent price The emerging micro satellites and nano satellites generation also generates a demand for much more integrated equipments In the 80s and 90s ESA and industrials developed a set of ASICs to reduce the size of electronics Functions such as the VCA VCM and PTD used to build a CCSDS TM TC system bus interfaces such as MACS OBDH 1553 or error correction chips EDAC Reed Solomon Viterbi were manufactured as Applicati
13. Unit Fault Tolerant Gaisler Research LIBrary aHb Asynchronous Direct Memory Access Hardware Description Language HouseKeePing HouseKeePing Function HardWare Interface Input Output Improved Channel Selection SCOC3 Primary Interrupt Controller SCOC3 Secondary Interrupt Controller Institute of Electrical amp Electronics Engineers Spacewire INTernal for Reception Instruction Spacewire INTernal for Transmission Input Output IO AHB Controller Intellectual Property Inter Processor Link IP MONitor Interrupt ReQuest Multi Processor Interrupt ReQuest controller Instruction Set Simulator Joint Test Action Group not an acronym SPARC V8 32 bit processor Lesser General Public License Least Recently Used Least Significant Bit Modular Attitude Contol System This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed ASTRIUM Ref R amp D SCOC3 RP 01377 E ASTR SCOC3 Issue 1 Rev 0 Date 2013 01 15 MAP MAPTCR MISC MMU MPW MSB NRZ OBC OBDH PC PLL PM PROM PTD PTME QPSK R W RAM RD RHI RMAP RMW ROM RS RST RT RTL SA SCET SCOC SCOC1 SCOC3 SCTM SDRAM SET SGM SIF SIP SL SoC or SOC SOFT SPARC SpW SpW RMAP SRAM STIL STME SW SWMA TAI TAP TC Page 9 Multiplexed Access Point MAP TC Recorder MISCellaneous Memory Management Unit Multi Project
14. Window Pointer TT Trap Type registers and both AHB busses As usual a special treatment was required for the resynchronisation flip flops The flip flop models for gate level simulation generate an X level when a setup or hold violation is encountered Generally this X level propagates and the whole design becomes at X To prevent this the model of the flip flops used for resynchronisation is modified not to generate an X level in case of violation The SDF and the netlist were modified accordingly It must be noticed that this modification is not used for the gate level simulation of the foundry test programs No violation must be encountered in the foundry programs otherwise the ASIC response will not be deterministic and the ASIC will not be testable This is achieved by adjusting frequencies and phases of the various clock signals see section 3 2 5 and Figure 5 This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 S hao Page 17 The status of the gate level simulations is given in Figure 4 As it can be seen all the simulations except the endurance traffic ones passed without error in min and max conditions Tested functionnality J Simulation name Sim MIN MCTL Proper management of diff accesses to diff resources 3 24 1 1 OK roper manageme
15. already selected for 8 satellites SCOC3 is flight proven since 9t September 2012 on the SPOT6 satellite SCOC3 is also commercially available with a comprehensive package to support its integration use and SW development This study also demonstrates the necessity for a reliable and effective design methodology for System on Chip development A good methodology allowed speeding up the development of the large and complex design of SCOC3 There is a great interest for this SoC methodology for the future development of highly integrated ASICs whether they integrate CPU cores or not The development of large SoC devices also relies on the availability of a library of validated IP cores Some of these cores were provided by ESA as the PTME the Spacewire IP the HurriCAN controller and a collection of small but indispensable IP The main processing function was procured as a commercial IP from Gaisler Research GRLIB and LEON3 FT The methodology also takes advantage from standards coming from commercial applications military developments or space industry such as AMBA busses for internal connections of the IP cores and also external interface standards that allow the reuse of developed IP cores Mil Std 1553 Spacewire CCSDS TM TC This strategy was beneficial for SCOC3 development as it allowed reusing previously developed validation tools emulators for the simulations and standard hardware testbenches for the board evaluation The c
16. anced Peripheral Bus ASIC Application Specific Integrated Circuit ASSP Application Specific Standard Product ATPG Automatic Test Pattern Generation AUS AUthentication Status BC Bus Controller BCRT53 IP 1553 BC RT BM This document is the property of Astrium It shall not be communicated to third parties without prior written agreement Its content shall not be disclosed EADS Astrium ASTRIUM Ref R amp D SCOC3 RP 01377 E ASTR SCOC3 Issue 1 Rev 0 Date 2013 01 15 Page 8 BIST BM CAN CCSDS CLOW CPDU CPDUS CPU CWP DMA DMATM DRAM DSU DSU3 EDAC EEPROM ESA FAR FPGA FPU GPS GR GREPU GREPU FT GRLIB HADMA HDL HK HKPF HW I F I O ICS ICTL1 ICTL2 IEEE INRX INST INTX IO IOAHBCTL IP IPL IPMON IRQ IRQMP ISS JTAG LEON LGPL LRU LSB MACS Built In Self Test Bus Monitor Controller Area Network Consultative Committee for Space Data Systems Command Link Control Word Command Pulse Distribution Unit CPDU Status Central Processing Unit Current Window Pointer Direct Memory Access DMA for TeleMetry Dynamic Random Access Memory Debug Support Unit Debug Support Unit for LEON3 Error Detection And Correction Electronically Erasable Programmable Read Only Memory European Space Agency Frame Analysis Report Field Programmable Gate Array Floating Point Unit Global Positioning System Gaisler Research Gaisler Research Floating Point Unit Gaisler Research Floating Point
17. cated to third parties without prior written agreement its content shall not be disclosed EADS Astrium Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 Bee coors Page 4 DOCUMENT CHANGE LOG Rian Date Modification Nb Modified pages a 2012 05 11 First Issue 2012 07 05 Took ESA QAR comments into account 2013 01 15 Added the radiation test results PAGE ISSUE RECORD Issue of this document comprises the following pages at the issue shown This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR QO ASTRIUM SCOC3 ise aoue Page 5 TABLE OF CONTENTS 1 INTRODUCTION at ctor ceecicce csvset cs ra tp co cin catia uae poue Ge sdudncwacewap pak oceneecuaausenieswtswtanuedentenctenicsanewcocwoeeduicesaniens 7 1 1 CONTEXT AND RELEVANCE OF THE STUDY crrcceed ous suessndivaseesaasticesntewseiascodane shee caladavensuesavncebesudeaatueeuleaigieeaiial dodaee adeedlcetneiaa 7 1 2 PUI cece ets E E AAEE ere E ssec ese vances barewsnaarvantontn oto cevettondetobe dex ote esttesaw ieee ateoxsteareedion fi 2 DESIGN OBJECTIVES AND CONST RAIN US bsiscsccdcssnccdnsensesceaveusicedeussvvwanecaueteveanudeoi rein ranasdenvreunsuantiay sien seeoes 11 2 1 BACKCOCROUND os caterers E es asta ew ene esa ena cea eas vet eae 11 ZL Me racers cg a S E cared atictsctge
18. contain the SCOC3 gates with the recommended security factor The JTAG circuitry is placed by ATMEL around the chip an empty space is left between memories and the pads 3 2 5 SCOC3 foundry test programs Foundry test programs have been developed for SCOC3 These programs correspond to 4 categories e The functional test programs e The JTAG test program e The BIST test programs e The ATPG test programs 32 test programs have thus been developed The total number of vectors is about 14 million which is almost the limit given by ATMEL 16 M vectors Such a number of vectors should guarantee the quality of the tested parts The functional test programs are based on a set of scenarios allowing to activate the various interfaces of SCOC3 It was not intended to reach a high fault coverage with this program since it is the role of the ATPG program The functional test program is used to activate SCOC3 at the highest frequency compatible with the tester capabilities In our case the functional test program is running at 32 MHz As explained earlier no violation must occur on the resynchronization flip flops located between 2 clock domains It leads to define the very specific clock arrangement depicted in Figure 5 This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 SS
19. d the KERTEL board are delivered with the SCOC3 SW package described in the previous section Ethernet or USB Figure 11 SCOC3 Starter Kit STARKIT FPGA based evaluation platform The SCOC3 simulator is a LEON3 Instruction Set Simulator ISS which also includes most of the SCOC3 peripherals except MMU HADMA and CAN It is as fast as real time and has been calibrated with HW This simulator is qualified for flight software development and it is a flexible and interesting solution for SW development and qualification This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR d Rev 0 ASTRIUM ee ee Page 26 3 7 RADIATION TEST A radiation test has been performed on SCOC3 to confirm and refine the results of the existing radiation analysis by validation of some experimental results The method used was 1 prior to the test to estimate test sensitivities using ATMEL data 2 after the test to compare these estimates with the actual test results It was chosen to have multiple simple and robust tests focusing on specific parts of the design rather than a complex test activating all the functions at once Indeed radiation data is most useful when it is analyzable and exploitable 7 tests have thus been developed The radiation test took place at RADEF
20. e ere 15 Figure 3 Overview ae ar ley 616 6 sha 01g 180101 TUL 610 Emer ey eerri net arm emer a ene rm rene erie te errr arene tent eames ee ore er reer res 16 ore Sars Oi ES Gace Cl Sita A OG sioen aisa aE ae iE EE EE EE catagetee 17 Figure 5 Clock definition for the functional foundry test program ssessesesrsresrsresesrerestsresrsrseesrerenesrsnrnrereenenee 19 Figure 6 SCOC3 preliminary Floorplan s sesssssesesesesssesesesrsesesrreserereseresesrsesrseststsestsrstsesestntststntststeststntntntsenenentnteeee 20 Figure 12 vViewor 2 OGG die shoving ie nnal MA serrera e E TEE 20 Pewee t SCOCIASIC moaned on a DOA direnoisuniian a verre a renee 2l Figure 9 SW Package Basic SW and Demons eat On SW sissseriaieari arseenin aai 23 Eea OO O n e D a E E E E A E E et ree 24 Figure 11 SCOC3 Starter Kit YTARKIT FPGA based evaluation platform sizes csssscscssscassovestaceasuasespeweo ances 25 Ploutre 12 SCOGS test boda Under he radiative DETTA morris inn T EE SE 26 This document is the property of Astrium It shall not be communicated to third parties EADS Astrium without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR SCOC3 Issue 1 Rev 0 Date 2013 01 15 Page 7 ASTRIUM 1 INTRODUCTION 1 1 CONTEXT AND RELEVANCE OF THE STUDY The objective of the Spacecraft Controller On a Chip SCOC series of activities was to produce a very integrated and cost effective solution fo
21. ibility of such an ASIC due to the margins taken at each level system design foundry In the end SCOC3 uses less resources than predicted This reduces power consumption and avoids problems during the layout phase For such complex designs the use of formal proof for equivalence checking is mandatory Finally the development of a Basic SW and of a complete set of utilities and services SW Simulator low cost FPGA platform technical support is essential to support the use of a System on Chip This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM SCOC3 Bee aons Page 30 DISTRIBUTION LIST Roland Weigand ESA Mathieu Vandenbossche Franck Koebel Marc Souyri Arnaud Wagner Jean Marc Taine Remi Cissou Jean Jacques Derrien Jean Paul Blanche Alexandre M ge a Aur lien Lef vre This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed
22. imulations have first been performed on the pre layout netlist All the functional simulations have been passed except two traffic simulations that were too long to be carried out at gate level Simulations in best and worst conditions have been run The same testbench and scripts as for RTL simulations has been used HM d lSim SE PLUS 63f ae ii ma i i i Eie Eat Very Compile Simca Add Wye Toni Laym Woireirer Help liebe ft SBT ae S FLEET BERS A Bae BB Sa0M 422 Mare Are DD t 7 H D p Layout Similate F wivi fara OLE Leon Regs r E ATANN pe D Arwa DURUAR aaja AARAA O E fod 2 wed VO058F ri eT Traeeecript F Nie mui ma sessa E 613 904 ui F Note pmu i MEM oA TESTO FC CAC HES dof SU vant uiar nt 1 ry pi 4 DET ua ONO GUID t he A a B14 FU ui F higa pmu s VEN DODICI a BIE BEN E Hit diui mi CORRECT DATA iiih it mAn Hoke emu ip gt in CT abit _ _ Ji MP u ui e ote cmu_ip i ETETETT E Rote bin ip P Hooit GmU_ip h E Home kmu ip gt Waa hri F Noe pmu gp h E Hoe Ger_ip gt fi is P ho p pmu sp r Wob E Hti Geu_ip a ELLTELISELITELITELITELITECLTECITECLTECLTEEI EE BRI a i ari E hois pmu ip FRAME TION 70073 al 6ST ua fA Trerecript wh Mew B62 728 870 pa Daik J tice anaes pu Aine 128 611821 3 pa be B1SS07512 p Figure 3 Overview of a Modelsim simulation Wave signals show LEON PC Program Counter INST Instr code CWP Current
23. ivities e SCOC3 synthesis amp static timing analysis e SCOC3 gate level simulations e SCOC3 formal proof e SCOC3 preliminary floorplan e SCOC3 foundry test programs 3 2 1 SCOC3 synthesis and static timing analysis The synthesis of SCOC3 has been performed using Synopsys DC compiler DC Ultra and the required DesignWare libraries have been evaluated But it appeared that the gain in performance was less than 5 DC Topo was not used because its support was too recent for the targeted technology The synthesis of SCOC3 took about 4 hours on a UNIX workstation which was acceptable since most of the syntheses were carried out during the night This duration included JTAG and scan insertion that were quite long LEON3FT was provided by Gaisler Research as a pre synthesized netlist therefore the exploration of the configuration space was limited since each new configuration of the generic parameters required a new synthesis and delivery by Gaisler Research This could also have been a limiting factor when evaluating the other versions of DC compiler Concerning SEU hardening all the flip flops are HDFF SEU hardened flip flops provided in ATMEL library A single clock tree is used the clock tree is not triplicated what simplifies gate level design A verilog netlist is created by the synthesis and the SDF file is generated using Primetime in best and worst conditions The static timing analysis was performed using Synopsys PrimeTime P
24. nt of diff accesses to diff resources 3 24 1 2 Write protections 3 24 2 est Boot in PROM EEPROM with various memory sizes 3 24 3 OK RAM EDAC protection 2 2 3 amp 2 2 4 ion 3 2 3 amp 3 3 3 IO area 3 35 1 amp 3 35 2 AHBR Regular accesses 3 19 1 ttempt to access protected IlO memory resources 3 19 2 nterrupt generation 3 19 3 OK OK OK OK U D D D a Yn 3 fe 3 D 2 o D O OK lt WD unlock amp interrupt 3 19 4 MISC Half Can mode halfcan EON3 AHBR AHBCTR facc s lock s locked_transfer HADMA Attempt to access protected IO mem during DMA transfers 3 20 2 IPMON race amp Statistics 3 16 2 AHB Status nterrupt generation 3 18 1 STME TM modulation amp encoding 3 8 4 TM misc internal interfaces 3 8 6 TM VC 6 owner definition 3 8 7 DM ATM ontiguous packets transfers with different combinations 3 22 1 SpwDMAVC successful transfers and error occurence 3 22 2 HKPF Source packets transfers 3 21 1 TCDD PSS04 conformity 3 9 3 External deciphering unit interface 3 9 7 Incom ing data storage management 3 9 8 Authentication Deciphering status 3 9 9 Transmission to redundant TC 3 9 10 MAPTCR Post reset configuration 3 23 1 Interface with redundant TCDD 3 23 2 Spacewire interfaces Proper implementation of the 7 instances 3 7 35 XStr IPL post reset status 3 7 36 SpwSIF Ottobrun s version 3 7 37 TickIn TickO ut 3
25. o satisfy the demand for increasing performance at reduced power and mass The increasing amount of functionalities integrated into the same ASIC implies that the development of a whole system relies on the use of pre developed and pre tested IP functions The ideal scenario is to be able to construct a whole system by simply integrating IP blocks This is often difficult In reality IP blocks usually have to be modified but these IP blocks should always be very well tested and have a well known history The gate level design methodology previously used for ASIC developments has been improved to focus on the validation of the whole system and to take into account its greater complexity The extensive validation campaign was performed using two different boards In addition to the test cases which had been performed before the ASIC manufacturing in simulation or on FPGA new tests were introduced testing SCOC3 under various operating conditions to confirm the functionality and the electrical and timing parameters as well as the completeness of the user documentation These tests were performed by HW teams and by SW teams The availability of a basic SW is essential for a System on Chip This need was partly addressed by the development of a non flight basic SW Finally SCOC3 successfully underwent a radiation test Several tools have been developed outside of this contract such as a Simulator for SW development and a low cost FPGA platform
26. on Specific Standard Products ASSP In the past years the ASICs developed under ESA contracts were offered to European industrials as ASSPs Most of these chips were designed using the VHDL language As a side product software macros IP cores were created that can be reused under certain conditions The idea of SCOC Spacecraft Controller On a Chip was to merge several of these available blocks in a single ASIC called a System on Chip that would be able to perform a large number of the Data Management System functions of a platform With SCOC 3 this idea has become reality and the component is now available for space systems Further integration is possible with the SIP System In a Package emerging concept Such a SIP device could also include e memories SDRAM SRAM EEPROM Flash e drivers e g CAN 1553 2 2 DESIGN OBJECTIVES The System on Chip approach is now feasible as the number of gates per ASIC has grown enough There are at least two main domains of applications that require ASICs in Space which are e Digital Signal Processing applications that are extremely demanding in terms of gate and power dissipation requirements These functions are by now far from the whole system on a single chip paradigm since they integrate hundreds of ASICs for some of them Each of these individual ASICs can however be a System on Chip by itself i e integrating a processor core together with other functions
27. onsistent use of these standards in space ESA programmes should be promoted and the catalogue of available IP cores should be enhanced accordingly The availability of large commercial programmable logic devices is beneficial They allow rapid prototyping of the system and a deeper functional validation than using only simulations FPGA prototyping also provides a breadboard platform for early software development well before the availability of the System On ASIC The development of a prototyping hardware platform does not suppress the essential simulation phase Nevertheless due to the complexity of SCOC3 the simulation time dramatically increases while partially compensated by the increase of the computational performance of the simulation platform The simulations are then used to fully verify the IP core functionality in a standalone mode while the system simulations only partially verify the core functionality of each IP focusing on the correct integration of SCOC3 But it has to be noticed that an extensive set of simulations has been used in order to increase confidence and allow early bug detection investigation This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR astrium SCOC3 Sehun Date 2013 01 15 Page 29 It is always difficult to estimate the real feas
28. r spacecraft control This solution is the SCOC3 System on Chip ASIC that integrates most of the functions of an On Board Data Handling system and significantly reduces the cost of embedded electronics In 2001 2003 Astrium developed a SCOC prototype design SCOC1 along with an evaluation board BLADE in the frame of ESA contract 13345 99 NL FM entitled Building Blocks for System On a Chip In 2003 2006 Astrium refined this SCOC prototype design into SCOC2 through internal R amp D activities In 2006 2009 Astrium started the development of the SCOC3 System on Chip in the frame of ESA contract 20167 06 NL FM entitled Further Development of the Spacecraft Controller on a Chip during which the architectural design VHDL simulation and FPGA prototyping was performed The present activity under ESA contract 22358 09 NL JK is the continuation of these 3 studies The aim of this activity is e to perform the gate level design of the SCOC3 ASIC e to perform the layout of the ASIC e to manufacture the ASIC e to validate the ASIC using boards specifically developed for this purpose e to develop a SW package comprising SW tools and a first level of basic SW e to prepare the commercialisation of SCOC3 and its establishment as an ASSP 12 ACRONYMS Name Description AHB Advanced High performance Bus AHBR AHb to ahb BRidge AMBA Advanced Microcontroller Bus Architecture AOCS Attitude and Orbital Control System APB Adv
29. rocedures have been developed to check the timings in functional mode scan mode and JTAG mode These checks are carried out in best and worst conditions SCOC3 is able to work at many frequencies for the CPU clock and the IO clock Thus the timing analysis is made for each clock configuration CPU IO clock 32 32 48 32 64 32 At this step the exact characteristics of the clock tree are unknown The clock tree is modelled by ideal buffers The value of these buffers have been chosen following ATMEL recommendations that consists in a table giving the estimated delay with respect to the number of flip flops of the tree and the die size A drawing of the clock tree is provided in Figure 2 The main difficulties of such a clock tree are e The different clock frequencies that are statically programmable and that require either a direct connection or a divide by 2 flip flop for generation It introduces a latency that ATMEL has to compensate for This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR Rev 0 2013 01 15 15 Issue Date Page SCOC3 ASTRIUM The balancing of the clock trees in scan mode that is more difficult than in functional mode due e to the scan chains that are pure shift registers
30. roposed by Astrium In particular since the critical path is located in the LEON3FT between the integer unit and the caches ATMEL has performed a hierarchical layout with LEON3FT enclosed in a square area in the top left of the die surrounded by its memories This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed ASTRIUM iN EADS RAD MIPA Ref R amp D SCOC3 RP 01377 E ASTR Issue 1 Rev 0 Date 2013 01 15 CPU MCTL IO MCTL Page 20 CPU MCTL DSU amp HW links SPWs D N to fye te t D IO MCTL CAN 1553 Adaa a a d d bbdd a bbedededdsdddded OT Figure 6 SCOC3 preliminary Floorplan eee eee eee eee keke RRR RRR RR RRA RRR RR RRR RRR RRR ED ma 7 S MAAALALA k k LAMAMA nnna AAAA AAAA AAAALAAAAAAA A aan TTT LALLA AAAA L kA AARAA MAAAAA ARAMA AAA A Figure 7 View of a SCOC3 die showing the final layout This document is the property of Astrium It shall not be communicated to third parties without prior written agreement Its content shall not be disclosed TM TC Legend M1 to M8 LEON I amp D cache data M9 to M12 LEON I cache tags M13 to M16 LEON D cache tags M17 to M18 LEON IU Register File M19 to M25 Spacewire FIFOs
31. sed Ref R amp D SCOC3 RP 01377 E ASTR ASTRIUM Issue 1 Rev 0 Date 2013 01 15 Page 23 3 SW DEVELOPMENT A first level of SW for SCOC3 has been developed This SW package consists of e a Board Support Package BSP for the RTEMS operating system e a HW SW interface layer and Drivers that provide access to IO modules 1553 SpW UART CAN as well as to other functions Timers Datation Interrupt controller Caches GPIOs IPMON DMA Switch Matrix e a Demonstration SW a set of test applications serving as SW examples illustrating the use of the drivers e a SW development environment Drivers HW SW interface layer A Figure 9 SW Package Basic SW and Demonstration SW These SW items have been developed at ground demonstration level An ESA funded activity is currently ongoing to expand the scope of this SW package mainly to add the TM TC support as well as its validation level The HW SW interface layer is independent of the real time operating system So are most drivers The Basic SW and the Demonstration SW are delivered in source code For the Demonstration SW the test applications show use examples of how the various drivers can be used This provides a quickstart introduction to the SCOC3 Basic SW A complete User Manual ts also available This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content
32. shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR Q ASTRIUM Issue 1 Rev 0 Date 2013 01 15 Page 24 The SW development environment comprises a compiler a linker and a tool to communicate with SCOC3 It is delivered in a virtual machine containing a Linux installation with all the tools properly installed and configured This virtual machine can be quickly installed on most platforms providing a quick way to install the environment without portability version compatibility or tool installation problems 3 6 COMMERCIALISATION A comprehensive framework has been set up to support the commercialisation of SCOC3 as shown in Figure 10 SCOC3 ASIC STARKIT KERTEL Board Order Delivery Order SS 7 Basic SW Reporting Technical support Simulator Order for technical support Board Assembly Techical support on request Order for SCOC3 Delivery Flight Application SW Figure 10 SCOC3 Complete Offer SCOC3 is available to the European space industry under fair and equal conditions as an ASSP Application Specific Standard Product The commercialisation plan which is an output of this activity covets the whole product portfolio the SCOC3 itself in various quality levels but al
33. so related technical support boards and SW SCOC3 commercialisation is organized by Astrium acting as the ASSP Procurement Agency APA to provide the clients with a complete spectrum of solutions for the use of SCOC3 This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR DELU SCOC3 a anne i Page 25 SCOC3 is advertised at the www scoc3 com website at which a contact address is provided User documentation and quotations for SCOC3 parts and related products can be requested via this contact SCOC3 is proposed at 3 quality levels EM prototype QML Q or QML V Since Atmel has refused to endorse SCOC3 as an ASSP ATMEL applies Minimum Order Quantities MOQ Therefore SCOC3 for the time being can be ordered only with MOQ of 15 for EM 20 for QML Q and 15 for QML V Discussions have started with ESA to circumvent the MOQ for the final customer by funding an initial stock of components to be dispatched by Astrium in small quantities For SCOC3 evaluation and application prototyping the SCOC3 Starter Kit STARKIT is proposed It is a cost efficient KPGA based evaluation platform It is 100 representative of the SCOC3 and its interfaces It is also scalable and can be adapted or extended through expansion boards The KERTEL board is also proposed Both the STARKIT an
34. stern sensu eeuson wesaameany nuances 11 3 MAIN TOPICS e A A E E AA E 13 5A SCOCI acess esote ste heh EOR na eae nect arts A aE AEA EAREN AEA EEEE RARA ENEE ENKER 13 3 2 GATE LEVELDESIGN rere eeen e e E E E A A a OERE 14 eA OCF IG SIA AB AA A E AA A cde int 14 T SO OO Be a E E NOONE EE EA S 16 Bil DO 700 E T EEA E E E T 18 CRA SCDOT D7 a EEANN AA E A nantes vomesersandettoustueesedteiantecentss 18 T E OIA TO aaa dn E T E E T N ES 18 a LAYOUT AND MANU UPACTURING orc ceceacincuayeiestcacanseantececsaseesiatenhdenedaisatedenndeseesacatauies ace a a aAa Or a a e Ea E a airi aait 19 3 4 Fe he NT CIN NE EEA EATE EE N A A A EAEN E EN EATA A AAAA A TETE 22 3 5 Meese rate T A E seca ene bas coun TA E T E 23 3 6 COMMERCIALISATION cae peace yee reeda e a aaa ara ear a a a a aa a aa neicecpncunnaameeutaverteveadseenee 24 3T RDL TONA T Taea A EE E A E EO A IEA 26 4 FOLLOW UP ACTIVITIES 0 cccccccccccccccccccccccccccccccccccscccccccccccccccccceccccccccscsceccccccccsccccscccccecccccccccccccccsecs 27 5 CONCLUSI IN a E Eais 28 This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR QO ASTRIUM SCOC3 ise iso Page 6 LIST OF FIGURES Poe E Gio DA TO eT eh ay ermrerre wereree rrere re treere E etree rte re eer errr ee cere cere 13 ra e Oe E E E Sesser eer eee eee Reece reer e
35. ties and the characteristics they are designed for Note that in addition to these activities there was an extensive verification of SCOC3 design before the foundry through module level simulations top level simulations and functional tests on an FPGA breadboard by both HW and SW teams SCOC3 embeds many functionalities and has several configurations Two different boards have been used for its validation e the KERTEL board developed for SCOC3 validation under ESA contract e the KEROBS board that is the processing board of the OSCAR Astrium OBC SCOC3 validation consisted in e the hardware validation composed of O the functional validation numerous HW oriented tests performed in various temperature and voltage conditions with various clock frequencies O the electrical characterization oscilloscope measurements of signals memory accesses power consumption measurements o the functional characterization measurement of operating limits on clock frequencies voltages wait states e the software validation aimed at validating the functionality from a software point of view avionics level tests defined in co engineering between the SW team and the Data Handling architect with performance measurements in representative and worst case scenarii This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclo
36. tter than that of discrete components SCOC3 nevertheless has MAP and other interfaces which allow cross strapping of two redundant on board computers The use of cache was a main concern for real time software developers Most internal studies in this domain lead to a solution satisfying both hardware and software teams The SCOC3 System on Chip resulting from this activity is a radiation hardened ASIC providing all the features of a spacecraft control system e A LEON3 FT SPARC V8 processor including a debug module DSU a high performance FPU GRFPU large caches 2 64kB and a MMU e ACCSDS TC decoder e ACCSDS TM encoder e ACCSDS Time Management controller e 8 SpaceWire controllers 2 of them being multiplexed and 7 of them supporting the RMAP protocol in HW e 2 1553 BC BM RT controllers each exclusive with the CAN controller that shares pins e 2 CAN controllers each exclusive with the 1553 controller that shares pins e 4 UART controllers 3 APB UART and 1 AHB UART e 2 memory controllers One dedicated to CPU and one dedicated to the IO and TMTC modules e lt A Housekeeping module e An AHB bus monitoring module e MAP interfaces to cross strap two SCOC3s e Power reduction modes This document is the property of Astrium It shall not be communicated to third parties EADS Astri um without prior written agreement Its content shall not be disclosed Ref R amp D SCOC3 RP 01377 E ASTR QASTRIUM SCOC3
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