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SCF5250 Integrated ColdFire® Microprocessor - Data

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1. Input Reset Signal Name Mnemonic Function Output State Linear regulator input LININ Input typically I O supply 3 3V In Linear regulator ground LINGND High Impedance HI Z Assertion Tri states all output signal In pins Debug Data DDATAO CTS1 SDATAO SDIO1 GPIO 1 Displays captured processor data and In Out Hi Z DDATA1 RTS1 SDATA2 BS2 GPIO2 break point status DDATA2 CTSO GPIO3 DDATAS RTSO GPIO4 Processor Status PSTO GPIO50 Indicates internal processor status In Out Hi Z PST1 GPIO49 PST2 INTMON2 GPIO48 PSTS INTMON1 GPIO47 Processor clock PSTCLK GPIO51 processor clock output Out Test Clock TCK Clock signal for IEEE 1149 1A JTAG In Test Reset Development TRST DSCLK Multiplexed signal that is In Serial Clock asynchronous reset for JTAG controller Clock input for debug module Test Mode Select Break TMS BKPT Multiplexed signal that is test mode In Point select in JTAG mode and a hardware break point in debug mode Test Data Input TDI DSI Multiplexed serial input for the JTAG or In Development Serial Input background debug module Test Data TDO DSO Multiplexed serial output for the JTAG Out Output Development Serial Output or background debug module 4 2 GPIO Many pins have an optional GPIO function General purpose input is always active regardless of state of pin General purpose output or primary output is determined by the appropriate setting of the P
2. Figure 11 JTAG Timing SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 36 Freescale Semiconductor Electrical Characteristics 5 1 IIS Module AC Timing Specifications Table 30 SCLK INPUT SDATAO OUTPUT Timing Specifications Name Characteristic Unit Min Max TU SCLK fall to SDATAO rise 25 ns TD SCLK fall to SDATAO fall 25 ns SCLK INPUT SDATAO1 2 OUTPUT Figure 12 SCLK Input SDATA Output Timing Table 31 SCLK OUTPUT SDATAO OUTPUT Timing Specifications Name Characteristic Unit Min Max TU SCLK fall to SDATAO rise 3 ns TD SCLK fall to SDATAO fall 3 ns SCLK OUTPUT SDATAO1 2 OUTPUT Figure 13 SCLK Output SDATAO Output Timing Diagram SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 37 Pin Out and Package Information Table 32 SCLK INPUT SDATAI INPUT Timing Specifications Name Characteristic Unit Min Max TSU SDATAI IN to SCLKn 5 ns TH SCLK rise to SDATAI 3 ns Ne Akai Mh oen AGLI SCLK INPUT OR OUTPUT w idu Figure 14 SCLK Input Output SDATAI Input Timing Diagram 6 Pin Out and Package Information 6 1 Pinning Chart Table 33 144 QFP Pin Assignments 144 QFP w Pin State Pin Name Type Description After Reset Number 01
3. Electrical Characteristics 4 20 BDM JTAG Signals The SCF5250 complies with the IEEE 1149 1A JTAG testing standard The JTAG test pins are multiplexed with background debug pins 4 21 Clock and Reset signals These signals configure the SCF5250 and provide interface signals to the external system 4 21 1 Reset In Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing When RSTI is recognized the data bus is tri stated 4 21 2 Clock Input SCF5250 includes on chip crystal oscillator The crystal should be connected between CRIN and CROUT An externally generated clock signal can also be used and should be connected directly to the CRIN pin 4 22 Wake Up Signal To exit power down mode apply a LOW level to the WAKE UP GPIO21 input pin 4 23 On chip Linear Regulator The SCF5250 includes an on chip linear regulator This regulator provides an 1 2 V output which is intended to be used to power the SCF5250 core Three pins are associated with this function LININ LINOUT and LINGND Typically LININ would be fed by the I O PAD supply 3 3 V with separate filtering recommended to provide some isolation between the I O and the core In portable solutions this linear regulator may not be efficient enough and in this case we would expect the 1 2 V supply to be generated externally possibly by a highly efficient DC DC convertor If not used leave pins not connected 5 Electrical Characteristics Table 14
4. GPIO IN GPIO OUT Figure 10 General Purpose Parallel Port Timing Definition Table 29 IEEE 1149 1 JTAG AC Timing Specifications Num Characteristic Units Min Max TCK Frequency of Operation 0 10 MHz J1 TCK Cycle Time 100 nSec J2a TCK Clock Pulse High Width 25 nSec J2b TCK Clock Pulse Low Widih 25 nSec J3a TCK Fall Time 5 nSec Viu 22 4 V to Vj 0 5 V J3b TCK Rise Time 5 nSec Vj 20 5 v to Vin 2 4 V J4 TDI TMS to TCK rising Input Setup 8 nSec J5 TCK rising to TDI TMS Invalid Hold 10 nSec J6 Boundary Scan Data Valid to TCK Setup tbd nSec J7 TCK to Boundary Scan Data Invalid to rising edge Hold tbd nSec J8 TRST Pulse Width 12 nSec asynchronous to clock edges J9 TCK falling to TDO Valid 15 nSec signal from driven or three state J10 TCK falling to TDO High Impedance 15 nSec J11 TCK falling to Boundary Scan Data Valid tbd nSec signal from driven or three state SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 35 Electrical Characteristics Table 29 IEEE 1149 1 JTAG AC Timing Specifications continued Num Characteristic Units Min Max J12 TCK falling to Boundary Scan tbd nSec Data High Impedance BOUNDARY SCAN DATA INPUT BOUNDARY SCAN DATA OUTPUT
5. 5 nSec 1 DSCLK and DSI are internally synchronized This setup time must be met only if recognition on a particular clock is required 2 AC timing specs assume 50pF load capacitance on PSTCLK and output pins If this value is different the input and output timing specifications would need to be adjusted to match the clock load PSTCLK DSI PST 3 0 DDATA 3 0 DSO Figure 5 Debug Timing Definition SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 29 Electrical Characteristics Table 23 Timer Module AC Timing Specification Num Characteristic Units Min Max T1 TIN Cycle time 3T bus clocks T2 TIN Valid to BCLK input setup 6 nSec T3 BCLK to TIN Invalid input hold 0 nSec T4 BCLK to TOUT Valid output valid 10 nSec T5 BCLK to TOUT Invalid output hold tbd nSec T6 TIN Pulse Width 1T an bus clocks T7 TOUT Pulse Width 1T bus clocks Figure 6 Timer Module Timing Definition SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 30 Freescale Semiconductor Table 24 UART Module AC Timing Specifications Electrical Characteristics Num Characteristic Units Min Max U1 RXD Valid to BCLK input setup 6 nSec U2 BCLK to RXD Invalid input
6. Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 47 How to Reach Us RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative Home Page www freescale com For information on Freescale s Environmental Products program go to E mail http www freescale com epp support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia Q9 freescale com For Literature Requests Only Freescal
7. l O Subcode RCK interface Out LOW QSPI_DIN QSPI_DOUT QSPI Data In Data Out GPIO26 SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 40 Freescale Semiconductor Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP Pin Stat Pin Name Type Description After a ut Number er Rese 57 QSPI_CLK SUBR y o QSPI clock pin subcode interface Out LOW GPIO25 58 QSPI DOUT SFSY l O QSPI Data Output subcode Out LOW GPIO27 interface SFSY 59 QSPI_CS1 EBUOUT2 y o QSPI Chip select 1 output Out LOW GPIO16 audio interface EBU output 2 60 QSPI_CS0 EBUIN4 y o QSPI chip select 0 Out LOW GPIO15 audio interface EBUIN 4 61 PAD GND 62 SCLK1 GPIO20 y o Audio interfaces serial clock 1 In LOW 63 LRCK1 GPIO19 y o Audio interfaces word clock 1 In LOW 64 SDATAO1 TOUTO y o Audio interfaces serial data Out LOW GPIO18 output 1 Timer output 0 65 SDATAM GPIO17 Audio interfaces serial data in 1 In LOW 66 CFLG GPIO5 l O CFLG input In LOW 67 EF GPIO6 I O Error flag input In LOW 68 QSPI_CS2 MCLK2 y o QSPI Chip Select output 2 Out LOW GPIO24 audio master clock output 2 69 SDATAI3 GPIO8 y o Audio interfaces serial data input 3 In LOW 70 ADINO GPI52 A AD input 0 In only 71 ADIN1 GPI53 A AD input 1 In only 72 ADIN2 GPI54 A AD input 2 In only 73 ADVDD 7
8. no other values are allowed The System Clock is derived from one of these crystals via an internal PLL PSTCLK Figure 2 Clock Timing Definition NOTE Signals above are shown in relation to the clock No relationship between signals is implied or intended SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 25 Electrical Characteristics Table 20 Input AC Timing Specification Num Characteristic Units Min Max B112 Signal Valid to BCLK Rising setup 3 nSec B2 BCLK Rising to signal Invalid hold 2 nSec B3 BCLK to Input High Impedance 5 BCLK cycle Inputs rising DATA 31 16 2 ACtiming specs assume 40pF load capacitance on BCLK and 50pF load capacitance on output pins If this value is different the input and output timing specifications would need to be adjusted to match the clock load Table 21 Output AC Timing Specification Num Characteristic Units Min Max e B10 BCLK 8mA Rising to signal Valid 10 nSec B11 BCLK 8mA Rising to signal Invalid hold 3 5 nSec B10 BCLK 4mA Rising to signal Valid 11 nSec B11 BCLK 4mA Rising to signal Invalid hold 4 ES nSec e B12 BCLK to High Impedance a 14 nSec Three State H1 HIZ to High Impedance tbd nSec e H2 HIZ to Low Impedance tbd nSec
9. 2 sectors e Third layer error encoding needs to be done in software This can use approximately 5 10 Mhz of performance for single speed 1 2 13 Dual UART Module Two full duplex UARTs with independent receive and transmit buffers are in this module Data formats can be 5 6 7 or 8 bits with even odd or no parity and up to 2 stop bits in 1 16 increments Four byte receive buffers and two byte transmit buffers minimize CPU service calls The Dual UART module also provides several error detection and maskable interrupt capabilities Modem support includes request to send RTS and clear to send CTS lines The system clock provides the clocking function from a programmable prescaler You can select full duplex auto echo loopback local loopback and remote loopback modes The programmable Dual UARTs can interrupt the CPU on various normal or error condition events 1 2 14 Queued Serial Peripheral Interface QSPI The QSPI module provides a serial peripheral interface with queued transfer capability It supports up to 16 stacked transfers at a time making CPU intervention between transfers unnecessary Transfers of up to 15 Mbits second are possible at a CPU clock of 120 MHz The QSPI supports master mode operation only 1 2 15 Timer Module The timer module includes two general purpose timers each of which contains a free running 16 bit timer Timer has an external pin TOUTO which can be used in Output Compare mode This mode triggers a
10. 94 RXDO GPIO46 y o First UART receive data input In LOW 95 PST3 INTMON1 l O Debug interrupt monitor output 1 Out HIGH GPIO47 96 PST2 INTMON2 y o Debug interrupt monitor output 2 Out HIGH GPIO48 97 PAD GND 98 PST1 GPIO49 y o Debug Out HIGH 99 PSTO GPIO50 y o Debug Out HIGH 100 PSTCLK GPIO51 y o Debug Out clock output 101 TDO DSO O JTAG debug BDM SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 42 Freescale Semiconductor Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP Pin Name Type Description ve nan 102 TDI DSI JTAG debug BDM 103 TCK JTAG BDM 104 TMS BKPT l JTAG debug BDM 105 TRST DSCLK l JTAG Debug BDM 106 RSTI Reset X 107 SCLK2 GPIO22 y o Audio interfaces serial clock 2 In LOW 108 LRCK2 GPIO238 y o Audio interfaces EBU out 1 In LOW 109 LINOUT A Linear regulator output X 110 LININ A Linear regulator input X 111 LINGND Linear regulator ground X 112 SDATAO2 GPIO34 y o Audio interfaces serial data output 2 Out LOW 113 MCLK1 GPIO 1 1 l O Audio master clock output 1 Out clock output 114 HI Z JTAG X 115 TEST2 Test X 116 TEST1 Test X 117 TESTO Test X 118 SDWE GPIO38 y o SDRAM write enable Out HIGH 119 SDCAS GPIO39 1 0 SDRAM CAS Out HIGH 120 PAD VDD 121 SDRAS GPIO59 l O SDRAM RAS Out HIGH 122 SD_CS0 GPIO60 1 0 SDRAM chip select
11. CSO EBUIN4 GPIO15 IEC958 outputs EBUOUT1 GPIO37 audio interfaces IEC958 outputs Out QSPI CS1 EBUOUT2 GPIO16 Serial data in SDATAM GPIO17 audio interfaces serial data inputs In SDATAI3 GPIO8 Serial data out SDATAO1 TOUTO GPIO18 audio interfaces serial data outputs In Out SDATAO2 GPIO34 Out Word clock LRCK1 GPIO19 audio interfaces serial word clocks In Out LRCK2 GPIO23 LRCKS GPIO43 AUDIO CLOCK Bit clock SCLK1 GPIO20 audio interfaces serial bit clocks In Out SCLK2 GPIO22 SCLK3 GPIO35 SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor Table 3 SCF5250 Signal Index continued Signal Descriptions F j Input Reset Signal Name Mnemonic Function Output State Serial input EF GPIO6 error flag serial in In Out Serial input CFLG GPIO5 C flag serial in In Out Subcode clock RCK QSPI_DIN QSPI_DOUT audio interfaces subcode clock In Out GPIO26 Subcode sync QSPI DOUT SFSY GPIO27 audio interfaces subcode sync In Out Subcode data QSPI CLK SUBR GPIO25 audio interfaces subcode data In Out Clock frequency trim XTRIM GPIOO clock trim control Out Audio clocks out MCLK1 GPIO 1 1 DAC output clocks Out QSPI CS2 MCLK2 GPIO24 Audio clock in LRCK3 GPIO43 AUDIO CLOCK Optional Audio clock Input MemoryStick SecureDigita EBUINS CMD SDIO2 GPIO14 Secure Digital command lane In Out interface MemoryStick inter
12. DATA16 yo Data X 02 A23 GPO54 y o SDRAM address static adr Out requires pull up down for boot up selection 03 PAD VDD 04 A22 O SDRAM address static adr Out 05 A21 O SDRAM address static adr Out 06 A20 A24 O SDRAM address static adr Out 07 A19 O SDRAM address static adr Out 08 A18 O SDRAM address static adr Out SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 38 Freescale Semiconductor Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP Pin Name Type Description d 09 PAD GND 10 A17 O SDRAM address static adr Out 11 A16 O SDRAM address static adr Out 12 A15 O SDRAM address static adr Out 13 A14 O SDRAM address static adr Out 14 A13 O SDRAM address static adr Out 15 PAD VDD 16 A12 SDRAM address static adr Out 17 A11 SDRAM address static adr Out 18 CORE VDD 19 CORE GND 20 A10 O SDRAM address static adr Out 21 A9 O SDRAM address static adr Out 22 A8 O SDRAM address static adr Out 23 A7 O SDRAM address static adr Out 24 A6 O SDRAM address static adr Out 25 A5 O SDRAM address static adr Out 26 PAD GND PAD GND 27 A4 O SDRAM address static adr Out 28 A3 e SDRAM address static adr Out 29 A2 e SDRAM address static adr Out 30 Al e SDRAM address static adr Out 31 CS0 CS4 e Static chip select 0 static chip Out se
13. Maximum Ratings Rating Symbol Value Units Supply Core Voltage Vec 0 5 to 2 5 V Maximum Core Operating Voltage Voc 1 32 V Minimum Core Operating Voltage Voc 1 08 V SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 21 Electrical Characteristics Table 14 Maximum Ratings continued Rating Symbol Value Units Supply I O Voltage Vec 0 5 to 4 6 V Maximum I O Operating Voltage Voc 3 6 V Minimum I O Operating Voltage Voc 3 0 V Input Voltage Vin 0 5 to 46 0 V Storage Temperature Range Tstg 65 to150 C Table 15 Operating Temperature Characteristic Symbol Value Units Maximum Operating Ambient Temperature Tamax 85 C Minimum Operating Ambient Temperature Tamin 40 C Note This published maximum operating ambient temperature should be used only as a system design guideline All device operating parameters are guaranteed only when the junction temperature does not exceed 105 C Table 16 Recommended Operating Supply Voltages Pin Name Min Typ Max CORE VDD 1 08V 1 2V 1 32V CORE VSS gnd PAD VDD 3 0V 3 3v 3 6V PAD VSS gnd ADVDD 3 0V 3 3v 3 6V ADGND gnd OSCPAD VDD 3 0V 3 3v 3 6V OSCPAD GND gnd PLLCORE1VDD 1 08V 1 2V 1 32V PLLCORE1GND gnd PLLCORE2VDD 1 08V 1 2v 1 32V PLLCORE2GND gnd LIN 3 0v 3 3V 3 6V SCF5250 Inte
14. Regulator JTAG l Cache Oo V2 lt System SDRAM Ctr ColdFire Bus amp Core Controller chip Selects Figure 1 SCF5250 Block Diagram 3 Documentation Table 2 lists the documents that provide a complete description of the SCF5250 and are required to design properly with the part Documentation is available from a local Freescale distributor a Freescale semiconductor sales office a Freescale Literature Distribution Center or through the Freescale DSP home page on the Internet http e www Freescale com the source for the latest information SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor Signal Descriptions Table 2 SCF5250 Documentation Document Name Description Order Number CFPRM D ColdFire Family Programmer s Reference Manual CFPRM D ColdFire2UM Version 2 2M ColdFire Core ColdFire2UM D Processor User s Manual ColdFire2UMAD Version 2 2M ColdFire Core ColdFire2UMAD D Processor User s Manual Addendum SCF5250UM SCF5250 User s Manual SCF5250UM D 4 Signal Descriptions 4 1 Introduction This section describes the SCF5250 input and output signals The signal descriptions as shown in Table 2 A are grouped according to relevant functionality Table 3 SCF5250 Signal Index z Input Reset Signal Name Mnemonic Function Output State Address A 24 1 24 address lin
15. and SDA1 RXD1 GPIOA4 are the inputs on which serial data is received by the DUART Data is sampled on RxD 1 0 on the rising edge of the serial clock source with the least significant bit received first Transmit Data The DUART transmits serial data on the TXDO GPIO45 and SCL1 TXD1 GPIO10 output signals Data is transmitted on the falling edge of the serial clock source with the least significant bit transmitted LSB first When no data is being transmitted or the transmitter is disabled these two signals are held high TxD 1 0 are also held high in local loopback mode Request To Send The DDATAS RTSO GP104 and DDATA1 RTS1 SDATA2 BS2 GPIO2 request to send outputs indicate to the peripheral device that the DUART is ready to send data and requires a clear to send signal to initiate transfer Clear To Send Peripherals drive the DDATA2 CTSO GPIO3 and DDATAO CTS1 SDATAO SDIO1 GPIO 1 inputs to indicate to the SCF5250 serial module that it can begin data transmission 4 10 Timer Module Signals The following signal provides an external interface to Timer0 Table 7 Timer Module Signals Serial Module Signal Description Timer Output The SDATAO1 TOUTO GPIO18 programmable output pulse or toggle on various timer events SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 15 Signal Descriptions 4 11 Serial Audio Interface Signals The following signa
16. out 0 Out HIGH 123 SDLDQM GPO52 O SDRAM LDQM Out HIGH 124 SDUDOM GPOS53 O SDRAM UDQM Out HIGH 125 BCLKE GPIO63 y o SDRAM clock enable output Out HIGH 126 BCLK GPIO40 y o SDRAM clock output Out HIGH 127 DATA31 1 0 Data X 128 DATA30 y o Data X SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 43 Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP Pin Name Type Description U Bese Number 129 PAD GND 130 DATA29 lO Data X 131 DATA28 VO Data X 132 DATA27 O Data X 133 DATA26 O Data X 134 DATA25 O Data X 135 PAD VDD 136 DATA24 O Data X 137 DATA23 O Data X 138 DATA22 O Data X 139 DATA21 O Data X 140 DATA20 O Data X 141 PAD GND 142 DATA19 lO Data X 143 DATA18 O Data x 144 DATA17 VO Data X 6 2 Package The SCF5250 is assembled in 144 pin QFP package Thermal characteristics are not available at this time SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 44 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 45 THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 46 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK SCF5250 Integrated ColdFire
17. size 4 3 5 Transfer Acknowledge The TA GPIO12 pin is the transfer acknowledge signal 4 4 SDRAM Controller Signals The following SDRAM signals provide a glueless interface to external SDRAM An SDRAM width of 16 bits is supported and can access as much as 32MB of memory ADRAMs are not supported Table 4 SDRAM Controller Signals SDRAM Signal Description Synchronous DRAM row address strobe The SDRAS GPIOS9 active low pin provides a seamless interface to the RAS input on synchronous DRAM Synchronous DRAM Column Address Strobe The SDCAS GPIO39 active low pin provides a seamless interface to CAS input on synchronous DRAM Synchronous DRAM Write The SDWE GPIO38 active low pin is asserted to signify that a SDRAM write cycle is underway This pin outputs logic 1 during read bus cycles SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 13 Signal Descriptions Table 4 SDRAM Controller Signals continued SDRAM Signal Description Synchronous DRAM Chip Enable The SD_CS0 GPIO60 active low output signal is used during synchronous mode to route directly to the chip select of a SDRAM device Synchronous DRAM UDQM and LODM The DRAM byte enables UDMQ and LDQM are driven by the signals SDUDQM GPO53 and SDLDQM GPO52 byte enable outputs Synchronous DRAM clock The DRAM clock is driven by the BCLK GPIO40 signal Synchronous DRAM Clock Enable Th
18. that complies with the IEEE 1149 1A standard for boundary scan testability often referred to as Joint Test Action Group or JTAG For more information refer to the IEEE 1149 1A standard Freescale provides BSDL files for JTAG testing 1 2 23 System Debug Interface The ColdFire processor core debug interface supports real time instruction trace and debug plus background debug mode A background debug mode BDM interface provides system debug In real time instruction trace four status lines provide information on processor activity in real time PST pins A four bit wide debug data bus DDATA displays operand data and change of flow addresses which helps track the machine s dynamic execution path SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 6 Freescale Semiconductor Introduction 1 2 24 Crystal and On chip PLL Typically an external 16 92 Mhz or 33 86 Mhz clock input is used for CD R W applications while an 11 2896 MHz clock is more practical for Portable CD player applications However the on chip programmable PLL which generates the processor clock allows the use of almost any low frequency external clock 5 35 Mhz Two clock outputs MCLK1 and MCLK2 are provided for use as Audio Master Clock The output frequencies of both outputs are programmable to Fxtal Fxtal 2 Fxtal 3 and Fxtal 4 The Fxtal 3 option is only available when the 33 86 Mhz crystal is connected The SCF5250 supports VCO oper
19. 1 Outputs 8mA DATA 31 16 ADDR 25 23 9 2 Outputs 4mA SDRAS SDCAS SDWE SD CS0 SDUDQM SDLDQM BCLKE 3 High Impedance Three State DATA 31 16 4 AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins If this value is different the input and output timing specifications would need to be adjusted to match the clock load SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 26 Freescale Semiconductor Electrical Characteristics END zo 1 1 1 1 1 1 1 1 I gt 4 ADDR 24 0 X DATA 31 16 Figure 3 Input Output Timing Definition l SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 27 Electrical Characteristics BCLK 63 44 pm INPUTS X OUTPUTS OUTPUTS Figure 4 Input Output Timing Definition lll SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 28 Freescale Semiconductor Table 22 Debug AC Timing Specification Electrical Characteristics Num Characteristic Units Min Max D1 PSTCLK to signal Valid Output valid 6 nSec D2 PSTCLK to signal Invalid Output hold 1 8 nSec D3 Signal Valid to PSTCLK Input setup 3 nSec D4 PSTCLK to signal Invalid Input hold
20. 4 ADGND 75 ADIN3 GPI55 A AD input 3 In only 76 ADIN4 GPI56 A AD input 4 In only 77 ADIN5 GPI57 A AD input 5 In only 78 ADREF A ADC reference input In 79 ADOUT SCLK4 y o AD output SCLK4 Out clock output GPIO58 for GPI function in low power applications SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 41 Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP Pin Stat Pin Name Type Description Aft we n Number PUES 80 LRCK3 GPIO43 l O Audio interface LRCK3 In LOW AUDIO CLOCK Audio master clock input 81 SCLK3 GPIO35 y o Audio interface SCLK3 In LOW 82 SCLO SDATA1 BS1 0 I2CO clock line FlashMedia Out LOW GPIO41 Data interface 83 SDAO SDATA3 l O I2CO data FlashMedia Hi Z GPIO42 data interface 84 DDATAO CTS1 l O Debug UART1 CTS FlashMedia Out HIGH SDATAO_SDIO1 data interface GPIO1 85 DDATA1 RTS1 l O Debug UART1 RTS FlashMedia Out HIGH SDATA2 BS2 GPIO2 data interface 86 DDATA2 CTSO GPIO3 y o Debug UARTO CTS Out HIGH 87 DDATAS RTSO GPIO4 y o Debug UARTO RTS Out HIGH 88 SCL1 TXD1 GPIO10 y o I2C1 clock line second Out LOW UART transmit data output 89 CORE VDD 90 CORE GND 91 SDA1 RXD1 GPlO44 y o I2C1 data line second UART Hi Z receive data input 92 PAD VDD 93 TXDO GPIO45 y o First UART transmit data output Out HIGH
21. A Low output valid 10 nSec M13 BCLK to SCL SDA Invalid output hold 3 nSec 1 Since SCL and SDA are open collector type outputs which the processor can only actively drive low this specification applies only when SCL or SDA are driven low by the processor The time required for SCL or SDA to reach a high level depends on external signal capacitance and pull up resistor values 2 Since SCL and SDA are open collector type outputs which the processor can only actively drive low this specification applies only when SCL or SDA are actively being driven or held low by the processor 3 SCL and SDA are internally synchronized This setup time must be met only if recognition on a particular clock is required SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 33 Electrical Characteristics SCL SDA IN SCL SDA OUT SCL SDA OUT Figure 9 I2C and System Clock Timing Relationship Table 28 General Purpose I O Port AC Timing Specifications Num Characteristic Units Min Max P1 GPIO Valid to BCLK input setup 6 nSec P2 BCLK to GPIO Invalid input hold 0 nSec P3 BCLK to GPIO Valid output valid _ tbd nSec P4 BCLK to GPIO Invalid output hold 1 B nSec SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 34 Freescale Semiconductor Electrical Characteristics
22. Freescale Semiconductor Document Number SCF5250 Data Sheet Rev 1 1 04 2005 VRoHS SCF5250 Integrated ColdFire Microprocessor Data Sheet 1 Introduction Table of Contents li TO Ci HO O y RR creer TE rr errr rrr a 1 SCE5250 BIOCK DISQFBET 4 scyix 4 ayixk ninkak nin 8 Doc ti T la li OT aedis socie rein ik FRE r da s k 8 Signal Desemnmpllong cec dite eser ttes 9 Electrical Characteristics 21 Pin Out and Package Information 38 This document provides an overview of the SCF5250 ColdFire processor and general descriptions of SCF5250 features and its various modules 9 I N The SCF5250 was designed as a system controller decoder for compressed audio music players especially portable and automotive CD and hard disk drive players The 32 bit ColdFire core with Enhanced Multiply Accumulate EMAC unit provides optimum performance and code density for the combination of control code and signal processing required for audio decoding and post processing file management and system control Low power features include a hardwired CD ROM decoder advanced 0 13um CMOS process technology 1 2V core power supply and on chip 128K Byte SRAM that enables Windows Media Audio WMA decoding without the need for external DRAM in CD applications The SCF5250 is also an excellent general purpose system controller with over 110 Dhrystone 2 1 MIPS 120MHz perform
23. GPIO register Digital Audio Out The EBUOUT1 GPIO37 and QSPI CS1 EBUOUT2 GPIO16 multiplexed pins can serve as general purpose I O or as digital audio IEC958 output EBUOUT1 is digital audio out for consumer mode EBUOUT is digital audio out for professional mode During reset the pin is configured as a digital audio output 4 13 Subcode Interface There is a 3 line subcode interface on the SCF5250 This 3 line subcode interface allows the device to format and transmit subcode in EIAJ format to a CD channel encoder device The three signals are described in Table 10 Table 10 Subcode Interface Signal Signal name Description RCK QSPI DIN QSPI DOUT GPIO26 Subcode clock input When pin is used as subcode clock this pin is driven by the CD channel encoder QSPI_DOUT SFSY GPIO27 Subcode sync output This signal is driven high if a subcode sync needs to be inserted in the EFM stream QSPI CLK SUBR GPIO25 Subcode data output This signal is a subcode data out pin 4 14 Analog to Digital Converter ADC The ADOUT signal on the ADOUT SCLKA GPIOSS pin provides the reference voltage in PWM format This output requires an external integrator circuit resistor capacitor to convert it to a DC level to be input to the ADREF pin The six AD inputs are each fed to their own comparator The reference input to each ADREF is then multiplexed as only one AD comparison can be made at any one t
24. RTSI SDATA2 BS2 GPIO2 DDATA2 CTS0 GPIO3 and DDATA3 RTSO GPIOA are four bits wide This nibble wide bus displays captured processor data and break point status 4 19 5 Processor Status The processor status pins PSTO GPIO50 PST1 GPIO49 PST2 INTMON GPI048 and PST3 INTMON GPIOZ47 indicate the SCF5250 processor status During debug mode the timing is synchronous with the processor clock PSTCLK and the status is not related to the current bus transfer Table 13 shows the encodings of these signals Table 13 Processor Status Signal Encodings PST 3 0 Definition HEX BINARY 0 0000 Continue execution 1 0001 Begin execution of an instruction 2 0010 Reserved 3 0011 Entry into user mode 4 0100 Begin execution of PULSE and WDDATA instructions 5 0101 Begin execution of taken branch or Synch PC 6 0110 Reserved 7 0111 Begin execution of RTE instruction 8 1000 Begin 1 byte data transfer on DDATA 9 1001 Begin 2 byte data transfer on DDATA A 1010 Begin 3 byte data transfer on DDATA B 1011 Begin 4 byte data transfer on DDATA C 1100 Exception processing D 1101 Emulator mode entry exception processing E 1110 Processor is stopped waiting for interrupt F 1111 Processor is halted Rev B enhancement These encodings are asserted for multiple cycles SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 20 Freescale Semiconductor
25. alled waiting for instructions The OEP is implemented in a two stage pipeline featuring a traditional RISC data path with a dual read ported register file feeding an arithmetic logic unit ALU 1 2 2 DMA Controller The SCF5250 provides four fully programmable DMA channels for quick data transfer Single and dual address mode is supported with the ability to program bursting and cycle stealing Data transfer is selectable as 8 16 32 or 128 bits Packing and unpacking is supported Two internal audio channels and the dual UART can be used with the DMA channels All channels can perform memory to memory transfers The DMA controller has a user selectable 24 or 16 bit counter and a programmable DMA exception handler External requests are not supported SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 2 Freescale Semiconductor Introduction 1 2 3 Enhanced Multiply and Accumulate Module EMAC The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture The EMAC provides functionality in three related areas 1 Faster signed and unsigned integer multiplies 2 New multiply accumulate operations supporting signed and unsigned operands 3 New miscellaneous register operations Multiplies of 16x16 and 32x32 with 48 bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers plus signed fixed po
26. ance at a very competitive price The integrated peripherals and enhanced MAC unit allow the e 7 oF Z freescale semiconductor Freescale Semiconductor Inc 2005 All rights reserved Introduction SCF5250 to replace both the microcontroller and the DSP in certain applications Most peripheral pins can also be remapped as General Purpose I O pins 1 1 Orderable Part Numbers 1 1 1 Orderable Part Table Table 1 Orderable Part Numbers Orderable Part Maximum Clock Operating Number Frequency Package Type Temperature Range Part Status SCF5250AG120 120 MHz 144 pin QFP 20 C to 70 C Lead Free SCF5250CAG120 120 MHz 144 pin QFP 40 C to 85 C Lead Free SCF5250VM120 120 MHz 196 ball MAPBGA 20 C to 70 C Lead Free 1 2 SCF5250 Features 1 2 1 ColdFire V2 Core The ColdFire processor Version 2 core consists of two independent decoupled pipeline structures to maximize performance while minimizing core size The instruction fetch pipeline IFP is a two stage pipeline for prefetching instructions The prefetched instruction stream is then gated into the two stage operand execution pipeline OEP which decodes the instruction fetches the required operands and then executes the required function Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue the IFP can prefetch instructions in advance of their actual use by the OEP which minimizes time st
27. as a glueless interface to steer these bus buffers with two bus buffer output signals BUFENB1 GPIO29 and BUFENB2 GPIO30 4 8 I2C Module Signals There are two C interfaces on this device The PC module acts as a two wire bidirectional serial interface between the SCF5250 processor and peripherals with an C interface e g LED controller A to D converter D to A converter When SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 14 Freescale Semiconductor Signal Descriptions devices connected to the I C bus drive the bus they will either drive logic 0 or high impedance This can be accomplished with an open drain output Table 5 I C Module Signals l2c Module Signal Description IC Serial Clock The SCLO SDATA1 BS1 GPIO41 and SCL1 TXD1 GPIO10 bidirectional signals are the clock signal for first and second I C module operation The I C module controls this signal when the bus is in master mode all IC devices drive this signal to synchronize 1 C timing Signals are multiplexed C Serial Data The SDAO SDATA3 GPIO42 and SDA1 RXD1 GP1044 bidirectional signals are the data input output for the first and second serial lc interface Signals are multiplexed 4 9 Serial Module Signals The following signals transfer serial data between the two UART modules and external peripherals Table 6 Serial Module Signals Serial Module Signal Description Receive Data The RXDO GPlIO46
28. ata is sent to interfaces 1and 3 respectively During reset the pins are configured as serial data inputs Serial Audio Data Out SDATO1 TOUTO GPIO18 AND SDATAO2 GPIO34 multiplexed pins can serve as general purpose l Os or serial audio outputs During reset the pins are configured as serial data outputs Serial audio error flag The EF GPIO6 multiplexed pin can serve as general purpose I Os or error flag input As error flag input this pin will input the error flag delivered by the CD DSP EF GPIO6 is only relevant for serial interface SDATAM Serial audio CFLG The CFLG GPIO5 multiplexed pin can serve as general purpose I O or CFLG input As CFLG input the pin will input the CFLG flag delivered by the CD DSP CFLG GPIO5 is only relevant for serial interface SDATAM SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 16 Freescale Semiconductor Signal Descriptions 4 12 Digital Audio Interface Signals Table 9 Digital Audio Interface Signals Serial Module Signal Description Digital Audio In The EBUIN1 GPIO36 EBUIN2 SCLK OUT GPIO 13 EBUINS CMD SDIO2 GPIO14 and QSPI CSO EBUINA GPIO15 multiplexed signals can serve as general purpose input or can be driven by various digital audio IEC958 input sources Both functionalities are always active Input chosen for IEC958 receiver is programmed within the audio module Input value on the 4 pins can always be read from the appropriate
29. ation of the oscillator by means of a 16 bit pulse density modulation output Using this mode it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS signal The maximum trim depends on the type and design of the oscillator Typically a trim of 100 ppm can be achieved with a crystal oscillator and over 1000 ppm with an LC oscillator 1 2 25 Boot ROM The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash memory or ROM Typically this occurs in systems which have a separate MCU to control the system and or the SCF5250 is used as a stand alone decoder The SCF5250 can be booted in one of three modes External ROM Internal ROM Master mode boots from I2C SPI or IDE Internal ROM Slave mode boots from I2C or UART 1 2 26 Voltage Regulator The SCF5250 contains an on chip linear regulator that generates 1 2V from a 3 3V input The regulator is self contained and drives the 1 2V core voltage out on one pin that can be used to power the core supply pins at the board level In battery powered portable applications it is recommended that an external dc dc converter be used to generate the 1 2V core voltage to minimize power consumption SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 7 SCF5250 Block Diagram 2 SCF5250 Block Diagram block d Media Int Dacca e x3 x2 IDE SPDIF Interface Tx PLL GPI O 1 2V
30. bus that exchanges data between devices The I C bus minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices Bus capacitance and the number of unique addresses limit the maximum communication length and the number of devices that can be connected 1 2 19 Chip Selects Up to four programmable chip select outputs provide signals that enable glueless connection to external memory and peripheral circuits The base address access permissions and automatic wait state insertion are programmable with configuration registers These signals also interface to 16 bit ports CSO is active after reset to provide boot up from external FLASH ROM 1 2 20 GPIO Interface A total of 60 General Purpose inputs and 57 General Purpose outputs are available These are multiplexed with various other signals Seven of the GPIO inputs have edge sensitive interrupt capability 1 2 21 Interrupt Controller The interrupt controller provides user programmable control of a total of 57 interrupts There are 49 internal interrupt sources In addition there are 7 GPIOs where interrupts can be generated on the rising or falling edge of the pin All interrupts are autovectored and interrupt levels are programmable 1 2 22 JTAG To help with system diagnostics and manufacturing testing the SCF5250 includes dedicated user accessible test logic
31. cy difference signal to be used after low pass filtering to control varicap voltage to control crystal oscillation frequency This will lock the crystal to the incoming digital audio signal 4 18 Clock Out The MCLKI GPIO11 and QSPI CS2 MCLK2 GPIO24 can serve as DAC clock outputs When programmed as DAC clock outputs these signals are directly derived from the crystal oscillator or clock Input CRIN 4 19 Debug and Test Signals These signals interface with external I O to provide processor debug and status signals 4 19 1 Test Mode The TEST 2 0 inputs are used for various manufacturing and debug tests For normal mode TEST 2 1 should be ways be tied low TESTO should be set high for BDM debug mode and set low for JTAG mode 4 19 2 High Impedance The assertion of HI Z will force all output drivers to a high impedance state The timing on HI Z is independent of the clock NOTE JTAG operation will override the HI Z pin 4 19 3 Processor Clock Output The internal PLL generates this PSTCLK GPIOS1 and output signal and is the processor clock output that is used as the timing reference for the Debug bus timing DDATA 3 0 and PST 3 0 The PSTCLK GPIOSI is at the same frequency as the core processor SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 19 Signal Descriptions 4 19 4 Debug Data The debug data pins DDATA0 CTS1 SDATA0_SDIO1 GPIO1 DDATAI
32. d for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e Pa oF Z freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 All rights reserved Document Number SCF5250 Rev 1 1 04 2005
33. e 1 data i o SCLO SDATA1 BS1 GPIO41 SecureDigital serial data bit 1 MemoryStick interface 1 strobe DDATA1 RTS1 SDATA2 BS2 GPIO2 SecureDigital serial data bit 2 MemoryStick interface 2 strobe Reset output signal Selection between Reset function and SDATA2_BS2 is done by programming PLLCR register SDAO SDATAS GPIO42 SecureDigital serial data bit 3 4 16 Queued Serial Peripheral Interface QSPI The QSPI interface is a high speed serial interface allowing transmit and receive of serial data Pin descriptions are given in Table 12 Table 12 Queued Serial Peripheral Interface QSPI Signals Serial Module Signal Description QSPICLK SUBR GPIO25 Multiplexed signal IIC interface clock or QSPI clock output Function select is done via PLLCR register RCK QSPIDIN QSPI_DOUT GPIO26 Multiplexed signal IIC interface data or QSPI data input Function select is done via PLLCR register RCK QSPI DIN QSPI DOUT GPIO26 QSPI data output QSPI DOUT SFSY GPIO27 SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 18 Freescale Semiconductor Signal Descriptions Table 12 Queued Serial Peripheral Interface QSPI Signals continued Serial Module Signal Description QSPICSO EBUINAGPIO15 4 different QSPI chip selects QSPICS1 EBUOUT2 GPIO16 QSPICS2 MCLK2 GPIO24 CS1 QSPICS3 GPIO28 4 17 Crystal Trim The XTRIM GPIOO output produces a pulse density modulated phase frequen
34. e BCLKE active high output signal is used during synchronous mode to route directly to the SCKE signal of external SDRAMs This signal provides the clock enable to the SDRAM 4 5 Chip Selects There are three chip select outputs on the SCF5250 device CS0 CS4 and CSI QSPI CS3 GPIO28 and CS2 which is associated with the IDE interface read and write strobes IDE DIOR and IDE DIOW CSO and CS4 are multiplexed The SCF5250 has the option to boot from an internal Boot Rom The function of the CS0 CS4 pin is determined by the boot mode When the device is booted from internal ROM the internal ROM is accessed with CSO required for boot and the CS0 CS4 pin is driven by CS4 When the device is booted from external ROM Flash the CS0 CS4 pin is driven by CSO and the internal ROM is disabled The active low chip selects can be used to access asynchronous memories The interface is glueless 4 6 ISA bus The SCF5250 supports an ISA bus Using the ISA bus protocol reads and writes for one ISA bus peripheral is possible IDE DIOR GPIO31 and IDE DIOW GPIO32 are the read and write strobe The peripheral can insert wait states by pulling IDE IORDY GPIO33 CS2 is associated with the IDE DIOR and IDE DIOW 4 7 Bus Buffer Signals As the SCF5250 has a complicated slave bus which allows SDRAM asynchronous memories and ISA peripherals on the bus it may become necessary to introduce a buffer on the bus in certain applications The SCF5250 h
35. e Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorize
36. endent programmable control of the assertion and negation of chip select and write enable signals The SCF5250 also supports bursting ROMs 1 2 8 External Bus Interface The bus interface controller transfers information between the ColdFire core or DMA and memory peripherals or other devices on the external bus The external bus interface provides 23 bits of address bus SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 3 Introduction space a 16 bit data bus Output Enable and Read Write signals This interface implements an extended synchronous protocol that supports bursting operations 1 2 9 Serial Audio Interfaces The SC5250 digital audio interface provides three serial Philips IIS Sony EIAJ interfaces One interface is a 4 pin 1 bit clock 1 word clock 1 data in 1 data out the other two interfaces are 3 pin 1 bit clock 1 word clock 1 data in or out The serial interfaces have no limit on minimum sampling frequency Maximum sampling frequency is determined by maximum frequency on bit clock input This is 1 3 the frequency of the internal system clock 1 2 10 IEC958 Digital Audio Interfaces The SCF5250 has one digital audio input interface and one digital audio output interface The single output carries the consumer c channel 1 2 11 Audio Bus The audio interfaces connect to an internal bus that carries all audio data Each receiver places its received data on t
37. es address line 23 Out X A 23 GPO54 multiplexed with GPO54 and address 24 is multiplexed with A20 SDRAM access only Read write control R W Bus write enable indicates if read or Out H write cycle in progress Output enable OE Output enable for asynchronous Out negated memories connected to chip selects Data D 31 16 Data bus used to transfer word data In Out Hi Z Synchronous row address SDRAS GPIO59 Row address strobe for external Out negated strobe SDRAM Synchronous column SDCAS GPIO39 Column address strobe for external Out negated address strobe SDRAM SDRAM write enable SDWE GPIO38 Write enable for external SDRAM Out negated SDRAM upper byte enableSDUDQM GPO53 Indicates during write cycle if high byte Out is written SDRAM lower byte enable SDLDQM GPO52 Indicates during write cycle if low byte Out is written SDRAM chip selects SD CSO GPIO60 SDRAM chip select In Out negated SDRAM clock enable BCLKE GPIO63 SDRAM clock enable Out System clock BCLK GPIO40 SDRAM clock output In Out SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 9 Signal Descriptions Table 3 SCF5250 Signal Index continued j Input Reset Signal Name Mnemonic Function Output State ISA bus read strobe IDE DIOR GPIO31 There is 1 ISA bus read strobe and 1 In Out CS2 ISA bus write strobe They allow ISA bus write strobe IDE DIOW GPIO32 connectio
38. face 2 data i o EBUIN2 SCLK OUT GPIO13 Clock out for both MemoryStick In Out interfaces and for Secure Digital DDATAO CTS1 SDATAO_SDIO1 GPIO1 SecureDigital serial data bit 0 In Out MemoryStick interface 1 data i o SCLO SDATA1 BS1 GPIO41 SecureDigital serial data bit 1 In Out MemoryStick interface 1 strobe DDATA1 RTS1 SDATA2 BS2 GPIO2 SecureDigital serial data bit 2 In Out MemoryStick interface 2 strobe Reset output signal SDAO SDATA3 GPIO42 SecureDigital serial data bit 3 In Out ADC IN ADINO GPI52 Analog to Digital converter input In ADIN1 GPI53 signals ADIN2 GPI54 ADIN3 GPI55 ADIN4 GPI56 ADIN5 GPI57 ADC OUT ADREF Analog to digital convertor output In Out ADOUT SCLK4 GPIO58 signal Connect to ADREF via integrator network QSPI clock QSPI_CLK SUBR GPIO25 QSPI clock signal In Out QSPI data in RCK QSPI_DIN QSPI_DOUT GPIO26 QSPI data input In Out QSPI data out RCK QSPI_DIN QSPI_DOUT GPIO26 QSPI data out In Out QSPI_DOUT SFSY GPI027 QSPI chip selects QSPI CSO EBUIN4 GPIO15 QSPI chip selects In Out QSPI CS1 EBUOUT2 GPIO16 QSPI CS2 MCLK2 GPIO24 CS1 QSPI CS3 GPIO28 Crystal in CRIN Crystal input In Crystal out CROUT Crystal Out Out Reset In RSTI Processor Reset Input In Freescale Test Mode TEST 2 0 TEST pins In Linear regulator output LINOUT outputs 1 2 V to supply core Out SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 11 Signal Descriptions Table 3 SCF5250 Signal Index continued
39. gh to Low Threshold Point Vr 95 V Load Capacitance DATA 31 16 SCLK 4 1 SCLKOUT CL 50 pF EBUOUT 2 1 LRCK 3 1 SDATAO 2 1 CFLG EF DDATA 3 0 PST 3 0 PSTCLK IDE DIOR IDE DIOW IORDY Load Capacitance ADDR 24 9 BCLK C 40 pF Load Capacitance BCLKE SDCAS SDRAS SDLDQM C 30 pF SD CS0 SDUDQM SDWE BUFENB 2 1 Load Capacitance SDAO SDA1 SCLO SCL1 CMD_SDIO2 C 20 pF SDATA2_BS2 SDATA1 BS1 SDATAO_SDIO1 CS0 CS4 CS1 OE R W TA TXD 1 0 XTRIM TDO DSO RCK SFSY SUBR SDATA3 TOUTO QSPID OUT QSPICS 3 0 GP 6 5 Capacitance Vi 0 V f 1 MHz Cin 6 pF DATA 31 16 ADDR 24 9 PSTCLK BCLK SCL SDA PST 3 0 DDATA 3 0 TDSO SDRAS SDCAS SDWE SD C80 SDLDQM SDUDQM R W TOUTO RTS 1 0 TXD 1 0 SCLK 4 1 BKPT TMS DSI TDI DSCLK TRST Capacitance Cj is periodically sampled rather than 100 tested SCLK 4 1 SCLO SCL1 SDAO SDA1 CRIN RSTI SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 24 Freescale Semiconductor Table 19 Clock Timing Specification Electrical Characteristics NUM Characteristic Units Min Max CRIN Frequency 5 00 33 86 MHz C5 PSTCLK cycle time 7 1 _ nSec C6 PSTCLK duty cycle 40 60 C7 BCLK cycle time 14 2 nSec C8 BCLK duty cycle 45 55 Note There are only three choices for the valid Audio frequencies 11 29 MHz 16 93 MHz or 33 86 MHz
40. grated ColdFire Microprocessor Data Sheet Rev 1 1 22 Freescale Semiconductor Table 17 Linear Regulator Operating Specification Electrical Characteristics Characteristic Symbol Min Typ Max Input Voltage Vin 3 0V 3 3V 3 6 Output Voltage LINOUT Vout 1 14V 1 2V 1 26V Output Current lout 100mA 150mA Power Dissipation Pd 436uW Load Regulation 40mV 50mV 60mV 10 lout gt 90 lout Power Supply Rejection PSRR 40dB Note Apmos regulator is employed as a current source in this Linear regulator so a 10uF capacitor ESR 0 5 Ohm is needed on the output pin LINOUT to integrate the current Typically this will require the use of a Tantalum type capacitor SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 23 Electrical Characteristics Table 18 DC Electrical Specifications I O Vcc 3 3 Vdc 0 3 Vdc Characteristic Symbol Min Max Units Operation Voltage Range for I O Voc 3 0 3 6 V Input High Voltage Vin 2 5 5 V Input Low Voltage Vit 0 3 0 8 V Input Leakage Current 0 0 V 3 3 V lin 1 HA During Normal Operation Hi Impedance Three State Leakage Current Its 1 HHA 0 0 V 3 3 V During Normal Operation Output High Voltage lop 8mA 4mA 2mA VoH 2 4 V Output Low Voltage lo 8mA 4mA 2mA VoL 0 4 V Schmitt Trigger Low to High Threshold Point VT 1 47 V Schmitt Trigger Hi
41. he audio bus and each transmitter takes data from the audio bus for transmission Each transmitter has a source select register In addition to the audio interfaces there are six CPU accessible registers connected to the audio bus Three of these registers allow data reads from the audio bus and allow selection of the audio source The other three register provide a write path to the audio bus and can be selected by transmitters as the audio source Through these registers the CPU has access to the audio samples for processing Audio can be routed from a receiver to a transmitter without the data being processed by the core so the audio bus can be used as a digital audio data switch The audio bus can also be used for audio format conversion 1 2 12 CD ROM Encoder Decoder The SCF5250 is capable of processing CD ROM sectors in hardware Processing is compliant with CD ROM and CD ROM XA standards The CD ROM decoder performs following functions in hardware e Sector sync recognition e Descrambling of sectors e Verification of the CRC checksum for Mode 1 Mode 2 Form 1 and Mode 2 Form 2 sectors e Third layer error correction is not performed The CD ROM encoder performs following functions in hardware e Sector sync recognition e Scrambling of sectors SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 4 Freescale Semiconductor Introduction Insertion of the CRC checksum for Mode 1 Mode 2 Form 1 and Mode 2 Form
42. hold 0 nSec US CTS Valid to BCLK input setup 6 nSec U4 BCLK to CTS Invalid input hold 0 nSec U5 BCLK to TXD Valid output valid tbd nSec U6 BCLK to TXD Invalid output hold 3 nSec U7 BCLK to RTS Valid output valid tbd nSec U8 BCLK to RTS Invalid output hold 3 nSec Figure 7 UART Timing Definition SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 31 Electrical Characteristics Table 25 I2C Bus Input Timing Specifications Between SCL and SDA Num Characteristic Units Min Max M1 Start Condition Hold Time B bus clocks M2 Clock Low Period bus clocks M3 SCL SDA Rise Time 1 mSec VIL 0 5 V to VIH 2 4 V M4 Data Hold Time 0 nSec M5 SCL SDA Fall Time 1 mSec VIH 2 4 V to VIL 0 5 V M6 Clock High time 4 bus clocks M7 Data Setup Time nSec M8 Start Condition Setup Time bus clocks for repeated start condition only M9 Stop Condition Setup Time 2 bus clocks Table 26 I2C Bus Output Timing Specifications Between SCL and SDA Num Characteristic Units Min Max M Start Condition Hold Time 6 bus clocks M2 Clock Low Period 10 bus clocks M3 SCL SDA Rise Time note 2 note2 mSec Vi 7 0 5 V to Vin 2 4 V M4 Data Hold Time 7 bus cl
43. ime NOTE To use the ADINx as General Purpose inputs rather than there analogue function it is necessary to generate a fixed comparator voltage level of VDD 2 This can be accomplished by a potential divider network connected to the ADREF pin However in portable applications where stand by power SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 17 Signal Descriptions consumption is important the current taken by the divider network in stand by mode could be excessive Therefore it is possible to generate a VDD 2 voltage by selecting SCLK4 output mode and feeding this clock signal which is 50 duty cycle through an external integration circuit This would generate a voltage level equal to VDD 2 but would be disabled when stand by mode was selected 4 15 Secure Digital MemoryStick Card Interface The device has a versatile flash card interface that supports both SecureDigital and MemoryStick cards The interface can either support one SecureDigital or two MemoryStick cards No mixing of card types is possible Table 11 gives the pin descriptions Table 11 Flash Memory Card Signals Flash Memory Signal Description EBUIN2 SCLKOUT GPIO13 Clock out for both MemoryStick interfaces and for SecureDigital EBUIN3 CMD_SDIO2 GPIO14 Secure Digital command line MemoryStick interface 2 data i o DDATAO CTS1 SDATAO SDIO1 GPIO1 SecureDigital serial data bit 0 MemoryStick interfac
44. in Multiplex Control Registers GPIO FUNCTION GPIO1 FUNCTION and PIN CONFIG At Power on reset all pins are set to their primary function 4 3 SCF5250 Bus Signals These signals provide the external bus interface to the SCF5250 SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor Signal Descriptions 4 3 1 Address Bus The address bus provides the address of the byte or most significant byte of the word or longword being transferred The address lines also serve as the DRAM address pins providing multiplexed row and column address signals e Bits 23 down to 1 and 24 of the address are available A24 is intended to be used with 256 Mbit DRAM s Signals are named A 23 1 A20 24 4 3 2 Read Write Control This signal indicates during any bus cycle whether a read or write is in progress A low is write cycle and a high is a read cycle 4 3 3 Output Enable The OE signal is intended to be connected to the output enable of asynchronous memories connected to chip selects During bus read cycles the ColdFire processor will drive OE low 4 3 4 Data Bus The data bus D 31 16 is bi directional and non multiplexed Data is registered by the SCF5250 on the rising clock edge The data bus uses a default configuration if none of the chip selects or DRAM bank match the address decode All 16 bits of the data bus are driven during writes regardless of port width or operand
45. int fractional input operands The EMAC has a single clock issue for 32x32 bit multiplication instructions and implements a four stage execution pipeline 1 2 4 Instruction Cache The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock The SCF5250 processor uses a 8K byte direct mapped instruction cache to achieve 107 MIPS at 120 MHz The cache is accessed by physical addresses where each 16 byte line consists of an address tag and a valid bit The instruction cache also includes a bursting interface for 16 bit and 8 bit port sizes to quickly fill cache lines 1 2 5 Internal 128 KByte SRAM The 128 KByte on chip SRAM is available in two banks SRAMO 64K and SRAMI 64K It provides one clock cycle access for the ColdFire core This SRAM can store processor stack and critical code or data segments to maximize performance Memory in SRAMI can be accessed under DMA 1 2 6 SDRAM Controller The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM up to 32 MB 256 Mbits The controller supports a 16 bit data bus A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards The controller operates in page mode non page mode and burst page mode and supports SDRAMS 1 2 7 System Interface The SCF5250 provides a glueless interface to 16 bit port size SRAM ROM and peripheral devices with indep
46. lect 4 32 RW e Bus write enable Out 33 OSC PAD VDD 34 CRIN l Crystal external clock input X SCF5250 Integrated ColdFire Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 39 Pin Out and Package Information Table 33 144 QFP Pin Assignments continued 144 QFP em Pin State Pin Name Type Description After Reset Number 35 CROUT O Crystal clock output X 36 OSC PAD GND OSC PAD GND 37 PLL CORE1 VDD 38 PLL CORE2 VDD 39 PLL CORE2 GND 40 PLL CORE1 GND 41 OE O Output Enable Out 42 IDE DIOW GPIO32 l O IDE DIOW Out HIGH 43 IDE IORDY GPIO33 I O IDE interface IORDY In LOW 44 IDE DIOR GPIO31 l O IDE interface DIOR Out HIGH 45 BUFENB2 GPIO30 l O External buffer 2 enable Out HIGH 46 BUFENB1 GPIO29 l O External buffer 1 enable Out HIGH 47 TA GPIO12 y o Transfer acknowledge In requires pull up for normal operation 48 WAKE UP y o Wake up input In requires GPIO21 pull up for normal operation 49 EBUIN2 SCLK OUT l O Audio interfaces EBU in 2 In LOW GPIO13 FlashMedia Clock 50 EBUIN3 CMD SDIO2 l O Audio interfaces EBU in 3 In LOW GPIO14 FlashMedia Command interface 51 PAD VDD 52 EBUIN1 GPIO36 l O Audio interfaces EBU in 1 In LOW 53 EBUOUT1 GPIO37 l O Audio interfaces EBU out 1 Out LOW 54 XTRIM GPIOO l O Audio interfaces X tal trim Out clock out 55 CS1 QSPI CSS GPIO28 l O Chip select 1 QSPI Chip Select 3 Out HIGH 56 RCK
47. ls provide the external audio interface Table 8 Serial Audio Interface Signals Serial Module Signal Description Serial Audio Bit Clock The SCLK1 GPIO20 SCLK2 GPIO22 and SCLK3 GPIO35 multiplexed pins can serve as general purpose l Os or serial audio bit clocks As bit clocks these bidirectional pins can be programmed as outputs to drive their associated serial audio IIS bit clocks Alternately these pins can be programmed as inputs when the serial audio bit clocks are driven internally The functionality is programmed within the Audio module During reset these pins are configured as input serial audio bit clocks Serial Audio Word Clock The LRCK1 GPIO19 LRCK2 GPIO23 and LRCKS GPIO43 AUDIO CLOCK multiplexed pins can serve as general purpose l Os or serial audio word clocks As word clocks the bidirectional pins can be programmed as inputs to drive their associated serial audio word clock Alternately these pins can be programmed as outputs when the serial audio word clocks are derived internally The functionality is programmed within the Audio module During reset these pins are configured as input serial audio word clocks LRCKS3 GPIO43 AUDIO CLOCK can be used as the external audio clock input If the core clock chosen to be non audio specific Serial Audio Data In The SDATAM GPIO17 and SDATAI3 GPIO8 multiplexed pins can serve as general purpose I Os or serial audio inputs As serial audio inputs the d
48. n external signal or interrupts the CPU when the timer reaches a set value and can also generate waveforms on TOUTO The timer unit has an 8 bit prescaler that allows programming of the clock input frequency which is derived from the system clock In addition to the 1 and 16 clock derived from the bus clock CPU clock 2 the programmable timer output pins either generate an active low pulse or toggle the outputs 1 2 16 IDE and SmartMedia Interfaces The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a minimum of external hardware The external hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE bus The control signals for the buffers are generated in the SCF5250 1 2 17 Analog Digital Converter ADC The six channel ADC is a based on the Sigma Delta concept with 12 bit resolution Both the analogue comparator and digital sections of the ADC are provided internally An external integrator circuit resistor capacitor is required which is driven by the ADC output A software interrupt is provided when the ADC measurement cycle is complete SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 Freescale Semiconductor 5 Introduction 1 2 18 I C Module The two wire C bus interface which is compliant with the Philips PC bus standard is a bidirectional serial
49. n of one independent ISA In Out CS2 bus peripherals e g an IDE slave device ISA bus wait signal IDE IORDY GPIOS33 ISA bus wait line available for both In Out busses Chip Selects 2 0 CS0 CS4 Enables peripherals at programmed Out negated CS1 QSPI_CS3 GP1028 addresses In Out CS 0 provides boot ROM selection Buffer enable 1 BUFENB1 GPIO29 Two programmable buffer enables In Out Buffer enable 2 BUFENB2 GPIO30 allow seamless steering of external In Out buffers to split data and address bus in sections Transfer acknowledge TA GPIO12 Transfer Acknowledge signal In Out Wake Up WAKE UP GPIO21 Wake up signal input In Serial Clock Line SCLO SDATA1 BS1 GPIO41 Clock signal for Dual 1 C module In Out SCL1 TXD1 GPIO10 operation Serial Data Line SDAO SDATA3 GPIO42 Serial data port for second I C module In Out SDA1 RXD1 GPIO44 operation Receive Data SDA1 RXD1 GPIO44 Signal is receive serial data input for In RXDO GPIO46 DUART Transmit Data SCL1 TXD1 GPIO10 Signal is transmit serial data output for Out TXDO GPIO45 DUART Request To Send DDATAS RTSO GPIO4 DUART signals a ready to receive Out DDATA1 RTS1 SDATA2 BS2 GPIO2 data query Clear To Send DDATA2 CTSO GPIO3 Signals to DUART that data can be In DDATAO CTS1 SDATAO_SDIO1 GPIO1 transmitted to peripheral Timer Output SDATAO1 TOUTO GPIO18 Capable of output waveform or pulse Out generation IEC958 inputs EBUIN1 GPIO36 audio interfaces IEC958 inputs In EBUIN2 SCLK_OUT GPIO13 EBUINS CMD SDIO2 GPIO14 QSPI
50. ocks M53 SCL SDA Fall Time 3 nSec Viy7 2 4 V to Vj 0 5 V Me Clock High time 10 bus clocks M7 Data Setup Time 2 bus clocks M8 Start Condition Setup Time 20 bus clocks for repeated start condition only M9 Stop Condition Setup Time 10 bus clocks p 1 Note Output numbers are dependent on the value programmed into the MFDR an MFDR programmed with the maximum frequency MFDR 0x20 will result in minimum output timings as shown in the above table The MBUS interface is designed to scale the actual data transition time to move it to the middle of the SCL low period The actual position is affected by the prescale and division values programmed into the MFDR however numbers given in the above table are the minimum values 2 Since SCL and SDA are open collector type outputs which the processor can only actively drive low the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull up resistor values 3 Specified at a nominal 20 pF load SCF5250 Integrated ColdFire amp Microprocessor Data Sheet Rev 1 1 32 Freescale Semiconductor Electrical Characteristics Figure 8 I2C Timing Definition Table 27 I2C Output Bus Timings 96 MHz Num Characteristic Units Min Max M10 SCL SDA Valid to BCLK input setup 2 nSec M11 BCLK to SCL SDA Invalid input hold 4 5 nSec M12 BCLK to SCL SD

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