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Insider`s Guide Philips ARM®7

1. Re bm L ij oben m i ii ie P um c IL ut mt a 1 ALL NM de au le Le Ss e a m 1 Em E EM r Ms s tT a n r m Er SL EE Fm Con Fim p I af ir ms ee fee Somme s me o The Keil UVISION a k a uVision IDE is designed to support several compilers the Gnu C compiler The ARM development suite and the Keil ARM compiler Before compiling make sure you have the GNU compiler selected This is done by activating the project workspace right clicking and selecting manage components In this dialog select the Folders extensions tab and make sure the Keil ARM tools box is selected Hitex UK Ltd Page 120 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Next click on the Books tab Compare mi eu poeme an Pek a Casques Folies Cot Hubs Too pecia OU D hun liim B Usum Lada Sains soe Change Hook Mer uses Book T UATR ARM Pte Loan lounge er LPC 1 E ox ce Now change the path to point to the LPC2000 user manual which can be found on the CD in the User Manuals directory You can now add any other documentation you wish through these menus Once the project has been fully c
2. void main void IODIR1 OxOOFF0000 Set the LED pins as outputs PINSELO 0x20000000 Select the EINT1 function in the pin connect block VICIntSelect 0x00008000 Enable a Vic Channel as FIQ VICIntEnable 0x00008000 Enable the EINT1 interrupt in the VIC IOCLR1 0 00 0000 Clear the LED s while 1 Loop here forever In the startup code the FIQ interrupt routine must be added to the vector table The address of the FIQ interrupt routine is suffixed with A to demote the routine as an ARM 32 Bit instruction set routine EXTERN CODE32 fiqint A Startup PROC CODE32 Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC PAbt Addr LDR PC DAbt Addr OP Reserved Vector LDR PC PC Ox0FFO LDR PC FIQ Addr Load the address of the FIQ routine into the PC from the constants table Reset_Addr DD Reset_Handler Undef_Addr DD Undef_Handler SWI_Addr DD SWI_Handler PAbt_Addr DD PAbt_Handler DAbt_Addr DD DAbt_Handler DD 0 Reserved Address IRQ Addr DD IRQ Handler Addr DD figint A The address of the routine is stored here When the INT1 button is pressed on the MCB2100 the FIQ interrupt is generated and the code will vector to the figint routine The routine is declared as an interrupt routine by using the fiq language extension Before exiting the ISR the peripheral flag is cleared void fiqint
3. E rare LP Fee Arey T en tit inte wear From the menu bar select Project New Project Hitex UK Ltd Page 174 hitex ms 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS In the New Project dialog name the project first uv2 and select Save A select new device for target dialog will appear Navigate through the device data base and select the Philips LPC2129 folder and select OK Hitex UK Ltd Page 175 hitex me 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS In the project browser highlight the Target1 root folder and select the local menu by pressing the right mouse button In this menu select Options for Target Translate Fle Build amp dd Giles to Group Remove Ien In the Linker tab select the linker file flash Id and tick the Garbage collection and do not use standard startup files boxes Note To build the project so it will run within the on chip RAM of the LPC2100 device configure the Text start as select the linker file RAM Id Hitex UK Ltd Page 176 hitex mum 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS In the debug tab make sure the Use Simulator radio button is active Also make sure Load Application at Startup and Go till main are checked ASIE for larges Simulata Target Duen Ling C em Lee LA Locate Debug Line
4. In the while loop we insert the call to func while 1 BEGIN USER CODE MAIN LOOP func END USER CODE MAIN LOOP We save this file and go back to StartEasy Here we click on the yellow folder Project Files and click on custom files with the right mouse button Hitex UK Ltd Page 195 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS H startEasy_for_ARM File Edit Info Project Thumb CA Project Settings Ca LPC2000 Setup gr Project files Source files Custom filas Select Deselect add file remove Expand Collapse Sort Now select add file In the file dialog we select the created file module c Click with the left mouse button on the new file entry module c and change the code type settings to THUMB sE StartEasy_for_ARM File Edit Info Project Thumb Options for custom C Files 1 Project Settings El Source File Idlec o C3 LPC2000 Setup z UMB E Project files Code type THUMB E Source files Location Intem Y g Custom files o Now create the new application but since there are now changes in the HiTOP project file we have to close HiTOP first Click on the menu File and select update code The changed project and application are now created and when we open it with HITOP and step through the code until the function func we s
5. 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS AS rece Ea eterno DM mam Er crade FO oreet ioci fo r rk FO r fl piri x AO pur chee To complete the filter settings we click with the right mouse button into a new line of the trace control window and select change Now we enter code_size isr_TIMERO into the length field which defines the length of the region to the same length as as the function isr_TIMERO We click on the advanced button and we select as action of the trigger IFltinc which means record all instructions of this region into the trace r Trigger Address Range Trigger Type Start fitmainttisr_TIMERO Execute C Read C White code sizefisr TIMERO Read lee r Advanced Trigger Conditions Value Range Minimum 00000006 External Input ox z Maximum Bus State Executed x Type DWord Action on Trigag Trace Recording Now we start the application F5 and after a short time we stop again shift F5 and look at the trace display Hitex UK Ltd Page 203 mmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS Fram Address State Data HLL Source Line Extern Time 0 0 197 3 0 05 us 11 0 198 SWITCH IRQ TO SYS 3 0 54 us 15 0 202 interrupt_identification TIMERO_IR 3 0 96 us 21 0 205 TIMERO_IR 0xFF 3 1 65 us 28
6. return fibo 5 ni main void Toggle Bookmark ine is Show Disassembly at 0xC8 Set Program Counter for Insert include LPCZI0X counter 0 H Run to Cursor line for i 0 i lt 2I Go To Line counter lh Insert Remove Breakpoint fiboCount Fibi WW Enable Disable Breakpoint Clear complete Code Coverage Info Run to a point in the code This is a quick way of getting to an arbitrary pointing your code Select a line of code open the local menu select run to cursor This will execute code until this line is reached You can also select Set program counter This forces the PC to the current position without running any code Hitex UK Ltd Page 127 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Select view disassembly to see the underlying assembler code Dxon cOnE4 Ri Rit 000000 8 R13r R4 R6 R11 R12 R14 PC Ux D CODEC FL1 R12 0x 00000004 O000G00FO EBFFFFEA EL 0205000040 2 for 21 10 OS OD CODE 4 RS 050030 000 R6 n noon lt 2D ies 131 xanacol G CEEiAD4DOSB HOW Aa 141 ter 00000104 5950000 RO RS 0000108 E2800001 ADD RO FO 0000000 x D OOID ESS50000 STR Ro R5 151 fLboCownt Fibonncci count amp er JE M nanngooli EBFTFFEG EL Fibcsacci xOnDOODBO 114 FE59F1014 F1 FC 060
7. mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 13 Exercise 10 Phase Locked Loop In this exercise we will configure the operation of the PLL to give maximum speed of operation for the ARM 7 core for a 12 00MHz oscillator We will also configure the VLSI bus to run at half the speed of the ARM7 core Using Cclk M x OSC calculate the maximum integer value for M given that OSC 12 00 MHz and Cclk lt 60 MHz Using Fcco cclk x 2 x P calculate a suitable value for P using the result for Cclk calculated above and were 156 MHz lt Fcco lt 320MHz Using the results for M and P calculate the value for PLLCFG answer M 5 and P 2 Calculate the value for VPBDIV to set Pclk at half the frequency of Cclk Open the project in C work EX7 PLL Complete the code in main as follows Set multiplier and divider of PLLin PLLCFG to give 60 00 MHz PLLCFG 0x00000024 Enable the PLL in PLLCON PLLCON 0x00000001 Update the internal PLL registers with the feed sequence PLLFEED PLLFEED 0x000000AA 0x00000055 Test the Lock bit in PLLSTAT until the PLL is stable while PLLSTAT amp 0x00000400 Connect the PLL as the main clock source PLLCON 0x00000003 Set the VLSI peripheral bus to 30 00MHz VPBDIV 0x00000002 Compile the code and load it into the board Hitex UK Ltd Page 148 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Run the initPLL routine a
8. wj m cos voeu e Compile and download the code into the debugger Open the disassembly window and single step through the code using the F11 key Hitex UK Ltd Page 134 5 Tutorial With Keil Tools Observe the switch from 32 bit to 16 bit code and the THUMB flag in the CPSR 1 CPSR lt 00 2 thumb_function 46 for 1 0 00010000 1 lt 32 bit ARM code ree 0 0000013 ES9FCOOO 0x00000140 E12FFF1C 0 00000144 00000149 0 47 0 48 0 0x00000148 4806 0 0 0000014 E007 0x10 LDR BX DD LDR B hitex mum DEVELOPMENT TOOLS R12 PC R12 0x00000149 0 010000 i i 1 RD PC 00018 0x0000015C The processor is running in ARM 32 bit mode the T bit is clear and the instructions are 4 bytes long A call to the THUMB function is made which executes a BX instruction forcing the processor into THUMB mode 16 bit Hitex UK Ltd Page 135 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 7 Exercise 4 Using STDIO Libraries In this exercise we will look at tailoring the Printf function to work with the LPC2100 UART We will look at the registers of the UART s in more detail later Open the project in EX4 printflwork In main c add a message for transmission to the printf statement while 1 1 printf Your Message Here Mn Call the prinfF function Add the file serial c in the work directory to the projec
9. Peripheral Dos ON Chip Pria Page 39 hitex mm 3 System Peripherals DEVELOPMENT TOOLS 3 3 Memory Map Despite the number of internal buses the LPC2000 has a completely linear memory map The general layout is shown below 4 0 GB Peripherals 3 75GB 0xF000 0000 VPB Peripherals 3 5 GB OxE000 0000 3 0 GB 0xC000 0000 Reserved for External Memory The memory map of the LPC2000 includes regions for on chip flash memory user SRAM a 0x8000 0000 pre programmed bootloader external bus and Boot Block user peripherals Reserved for On Chip Memory On Chip Static RAM 1 0 GB 0x4000 0000 Reserved for Special Registers Ox3FFF 8000 Reserved for On Chip Memory 0 0 GB 0x0000 0000 The on chip flash is fixed at 0 00000000 upwards with the user RAM fixed at 0x4000000 upwards The LPC2000 is pre programmed at manufacture with a FLASH bootloader and the ARM real monitor debug program These programs are placed in the region OX7FFFFFF 0x8000000 The region between 0x8000000 and 0 000000 is reserved for external memory Currently the LPC22xx devices are capable of addressing external memory via four chipselects each with a 16 Mbyte page 2 0GB System Control Block OxFFDF FFFF Reserved po All the user peripherals are located on D the VLSI peripheral bus Each Pin Connect Block peripheral has a 16K address range for its registers OxF000 0000 GPIO g
10. AData Trace i ett iet itii te Trace Examples 2 dite tem edet ety Appendices cien ene imu Penes Bibliography uite exit Webliography in metet ds es Re ner t tede R feience Sites tah ese Eum Eis Tools and Software Development Evaluation Boards And Modules Hitex UK Ltd Page 6 Introduction 182 183 185 187 187 188 189 191 194 195 197 197 199 199 199 Introduction to the LPC2000 Introduction Introduction This book is intended as a hands on guide for anyone planning to use the Philips LPC2000 family of microcontrollers in a new design It is laid out both as a reference book and as a tutorial It is assumed that you have some experience in programming microcontrollers for embedded systems and are familiar with the C language The bulk of technical information is spread over the first four chapters which should be read in order if you are completely new to the LPC2000 and the ARM7 CPU The first chapter gives an introduction to the major features of the ARM7 CPU Reading this chapter will give you enough understanding to be able to program any ARM7 device If you want to develop your knowledge further there are a number of excellent books which describe this architecture and some of these are listed in the bibliography Chapter Two is a description of how to write C programs to run on an ARM7 processor and as such describes specific extensions to
11. Hitex UK Ltd Page 152 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 17 Exercise 14 Nested Interrupts In this exercise we will setup two interrupt sources First timerO which sets a port pin high for the duration of the interrupt and secondly external interrupt one which also sets a second port pin high for the duration of the interrupt Under normal operation both interrupts would block each other while they are running However by adding the appropriate macros to the External interrupt routine we can allow the timer interrupt to interrupt the external interrupt routine so it will be guaranteed to run every 10ms This can be observed on the LEDS on theMCB2100 or in the logic analyser of the simulator Open the project in EX14 Interrupt Non Vectored work In Main c complete the two IENABLE and IDISABLE macros define IENABLE Nested Interrupts Entry __asm MRS LR SPSR Copy SPSR irq to LR asm STMFD SP LR Save SPSR irq asm MSR CPSR c 0 1 Enable IRQ Sys Mode asm STMFD SP LR Save LR define IDISABLE Nested Interrupts Exit asm LDMFD SP LR Restore LR asm MSR CPSR c 0x92 Disable IRQ Mode asm LDMFD SP LR Restore SPSR irq to LR asm MSR SPSR cxsf LR Copy LR to SPSR irq Add the two macros to the External interrupt service routine void EXINT1 ISR v
12. IOSET1 EXTINT Exercise 11 void 0x00FF0000 0x00000002 FIQ interrupt __fiq Set the LED pins Clear the peripheral interrupt flag This exercise sets up the VIC to respond to an external interrupt line as a FIQ exception Hitex UK Ltd Page 64 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 12 6 Vectored IRQ If we have one interrupt source defined as an FIQ interrupt all the remaining interrupt sources must be connected to the remaining IRQ line To ensure efficient and timely processing of these interrupts the VIC provides a programmable hardware lookup table which delivers the address of the C function to run for a given interrupt source The VIC contains 16 slots for vectored addressing Each slot contains a vector address register and a vector control register V Add For a Vectored IRQ the VIC provides a hardware ecior Address lookup table for the address of each ISR The interrupt priority of each peripheral may also be Daiju Vector controlled Vector Address 0 0 4 5 Y vector Address 15 5 vector Contato D or Contra Channa 4 lee Skin Chana S 1 Vector Control 15 Vector Control n Each vector address slot may be assigned to any peripheral interrupt channel the lower the number of the vector address the higher its Channel 15 priority The Vector Control Register contains two fields a channel field
13. Pede e toe neg 101 CAN Message Objects sssssssesseeeeneeeeen eren 103 CAN Bus Arbitration eti ce a Eee mte Matt 105 Bit TIMNA oit HS rn BRE e 106 CAN Message Transmission seeeeeneeneme 108 CAN Error Containment ss 110 Hitex UK Ltd Page4 Introduction Introduction to the LPC2000 Introduction 4 12 8 CAN Message Reception 113 4 12 9 Acceptance Filtering iicet ee mienne 114 4 12 9 1 Configuring The Acceptance Filter 115 4 13 Since UU 116 5 Chapter 5 Keil Tutorial 118 5 1 Install tlon ente eene nene iet R 118 5 1 1 Using the Keil UVISION IDE 119 5 2 Exercise 1 Using the Keil Toolset se 120 5 3 Using The Deb gger ner nri tereti de ite Les 126 5 4 Using The ULINK Hardware 130 5 4 1 Setting up the ULINK JTAG hardware 130 5 5 Exercise 2 Startup Code 133 5 6 Exercise 3 Using THUMB Code 134 5 7 Exercise 4 Using STDIO 136 5 8 Exercise 5 Simple Interrupt 138 5 9 Exercise 6 Software Interrupt ecceeeseeeeeeeseeeeeeeeeeeeeeeaeeseaeeseaeeeeeeeeses 140 5 10 Exerci
14. The register defines the action A applied to the match pin when a match is made on its channel The CPU can also directly control the logic level on the match pin by directly writing to the first four bits in the register EMA Contact Bits na Da n Lar Pin fet Pin 11 Tagg Pin Exel Visio 0 1 The external match register contains a configuration field for each match channel Programming this field decides the action to be carried out on the match pin when a match event occurs In addition each match pin has a bit that can be directly programmed to change the logic level on the pin The example below demonstrates how to perform simple pulse width modulation using two match channels Match channel zero is used to generate the period of the PWM signal When the match event occurs the timer is reset and an interrupt is generated The interrupt is used to set the Match 1 pin high Match channel 1 is used to control the duty cycle When the match 1 event occurs the Match 1 pin is cleared to zero So by changing the value in the Match 1 register it is possible to modulate the PWM signal int main void VPBDIV 0x00000002 Configure the VPB divi PINSELO 0x00000800 Matchl as output TOPR 0x0000001E Load presaler TOTCR 0x00000002 Reset counter and presale TOMCR 0x00000003 On match reset the counter and generate an
15. ii The manage components project components option also allows you to customise your project by adding extra source groups and different build options such as build for RAM debugging or Flash debug in the simulator or with the JTAG Build the code by selecting the Project build target menu or the F7 key Build Icons are also available on the toolbar Start debugger Make project t gem Peet CT shes Pt AN ARS PR jas 2 fers oss x For the rest of the tutorial the projects will be defined but relevant bits of code will be missing A complete copy of the exercise can be found in the solution directory All the example code is included on your CD Hitex UK Ltd Page 125 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 3 Using The Debugger Launch the debugger by selecting the debugger start stop debugger session menu or the button on the toolbar Debugger Toolbar Source Window Disassembly Window Buampin 1 pr LANE Pamcmrigaius efi m demos Eragi EEN 0 20 ee laine sibna fregesesy jj das E Parga Hil TRI i Bil ETE S mia DREP BID EL CARS IL ea LJ n miser EM al EITIAZPTS paidi Lise PTIT d ne ret ICD et PO m F oon Pi D du
16. 4 User Peripherals DEVELOPMENT TOOLS At the end of a conversion the Done bit is set and an interrupt may also be generated The conversion result is stored in the V Vdda field as a ratio of the voltage on the analogue channel divided by the voltage on the analogue power supply pin The number of the channel for which the conversion was made is also stored alongside the result This value is stored in the CHN field Finally if the result of a conversion is not read before the next result is due it will be overwritten by the fresh result and the OVERUN bit is set to one The example below demonstrates use of the A D converter in hardware mode int main void VPBDIV 0x00000002 Set the Pclk to 30 MHz IODIR1 0 00 0000 P1 16 23 defined as Outputs ADCR 0x00270607 Setup A D 10 bit AINO 3MHz VICVectCnt10 0x00000032 connect A D to slot 0 VICVectAddr0 unsigned AD_ISR pass the address of the IRQ into the VIC slot VICIntEnable 0x00040000 enable interrupt while 1 void AD ISR void unsigned val chan Static unsigned result 4 val ADCR val val gt gt 6 amp Ox03FF Extract the A D result chan ADCR gt gt 0x18 amp 0x07 result chan val The A D has a second software conversion mode In this case a channel is selected for conversion using the SEL bits and the conversion is started under software control by writing 0x01 to the START fie
17. 4 transmission to the channel being used tA Sync Sample Seg Point end of Tseg1 so changing the ratio of Tseg1 to Tseg2 adjusts the sample point This allows the CAN protocol to be tuned to the transmission channel If you are using long transmission lines the sample point can be moved backwards If you have drifting oscillators you can bring the sample point forward In addition the receivers can adjust their bit rate to lock onto the transmitter This allows the receivers to compensate for small variations in the transmitter bit rate The amount that each bit can be adjusted is called the synchronous jump width and may be set to between 1 4 time quanta and is again user definable To calculate the bit timing the formula is given by Bit rate Pclk BRP x 1 Tsegl Tseg2 Where BRP Baud rate prescaler This calculation has a lot of unknowns If we assume that we want to reach a bit rate of 125K with a 60 MHz Pclk and a sample point of about 70 here is how the BRP calculation is performed The total number of time quanta in a bit period is given by 1 Tseg1 Tseg2 If we call this term QUANTA and rearrange the equation in terms of the Baud rate prescaler BRP Pclk Bit rate x QUANTA Using our known values BRP 60 MHz 125K x QUANTA Now we know that we can have between 8 and 25 time quanta in the bit period so using a spreadsheet we can substitute in integer values between 8 and 25 for
18. E iera Fang TTTTTT Litt bee lisi C 4 155 g hisen Capia 0 3 the general purpose timers when new value is written to a match register the new match value becomes effective immediately Unless care is taken in your software this may be part way through a PWM cycle If you are updating several channels the new PWM values will take effect at different points in the cycle and may cause unexpected results The PWM modulator has an additional shadow latch mechanism which allows the PWM values to be updated on the fly but the new values will only take effect simultaneously at the beginning of a new cycle The PWM shadow latches allow the match registers to be updated thought the PWM cycle but the new Miami Values will only become effective at the beginning of a cycle Tiras ore The value in given match register be updated at any time but it will not become effective until the bit corresponding to the match channel is set in the Latch Enable register LER Once the LER is set the value in the match register will be transferred to the shadow register at the beginning of the next cycle This ensures that all updates are done simultaneously at the beginning of a cycle Apart from the shadow latches the PWM modulator match channels function in the same way as the timer match registers Hitex UK Ltd Page 78 hitex mum 4 User Peripherals DEVELOP
19. Worst Case Instruction execution Entry to first Instruction FIQ Latency 12 cycles 200 nS 60MHz IRQ Interrupt sync Worst case instruction execution Entry to first instruction Nesting IRQ Latency 25 cycles 416nS 60MHz 3 12 10 Nested Interrupts The interrupt structure within the ARM7 CPU and the VIC does not support nested interrupts If your application requires interrupts to be able to interrupt ISRs then you must provide support for this in software Fortunately this is easy to do with a couple of macros Before discussing how nested interrupts work it is important to remember that the IRQ interrupt is disabled when the ARM7 CPU responds to an external interrupt Also on entry to a C function that has been declared as an IRQ interrupt routine the LR_isr is pushed onto the stack IRQ Mode System Mode Two macros can be used to allow nested interrupt processing in the LPC2000 for a very small code and time overhead Once the processor has entered the IRQ interrupt routine we need to execute a few instructions to enable nested interrupt handling First of all the SPSR_irq must be preserved by placing it on the Hitex UK Ltd Page 69 hitex mum 3 System Peripherals DEVELOPMENT TOOLS stack This allows us to restore the CPSR correctly when we return to user mode Next we must enable the IRQ interrupt to allow further interrupts and switch to the system mode remember system mod
20. Software Development DEVELOPMENT TOOLS The basic syntax is shown below ERAM 0x40000000 0x40000FFF This entry should be made in the LA Locate dialogue of the options for target menu Ces Jour 0 gee ere E xl Beste Tapt Cut Linking E Ju Lake L Lim feux D ni Live bloc Lipad corn Finger hee BOOT CIT FFL CCE CONST zj Eu FE Cancel Defauts Hep The compiler does not check if your RAM function is calling functions or library functions which are not also stored in the RAM So if your fast RAM function makes calls to a maths routine stored in the FLASH memory you may not get the performance you were expecting This method of locating functions in RAM is not only simple and easy to use it has the added advantage that the linker knows where the function will finally end up and can place the debug symbols at the correct address This will give you not only a ROMable image which will run standalone but also an image which can be debugged 2 9 Inline Functions It is also possible to increase the performance of your code by inlining your functions The inline keyword can be applied to any function as shown below void NoSubroutine void _ inline When the inline keyword is used the function will not be coded as a subroutine but the function code will be inserted at the point where the fun
21. This chapter contains worksheets for the practical examples that are available on the CD There are two sets of examples one for the Keil compiler and one for the GNU compiler This chapter is written for the Keil compiler If you want to use the GNU compiler you should start with Appendix A which details the non ANSI additions to the GCC compiler Appendix A also contains example worksheets for the first six exercises that deal with the specifically with GNU tools After exercise six you can rejoin this chapter and use either the GNU or Keil examples for the remaining examples 5 1 Installation All the necessary software for the practical examples is on the CD that comes with this book If you place the CD in the drive on your PC the following window will appear Philipa LD Samunar 2189 CO Welcome to tha embedded world of Hitex Application notes for the ARM processor Course notes for the ARM Tools Exercises ISP MCB2100 Information User Manuals CMX Operating System Exit Install Keil GNU Compiler Li r Setup Koil ARM uVision Cevelopement Software 1 First it is necessary to install the Keil uVision software this will also install the Keil compiler D If you wish to use the GNU compiler you will need to install this separately once uVision is installed 3 Next install the example set for the compiler you plan to use 4 Finally install the Philips ISP flash programming tool Once the software has been in
22. 0 50usec 50 100 and the numbers of occurrences are displayed in a graph Execution time distribution of random_wait The second example shows how to examine a serial communication protocol and to record the transmission and reception of data including time stamps For the Philips LPC2000 family the transmit and the receive buffer are at the same address 0 000 000 To record all reads and writes to this address we have to enable the data tracing in the ETM settings with data portion the recording of the address portion is not necessary if only data from this address are filtered and we have to define a filter to the address 0xE000C000 with the length of 1 the Bus State RdWr and the Trace Recording DFltInc The result is Hitex UK Ltd Page 209 mmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS Frame Address State Data Instruction 594 0 Ox0000044C 0020C3E5 strb r2 r3 1 109 ms 594 1 OxE000C000 Ww 3 586 0 BRAD 572 0 Ox0000044C 0020C3E5 strb r2 r3 1 109 ms 572 1 OxEO00C000 Ww 31 564 0 BRAD 550 0 Ox0000044C 0020 5 strb r2 r3 1 109 ms 2 Linie 542 0 BRAD 528 0 Ox0000044C 0020 5 strb r2 r3 1 109 ms 528 1 OxE000C000 Ww 35 520 0 BRAD 506 0 0x0000044C 0020 5 strb r2 r3 1 109 ms 506 1 OxE000C000 Ww 3 498 0 BRAD 484 0 0x000004AC 0020C3E5 strb r2 r3 1 109 ms 484 1 OxE000C000
23. 3 6 040 ms 0 0 67 3 174 66 us E Source example c Trace Control Disassembly Startup sor Id State Address Value Action ra T2 Executed example random_wait IFltinc uinti amp 6 1 Executed example 67 OXXXXXXXXX IFltInc v The time stamps in the rows marked with 44 the beginning of the function are the times between function return and function entry and the times in the rows marked with 67 are the durations of the function itself which are of interest here In this part of trace these times vary from about 60usec to 230sec We now can make a better display with the help of another tool like Microsoft Excel We write the trace contents into a file open the context menu of the trace window with a right mouse click and select Log to File We enter a file name and click Start When the logging is finished we click close An import into Excel can be calculated and displayed as normal curve execution time versus number of occurrences Hitex UK Ltd Page 208 hitex 8 Extended Debugging With ETM Trace EVELOPMENT NA JN E AL E HD NI BRL CU 111 AL tt LU NIE LECT Ml Un nts 1 1 51 n LAJ Li 7 amp Or even better as calculated profile analyses where the time of each occurrence of random_wait is counted a time class
24. Each UART has a sixteen byte Usar receive FIFO which can be programmed to Trager ruit generate an UART interrupt at various trigger levels The character timeout be used to read bytes which do not reach a trigger level 18 Bytes The receive interrupt can be set to trigger after it has received 1 4 8 or 14 characters So if the interrupt is set to trigger when eight characters are in the buffer and a total of 34 characters are sent then four interrupts will be generated with two characters left in the FIFO These remaining characters will cause a character time out indication CTI interrupt The CTI interrupt occurs when there are one or more characters in the FIFO and no FIFO activity has occurred for 3 5 4 5 character times Hitex UK Ltd Page 88 hitex mms 4 User Peripherals DEVELOPMENT TOOLS The transmit FIFO will also generate interrupts when the transmit holding register is empty and when the transmit shift register is empty UART Transmit FIFO Like the RX FIFO the TX FIFO is 16 bytes deep and can generate an interrupt when empty and when it has 18 Bytes finished transmitting THEE empty THA tempi TSA ampia UART1 has the same basic structure as UARTO however it has additional support for modem control This consists of additional external pins to support the full modem interface CTS DCD DSR DTR RI RTS there are two additional registers the modem control
25. Eli NM A PRI Saa CAGE Exercise 9 External Bus Interface This exercise shows the necessary changes to the project we set up in Exercise 1 so that it will boot and run from external memory Hitex UK Ltd Page 55 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 9 Phase Locked Loop The Phase Locked Loop is used to take an external oscillator frequency from between 10 MHz 25MHz from a fundamental crystal and multiply this frequency up to a maximum of 60MHz to provide the on chip clocks for the ARM7 CPU and peripherals This allows the LPC2000 to run at its maximum frequency with a low value external oscillator thus minimising the EMC emissions of the LPC2000 The PLL output frequency can also be changed dynamically allowing the device to throttle back its execution speed in order to conserve power when it is idling Within the PLL are two constants which must be programmed in order to determine the clock for the CPU and 10MHz 25 MHz The PLL is used to 10MHz 60 MHz multiply the external crystal frequency up to the maximum 60 MHz It CCLK is controlled by the constants M and P XM P AHB This clock is called Cclk The first constant is a straightforward multiplier of the external crystal The output frequency of the PLL is given by Cclk M x Osc In the feedback path of the PLL is a current controlled oscillator which must operate in the range 156MHz 320 MHz The second constant acts as a programma
26. OxEFFF FFFF Reserved 0xE020 0000 0x01F 0000 0xE000 0000 gt gt Watchdog Timer VPB Peripherals The user peripherals located on the VPB are all mapped into the region between 0 000000 and 0xE020000 and each peripheral is allocated a 16K memory page Finally the Vector Interrupt Unit is located at the top of the address range at OxFFFFFOOO If your user code tries to access memory outside these regions or non existent memory within them an abort exception will be produced by the CPU This mechanism is hardwired into the design of the processor and cannot be changed or switched off Hitex UK Ltd Page 40 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 4 Register Programming Before we start our tour through the system block it is worth noting how Special Function Registers SFR are programmed on ARM7 chips As a general rule all Special Function Registers originating from TY ARM are controlled by three Status 1100 registers a Set Clear and Status register NB To clear bits you must write a Sat 39209 LM SFR logic 1 to the relevant bit in the clear register Each underlying SFR is controlled by three user registers A Set register which is used to set bits a Clear register which is used to clear bits by writing a logic 1 to the bits you wish to clear and a Status register which is used to read the current contents of the register The most common mistake made when new to the LPC2100 is
27. This causes the ETM to record all read or write accesses to the structure Clock In the trace recording below we see a part of the application where Clock MilliSec gets an overflow over 1000 and is reset to 0 and Clock Sec is incremented Hitex UK Ltd Page 206 hitex mmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS The ETM has the advantage that the instructions which are responsible for the data accesses are also recorded in the trace and the corresponding C source lines are displayed Please remember that with the link to source feature the corresponding C sources to the current trace line can be displayed State Data HLL Source Line Exte Time 1 Clock Millisec D3DE ee KE NEN D 13805 1 Clock MilliSec W 03 13798 0 106 if Clock MilliSec gt 1000u 13789 1 Clock MilliSec R 03E3 13777 0 125 13773 0 209 if Clock MilliSec 100u Ou 13768 1 Clock MilliSec 03E3 13754 1 Clock MilliSec 03E3 13728 1 Clock Millisec 13723 1 Clock Millisec 03 8 4 999 ms 0 47 us 0 42 us 13716 0 106 if Clock MilliSec gt 10000 4 997 ms 13707 1 Clock MilliSec 13689 1 Clock MilliSec 13670 1 Clock Sec 00 13665 1 Clock Sec 01 13656 0 110 if Clock Sec gt 60u 13649 1 Clock Sec 13641 0 125 13637 0 209 if Clock MilliSec 100u Ou 13632 1 Clock MilliSec 13618 1 Clock Hour 13595 1 Clock Time 0 03 8 0
28. cause the transmitter to resend the message so the CPU does not need to intervene unless there is a gross error on the bus There are three error detection methods at the packet level form check CRC and acknowledge plus two at the bit level bit check error and bit stuffing error Within the CAN message there are a number of fields that are added to the basic message On reception the message telegram is checked to see if all these fields are present If not the message is rejected and an error frame is generated This ensures that a full correctly formatted message has been received Le Frame Space gs camniri e LII Kit lec RTE PRE ST ener Find ol Frunz ACK Delum ACE Sil Frame Check The frame check tests that F a correctly formatted CAN Data Fiski message has been Length Const received but Tra IDE bsi ihi KTE bit ii Fei Fiat o Frame Each message must be acknowledged by having a dominant bit inserted in the acknowledge field If no acknowledge is received the transmitter will continue to send the message until an acknowledge is received SAS hate Lata Fraise later Frame Spas Li ieftina i av i 0 Chrome pou _ __ Iri ornari te Esal of Acknowledge Rece ae My ACE Debra thi lai ACE All CAN frames must b
29. connected on to it In the case of the FLASH memory it has a 90ns read cycle so at 60MHz with a cycle time of 16 ns we need 6 Cclk read waitstates with one idle cycle The FLASH is accessed word wide so RBLE is set to zero to disable the byte laning During normal operation the FLASH will not be written to so WST2 is set to zero Also the write protect may be set to detect accidental writes to the FLASH bank but during development it Each Chipselect may be configured Bit with a buswidth of 8 16 or 32 bits 0 1 16 Bit 10 32 Bit Reserved may be wise to set it to zero and disable write protect in case it interferes with the FLASH programming algorithm of the ULINK Finally the bus width is set to 32 bits This gives a configuration value for Chipselect zero of 0x20000060 Hitex UK Ltd Page 52 hitex mum 3 System Peripherals DEVELOPMENT TOOLS In the case of the RAM it has a 70ns read and write time Consequently at 60MHz the read and write waitstate WST1 and WST2 should be set to 5 Cclk cycles with IDCY set to one cycle As the RAM is a byte partitioned device the byte lane control must be enabled by setting RBLE to one And again the bus width must be set to 32 bits This gives us a chipselect configuration value of 0x20001440 These values can be configured with the graphical editor in the Keil startup code Stack Configuration Stack Sizes in Bytes PLL Setup v H MAM Setu
30. e 2 532400 ms gm zi Now as you run the code any activity on the match1 pin will be recorder into the logic analyser window Hitex UK Ltd Page 159 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 21 Exercise 18 Dual Edge Symmetrical PWM Generation In this exercise we will use the PWM module to generate a single channel of symmetrically modulated PWM signal This will use the MATO channel to generate to total signal period and will be configured to reset the timer MAT1 will be user to generate the turn on off and MAT2 will generate the turn off point The PWM duty cycle can then be modulated by the keys in serial window 2 Open the project in C work EX20 PWMModule In main c complete the code as follows Enable pin 0 7 as PWM2 PINSELO 0x00008000 Configure PWM channel two to double edge control output enabled PWMPCR 0x0000404 Configure Timer 0 reset to the counter PWMMCR 0x00000003 Set the reload values of mat1 and mat to give an initial spike which is gradually broadened in the main loop as the code runs PWMMRO 0x000000FF PWMMR1 0x00000080 PWMMR2 0x00000080 enable shadow latch for match 0 2 PWMLER 0x00000007 Reset counter and prescaler and enable PWM mode PWMTCR 0x00000002 enable timer with PWM enabled PWMTCR 0x00000009 In the main while loop enable the shadow latch to update the match registers when a new valu
31. 0 208 inc_clock 3 1 92 us 43 0 209 if Clock MilliSec 100u Ou 3 3 59 us 477 0 214 if Clock MilliSec 100u 500 3 5 33 us 109 0 221 SWITCH SYS TO IRQ 3 6 90 us 113 0 223 vICvect ddr 0 3 7 02 us 118 0 224 3 DENE NEN EGENT E RE II EE f 145 0 198 SWITCH IRQ TO SYS 3 149 0 202 interrupt identification TIMERO IR 3 155 0 205 TIMERO_IR 0xFF 3 162 0 208 inc clock 3 177 0 209 if Clock MilliSec 100u 00 3 211 0 214 if Clock MilliSec 100u 500 3 5 004 ms 243 0 221 SWITCH SYS TO IRQ 3 5 005 ms 4247 0 223 VICVectAddr 0 3 5 005 ms 4252 0 224 3 5 006 ms 268 0 197 3 9 999 ms 279 0 198 SWITCH IRQ TO SYS 3 10 000 ms 283 0 202 interrupt identification TIMERO_IR 3 10 000 ms 289 0 205 TIMERO_IR OxFF 3 10 001 ms 296 0 208 inc_clock 3 10 001 ms a 4311 0 209 if Clock MilliSec 100u Ou 3 10 003 ms 345 n 714 iff Clock Millisec9z 100 n SO a 1n 4 me 7 We see here the first line of the ist TIMERO is 197 with the corresponding as C source line After this 9 lines of code are recorded and after a pause the 197 with the following lines are recorded again The time column here is switched to the absolute mode which displays the time distance to the first frame frame 0 0 The isr TIMERO is executed every 5msec as intended The ISR calls an second function called inc clock in the trace listing we can see the call to th
32. 0000 AIN3 0 0000 A new simulation script has been added that allows you to change the A D voltage via buttons in the toolbox Hitex UK Ltd Page 167 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 27 Exercise 24 Digital to Analogue Converter In this exercise we will setup the A D to make a conversion every 50uSec 20 KHz by using a timer match channel to trigger the conversion As soon as the conversion is made the converted value is fed into the Digital to Analogue converter If you have access to a signal generator and a scope you can compare the input and output waveforms or use the simulator and the Logic analyzer Open the A to D project in C work EX20 AtoD Configure the A D so it is triggered by timerO match channel Copy the A D result into the DAC register Build the project and start the debugger If you are using the MCB2100 connect a signal generator to the A D input channel and an oscilloscope to the output Run the code and compare the two waveforms Vary the input frequency and find the frequency at which aliasing occurs If you are using the simulator an input script is provided in the toolbox and the input output signals can be compared in the logic analyser window Hitex UK Ltd Page 168 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 28 Exercise 25 Transmitting CAN Data In the next two exercises we are going to look at transmitting and receiving CAN mes
33. 58 us 2097006 0 125 3 0 45 us 2097002 0 209 if Clock MilliSec 100u 3 0 38 us 2096968 0 214 if Clock MilliSec 100u 500 3 1 62 us 2096936 0 221 SWITCH_SYS_TO_IRQ 3 1 80 us 2096932 0 223 VICVectAddr 0 3 0 11 ps 2096927 0 224 3 0 13 us rl Here the content is different and includes all lines of code which are executed between the first filter and the second filter After the line inc_clock the call to the function inc clock the next recorded line is the first statement of the called function The recording stops with the return of the isr in line 224 Hitex UK Ltd Page 205 mmmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS 8 4 A Data Trace So far we have used the ETM to record lines of code to examine program execution However the ETM also allows us to record data accesses to both RAM and special function registers Having access to the real time data flow within an application can be a major asset for debugging and testing of real projects Like many things the ETM is not a perfect solution The is effectively a four bit wide serial port which is used to shift debug information out to the TANTO this technique does not have enough bandwidth to transfer all of the program information all of the time Consequently we have to be selective with the trace filters to ensure the ETM is not overloaded and debug information is lost To enable the recording of data accesses we fi
34. Code 172 6 4 Accessing Peripherals ss 172 6 5 Interrupt Service Routines 172 6 5 1 Software Interrupt deena id eene eeu ine 173 6 6 Inline Functions 6 7 Exercise 1 Using The Keil Toolset With The GNU Compiler 174 6 8 Exercise 2 Startup Code 179 6 9 Exercise 3 Using THUMB Code 179 Hitex UK Ltd Page 5 Introduction to the LPC2000 6 10 6 11 6 12 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 8 1 8 2 8 3 8 4 8 5 9 1 9 1 1 9 1 2 9 1 2 1 9 1 3 9 2 Exercise 4 Using The GNU Libraries Exercise 5 Simple Interrupt Exercise 6 Software Interrupt ecceeeeeeeeeeseeeeeeeeeeeeeeeaeeseaeeteaeeseneeesaee Chapter 7 Hitex Tutorial With Keil Or GNU Compiler Installation item de el ae ee Creating The First Project Exercise 1 Creating The First Project Using ATOR tup ep RB Exercise 2 Startup Code ss Exercise 3 Using THUMB code ses e Using The Tantino Hardware Setting Up The Tantino JTAG hardware Chapter 8 Extended Debugging With ETM Trace ei ED Using The Tanto With Trace Recording Execution Trace
35. From Page 201 06600000 Y Direction e Up C Down Close x Address inc clock mmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS Insert inc clock in the address field and clock on find The first found occurrence of inc clock is now displayed Close the dialog and switch the trace display into the line mode by opening the context window right mouse button and select lines The C source lines are now displayed along with a timestamp showing the execution time of each line The display of the trace can also be linked to the source window to get a better view of the context of the current trace line We arrange the source and the trace window that both are visible i e with the menu Window tile horizontally activate the trace window and when we move the cursor over the trace lines the corresponding source is displayed and marked with a green triangle By moving through the trace buffer listing we can see how the code executed in the original source files This is a very helpful way of interpreting the trace information it is like single stepping the real time code E race E State Data Frame Address HLL Source Line Extern Time 85 0 197 3 0 11 ps 80 0 198 SWITCH_IRQ_TO_SY5 3 0 49 ps 76 0 202 interrupt_identification TIMERO_IR 3 0 42 us 70 0 205 TIMERO IR xFF 3 0 75 us 63 0 208 inc c
36. Locate tab make sure that the Use memory layout from target dialog box is ticked Hitex UK Ltd Page 123 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS In the debug tab select make sure the use simulator radio button is checked along with the Load application at startup and Go till main Select OK to complete the target options In the project browser expand the target1 root node to show the source group 1 folder Elsa Target 1 8 28 Source Group 1 Highlight the source group 1 folder open the local menu with a right click and select Add files to source group source group1 Hitex UK Ltd Page 124 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS zixl 5 59 Target 1 S Source Group 1 Select Device for Target Target 1 Options for Group Source Group 1 Open File Translate File e Stop build Add Files to Group Source Group 1 Manage Components Remove Group Source Group 1 and it s Files lv Include Dependencies In the Add files to group dialog add the file blinky c and serial c uw em Change the Type of file filter to ASM and add the file startup s These are all the source files necessary for the project so select Close Notes i You can view the source code contained in a file by double clicking on the file name in the project browser window
37. MHz PLLCON 0x00000001 Enable the PLL PLLFEED 0 000000 Update PLL registers with feed sequence PLLFEED 0x00000055 while PLLSTAT amp 0x00000400 test Lock bit PLLCON 0x00000003 Connect the PLL PLLFEED 0x000000AA Update PLL registers PLLFEED 0x00000055 VPBDIV 0x00000002 Set the VLSI peripheral bus to 30 000MHz Exercise 10 Phase Locked Loop In this exercise we configure the PLL to generate a Cclk of 60MHz and a Pclk of 30MHz Hitex UK Ltd Page 58 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 11 Power Control Power consumption on all well designed microcontrollers is a direct relationship with the number of gates and the switching speed The LPC2000 is no exception The simplicity and low gate count of the ARM7 core contributes to its low power consumption Intelligent use of the PLL and VPB divider can contribute to reducing the runtime switching speed In addition the LPC2000 has additional dedicated power control features The ARM7 CPU has two power down modes controlled by the first two bits of the PCON register The CPU may be placed into Idle mode where the CPU is halted but the peripherals are still operational Any interrupt from a peripheral will wake up the CPU and processing will resume Ext ini ec Idle mode stops the clock to the CPU Tener a but the peripherals are still running and interrupt will restart the CPU 1 1 LA
38. Ox400000DE 00 00 00 00 00 00 00 400000 0 00 00 00 OO OO OO OO OO OO OO OO OO OO O0 0x40000102 View the device peripherals Open some of the windows under the Peripherals menu 8S Reset CPU System Control Block Vectored Interrupt Controller VIC 0 00000000H 0 0 Timer 0 4 IRQ 00000000H 0 0 Timer 1 5 IRG 00000000H 0 0 GPIO UARTO 6 IRQ 00000000H 0 0 UART gt UART1 7 IRQ 00000000H 0 0 PWM 8 IRQ 00000000 0 0 SPI Interface SPI 10 IRQ 00000000H 0 0 Timer PLL Lock PLOCK 12 IRQ 00000000H 0 0 Pulse Width Modulator RIC 13 IRQ 00000000H 0 0 al Time Clock External Interrupt 0 EINTO 14 IRQ 00000000H 0 0 Bearman External Interrupt EINT1 15 IRQ 00000000H 0 0 Watchdog External Interrupt 2 EINT2 16 IRQ 00000000H 0 0 r Selected Interrupt I IntSelect Softint F IntEnable Rawlnt r Vectored IRQ Slot 0 Enable VCVectCnio 0400000000 VICVect ddr 0 00000000 Channet 0 7 VICVect ddo D 00000000 VICDe ect ddr 0 00000000 VICProtection 0500000000 VICIntSelect 0 00000000 VICRawlntr 0500000000 VICSoftInt 0500000000 VICIntEnable p o0000000 VICIRGStatus 0500000000 VICSoftIntClear 0 00000000 VICIntEnCIr 0500000000 VICFIGStatus 0500000000 The debugger has mode functions but the above debugging tools will allow you run the course exercises The simulator ca
39. Page 96 hitex mms 4 User Peripherals DEVELOPMENT TOOLS 4 10 Analog To Digital Converter The A D converter present on some LPC2000 variants is a 10 bit successive approximation converter with a conversion time of 2 44 uSec or just shy of 410 KSps The A D converter has either 4 or 8 multiplexed inputs depending on the variant The programming interface for the A D converter is shown below An 0 A Abn 7 A D Analogue to digital converter The converter is available with 4 or 8 channels of ap 10 bit resolution VSS The A D control register establishes the configuration of the converter and controls the start of conversion The first step in configuring the converter is to set up the peripheral clock As with all the other peripherals the A D clock is derived from the PCLK This PCLK must be divided down to equal 4 5MHz This is a maximum value and if PCLK cannot be divided down to equal 4 5MHz then the nearest value below 4 5MHz which can be achieved should be selected Edge Get Ted POH CLEE Bond CLR Di SEL AD Control register The control register determines the conversion mode channel and resolution PCLK is divided by the value stored in the CLKDIV field plus one Hence the equation for the A D clock is as follows CLKDIV PCLK Adclk 1 As well as being able to stop the clock to the A D converter in the peripheral power down register the A D has the ability to fully power down This reduces the overa
40. QUANTA until we get an integer value for BRP In this case when QUANTA 16 BRP 30 Then 16 Quanta 1 Tseg1 Tseg2 Hitex UK Ltd Page 106 hitex mum 4 User Peripherals DEVELOPMENT TOOLS So we can adjust the ratio between Tseg1 and Tseg2 to give us the desired sample point Sample point QUANTA x 70 100 Hence 16 0 7 11 2 This gives Tseg 1 10 Tseg2 5 and the sample point 68 896 The value for the synchronous jump width may be calculated via the following rule of thumb 2 gt 5 Tq then program SJW to 4 Tseg2 5 Tq then program SJW to Tseg2 1 Tq In this case SJW 4 Hitex UK Ltd Page 107 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS 4 12 6 CAN Message Transmission In the LPC2000 each CAN controller has a number of status and control registers plus three transmit buffers and a receive buffer CAN CAM MOD Controls Operating Mode Control CAN CMA Command Register Register CAN GSR Global Status Register CAN ICA Interupt Status CAN IER Interrupt Enable Rx Buffer CAN BTR Bit Timing Register CAN EWL Error Warning Limit Tx1 Buffer CAN SR Status Register Tx2 Buffer Tx3 Buffer In order to configure CAN controller we must program the bit timing register However the bit timing register is a protected register and may only be written to when the CAN controller is in reset Bit zero of the mode register is used to place the CAN controller into reset e BRP The CAN
41. RAM at 0x40000000 with a size of 0x400 Click the add button and select the flash algorithm for the device you are using then click OK to quit Switch from the simulator to the JTAG debugger Again open the options for target dialogue and select the debugger menu On the right hand side of the menu select the ULINK ARM7 Debugger from the dropdown menu and tick the Use radio button UVISION is now ready to use the ULINK JTAG in place of the simulator If you are in the JTAG debugger or simulator you must halt any running code and quit the debugger before you can rebuild the code or quit the project Hitex UK Ltd Page 131 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Important Note for the following exercises All the following exercises have builds to be debugged in either the Keil Simulator or to be downloaded onto the MCB2100 target hardware and debugged via the ULINK JTAG debugger The root folder of the project will be named Simulator for the simulation version or Flash for the version built to be debugged on the hardware Only the debug options in the project are changed To switch between the two versions make the project workspace the active window right click and select manage components Cenponenio and S Lo IC CI ri P angerz JE Does DJE De 6 rc coe u Gami Ep In the project components
42. TOOLS 5 24 Exercise 21 I2C interface This exercise will demonstrate using the 12C interface to write and read back from a serial EEPROM of the type see the CD for the full datasheet Because the MCB2100 evaluation board is not fitted with such a memory a script file is used to simulate the EEPROM so we can test our routines and have them ready as soon as the hardware becomes ready Open the project in C work l2C The script file is in I2C ini and this is added to the project in Options for Target Debug Add the following lines to the C code Build the code and start the simulator Open the peripherals I2C window The I2C Hardware tab shows the configuration of the peripheral and the I2C communication tab will show all the bus transactions In this code the l2Ctransfer function starts the I2C bus transaction which is then handled by the I2C interrupt function The interrupt function is a state machine in the form of a case statement By setting a breakpoint on the initial switch statement we can run the code and observe the activity on the 12C bus USZ 093 void IZCISR void irq a94 3t 7 095 Joss switch 12STAT 097 After running the code the transactions on the 12C bus will look as follows Interface Hardee LC Communscation Mode Actors Direction Dota f n Taser QU CL 0 CH Maries n O Mache CE M The Simu
43. and an enable bit By programming the channel field any interrupt channel may be connected to any given slot and then activated using the enable bit The priority of a vectored interrupt is given by its slot number the lower the slot number the more important the interrupt The other register in the VIC slot is the Vector Address Register As its name suggests this register must be initialised with the address of the appropriate C function to run when the interrupt associated with the slot occurs In practice when a vectored interrupt is generated the interrupt channel is routed to a specific slot and the address of the ISR in the slot s Vector Address Register is loaded into a new register called the Vector Address Register So whenever an interrupt configured as a vectored interrupt is generated the address of it s ISR will be loaded into a fixed memory location called the Vector Address Register When interrupt occurs the vector address slot associated with the interrupt channel will transfer its contents to the vector address Wii ases Hitex UK Ltd Page 65 hitex mm 3 System Peripherals DEVELOPMENT TOOLS While this is happening in the VIC unit the ARM7 CPU is going through its normal entry into the IRQ mode and will vector the 0x00000018 the IRQ interrupt vector In order to enter the appropriate ISR the address in the VIC Vector Address Register must be loaded into the PC The assembly instruc
44. been called and then use a case statement to run the appropriate code Open the project in C work EX6 SWI Add the file SWI to the project In Main c declare the two function as SWI functions as follows void SWI Calll int pattern swi 8 void SWI_Call2 void __swi 9 Compile and download the code into the debugger Step the code and observe the SWI being serviced In the disassembly window we can see the call to the first function This passes the parameter and generates an SWI which is packed with the integer 8 In the register window we can read the CPSR which shows we are in user mode CPSR 040000030 50 SWI_Calli pattern 51 Ox0000019E 4807 LDR RO PC 0x001C Branch to function is replaced by a SWI instruction lt gt 0 1 0 0 0 0 1 0x10 User mode Once we have generated the software interrupt the chip will change modes run the code in vectors s and then enter our number 8 SWI function Er Ox800000b3 30 void SWI Calli int pattern swi 8 N 1 31E T Z 0 m E E533 IOCLR1 OxOOFFO0000 34 IOSET1 pattern 35 F 0 x T 1 M 0x13 amp A XI a Hitex UK Ltd Page 140 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 10 Exercise 7 Memory Accelerator Module This exercise demonstrates the importance of the memory accelerator module Initially the PLL is set to 60MHZ opera
45. bit in each of the four GPIO registers These bits are data direction set and clear and pin status The IODIR pin allows each pin to be individually configured as an input 0 or an output 1 If the pin is an output the IOSET and IOCLR registers allow you to control the state of the pin Writing a 1 to these registers will set or clear the corresponding pin Remember you write a 1 to the IOCLR register to clear a pin not a 0 The state of the GPIO pin can be read at any time by reading the contents of the IOPIN register A simple program to flash the LED on the evaluation board is shown below Hitex UK Ltd Page 72 mmm 4 User Peripherals DEVELOPMENT TOOLS int main void unsigned int delay unsigned int flasher 0x00010000 define locals IODIR1 0 00 0000 set all ports to output while 1 for delay 0 delay lt 0x10000 delay simple delay loop f IOCLR1 flasher clear output pins IOSET1 flasher set the state of the ports flasher flasher lt lt 1 shift the active led if flasher amp 0x01000000 flasher 0x00010000 Increment flasher led and test for overflow Exercise 15 GPIO This simple exercise demonstrates using the GPIO as an LED chaser program Hitex UK Ltd Page 73 hitex mum 4 User Peripherals DEVELOPMENT TOOLS 4 3 General Purpose Timers The LPC2000 have a number of general purpose timers The exact number
46. can be downloaded and run on the MCB2100 evaluation board There are two sets of examples on the CD one for the Keil compiler and one for the GNU The main text concentrates on the Hitex UK Ltd Page 27 hitex mm 2 Software Development DEVELOPMENT TOOLS Keil compiler However Appendix A describes how to use the GNU compiler and also describes the GNU version of the exercises up to exercise 6 After exercise 6 you can use the exercise descriptions in the main text As you read through the rest of the book at the end of each section there will be an exercise described in the tutorial section which illustrates what has been discussed The best way to use this book is to read each section then jump to the tutorial and do the exercise This way by the time you have worked through the book you will have a firm grasp of the its tools and the LPC2000 microcontroller Exercise 1 Configuring A New Project The first exercise covers installing the uVISION Keil tutorial or installing StartEasy and HiTOP Hitex tutorial and setting up a first project 2 3 Startup Code There are multiple ways to write correct startup code Here we describe the Keil variant The Hitex variant is described in the Hitex Tutorial Exercise 2 In our example project we have a number of source files In practice the C files are your source code but the file STARTUP S is an assembler module provided by Keil As its name implies the start up code
47. e o ee NR tee edite Reise dta eed 61 External Interrupt rh RR tte 61 Interrupt Str ct re in a recep t eec tede des 62 EIG interrupt s iiit 63 Leaving An FIQ Interrupt ss 63 Example Program FIQ Interrupt 64 Vectored dee Ree Re ce e ae er tere dens 65 Leaving An IRQ Interrupt s 66 Example Program IRQ interrupt esssseeeeenn 67 Non Vectored Interrupts 67 Leaving A Non Vectored IRQ Interrupt 68 Example Program Non Vectored 68 Nested Interrupts 23 ities Ae pe Ed ig 69 einge 70 Chapter 4 User Peripherals 72 SV E 72 General P rpose I O i d edd e com ees 72 General Purpose Timers nne 74 PWM Modu lator s s sit t ot E e Ptr aree ite ede evite ias 78 Real Time no ne Ince eter Gawain 81 Watchdog irt citet dn ths e i t aet fs 84 VART sein niet nine Gite ie d daten b t cbe dn 86 I2C Interface ome p ene eere a detis 90 SPl Interface rie atn en nied eei needed 95 Analog To Digital Converter 97 Digital To Analog Converter 100 CAN Gohitrollet Antenne 101 1507 Lay r Modelit air mere 101
48. i i i i i i i i i i i n i i i i i i i i i i i i 1 i i i i i i i i i Hitex UK Ltd Page 161 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 22 Exercise 19 Real Time Clock In this exercise we will use all the major features of the real time clock The first step is to configure the reference clock to give 32 768 KHz We can then configure the counter increment registers to give an interrupt every second and the alarm registers to give an interrupt at 10 seconds External oscillator 12 00MHz Cclk 60 000MHz Pclk 30 000MHz Calculate the value of PREINT using PREINT int pclk 32768 1 Answer 0x392 Calculate the value of PREFAC using PREFRAC Pclk PREINT 1 x32768 Answer 0x4380 Open the project in ex16 RTC work In main c enter the values for PREINT and PREFAC Next enable the Seconds increment interrupt CIIR 0x00000001 Set the Seconds alarm register for 3 seconds and enable the seconds alarm in the alarm mask register ALSEC 0x00000003 Program the Clock control register to start the RTC running CCR 0x00000001 In the interrupt routine test the interrupt location register to determine the cause of the RTC interrupt seconds increment or alarm if ILR amp 0x00000001 increment if ILR amp 0x00000002 Alarm In either case make sure the interrupt flag is cleared be
49. individual peripheral if it is not being used via its power control bit in the PCONP register A few peripherals cannot be powered down these are the Watchdog GPIO pin connect block and the system control block Your code can optimise the configuration of the LPC2000 for minimum power consumption for a given application Some unofficial power consumption figures are given below LPC2106 60MHz 30mA Power down 10 15uA LPC2129 60MHz 55mA 60MHz VPBDIV 4 40mA During development it is likely you will be using a JTAG development tool connected to the ARM7 via a dedicated serial link If you place the CPU into Idle or Power Down mode no further debugging will be possible until the CPU is woken up Hitex UK Ltd Page 60 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 12 LPC2000 Interrupt System In the C code section we saw how to deal with ARM7 exceptions for an undefined instruction a memory abort and a SWI instruction In this section we will look at the remaining two exception sources the General Purpose Interrupt IRQ and Fast Interrupt FIQ These two exceptions are used to handle all the interrupt sources external to the ARM7 CPU In the case of the LPC2100 these are the user peripherals In order to examine the LPC interrupt structure we need a simple interrupt source For this we can use the external interrupt pins which are the easiest peripheral to configure and EINT1 is connected to a switch on the development
50. is stored back into memory Mere Ms Ai M ARM7 CPU is a store architecture All data m Me Ae Acid Aa Ae Ro Pu fg processing instructions may only be carried out on a central register file Lj pe ao r The central set of registers are a bank of 16 user registers RO R15 Each of these registers is 32 bits wide and RO R12 are user registers in that they do not have any specific other function The Registers R13 R15 do have special functions in the CPU R13 is used as the stack pointer SP R14 is called the link register LR When a call is made to a function the return address is automatically stored in the link register and is immediately available on return from the function This allows quick entry and return into a leaf function a function that is not going to call further functions If the function is part of a branch i e it is going to call other functions then the link register must be preserved on the stack R13 Finally R15 is the program counter PC Interestingly many instructions can be performed on R13 R15 as if they were standard user registers The central register file has 16 word wide registers plus an additional CPU register called the current program status register RO R12 are user registers R13 R15 have special functions 15 User registers PC RO R6 R8 Ro RIO R10 R13 is used as the stack pointer R14 i
51. m m C8 EU m miuus m xac c m url oc DB DE n nm NE IJ UP HN E M m OM M FF F U Im mw p E Ff Bw I T i8 aD E E I PHBE E 0 p D gg ow Gu i i b ow qu D x w 5 Ec M El E B d Ei i ii CC m ow d x w mw a i a n u A aD op a rj Eu Fm DewieiFabh ee Veer iT T Flange fuse rms am Era fete LPC2000 Flash Utility Once the Target LPC2100 has been programmed the chip will automatically be rebooted and start to run your code Turn the potentiometer fully clockwise Reset the code and the LED s will start to sequence If you turn the potentiometer anticlockwise the mam will be enabled and you can see the LPC2000 turbo kick in In the ISP utility under the buffer option you can view a HEX dump of you program In this view the calculated program signature is also shown If you reconnect the JTAG and start the debugger without downloading the program you can examine the interrupt vector table As we have programmed the flash with the Philips ISP tool the program signature has been added in location 0x00000014 which exists as a NOP in the startup code Hitex UK Ltd Page 142 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 11 Exercise 8 In Application Programming This example demonstrates how to call the bootloader API from within
52. move the contents of R2 directly into the program counter and initiate the requested In Application Programming routine When the IAP routine has finished it will return to your application code using the value stored in the link register which is the next instruction in the function which called our void IAP function You should also note that the In Application functions return in ARM mode not THUMB The IAP functions require the top 32 bytes of on chip RAM so you must either locate the stacks to start below this region so it is unused or if you need all the RAM place the IRQ stack at the top of memory and disable interrupts before you enter the IAP routines Using a pointer you can now copy the top 32 bytes of on chip SRAM into a temporary array and then restore them once you return from the IAP functions This way you will not risk corrupting any stacked data Hitex UK Ltd Page 48 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 7 External Bus Interface The LPC22xx variants have an External Memory Controller EMC When enabled the EMC provides four chipselects from 0x80000000 Each chipselect has a fixed 16Mbyte address range and a programmable wait state generation and can be programmed as an 8 16 or 32 bit wide bus As well as allowing additional memory and peripheral devices to be interfaced to the LPC22xx devices it is possible to boot the chip from external FLASH memory located on chip select zero 3 7 1 Exte
53. r2 r3 Isr 5 3 0 06 us 22 0 0 00000550 0230 0 1 moy r3 r2 3 0 06 us 20 0 0 00000554 033140E1 mov r3 r3 Isl 2 3 0 07 us 18 0 0 00000558 023083E0 add r3 r3 r2 3 0 06 us 16 0 0 0000055 032140E1 mov r2 r3 Isl 2 3 0 06 us 14 0 0x00000560 023083E0 add r3 r3 r2 3 0 07 us 12 0 0 00000564 033140E1 mov r3 r3 Isl 2 3 0 06 us 10 0 0 00000568 013063E0 rsb r3 r3 r1 3 0 06 us 8 0 0x0000056C 0338 0 1 mov r3 r3 Isl 16 3 0 07 us 6 0 0x00000570 2338A0E 1 mov r3 r3 Isr 1 3 E 4 0 0x00000574 000053 r3 0h 3 2 0 0 00000578 02000014 bne 214 3 1 0 211 O7FFFFEB bl convert_clock 3 ER Bus Status Executed instructions Time stamp This instruction view of the trace recording is the disassembled executed code reconstructed from the messages recorded from the ETM of the LPC controller In addition the Tanto PT adds a time stamp to each trace frame In the time stamp column the time difference between the executed instruction and the instruction one line above is displayed With an optional data probe external signals can be recorded which are displayed in the external lines column We now can navigate through the trace with cursor or scroll bar or we can use more navigation features with the context menu by clicking the right mouse button When selecting find this dialog appears Hitex UK Ltd Trace Find Data External Bus State DontCare v 59 Found matching frame at 58
54. register and the appropriate code executed Clearly having several FIQ sources slows entry into the ISR code Once you have selected an FIQ source the interrupt can be enabled in the VIC interrupt enable register As well as configuring the VIC the peripheral generating the interrupt must be configured and its own interrupt registers enabled Once an FIQ interrupt is generated the processor will change to FIQ mode and vector to 0x0000001C the FIQ vector You must place a jump to your ISR routine at this location in order to serve the interrupt 3 12 5 Leaving An FIQ Interrupt As we have seen declaring a C function as an FIQ interrupt will make the compiler use the correct return instructions to resume execution of the background code at the point at which it was interrupted However before you exit the ISR code you must make sure that any interrupt status flags in the peripheral have been cleared If this is not done you will get continuous interrupts until the flag is cleared Again be careful as to clear the flag you will have to write a logic 1 not a logic 0 At the end of an interrupt the interrupt status flag Clear gt Peripheral Interrupt Register must be cleared Failure to do this will result in continuous interrupts Hitex UK Ltd Page 63 hitex mum DEVELOPMENT TOOLS 3 System Peripherals 3 12 5 1 Example Program FIQ Interrupt This function sets up the external interrupt as an FIQ interrupt then sits in a loop
55. register and the modem status register and an additional interrupt source to provide a modem status interrupt 1 Ti A Fi a ick i Diis EXT nic Mod Daia DAE 2 ART register m P SS LL UART1 Modem registers me T UART1 has additional Ba T support for modem ma i interfacing The DTR and 1 L RTS signals may be directly r1 controlled Changes ls E modem status can also 47 generate UART interrupt control r gis on These additional features allow optimal connection to a modem with an interrupt generated each time there is a change in the modem status register Exercise 20 UART In Exercise 4 we saw how to use the STDIO library with the UARTs In this example we look at how the UARTs are initialised to run at a specific baud rate Hitex UK Ltd Page 89 hitex mum 4 User Peripherals DEVELOPMENT TOO 4 8 12C Interface As Philips were the original inventors of the I2C bus standard it is not surprising to find the LPC2000 equipped with a fully featured 12 interface The I2C interface can operate in master or slave mode up to 400K bits per second and in master mode it will automatically arbitrate in a multi master system SDA Typical I2C bus configuration The bus SCL consists of separate clock and data lines with a pull up resistor on each line The two external devices used in the example are LPC 2100 por
56. sensitive and then connect it to the processor pin via the pinselO register Hitex UK Ltd Page 61 hitex mum 3 System Peripherals DEVELOPMENT TOOLS The external interrupt pins are an easy to configure interrupt source when first experimenting with the LPC2000 interrupt structure 3 12 3 Interrupt Structure The ARM7 CPU has two external interrupt lines for the fast interrupt request FIQ and general purpose interrupt IRQ request modes As a generalisation in an ARM7 system there should only be one interrupt source which generates an FIQ interrupt so that the processor can enter this mode and start processing the interrupt as fast as possible This means that all the other interrupt sources must be connected to the IRQ interrupt In a simple system they could be connected through a large OR gate This would mean that when an interrupt was asserted the CPU would have to check each peripheral in order to determine the source of the interrupt This could take many cycles Clearly a more sophisticated approach is required In order to handle the external interrupts efficiently an on chip module called the Vector Interrupt Controller VIC has been added The VIC provides additional hardware support or the on chip peripheral interrupts Without he VIC the interrupt response time would be very slow AHB niRQ Vector Ini enupt Controller The VIC is a component from the ARM prime cell range of modules and as such is a hig
57. serial c in the Keil lib directory By adding this file to your project the default library version is ignored and the code in serial c is used in its place So by rewriting the putchar and getchar routines the high level printf and scanf function can be redirected to any IO device you want to use such as an LCD and keypad Bear in mind that the high level STDIO functions are quite bulky and should only be used if your application is very I O driven Exercise 4 STDIO This exercise demonstrates the low level routines used by printf and scanf and configures them to read and write to the on chip UART 2 6 Accessing Peripherals Once we have built some code and got it running on an LPC2000 device it will at some point be necessary to access the special function registers SFR in the peripherals As all the peripherals are memory mapped they can be accessed as normal memory locations Each SFR location can be accessed by hardwiring a volatile pointer to its memory location as shown below define SFR volatile unsigned long OxFFFFFOOO The Keil compiler comes with a set of include files which define all the SFR s in the different LPC2000 variants Just include the correct file and you can directly access the peripheral SFR s from your C code The names of the include files are LPC21xx h LPC22xx h LPC210x h Hitex UK Ltd Page 32 hitex mm 2 Software Development DEVELOPMENT TOOLS 2 7 Interrupt Service R
58. tab select the project target you want either Simulation or Flash and click the Set as current target button In a real project this feature of uVision allows you to setup several different builds of a project or have several different programs in a project which are part of one larger application Hitex UK Ltd Page 132 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOO 5 5 Exercise 2 Startup Code In this exercise we will configure the compiler startup code to configure the stack for each operating mode of the Arm7 we will also ensure that the interrupts are switched on and that our program is correctly located on the interrupt vector Open the project in C work EX2 startup Open the file Startup s and using the graphical editor configure the operating mode stacks as follows El Stack Configuration Too of Adress 0x4000 4000 Undefined Mode 0x0000 0080 Supervisor Mode 0x0000 0080 Abort Mode 0 0000 0080 Fast Interrupt Mode 0x0000 0080 Interrupt Mode 0x0000 0080 User System 0 0000 0400 PLL Setup v Now Compile the code Start the simulator and when the PC reaches main examine the contents of each R13 register Examine the flags in the CPSR to determine the operating mode and instruction set being used At last entry in the register window is the Internal Mode this gives additional information including timing information if you are in the simulator Project Worksp
59. that execute one instruction while decoding a second and fetching a third The pipeline speeds up the throughput of CPU instructions so effectively that most ARM instructions can be executed in a single cycle The pipeline works most efficiently on linear code As soon as a branch is encountered the pipeline is flushed and must be refilled before full execution speed can be resumed As we shall see the ARM instruction set has some interesting features which help smooth out small jumps in your code in order to get the best flow of code through the pipeline As the pipeline is part of the CPU the programmer does not have any exposure to it However it is important to remember that the PC is running eight bytes ahead of the current instruction being executed so care must be taken when calculating offsets used in PC relative addressing For example the instruction 0x4000 LDR PC PC 4 will load the contents of the address PC 4 into the PC As the PC is running eight bytes ahead then the contents of address 0x400C will be loaded into the PC and not 0x4004 as you might expect on first inspection Hitex UK Ltd Page 9 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 3 Registers The ARM7 is a load and store architecture so in order to perform any data processing instructions the data has first to be moved from the memory store into a central set of registers the data processing instruction has to be executed and then the data
60. the ISO C standard which are necessary for embedded programming In this book a commercial compiler is used in the main text however the GCC tools have also been ported to ARM Appendix A details the ARM specific features of the GCC tools Having read the first two chapters you should understand the processor and its development tools Chapter Three then introduces the LPC2000 system peripherals This chapter describes the system architecture of the LPC2000 family and how to set the chip up for its best performance In Chapter Four we look at the on chip user peripherals and how to configure them for our application code Throughout these chapters various exercises are listed Each of these exercises are described in detail in Chapter Five the Tutorial section The Tutorial contains a worksheet for each exercise which steps you through an important aspect of the LPC2000 All of the exercises can be done with the evaluation compiler and simulator which come on the CD provided with this book A low cost starter kit is also available which allows you to download the example code on to some real hardware and prove that it does in fact work It is hoped that by reading the book and doing the exercises you will quickly become familiar with the LPC2000 Hitex UK Ltd Page 7 Introduction to the LPC2000 Introduction Hitex UK Ltd Page 8 Introduction to the LPC2000 Introduction 1 Chapter 1 The ARM7 CPU Core 1 1 Outline The CPU at
61. the exception source required FIQ IRQ SWI UNDEF This function declaration is only required on the function prototype and should not be used on the main body of the function An interrupt service routine is shown in example 5 Hitex UK Ltd Page 172 mmm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 5 1 Software Interrupt There is no real software interrupt support in the GCC compiler To generate a software interrupt you must use inline Assembler as shown below define Softwarelnterrupt2 asm swi 02 This will place a SWI instruction encoded with the value 2 in your code Next it is possible to declare a pointer to a CPU register using the non ANSI register keyword as shown below register unsigned link ptr asm r14 This allows us to read the contents of the link register when we enter the ISR When the SWI instruction is executed the CPU will enter supervisor mode and jump to the SWI vector The address of the SWI instruction plus four will be stored in the link register On entry to the software interrupt ISR the following line of code is executed temp link ptr 1 amp OxOOFFFFFF The address stored in the link register is rolled back by one instruction word wide pointer i e four bytes so that it is pointing at the address of the SWI instruction which generated the exception The top eight bits of the SWI instruction are masked off and bits 0 23 are copied into the temp variable
62. the feed register This needs a feed sequence similar to the PLL To feed the watchdog you must write OxAA followed by 0x55 If this sequence is not followed a watchdog feed error occurs and a Hitex UK Ltd Page 84 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS watchdog timeout event is generated with its resulting interrupt reset It is also important to note that although the watchdog may be enabled via the watchdog mode register it does not start running until the first correct watchdog feed sequence is encountered Once fully started the watchdog must receive regular feed sequences in order to stop the watchdog counter reaching zero and timing out The final Watchdog register is the Watchdog Timer Value Register which allows you to read the current value of the watchdog timer Hitex UK Ltd Page 85 hitex am 4 User Peripherals DEVELOPMENT TOOLS 4 7 UART The LPC2xxx devices currently have two on chip UARTS They are both identical to use except UART1 has additional modem support Both peripherals conform to the 550 industry standard specification Both have a built in Baud rate generator and 16 byte transmit and receive FIFOs wa 1 Tan d i T ERES ox iC T E pru Lo Rx Di mum sai E LE Initialisation of the UARTO is shown below void init serial void Initialize Serial Interface xy PINSELO 0x00050000 Enable RxD1 and
63. the heart of the LPC2000 family is an ARM7 You do not need to be an expert in ARM7 programming to use the LPC2000 as many of the complexities are taken care of by the C compiler You do need to have a basic understanding of how the CPU is working and its unique features in order to produce a reliable design In this chapter we will look at the key features of the ARM7 core along with its programmers model and we will also discuss the instruction set used to program it This is intended to give you a good feel for the CPU used in the LPC2000 family For a more detailed discussion of the ARM processors please refer to the books listed in the bibliography The key philosophy behind the ARM design is simplicity The ARM7 is a RISC computer with a small instruction set and consequently a small gate count This makes it ideal for embedded systems It has high performance low power consumption and it takes a small amount of the available silicon die area 1 2 The Pipeline At the heart of the ARM7 CPU is the instruction pipeline The pipeline is used to process instructions taken from the program store On the ARM 7 a three stage pipeline is used The 7 three stage pipeline has independent fetch decode and execute stages A three stage pipeline is the simplest form of pipeline and does not suffer from the kind of hazards such as read before write seen in pipelines with more stages The pipeline has hardware independent stages
64. the project so select close You can view the source code contained in a file by double clicking on the file name in the project browser window Once you have added all the source files the project can be built via the program menu or by the build button on the toolbar Start debugger Make project Um DR Gt Den y eee ee Eee rug m da ue QUE cere oe4 Once the code is built you can start the simulator by pressing the debugger button The use of the simulator and JTAG debugger are detailed in Exercise One in the Tutorial and are the same for the GNU compiler Hitex UK Ltd Page 178 hitex mm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 8 Exercise 2 Startup Code In this exercise we will configure the compiler startup code to configure the stack for each operating mode of the ARM7 We will also ensure that the interrupts are switched on and that our program is correctly located on the interrupt vector Open the project in EX2 Startup work Open the file Startup s and using the graphical editor configure the operating mode stacks as follows El Stack Configuration Top of Stack Address 0 4000 4000 EE stack Sizes in Bytes Undefined Mode 0 0000 0080 Supervisor Mode 0 0000 0080 Abort Mode 0 0000 0080 Fast Interrupt Mode 0x0000 0080 Interrupt Mode 0x0000 0080 User System Mode 0 0000 0400 PLL Setup v Compile the code Start the simulator and w
65. the pulse is shown below signal void Toggle void PORTO PORTO 0x4000 twatch 200 PORTO PORTO 0x4000 KILL BUTTON DEFINE BUTTON GenerateEINT1 Toggle This script is stored in the file signal ini and is added to the project in the debug window For more details on the scripting language see the uVision documentation Hitex UK Ltd Page 184 mmm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 12 Exercise 6 Software Interrupt In this exercise we will define an inline Assembler function to call a software interrupt and place the value 0x02 in the calling instruction In the software interrupt SWI we will decode the instruction to see which SWI function has been called and then use a case statement to run the appropriate code Open the project in EX6 SWl work In main c add the following code As the first instruction in main add the assembler define which calls the swi instruction define SoftwareInterrupt2 asm swi 02 In the SWI ISR complete the register definition to access R14 register unsigned link ptr asm r14 Complete the code to pass value of the SWI ordinal into the temp variable temp link ptr 1 amp OxOOFFFFFF Compile and download the code into the debugger Step the code and observe the SWI being serviced In the disassembly window the first SWI instruction has been encoded with the value 1 at location 0x0000015C 42 SoftwareInte
66. to write zero into the Clear register which has no effect 3 5 Memory Accelerator Module The Memory Accelerator Module MAM is the key to the high instruction execution rate of the LPC2100 family The is present on the local bus and sits between the FLASH memory and the ARM7 CPU i T Running from on chip FLASH is a performance T bottleneck for all ARM implementations Philips MAII have added a Memory Accelerator Module which greatly enhances the performance of the ARM7 CPU FLASH One of the main constraints in designing a high performance single chip microcontroller based on the ARM7 is the access time to the on chip FLASH memory The ARM CPU is capable of running up to 80MHz however the on chip FLASH has an access time of 50ns Consequently just running out of the FLASH would limit the execution speed to 20MHz a quarter of the possible clock rate of the processor There are a number of ways round this problem The simplest is to load the critical sections of your program into RAM and run out of RAM As the RAM has a much faster access time our overall performance will be greatly increased The down side is that on chip RAM is a finite and precious resource Using it to hold program instructions greatly limits the size of application code which we could run Another approach would be to have an on chip cache A cache is a small region of memory placed between the processor and memory store which stores regions
67. use ARM or THUMB Assembler instructions within a C file This can be done as shown below asm mov r15 r2 This can be useful if you need to use features which are not supported by the C language for example the MRS and MSR instructions Hitex UK Ltd Page 36 hitex mum 2 Software Development DEVELOPMENT TOOLS 2 13 Hardware Debugging Tools Philips have designed the LPC2000 to have the maximum on chip debug support There are several levels of support The simplest is a JTAG debug port This port allows you to connect to the LPC2000 from the PC for a debug session The JTAG interface allows you to have basic run control of the chip That is you can single step lines of code run halt and set breakpoints and also view variables and memory locations once the code is halted VCC 3 3 VCC 3 3 J Debug support on the LPC2000 includes a JTAG port for Flash programming and basic run control debugging In addition Philips has included the ARM embedded trace module The embedded trace module provides much more powerful debugging options and real time trace code coverage triggering and performance analysis toolsets In addition to more advanced debug tools the ETM allows extensive code verification and software testing which is just not possible with a simple JTAG interface If you are designing for safety critical applications this is a very important consideration In addition to the JTAG port Philips have incl
68. while loop Set a breakpoint in the EXTintFIQ function Press F5 to set the program running On the MCB2100 board press the INT button to generate the interrupt If you want to see the entry and exit mechanisms to the exception it is best to use the simulator and single step in the disassembly window This way you can watch the program flow and the actions on the CPU registers Hitex UK Ltd Page 183 hitex mm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS To control the interrupt in the simulator open the peripherals GPIO port 0 window Pin 0 14 is set high by the map ini startup script If you set the program running unchecking the Pin1 4 box will generate the interrupt You must raise the pin high again to stop interrupts General Purpose Input Output 0 GPIO 0 GPIOU IODIRO 000000000 IOSETO fOx00000000 100180 000000000 31 Bits ___ 24 23 Bis __16 15 Bits Bits 0 IOPINO 000004000 FT FTTTTTTT CRIE FT Pins 0 00004000 PPT FT TTTTTTTT FPTTTTTT FTTTTTTT Alternatively in the toolbox there is a Generate EINT1 button This button will generate a simulated pulse on to the interrupt pin Toolbox x Toolbox button Toolbox with user Update windows configurable scripts Generate EINT 1 Within uVision there is a full scripting language which allows you to simulate external events These scripts are based on the C language and are stored in text files The script used to simulate
69. www keil co uk http www ucos ii com http www ristancase com http gcc GNU org onlinedocs gcc 9 2 Evaluation Boards And Modules http www phytec co uk http www embeddedartists com Hitex UK Ltd Page 212
70. your application programs The code makes a Call into the bootloader functions to run the Read Part ID function This example has only been built to work with the MCB2100 evaluation board Open the project in C work EX8 IAP Add the following lines of code to main c command 0 0x36 command result OX7FFFFFFO Add the following lines to API c pragma asm mov r15 r2 move entry address into PC pragma endasm Now make sure that main is compiled as ARM code and API is built as Thumb code Build the code and start the debugger Run the code up to the first call to the IAP function Set a breakpoint on the line of code after this function Step into the IAP function Look at the contents of RO R2 These registers should contain the addresses of the command table the results table and the entry address of the bootloader functions Also R14 should contain the return address to the main function Step the line of assembly code which will jump you to Ox7FFFFFFF This is the entry to the bootloader code Now run the code at full speed it will execute the bootloader function called and return to the address held in R14 the next line in main c When the code hits the breakpoint examine the CPSR to see which instruction set is now being used Take a look at the result table and read the PartID number returned by the bootloader Compare this to the value returned in the previous example Run the next call to the Bootloader
71. 000 7z m Co CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO Hitex UK Ltd Page 207 hitex mum 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS 8 5 Trace Examples Here two examples for a useful trace handling are shown The first is how to measure the execution times of a function and the second is how to record a communication protocol with the UART Often the execution time of a function especially interrupt functions is very important to know With the trace filtering it is very easy to construct a timing profile of any function This example now evaluates the execution time of the function random wait which is included in the standard clock projects of the HiTOP installation This function is called with a random variable num as parameter and contains a loop which is executed num times The time measurement of this functions is done be defining two trace filter events one at the beginning of the function 44 and one at the return address of the calling function 67 The recorded trace looks like this 10 x y Sta Data HLL Source Line External Time 15 44 a 6 040 ms 14 67 3 230 60 us 13 44 3 6 043 ms 12 67 3 230 59 us 10 44 3 6 040 ms 96 0 67 3 118 66 ps 84 0 44 3 6 040 ms 72 0 67 3 230 59 us 60 0 44 3 6 040 ms 48 0 67 3 62 66 us 36 0 44 3 6 040 ms 24 0 67 3 174 66 us 12 0 44
72. 00000200 enable interrupt PINSELO 0x50 Switch GPIO to I2C pins I2SCLH 0x08 Set bit rate to 57 6KHz I2SCLL 0 08 The 12 peripheral must be programmed to respond to each event which occurs the bus This makes it very interrupt driven peripheral Consequently the first thing we must do is to configure the VIC to respond to an I2C interrupt Next the pinselect block is configured to connect the 12C data and clock lines to the external pins Hitex UK Ltd Page 90 hitex mum 4 User Peripherals DEVELOPMENT TOOLS Lastly we must set the bit rate by programming I2SCLH and I2SCLL In both of these registers only the first 16 bits are used to hold the timing values The formula for the 12C bit rate is given as Bit Rate Pclk I2SCLH I2CSLL In the above example the PLL is not enabled and the external crystal is 14 7456MHz Hence the I2C bit rate is Bit Rate 14 7456 B 8 8 937500 Once configured the LPC2100 can initiate communication with other bus devices to read and write data as a bus master or receive and reply to requests from a bus master The contents of the 12 control register are shown below Remember this register is controlled by the CONSET and CONCLR registers a a TTTTTT1 12C control registers Er The control registers are used to Fea w enable the I2C peripheral and I2CONSET interrupt as well as controlling the Mehe Stat Sing benny acdbnosie ge 12C bus start stop and ack
73. 00020 0 00000024 000000028 0x0000002 0 00000030 0 00000034 000000038 0x0000003 0 00000040 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ ANDEQ RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Open the peripherals system control block memory mapping control Memory Mapping Control Memory Mapping Control MEMMAP 0x01 MAP User Flash Mode Switch from User Flash Mode to Ext Flash Mode This will map the first 64 bytes of chipselect Zero into address 0x00000000 upwards This is our vector table that is located in the external flash 0x00000000 0 00000004 0x 00000008 0x0000000 0x00000010 0 00000014 0 00000018 0 0000001 000000020 0 00000024 0 00000028 0x0000002 0 00000030 0 00000034 000000038 0 0000003 ESSFFO18 ESSFFO18 E59FF018 ESSFFO16 ESSFFO18 1 00000 ES1FFFFO ESSFFO18 60000040 80000324 80000320 6000031C 80000318 00000000 80000314 80000310 PC 0 0018 PC PC 020018 PC PC 40x0018 PC 0 0018 PC PC 0x0018 PC PC OxOFFO PC 0 0018 0x80000040 0x8000
74. 014 an0000118 STA RO R3 Examine program variables In the C code window place the cursor on the counter variable Open the local window and select Add counter to watch window in the sub menu select 1 Go To Line for 3 M Insert Remove Breakpoint E Enable Disable Breakpoint EUUBEEE Clear complete Code Coverage Info for i Add counter to Watch Window count J fiboCount Fibonacci counter In the Watch and call stack window select the Watch 1 tab to view the contents of counter counter E lt tupe F2 to edit Examine memory locations Open the memory window with view memory window Hitex UK Ltd Page 128 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Set the start of the memory window to 0x40000060 the address of the counter variable 0 40000060 06 00 00 00 00 00 00 0 40000072 00 00 00 00 00 0 40000084 00 00 00 00 00 00 00 00 00 00 x40000096 00 00 00 00 00 0x400000A8 00 00 00 00 OO 00 OO 00 00 00 00 Ox400000BA 00 00 OO 00 OO 00 OO OO 00 0x400000C C 00 00 00 00 00 00 00 00 00
75. 0324 0x80000320 0x8000031C 0x80000318 0 00000000 0 80000314 0 80000310 If you single step off the reset vector you will jump to 0 80000040 and start running code from the external Flash device Hitex UK Ltd Page 146 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS The ULINK JTAG can also be used to program external flash devices This can be achieved as follows Open the options for target utilities window and add the file flash ini as shown below Bar largas phone PC FFE Deere Tanger Ling im La elc LA Locate Dag Lite Lanig Nigh Men Correct Pe ije Target orem ber Flash Pho amni Ce Fi Target batos mms dera Toc ls amm This is a script file that is used by the ULINK JTAG to configure the necessary chipselects to allow code to be programmed into the external flash and as such should reflect the values used in the startup code Next select the settings button and you can add the flash algorithm to match the external device used Flag Eorerrdad Setup Penna urgin PLU dra 3 m mejet F Ves axaoons Soe 0 Dersi Eie 7 fis rai uns Prog areas l gantes De Devis T were Adde AA 295008 T Flash 224 SOR FFEFFH With this configuration using the debugger with the JTAG and external flash becomes seamless Hitex UK Ltd Page 147
76. 15 1 6 1 17 1 6 2 Data Processing Instructions 18 1 6 2 1 Copying Registers eene ie eere nte cese id 19 1 6 2 2 Copying Multiple Registers sesseeeeenenenmnn 19 1 7 Swap Instructions cocotte t d o n incites 20 1 8 Modifying The Status Registers 20 1 9 Software Interr pt cutie et ce dee eee Eee ntes 20 1 10 MAG Unite ito e Dueb rte 22 1 11 THUMB Instruction Set 23 1 12 nri 25 2 Chapter 2 Software Development 26 2 1 Outlines itu ee e SS 26 2 2 Which Compile i uses genres etate n ie tide tg t 26 2 2 1 Vision EE eee D DECR be 27 2 2 2 UTOR IDE 2 ete t rob een tet eui 27 2 2 3 Tutorial se edi 27 2 3 Startup Code ion 28 2 4 Interworking ARM THUMB Code 30 2 5 STDIO Libraries ED 32 2 6 32 2 7 Interrupt Service Routines ss 33 2 7 1 Software Int rrupt ede ER et prie 34 2 8 Locating Code In RAM cet eme tet oe edes 34 2 9 Inline Functloris a o Imo 35 2 10 Operating System Support VU 36 2 11 Fixing Objects At Absolute Locations 36 2 12 Inline Assemblet cet teens 36 2 13 Hardware
77. 20012002 Setup the standard filter table StandardFilter 1 0x20032004 Allow Ids 1 2 3 amp 4 SFF_sa 0x00000000 Set start address of Standard table SFF_GRP_sa 0x00000008 Set start address of Standard group table EFF_sa 0x00000008 Set start address of Extended table EFF_GRP_sa 0x00000008 Set start address of Extended group table ENDofTable 0x00000008 Set end of table address AFMR 0x00000000 Enable Acceptance filters C1MOD 0x00000000 Release CAN controller Exercise 26 CAN Receive Like the last exercise this example configures the CAN peripheral for 125Kbits sec and sets the acceptance filters to receive one of three message frames 4 13 Summary This chapter is a bit of a moving target The LPC2000 is a rapidly growing family with new variants being released on a regular basis Check the CD that came with this book for a PDF update to this chapter or keep an eye on the web at http www hitex co uk arm lpcbook If you have worked through this and the proceeding chapters you should now have a firm grasp of the LPC2000 family the ARM7 CPU and the necessary development tools Appendix B lists further reading and web resources for the ARM7 and the LPC2000 in particular Hitex UK Ltd Page 116 hitex mum 4 User Peripherals DEVELOPMENT TOOLS Hitex UK Ltd Page 117 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 Chapter 5 Keil Tutorial
78. 7 Open thumb c Rebuild target Build target F7 Translate C WorkK ARM Philips Course Image GCC ARM Exercises EX3 Thumb Code Solution thumb c Stop bul 1 d Manage Components Remove File thumb c Include Dependencies Select the CC tab and in the misc controls add mthumb or tick the compile thumb code box and click OK pee C eerie eee Lam a Ppi T Again in the file browser select the root target FLASH and in the local menu options for target Hitex UK Ltd Page 180 hitex mum 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS In the CC tab tick the enable APCS option and the support calls between THUMB and ARM cme Tege Carp Loing CC dmim Linnie Dent ie Gemser FF Eras PCI jid Poche Cll arabe Oommen a V rma Canh o eram Lanes ah priame ME HOMI beber pd Fast Compile and download the code into the debugger Open the disassembly window and single step through the code using the F11 key Observe the switch from 32 bit to 16 bit code and the THUMB flag in the CPSR 060000010 N 0 1 36 thumb_function 37 1 y 0 0 00000198 EB000000 Ox000001A0 0 0 0000019 EAFFFFFC 0 00000194 0 Ox000001A0 ESSFCOO0 LDR R12 PC T 0 epox000001A4 E12FFF1C R12 M 0x10 The processor is running in ARM 32 bit mode the T bit
79. API and check that the correct bootloader version is returned Hitex UK Ltd Page 143 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 12 Exercise 9 External Bus Interface This exercise demonstrates how to build a project to use the external bus It is necessary to link the code so it is located in an external flash device configure any chipselect that is used Because the MCB2100 evaluation board uses a true single chip device this example uses the simulator to demonstrate the external bus interface The project is built to place code in flash at 0 80000000 which is the boot chipselect and RAM at 0x81000000 which is chipselect one On real hardware the boot method is determined by the state of the two external boot pins in the simulator we use a script file to set the correct condition However we will also look at configuring the JTAG to program external flash memory so this example can be used on real hardware Open the project in C work ebi In the Options for target menu select the device tab and select the LPC2294 Next select the Target tab and fill in two regions of external memory and uncheck the Use on chip ROM as shown below Options for lapri phere LACHY re lange Clos Lung E Aum cl LE Loca Daig Lit Piin LPC sta noi D Eg nian Les VOOR 9 Un RON amra Hansa pim Le
80. Debugging Tools 37 2 43 14 Important ec eet PER eive ein lak ce ede 38 2 13 1 2 Even More Important 38 2 14 iiS 38 3 Chapter 3 System Peripherals 39 3 1 Outline esie eir RERBA 39 3 2 Bus Structures eec eee gemere ebrei eL ea e ga 39 3 3 Memory Map ein ED RERO MERE 40 3 4 Register Programming 41 3 5 Memory Accelerator Module 41 3 5 1 Example MAM Configuration 44 Hitex UK Ltd Page 3 Introduction to the LPC2000 3 6 3 6 1 3 6 2 3 6 3 3 6 4 3 7 3 7 1 3 7 2 3 8 3 9 3 10 3 10 1 1 3 11 3 12 3 12 1 3 12 2 3 12 3 3 12 4 3 12 5 3 12 5 1 3 12 6 3 12 7 3 12 7 1 3 12 8 3 12 9 3 12 9 1 3 12 10 3 13 4 1 4 2 4 3 44 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 12 1 1 4 12 2 4 12 3 4 12 4 4 12 5 4 12 6 4 12 7 FLASH Memory Programming 45 Memory Map Gonttol reduce teen a 45 Bootloader 1 ce detta etit errare us ee rts 46 Philips ISP Utility oiii roter e annees 46 In Application Programming 48 External Bus Interface ota ede teu 49 External Memory Interface 49 Using The External Bus Interface 52 Booting From ROM e a pep Ene teas 54 Phase Locked ennemies 56 VLSI Peripheral Bus Divider 58 Example Code PLL And VPB 58 Power GOolltol 2 iei em ei et enon eR 59 LPC2000 Interrupt System ss 61 Pirni GonnecEBlock u 3
81. Easy in this case the instruction set simulator 4 When the download dialog appears please press OK Hitex UK Ltd Page 191 hitex mm 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS Workspace Window Toolbars Source Window NT AR kaa hip Per shee ai xj ot em enmt Deus 774 memes en JPR Oe 1 FPA zji ELLI ED EI pussy et eaaa E CREER LER FC EME Addr tea bo FAR Add LIF BC DARE Add Sum Resrsrrsed Vector bc 2 4 3 LER BC POO Adds Ropet Aliri WMardisr o Ondes Addr LE Unies EandlmsrA mal addi p miz masdlagl amp L WAbt Addti FAbt WandimriA rane adiri ne D kt Bandlmrlk More EI a ll ria nidi ix FIG m 1 A ron ui De ssrt Bani ler L fr E gr jin mH o ura sro cs s a 8 xxm i From becs and BoltRsget FS RE Jill E aj Register Window HLL Stack Watch Window The code is now loaded and the PC is at the reset vector at address 0 To walk through the application use the menu Debug or the function keys F9 to step an instruction F10 to step over a line F11 to step into a function F11 to step out of a function to
82. Exception Handling In this exercise we configure a C routine to be a simple interrupt and see it working in the debugger Later on we will see how the LPC2000 hardware is configured to service interrupts Hitex UK Ltd Page 33 hitex mm 2 Software Development DEVELOPMENT TOOLS 2 7 1 Software Interrupt The Software Interrupt exception is a special case As we have seen it is possible to encode an integer into the unused portion of the SWI opcode define SWIcall2 asm swi 2 However in the Keil CA ARM compiler there is a more elegant method of handling software interrupts A function can be defined as a software interrupt by using the following non ANSI keyword adjacent to the function prototype int Syscall2 int pattern __swi 2 In addition the assembler file SWI VEC S must be included as part of the project Now when a call is made to the function an SWI instruction is used causing the processor to enter the supervisor privileged mode and execute the code in the SWI VEC S file This code determines which function has been called and handles the necessary parameter passing This mechanism makes it very easy to take advantage of the exception structure of the ARM7 processor and to partition code which is non critical code running in user mode or privileged code such as a BIOS or operating system In the tutorial section we will take a closer look at how this works Exercise 6 Software Interrupt The SWI support i
83. GB address space with regions for on chip Static Ram flash static ram and peripherals Dx 4000 0000 Flash DxDOOD1 FFFF Miarnony 0 Since the reset and exception vector table are located from zero the on chip flash memory is located from zero for up to 256K The on chip SRAM starts at 0x40000000 for up to 64K and the on chip peripherals are mapped from 0xE0000000 to the top of memory Before we begin to look at the compiler in detail will run through a step by step tutorial on how to set up a UVISION project compile the code and run the debugger This does not cover all the features of uVision but once you have a basic understanding of the IDE feel free to explore If you copy the example from the CD onto you hard disk the source files referred to below can be found in C examples ex1 first project Ok lets build our first project Hitex UK Ltd Page 119 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 2 Exercise 1 Using the Keil Toolset This example is based on the source code that can be found in C Work EX1 first program In this first exercise we will spend some time defining a first project building the code and downloading it into the simulator for debugging We will then cover the basic debugging functions of the Keil simulator Double click on the Keil UVision3 icon to start the IDE I PE CNT a tomo msc oe LOS MED Er 24 RE STE
84. IDE feel free to explore Hitex UK Ltd Page 188 hitex mm 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 3 Exercise 1 Creating The First Project In this first exercise we will spend some time defining an initial project with StartEasy then opening the project in HiTOP which can be used to invoke the compiler to build the code and then download it into the simulator for debugging We will then cover the basic debugging functions of the simulator 1 Double click on the StartEasy icon to start the StartEasy i StarlEasy_for_ARM xj Fin Ed infa Project Select Target MEU a Project Settings Veridoi ene E Sato B Pr Tye LEM pat hier Casio reuera 2 First of all the general project settings have to done Please click the yellow folder picture of Project Settings to expand this folder 3 Please click on project settings and insert the settings and description of this project The entries Path and Project name are mandatory To browse your disks please use the The project is also used for the file names of some project elements 4 Next click on Tool Path to select the desired compiler either Keil or GNU and the correct tool path i e the path for the executables For the Keil compiler it ends normally with keil arm bin for GNU with bin The HiTOP path is the location of the HiTOP exe normally in the HiTOP ARM fold
85. LPC2000 CAN peripherals The Controller Area Network CAN Protocol was developed by Robert Bosch for Automotive Networking in 1982 Over the last 22 Years CAN has become a standard for Automotive Networking and has had a wide uptake in non automotive systems where it is required to network together a few embedded nodes CAN has many attractive features for the embedded developer It is a low cost easy to implement peer to peer network with powerful error checking and a high transmission rate of up to 1 Mbit sec Each CAN packet is quite short and may hold a maximum of eight bytes of data This makes CAN suitable for small embedded networks which have to reliably transfer small amounts of critical data between nodes 4 12 1 1 ISO 7 Layer Model In the ISO seven layer model the CAN protocol covers the layer two data link layer i e forming the message packet error containment acknowledgement and arbitration Object layer Application Layer Prioritizer Message Handling Acceptance filtering Presentation Layer Transfer Laver Session Laver Fault confinement Error detection Acknowledgement Message framing Arbitration Transport Layer Network Layer Physical layer Data Link Layer Jit representation A Transfer rate Physical Layer Signal level and timing a Transmission medium CAN does not rigidly define the layer 1 Physical layer so CAN messages may be run over many different physical mediums However the most co
86. MENT TOOLS The second hardware addition to the PWM modulator over the basic timers is in the output to the device pins In place of the match channels directly controlling the match output pin are a series of SR flip flops Mar 1 n ch Paw PAM BEL Additional circuitry on the match output channels allows the generation of six channels of single edge ML amp PARED A PWM modulation or three channels of dual edge PWM modulation A 4 FANM ENA S PAM SEL AX D e PAM Mars Y 4 a inh 1 4 PAM ENAJ Pwd Cota Resim This arrangement of SR flip flop and multiplexers allows the PWM modulator to produce either single edge or dual edge controlled PWM channels The multiplexer is controlled by the PWMSEL register and can configure the output stage in one of two configurations The first arrangement is for single edge modulation gt Fier SiTi Gouin FWM 1 The multiplexer can be programmed to Singe Edge PM use Match 0 to set the external pin at the E beginning of a cycle the remaining E match channels are used to modulate dl each PWM channel PAM 2 Here the multiplexer is connecting Match 0 to the 5 input of each flip flop and each of the remaining channels are connected to the R input With this scheme Match 0 is set up to count to total cycle period At the end of the cycle it
87. Match 3 MRO Interrupt Interrupt MR2 Interrupt Interrupt Capture Channels CCR 0 00000000 CRO 0500000000 CRI p 00000000 CR2 000000000 0900000000 Rising Edge 0 Rising Edge 1 Rising Edge 2 Rising Edge 3 Falling Edge 0 Falling Edge 1 Falling Edge 2 Falling Edge 3 Interrupt on Event 0 Interrupt on Event 1 Interrupt on Event 2 Interrupt on Event 3 C amp PD U 5 1 02 G4P0 3 CRO Interrupt Interrupt CR2 Interrupt Interrupt MRO 000000010 MR1 000000008 000000000 000000000 hitex mm DEVELOPMENT TOOLS Match on 0x08 The simulator also includes a logic analyser window that can display a graphical trace of activity on a pin over time The logic analyser is used as follows Open the logic analyser window with view logic analyser In the top left hand corner press the setup button Add an new signal called PORTO set the mask to 0x00000020 and set the display type to bit Hitex UK Ltd Clear the match1 pin i a bim ia SLM e Mari CONTENT Sha Right t Add new signal Page 158 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Min Time Max Time Range Grid Zoom Code Setup Export 0 000533 ms 2532347 ms 2 000000 us 0 100000 us m ou Show 0 1 o A 5 o o
88. ModuleView 10 Clicking with the right mouse button on a symbol opens a context window to show the source or set breakpoints for functions and labels or to quick watch the values for variables These symbols may also be dragged and dropped into other debug windows such as the variable watch window or the breakpoint window Once you have mastered the basic functionality of HiTOP explore the following windows The memory window Allows a raw view of the contents of any area of memory Watch Window Allows you to view and modify symbolic variables and complex C objects such as arrays unions and structures Register Window Allows you access to the CPU registers SFR Window Presents the LPC2000 peripherals in a data book format so you can easily see and modify a peripherals configuration Hitex UK Ltd Page 193 hitex mum Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 5 Exercise 2 Startup Code In this example we will configure the startup code to adapt the stack sizes for the different modes to the needs of the application Also we have to initialize the stack pointers for all the modes 1 Please go to StartEasy with the last project click on the yellow folder beside Project Settings and select Stack Sizes Here the values for the stacks for the different ARM modes can be adjusted EET for ARM C temp STEARM ARMTrace hse y Du x mi x
89. PREINT int pclk 32768 1 PREFRAC pclk PREINT 1 x 32768 So for a 30MHz PREINT int 30 000 000 32768 1 914 Then Hitex UK Ltd Page 81 hitex mms 4 User Peripherals DEVELOPMENT TOOLS PREFRAC 30 000 000 914 1 x 32768 17280 These values can be programmed directly into the RTC prescaler registers and the RTC is then ready to run Just enable the clock in the clock control register and the time counters will start PREINT 0x00000392 Set RTC prescaler for 30 000 MHz Pclk PREFRAC 0x00004380 CCR 0x00000001 Start the RTC There are eight time counter registers each of which contains a single time quantity which can be read at any time In addition there are a set of consolidation registers which present the same time quantities in three words allowing all the time information to be read in just three operations Consoldabon 0 The RTC consolidation registers allow all the clock calendar information to be read Consolidation 1 in three words Consolidation 2 As well as maintaining a clock the RTC can also generate alarm events as interrupts There are two interrupt mechanisms You can program the RTC to generate an interrupt when any time counter register is incremented so you could generate an interrupt every second when the second counter is updated or once a year when the year counter is incremented The counter increment interrupt register allows you
90. PSR condition codes If they do not match the instruction is executed as a NOP COND Hitex UK Ltd Page 15 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS So it is possible to perform a data processing instruction which affects the condition codes in the CPSR Then depending on this result the following instructions may or may not be carried out The basic assembler instructions such as MOV or ADD can be prefixed with sixteen conditional mnemonics which define the condition code states to be tested for itt ra Sie aes Each ARM 32 bit instruction can i angst oe be prefixed by one of 16 condition m awa m codes Hence each instruction has a wane 16 different variants a Le Ce CRE TT ET E7777 ECTS mem a anc CRGE EQMOV R1 0x00800000 will only move 0x00800000 into the R1 if the last result of the last data processing instruction was equal and consequently set the Z flag in the CPSR The aim of this conditional execution of instructions is to keep a smooth flow of instructions through the pipeline Every time there is a branch or jump the pipeline is flushed and must be refilled and this causes a dip in overall performance In practice there is a break even point between effectively forcing NOP instructions through the pipeline and a traditional conditional branch and refill of the pipeline This break even point is three in
91. R 0x000000FE Enable seconds Alarm CCR 0x00000001 Start the RTC VICVectAddr13 unsigned RTC_isr Set the timer ISR vector address VICVectCnt113 0x0000002D Set channel VICIntEnable 0x00002000 Enable the interrupt while 1 void RTC isr void unsigned led if ILR amp 0x00000001 Test for RTC counter interrupt led IOPINI read the current state of the IO pins IOCLR1 led amp 0x00030000 Clear the illuminated LED IOSETI led amp 0x00030000 Set the idle LED ILR 0x00000001 Clear the interrupt register if ILR amp 0x00000002 IOSET1 0 00100000 Set LED 0 7 ILR 0x00000002 clear the interrupt register VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 19 Real Time Clock This exercise configures the RTC and demonstrates both the alarm and increment interrupts Hitex UK Ltd Page 83 5 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS 4 6 Watchdog In common with many microcontrollers the LPC2xxx family has a watchdog system to provide a method of recovering control of a program that has crashed Watchdog Register Interface Mexia The on chip watchdog can force a Prat processor reset or interrupt In the case of watchdog reset a flag is set Courier so your code can stop a soft reset Feed Carter Viim The watchdog has four registers as shown above The watchdog t
92. Receiving CAN Data This is the same code as in the previous example but this time it is presented from the receive point of view Open the project in C work EX24 CANRX In main c add the following lines to configure the acceptance filter to receive messages Declare an array in the filter memory unsigned int StandardFilter 2 at O0xE0038000 Configure the standard message filter table AFMR 0x00000001 StandardFilter 0 0x20012002 StandardFilter 1 0x20032004 SFF_sa 0x00000000 SFF GRP sa 0x00000008 Release the receive buffer before leaving the ISR C1CMR 0x00000004 Build the code and start the debugger Run the code as far as initialising the CAN peripherals Examine the Acceptance filter memory in peripherals CAN Acceptance filter This view shows you which messages may be received by the CAN peripherals Continue to run the code and receive a message Check that the message ID matches the Index assigned in the Acceptance filter Hitex UK Ltd Page 170 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Hitex UK Ltd Page 171 mmm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 Chapter 6 Keil Tutorial With GNU Tools 6 1 Intoduction The following tutorial demonstrates how to setup a project in uVision for the GNU compiler Exercises 1 6 are repeated to show the non ANSI aspects of the GNU compiler Once you are familiar with these exercises you can rejoin
93. Register Stack Register Link Register Program Counter The APCS splits the register file into a number of regions RO to R3 are used for parameter passing between functions If you need to pass more than 16 bytes then spilled parameters are passed via the stack Local variables are allocated R4 R11 and R12 is reserved as a memory location for the intra call veneer code In the Keil compiler all code is built for interworking and the global instruction set is the THUMB so all code will be compiled as THUMB instructions except for interrupt code which defaults to ARM This global default can be changed in the Options for Target menu In the CC tab uncheck the use THUMB code box and the default instruction set will be ARM In addition the programmer can force a given function to be compiled as ARM or z six THUMB code This is done with the two Dess Tanger uaa im Li ame Cia le programming directives Pragma ARM and pragma THUMB as shown below n e The main function is compiled as ARM 9 code and calls a function called THUMB function No prizes for itum Ms fr mer zj guessing that this function is compiled in iar SSS Fe tein ivan TES the 16 bit instruction set EF uoa r L dd camo mj ns panier cca is en ea tme 7 LJ Hitex UK Ltd Page 30 2 Software Developme
94. Software Development DEVELOPMENT TOOLS 2 Chapter 2 Software Development 2 1 Outline In this book we will be using an Integrated Development Environment from Hitex Development tools and from Keil Electronik The Keil IDE is called uVision pronounced MicroVision and versions already exist for other popular microcontrollers including the 8051 and the Infineon C16X family uVision successfully integrates project management editor compiler and debugger in one seamless front end The Hitex IDE is called HiTOP which controls instruction set simulators JTAG debuggers and also high end in circuit emulators for various microcontroller architectures HiTOP works with different compilers in the case of ARM especially with the Keil and the GNU compiler Although we are concentrating on the LPC2000 family in this book the Hitex and Keil ARM tools can be used for any other ARM7 based microcontroller 2 2 Which Compiler Both the uVision and the HiTOP development environment can be used with several different compiler tools These include the commonly used ARM ADS compiler the GNU compiler and Keil s own ARM compiler In this book the examples are based on the Keil CA ARM compiler However a parallel set of examples is also included for the GNU compiler and Appendix A details the differences between the Keil and GNU compilers This does beg the question of which compiler to use First of all the GNU compiler is free can be downloaded from the intern
95. System Peripherals 3 Chapter 3 System Peripherals 3 1 Outline Now that we have some familiarity with the ARM7 core and the necessary development tools we can begin to look at the LPC2000 devices themselves In this section we will concentrate on the system peripherals that is to say the features which are used to control the performance and functional features of the device This includes the on chip flash and SRAM memory the external bus interface which is present on the LPC22xx devices the phase locked loop which is used to multiply the external oscillator in order to provide a maximum of 60MHz processor clock and the power control features Finally we will take a look at the simplest user interrupt source the external interrupt pins before going on to look at the exception system in detail in the next section 3 2 Bus Structure To the programmer the memory of all LPC2100 devices is one contiguous 32 bit address range However the device itself is made up of a number of buses The ARM7 core is connected to the Advanced High performance Bus AHB defined by ARM As its name implies this is the fastest way of connecting peripheral devices to the ARM7 core Connected to the AHB is the vector interrupt controller and a bridge to a second bus called the VLSI peripheral bus VPB Since the Interrupt vector controller is responsible for managing all the device interrupt sources it is connected to the ARM7 core by the fastest bus All the r
96. T amp ool l 1 PIC asira 12 PCON rem Hitex UK Ltd Page 59 3 System Peripherals DEVELOPMENT TOO The ARM7 can also be placed into a power down mode which halts both the CPU and the peripherals In this mode only a reset or an interrupt generated by the external interrupt pins will cause the chip to wake up In power down mode the oscillator is shut down All the internal states of the processor registers and on chip SRAM are preserved as are the static logic levels on the I O pins On wake up from power down the clock source is the external oscillator and the PLL must be reconfigured wwa j Power down mode halts the processor and the peripheral clocks The external interrupts can t L sn be used to restart the processor and peripherals ec rcov Pa Carre Bises m The LPC2000 has an internal wake up timer which ensures the external oscillator is stable and the on chip memory and peripherals have initialised before the CPU starts to execute instructions From wake up the oscillator will start to resonate When its cycles become strong enough to drive the chip the wake up timer will count 4096 cycles before initialising the FLASH memory and resuming program execution This ensures the minimum restart delay after a power down or chip reset It is also possible to power down an
97. TTTTTT TTTTTTT 00000000 FTTTTTTT TTTTTTTT TTTTTTTT FTTTTTTT IOPINO 000004000 T T T TT T T FTTT TT Peer FR Pins 000004000 FTTT FT FTTTTTTT FETTTTTT FTTTTTTT These tick boxes control the logic level the simulator sees on the external pins of the LPC2100 Alternatively in the toolbox there is a Generate EINT1 button This button will gene rate a simulated pulse onto the interrupt pin Toolbox A Toolbox with user Toolbox button configurable scripts Update Windows Generate EINT 1 Within uVision there is a full scripting language that allows you to simulate external events These scripts based on the C language and are stored in text files The script used to simulate the pulse is shown below signal void Toggle void PORTO PORTO 0x4000 twatch 200 PORTO PORTO 0x4000 KILL BUTTON DEFINE BUTTON GenerateEINT1 Toggle This script is stored in the file signal ini and is added to the project in the debug window For more details on the scripting language see the uVision documentation Hitex UK Ltd Page 139 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 9 Exercise 6 Software Interrupt In this exercise we will define an inline assembler function to call a software interrupt and place the value 0x02 in the calling instruction In the Software interrupt SWI we will decode the instruction to see which SWI function has
98. This in effect loads the number 2 into the temp variable A switch statement can now be used to run the desired code This method of handling software interrupts is shown in example 6 6 6 Inline Functions Within the GNU compiler functions may be declared as inline functions as follows inline int fast function char paraml Hitex UK Ltd Page 173 hitex mum 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 7 Exercise 1 Using The Keil Toolset With The GNU Compiler This example is based on the source code which can be found in C Exercise Work EX1 first program In this first exercise we will spend some time defining a first project building the code and downloading it into the Simulator for debugging We will then cover the basic debugging functions of the Keil simulator The Keil uVision IDE is designed to support several compilers the GNU C compiler the ARM development suite and the Keil ARM compiler Before compiling make sure you have the GNU compiler selected This is done by activating the project workspace right clicking and selecting manage components In this dialog select the Folders extensions tab and make sure the GNU tools box is selected bpom ra IP Double click on the Keil UVision3 icon to start the IDE k 7 Edi E Preni Lempocen Sahel seers ge T ara Faber Dd uii F r dau Toiv AH Craig Une ed aa E Marr a
99. This will be written on to the bus and will be acknowledged by the slave When the acknowledge is received another interrupt is generated and the status register will contain the code 0x18 if the transfer was successful Now that the slave has been addressed and is ready to receive data we can write a string of bytes into the I2C data register As each byte is written it will be transmitted and acknowledged When it is acknowledged an interrupt is generated and 0x28 will be in the status register if the transfer was successful If it failed and had a NACK the code will be 0x20 and the byte must be sent again So as each byte is transferred an interrupt is generated the status code can be checked and the next byte can be sent Once all the bytes have been sent the stop condition can be asserted by writing to the I2C control register and the transaction is finished The 12C interrupt is really a state machine which examines the status register on each interrupt and performs the necessary action This is easy to implement as a switch statement as shown below Hitex UK Ltd Page 92 hitex mms 4 User Peripherals DEVELOPMENT TOOLS void I2CISR void I2C interrupt routine switch I2STAT Read result code and switch to next action case 0x08 Start bit I2CONCLR 0x20 Clear start bit I2DAT I2CAddress Send address and write bit break case 0x18 Slave address W ACK I2DAT I2Cdata Write data to
100. TxD1 ULLCR 0x00000083 8 bits no Parity 1 Stop bit U1LDLL 0x000000C2 9600 Baud Rate 30MHz VPB Clock U1LCR 0x00000003 DLAB 0 First the pinselect block must be programmed to switch the processor pins from GPIO to the UART functions Next the UART line control register is used to configure the format of the transmitter data character UART Line control register The LCR configures the format of transmitted email data Setting the DLAB bit allows tenpe programming of the BAUD rate Shop bit select generators Parity enable Pari select Break cosine Diener Latch access bel In our example the character format is set to 8 bits no parity and one stop bit In the LCR there is an additional bit called DLAB which is the divisor latch access bit In order to be able to program the Baud rate generator this bit must be set The Baud rate generator is a sixteen bit prescaler which divides down Pclk to generate the UART clock which must run at 16 times the Baud rate Hence the formula used to calculate the UART Baud rate is Divisor Pclk 16 x BAUD In our case at 30MHz Divisor 30 000 000 16 x 9600 approx 194 or 0xC2 Hitex UK Ltd Page 86 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS This gives a true Baud rate of 9665 Often it is not possible to get an exact Baud rate for the UARTs however they will work with up to around a 5 error in the bit timing So you have some leewa
101. VLSI Peripheral Bus Divider The external oscillator or the output of the PLL is used as the source for the Cclk which is the clock source for the ARM7 CPU and the AHB bus The peripherals are on the separate VPB bus 90 Mika if hr Procekkcr iogh Gus The Output from the PLL is called Cclk and provides the clock for the CPU and AHB bus The VLSI bus clock is called Pclk and is derived from Cclk by the VPB P divider 29 26 GO MR The clock on the VPB bus is called Pclk This clock is derived from Cclk via the VPB bridge The VPB bridge contains a divider which can divide down the Cclk by a factor of 1 2 or 4 The VPB divider register can be programmed by your application at any time At reset it is set to the maximum value of four so the Pclk is running at a quarter of the Cclk value at startup Currently all the peripherals on the LPC2000 derivatives can run at the full 60MHz so the VPB divider is principally used for power saving by running the VPB clock at the slowest speed acceptable for your application 3 10 1 1 Example Code PLL And VPB Configuration The code below demonstrates how to configure the PLL to give 60MHz Cclk and 30 MHz with an external crystal of 12MHz void init PLL void PLLCFG 0x00000024 Set multiplier and divider of PLL to give 60 00
102. Ww 476 0 BRAD 462 0 Ox0000044C 0020C3E5 strb r2 r3 1 109 ms 462 1 OxE000C000 Ww 00 454 0 BRAD 440 0 0x000004AC 0020C3E5 strb r2 r3 42 697 ms 440 1 OxE000C000 Ww 1B v In this trace we can see the data written to the UART The State column shows the write cycles indicated with a W and the data column shows the value written in Hex Since only executed instructions can have time information the time can be derived from the instructions which caused the writes which are automatically recorded with the data cycles here the strb2 r3 instructions These are only two simple examples which should give an impression of the additional help the trace recording gives in getting a quick overview of the behaviour of the application Hitex UK Ltd Page 210 9 Appendices DEVELOPMENT TOO Hitex UK Ltd Page 211 9 Appendices 9 Appendices 9 1 Appendix A 9 1 1 Bibliography ARM7TDMI datasheet LPC2119 2129 2194 2292 2294 User Manual ARM System on chip architecture Architecture Reference Manual ARM System developers guide MicroC OS II GCC The complete reference 9 1 2 Webliography 9 1 2 1 Reference Sites http www arm com http www philips com http www lpc2000 com DEVELOPMENT TOOLS ARM Philips Steve Furber David Seal Andrew N Sloss Domonic Symes Chris Wright Jean J Labrosse Arthur Griffith 9 1 3 Tools and Software Development http ww hitex co uk http
103. ace Register Current User System Fast Interrupt Interrupt Each stack is allocated a space of 0x80 Supervisor The user stack is 0x400 bytes so user data will start at 0x40003d80 0x400 R14 LR 0 00000000 SPSR 0 00000000 Abort Undefined Internal Hitex UK Ltd Page 133 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 6 Exercise 3 Using THUMB Code In this example we will build a very simple program to run in the ARM 32 bit instruction set and call a 16 bit thumb function and then return to the 32 bit ARM mode Open the project in C work EX3 Thumb code In main c complete the function declarations for the main function and thumb function as follows void main void arm void thumb function void thumb NB use double underscor Again in the file browser select the root target Flash and in the local menu options for target In the C tab you can select the global instruction set by checking or unchecking the use thumb mode box It is also possible to define the instructions set to be used for a C module by checking or unchecking the same flag in the local C options menu for the C module PIRE AM en iru Des Target Dame ig aum Loon L Loc Dag Uis Level 7 Lind sigh eden NE mri 1 PEU P Thumb Blind r das chery im peie ee Putte 3j Lok Cong s PHE SPEE EEA TAE
104. ange These two instructions perform the same branch operation but also swap instruction operation from ARM to THUMB and vice versa 2 BLX 08000 0x400 PC m il T 1 LOAAS 10 The branch exchange and branch link exchange instructions perform the same jumps as branch and branch link but also swap instruction sets from ARM to THUMB and vice versa FE BLX OXBODO Ox 00 PC OO T 1 14 0 lt el LDARS 10 This is the only method you should use to swap instruction sets as directly manipulating the T bit in the CPSR can lead to unpredictable results Hitex UK Ltd Page 17 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 6 2 Data Processing Instructions The general form for all data processing instructions is shown below Each instruction has a result register and two operands The first operand must be a register but the second can be a register or an immediate value OP code Ofperands 32 bit shaft The general structure of the data processing instructions allows for Cond S R2 sh conditional execution a logical shift of up to 32 bits and the data operation all in the k one cycle Conditional execution Enable condition code flags In addition the ARM7 core contains a barrel shifter which allows the second operand to be shifted by a full 32 bits within the instruction cycle The S bit is used to control the conditio
105. ausing the IRQ interrupt line to be disabled If you need to have nested IRQ interrupts your code must manually re enable the IRQ interrupt and push the link register onto the stack in order to preserve the original return address From the exception interrupt vector your code will jump to the exception ISR The first thing your code must do is to preserve any of the registers RO R12 that the ISR will use by pushing them onto the IRQ stack Once this is done you can begin processing the exception UAFA Bo 1 Save FC link When an exception occurs the CPU will change t ave imi modes and jump to the associated interrupt SH Get vartar LIT mu 25 Once your code has finished processing the exception it must return back to the user mode and continue where it left off However the ARM instruction set does not contain a return or return from interrupt instruction so manipulating the PC must be done by regular instructions The situation is further complicated by there being a number of different return cases First of all consider the SWI instruction In this case the SWI instruction is executed the address of the next instruction to be executed is stored in the Link register and the exception is processed In order to return from the exception all that is necessary is to move the contents of the link register into the PC and processing can continue However in order to make t
106. bit timing is defined by 5 separate parameters 31 23 22 19 15 14 9 SAM Sampling TSEG2 Timing Segment 2 TSEG1 Timing Segment 1 SJW Synchronous Jump Width BRP Baurate Prescaler We can use the values calculated above to initialise one of the CAN controllers to 125Kbit sec It is important to note that the values stored in the register are the calculated values minus 1 This ensures that no timing segment is set to zero Once the CAN controller has been initialised it is possible to transmit a message by writing to a transmit buffer Each transmit buffer is made up of four words Hitex UK Ltd Page 108 4 User Peripherals CANT Fix CANT iDx CAN CAN TDBx hitex mum DEVELOPMENT TOOLS Transmit Frame Info Transmit Identifier Transmit Data 1 4 Transmit Data 5 8 Two words are used to hold the 8 bytes of data and one word holds the message identifier The final register is the frame information register FF ATR DLC PRIO The parameters of each CAN message are defined in each message buffer 31 23 19 16 7 DTR DLC Prio Frame Format Remote Transmit Request Data Len gth Code Priority This register holds the values of the DLC and the RTR bit In addition there is a frame format FF bit that defines whether the message has an 11 bit or 29 bit identifier As there are three TX buffers it is possible to define an internal priority for each TX buffer If several buffers are scheduled simu
107. ble divider which ensures that the CCO is kept in specification The operating frequency of the CCO is defined as Fcco Cclk x 2x P On our development board there is a 12MHz oscillator so to reach the maximum CPU frequency of 60MHz M Cclk Osc 60 12 5 And then for P 156 lt Fcco 320 60 x 2 x P By inspection P 2 The programming interface for the PLL is shown below PLL CS PLLCFO STAT PLL FEED The PLL control registers can be programmed at any time but the new values will not take effect until a correct feed sequence has been written to PLL FEED Hitex UK Ltd Page 56 hitex mum 3 System Peripherals DEVELOPMENT TOOLS The values written to the user SFRs are not transferred to the internal PLL registers until a feed sequence is written to the PLL feed register Once you have updated the PLLCON and PLLCFG registers you must write 0x000000AA followed by 0x00000055 the PLLFEED register These values must be written on consecutive cycles If you program the PLL with interrupts enabled it is conceivable that an interrupt could occur after the first word of the sequence is written and the new PLL settings would not become effective To set up the PLL you must write the values for P and M to the PLLCFG register Then using the PLLCON register the PLL is enabled This starts up the PLL but there is a finite startup time before it is stable enough to be used as the Cclk source The startup
108. board which allows us to trigger an interrupt at will and observe the results with the debugger 3 12 1 Pin Connect Block All of the I O pins on the LPC2000 are connected to a number of internal functions via a multiplexer called the pin select block The pin select block allows a user to configure a pin as GPIO or select up to three other functions Pinel g 10 PWM 1 The Pinselect module allows each I O pin to be multiplexed between one of four PO peripherals Reserved On reset all the I O pins are configured as GPIO The secondary functions are selected through the PINSEL registers The EINT1 interrupt line shares the same I O pin as GPIO 0 14 and a UART1 control line So in order to use EINT1 we must configure the pin select register to switch from the GPIO function to EINT1 3 12 2 External Interrupt Pins The external interrupts are controlled by the four registers shown below The EXMODE register can select whether the interrupt is level or edge sensitive If an external interrupt is configured as edge sensitive the EXPOL register is used to qualify whether the interrupt is triggered on the rising or falling edge In the case of level sensitive triggering the external interrupts can only trigger on a logic zero level If the power down mode is being used the EXWAKE register can enable an interrupt to wake up the CPU So to set up a simple interrupt source program configure the EINT1 interrupt to be level
109. ces crabes ol bye es CE Fleur check med ue er ni nu Pari EF i Lost caen uen cie Philips provide a ready made FLASH In System Programming utility for the PC which can be used to program the development board This tool automatically calculates and adds the program signature to your code to ensure that your program will run If you are using this tool to program the FLASH your code should have a NOP instruction on the unused vector for this tool to work correctly Exercise 7 Memory Accelerator Module and Flash Programming Utility This exercise describes the use of the Philips Flash programming tool to load a simple program into the LPC2000 This program runs without the MAM switched on By adjusting the A D value the MAM is enabled so we can see the performance increase caused by this important peripheral Hitex UK Ltd Page 47 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 6 4 In Application Programming It is also possible to reprogram the FLASH memory from within your program All of the bootloader commands are available as an on chip API and can be called by your code To access the bootloader functions you must set up a table in RAM which contains a command code for the function you want to use followed by its parameters The start address of this table is stored in RO The start address of a second table which contain
110. compiler is to be used please install the Keil or the GNU comp ler for ARM 3 Finally install the StartEasy for ARM software This is a CASE tool for the LPC2000 which will allow you to easily configure the LPC2000 devices Once the software has been installed you are ready to start the tutorial exercises Hitex UK Ltd Page 187 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 2 Creating The First Project This section will cover the Hitex development tools that can be used to develop code for the LPC2000 The generation of the startup and initialization code and the creation of the project is done by StartEasy The difference between using the Keil or the GNU compiler is only the compiler setting is made in StartEasy The debugging tool is HiTOP with the instruction set simulator HiSIM the Tantino for ARM 7 9 or Tanto for ARM the last two are for debugging in the real hardware If you are using a Hitex starterkit the Tantino for ARM7 9 is included with a MCP2100 or an MCB2130 board Most of these examples run on both boards Free versions of HiTOP with HiSIM the GNU compiler and StartEasy are available at http www hitex com in the download area Before we begin to look at the compiler in detail we will run through a step by step tutorial on how to set up a project compile the code and run the debugger This does not cover all the features of HiTOP but once you have a basic understanding of the
111. conditions 1 a F B E I2CONCIER We will first look at the bus master mode To enter this mode the 12C peripheral must be enabled and the acknowledge bit must be set to zero This prevents the I2C peripheral acknowledging any potential master and entering the slave mode In the master mode the LPC2000 device is responsible for initiating any communication During a I2C bus transfer a number of bus events must occur A Typical I2C transaction A s z 12 bus transaction is d nd characterised by a start mda Mos condition slave address pt m data exchange and stop condition with acknowledge handshaking a DA ler Net cran reni START conden P a ETOP condition from Mugs ks flan _ Prom stave to Master The bus master must first signal a start condition To do this the I2C clock line is pulled high and the data is pulled low The address of the slave which the master wants to talk to is then written onto the bus followed by a bit which states if a read or write is being requested If the slave has received this preamble correctly it will reply with an acknowledge Then data can be transferred as a series of bytes and acknowledges until the master terminates the transaction with a stop condition The I2C peripheral on the LPC2000 series is really a 126 engine It controls all the bus events but has no intelligence This means that the ARM7 CPU has to mic
112. ction is called each time it is called This removes the prologue and epilogue code which is necessary for a subroutine making its execution time faster However you are duplicating the function every time it is called so it is expensive in terms of your FLASH memory Hitex UK Ltd Page 35 hitex mm 2 Software Development DEVELOPMENT TOOLS 2 10 Operating System Support If you are using an operating system for the LPC2000 the OS is likely to take care of the system stacks and context switching To avoid duplicating this by the compiler it is possible to declare a function as a task within the operating system This causes the compiler to just translate the code within the function and not to add the normal prologue and epilogue code which saves and restores registers to the stack A function may be declared as a task as shown below void AnalogueSample void task 2 11 Fixing Objects At Absolute Locations The compiler also allows you to fix any C object such as a variable or a function at any absolute memory location The compiler has an extension to the C language as shown below int checksum _ at 0x40000000 Variables declared using this keyword cannot be initialised by the startup code You must also be careful to fix variables on the correct boundaries or you will get a memory abort For example if an integer is located at an uneven memory address 2 12 Inline Assembler The compiler also allows you to
113. de If a message is scheduled and the bus is active it will have to wait until the bus is idle before it can be transmitted If several messages are scheduled while the bus is active they will start transmission simultaneously once the bus becomes idle being synchronised by the start of frame bit When this happens the CAN bus arbitration will take place to determine which message wins the bus and is transmitted CAN arbitrates its messages by a method called non destructive bit wise arbitration In the diagram above three messages are pending transmission Once the bus is idle and they are synchronised by the start bit they will start to write their identifiers onto the bus For the first two bits all three messages write the same logic and Node X AIT Node A Node ua AAT TTT TIT T ds CAN arbitration Node C A ao Message arbitration guarantees that the most important aaa Arbitration phase of message frame message will win the bus and TD Remainder of message frame be sent without any delay Stalled messages will then be A Schedules Message Tx sent in order of priority lowest adc value identifier first Node A x Node B TF V fa Node C ird m Node B loses Node C loses hence read back the same logic so each node continues transmission However on the third bit node A and C write dominant bits and node B writes recessive At this point node B wrote recessive but reads back do
114. e ser Wher raras Bun acknowledged If there is no CRC CAN Sapena handshake the message will serres Data Feki be re sent math Doit Dis Fenrir Egg wo ilem iod ba Da ped bach EDE taii enint then ba iD LACET Fail Hitex UK Ltd Page 110 hitex mum DEVELOPMENT TOOLS 4 User Peripherals The CAN message packet also contains a 15 bit CRC which is automatically generated by the transmitter and checked by the receiver This CRC can detect and correct 4 bits of error in the region from the start of frame to the beginning of the CRC field If the CRC fails and the message is rejected an error frame is placed onto the bus ERE Standard 8 byte Data Frame Inter Frame Space lt DEL A 1 Recessive Xu AAT 0 Dominant CRC is gt Intermission CRC A 15 bit CRC is calculated using Ed End of Frame automatically generated all previous bits ACK Delimiter which is a weighted ear polynomial checksum that res Ba CRC Delimiter provides error detection and cn ee correction across the Each message Des Length code O99899 packet frame includes a reserved bit D 15 bit CRC checksum IDE bt D RTR bit D Identifier Field Start of Frame Once a node has won arbitration it
115. e 0x01 Send Write opcode SOSPDR 0x00000005 status 0x02 set next state break Compile the code and start the simulator Set a breakpoint on the switch statement in the SPI ISR Run the code and examine the state of the virtual EEPROM memory and the debug output in the message window Hitex UK Ltd Page 166 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 26 Exercise 23 Analog To Digital Converter In this exercise we will configure the A D in hardware mode and do an 8 bit conversion on channel 0 The results are modulated onto the LED pins Open the A to D project in C work EX20 AtoD Program the ADCR to give hardware conversion on channel zero 8 bits resolution Adjust the A D clock for a Pclk of 30 MHz ADCR 0x00270601 Test the done bit in ADDR to find a finished conversion while val amp 0x80000000 0 Compile the code and load it into the debugger If you are using the target board turning the potentiometer will change the analogue value analogue channel 0 If you are using the simulator the peripheral window will allow you to simulate external voltages A D Converter x A D Control ADCR 10 01270601 SEL 0x01 PDN BURST CLKS 8cik 7bt gt CLKDIV 0x06 EDGE START Now A D Rate 4285714 A D Data ADDR 0 00004 00 CHN 0 00 DONE OVERUN 13 3000 00130 Analog Inputs AINO 1 0000 AIN1 0 0000 AIN2 0
116. e effectiveness of the MAM can be calculated Flash Access Counter Statistical Control Register The Statistics registers are based around two counters which record the accesses made to the FLASH and the accesses made to the MAM buffers The statistical control register can further refine the type of access which will cause the counters to increment By configuring the statistical control register we can differentiate between code constant and instruction fetches so it is possible to determine the instruction or data hit rate or the combined instruction and data hit rate These metrics can give us some information on the efficacy of the MAM with our application On the CD there is a simple example which demonstrates the use of the MAM its statistical registers and demonstrates how vital it is to the overall performance of the LPC2000 family Hitex UK Ltd Page 43 hitex mm 3 System Peripherals DEVELOPMENT TOOLS 3 5 1 Example MAM Configuration The example code shown below starts the LPC2000 with the PLL set to 60MHZ and the MAM disabled The code FLASHes each LED in sequence with a delay loop between each increment An A D conversion is also done and if the result is above 0x00000080 the code enables the MAM for maximum execution speed The effect of the MAM can be seen on the update rate of the LEDs In the next section we will look at burning the code into the FLASH to observe its operation int main void unsigned int d
117. e exception In other words subtract eight from the link register and store the result in the PC For a data abort exception the return instruction is SUBS R15 R14 8 Once the return instruction has been executed the modified contents of the link register are moved into the PC the user mode is restored and the SPSR is restored to the CPSR Also in the case of the FIQ or IRQ exceptions the relevant interrupt is enabled This exits the privileged mode and returns to the user code ready to continue processing PSR n maed Brom UTER FaK d I i At the end of the exception the CPU returns to user mode and the context is restored by moving the SPSR to the CPSR l PIE Asal ui irom al a PR Ci Hitex UK Ltd Page 14 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 6 The ARM 7 Instruction Set Now that we have an idea of the ARM7 architecture programmers model and operating modes we need to take a look at its instruction set or rather sets Since all our programming examples are written in C there is no need to be an expert ARM7 assembly programmer However an understanding of the underlying machine code is very important in developing efficient programs Before we start our overview of the ARM7 instructions it is important to set out a few technicalities The ARM7 CPU has two instruction sets the ARM instruction set which has 32 bit wide instructions and the THUMB instruction set which has 16 bit wide ins
118. e is user mode but the MSR and MRS instructions work In system mode the new link register must again be preserved because it may have values which are being used by the background user mode code so this register is pushed onto the system stack also the user stack Once this is done we can run the ISR code and then execute a second macro that reverses this process The second macro restores the state of the link register Disables the IRQ interrupts and switches back to IRQ mode finally restores the SPSR_irq and then the interrupt can be ended The two macros that perform these operations are shown below define IENABLE Nested Interrupts Entry __asm MRS LR SPSR Copy SPSR_irq to LR 7 __asm STMFD SP LR Save SPSR_irq __asm MSR CPSR_c 0 1 Enable IRQ Sys Mode asm STMFD SP LR Save LR define IDISABLE Nested Interrupts Exit asm LDMFD SP LR Restore LR asm MSR CPSR c 40x92 Disable IRQ IRQ Mode asm LDMFD SP LR Restore SPSR to LR asm MSR SPSR cxsf LR Copy LR to SPSR irq The total code overhead is 8 instructions or 32 Bytes for ARM code and execution of both macros takes a total of 230 nSec This scheme allows any interrupt to interrupt any other interrupt If you need to prioritise interrupt nesting then the macros would need to block low priority interrupts by disabling the lower pr
119. e located from address 0x80000000 In practice this means changing the start address to 0x80000000 instead of 0x0000000 In the Keil startup code this is done by an assembler directive which is used to relocate the CODE BASE segment containing the vector table IF EXTERNAL MODE CODE BASE EQU 0x80000000 SELSE CODE BASE EQU 0x00000000 SENDIF AREA STARTUPCODE CODE AT CODE BASE READONLY ALIGN 4 PUBLIC startup The define EXTERNAL MODE is declared in the assembler local options menu as shown below Properties Asm m Conditional assembly control Symbols Set CARRE Reset m Macro processor Standard IV Case sensitive symbols Include NENNEN Paths Misc Controls tre SET EXTERNAL DEBUG PRINT phy Startup Ist EP control string ha Once we have our program ready to run from external FLASH there is a slight chicken and egg situation In order to be able to program the external FLASH the chipselect must be configured but to do this we must have code running on the chip One solution would be to place a configuration program into the on chip FLASH boot from this and use it to configure the chipselects However some LPC variants are available without on chip FLASH Fortunately the ULINK JTAG can run a script file to setup the chipselects as required and then program the external memory In addition it i
120. e pin high Open the project in EX18 Timer Match work In Main c complete the timer initialising code as follows Configure the pin connect block with P0 5 as MAT1 PINSELO 0x00000800 Set match zero to reset the counter and generate an interrupt TOMCR 0x00000003 Set the PWM period to 16 msec TOMRO 0x00000010 Set the Match 1 to give a 50 duty cycle TOMR1 0x00000008 Configure match 1 pin to clear on Match It is also set high for the first cycle TOEMR 0x00000042 In the interrupt set Match 1 output pin High TOEMR 0x00000002 Compile and download the code into the debugger Run the code and observe the activity on GPIO pin 0 5 with an oscilloscope Hitex UK Ltd Page 157 5 Tutorial With Keil Tools Again we can see the configuration of the timer in the peripherals window Match on 0x10 Generate interrupt and reset x m Prescaler Timer Interrupt Register PR 00000001E TCR 0900000001 IV Enable IR 0 00000000 PC 0 00000009 000000000 Reset Match Channels MCR 0 00000003 EMR 0 00000042 Interrupt on InteruptonMR1 InteruptonMR2 Interrupt on Reset on MRO Reset on MR1 Reset on MR2 Reset on MR3 Stop on MRO Stop on MR1 Stop on MR2 Stop on EMCO Nothing 7 EMCI Clear 7 2 Nothing EMC3 Nothing 7 ExtemalMatch0 ExtemalMatch1 ExtemalMatch2 7 Extemal
121. e the PWM module for dual edge PWM void main void PINSELO 0x00028000 Enable pin 0 7 as PWM2 PWMPR 0x00000001 Load prescaler PWMPCR 0x0000404 PWM channel 2 double edge control output enabled PWMMCR 0x00000003 On match with timer reset the counter PWMMRO 0x00000010 set cycle rate to sixteen ticks PWMMR1 0x00000002 set rising edge of PWM2 to 2 ticks PWMMR2 0x00000008 set falling edge of PWM2 to 8 ticks PWMLER 0x00000007 enable shadow latch for match 0 2 PWMEMR 0x00000280 Match 1 and Match 2 outputs set high PWMTCR 0x00000002 Reset counter and prescaler PWMTCR 0x00000009 enable counter and PWM release counter from reset while 1 main loop Js Modulate PWMMR1 and PWMMR2 One important line to note is that the PWMEMR register is used to ensure the output of the match channel is logic 1 when the match occurs If this register is not programmed correctly the PWM scheme will not work Also the PWM modulator does not require any interrupt to make it work unlike the basic timers Exercise 18 Centre Aligned PWM This exercise configures the PWM unit to produce a centre aligned PWM signal without any CPU overhead Hitex UK Ltd Page 80 hitex mum 4 User Peripherals DEVELOPMENT TOOLS 4 5 Real Time Clock The LPC2xxx Real time clock RTC is a clock calendar accurate up to 2099 Like all the other peripherals the RTC r
122. ebugger Run the code on the MCB2100 to see the LED chaser If you are using the simulator step through the code and check it works by examining the state of the IO pins via the GPIO peripheral window Hitex UK Ltd Page 154 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 19 Exercise 16 Timer Capture In this exercise we will use timer 0 in a simple compare mode to measure the time between starting the timer and getting a rising edge on pin 0 02 Because the MCB2100 does not have a button on a capture channel to generate the pulse this exercise is based on the Simulator target version is included but you would need to modify the MCB2100 hardware and observe the output on an oscilloscope Pclk 30 MHz Pclock tick 0 033MHz Open the project in EX18 Timer capture work In main c complete the code as follows Enable pin 0 2 as capture channel 0 PINSELO 0x00000020 Load prescaler with 1 micro second tick value TOPR 0x0000001E Reset timer counter and prescaler counter registers TOTCR 0x00000002 Configure capture channel 0 to capture on the rising edge TOCCR 0x00000005 Enable the timer TOTCR 0x00000001 In the interrupt routine copy the capture value into a dummy variable Value TOCRO Compile and load the code into the debugger Run the program and check the following Test the capture interrupt is working by setting a breakpoint on the timer ISR and running the code In the
123. ected register Mnemonic LDR LDRH LDRSH LDRB LRDSB STR STRH STRSH STRB STRSB lf Word Meaning Load Word Load Half Word Load Signed Half Word Load Byte Load Signed Byte Store Word Store Half Word Store Signed Hal Store Byte Store Signed Hal lf Word Since the register set is fully orthogonal it is possible to load a 32 bit value into the PC forcing a program jump anywhere within the processor address space If the target address is beyond the range of a branch instruction a stored constant can be loaded into the PC 1 6 2 2 Copying Multiple Registers In addition to load and storing single register values the ARM has instructions to load and store multiple registers So with a single instruction the whole register bank or a selected subset can be copied to memory and restored with a second instruction Ma 18 Hitex UK Ltd 19 The load and store multiple instructions allow you to save or restore the entire register file or any subset of registers in the one instruction hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 7 Swap Instruction The ARM instruction set also provides support for real time semaphores with a swap instruction The swap instruction exchanges a word between registers and memory as one atomic instruction This prevents crucial data exchanges from being interrupted by an exception This instruction is not reachable from the C lang
124. ee that this function is now in THUMB mode This is indicated by the T bit in the register window and in the disassembly window all THUMB code addresses have the prefix T Hitex UK Ltd Page 196 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 7 Using The Tantino Hardware Debugger The debugger system included with the Hitex starter kit is called the Tantino This connects to the JTAG port on MCB2100 P5 and then connects to the PC via USB To switch from using the simulator to using the Tantino follow the steps below 7 8 Setting Up The Tantino JTAG hardware Debugger Connect the Tantino to the MCB2100 and plug the USB connection into the PC Power should also be connected to the MCB2100 6 5V The Tantino needs a running LPC2000 processor to work correctly The green ON LED of the Tantino must blink If the green and the yellow LED are on the USB power of the Hub is not enough and the Tantino has to be connected to a USB port delivering more than 100mA To select the Tantino instead of the HiSIM please go back to Start Easy select Debug tool in Project Setting Change here the Tool to TantinoARM7 9 and insert the serial number of the Tantino below The serial number is written on the bottom side of the Tantino Hitex UK Ltd Page 197 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS Hitex UK Ltd Page 198 hitex mum 8 Extended Debugging W
125. ei eo feront dre Ina Next highlight the startup s file right click and select Options for file and select the ASM tab Hitex UK Ltd Page 144 hitex mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Enter the EXTERNAL MODE symbol in the control directives box as shown below Lippe Per Fier Pas B C r roh d B EXTEFIHAL MODE DEBUG PART ie tu e EP oni eng This will ensure the startup code is correctly built for an external boot Next in the graphical display of the startup code add the parameters necessary for the chipselect configuration External Memory Controller v Bank Configuration 0 BCFGO IDCY Idle Cycles 3 WST1 Wait States 1 7 WST2 Wait States 2 7 RBLE Read Byte Lane Enable Lj WP Write Protect a BM Burst ROM MW Memory Width 32 bit Bank Configuration 1 BCFG1 IDCY Idle Cycles 3 WST1 Wait States 1 7 WST2 Wait States 2 FA RBLE Read Byte Lane Enable v WP Write Protect EM Burst ROM MW Memory Width 32 bit Build the code and start the simulator Hitex UK Ltd Page 145 5 Tutorial With Keil Tools hitex mum DEVELOPMENT TOOLS In the disassembly window the PC is set to address 0x00000000 and no meaningful code has been loaded 0x00000000 0 00000004 000000008 0x0000000 0 00000010 000000014 000000018 0 0000001 0 000
126. elay unsigned int FLASHer 0x00010000 define locals IODIR1 0 00 0000 set all ports to output VPBDIV 0x02 ADCR 0x00270601 Setup A D 10 bit AINO 3MHz ADCR 0x01000000 Start A D Conversion while 1 do val ADDR Read A D Data Register while val amp 0x80000000 0 val val gt gt 6 amp Ox03FF if val 0x80 MAMCR 0 MAMTIM 0 03 MAMCR 0 02 else MAMCR 0 0 for delay 0 delay lt 0x100000 delay simple delay loop ChangeGPIOPinState FLASHer set the state of the ports FLASHer FLASHer lt lt 1 shift the active led if FLASHer amp 0x01000000 FLASHer 0x00010000 Increment FLASHer led and test for overflow void ChangeGPIOPinState unsigned int state IOCLRI IOSET1 state clear output pins state set output pins Hitex UK Ltd Page 44 hitex mmm 3 System Peripherals DEVELOPMENT TOOLS 3 6 FLASH Memory Programming Although the internal FLASH is arranged as two interleaved banks you will be relieved to know that to the user it can be treated as one contiguous memory space and no special tools are required to prepare the code prior to programming the chip In terms of programming the FLASH to the user it appears as a series of 8K sectors which can be individually erased and programmed There are several methods which can be used to program the on chip FLASH The easiest is by the built in b
127. emaining user peripherals are connected to the VPB The VBP bridge contains a clock divider so the VPB bus can be run at a slower speed than the ARM7 core and the AHB This is useful for two reasons Firstly we can run the user peripherals at a slower clock rate than the main processor to conserve power Secondly it gives Philips the option of adding a slower peripheral to the LPC2000 family without it becoming a bottleneck on the AHB bus Currently all the on chip peripherals are capable of running at 60MHz so the VPB bus can be set to the same speed as the AHB bus It is important to note that after reset the VPB divider is set to divide down the AHB clock by four so all the on chip peripherals will be running at 1 4 the CPU clock frequency Finally there is a third local bus which is used to connect the on chip Flash and RAM to the CPU Connection of the program code and data store to the ARM7 CPU via the AHB bus is possible but this introduces some execution stalls because of contention on the bus Using a separate local bus removes the possibility of these stalls to give the best processor performance neue nca Local Gus RM E da Although the LPC2000 has a linear Avance High Peicemance Bus address space there are several T internal buses It is important to be AHB VPB aware of the difference between them Program i and how the performance of the processor is affected Hitex UK Ltd
128. eptance filter mode register provides global control 31 0 of the acceptance filter AccOFF ENABLE DISABLE ACCEPTANCE FILTER AccBP eFCAN ENABLES FULLCAN MODE Once the acceptance filter is disabled each of the four filter tables may be configured The four tables are as follows Individual standard identifiers 11 bit ID Groups of standard identifiers 11 bit ID Individual Extended identifiers 29 bit ID Groups of extended identifiers 29 bit ID The acceptance filter RAM starts at OxE0038000 Each of the tables must be defined and fixed at absolute locations in the filter RAM The start address of each table should then be written into the relevant acceptance filter register The tables should start at the beginning of RAM and use the memory contiguously Finally the address of the last used location of RAM should be written into the End of Table register To enable the Acceptance filter set the ACCoff bit to logic one and AccBP bits to zero Each of the tables is constructed as follows 31 29 26 16 15 10 0 13 Controller Dis not Identifier able used The Individual Standard identifier table allows you to define individual 11 bit identifiers that will pass through the acceptance filter Each definition takes two bytes the first 11 bits contains the message identifier to be passed This is followed by a bit to dynamically enable or disable this filter entry Finally the top three bits associates this filter entry with a particu
129. equential code execution the code fetched from one bank into the MAM is being executed while the next 128 bits of instructions from the second bank is being perfected This ensures that it will be ready for execution once the last 128 bits has been executed This technique works particularly well with the ARM instructions which can use the condition codes to iron out small branches in order to keep the code flow largely linear In the case of small loops and jumps the MAM has branch and trail buffers that hold recently loaded instructions which can be re executed if required The complexities of the MAM are transparent to the user and it is configured by two registers the timing register and the control register There are some additional registers to provide runtime information on the effectiveness of the MAM The timing register is used to control to relationship between the CPU clock and the FLASH access time By writing to the first three bits of the timing register you can specify the number of CPU clock cycles required by the MAM to access the FLASH As the FLASH has an access time of 20 MHz and the CPU clock can be set to a maximum of 60MHz the number of cycles required to access the FLASH is 3 So for each three CPU cycles we can load four instructions which keep the MAM ahead of the game The MAM configuration register is used to define the operating mode of the MAM ARM7 7 ARM 7 Fully Enabled Sequencial Code Branch
130. er 5 The next step is to set the compiler options We now choose them by clicking on Compiler options An important setting for the application is the setting of the correct global compiler switches Some switches are mandatory so these cannot be changed The optimization level and the warning output can be defined by selecting the desired list entry Other options can be found in the compiler manual Keil Compiler Directives GNU If you want to combine ARM and THUMB code the global compiler switch INTERWORK is necessary 6 Next click on linker options Here only the correct path to the compiler library has to be defined Hitex UK Ltd Page 189 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 Experienced users may now click on Stack Size to adjust the stacks for the different ARM operating modes For our examples these settings are ok If larger stacks are needed i e if you are using nested IRQs then the IRQ and user stack may be adjusted here 8 Click on CPU to define the current derivative When working with the MCB2100 board please select here Philips as vendor LPC2129 as Type and 12MHz as frequency With the MCP2130 board please select the LPC2138 9 Next we click on Debug tool and select HiSIM this will allow you to become familiar with the basic features of the HiTOP user interface The item Build Logfile can be used to review the actions during the project build process All other set
131. es amp Code Data All code amp data present in latches MAM MAM Disabled MAM Instruction prefetch enabled MAM Instruction prefetch enabled FLASH FLASH FLASH Hitex UK Ltd Page 42 hitex mm 3 System Peripherals DEVELOPMENT TOOLS On reset the is disabled and all access to code and constant data are made directly to the FLASH It is possible to partially enable the MAM so that all sequential code is fetched from it but branches and constant data stored in the FLASH are accessed directly from the FLASH Finally the MAM may be fully enabled so that it fetches all FLASH memory accesses from the MAM The reason for these modes is that like a cache code running from the MAM is not deterministic so we have the option to switch it off or reduce its impact if we need to guarantee the run time of our application code However even in its full operating mode the impact of the MAM is not as great as a cache It is possible to predict runtime performance particularly with the use performance analysis features in development tools To help with this analysis and also to gauge the effectiveness of the MAM there are a group of statistical registers which can be used to measure the MAM s performance Statistical Status Register Buffer Access Counter All code amp data present in latches The MAM has some statistics registers which show the number of accesses to the FLASH and the number of accesses to the MAM so th
132. es are available PWMLER 0x0000006 Compile and download the code into the debugger Run the code and check that it is correct with the simulator Again the peripheral window can be user to view the configuration of the PWM module Hitex UK Ltd Page 160 hitex mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 0300000001 0300000003 y 0x00000000 0500000000 7 Hs ERI UTC SETS TE O 00000010H 1 1 Nothing 0 1 00000002H Set 00000008H Set 00000000H Nothing 00000000H Nothing 00000000H Nothing 00000000H Nothing 0x00000010 0x00000007 The logic analyser can also be used to examine the activity on the PWM 1 pin This time the mask should be set to 0x00000080 Setup Export 0 002667 ms 10 35253 ms 10 00000 ps i D i T i i 1 i 1 i D i 1 i 0 n i 1 i i 1 D D D D i i i i i i i i i i i i i D i D i i n i i i n i i i i i i i i i i i n i i i i i i i i i i 1 i D i D i i i i i i D i i i i i i 1 i i i i n i i i i i i i i i i i i i i i i i i i i i i i i
133. et and is also included on the CD which comes with this book So why use an expensive commercial compiler Well before you embark on a full project it is worth looking at the table of benchmarks comparing some of the most popular C compilers available for the ARM CPU We can see from this simple analysis that the commercial compilers are streets ahead of the GNU tools in terms of code density and speed of execution The reasons to use each of the given compilers can be summed up as follows if you want the fastest code and standard tools use the ARM compiler for best code density use the Dhrystone V2 1 Compiler Parameter Keil CA GNU ARM ADS BETA 3 22 1 2 Execution Speed Seconds 112 9 Dhrystones sec 8 857 4 Total Code Size bytes 36 004 Stack Size bytes 852 Total Data Size bytes 11 912 All tests were performed under identical conditions using the Keil yvision Simulator The ARM device used was a Philips LPC2294 running at 60MHz in Thumb Mode Whetstone Compiler Parameter Keil CA GNU ARMADS IAR BETA LENTA v1 2 V4 11A Execution Speed seconds 0 195308 2 461430 0 268623 Whetstone KWIPS 406 3 846 Total Code Size bytes 44 428 28 516 Stack Size bytes 1 552 710 Total Data Size bytes 1 768 76 All tests were performed under identical conditions using the Keil pVision Simulator The ARM device used was a Philips LPC2294 running at 60MHz in Thumb Mode Keil if you have no budget
134. fore exiting the interrupt ILR ILR 0x00000001 increment 0x00000002 Alarm Using either the simulator or the MCB2100 hardware prove the code works correctly Remember the simulator is not realtime and you have to use the Internal Sec counter in the register window to get timing information Hitex UK Ltd Page 162 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 23 Exercise 20 UART In this exercise we will configure UART1 to transmit at 19200 Baud 8 bits no parity on stop bit We will use the UART to echo characters sent to it from the simulator terminal window Open the project in EX13 UART work Configure the UART for 9600 Baud 8 N 1 with pclk 30MHz The actual achievable Baud rate is 9664 UART1_LCR 0x00000083 UART1_DLL 0x000000C2 UART1_LCR 0x00000003 In getchar and putchar add the code to monitor the line status register a For Putchar while UART1 LSR amp 0x20 This line is used twice b For Getchar while UART1 LSR amp 0x01 Compile and download the code into the debugger If you are using the MCB2100 hardware connect UART1 to the serial port of a PC and start Hyperterminal When you run the code enter characters in Hyperterminal and see them echoed back to the screen If you are using the simulator use the built in serial window to simulate a terminal serial window 2 Hitex UK Ltd Page 163 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT
135. ge wo R bullet i Load the INDES value icio the EFS Hitex UK Ltd seek 19 received oae E x FT amp a AA MAT C tab es Page 114 Acceptance filters The CAN modules one 2K block of RAM which is used to set up filter tables to efficiently handle high bus loadings without overloading the CPU mmm 4 User Peripherals DEVELOPMENT TOOLS The acceptance filter also has a full CAN mode In this mode the messages are received and scanned against the table of permissible identifiers If a match is made the message is stored not in the CAN controller receive buffer but in a dedicated message buffer within the acceptance filter memory In this mode each message has its own unique message buffer at a fixed location making all the CAN data easily accessible from the CPU 4 12 9 1 Configuring The Acceptance Filter The acceptance filter is configured by seven registers Control of the filter is via the mode register The various ID tables are configured by the next five registers and the seventh register is an error reporting register Before configuration of the acceptance filter can start it must be disabled This is done by setting the AccOff bit and clearing the AccBP bit in the acceptance filter mode register If the CAN controller is run with this configuration then all messages on the bus will be received gt Q X S amp 5 Y The Acc
136. gister The DAC is enabled by writing to bits 18 and 19 of PINSEL1 and converting pin 0 25 from GPIO to the AOUT function It should also be noted that a channel of the analogue to digital converter also shares this pin BIAS Value 15 6 The DAC is controlled by a single register The value to be converted is written here along with the bias value 31 0 Once enabled a conversion can be started by writing to the VALUE bits in the control register The conversion time is dependant on the value of the BIAS bit If it is set to one the conversion time is 2 5uSec but it can drive 700 UA If it is zero the conversion time is 1 uSec but it is only able to deliver 350 uA However the total settling time is also dependent on the external impedance Figures for the impedance of the DAC have not yet been released Exercise 24 Digital to Analog converter This exercise simulates a sine wave which is sampled by the Analogue to digital converter These values are loaded straight into the Digital to Analogue converter to regenerate the sine wave The two sine waves can be compared in the logic analyzer window Hitex UK Ltd Page 100 mmm 4 User Peripherals DEVELOPMENT TOOLS 4 12 CAN Controller Variants of the LPC2000 are available with up to 4 independent CAN controllers on board the chip The CAN controllers are one of the more complicated peripherals on the LPC2000 In this section we will have a look at the CAN protocol and the
137. he CPU switch modes back to user mode a modified version of the move instruction is used and this is called MOVS more about this later Hence for a software interrupt the return instruction is MOVS R15 R14 Move Link register into the PC and switch modes Hitex UK Ltd Page 13 hitex mm 1 The ARM7 CPU Core DEVELOPMENT TOOLS However in the case of the FIQ and IRQ instructions when an exception occurs the current instruction being executed is discarded and the exception is entered When the code returns from the exception the link register contains the address of the discarded instruction plus four In order to resume processing at the correct point we need to roll back the value in the Link register by four In this case we use the subtract instruction to deduct four from the link register and store the results in the PC As with the move instruction there is a form of the subtract instruction which will also restore the operating mode For an IRQ FIQ or Prog Abort the return instruction is SUBS R15 14 4 In the case of a data abort instruction the exception will occur one instruction after execution of the instruction which caused the exception In this case we will ideally enter the data abort ISR sort out the problem with the memory and return to reprocess the instruction that caused the exception In this case we have to roll back the PC by two instructions i e the discarded instruction and the instruction that caused th
138. he UART These low level drivers are called by the Keil STDIO functions such as printf and scanf So if you want to redirect the standard I O from the UART to say an LCD display and a keypad rewrite these functions to support sending and receiving a single character to your desired I O devices Both the putchar and getchar functions read the Link Status Register LSR to check on UART error conditions and to check the status of the receive and transmit FIFOS Hitex UK Ltd Page 87 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS UART Line Status Register The LSR contains flags which indicate Panty caper events within the Framing error UART It may be polled or should be read after a Transmiter h hiang T L empty UART interrupt is generated 8 8 amp Data rea LET Break iwterupt in Ex FIF The UART has a single interrupt channel to the VIC but three sources of interrupt UART interrupts can be generated on a change in the Receive line status So if an error condition occurs an interrupt is generated and the LSR can be read to see what is the cause of the error The remaining two interrupt sources are receive and transmit interrupts The receive interrupt is triggered by characters being received into the RX FIFO The depth at which the interrupt is triggered is set in the UART FIFO control register 11 H MH UART RX FIFO
139. he next exercise Next select the MAM hex file from the project directory and press Upload to Flash this will program the target LPC2100 You can also use the Compare button the verify that the flash has programmed correctly If you select the buffer option the same operations can be performed along with calculation of the program signature and limited debugging options Hitex UK Ltd Page 141 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS i amp Fe y d YN LS oid PW im ow 15 i i i 1 m wu m uw mem M ow a w in T i BEER o D OD QD pe m a E m m E u ae 0 UE EB WU D E m iB EN aD Heat A d E 4 x ab D m i m x s mnmIE E te m oU Eom mw D i 1 i E m mw m ine E wrn Konn X 2 m mnm HRA 07 3g D DO al Bee i F E EI DP E E D Mi MP L HAR 60 d e Um dd Dj HAH LB m C md Zao i 32 EB OW i i E D 15 s m mu muri M La ADO oa moe q E 08 EL D4 DB a HH a 1 ES mom a Ip m 00 ee g w amp 0 uw Banh X m ox aud atr Eh Ww i ib moa d D gm ow KH od gm pm o3 m F Fi i I E A amp ED g UN b 1 xu D i neat d Gi D og X s D i od ai D D gw LT ARH d i a m apr duxi mu ud 1
140. hen the PC reaches main examine the contents of each R13 register User Syst R8 0x00000000 R3 0x00000000 R10 0 40003980 R11 0x00000000 R12 000000000 R13 SP x40003d80 14 08 000000000 Fast Interrupt R8 0 00000000 Rg 0 00000000 R10 0 00000000 R11 0 00000000 R12 0x00000000 13 5 Ox40003f00 Each stack is allocated space of 0 80 The user stack is 14 08 000000000 0x400 bytes so user data will start at 0x40003d80 0 400 SPSR 0x00000000 Interrupt Ri3 SP 0 40003 80 Ri4 LR 000000000 H SPSR 0 00000000 El Supervisor R13 SP 0 40003 00 R14 LR 000000000 SPSR 000000000 Abort R13 SP Ox40003f80 RHi4 LR Ox00000000 H SPSR 0 00000000 El Undefined R13 SP 040004000 R14 LR 0x00000000 H SPSR 0 00000000 Start of stack space at the top of on chip memory 6 9 Exercise 3 Using THUMB Code Hitex UK Ltd Page 179 6 Keil Tutorial With GNU Tools hitex mum DEVELOPMENT TOOLS In this example we will build a very simple program to run in the ARM 32 bit instruction set and call a 16 bit THUMB function and then return to the 32 bit ARM mode Open the project in EX3 THUMB code work In the files browser select thumb c open the local menu right click and select options for thumb c Flash 3 63 Source Group 1 25 26 m void thumb function void Exterr 2
141. hitex EN 5 Insider s Guide Philips ARM 7 An Engineer s Introduction To The LPC2100 Series Trevor Martin BSc hons CEng MIEE www hitex co uk Introduction to the LPC2000 Published by Hitex UK Ltd ISBN 0 9549988 1 First Published February 2005 First Reprint April 2005 First Revision February 2006 Hitex UK Ltd Sir William Lyons Road University Of Warwick Science Park Coventry CV4 7EZ Credits Author Trevor Martin Illustrator Sarah Latchford Editors Michael Beach Cover Wolfgang Fuller Acknowledgements Introduction The author would like to thank Kees van Seventer and Chris Davies of Philips Semiconductors for their assistance in compiling this book Hitex UK Ltd 13 02 2006 All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical or photocopying recording or otherwise without the prior written permission of the Publisher Hitex UK Ltd Page 2 Introduction to the LPC2000 Introduction 1 Chapter 1 The ARM7 CPU Core 9 1 1 Outlines date tee ent rte tte test 9 1 2 The Pipeline 1 3 Registers E tie be Se eh ea Pado e ORE Ed 1 4 Current Program Status Register 11 1 5 Exception Modes ene eee 12 1 6 The ARM 7 Instruction Set
142. hly optimised interrupt controller The VIC is used to handle all the on chip interrupt sources from peripherals Each of the on chip interrupt sources is connected to the VIC on a fixed channel your application software can connect each of these channels to the CPU interrupt lines FIQ IRQ in one of three ways The VIC allows each interrupt to be handled as an FIQ interrupt a vectored IRQ interrupt or a non vectored IRQ interrupt The interrupt response time varies between these three handling methods FIQ is the fastest followed by vectored IRQ with non vectored IRQ being the slowest We will look at each or these interrupt handling methods in turn 0 Fg ET The VIC provides three levels of i interrupt service on chip interrupt TOA VEC 4 sources be allocated into each i group hos LER ES Hitex UK Ltd Page 62 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 12 4 FIQ interrupt Any interrupt source may be assigned as the FIQ interrupt The VIC interrupt select register has a unique bit for each interrupt Setting this bit connects the selected channel to the FIQ interrupt In an ideal system we will only have one FIQ interrupt However setting multiple bits in the Interrupt Select Register will enable multiple FIQ interrupt sources If this is the case on entry the interrupt source can be determined by examining the VIC FIQ Status
143. idth of a pulse applied to a capture pin Each timer also has up to four match channels Each match channel has a match register which stores a 32 bit number The current value of the timer counter is compared against the match register When the values match an event is triggered This event can perform an action to the timer reset stop or generate interrupt and also affect an external pin set clear toggle When the timer counter equals the value stored in the match register it can trigger a timer event and also affect an external match pin Reso Ti l Siop Tc Inaermups External Mateh Regeter Hitex UK Ltd Page 75 hitex mms 4 User Peripherals DEVELOPMENT TOOLS To configure the timer for a match event load the match register with the desired value The internal match event can now be configured through the Match Control Register In this register each channel has a group of bits which can be used to enable the following actions on a match event generate a timer interrupt reset the timer or stop the timer Any combination of these events may be enabled In addition each match channel has an associated match pin which can be modified when a match event occurs As with the capture pins you must first use the pin connect block to connect the external pin to the match channel The match pins are then controlled by the first four bits in the external match register CRETE amp Ess Liban kb
144. imeout period is set by a value programmed into the Watchdog Constant Register WDTCR The timeout period is determined by the following formula Wdperiod Pclk x WDTC x 4 The minimum value for WDTC is 256 and the maximum is 2132 Hence the minimum watchdog period at 60MHz is 17 066us and the maximum is just under 5 minutes Once the watchdog constant is programmed the operating mode of the watchdog can be configured The Watchdog mode register contains three enable bits controlling whether the watchdog generates an interrupt whether it generates a reset and a final bit which is used to enable operation of the watchdog Crvarfiow Feed error The watchdog mode register allows configuration the watchdog action on underflow reset or interrupt t inbemumt The Mode register also contains two flags the WDTOF is set when the watchdog times out and is only cleared after an external hard reset This allows your startup code to detect if the reset event was a power on reset or a reset due to a program error The Mode register also contains the watchdog interrupt flag This flag is read only but it must be read in order to clear the watchdog interrupt If you need to debug code with the watchdog active you should not enable the reset option as this will trip up the JTAG debugger when the watchdog times out Once the watchdog timer constant and mode registers have been configured the watchdog can be kicked into action by writing to
145. in Fesses ix mt Bi ami zac 15 wei EP nea Seis CHE CENTER FES E RE LE Tbh dattes WERL ALTER mamari i DE AS H FO UT 1 a I BG DO ZG 48 OU PETE a am Command Line CPU Registers Memory Window Watch Window The code will be loaded into the simulator and executed from the reset vector until it reaches main The project browser is replaced by a register window that allows you to view the contents of the CPU registers Here you can View the registers in each of the different operating modes Open the SPSR and CPSR registers to view the flags View the internal mode to the simulated cycle count and timestamp Change the contents of a register by triple clicking on its value and then entering a new value Hitex UK Ltd Page 126 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS From main single step the code Use F11 to step a line of code Use F10 to block step lines of code and functions Use F5 to run the code at full speed Use ESC to halt the code Note For the single step commands to work a source code window must be the active window To set a breakpoint Select a line of code right click for the local menu and select insert remove breakpoint Now press F5 to run to the breakpoint i 2 while lt n fibo fibl fib2 fibl fib2 fib2 fibo i
146. instruction 1 9 Software Interrupt Hitex UK Ltd Page 20 hitex DEVELOPMENT TOOLS 1 The ARM7 CPU Core The Software Interrupt Instruction generates an exception on execution forces the processor into supervisor mode and jumps the PC to 0x00000008 As with all other ARM instructions the SWI instruction contains the condition execution codes in the top four bits followed by the op code The remainder of the instruction is empty However it is possible to encode a number into these unused bits On entering the software interrupt the software interrupt code can examine these bits and decide which code to run So it is possible to use the SWI instruction to make calls into the protected mode in order to run privileged code or make operating system calls 31 28 27 24 23 The Software Interrupt Instruction forces the CPU into SUPERVISOR mode and jumps the PC to the SWI vector Bits 0 23 are unused and user defined numbers can be encoded into this space The Assembler Instruction SWI 3 Will encode the value 3 into the unused bits of the SWI instruction In the SWI ISR routine we can examine the SWI instruction with the following code pseudo code switch R14 4 amp OxOOFFFFFF voll back the address stored in link reg by 4 bytes Mask off the top 8 bits and switch on result case SWI 1 Depending on your compiler you may need to implement this yourself or it may be done for you in the compiler implementa
147. interrupt TOMRO 0x00000010 Set the cycle tim TOMR1 0x00000008 Set 50 duty cycle OEMR 0x00000042 On match clear MAT1 and set MATI pin high for first cycle TOTCR 0x00000001 Enable timer VICVectAddr4 unsigned TOisr Set the timer ISR vector address VICVectCntl4 0x00000024 Set channel VICIntEnable 0x00000010 Enable the interrupt while 1 Hitex UK Ltd Page 76 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS void TOisr void irq OEMR 0x00000002 Set MATI high for beginning of the cycle TOIR 0x00000001 Clear match 0 interrupt VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 17 Timer Match This second timer exercise uses two match channels to generate a PWM signal there is some CPU overhead in the timer interrupt routine Hitex UK Ltd Page 77 hitex mm 4 User Peripherals DEVELOPMENT TOOLS An 4 4 PWM Modulator At first sight the PWM modulator looks a lot more complicated than the general purpose timers However it is really an extra general purpose timer with some additional hardware The PWM modulator is capable of producing six channels of single edge controlled PWM or three channels of dual edge controlled PWM Frise Press Corse Maki Hagai LE The PWM module is a third general purpose time with additional hardware for dedicated PWM generation
148. interrupts Check for ARM or Thumb mode Load an Exit address into the link register p Jump to the C init routine MSR CPSR Mode USR MOV SP RO Enter the C code LDR RO C INIT TST RO 1 Bit 0 set INIT is Thumb LDREQ LR exit A ARM Mode LDRNE LR exit T Thumb Mode BX Since each operating mode has a unique R13 there are effectively six stacks in the ARM7 The strategy used by the compiler is to locate user variables from the start of the on chip RAM and grow upwards The stacks are located at the top of memory and grow downwards The startup code enters each different mode of the ARM7 and loads each R13 with the starting address of the stack ack Configuration Steck Sors in Eines Mode CrcOOCDIO Oo Paar Dono DOS Abort Mode Onli DOC Fail Irbernuph Mads Interrupt feas Cre aon Dono Lines seri Peden rein Cu E PEL Setup E MAM Setup XI XI nterna Merny Controller MC Like the vector table you are responsible for configuring the stack size This can be done by editing the startup code directly however Keil provide a graphical editor that allows you to more easily configure the stack spaces In addition the graphical editor allows you to configure some of the LPC2000 system peripherals We will see these in more detail later but remember that they can be configured directly in the startup code Exercise 2 Startup code The second exercise in the Keil or H
149. iority interrupt sources in the VIC Exercise 14 Nested Interrupts OK one last interrupt exercise This exercise demonstrates setting a timer to generate a regular periodic interrupt which must run It also configures an interrupt which is triggered by Eint1 The external interrupt uses the above technique to allow the timer interrupt to run even if the external interrupt routine is active 3 13 Summary This is the most important chapter in this book as it describes the system architecture of the LPC2000 family You must be familiar with all the topics in this chapter in order to be able to successfully configure the LPC2000 for its best performance and to avoid many of the common pitfalls which trap people new to this family of devices Hitex UK Ltd Page 70 hitex mum 4 User Peripherals DEVELOPMENT TOOLS Hitex UK Ltd Page 71 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS 4 Chapter 4 User Peripherals 4 1 Outline This chapter presents each of the user peripherals in turn The examples show how to configure and operate each peripheral Once you are familiar with how the peripherals work the example code can be used as the basis for a set of low level drivers 4 2 General Purpose I O On reset the pin connect block configures all the peripheral pins to be general purpose 1 0 GPIO input pins The GPIO pins are controlled by four registers as shown below GPO FES Each GPIO pin is controlled by a
150. is clear and the instructions are 4 bytes long A call to the THUMB function is made which executes a BX instruction forcing the processor into THUMB mode 16 bit The THUMB bit is set and on entry to the THUMB function a PUSH instruction is used to preserve registers on to the stack Hitex UK Ltd Page 181 hitex mum 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS 6 10 Exercise 4 Using The GNU Libraries In this exercise we will look at tailoring the GNU Printf function to work with the LPC2100 UART We will look at the registers of the UARTs in more detail later Open the project in EX4 printflwork In main c add a message for transmission to the printf statement while 1 1 printf Your Message Here Mn Call the prinfF function Add the file syscalls c in the work directory to the project 1 29 Flash H 6 Source Group 1 main c serial c Startup s Syscalls c E E E In syscalls c add modify the write function as follows Complete the for loop statement so it runs for the length of the printf string len Inside the for loop add the putchar statement to write a single character to the stdio channel putchar ptr Increment the pointer to the character string ptr int write int file char ptr int len int i for i 0 i lt len i putchar ptr return len Compile the code and download it to the development board Run the code and observe the output withi
151. is function but not the code contained within the function This is because the trace filter excludes any lines of code outside the defined address range of the TIMER 0 function Next we will look at making an inclusive trace which shows the execution of the TIMER O0 function and the lines of code executed in all the functions it calls Redefine the trace filter with the changes Length 1 Trace Recording Enable Define a second filter with the settings please click into the next line with the right mouse button and select change Address TIMERO code size isr TIMERO 4 Length 1 Trace Recording Disable The address isr TIMERO ecode size isr TIMERO 4 is the last instruction of the function isr TIMERO which is used to disable the trace recording We start again the application and stop after a short time and see another trace display Hitex UK Ltd Page 204 mmm 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS loxi Frame Address Sta Da HLL Source Line Exter Time 2097062 0 197 3 1 58 us 2097052 0 198 SWITCH IRQ TO SY5 3 0 42 us 2097048 0 202 interrupt identification TIMERO IR 3 0 38 us 2097042 0 205 TIMERO IR OxFF 3 0 69 us 2097034 0 208 inc clock 3 0 34 us 2097033 0 209 if Clock MilliSec 100u 00 3 2097028 0 104 Clock MilliSec CLOCK_DISTANCE 3 0 22 us 2097020 0 106 if Clock MilliSec gt 1000u 3 0
152. is located to run from the reset vector It provides the exception vector table as well as initialising the stack pointer for the different operating modes It also initialises some of the on chip system peripherals and the on chip RAM before it jumps to the main function in your C code The start up code will vary depending on which ARM7 device you are using and which compiler you have so for your own project it is important to make sure that you are using the correct file The start up code for the Keil compiler may be found in C keil ARM startup and for the GNU use the files in C keil GNU startup First of all the startup code provides the exception vector table as shown below EXTERN Undef Handler A Declare the external C EXTERN CODE B EXTERN Ct exception routines EXTERN Cc EXTERN The suffix A denotes an EXTERN CODE ARM routine Vectors LDR Reset Ad r LDR LDR PC LDR LDR Unused vector this will become important later LDR PC IRQ_Ad LDR PC FIQ Add DD Reset_Handler Undef Addr DD Undef Handle A Constants table for ISR d Db Pabt_Ad r DD Handler address DD DAbt_Handler A 0 f Reserved Address IRQ Ad DD FIQ_Addr DD FIQ Handle The vector table is located at 0x00000000 and provides a jump to interrupt service routines ISR on each vector To ensure that the full address range of the processor is available the LDR L
153. itex tutorial takes processor stack and examines the vector table SVC Stack gt RAM LIMIT 0x40010000 IRQ Stack 256 bytes FIQ Stack gt ABT Stack 3 UNDEF Stack gt eee USR Stack The six on chip stack pointers R13 are initialised at the top of on chip memory Care must be taken to allocate enough memory for the maximum size of each stack you through allocating space for each Hitex UK Ltd Page 29 hitex mum 2 Software Development DEVELOPMENT TOOLS 2 4 Interworking ARM THUMB Code One of the most important things that we need to do in our application code is to interwork the ARM and THUMB instruction sets In order to allow this interoperability ARM have defined a standard called the ARM THUMB Procedure Call Standard ATPCS The ATPCS defines among other things how functions call one another how parameters are passed and how stacks are handled The APCS adds a veneer of assembler code to support various compiler features The more you use the larger these veneers get In theory the APCS allows code built in different toolsets to work together so that you can take a library compiled by a different compiler and use it with the Keil toolset Parameter Passing The ARM procedure call standard defines how the user CPU registers should be used by compilers Adhering to this standard allows interworking between different manufacturers tools Local Variables Scratch
154. ith ETM Trace DEVELOPMENT TOOLS 8 Chapter 8 Extended Debugging With ETM Trace 8 1 Outline This chapter describes the advantages of using the ETM capabilities of the LPC2000 controllers and how to use the Tanto System with trace expansion After explaining the principles of the ETM and how to handle the trace recording the benefit of this feature is explained with some special examples The LPC2000 is unique among ARM7 based microcontrollers in that Philips have included the ETM module as a standard feature of the chip The ETM is an extra cost in die space on the chip and has an additional licensing cost from ARM However as we shall see the ETM greatly enhances the debug capability of the LPC2000 over standard JTAG This allows firmware to be developed to much higher standards making the LPC2000 suitable for use in safety critical applications such as medical and Aerospace Even if you do not plan to use an ETM based debugger we would strongly recommend adding the ETM socket to you design then if you run into complex problems you at least have the option to use the TANTO to solve the problem The pinout of the connector is shown in chapter 2 and a PDF of the socket is on the CD 8 2 Using The Tanto With Trace To use the Tanto system the option Tanto has to be installed with HiTOP for ARM please refer to Chapter 7 The 38 pin Mictor socket from AMP is designed to carry high speed signals in addition to the JTAG signals there are trace
155. its behaviour during reset If the ARM7 CPU is reset all of the peripherals including the JTAG are reset When this happens the ULINK debugger loses control of the chip and has to re establish control once the LPC2000 device comes out of reset This will take a finite number of clock cycles While this is happening any code which is on the chip will be run as normal Once the ULINK gets back control of the chip it performs a soft reset by forcing the PC back to address zero However the on chip peripherals are no longer in the reset condition ie peripherals will be initialised interrupt enabled etc You must bear this in mind if the application you are developing could be adversely affected by this A quick solution is to place a simple delay loop in the startup code or at the beginning of main After a reset occurs the CPU will be trapped in this loop until the ULINK regains control of the chip None of the application code will have run leaving the LPC2000 in its initialised condition 2 14 Summary So by the end of this section you should be able to set up a project in the Keil uVision IDE select the compiler and LPC2000 variant you want to use configure the startup code be able to interwork the ARM and THUMB instruction sets access the LPC2000 peripherals and write C functions to handle exceptions With this grounding we can now have a look at the LPC2000 system peripherals Hitex UK Ltd Page 38 hitex m DEVELOPMENT TOOLS 3
156. j File Edit Info D E ad 8 Project ARMTrace Adjust Stack Size words zy Project Settings UND E Global Settings Sve e E Tool path E Compiler Options ABT mm m El Linker Options FIQ m Stack Size _ 50 E CPU IRQ E Debug Tool us fos E Build Logfile E INFO E Ini data m C LPC2000 Setup CA Project files 2 Now we create the changes code with the menu File and the item Update code After the successful creation of the code we can now debug this application with HiTOP Please open HiTOP select menu Project item Open and browse for the file project file it was created in the folder defined in StartEasy in Project Path with the name lt project name gt htp 3 Now the connection to Tantino is established and with click on ok in the download dialog the application is programmed into the FLASH We let run the application behind the startup code with the command Go Until main menu Debug item Go until insert main and click ok The initialized values of the stack pointers can be read out with the SFR window open it with menu View item SFR window and select ARM Processor Register For each mode the set of registers is displayed and all the SP registers of the modes are initialized with the correct values When you open the disassembly window and change the address display to address 0 double click in the add
157. lar CAN controller 31 29 26 16 10 0 Lower Identifier Bound conroters Lu Upper Identifier Bound Hitex UK Ltd Page 115 mmm 4 User Peripherals DEVELOPMENT TOOLS The group standard identifier table uses the same format but two entries are used to define the upper and lower identifier address range for messages that are allowed to pass through the acceptance filter 31 29 28 0 Controller Identifier The individual extended identifier table uses four bytes per entry as shown above The first 29 bits define the message identifier to be passed through the acceptance filter and the top three bits associates the filter entry with a particular CAN controller The group extended identifier table uses two words in the same format as the individual extended table to build up a start and end identifier values in the same fashion as the standard message group table The following code shows how the acceptance filters may be configured for the basic CAN mode unsigned int StandardFilter 2 _at_ 0xE0038000 Declare the standard acceptance filter tabl unsigned int GroupStdFilter 2 _at_ 0xE0038008 Next the standard Group filter table unsigned int IndividualExtFilter 2 _at_ 0xE0038010 Now th xtended filter table unsigned int GroupExtFilter 2 _at_ 0xE0038018 Finally the Group extended filter table AFMR 0x00000001 Disable the Acceptance filters StandardFilter 0 0x
158. lated EEPROM memory is mapped into an unused section of the processor address range In this case 0x00030000 to 0x000300FF As the code is run you can view data as it is written and read from the memory this can be great aid to debugging your drivers Hitex UK Ltd Page 164 hitex mms 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Address 030000 0x 00030000 03 00 00 00 00 O0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Memory Hitex UK Ltd Page 165 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 25 Exercise 22 SPI Like the 12C example this example uses the SPI interface to communicate to a serial EEPROM and demonstrates how to write and read data to such a device Since the MCB2100 is not fitted with such a memory this example uses the simulator with a script file to simulate the EEPROM Open the project in C work EX16 SPI The script file is in and this is added to the project in Options for Target Debug The script maps some memory for the SP EEPROM at 0x700000 0x7000FF In Main c add the following lines of Code Configure the operation mode and bit timing SOSPCCR 0x000000FF SOSPCR 0 000000 0 Kick off an SPI transfer SPI write output buffer 8 Use a case statement for each state of the transaction cas
159. ld This causes the to perform a single conversion and store the results in the ADDR in the same fashion as the hardware mode The end of conversion can be signalled by an interrupt or by polling the done bit in the ADDR In the software conversion mode it is possible to start a conversion when a match event occurs on timer zero or timer one Or when a selected edge occurs on P0 16 or P0 22 the edge can be rising or falling as selected by the EDGE field in the ADCR Halted Start Now FO 16 The A D may be started by a PO 22 software event or it may be started MAT 0 1 by several hardware triggers MAT 0 3 MATT 1 0 MAT 1 1 Hitex UK Ltd Page 98 mmm DEVELOPMENT TOOLS 4 User Peripherals The simplest method of using the A D converter is shown below VPBDIV 0x02 Set the Pclk to 30 MHz IODIR1 0x00FF0000 P1 16 23 defined as Outputs ADCR 0x00270601 Setup A D 10 bit AINO 3MHz ADCR 0x01000000 Start A D Conversion while 1 do val ADDR Read A D Data Register Exercise 23 Analog To Digital Converter This exercise uses the A D to convert an external voltage source and modulate a bank of LEDs with the result Hitex UK Ltd Page 99 mmm 4 User Peripherals DEVELOPMENT TOOLS 4 11 Digital To Analog Converter The LPC2132 2138 variants have a 10 bit Digital to Analogue converter This is an easy to use peripheral as it only has a single re
160. le 0x04000000 AFMR 0x00000001 C1MOD 0x00000000 while 1 void CANIIRQ void __irq IOCLR1 IOSET1 C1CMR 0x0000 VICVectAddr Hitex UK Ltd CIRDA clear Set 1 to 60MHz set all ports to output Enable Pin 0 25 as CAN1 RX Set CAN controller into reset Set bit timing to 125k Enable the Receive interrupt select a priority slot for a given interrupt unsigned CANIIRO pass the address of the IRQ into the VIC slot enable interrupt Disable the Acceptance filters Release CAN controller output pins set output pins 0004 r lease the receive buffer 0x00000000 Signal the end of interrupt Page 113 4 User Peripherals 4 12 9 Acceptance Filtering hitex mum DEVELOPMENT TOO While the receive example shown above will work perfectly well it suffers from two problems Firstly it receives every message transmitted on the bus In a fully loaded CAN bus this could mean a message would be received every 72us As the LPC2000 has up to 4 CAN controllers the CPU would have to spend a lot of time just managing the CAN busses Secondly once the message has been received the CAN controller would have to read and decode the message identifier in order to decide what to do with the message In order to overcome these problems the LPC2000 CAN controllers have a sophisticated acceptance filtering scheme The acceptance filter is u
161. ll power consumption and the on chip noise created by the A D On reset the A D is in power down mode so as well as setting the clock rate the A D must be switched on This is controlled by the PDN bit in ADCR Logic one in this field enables the converter Unlike other peripherals the A D converter can make measurements of the external pins when they are configured as GPIO pins However by using the pinselect block to make the external pins dedicated to the A D converter the overall conversion accuracy is increased Prior to a conversion the resolution of the result may be defined by programming the CLKS field The A D has a maximum resolution of 10 bits but can be programmed to give any resolution down to 3 bits The conversion resolution is equal to the number of clock cycles per conversion minus one Hence for a 10 bit result the A D requires 11 ADCLK cycles and four for a 3 bit result Once you have configured the A D resolution a conversion can be made The A D has two conversion modes hardware and software The hardware mode allows you to select a number of channels and then set the A D running In this mode a conversion is made for each channel in turn until the converter is stopped At the end of each conversion the result is available in the A D data register Dona Oven THN VA dea AD data register The data register contains the conversion result channel overrun error and conversion done flag Hitex UK Ltd Page 97 hitex mum
162. llow a node TEC gt 127 DEC 1278 Ne 11 recessive bits to fail in an elegant fashion without x 127 blocking the bus Error Passive Bus Off REC Recessive Error Counter TEC Transmit Error Counter These are a receive error counter and a transmit error counter These counters will count up when receiving or transmitting an error frame If either counter reaches 128 then the CAN controller will enter an error passive mode In this mode it still responds to error frames but if it generates an error frame it writes recessive bits in place of dominant bits If the transmit error counter reaches 255 then the CAN controller will go into a bus off condition and take no further part in CAN communication To restart communication the CPU must intervene to reinitialise the controller and put it back onto the bus Both these mechanisms are to ensure that if a node goes faulty it will fail gracefully and not block the bus by continually generating error frames The LPC2000 CAN controllers have a number of error detection mechanisms First of all the current count of the transmit and receive error counters can be read in the Global Status Register Also in this register are two error flags the Bus Status flag will be set when the maximum error count is reached and the CAN controller is removed from the bus The second error flag is the Error Status flag which is set when the CAN error counters reach a warning limit This warning limit is an a
163. lock 3 0 26 ps 58 0 104 Clock MilliSec CLOCK DISTANCE 3 0 22 us 5000106 Clock Milisec gt 1000u i a 36 0 125 3 0 44 us 32 0 209 if Clock MilliSec 100u Qu 3 0 38 us 1 0 211 convert clock 3 1 34 us gt Source main c E BE lol Disassembly startup main interrupt always called from interrupt routine no critical section Clock MilliSec CLOCK DISTANCE if Clock MilliSec gt 1000u f 1 Clock MilliSec Ou Clock Sect if Clock Sec gt 60u Clock Sec Ou Clock Min if Clock Min gt 60u In its default setting the trace will record every line of code executed In a real application this will fill the trace buffer with many lines of code that are of no interest to us lots of while statements from a delay loop for example Therefore it is very important to be able to filter the trace buffer so only selected functions are recorded into the trace This is also very useful for timing analysis Often we are only interested in the behaviour of an interrupt routine so it is useful to exclude all the background code from the trace in order to easily analyse the interrupt behaviour Please open with the trace context menu the filter dialog clock with right mouse button into the trace window and select Filter The trace control dialog is now open We now drag the function isr_TIMERO and drop it into the trace control dialog Hitex UK Ltd Page 202
164. lows immediately after the vector table This means that the complete vector table takes the first 64 bytes of memory The Keil startup code contains predefined names for the Interrupt Service Routines ISR You can link your ISR functions to each interrupt vector by using the same name as your C function name The table below shows the constants table symbols and the corresponding C function prototypes which should be used Exception source Constants table C function prototype Undefined Instruction Undef Handler A void Undef Handler void abort Prefetch Abort PAbt Handler A void Pabt Handler void abort Data Abort DAbt Handler A void Dabt Handler void abort Fast Interrupt FIQ Handler A void FIQ Handler void ti The SWI and IRQ exceptions are special cases as we will see later The A is used to tell the linker that the corresponding function should be compiled with the ARM instruction set T is used for the THUMB instruction set Only the IRQ and FIQ interrupt sources can be disabled The protection exceptions Undefined instruction Prefetch Abort and Data abort are always enabled Consequently these exceptions must always be trapped If you do not declare a corresponding C function for these interrupt sources then the compiler will default to using a tight loop to trap any entry to these exceptions Default handling of exceptions Pabt_Handler B Pabt Handler Branch self for which no C function has been declared Exercise 5
165. ltaneously the CAN controller will use internal arbitration to decide which is transmitted first This can be done in one of two ways if the TPM bit in the MODE register is Zero the transmit buffer with the lowest value identifier will be sent first If TPM is high then arbitration will use the values stored in the PRIO field in the Tx Frame Information register and the buffer with the lowest PRIO value is sent first Once the buffer has been filled with a message transmission can be started by setting the Transmit request bit TR in the COMMAND register The code below shows some code fragments to initialise the CAN peripheral and transmit a message C2MOD 0x00000001 C2BTR 0x001C001D C2MOD 0x00000000 if C2SR amp 0x00000004 Set CAN controller into reset Set bit timing to 125k Release CAN controller See if Tx Buffer 1 is free C2TFI1 0x00040000 Set DLC to 4 bytes C2TID1 0x00000022 Set address to 0x22 Standard Frame C2TDA1 NetworkData Copy some data into first four bytes C2CMR 0x00000001 Transmit the message Exercise 25 CAN Transmit This exercise configures the second CAN channel for 125K bits second and repeatedly transmits a CAN message frame Hitex UK Ltd Page 109 hitex 4 User Peripherals DEVELOPMENT TOOLS 4 12 7 CAN Error Containment The CAN protocol has five methods of error containment built into the silicon If any error is detected it will
166. med In addition to the JTAG connector the LPC2000 devices have a second debug port called the Embedded Trace Module ETM With this ETM connection an external Trace tool can record the execution of the microcontroller and the trace recording can be displayed in the HiTOP IDE as high level language lines executed instructions or as executed cycles The ETM also allows tracing a data flow within the application READs and WRITEs to RAM and SFR s can be recorded in the trace buffer for later analysis A basic JTAG cannot access the ETM information so a more complex system called Tanto is used The features of this System are discussed in the exercises section but one big advantage is that both the Tantino and Tanto use the same HiTOP IDE A CASE tool called StartEasy is supplied with the Hitex tools that allows you to define a LPC2000 project and generate a project skeleton containing the startup code and initialisation functions for the peripherals you are going to use Even if you are not using the Hitex tools you can download the full version of StartEasy from the Hitex website 2 2 3 Tutorial Included with this book is a demonstration version of the Keil uVision IDE The installation comes with two compilers the Keil ARM compiler and the GNU tools The tutorial section talks you through example programs illustrating the major features of the LPC2000 These examples can be run on the simulator or if you have a starter kit from Hitex or Keil they
167. miliar with its layout and how the VIC is configured Wertored Internupt Controller VIC 5 y T i B in 4 EX IRQ QU u 10 SPI IRQ Coie LES i ih Each VIC slot is shown 11 5P11 IRG OOODODOOH here LE PLL Lock PLOCK IRU LMH 1 1 WIL 14 Lester intesut IAG UDOQUUOUCH u Th TON ETT OHOO O H 1 16 Leena ines LNTZ IAG COCO Selected Intermapt 1 FF innsbe usen D 000001 20 Details of the selected slot elei F Flan are shown here EEEN elect i vAr VicSamine 0 00000000 CAE nabia ORGHAN 0000000 Global registers are Wisiri 0000000 ME ON OO shown here In the simulator use the cycle counter in the register window calculate how long the device takes to enter to the first line of your code in the interrupt routine Hitex UK Ltd Page 151 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 16 Exercise 13 Non Vectored Interrupt In this exercise we will use the Vector interrupt unit to generate the slowest form of interrupt response a non vectored interrupt We will use External interrupt one EINT1 to generate an interrupt The VIC will respond to this interrupt event by providing the address of a general purpose ISR for the processor to jump to On entry to this routine the ISR must calculate the source of the interrupt take appr
168. minant In this case it will back off the bus and start listening Node A and C will continue transmission until node C write recessive and node writes dominant Now node C stops transmission and starts listening Now node A has won the bus and will send its message Once A has finished nodes B and C will transmit and node C will win and send its message Finally node B will send its message If node A is scheduled again it will win the bus even though the node B and C messages have been waiting In practice the CAN bus will transmit the message with the lowest value identifier Hitex UK Ltd Page 105 hitex mum 4 User Peripherals DEVELOPMENT TOOLS 4 12 5 Bit Timing Unlike many other serial protocols the CAN bit rate is not just defined by a Baud rate prescaler The CAN peripheral contains a Baud rate prescaler but it is used to generate a time quanta i e a time slice A number of these time quanta are added together to get the overall bit timing The bit period is split into three segments First is the sync segment which is fixed at one time quanta long The next two segments are Tseg1 and Tseg2 where the user defines the number of time quanta in each region The minimum number of time quanta in a bit period is 8 and the maximum is 25 The receiving sample point is at the CAN bit timing Unlike other serial protocols the CAN bit period is constructed as a number of segments that allow you to tune the CAN data 1 Bit Time
169. mmon physical layer is a twisted pair and standard line drivers are available The other layers in the IOS model are effectively empty and the application code directly addresses the registers of the CAN peripheral In effect the CAN peripheral can be used as a glorified UART without the need for an expensive and complex protocol stack Since CAN is also used in Industrial Automation there are a number of software standards that define how the CAN messages are used to transfer data between different manufacturers equipment The most popular of these application layer standards are CANopen and Device net The sole purpose of these standards is to provide interoperability between different OEM equipment If you are developing your own closed system you do not need these application layer protocols and are free to implement you own proprietary protocol which is what most people do 4 12 2 CAN Node Design A typical CAN node is shown below Each node consists of a microcontroller and a separate CAN controller The CAN controller may as in the case of the LPC2000 be fabricated on the same silicon as the microcontroller or it may be a stand alone controller in a separate chip to the microcontroller The CAN controller is interfaced to the twisted pair by a line driver and the twisted pair is terminated at either end by a 120 Ohm resistor The most common mistake with a first CAN network is to forget the terminating resistors and then nothing works Hite
170. mory mode When selected a new vector table will be mapped into the first 64 bytes of memory So for the RAM mode the contents of 0x4000000 0x400003F will be mapped to the start of memory This allows a program to be loaded into RAM starting at 0x4000000 and the vector table can then be redirected thus allowing the program and its interrupts to run in RAM This mode is normally only used for debugging small programs FLASH mode leaves the first 64 bytes of user FLASH unchanged and is the normal mode for user applications Boot mode replaces the first 64 bytes of FLASH with the vector table for the bootloader and places a jump to the on chip bootloader on the reset vector The MEMMAP register maps the first 64 bytes of memory from one of four regions Hitex UK Ltd Page 45 hitex mms 3 System Peripherals DEVELOPMENT TOOLS 3 6 2 Bootloader Every time the LPC2000 comes out of reset its memory map will be in boot mode so the instruction on the reset vector will cause it to jump into the bootloader code entry point at Ox7FFFFFFF This can be the bane of new users if they load their code into FLASH with a JTAG reset and single step the first instruction only to find that the program counter is at some wild high address If this happens you need to program the MEMMAP register to 0x00000002 to force the chip into FLASH mode and return the user vector table Once the bootloader code has been entered it will perform a number of checks to
171. n also be replaced by a JTAG debugger and the same front end can be used to debug real hardware Hitex UK Ltd Page 129 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 4 Using The ULINK Hardware Debugger The JTAG debugger included with the starter kit is the Keil ULINK This connects to the JTAG port on MCB2100 P5 and then connects to the PC via USB To switch from using the simulator to using the ULINK follow the steps below 5 4 1 Setting up the ULINK JTAG hardware debugger Connect the ULINK to the MCB2100 as shown below and plug the USB connection into the PC Power should also be connected to the MCB2100 6 5V EST _ A0 L JE j 3 e LA Z ULINK Configure UVISION to use the ULINK in place of the simulator First open the utilities menu in the Options for target dialogue Select the use target device for Flash programming radio button and select the ULINK ARM7 debugger from the drop down menu Also tick the update target before debugging box SS UU Hs Bone Fuge Lo nmm Lehm inten ser Cam tga D Maio T email EE UL I LI iam bare 8 iee LE La T dus mera les Frog apa Hitex UK Ltd 130 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Configure the flash algorithm Next click the setting button Set the start address for the
172. n codes If it is set the condition codes are modified depending on the result of the instruction If it is clear no update is made If however the PC R15 is specified as the result register and the S flag is set this will cause the SPSR of the current mode to be copied to the CPSR This is used at the end of an exception to restore the PC and switch back to the original mode Do not try this when you are in the USER mode as there is no SPSR and the result would be unpredictable Mnemonic Meaning AND ogical bitwise AND EOR Logical bitwise exclusive OR SUB Subtract RSB Reverse Subtract ADD Add ADC Add with carry SBC Subtract with carry RSC Reverse Subtract with carry TST Test TEQ Test Equivalence CMP Compare CMN Compare negated ORR Logical bitwise OR MOV Move BIC Bit clear MVN Move negated These features give us a rich set of data processing instructions which can be used to build very efficiently coded programs or to give a compiler designer nightmares An example of a typical ARM instruction is shown below if 7 1 R1 R2 R3x4 Can be compiled to EQADDS R1 R2 R3 LSL 2 Hitex UK Ltd Page 18 1 The ARM7 CPU Core 1 6 2 1 Copying Registers hitex mum DEVELOPMENT TOOLS The next group of instructions are the data transfer instructions The ARM7 CPU has load and store register instructions that can move signed and unsigned Word Half Word and Byte quantities to and from a sel
173. n hyper terminal If you are using the simulator select view serial window 1 This opens a terminal window within the simulator which displays the UARTO output Hitex UK Ltd Page 182 WELOPMENT TOOLS 6 Keil Tutorial With GNU Tools 6 11 Exercise 5 Simple Interrupt In this exercise we will setup a basic FIQ interrupt and see it serviced Open the project in EX5 Interrupt work In main c complete the definition of the EXTintFIQ function prototype to define it as the FIQ interrupt service routine void EXTintFIQ void __attribute__ interrupt FIQ In startup s complete the vector constants table to define EXTintFIQ as the FIQ ISR global EXTintFIQ Declare the name of the C ISR function as a global global _startup fune Startup _startup Vectors LDR PC Reset_Addr LDR PC Undef_Addr LDR PC SWI_Addr LDR PC PAbt_Addr Vector Table LDR PC DAbt_Addr long 0xB8A06F58 LDR PC PC OxFFO LDR PC FIQ Addr Reset_Addr word Reset_Handler Undef_Addr word Undef Handler SWI Addr word SWI Handler Constants table PAbt Addr word PAbt Handler DAbt Addr word DAbt Handler word 0 IRQ Addr word IRQ Handler FIQ Addr word EXTintFIQ Insert the name of the C ISR function in the constants table Compile the code and download it onto the board Step through the code and observe the following using the disassembly window and the registers window Step through the code until you reach the
174. n the Keil compiler is demonstrated in this example You can easily partition code to run in either the user mode or in supervisor mode 2 8 Locating Code In RAM As we shall see later the main performance bottleneck for the ARM7 CPU is fetching the instructions to execute from the FLASH memory The LPC2000 has special hardware to solve this problem for the on chip FLASH However if you are running from external FLASH you are stuck with the access time of the external FLASH One trick is to boot the executable code into fast RAM and then run from this RAM This means that you need to compile position independent code which can be copied into the RAM or compile code so that it runs in the RAM and is loaded by a separate bootloader program Both of these solutions will work but require extra effort to develop Fortunately the Keil compiler has a directive which defines a function as a RAM function The startup code will copy the function into RAM and the linker will resolve all calls to it as being located in the defined RAM area The function declaration is shown below int RAM FUNCTION int my VAR ram It is also necessary to define which section of memory will be used to hold these functions This is done by declaring a section of the RAM as executable RAM or ERAM This declaration makes use of the classes directive to allocate a region of RAM to contain all the executable RAM functions Hitex UK Ltd Page 34 hitex mum 2
175. n which be enabled via the pin connect block The Capture control register can configure if a rising or falling edge or both on this pin will trigger a capture event When the capture event occurs the current value in the timer counter will be transferred into the associated capture register and if necessary an interrupt can be generated The code below demonstrates how to configure a capture channel This example sets up a capture event on a rising edge on pin 0 2 Capture 0 0 and generates an interrupt Hitex UK Ltd Page 74 4 User Peripherals int main void hitex mum DEVELOPMENT TOOLS VPBDIV 0x00000002 Set pclk to 30 MHz PINSELO 0x00000020 Enable pin 0 2 as capture 10 TOPR 0x00007530 Load prescaler for 1 Msec tick OTCR 0x00000002 Reset counter and prescaler TOCCR 0x00000005 Capture on rising edge of 10 OTCR 0x00000001 enable timer VICVectAddr4 unsigned TOisr Set the timer ISR vector address VICVectCntl4 0x00000024 Set channel VICIntEnable 0x00000010 Enable the interrupt while 1 void TOisr void __irq static int value value TOCRO read the capture value TOIR 0x00000001 Clear match 0 interrupt VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 16 Timer Capture This exercise configures a general purpose timer with a capture event to measure the w
176. natructeon beige memory abcrti Aboi Ooi 0x00000014 Cea Abort diate access memory abort Abort 10 harpe IR FIC cat DONC Hitex UK Ltd Page 12 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS NB There is a gap in the vector table because there is a missing vector at 0x00000014 This location was used on an earlier ARM architecture and has been preserved on ARM7 to ensure software compatibility between different ARM architectures However in the LPC2000 family these four bytes are used for a very special purpose as we shall see later Each of the exception sources has a fixed priority The on chip peripherals are served by FIQ and IRQ interrupts Each peripheral s priority may be assigned om Under meian Swi If multiple exceptions occur then there is a fixed priority as shown below When an exception occurs for example an IRQ exception the following actions are taken First the address of the next instruction to be executed PC 4 is saved into the link register Then the CPSR is copied into the SPSR of the exception mode that is about to be entered i e SPSR_irq The PC is then filled with the address of the exception mode interrupt vector In the case of the IRQ mode this is 0x00000018 At the same time the mode is changed to IRQ mode which causes R13 and R14 to be replaced by the IRQ R13 and R14 registers On entry to the IRQ mode the bit in the CPSR is set c
177. nd observe the results in the Peripherals PLL window This will show the true bus frequency Sa a j _ Ruen foo FPE _ s LE __ PUSTAT oM T E ex E E ALE fe PUE Aiten fo b Processor Clee MIAL 12000000 Cubo M MHz Procesos Clock OCLC Configuration of the PLL can be done via the Keil startup code but for this exercise this code is disabled The equivalent settings for the startup code are shown below Stack Configuration Stack Sizes in Bytes VPBDIV Setup M TE MSEL PLL Multiplier Selection 5 PSEL PLL Divider Selection 2 MAM Setup External Memory Controller EMC Hitex UK Ltd Page 149 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 14 Exercise 11 Fast Interrupt In this exercise we will configure an the external interrupt to be handled as an FIQ This code was used in exercise 5 to show the C handling of an interrupt function This time we will see how to configure the hardware for an FIQ interrupt Open the project in EX12 Interrupt vectored work Configure the external interrupt as an FIQ by programming the IntSelect register VICIntSelect 0x00008000 Compile the code and start the debugger and check the interrupt works as in exercise 5 The name of the FIQ ISR must match the name in the vector constant table in sta
178. nnected to Chipselect 0 and the RAM is connected to Chipselect 1 The schematic for each Chipselect is shown below Hitex UK Ltd Page 49 hitex mum 3 System Peripherals DEVELOPMENT TOOLS A2 25 26 Di A3 19 20 20 baa DT A4 Ad 13 E27 RA CEE D2 4s DIVA A6 T m 03 18 024 AT 20 D4 8 bi A AF M fe 56 17 077 A 2 25 074 AD 0 D8 322 03 ATS 09 D Al2 17 Als 23 M 010 P39 Dr VDD V3V3 Ald 12 ae Em AIS 6 431 537 Ale 38 KM R30 7 JR301 A AIS DISA 10k 10k AD 8 A16 9 A17 WP ACC A20 15 A18 NC 16 22 19 2 21 A20 4 37 10 NE 4 oe CSF031 40 VCC fVDD_V3V3 10 ESET mag RESET 3 BYTE Hi nx GND 29LV320DT 90WMI GND 29LV320DT 90WMI GND RESET 1 J300 P017 1 gp 4 4 JIX2 137 default open Two of the 29LV320DT devices are arranged as 16 bit wide memories to give a 2M page of 32 bit wide FLASH memory The byte pin is pulled high on each device to enable the 16 bit mode The FLASH device is designed to be a boot sector device and consequently has an option to protect the top and bottom sectors so that they cannot be corrupted This feature is enabled by pulling the WP ACC pin low Since we do not want this feature the pin is pulled high allowing us to reprogram any sector of the FLASH memory We are also not using the Ready Busy output so this is also tied high The remaining contr
179. nt pragma ARM Switch to ARM instructions int main void while 1 THUMB_function Call THUMB function pragma THUMB Switch to THUMB instructions void THUMB function void unsigned long i delay for i 0x00010000 i lt 0x01000000 i i lt lt 1 for delay 0 delay lt 0x000100000 delay hitex mm DEVELOPMENT TOOLS LED FLASHer simple delay loop 1 i Set the next led It is also possible to declare individual functions as either ARM or THUMB functions by using the following declarations on the function prototype int ARM FUNCTION int my var THUMB int THUMB FUNCTION int my var _ THUMB Exercise 3 Interworking The next exercise demonstrates setting up a project which interworks ARM and THUMB code Hitex UK Ltd Page 31 hitex mm 2 Software Development DEVELOPMENT TOOLS 2 5 STDIO Libraries The high level formatted IO functions in the STDIO library such as printf and scanf are directed at UARTO on the LPC2000 It is up to the programmer to initialise the UART to the correct BAUD rate Once this is done it is possible to use these high level functions to stream data to a terminal program on a PC for example The STDIO functions use two low level drivers to send and receive a single character to the conio the UART in this case The two functions are called putchar and getchar and the source for them is available in
180. nto the TANTO trace buffer and then how to evaluate it Please start the application by selecting Debug Go Until and enter the function convert clock Now open the trace window menu view trace The default settings will display the executed code as assembly instructions Hitex UK Ltd Page 200 8 Extended Debugging With ETM Trace hitex mum DEVELOPMENT TOOLS Program address Data External Lines Frame Addless State Datal Instruction Exterhal Time 2 63 0 20 98FFAFEB bl inc clock 3 62 0 BRAD 3 58 0 inc Wick ES idr r2 pc c4h 46ch 3 0 22 us 56 0 0 00000344 CO309FES Idr r3 pe cOh 46ch 3 0 15 us 54 0 Ox000003A8 BO30D3E1 r3 r3 00h 3 0 15 us 53 0 Ox0000034C 053083 2 add r3 r3 5h 3 52 0 0 000003 0 2 1 strh r3 r2 00h 3 0 11 us 50 0 106 BO3O9FES Idr r3 pc bOh 46ch 3 0 16 ps 48 0 Ox000003B8 02003 1 Idrh r2 r3 00h 3 0 20 ps 46 0 Ox000003BC F93FADE3 mov r3 3e h 3 0 06 us 44 0 0x000003C0 033083E2 add r3 r3 3h 3 0 06 us 42 0 0x000003C4 030052 1 r2 r3 3 0 07 us 41 0 0 000003 8 26000094 bls 125 3 40 0 BRAD 3 36 0 125 1EFF2FE1 bx Ir 3 0 05 us 35 0 BRAD 3 32 0 209 B4309FE5 Idr r3 pc b4h 5f8h 3 0 42 us 30 0 Ox00000540 BO10D3E1 ldrh r1 r3 00h 3 0 11 us 28 0 0 00000544 B0309FES Idr r3 pc b0h Sfch 3 0 06 us 26 0 0 00000548 912383E0 umull r2 r3 r1 r3 3 0 36 us 24 0 0 0000054 A322A0E1 mov
181. o the network by sending a message packet which contains no data but has the RTR bit set The remote frame is requesting a message packet to be transmitted with a matching identifier On receiving a remote frame the node which generates the matching message will transmit the corresponding message frame Remote Transmit request The RTR frame Identifier CRC EOF is used to request message packets from the network as a master slave transaction uou Hitex UK Ltd Page 103 4 User Peripherals hitex mum DEVELOPMENT TOOLS As previously mentioned the CAN message identifier can be up to 29 bits long There are two standards of CAN protocol the only difference being the length of the message identifier 2 0A Has an 11 bit identifier 2 0B Passive Has an 11 bit identifier 2 0B Active Has a 29 bit identifier It is possible to mix the two protocol standards on the same bus but you must not send a 29 bit message to an 2 0A device Frame with Frame with 11 bit ID 29 bit ID V2 0B Active uM Tx Rx OK Tx Rx OK CAN Module m ad V2 0B Passive CAN Module Tx Rx OK Ignored V2 0A CAN i Modile Tx Rx OR Bus ERROR Hitex UK Ltd Page 104 hitex DEVELOPMENT TOOLS 4 User Peripherals 4 12 4 CAN Bus Arbitration If a message is scheduled to be transmitted on to the bus and the bus is idle it will be transmitted and may be picked up by any interested no
182. oad Register instruction is used This loads a constant from a table stored immediately above the vector table The vector table and the constants table take up the first 64 bytes of memory On the LPC2000 this first 64 bytes can be mapped from several sources depending on the operating mode of the L PC2000 This is discussed more fully later on The NOP instruction is used to pad out the vector table at location 0x00000014 which is the location of the missing vector Again this location is used by the LPC2000 bootloader discussed again later You are responsible for managing the vector table in the startup code as it is not done automatically by the compiler Hitex UK Ltd Page 28 2 Software Development The startup code is also responsible for configuring the stack hitex mm DEVELOPMENT TOOLS pointers for each of the operating modes Setup Stack for each mode LDR RO Top_Stack Enter Undefined Instruction Mode and set its Stack Pointer Switch mode and disable interrupts p Load address into the stack pointer p Calculate start address of next stack o MSR CPSR c Mode Bit F Bit MOV SP RO SUB RO UND Stack Size Enter Abort Mode and set its Stack Pointer MSR CPSR Bit MOV 8 SUB Stack Size FIQ and supervisor stacks Enter User Mode and set its Stack Pointer Finally switch to USER mode and gt enable
183. oan TUBR 158011 cer eno H2 E KOFIGIGUGA EFTO KGFIGIGUGA ETF7O lh GND GND RESET Finally the boot pins D26 and D27 must be pulled low if we want to boot from the external device Hitex UK Ltd Page 51 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 7 2 Using The External Bus Interface Each chipselect has a fixed address range and has a dedicated bus configuration register BCFGO BCFG3 The address range of each chipselect is shown below 8000 0000 80FFF FFFF 8100 0000 81FFF FFFF 8200 0000 82FFF FFFF 8300 0000 83FFF FFFF In our hardware example above we have mapped the FLASH onto chip select 0 at 0x80000000 and the ram onto chipselect 1 at 0x81000000 Before we can use the external memory we must setup the chipselect configuration registers AT MN EM WP WP ERA BUSS ERR WET WEST mcr IDEY Controls the number of idle eveles between read and write operati ns Wall Controls the length or read accesses 0 for byte wide devices drives BLS signals high for 16 32 bat devices drives BLS signals bow WST2 Controls the length of write accesses WPERR Set if software attempts to write to a memory bank WP Write protect once set write protects n bank BM Enables memory bank as Burst NW Defines the width of the data bus AT BUSS ERR ERR Not used Each of the chipselects in use must be programmed with the correct parameters to match the external device
184. of recently referenced main memory In a well designed cache the processor will use the cache memory whenever possible thus reducing the bottleneck imposed by slow memory However a full cache is a complex peripheral that demands Hitex UK Ltd Page 41 hitex mm 3 System Peripherals DEVELOPMENT TOOLS a high number of gates and consequently a large portion of the LPC2000 die area This flies in the face of the ARM7 design which has simplicity as its watchword Another downside of a full cache is that the runtime of code using the cache is no longer deterministic and could not be used by any application that required predictability and repeatability The Memory Accelerator Module is a compromise between the complexity of a full cache and the simplicity of allowing the processor to directly access the FLASH memory Bari Gi Bank 1 The FLASH memory is arranged as two 128 interleaved banks of 128 bit wide memory One flash access from the MAM loads four ARM instructions or eight THUMB instructions which be executed by the ARM7 CPU Like a cache the MAM attempts to have the next ARM instruction in its local memory in time for the CPU to execute First of all the FLASH memory is split into two banks which are 128 bits wide and can be independently accessed This means that a single FLASH access can load four ARM instructions or eight THUMB instructions User code is interleaved between the two banks so during s
185. of the PLL can be monitored by reading the LOCK bit in the PLLSTATUS register Once the lock bit is set the PLL can be used as the main clock source Alternatively an interrupt can be generated when the PLL locks so that you can carry out other tasks while the PLL starts Once the PLL has locked as a stable clock source it can replace the external oscillator as the source for Cclk This is done via the PLLC bit in the PLLCON register The PLL setup sequence is performed by the Keil compiler startup code and you just need to provide values for M and P An interrupt is also generated when the PLL locks This can be used to replace the polling of the lock bit to achieve maximum startup performance F i J ts PLL Locked Care should be taken with the values stored for the constants in the PLLCFG register The values written to the register for the constants are P 1 and M 1 which ensures that the values of P and M in the PLL are never zero Also the value for M is 5 bits long so the value for P is not on an even nibble boundary If you make a simple mistake setting up the PLL the whole chip may be running out of specification If the chip enters power down mode the PLL is switched off and disconnected A wakeup from power down does not restore the PLL so the sme startup sequence must be followed each time the chip exits the power down setting Hitex UK Ltd Page 57 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 3 10
186. oid __irg EXTINT 2 Clear EINT1 interrupt flag IENABLE allow nested interrupts IOSET1 0x00010000 Switch on an LED delay 0x500000 wait a long time IOCLR1 0x00010000 Switch off the LED IDISABLE disable interrupt nesting VICVectAddr 0 Acknowledge Interrupt Build the project and download it to the debugger If you are using the MCB2100 run the code at full speed One LED will flash for the period it is in the timer interrupt Press the INT1 button and the second led will illuminate for the longer period it is in the External interrupt routine However the timer led will continue to flash because the interrupt is not blocked If you are using the simulator the same behaviour can be observed using the logic analyser Remove the IDISABLE and IENABLE macros and observe the new behaviour Hitex UK Ltd Page 153 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 18 Exercise 15 General Purpose IO Pins In this exercise we will use the GPIO pins A group of pins will be set as outputs and then each will be flashed sequentially Open the project in EX12 GPIO work Add the include file for the LPC21xx SFR s include lt LPC21xx H gt Program the data direction register to enable pins 1 16 1 23 as output IODIR1 0x00FF0000 Complete the ChangeGPlOPinState function to clear and set the relevant pins IOCLR1 state IOSET1 state Compile the code and download it into the d
187. ol signals reset Output enable OE Write Enable WE and Chip Enable are connected directly to the processor As the memory is to be arranged word wide 32 bits we need to be able to address it every quad bytes hence AO and A1 are not used If it is necessary to add more memory onto this chipselect the 29LV320 can be replaced with a XXX to give a 4M page of word wide memory To access the full 16 Mbyte address range a duplicate pair of devices can be added and the chipselect gated with A23 to provide a chipselect for each half of the memory page Hitex UK Ltd Page 50 hitex mum 3 System Peripherals DEVELOPMENT TOOLS 0x81000000 CS0 A23 Four devices with 2 M x16 bit can be arranged as a linear 4M x 32 bit address space The address line A23 0x80800000 and CS0 are used to decode between the two different banks 50 A23 0 80000000 The RAM is interfaced to the address bus in a similar fashion using Chipselect1 except the devices 1 Mbyte in size so we are using A2 to A21 Further devices can be mapped in by multiplexing A22 and A23 with the chipselect line As this is a RAM device and we may want to access it word half word or byte wide we can use the byte lane pins to allow access to the upper and lower bytes in each device BLSO 1400 13402 misi am BLS2 HLBR Nc 48 N JIX3A 25 UB vec VCCRAM OE 10012 BLS VCC 777 default 142
188. one given consumer node on the network In the message packet the RTR bit is always set to zero This field will be discussed shortly The DLC field is the data length code and contains an integer between 0 and 8 which indicates the number of data bytes being sent in this message packet So although you can send a maximum of 8 bytes in the message payload it is possible to truncate the message packet in order to save bandwidth on the CAN bus After the 8 bytes of data there is a 15 bit cyclic redundancy check This provides error detection and correction from the start of frame up to the beginning of the CRC field After the CRC there is an acknowledge slot The transmitting node expects the receiving nodes to assert an acknowledge in this slot within the transmitting CAN packet In practice the transmitter sends a recessive bit and any node which has received the CAN message up to this point will assert a dominant bit on the bus thus generating the acknowledge This means that the transmitter will be happy if just one node acknowledges its message or if 100 nodes generate the acknowledge So when developing your application layer care must be taken to treat the acknowledge as a weak acknowledge rather than confirmation that the message has reached all its destination nodes After the acknowledge slot there is an end of frame message delimiter It is also possible to operate the CAN bus in a master slave mode A CAN node may make a remote request ont
189. onfigurations Firstly the polarity and phase of the clock must be defined The polarity can be active high or active low as shown below and the clock phase can be edge or centre aligned Hitex UK Ltd Page 95 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS Finally the data orientation may also be defined as the most significant bit transferred first or the least significant bit transferred first LS 7 LJ LJ Corn Finger M LSB 5 data transmission can be 74 configured to match the characteristics of SPI device 1 LEBF cem MSH LSB r _ PET Each of these configuration features has a configuration bit in the control register and you must program these bits to match the SPI peripheral you are trying to communicate with Once the bit rate has been set and the control register configured then communication can begin To communicate with the SPI memory shown above first set the GPIO pin to enable the memory for communication Then writing to the SPI data register will send a byte of data and reading from the register will collect any data sent from the external peripheral The actual data format used in the transaction will depend on the SPI device you are trying to communicate with Exercise 22 SPI This exercise demonstrates how to configure the SPI peripheral and communicate with an external EEROM on the SPI bus Hitex UK Ltd
190. onfigured the on line documentation can be accessed through the Books tab in the project workspace window The full Keil documentation for uVision and the CARM compiler is found under Complete Users Guide Selection Project Workspace MES E td Tools User s Guide e Release Notes e Complete User s Guide Selection gt GNU C Compiler GNU C Run Time Libraries gt GNU C Utilities GNU C Assembler E td Device Data Books User Manual Once you have added the datasheet click the OK button to continue defining the project Hitex UK Ltd Page 121 hitex ms 5 Tutorial With Keil Tools DEVELOPMENT TOOLS From the menu bar select Project new Project In the new project dialog name the project first uv2 and select Save A select new device for target dialog will appear Navigate through the device database and select the Philips LPC2129 folder and then OK Hitex UK Ltd Page 122 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS In the project browser highlight the Target1 root folder and select the local menu by pressing the right mouse button In this menu select options for target Options For Target Target 1 Translate Fle top Build Files to Groupi Remove lten In the Target tab set the simulation frequency to 12 000 MHz Also make sure the Use on chip Rom and Use On chip Ram boxes are ticked In the LA
191. ons MOV ADD CMP The THUMB instruction set does not contain MSR and MRS instructions so you can only indirectly affect the CPSR and SPSR If you need to modify any user bits in the CPSR you must change to ARM mode You can Hitex UK Ltd Page 23 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS change modes by using the BX and BLX instructions Also when you come out of RESET or enter an exception mode you will automatically change to ARM mode Roset p a exception LER end ol expephonm Bx The THUMB instruction set has the more traditional PUSH and POP instructions for stack manipulation They implement a fully descending stack hardwired to R13 BLY Push Hio Por Pop Mo An R Rz The THUMB instruction set has dedicated PUSH and POP instructions which implement a descending stack using R13 as a stack pointer Finally the THUMB instruction set does contain a SWI instruction which works in the same way as in the ARM instruction set but it only contains 8 unused bits to give a maximum of 255 SWI calls Hitex UK Ltd Page 24 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 12 Summary At the end of this chapter you should have a basic understanding of the ARM7 CPU Please see the bibliography for a list of books that address the ARM7 in more detail Also included on the CD is a copy of the ARM7 user manual Hitex UK Ltd Page 25 hitex mum 2
192. ooner or later you will need to take some inputs from the real world This can be done to a certain extent with the simulator scripting language but eventually you will need to run your code on the real target The simulator front end can be connected to your hardware by the Keil ULINK interface The ULINK interface connects to the PC via USB and connects to the development hardware by the LPC2000 JTAG interface The JTAG interface is a separate peripheral on the ARM7 which supports debug commands from a host By using the JTAG you can use the uVision simulator to have basic run control of the LPC2000 device The JTAG allows you to download code onto the target to single step run code at full speed to set breakpoints and view memory locations 2 2 2 HiTOP IDE HiTOP supports several different debug tools You can test generic ARM7 code with the instruction set simulator and for standard debugger functions in the real hardware the Tantino system can be used Unlike the Keil ULINK the Tantino supports ARM9 and ARM11 in addition to ARM If you are working with large images it also has a shorter download time when programming FLASH and there are some more sophisticated debugging functions such as being able to set and clear breakpoints on the fly The Tantino is connected via USB to the HiTOP IDE and to the LPC2000 microcontroller through a JTAG connector Download FLASH programming and the basic run control of the LPC2000 device can be perfor
193. ootloader which allows your code to be downloaded via UART 0 into RAM and then be programmed into the FLASH It is also possible to use a JTAG development tool to program the memory This is useful during development because it can be done from the debugging environment without the need to keep switching between debugger and bootloader Also the JTAG connection can be very fast up to 400Kbytes sec download so in large applications particularly those using external FLASH memory it can be the best method of production programming Finally it is also possible to reprogram sections of the FLASH memory under command of the application already on the chip This in application programming can use any method to load the new code onto the chip SPI CAN 12 and then load it into a given section of FLASH So there is an easy to use mechanism which allows field updates to your application 3 6 1 Memory Map Control Before looking at the operation of the bootloader we must first understand the different memory modes available on the LPC2100 As we have seen the ARM7 interrupt vector table and its constants table take up the first 64 bytes of memory In the LPC2000 these first 64 bytes may be mapped from a number of locations depending on the mode set in the MEMMAP register It is important to note that these modes have nothing to do with the ARM7 operating modes The MEMMAP register allows you to select between boot mode FLASH mode RAM mode and External me
194. opriate action and then correctly exit the ISR and resume normal processing Open the project in EX9 Interrupt Non Vectored work In Startup s add the correct assembly code to the IRQ interrupt vector LDR PC PC OxFFO In main c configure the Pin Connect Block to enable P0 14 as an External interrupt PINSELO 0x20000000 Place the address of the NonVectored ISR into the Default vector address register Note in C this can be done as follows VICDefVectAddr unsigned lt Name of ISR routine gt Enable the External interrupt channel in the VIC VICIntEnable 0x8000 In the interrupt routine check the IRQ status register to find the source of the interrupt if VICIRQStatus amp 0x00008000 At the end of the ISR clear the interrupt flag in EINTO register and perform dummy write to the correct register in the VIC to clear the interrupt source EXTINT 0x00000002 VICVectAddr 0x00000000 Compile the code and start the debugger Run the code and check that the interrupt is entered correctly and that it only runs once for each press of the EINT1 button pin 0 14 If you are using the simulator open the GPIO Port 0 peripheral window The interrupt can be triggered by bringing pin 0 14 low Alternatively open the toolbox and use the Generate EINT1 button In the simulator use the cycle counter in the register window calculate how long the device takes to enter to the first line of your code in the interrupt routine
195. or a simple project use the GNU Since we are writing code for a small single chip microcontroller with limited on chip resources the obvious choice for us is the Keil ARM compiler When deciding on a toolset it is also important to examine how much support is given to a specific ARM7 Hitex UK Ltd Page 26 hitex mm 2 Software Development DEVELOPMENT TOOLS implementation Although a toolset may generate code for an ARMT it may not understand how the ARM7 is being used in a specific system i e LPC2000 Using a ARM7 will generate code which will run on the LPC2000 but you will have to spend time writing the start up code and struggle with a debugger which will not understand the LPC peripherals This can lead to fighting the development tools which needless to say can be very frustrating 2 2 1 uVision IDE uVision also includes two debug tools Once the code has been compiled and linked it can be loaded into the uVision simulator This debugger simulates the ARM7 core and peripherals of the supported micro Using the simulator is a very good way of becoming familiar with the LPC2000 devices Since the simulator gives cycle accurate simulation of the peripherals as well as the CPU it can be a very useful tool for verifying that the chip has been correctly initialised and that the correct values for things such as timer prescaler values have been calculated However the simulator can only take you so far and s
196. ou should be careful when programming these two bits because in order to disable either interrupt source the bit must be set to 1 not 0 as you might expect Bit 5 is the THUMB bit The ARM7 CPU is capable of executing two instruction sets the ARM instruction set which is 32 bits wide and the THUMB instruction set which is 16 bits wide Consequently the T bit reports which instruction set is being executed Your code should not try to set or clear this bit to switch between instruction sets We will see the correct entry mechanism a bit later The last five bits are the mode bits The ARM7 has seven different operating modes Your application code will normally run in the user mode with access to the register bank RO R15 and the CPSR as already discussed However in response to an exception such as an interrupt memory error or software interrupt instruction the processor will change modes When this happens the registers RO R12 and R15 remain the same but R13 LR and R14 SP are replaced by a new pair of registers unique to that mode This means that each mode has its own stack and link register In addition the fast interrupt mode FIQ has duplicate registers for R7 R12 This means that you can make a fast entry into an FIQ interrupt without the need to preserve registers onto the stack Hitex UK Ltd Page 11 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS Each of the modes except user mode has an additional regi
197. outines In addition to accessing the on chip peripherals your C code will have to service interrupt requests It is possible to convert a standard function into an ISR as shown below void fiqint void fiq IOSET1 0x00FF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag The keyword fiq defines the function as a fast interrupt request service routine and so will use the correct return mechanism Other types of interrupt are supported by the keywords _ IRQ SWI _ ABORT As well as declaring a C function as an interrupt routine you must link the interrupt vector to the function Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC PAbt Addr LDR PC DAbt Addr OP Reserved Vector LDR PC IRQ_Addr LDR PC PC Ox0FFO Vector from VicVectAddr LDR PC FIQ_Addr Reset_Addr DD Reset_Handler Undef_Addr DD Undef_Handler A SWI_Addr DD SWI_Handler A PAbt_Addr DD PAbt_Handler A DAbt_Addr DD DAbt_Handler A DD 0 Reserved Address IRQ Addr DD IRQ Handler A FIQ Addr DD FIO Handler A The vector table is in two parts First there is the physical vector table which has a Load Register Instruction LDR on each vector This loads the contents of a 32 bit wide memory location into the PC forcing a jump to any location within the processor s address space These values are held in the second half of the vector table or the constants table which fol
198. p v External Memory Controller EMC v Bank Configuration 0 BCFGO v IDCY Idle Cycles 1 WST1 Wait States 1 6 WST2 Wait States 2 0 RBLE Read Byte Lane Enable WP Write Protect Burst ROM E MW Memory Width 32 bit Bank Configuration 1 BCFG1 v IDCY Idle Cycles 1 WST1 Wait States 1 5 WST2 Wait States 2 5 RBLE Read Byte Lane Enable v WP Write Protect Burst ROM E MW Memory Width 32 bit f Bank Configuration 2 BCFG2 E Bank Configuration 3 BCFG3 Hitex UK Ltd Page 53 hitex mm 3 System Peripherals DEVELOPMENT TOOLS 3 8 Booting From ROM By default the LPC22xx devices will boot from their internal FLASH memory and can access the external memory once the chipselects are configured However if the external bootpins are pulled low the chip will boot from external memory In this case Chipselect zero will be enabled in the bus width selected by the boot pins Its waitstate parameters will default to 34 Cclk cycles for WST1 and WST2 and 16 Cclk cycles for the IDCY This ensures that the accesses on Chipselect zero will be slow enough to interface with any external device When booting from an external device is selected the value in the MEMMAP register will be set to 0x3 boot from external FLASH and the first 64 bytes of external memory on Chipselect 0 will appear at Zero This means that you must build your code so that the interrupt vector table and the constants table ar
199. r f5 Ua Tanp o TT Fe Lid atr a Catan ma iari opaabhrshesen a Ge Hmi et Vito acr E den swell Bash parii FF Toi F Brno B ff LER Face D bel tice Detain Dei CPU HL Parer Esrves DLL Fairer DLL pari DLL Ernie DEL Panier DLL Vener Select OK to complete the target options In the project browser expand the Target1 root node to show the Source group 1 folder EE Target 1 Source Group 1 Highlight the Source Group 1 folder open the local menu with a right click and select Add Files to group Source Group1 xl 5 59 Target 1 Source Group 1 Select Device for Target Target 1 Options For Group Source Group 1 Open File F7 Translate File Stop build Add Files to Group Source Group 1 Manage Components Remove Group Source Group 1 and it s Files lv Include Dependencies In the Add files to Group dialog add the file blinky c and serial c Hitex UK Ltd Page 177 hitex mm 6 Keil Tutorial With GNU Tools DEVELOPMENT TOOLS Mm S z Qa 04 Ti neis 73 ew Fim tie Ge Change the Type of file filter to ASM and add the file startup s These are all the source files necessary for
200. ransfer An external peripheral is selected by a slave select pin which is a separate pin Typically if the LPC2000 is acting in master mode it could use a GPIO pin to act as slave select chip enable for the desired SPI peripheral When the SPI peripheral is in slave mode it has its own slave select input which must be pulled low to allow an SPI master to communicate with it The two data transfer pins master in slave out and master out slave in are connected to the remote SPI device and their orientation depends on whether the device is operating in master or slave mode The diagram below shows a typical configuration for connecting to an EEROM device The programmers interface for the SPI peripheral has five registers The clock counter register determines the Baud rate Pclk is simply divided by the value in the clock counter to give the SPI bit rate This register must Le HH EE Euaad CET is diagram shows how to interface an external EEROM onto the SPI bus of the LPC2000 It NM should be noted that pins P0 7 and P0 20 must be pulled high to enable the SPI peripheral as a master AF Shaip Siana kee n hold a minimum value of eight The control register is used to configure the operation of the SPI bus Because of the simple nature of the SPI data transfer and the wide range of SPI peripherals available the SPI clock and data lines can be configured to operate in several different c
201. rbitrary value that is set by writing a value into the Error Warning limit register The default value in this register is 96 Like the bit timing registers the EWL register may only be modified when the CAN controller is in reset In addition the Interrupt Capture Register provides extensive diagnostics for managing events on the CAN bus Hitex UK Ltd Page 112 4 User Periphera Is hitex mum DEVELOPMENT TOOLS The CAN controller has the following interrupt sources Data overrun Wake up Bus error ID ready o NO BE D Error Passive Arbitration lost Transmit interrupt one for each buffer Receive interrupt Error Warning 4 12 8 CAN Message Reception Once initialised the CAN controller is able to receive messages into its receive buffer This is similar in layout to the transmit buffers CAN RFS CAN RID CAN ADA CAN RDB Reciever Frame Status Recieved Identifier Recieved Data 1 4 Recieved Data 5 8 The Rx Frame Status register is analogous to the Tx Frame information register However it has two additional values These are the ID Index and the BP bit and these will be explained in the next section The code below demonstrates how to receive a CAN message int main void VPBDIV 0x000 IODIR1 0x00F PINSEL1 0x00 C1MOD 0x0000 CIBTR 0x001C C1IER 0x00000 VICVectCntl0 VICVectAddrO 00001 F0000 040000 0001 001D 001 0x0000003A VICIntEnab
202. red interrupt sources are served by a single ISR The address of this ISR is stored in an additional vector address register called the default vector address register If an interrupt is enabled in the VIC and is not configured as an FIQ or does not have a vectored interrupt slot associated with it then it will act as a non vectored interrupt When such an interrupt is asserted the address in the default vector address is Hitex UK Ltd Page 67 hitex ame 3 System Peripherals DEVELOPMENT TOOL An loaded into the vector address register causing the processor to jump to this routine On entry the CPU must read the IRQ status register to see which of the non vectored interrupt sources has generated the exception Default Vector Address Exrepiien The non vectored interrupt has one vector address slot that will jump all non vectored interrupt sources to Vector Address one default ISR 3 12 9 Leaving A Non Vectored IRQ Interrupt As with the vectored IRQ interrupt you must clear the peripheral flag and write to the vector address register 3 12 9 1 Example Program Non Vectored Interrupt void main void IODIR1 0x000FF000 Set the LED pins as outputs PINSELO 0x20000000 Enable the EXTINTO interrupt VICDefVectAddr unsigned NonVectoredIRQ pass the address of the IRQ into the VIC slot VICIntEnable 0x8000 Enable EXTINTO in the VIC while 1 Vector
203. ress column and insert 0 you see the vector table with Idr pc instructions Only at address 0x14 there is a strange instruction Please remember that this is the reserved vector where the LPC controller assumes a correct checksum to indicate that there is a valid FLASH program and which causes the Memory Map Controller to switch to user flash mode This checksum is automatically inserted by StartEasy Hitex UK Ltd Page 194 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 6 Exercise 3 Using THUMB code In this example we add an additional module to the application which is compiled in THUMB mode We open start easy and open any of the previos projects With any editor we write a small new module like void func void this is a thumb function int i i 0 for i 100 i lt D i We save it into the directory of our StartEasy project tith the name module c To call this function from main we have to edit the main c file which was vreated by StartEasy Please open it with an editor and insert the declaration of this function and the call to this function In main c there are prepared sections to insert user code Go to the beginning of main and search for the section where user code includes can be made Here we insert the external declaration of func BEGIN USER CODE INCLUDE extern void func void END USER CODE INCLUDE
204. rnal Memory Interface The External Memory Interface of the LPC22xx devices is shown below BLS0 3 WE The data bus uses port 2 GPIO pins 2 0 2 31 and the address bus uses Port 3 GPIO pins 3 0 3 23 The remainder of port 3 is used for the Chipselects 1 3 the bytelane select pins and the write enable signal The remaining signal Chipselect 0 and output enable are on port 1 The two boot pins are multiplexed with the databus pins D26 and D27 Depending on the state of these pins at reset the LPC22xx variants can boot from internal FLASH or any width of memory connected to Chipselect zero The table below shows the states the pins should be held in to boot from a particular device These two pins are fitted with weak internal pull up resistors which ensure the device will boot from internal FLASH in its default condition The LPC22xx datasheet shows basic schematics for the most common memory interfacing options However 00 B Bit 01 16 Bit 10 32 Bit 11 Internal FLASH we will consider a practical example of interfacing external FLASH and static RAM onto a 32 bit bus The FLASH memory we will use is the AMD AM29LV320DT This is a 32 megabit FLASH memory which can be arranged as 4M by 8 bits or 2M by 16 bits For the RAM we will use a K6F1616U6A which is a 1M by 16 bit static RAM Both these devices are designed for low power applications and the programming algorithm is supported by the ULINK JTAG interface The FLASH is co
205. ro manage the I2C bus for each transaction Fortunately this is easy to do and is centred around the 12C interrupt Once the 12 peripheral is initialised in master mode we can start a write data transfer as follows Hitex UK Ltd Page 91 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS void I2CTransferByte unsigned Addr unsigned Data I2CAddress Addr Place address and data in Globals to be used by the interrupt I2CData Data I2CONCLR 0x000000FF Clear all I2C settings I2CONSET 0x00000040 Enable the I2C interface I2CONSET 0x00000020 Start condition The slave address and data to be sent are placed in global variables so that they can be used by the I2C interrupt routine The address is a seven bit address with the LSB set for write and cleared for read The routine next clears the 12C control flags enables the I2C peripheral and asserts a start condition Once the start condition has been written onto the bus an interrupt is generated and a result code can be read from the I2C status register iSi x 18 kx 28 28 nO 12C status Register For each bus i a event an interrupt is generated a condition code is returned in the status register This code is used to perform within the I2C peripheral If the start condition has been successful this code will be 0x08 Next the application software must write the slave address and the R W bit into the I2Cdata register
206. rruptl 0 0000015 EF000001 SWI 0x00000001 On entry to the ISR the supervisor link register contains the value 0 00000160 R14 LR 0 00000160 The calculation for temp is temp link_ptr 1 amp OxOOFFFFFF or 0x164 4 word wide pointer remember which is 0x15C which points to the instruction which generated the SWI The top 8 bits are masked off which yields a value of 1 This is used in the case statement to run the required code Hitex UK Ltd Page 185 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS Hitex UK Ltd Page 186 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 Chapter 7 Hitex Tutorial With Keil Or GNU Compiler This chapter describes how to use the Hitex tools with the Keil or GNU compiler for the tutorial examples The debugging can be done with the HiSIMARM instruction set simulator as long as no peripherals of the LPC2000 microcontroller are used For examining the peripherals a starter kit from Hitex or the full Tantino or Tanto System is recommended T 1 Installation All the necessary software for the practical examples is on the Hitex CD that comes with this book 1 First it is necessary to install the HiTOP IDE Please install the options HiSIM for ARM and if you are using a starter kit the Tantino7 9 for ARM option also For high end system users please install the option Tanto for ARM as well 2 Depending which
207. rst have to enable this in the ETM settings We do this by opening the context menu of the trace window and select Options To change the ETM settings we select ETM Configuration Project settings X m Options El Applications ETM port size small 4 bit x E ARMTrace amp E Flash Programming ETM port mode normal xl E LPC2124INTERN i m Emulator Settings Cycle accurate tracing disabled mn Trace Setup m TAP Clock FIFO warning level 100 m Breakpoint setting El n Processor Settings e Trigger Delay Counter before trigger Target Settings Data tracing both address and data a ETM Configuration m Target Reset w Show instructions not being executed IN cycles m Memory Monitor coprocessor cycles no Cancel To see both address and data of the data accesses we have to select both address and data in the Data tracing field If only data accesses of a specified address are filtered the address portion can be neglected to reduce the load on the ETM In some cases only the access to specified addresses is of interest so the setting only address portion is recommended Close the dialog and select a new trace filter to record only data accesses Please open the trace control dialog trace context menu filter and insert a new filter definition Start Clock Length sizeof Clock BusState RdWr TraceRecording DFitinc
208. rtup PROC CODE32 Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC PAbt Addr LDR PC DAbt Addr OP Reserved Vector LDR PC PC 4 OxOFFO0 LDR PC The FIQ interrupt vector the instruction loads oo eg md the address of the routine into the PC SWI_Addr DD SWI_Handler PAbt_Addr DD PAbt_Handler DAbt_Addr DD DAbt_Handler DD 0 Reserved Address IRQ_Addr DD IRQ_Handler FIQ Addr DD FIQ Handlewqn constants table holds the address of the FIQ C routine Compile the code and download it onto the board Step through the code until you reach the while loop Set a breakpoint in the FIQ Handler function Press F5 to set the program running On the MCB2100 board press the INT button to generate the interrupt Hitex UK Ltd Page 138 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS If you want to see the entry and exit mechanisms to the exception it is best to use the simulator and single step in the disassembly window This way you can watch the program flow and the actions on the CPU registers To control the interrupt in the simulator open the peripherals GPIO port 0 window If you set the program running unchecking the Pin1 4 box will generate the interrupt You must raise the pin high again to stop interrupts General Purpose Input Output 0 GPIO 0 E xl GPIOU 100180 000000000 31 Bis 24 23 Bis 16 15 Bits B Bits 0 IOSETO fOx00000000 ee FTTTTTTT FT
209. rtup s The default name given by Keil is FIQ_Handler If you are using the simulator the interrupt can be triggered by setting pin 0 14 low in the peripherals GPIO window or by using the Generate EINT1 button in the toolbox Hitex UK Ltd Page 150 hitex mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 15 Exercise 12 Vectored Interrupt In this exercise we will configure a IRQ source to be handled as a vectored interrupt by the VIC We will use the same external interrupt as exercise 9 but this time it will have its own dedicated ISR to give faster servicing of the interrupt request Open the project in C work EX11 Interrupt vectored Configure slot 0 in the VIC to service the EINT1 interrupt VICVectCnt10 0x0000002F Place the address of the dedicated external interrupt routine in the correct vector address register VICVectAddr0O unsigned EXTINTVectoredIRQ Complete the code in the EXTINTVectored to cancel the interrupt EXTINT VICVectAddr 0x00000002 0x00000000 Compile the code and start download it into the debugger Run the code and check that the interrupt is entered correctly and that it only runs once for each press of the EINT1 button pin 0 14 If you are using the simulator open the GPIO Port 0 peripheral window The interrupt can be triggered by bringing pin 0 14 low or use the Generate EINT1 button in the toolbox Open the VIC peripheral window in the debugger and get fa
210. s LDR PC Reset_Addr LDR PC Undef_Addr LDR PC SWI_Addr LDR PC PAbt_Addr LDR PC DAbt_Addr NOP LDR PC PC Ox0FFO Vector from VicVectAddr LDR PC FIQ_Addr void NonVectoredIRO void _ irq if VICIROStatus amp 0x00008000 Test for the interrupt source IOSET1 0x00FF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag updatett VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 13 Non Vectored Interrupt This final exercise with the VIC demonstrates how to handle a non vectored interrupt It is included for completeness since this mode will not normally be required Hitex UK Ltd Page 68 hitex mum 3 System Peripherals DEVELOPMENT TOOLS Soltware interrupt Register It is possible to simulate an interrupt source via the software interrupt set and clear registers in the VIC minugi Channel Interrupt Source In addition the VIC has a protected mode which prevents any of the VIC registers from being accessed in USER mode If the application code wishes to access the VIC it has to enter a privileged mode This can be in an FIQ or IRQ interrupt or by running a SWI instruction Typical latencies for interrupt sources using the VIC are shown below In the case of the non vectored interrupts use the latency for the vectored interrupt plus the time taken to read the IRQstatus register and decide which routine to run FIQ Interrupt Sync
211. s the status code and function results is stored in R1 Command Code parameter table The bootloader functions be accessed to perform In application programming Commands are passed via two tables in memory The start addresses for each table are stored in Result 0 Command Result 1 result table ARM Register The IAP entry point is at Ox7FFFFFFO if you wish to call the functions from a THUMB function or at Ox7FFFFFF1 if you wish to enter from an ARM function The return address is expected to be stored in the link register This convention is designed to work within the ARM procedure call standard A method of calling the IAP routines through function pointers is detailed in the datasheet An alternative method is shown below and both methods are used in the example program If you are short of program space you can experiment with both methods to see which is the most efficient in your compiler If we define a THUMB function with three parameters as shown below void iap unsigned cmd unsigned rslt unsigned entry asm mov ri15 r2 We can pass the start address of a command and result array and by the APCS convention these values will be stored in RO and R1 We can also store the address of the entry point to the IAP routines in the next available parameter register R2 In THUMB mode we cannot program the high registers directly but we can move low registers to high registers hence we can
212. s possible to use the on chip FLASH in conjunction with the external FLASH on chipselect 0 In this case you can make best use of the on chip flash by placing your interrupt functions in it Since these will be coded in the ARM instruction set you will want them to run as fast as possible However you must be careful when locating code into the on chip FLASH If you are booting from external FLASH the interrupt vector table will be mapped into the first 64 bytes of internal memory This means that you must locate any on chip code from location 0x00000040 upwards Anything located below 0x00000040 will be programmed into the FLASH Hitex UK Ltd Page 54 hitex mum 3 System Peripherals DEVELOPMENT TOOLS memory but will be mapped out during normal program operation As a result your code will crash probably in quite a spectacular fashion In the Keil compiler this can be achieved by reserving the vector table bytes as shown below Dpther ru ell scr LPC 37245 Deas Lung E Aum LA Bie Lh Lose Utilis Aj Lis Danny boe angeli The RESERVE command makes sure the first 64 bytes of on chip flash are unused C FERE GARCON allowing the external minam CODE SOMSOCOUOUO DAETEFFFFT E CONST AE T vector table to be mapped in The user segments table allows a specific routines to be mapped on chip ray Hee
213. s the link register R15 is the Program Counter R15 PC Current Program Status Register CPSR Hitex UK Ltd Page 10 hitex mm 1 The ARM7 CPU Core DEVELOPMENT TOO 1 4 Current Program Status Register In addition to the register bank there is an additional 32 bit wide register called the current program status register CPSR The CPSR contains a number of flags which report and control the operation of the ARM7 CPU 31 30 29 28 27 87654 32 1 Interrupt i ating mode Condition code flags IRQ FIQ Negative FIQ Thumb instruction set RQ Zero System Carry User oVerflow Undefined instruction The Current Program Status Register contains condition code flags which indicate the result of data processing operations and User flags which set the operating mode and enable interrupts The T bit is for reference only The top four bits of the CPSR contain the condition codes which are set by the CPU The condition codes report the result status of a data processing operation From the condition codes you can tell if a data processing instruction generated a negative zero carry or overflow result The lowest eight bits in the CPSR contain flags which may be set or cleared by the application code Bits 7 and 8 are the and F bits These bits are used to enable and disable the two interrupt sources which are external to the ARM7 CPU All of the LPC2000 peripherals are connected to these two interrupt lines as we shall see later Y
214. s up to a maximum of 1 Mbit sec Typically this can be achieved over about 40 metres of cable By dropping the bit rate longer cable runs may be achieved In practice you can get at least 1500 metres with the standard drivers at 10 Kbit sec Hitex UK Ltd Page 102 mmm 4 User Peripherals DEVELOPMENT TOOLS 4 12 3 CAN Message Objects The CAN bus has two message objects which may be generated by the application software The message object is used to transfer data around the network The message packet is shown below Arbitration Field DATA Field Field s R A 29 Bit Identifier 0 8 Bytes Data 15 bit CRC f R K Remote transmit request Control Error control and end of frame Data length code CAN message packet The message packet is formed by the CAN controller the application software provides the data bytes the message identifier and the RTR bit The message packet starts with a dominant bit to mark the start of frame Next comes the message identifier which may be up to 29 bits long The message identifier is used to label the data being sent in the message packet CAN is a producer consumer protocol A given message is produced from one unique node and then may be consumed by any number of nodes on the network simultaneously It is also possible to do point to point communication by making only one node interested in a given identifier Then a message can be sent from the producer node to
215. sages In order for a CAN network to work we need a minimum of two nodes Fortunately the LPC2194 has two independent CAN controllers which are brought out to two D Type connectors on the evaluation board For our examples we will connect the two channels together and send data from one channel to the other Setup the evaluation board with the JTAG debugger and connect Pin 2 CAN low of socket P3 to pin 2 of socket P4 Do the same with pin7 CAN High Open the project in c examples work EX22 TXCAN Calculate the bit timing values for 125 Mbit sec withPclk 60 MHz Complete the lines of code in the example Program the bit timing register C2BTR 0x001C001D To transmit the data set the Data length code to four bytes C2TFI1 0x00040000 Set the address to message 22 and a standard 11 bit identifier C2TIDI 0x00000022 Copy the A D result into the first byte of the TX buffer C2TDAI val Schedule the message for transmission C2CMR 0x00000001 Build the code and start the debugger Once the code is running the A D conversion will be transmitted from the CAN2 module and received by CAN1 The received data is then written to the GPIO to modulate the LED s In the simulator the two CAN channels are looped back by a script file and the CAN traffic may be observed in the Peripherals CAN communication window Hitex UK Ltd Page 169 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 29 Exercise 26
216. se 7 Memory Accelerator Module 141 5 11 Exercise 8 In Application Programming 143 5 12 Exercise 9 External Bus Interface 144 5 13 Exercise 10 Phase Locked Loop 148 5 14 Exercise 11 Fast Interrupt ss 150 5 15 Exercise 12 Vectored Interrupt s 151 5 16 Exercise 13 Non Vectored Interrupt 152 5 17 Exercise 14 Nested 153 5 18 Exercise 15 General Purpose IO 154 5 19 Exercise 16 Timer Capture ss 155 5 20 Exercise 17 Timer Match 157 5 21 Exercise 18 Dual Edge Symmetrical PWM Generation 160 5 22 Exercise 19 Real Time Clock 162 5 23 Exercise 20 UART en eee e Rer XR eene 163 5 24 Exercise 21 12C interface 164 5 25 Exercise 22 9PlL tiat edad 166 5 26 Exercise 23 Analog To Digital 167 5 27 Exercise 24 Digital to Analogue 168 5 28 Exercise 25 Transmitting CAN Data sse 169 5 29 Exercise 26 Receiving CAN Data 170 6 Chapter 6 Keil Tutorial With GNU Tools 172 6 1 IMOAUCION EE 172 6 2 GCC Startup Gode enc 172 6 3 Interworking ARM THUMB
217. sed to screen messages as they come in from the CAN bus The acceptance filter can be programmed to pass or block message identifiers before they enter the CAN controller for processing This prevents unwanted messages entering the CAN receive buffer and consequently greatly reduces the overhead on the CPU CAN Controller 1 TX Acceptance Filter with Identifier Look up Table 3 The CPU can read the message objects at any time gt 1 CAN message received 4 2 Scan ID against acceptance tables On Match transfer message to unique message buffer Full CAN mode In full CAN mode the CAN RAM may also be configured as additional receive buffers which store incoming data for the CPU to read as required The acceptance filter has 2K of RAM 512 x 32 which may be allocated into tables of identifiers This allows ranges of messages and individual messages to be able to enter into the CAN receive buffer As a message passes through the acceptance filter it is assigned an ID Index This is an integer number that relates to the message ID s offset in the acceptance filter table This number is stored in the RX Frame Status register So rather than decode the raw message ID it is easier and faster to use the index value to decide what message has been received 5 f enabled ponerse ing Rx RG i l On Match load the messa
218. see if the FLASH needs to be programmed First the watchdog is checked to see if the processor has had a hard reset of a soft reset If itis a hard reset the logic level on pin0 14 will be tested If it is low then the bootloader command handler will be entered If it is a soft reset ie watchdog timeout or pin 0 14 is high then there is no external request to reprogram the FLASH However before handing over to the user application the bootloader will check to see if there is a valid user program in FLASH In order to detect if a valid program is present every user program must have a program signature This signature is a word wide number that is stored in the unused location in the ARM7 vector table at 0x00000014 The program signature is the two s compliment of the checksum of the ARM vector table L FIO IRG UNUSED x ABORT D cru _ UNDEF r The program signature is calculated as RESET x the two s compliment of the checksum JP of the vector table This signature must be stored the unused vector at Lon 0x00000014 or your program will not run When this value is summed with the program signature the result will be zero for a valid program If a valid program is detected the memory operating mode is switched to FLASH which restores the user vector table the program counter is forced to zero and the user application starts execution If there is no valid program then the boo
219. shown below case 0x40 Slave Address R ACK I2CONSET 0x04 Enable ACK for data byte break case 0x48 Slave Address R Not Ack I2CONSET 0x20 Resend Start condition break case 0x50 Data Received ACK message I2DAT I2CONSET 0x10 Stop condition lock 0 Signal end of I2C activity break case 0x58 Data Received Not Ack I2CONSET 0x20 Resend Start condition break Exercise 21 I2C This exercise demonstrates how to use the 2 interface to communicate to an I2C EEROM Hitex UK Ltd Page 94 hitex mms 4 User Peripherals DEVELOPMENT TOOLS 4 9 SPI Interface Like the 12C interface the SPI interface is a simple peripheral engine which can write and read data to the SPI bus but is not intelligent enough to manage the bus It is up to your code to initialise the SPI interface and then manage the bus transfers SPI interface SOK Dame Saed MIBO MOSI SP Faun Complet The SPI peripheral has four external pins a serial clock pin slave select pin and two data pins master in slave out and master out slave in The serial clock pin provides a clock source of up to 400Kbits sec when in master mode or will accept an external clock source when in slave mode The SPI bus is purely a serial data connection for high speed data transfer and unlike I2C does not have any addressing scheme built into the serial t
220. signals which include four trace data lines TRACEPKTn the trace clock TRACESYNC and the trace status signals PIPESTATEN Now we connect the TantoPT to the TantoBase and connect with the TantoPL to the 38pin ETM connector of the target You must also add JP10 on the MCB2100 to enable the port trace After plugging in the power cables we switch the power on and connect the Tanto system with an Ethernet or an USB cable to the PC To create a project for Tanto please use StartEasy make the necessary settings described below and create the example application Clock Hitex UK Ltd Page 199 hitex mum 8 Extended Debugging With ETM Trace DEVELOPMENT TOOLS The necessary settings for the project are the same as in the former projects except the tool setting Tanto with the correct serial number The necessary settings for the peripherals are PLL VBP MAM PLL enabled multiplier 4 divider 4 VIC Sources TimerO enabled IRQ VIC Channels ChannelO TimerO PO POO P01 Function Enabled Prescaler 12 Compare Channel 0 5000 restart enabled UARTO Enabled 9600 default values When the application is fully created with StarEasy we can open the created project with HiTOP The application is automatically programmed into the FLASH and the benefits of the debugging with trace can be tested 8 3 Recording Execution Trace This exercise describes how make a real time recording of code as it is executed i
221. simulator a script has been added to the toolbox to generate a pulse on 0 02 If you are using the MCB2100 you need to pull the port pin up to Vcc via a 10K resistor Hitex UK Ltd Page 155 hitex mm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS In the simulator check that the timer is incrementing at the required rate by single stepping until the timer increments and measuring the time interval with the clock in the register window Timer count Ds de Te 77838 07 Femmes E IIIMMM DL D xl F Pas m Iu I 1 Basis re TI RTL das m n aca ene Varie sj 4 D Loi T dumme bmi mn fil 1 ML I ULIS O a 1 7j Timer value at 1 capture event PLU mt rail T gt CCE IN E T um Hs E om ER LT CIE FH penes CHI mue TU ONU ime vemm T D me Hitex UK Ltd Page 156 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 20 Exercise 17 Timer Match In this exercise we will configure the timer to generate a single edge PWM signal using two match channels Match zero will be used to generate the total PWM period On match it will be used to reset the timer and generate an interrupt Match one will be used to create the duty cycle On match it will clear the external match one pin At the beginning of the cycle the interrupt will set the external match on
222. stalled you are ready to start the tutorial exercises Hitex UK Ltd Page 118 hitex mum 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 1 1 Using the Keil UVISION IDE This section will cover the development tools that can be used to develop code for the LPC2000 In this book all the example are written for the Keil ARM toolset The Keil toolset comprises of the UVISION IDE which contains an editor and project manager an ARM7 Compiler and linker and a Software simulator The simulator will simulate the ARM7 core and the LPC2000 peripherals so it is possible to see the full operation of the chip by just using the simulator An evaluation version of the toolset is available free from the Keil website at www keil com or on the CD supplied with this book It is also possible to purchase a starter kit which contains an evaluation board and JTAG debugger that allows you to develop code on a real target device The Keil ARM compiler allows us to write in the C language and compile code to run on the LPC2000 devices In order to cope with the microcontroller architecture the compiler has a number of non ANSI extensions that allow us to handle features such as interrupts ARM Thumb interworking and accessing device peripherals Before we start its worth looking at a simplified memory map of an LPC2000 so we can understand how to build a project OxFFFF FFFF Peripherals O00 The memory of the LPC21xx is linear 40 04000 FEFE
223. ster called the saved program status register If your application is running in user mode when an exception occurs the mode will change and the current contents of the CPSR will be saved into the SPSR The exception code will run and on return from the exception the context of the CPSR will be restored from the SPSR allowing the application code to resume execution The operating modes are listed below Saber A Abort mg na nn no n CTI m m Fat Ra Fa fa Fa The ARM7 CPU has six operating modes Ha which are used to process exceptions The Fe n n ha shaded registers are banked memory that m ni RE m is switched in when the operating mode FF changes The SPSR register is used to na ni n aes id copy of the CPSR when the switch Bn LE Anti ATE Aaa ARE Rig ira pius orca nes Per nis me Ari CA CPZH CPER 1 5 Exception Modes When an exception occurs the CPU will change modes and the PC be forced to an exception vector The vector table starts from address zero with the reset vector and then has an exception vector every four bytes Each operating mode has an associated interrupt vector When Plag Duper im the processor changes mode the Leira enuan Lir lire aO PC will jump to the associated TE TSS UU PSS PRE ET ET vector infernal S T NB there is a missing vector at Peutetchi Abort o
224. structions so a small branch such as if x lt 100 sorry would be most efficient when coded using conditional execution of ARM instructions The main instruction groups of the ARM instruction set fall into six different categories Branching Data Processing Data Transfer Block Transfer Multiply and Software Interrupt Hitex UK Ltd Page 16 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 6 1 Branching The basic branch instruction as its name implies allows a jump forwards or backwards of up to 32 MB A modified version of the branch instruction the branch link allows the same jump but stores the current PC address plus four bytes in the link register B 0x000 Daoa PC 0x8000 410 The branch instruction has several forms The Ps BL xBoDO ooo branch instruction will jump you to a destination f address The branch link instruction jumps to the PC 8000 destination and stores a return address in R14 Aide Oxted op LDAR2 10 0200C So the branch link instruction is used as a call to a function storing the return address in the link register and the branch instruction can be used to branch on the contents of the link register to make the return at the end of the function By using the condition codes we can perform conditional branching and conditional calling of functions The branch instructions have two other variants called branch exchange and branch link exch
225. t ES Printf 1 5 source code E main c Ipe21xx h Le stdio h E serial c Assembler startup code A Startup s x Documentation Lx abstract txt In serial c complete the putchar function so it writes a single character to the serial port int putchar int ch is ch at while UOLSR amp 0x20 UOTHR CR while UOLSR amp 0x20 return UOTHR ch Compile the code and download it to the development board or simulator Connect COMO on the board to PC comm Port 1 and start Hyperterminal with the configuration file in the exercise directory If you are using the simulator select view serial window 1 This opens a terminal window within the simulator that displays the UARTO output Run the code and check that the message appears on the terminal window Hitex UK Ltd Page 136 hitex mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS Jar 2 EE ere je wes sali bus Doe ELS Hitex UK Ltd Page 137 mmm 5 Tutorial With Keil Tools DEVELOPMENT TOOLS 5 8 Exercise 5 Simple Interrupt In this exercise we will setup a basic FIQ interrupt and see it serviced Open the project in C work EX5 Interrupt In main c complete the definition of the FIQ Handler function to define it as the FIQ interrupt service routine void FIQ Handler void fiq In startup s complete the vector constants table to define EXTintFIQ as the FIQ ISR Sta
226. t expander chips PCA 8574 Rp 50 D Number of Devices D RpinKQ PCA 8574 A typical I2C system is shown above where the LPC2000 is connected to two external port expander chips As with the other peripherals the Serial Clock SCL and Data SDA lines must be converted from GPIO pins to I2C pins via the pin connect block 12C peripheral registers The programmers interface includes two timing registers set and clear registers for the control register an address register to hold the node address when sna in slave mode and a data register to send and receive bytes of data The 12C peripheral interface is composed of seven registers The control register has two separate registers which are used to set and clear bits in the control register IZCONSET I2CONCLR The bit rate is also determined by two registers I2SCLH I2SCLL The status register returns control codes which relate to different events on the bus The data register is used to supply each byte to be transmitted or as data is received it will be transferred to this register Finally when the LPC2000 is configured as a slave device its network address is set by programming the I2ADR register In order to initialise the 12C interface we need to run the following lines of code VICVectCnt11 0x00000029 select priority slot for a given interrupt VICVectAddrl unsigned I2CISR pass the address of the IRQ into the VIC slot VICIntEnable 0x
227. th messages will fight for arbitration and both will win as they have the same ID Once they have won arbitration they will both start to write their data onto the bus At some point this data will be different and this will cause a bit check error Both messages will be rescheduled win arbitration and go into error again Potentially this deadly embrace can lock up the network so beware Hitex UK Ltd Page 111 hitex mum 4 User Peripherals DEVELOPMENT TOOLS At the bit level CAN also implements a bit stuffing scheme For every five dominant bits in a row a recessive bit is inserted Arbiration Data n ntl n 2 n 3 4 n 5 n 6 n 7 Bit Stuffing For every five bits of one logic in a row a stuff bit of the opposite logic is inserted The error frame CAN Bit Stream Stuff breaks this rule by being six Bit 1__ dominant bits in a row n ntl n 2 n 3 4 n 5 n 6 n 7 This helps to break up DC levels on the bus and provides plenty of edges in the bit stream which are used for resynchronisation An error frame in the CAN protocol is simply six dominant bits in a row This allows any CAN controller to assert an error onto the bus as soon as the error is detected without having to wait until the end of a message Internally each CAN controller has two counters Reset and Configuration 4 gt Error counters j The CAN controller moves between a REC A Pr eric D number of error states that a
228. the VIC for a vectored IRQ interrupt The vector table should contain the instruction to read the VIC vector address as follows Vectors LDR PC Reset_Addr LDR PC Undef_Addr LDR PC SWI_Addr LDR PC PAbt_Addr LDR PC DAbt_Addr NOP LDR PC PC Ox0FFO Vector from VicVectAddr LDR PC FIQ Addr The C routines to enable the VIC and sever the interrupt are shown below void main void IODIR1 0x000FF000 Set the LED pins as outputs PINSELO 0x20000000 Enable the EXTINT1 interrupt VICVectCnt10 0x0000002F select a priority slot for a given interrupt unsigned EXTINTVectoredIRQ pass the address of the IRQ into the VIC slot VICVectAddrO0 VICIntEnable 0x00008000 enable interrupt while 1 void EXTINTVectoredIRQ void __irq IOSET1 0x000FF000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag VICVectAddr 0x00000000 Dummy write to signal end of interrupt Exercise 12 Vectored interrupt This exercise uses the same interrupt source as in exercise 11 but this time the VIC is configured to respond to it as a vectored IRQ exception 3 12 8 Non Vectored Interrupts The VIC is capable of handling 16 peripherals as vectored interrupts and at least one as an FIQ interrupt If there are more than 17 interrupt sources on the chip any extra interrupts can be serviced as non vectored interrupts The non vecto
229. the caller To set breakpoints move the cursor to the desired line and in the grey column on the left hand edge the cursor will then change shape to show the breakpoint icon A click with the left mouse button will now set or clear the breakpoint A click with the right mouse button opens a context window to change the properties of the breakpoint Breakponts can be only set in lines which have produced corresponding code These lines are marked with a blue rectangle in the lefthand side grey column Hitex UK Ltd Page 192 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 5 To execute the code up to an arbitrary point in the program select the line of code you wish to run to and place the cursor into its blue rectangle the cursor will change shape to 6 Now left click and the program will run until it reaches this point 7 Torun the application until a desired function is reached such as main use the command Debug Go until or Shift F10 and insert main in the dialog 8 Now the application was executed until the function main and the C source is displayed 9 Inthe Module view tab of the workspace window all modules of this application are listed Clicking on the sign of a module i e main opens this module and shows all the functions and if present also the variables Workspace a X ARMbook MIS interrupt H A irq EME main fO C INIT fO init main J a startup ma Globals 8 3
230. the main tutorial but use the exercise examples in the GCC directory 6 2 GCC Startup Code The startup code used in the GNU project is different in that the Keil Assembler has different directives and naming conventions However it is performing the same operations It is up to the programmer to edit the vector table as discussed in the section on the Keil compiler startup code The graphical editor allows you to configure the processor stacks and system peripherals in the same way as the Keil compiler startup code 6 3 Interworking ARM THUMB Code The GCC compiler also supports the ARM procedure calling standard and allows interworking between the ARM and THUMB instruction sets However unlike the Keil compiler it is not possible to select individual functions as ARM or THUMB In the GCC compiler all ARM code must be in one module or modules and the THUMB code must be in separate modules These modules are compiled as ARM or THUMB as required and then linked together This process is described in example 3 in this section 6 4 Accessing Peripherals The Keil and GNU compilers can use the same include files to access the on chip SFR registers 6 5 Interrupt Service Routines The GCC compiler has a set of non ANSI extensions which allow functions to be declared as interrupt routines The general form of the declaration is shown below void IRQ_Routine void __attribute__ interrupt IRO The following keywords are available to define
231. tings are not necessary for the first steps and now the first LPC application can be created by selecting the menu File followed by the entry Write Code The Build log window displays the actions of the compiler Please look for possible error messages which may occur when the paths to the tools or libraries are not correct When you have a clean build we can start debugging with HiTOP Hitex UK Ltd Page 190 hitex mum 7 Tutorial With Hitex Keil amp GNU Tools DEVELOPMENT TOOLS 7 4 Using HiTOP 1 Launch the HiTOP IDE by double clicking on the desktop icon P 2 To open the new project please use the menu Project and the item Open and please remember the project path and the project name used in StartEasy Browse to this directory and open the project project name gt htp 3 f you have only a 16k code size limited licence included in a starter kit or the free HDS the Upgrade evaluation license following dialog appears Please click want to continue evaluation HiTOP has not found a full license for your system HIT OP allows you to download applications which are code size limited to 16K Bytes You can get 30 days license without code size limitation for free or you may purchase a full license want to get a 30 day full license want to buy a full license want to continue evaluation Now the created application is opened with the debug tool you selected in Start
232. tion Hitex UK Ltd Page 21 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 10 MAC Unit In addition to the barrel shifter the ARM7 has a built in Multiply Accumulate Unit MAC The MAC supports integer and long integer multiplication The integer multiplication instructions support multiplication of two 32 bit registers and place the result in a third 32 bit register modulo32 A multiply accumulate instruction will take the same product and add it to a running total Long integer multiplication allows two 32 bit quantities to be multiplied together and the 64 bit result is placed in two registers Similarly a long multiply and accumulate is also available Mnemonic Meaning Resolution MUL Multiply 32 bit result MULA Multiply accumulate 32 bit result UMULL Unsigned multiply 64 bit result UMLAL Unsigned multiply accumulate 64 bit result SMULL Signed multiply 64 bit result SMLAL Signed multiply accumulate 64 bit result Hitex UK Ltd Page 22 hitex mum 1 The ARM7 CPU Core DEVELOPMENT TOOLS 1 11 THUMB Instruction Set Although the ARM7 is a 32 bit processor it has a second 16 bit instruction set called THUMB The THUMB instruction set is really a compressed form of the ARM instruction set The THUMB instruction set is essential for archiving the necessary code density to make small single chip ARM7 micros usable 16 bit Thumb code This allows instruc
233. tion but the MAM is disabled A simple LED flashing routine is used to illuminate the LEDs on the target board in sequence This shows the sort of performance you can expect from and ARM7 running directly from on chip FLASH memory When the value of the potentiometer is changed the MAM is enabled and the code will run faster making the LEDs flash faster This increase in performance caused solely by the MAM which is why it is so important to this kind of small single chip microcontroller In this example we will use the bootloader to load the code into the flash in place of the JTAG Open the project in exercises EX7 MAM In main c complete the code to enable the MAM In Options for target output tick the generate hex box Build the code Connect the PC serial port to COMO on the target board Apply power to the board Start the Philips ISP Utility to get the screen shown below PHILIPS LPC2000 Flash Utility V2 2 0 Flash Fer Eim sn i CE fea Flach por Lis i uncus Flick Marnal Fani _ End Sect biens Lie TURTE ra TSE rw ol kx ara ae iL Rami E F a Lai Fo Kies Loads ef ator Make sure the Use DTR RTS box is ticked Press the Read Device ID button If the board is connected ok the part ID number and bootload version will be displayed Make a note of these numbers as we will use them in t
234. tion shown below does this in a single cycle LDA PC PC OxFFO As we are on the IRQ we know the address is 0x00000018 8 for the pipeline If we deduct OxFFO from this it wraps the address round the top of the 32 bit address space and loads the contents of address OxFFFFFF020 the Vector Address Register x DOR When an IRQ exception occurs the CPU executes the instruction LDA PC PC OxFFO which loads the contents of the LOR FC Pt FFE Load Contents of 1 vector address register into the PC forcing QutB FFO PC PC a jump to the ISR 00 J xFFFF FFF Ven Accro lesions 3 12 7 Leaving An IRQ Interrupt As in the FIQ interrupt you must ensure that the interrupt status flags are cleared in the peripheral which generated the request In addition at the end of the interrupt you must do a dummy write to the Vector Address Register This signals the end of the interrupt to the VIC and any pending IRQ interrupt will be asserted Write Vector Address Register At the end of a vectored IRQ interrupt you must make a dummy write to the Vector Clear Peripheral Interrupt Register Address Register in addition to clearing the peripheral flag to clear the interrupt Hitex UK Ltd Page 66 hitex mm 3 System Peripherals DEVELOPMENT TOOLS 3 12 7 1 Example Program IRQ interrupt This example is a repeat of the FIQ example but demonstrates how to set up
235. tions to be stored in a 16 bit format expanded into ARM instructions and then executed Although the THUMB instructions will result in lower code performance compared to ARM instructions they will achieve a much higher code density So in order to build a reasonably sized application that will fit on a small single chip microcontroller it is vital to compile your code as a mixture of ARM and THUMB functions This process is called interworking and is easily supported on all ARM compilers By compiling code in the THUMB instruction set you can get a space saving of 3095 while the same code compiled as ARM code will run 40 faster The THUMB instruction set is much more like a traditional microcontroller instruction set Unlike the ARM instructions THUMB instructions are not conditionally executed except for conditional branches The data processing instructions have a two address format where the destination register is one of the source registers ARM Instruction THUNB Instruction ADD RO RO R1 ADD RO R1 RO RO RI The THUMB instruction set does not have full access to all registers in the register file All data processing instructions have access to RO R7 these are called the low registers In the THUMB programmers model all instructions have access to RO R7 Only a Low Fegistens few instructions may access R8 R12 High Registers However access to R8 R12 the high registers is restricted to a few instructi
236. tloader enters its command handler So without the program signature your code will never run The program signature can be added to your startup code as shown below LDR PC Reset_Addr LDR PC Undefined_Addr LDR PC SWI_Addr LDR PC Prefetch_Addr LDR PC Abort_Addr long 0xB8A06F58 Program signature LDR PC IRQ_Addr LDR PC FIQ_Addr 3 6 3 Philips ISP Utility If there is a valid program signature or pin 0 14 is held low after reset the LPC2000 will start the bootloader Before handing over to the command handler it enters an auto Baud routine This routine listens on UART 0 for a synchronisation character When this is sent by the host the LPC2000 measures the bit period and adjusts the UART 0 Baud rate generator to match the host Once this is done some further handshaking and configuration takes place and then control is passed to the command handler The Bootloader command handler takes commands from UARTO in ASCII format The command set is shown below and allows you full programming control of the FLASH In addition the GO command is a simple Hitex UK Ltd Page 46 hitex mum 3 System Peripherals DEVELOPMENT TOOLS debugging command which can be used to start execution of code loaded into RAM A full description of the bootloader communication protocol is given in the LPC2000 datasheet Cocke Teee TU EN mien onto vie Pr ed i RAM es Pian Goaf eee i
237. to enable an increment interrupt for each of the eight time counter registers The second method for generating an RTC interrupt is with the alarm registers Each time counter register has a matching Alarm register If the matching Alarm register is unmasked it is compared to the time counter register If all the unmasked alarm registers match the time counter registers then an interrupt is generated So it is possible to set an alarm between now and 2099 with one second s accuracy The Alarm Mask register controls which alarm registers are used in the compare As both the increment and alarm events can generate an RTC interrupt it is necessary to distinguish between them from within the interrupt The Interrupt location register provides two flags which can be interrogated to see what caused the RTC interrupt Again remember that these flags must be cleared to cancel the interrupt An RTC program which sets the clock and uses both styles of interrupt is shown below Hitex UK Ltd Page 82 hitex mum 4 User Peripherals DEVELOPMENT TOOL int main void VPBDIV Ox IODIRI Ox IOSET1 0x00020000 PREINT 0x00000392 Set RTC prescaler for 30MHz Pclk 000 F 2 0 PREFRAC 0x00004380 0 0 F 0 0002 0000 set LED ports to output CC CIIR 0 00000001 Enable seconds counter interrupt ALSEC 0x00000003 Set alarm register for 3 seconds C3 0 AM
238. tructions In the following section the use of the word ARM means the 32 bit instruction set and ARM7 refers to the CPU The is designed to operate as a big endian or little endian processor That is the MSB is located at the high order bit or the low order bit You may be pleased to hear that the LPC2000 family fixes the endianess of the processor as little endian i e MSB at highest bit address which does make it a lot easier to work with However the ARM7 compiler you are working with will be able to compile code as little endian or big endian You must be sure you have it set correctly or the compiled code will be back to front MSB L58 Bat 31 Bit The ARM7 CPU is designed to support code compiler in big endian or little endian format The Philips silicon is fixed as little endian L5B8 MSB Big endinm Bst 41 Bit 0 One of the most interesting features of the ARM instruction set is that every instruction may be conditionally executed In a more traditional microcontroller the only conditional instructions are conditional branches and maybe a few others like bit test and set However in the ARM instruction set the top four bits of the operand are compared to the condition codes in the CPSR If they do not match then the instruction is not executed and passes through the pipeline as a NOP no operation 31 28 Every ARM 32 bit instruction is conditionally executed The top four bits are ANDed with the C
239. tx register break case 0x20 Slave address W Not ACK I2DAT I2CAddress Resend address and write bit break case 0x28 Data sent Ack I2CONSET 0x10 Stop condition break default break I2CONCLR 0x08 Clear I2C interrupt flag VICVectAddr 0x00000000 Clear interrupt in This example sends a single byte but could be easily modified to send multiple bytes Additional case statements may be added to handle a master request for data 255b OK Dx du Ox 80 Ux Si Se 12 master TX This bus x transaction demonstrates a master to slave write DATA DATA transaction In the case of a master receive the start condition will be the same but this time the address written on to the bus will have the R W bit cleared When the acknowledge is received after the slave address is sent it will be followed by the first byte of data from the slave so the master does not have to do anything However in the case statement we can set the acknowledge bit so that an ACK is generated as soon as the byte has been transferred As each byte is transferred the data can be read from I2CDAT When all the bytes have been received the stop condition can be asserted and the transaction ends Hitex UK Ltd Page 93 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS The same l2CtransferByte function can be used to start a read transaction and the additional case statements required in the interrupt are
240. uage and is supported by intrinsic functions within the compiler library The swap instruction allows you to exchange the contents of two registers This takes two cycles but is treated as a single atomic instruction so the exchange cannot be corrupted by an interrupt 1 8 Modifying The Status Registers As noted in the ARM7 architecture section the CPSR and the SPSR are CPU registers but are not part of the main register bank Only two ARM instructions can operate on these registers directly The MSR and MRS instructions support moving the contents of the CPSR or SPSR to and from a selected register For example in order to disable the IRQ interrupts the contents of the CPSR must be moved to a register the 1 bit must be set by ANDing the contents with 0x00000080 to disable the interrupt and then the CPSR must be reprogrammed with the new value MSA ENN CEPR APSR The CPSR and SPSR are not memory mapped or part of the central register file The only instructions Fas which operate on them are the MSR and MRS instructions These instructions are disabled when the CPU is in USER mode eS MAS SPR The MSR and MRS instructions will work in all processor modes except the USER mode So it is only possible to change the operating mode of the process or to enable or disable interrupts from a privileged mode Once you have entered the USER mode you cannot leave it except through an exception reset FIQ IRQ or SWI
241. uded the ARM ETM module for high end debugging tools The final on chip debug feature is the Real Time Monitor This is a kernel of code which is resident in a reserved area of memory During a debug session the debugger can start the real monitor via the JTAG port The real monitor can be used to provide on the fly updates as your code is running This process is pseudo real time in that the real monitor code interrupts your code and uses some processor time to read and communicate debug information to the PC Hitex UK Ltd Page 37 hitex mm 2 Software Development DEVELOPMENT TOOLS 2 13 1 1 Important The JTAG and ETM tools simply provide a fairly dumb serial debug connection to the ARM7 core A generic ARM JTAG tool does not have any understanding of the overall LPC2000 architecture This means that a generic tool will always enter the bootloader after reset because it does not write the program signature into the FLASH this feature is discussed later and consequently will never run your code If you are new to the LPC2000 this is likely to catch you out and be very frustrating Since the Keil tools are developed for ARM7 based general purpose microcontrollers MicroVision uVision understands the LPC2000 memory architecture and will debug the device seamlessly 2 13 1 2 Even More Important As mentioned above the JTAG port is a simple serial debug connection to the ARM7 device It is very important to understand
242. uns off the PCLK so an additional external oscillator is not required The RTC is designed to be an ultra low power peripheral and through use of the LPC2xxx low power modes is suitable for running off batteries As well as providing a clock calendar the RTC has a set of alarm registers that can be used to trigger a particular date and time or on a specific value held in a time count register Retenenca Clock Divider Alam Marne Alann The RTC is a clock calendar with alarm valid up until 2099 How Alan interrupt avniiah s cn ol register value Dar 0d mong dde Cry cH mon Arm Dry il pint Mors Alarm Year Abr on match The RTC clock runs on a standard 32 7KHz clock crystal frequency In order to derive this frequency the Pclk is connected to the reference clock divider In effect this is a prescaler whicht can accurately divide any Pclk frequency to produce the required 32KHz frequency PCLK 32 768 RTC Prescaler RTC Clock Logic The RTC watch crystal frequency may be derived from any value of PREINT PREFRAC Pclk To ensure that the RTC clock can be accurately derived from any Pclk the prescaler is more complicated than the general purpose timer prescalers The prescaler is programmed by two registers called PREINT and PREFRAC As their name implies these hold integer and fractional divisor values The equations used to calculate the load values for these registers are as follows
243. will reset the counter and set match 0 high This causes all the flip flops to be set at the beginning of the cycle The output Q goes high raising all the output pins high Modulation of the PWM signal is done with the remaining match channels Each PWM channel has an associated match channel which is connected to the R input of the flip flop When the match is made the flip flop is reset and the PWM pin is set low This allows modulation of the PWM signal by changing the value of the dedicated match channel Hitex UK Ltd Page 79 hitex mms 4 User Peripherals DEVELOPMENT TOOLS Match 0 Timer counter reset Match 1 PME m mmm mm mm Double Edge PWM h ins Match 0 controls the period of the PWM cycle Two match channels are used to modulate the pulse rise and fall times for each PWM rhannal By reprogramming the multiplexer the output stage of the PWM modulator can be configured to dual edge controlled modulation In this configuration Match 0 is not connected to any output and is used solely to reset the timer at the end of each PWM period In this configuration the S and R inputs to each flip flop have a dedicated Match channel At the beginning of a cycle the PWM output is low The rising edge of the pulse is controlled by the Match channel connected to the S input and the falling edge is controlled by the Match channel connected to the R input The example below illustrates how to configur
244. will start to write its message onto the bus As during arbitration as each bit is written onto the bus the CAN controller is reading back the level written onto the bus As the node has won arbitration nothing else should be transmitting so each bit level written onto the bus must match the level read back If the wrong level is read back the transmitter generates an error frame and reschedules the message The message is sent in the next message slot but must still go through the arbitration process with any other scheduled message ENDE Standard 8 byte Data Frame Inter Frame Space lt 1 Recessive 0 Dominant Transmitting p Intermission node expects bus End of Frame Bit check error state to be the ACK Delimiter Once the arbitration has same as the state ACK Slot finished the write and read it is transmitting CRC Delimiter back mechanism is use for N B Do not CRC Sequence bitwise error checking allow multiple Data Field nodes to Data Length Code transmit reserved bit D messages with 5 the same ID IDE bit D RTR bit D Identifier Field Start of Frame This leads to one of the golden rules in developing a CAN network In a CAN network every identifier must be uniquely generated So you must not have the same identifier sent from two different nodes If this happens it is possible that two messages with the same ID are scheduled together bo
245. will vary depending on the variant but there are at least two timers All of the general purpose timers are identical in structure but vary slightly in the number of features supported The timers are based around a 32 bit timer counter with a 32 bit prescaler The clock source for all of the timers is the VLSI peripheral clock PCLK The two timers and the PWM module have the same basic timer structure A 32 bit timer counter iih FS necu n mm p Reset Enable The tick rate of the timer is controlled by the value stored in the prescaler register The prescale counter will increment on each tick of Pclk until it reaches the value stored in the prescaler register When it hits the prescale value the timer counter is incremented by one and the prescale counter resets to zero and starts counting again The Timer control register contains only two bits which are used to enable disable the timer and reset its count In addition to the basic counter each timer has up to four capture channels The capture channels allow you to capture the value of the timer counter when an input signal makes a transition CAP Pin Timer Counter Each capture channel has a capture Logic pin This pin can trigger a capture Capture Register event on a rising or falling edge When an event occurs the value in Captum control the timer counter is latched into an associated capture register Each capture channel has an associated capture pi
246. x UK Ltd Page 101 hitex mmm 4 User Peripherals DEVELOPMENT TOOLS Microcontroller CAN Controller physical layer and is connected to a twisted pair terminated by 120 Ohm TXI RXO RX resistors CAN Transceiver CANL CANH CAN node hardware A typical CAN node has a microcontroller CAN controller Rr Ri One important feature about the CAN node design is that the CAN controller has separate transmit and receive paths to and from the physical layer device So as the node is writing on to the bus it is also listening back at the same time This is the basis of the message arbitration and for some of the error detection The two logic levels are written onto the twisted pair as follows a logic one is represented by bus idle with both wires held half way between 0 and Vcc A logic Zero is represented by both wires being differentially driven V Recessive Dominant Recessive amp CAN Physical layer signals On the CAN bus logic zero is represented by a maximum voltage difference called Dominant and logic one by a bus idle state called recessive dominant bit will overwrite a recessive bit un In CAN speak a logic one is called a recessive bit and a logic zero is called a dominant bit In all cases a dominant bit will overwrite a recessive bit So if ten nodes write recessive and one writes dominant then each node will read back a dominant bit The CAN bus can achieve bit rate
247. y with the UART timings if you need to adjust the Pclk to get exact timings on other peripherals such as the CAN bit timings The divisor value is held in two registers Divisor latch MSB DLM and Divisor latch LSB DLL The first eight bits of both registers holds each half of the divisor as shown below Finally the DLAB bit in the LCR register must be set back to zero to protect the contents of the divisor registers 16 BAUD X 1 UART baud rate The UART clock frequency must be 16 times the required BAUD rate This is derived by dividing Pclk by a 16 bit divisor register Once the UART is initialised characters can be transmitted by writing to the Transmit Holding Register Similarly characters may be received by reading from the Receive Buffer Register In fact both these registers occupy the same memory location writing a character places the character in the transmit FIFO and reading from this location loads a character from the Receive FIFO The two routines shown below demonstrate handling of transmit and receive characters int putchar int ch Write character to Serial Port 4 if ch n while UILSR amp 0x20 U1THR CR output CR while UILSR amp 0x20 return UITHR ch int getchar void Read character from Serial Port n while U1LSR amp 0x01 return UIRBR The putchar and getchar functions are used to read write a single character to t

Insider`s Guide Philips ARM®7

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Insider`s Guide Philips ARM&reg;7

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Insider`s Guide Philips ARM®7