WIZ820io User Manual
Contents
1. High Power Down Mode Enable 32 Reset This pin is active low input to initialize or re initialize W5200 It should be held at least 2us after low 5 I nRESET assert and wait for at least 150ms after high de assert in order for PLL logic to be stable SPI Master In Slave Out This pin is used to SPI MISO signal pin 6 O MISO WIZ820io User Manual WIZnet Co Ltd gt W IZnet 3 Device SPI operations WIZ820io is controlled by a set of instruction that is sent from a external host commonly referred to as the SPI Master The SPI Master communicates with W5200 via the SPI bus which is composed of four signal lines Slave Chip Select nSS Serial Clock SCLK MOSI Master Out Slave In and MISO Master In Slave Out The SPI protocol defines four modes for its operation Mode 0 3 Each mode differs according to the SCLK polarity and phase how the polarity and phase control the flow of data on the SPI bus The W5200 operates as SPI Slave device and supports the most common modes SPI Mode 0 and 3 The only difference between SPI Mode 0 and 3 is the polarity of the SCLK signal at the inactive state With SPI Mode 0 and 3 data is always latched in on the rising edge of SCLK and always output on the falling edge of SCLK 3 1 Process of using general SPI Master device Configure Input Output direction on SPI Master Device pins Configure nSCS as High on inactive Write target address2. Wiznet WIZ820io User Manual Version 1 0 W 1Znet 2011 WIZnet Co Ltd All Rights Reserved For more information visit our website at http www wiznet co kr WIZ820io User Manual WIZnet Co Ltd W IZnet Document Revision History Date Revision Changes 2011 09 15 V1 0 Official Release WIZ820io User Manual WIZnet Co Ltd WiZnet 1 Introduction WIZ820io is the internet offload network module that includes W5200 TCP IP hardwired chip include PHY MAG JACK RJ45 with X FMR with other glue logics It can be used as a component and no effort is required to interface W5200 and Transformer The WIZ820io is an ideal option for users who want to develop their Internet enabling systems rapidly For the detailed information on implementation of Hardware TCP IP refer to the W5200 Datasheet WIZ820io consists of W5200 and MAG JACK e TCP IP Ethernet MAC W5200 e Ethernet PHY Included in W5200 e Connector MAG JACK RJ45 with Transformer 1 1 Feature e Supports 10 100 Base TX e Supports half full duplex operation e Supports auto negotiation and auto cross over detection e IEEE 802 3 802 3u Compliance Supports high speed SPI Interface SPI mode 0 3 e Operates 3 3V with 5V I O signal tolerance e Supports network status indicator LEDS Includes Hardware Internet protocols TCP IPv4 UDP ICMP ARP PPPoE IGMP e Includes Hardware Ethernet protocol
3. after the falling edge of the nSS nSCS MODE 14 15 30 31 32 33 34 35 36 37 38 39 4H MODES nm 2 12 13 17 18 19 28 29 RL Li UUU UULUUUUI UU UT UU MISO TE A OCO FOOD ETA 0010 0000 0000 nscs 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 I CLK I SUK 4 bit Data2 e dit Data fr bit Data4 most HEX KKK KKK KK KOKI KH KIKI KAKAK H H miso th 7XEXSKAXEKEX 0 HOW lt Write Sequence gt WIZ820io User Manual WIZnet Co Ltd 9 WiZnet Pseudo Code for Write data of 8bit per packet define data_write_command 0x80 uint16 addr Address 16bits int16 data_len Data length 15bits uint8 data buf Array for data SpiSendData Send data from MCU to W5200 ISR_DISABLE Interrupt Service Routine disable CSoff CS 0 SPI start SpiSendData addr idx amp OxFFOO gt gt 8 Address byte 1 SpiSendData addr idx amp OxOOFF Address byte 2 Data write command Data length upper 7bits SpiSendData data_write_command data_len amp 0x7F00 gt gt 8 Data length bottom 8bits SpiSendData data_len amp OxOOFF Write data On data_len gt 1 Burst Write Processing Mode for int idx 0 idx lt data_len idx SpiSendData data_buf idx CSon CS 1 SPI end IINCHIP_ISR_ENABLE Interrupt Service Routine disable WIZ820io User Manual WIZnet Co Ltd 10 W IZnet 4 Timing diag
4. for transmission on SPDR register SPI Data Register Write OP code and data length for transmission on SPDR register Write desired data for transmission on SPDR register Configure nSCS as Low data transfer start Wait for reception complete AN O u A U NI If all data transmission ends configure nSCS as High 1 2 nes Address ITT ITT OP Code 1bit data length n 16bit Byte Byte lt W5200 SPI Frame Format gt WIZ820io User Manual WIZnet Co Ltd 6 WIZnet nSCS Gi ob 2 dd 6 ee Ri oS AO AZ Id 19 SCLK MmoDEo S8 Address SB Address NOs AE K7 X6 5 XB AE MISO KRA a Address Sequence nScs AH NOORES 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK MOREO g ASB Data Length SB Data Length Kost 0000000000000000 MISO OOOO OOOO OY IXY OO t b OP Data Length Sequence lt Address and OP DATA Length Sequence Diagram gt 3 2 Read processing The READ processing is entered by driving nSS low followed by the Address the OP code the Data Length and the Data byte on MOSI The OP code OP is defined type of the READ OP and WIRTE OP On OP O the read operation is selected Otherwise On OP 1 the write operation is selected In W5200 SPI mode the Byte READ processing and the burst READ processing are provided The Byte READ processing takes 4 instructions which is consist of the 16 bit Addre
5. o User Manual WIZnet Co Ltd 19 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information WIZnet WIZ820io
6. orkmanship under normal use for period of standard ONE 1 YEAR for the WIZ820io module and labor warranty after the date of original retail purchase During this period WIZnet will repair or replace a defective products or part free of charge Warranty Conditions The warranty applies only to products distributed by WIZnet or our official distributors The warranty applies only to defects in material or workmanship as mentioned above in 3 Warranty The warranty applies only to defects which occur during normal use and does not extend to damage to products or parts which results from alternation repair modification faulty installation or service by anyone other than someone authorized by WIZnet damage to products or parts caused by accident abuse or misuse poor maintenance mishandling misapplication or used in violation of instructions furnished by us damage occurring in shipment or any damage caused by an act of God such as lightening or line surge Procedure for Obtaining Warranty Service 1 Contact an authorized distributors or dealer of WIZnet for obtaining an RMA Return Merchandise Authorization request form within the applicable warranty period Send the products to the distributors or dealers together with the completed RMA request form All products returned for warranty must be carefully repackaged in the original packing materials 3 Any service issue please contact to sales wiznet co kr WIZ820i
7. ram 4 1 Reset Timing DD pp nRST I Tpi I PLOCK Internal UA Symbol Description Min Max TRC Reset Cycle Time 2 US TPL nRST internal PLOCK 150 ms WIZ820io User Manual WIZnet Co Ltd 11 W IZnet 4 2 SPI Timing Vin i aScS y DJ LI Kk Vin SCLK Hi IL Toe T Ds CEN MOSI y ZO VEN TPT Tov KL Co MISO Symbol Description Min Max Units Fsck SCK Clock Frequency 80 MHz TwH SCK High Time 6 ns Tw SCK Low Time 6 ns Tes nSCS High Time 5 ns Tess nSCS Hold Time 5 ns Tesh nSCS Hold Time 5 ns Tos Data In Setup Time 3 ns Tou Data In Hold Time 3 ns Tov Output Valid Time 5 ns Tou Output Hold Time 0 ns Terz nSCS High to Output Hi Z 5 ns 12 WIZ820io User Manual WIZnet Co Ltd WiZnet 5 Dimensions Symbol Dimension mm Symbol Dimension mm A 23 00 G 1 34 B 20 32 2 54 x 8 H 2 50 0 50 E 1 34 I 6 40 D 2 11 J 2 54 E 16 10 K 5 80 F 2 11 L 25 00 WIZ820io User Manual WIZnet Co Ltd 13 WIZnet 6 Reference Schematics WIZ820io User Manual WIZnet Co Ltd WIZnet 7 Warranty WIZnet Co Ltd offers the following limited warranties applicable only to the original purchaser This offer is non transferable WIZnet warrants our products and its parts against defects in materials and w
8. s DLC MAC Supports 8 independent connections simultaneously Supports Power down mode Supports Wake On LAN Supports Socket API for easy application programming e Interfaces with two 2 54mm pitch 1 x 6 header pin e Very small form factor 23mm x 25mm PCB size WIZ820io User Manual WIZnet Co Ltd 3 WiZnet 2 Pin assignment amp description 2 1 Pin assignment ee en lt TOP side view gt GND A 3V3D O 3V3D O PWDN O nRESET C MISO 7 Mae lt Pin assignment gt WIZ820io User Manual WIZnet Co Ltd 4 WI IZnet 2 2 Pin description Pin No I O Pin Name Description 1 P GND Ground 2 P GND Ground SPI Master Out Slave In This pin is used to SPI MOSI signal pin 3 I MOSI SPI Clock This pin is used to SPI Clock Signal pin 4 I SCLK SPI Slave Select Active Low 5 I nSS This pin is used to SPI Slave Select signal J1 Pin when using SPI interface Interrupt Active low This pin indicates that W5200 requires MCU attention after socket connecting disconnecting data receiving timeout and WOL Wake on LAN The interrupt is cleared by writing IR Register or Sn IR Socket n th Interrupt Register All 6 O nINT interrupts are maskable GND Ground 2 P 3V3D Power 3 3 V power supply 3 P 3V3D Power 3 3 V power supply Power Down Active High This pin is used to power down pin 4 I PWDN Low Normal Mode Enable
9. ss the 1 bit OP code 0x0 the 15 bit Data length and 8 bit Data Otherwise The Burst READ processing only takes the Data instruction after the setting of the burst read processing To distinguish between the Byte READ and the burst READ processing the Data length is used If the Data length is 1 the Byte READ processing is operated Otherwise the Burst READ Processing is operated when the Data length is more than two The MISO pin should be selected by driving MISO low after the falling edge of the nSS WIZ820io User Manual WIZnet Co Ltd I MODES 0 1 2 12 13 14 15 17 18 19 28 29 30 31 32 33 34 35 36 37 38 39 l I I 16 bit Address OP Data Length 1bit 15bit A 8 bit Data Vel AH COREA KEKE EIA MISO inch AKKKKKA HAKKKKKKKKKKKK HA KAKAK KAKAK KK nscs J 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 i I SCLK _ bit Data2 Yi Data3 bit Data4 I I most 1 7 C3 XA KIKEKT KOK NENEKAKEKEKTKONTIKENENEXEXENT XO nso TAX RK KKK KKK KH KEKE KK e lt Read Sequence gt Pseudo Code for Read data of 8bit per packet define data_read_command 0x00 uint16 addr Address 16bits int16 data len Data length 15bits uint8 data_buf Array for data SpiSendData Send data from MCU to W5200 SpiRecvData Receive data from W5200 to MCU ISR_DISABLE Interrupt Service Routine disable CSoff CS 0 SPI start SpiSendData SpiSendDa
10. ta addr idx amp OxFF00 gt gt 8 Address byte 1 SpiSendData addr idx amp OxOOFF Address byte 2 Data write command Data length upper 7bits SpiSendData data read command data len amp 0x7F00 gt gt 8 Data length bottom 8bits SpiSendData data_len amp Ox00FF Read data On data_len gt 1 Burst Read Processing Mode for int idx 0 idx lt data_len idx WIZ820io User Manual WIZnet Co Ltd 8 WIZnet SpiSendData 0 Dummy data data buffidxJ SpiRecvData idx Read data CSon CS 1 SPI end ISR ENABLE Interrupt Service Routine disable 3 3 3 Write processing The WRITE processing is entered by driving nSS low followed by the Address the OP code the Data Length and the Data byte on MISO In W5200 SPI mode the Byte WRITE processing and the Burst WRITE processing are provided The Byte WRITE processing takes 4 instructions which is consist of the 16 bit Address the 1 bit OP code 0x1 the 15 bit Data length and 8 bit Data Otherwise The Burst WRITE processing only takes the Data instruction after the setting of the Burst WRITE processing To distinguish between the Byte WRITE and the Burst WRITE processing the Data length is used If the Data length is 1 the Byte WRITE processing is operated Otherwise the Burst WRITE Processing is operated when the Data length is more than two The MOSI pin should be selected by driving MOSI low
Download Pdf Manuals
Related Search