RZ/A1H Group Capture Engine Unit Sample Program
Contents
1. CS3 space 64MB CS3 mirror space CS2 space 64MB CS2 mirror space CS1 space 64MB CS1 mirror space CSO space 64MB CSO mirror space Others 502MB Others 502MB Large capacity on chip RAM 10MB Large capacity on chip RAM 10MB SPI multi I O bus space 2 64MB Serial flash memory 64MB SPI multi I O bus space 1 64MB Serial flash memory 64MB CS5 space 64MB CS4 space 64MB User area CS3 space 64MB SDRAM 64MB CS2 space 64MB SDRAM 64MB CS1 space 64MB NOR flash memory 64MB CSO space 64MB RENESAS NOR flash memory 64MB Page 9 of 26 RZ A1H Group 6 2 1 Capture Engine Unit Sample Program Section Assignment in Sample Code In this sample code the exception processing vector table and the IRQ interrupt handler are assigned to the large capacity on chip RAM and they are executed in such RAM to speed up the interrupt processing The transfer processing from the NOR flash memory area which is the program code of the exception processing vector table and the IRQ interrupt handler to the large capacity on chip RAM area the clear to zero processing for the data selection without initial data and the initialization for the data selection with initial data are executed by using the scatter loading function Refer to Image structure and generation in ARM Compiler toolchain Using the Linker provided by the2. RZ A1H Group Capture Engine Unit Sample Program 6 Software 6 1 Operational Overview Using the CEU this sample program transfers image data from the camera module to the on chip RAM After capturing one frame it converts the data On the VDC5 the conversion results become samples which can be displayed on the LCD The camera module MT9V024 for this sample program is an image sensor which does not have R G and B values for each pixel Image data from this camera module cannot therefore be displayed on the LCD without processing Thus by using brightness information for each pixel the sample program processes image data to display 256 gradation monochrome data on the LCD 6 1 1 Data capture timing FRAME VALID LINE VALID connected with VIO VD VIO HD provides interface with the camera module MT9V024 Data is captured in data enable fetch mode of the CEU Data is captured through the CEU when VIO HD is asserted set to high while VIO VD is being high Figure 6 1 and Table 6 1 show the timing when image data from the camera module MT9V024 is output VIO VD FRAM VALID LINE VALID Figure 6 1 Row Timing and FRAME VALID LINE VALID Signal Table 6 1 Frame Time Parameter Name Default Timing A Active data time 752 pixel clocks P1 Frame start blanking 72 pixel clocks P2 Frame end blanking 23pixelclocks Q Horizontal blanking 94 pixel clocks 6 1 2 Conversion of 10 bit data in
3. ARM for more information about the scatter loading function Table 6 2 and Table 6 3 list the Sections to be Used in this sample code Figure 6 3 shows the Section Assignment for the initial condition of the sample code and the condition after using the scatter loading function Table 6 2 Area Name VECTOR TABLE Sections to be Used 1 2 Description Exception processing vector table Loading Area Execution Area RESET HANDLER Program code area of reset handler processing This area consists of the following sections e INITCA9CACHE L1 cache setting e INIT TTB MMU setting e RESET HANDLER Reset handler CODE BASIC SETUP Program code area to optimize operating frequency and flash memory InRoot This area consists of the sections Code FLASH FLASH located in the root area such as C and standard library RO Data CODE FPU INIT Program code area for NEON and Code FLASH FLASH CODE RESET VFP initializations This area consists of the following sections e CODE FPU INIT e FPU INIT Program code area for hardware initialization This area consists of the following sections e CODE_RESET Startup processing e INIT_VBAR Vector base setting CODE IO REGRW Program code area for read write functions of I O register CODE Program code area for defaults All the Code type sections which do not define section names with C source are assigned in this area Constant data
4. Page 13 of 26 RZ A1H Group Capture Engine Unit Sample Program 6 3 Interrupts Table 6 5 shows interrupts for the sample code Table 6 5 Interrupts for the Sample Code ieu source lb Priory INTC ID CEUI 1 frame capture end report 6 4 Fixed Width Integers Table 6 6 shows the Fixed Width Integers Used in Sample Code Table 6 6 Fixed Width Integers Used in Sample Code bool t Boolean type value true 1 or false 0 int t High speed integer signed 32 bit integer in this sample code int8 t 8 bit integer singed Defined by standard library int16 t 16 bit integer singed Defined by standard library int32 t 32 bit integer singed Defined by standard library intc4 t 64 bit integer singed Defined by standard library uint8 t 8 bit integer unsigned Defined by standard library uinti6 t 16 bit integer unsigned Defined by standard library uint32 t 32 bit integer unsigned Defined by standard library uint64 t 64 bit integer unsigned Defined by standard library float32 t 32 bit floating point Defined by standard library when specifying ARM NEON float64_t 64 biy floating point Defined by standard library Defined by standard library when specifying ARM NEON float128 t 128 bit floating point RO1AN1824EJ0100 Rev 1 00 Page 14 of 26 May 28 2014 RENESAS RZ A1H Group p 5 List of Constants and Error Codes Table 6 7 lists the constants for the sample program Tab
5. area for defaults All the RO Data type sections which do not define section names with C source are assigned in this area R01AN1824EJ0100 Rev 1 00 May 28 2014 RENESAS RO Data Page 10 of 26 RZ A1H Group Table 6 3 Area Name VECTOR MIRROR TABLE Capture Engine Unit Sample Program Sections to be Used 2 2 Description Exception processing vector table Section to transfer data to large capacity on chip RAM Type Loading Area Execution Area CODE HANDLER JMPTBL Program code area for user defined functions of IRQ interrupt handler CODE HANDLER Program code area of IRQ interrupt handler This area consists of the following sections e CODE HANDLER e RQ FIQ HANDLER DATA HANDLER JMPTBL Registration table data area for user defined functions of IRQ interrupt handler RW Data ARM LIB STACK Application stack area Zl Data IRQ STACK IRQ mode stack area Zl Data LRAM FIQ STACK FIQ mode stack area Zl Data LRAM SVC STACK Supervisor SVC mode stack area Z Data LRAM ABT STACK Abort ABT mode stack area Zl Data TTB ARM LIB HEAP MMU translation table area Application heap area Zl Data Zl Data DATA VRAM Data area with initial value for defaults All the RW Data type sections which do not define section names with C source are assigned in this area Data area without initial value for defaults All the ZI D
6. 0 H O3FF FFFF H 4000 0000 DATA HANDLER JMPTBL H 20A0 0000 Large capacity on chip RAM CODESPANDEER H 2000 0000 10MB CODE_HANDLER_JMPTBL Transfer program CONST code which requires CONST speeding up to on chip RAM H 1C00 0000 CODE CODE H 1800 0000 CODE IO REGRW CODE IO REGRW CODE RESET CODE RESET CODE FPU INIT CODE FPU INIT H 1000 0000 InRoot InRoot H 0C00 0000 CODE BASIC SETUP CODE BASIC SETUP H 0800 0000 RESER HANDLER RESER HANDLER Transfer exception H 0000 0200 processing vector to i on chip RAM H 0400 0000 H 0000 0100 VECTOR MIRROR TABLE E H 0000 0000 H 0000 0000 VECTOR TABLE VECTOR TABLE Figure 6 3 Section Assignment RO1AN1824EJ0100 Rev 1 00 Page 12 of 26 May 28 2014 RENESAS RZ A1H Group 6 unit should be 1MB when customizing the MMU based on the system Table 6 4 2 2 Setting for MMU Capture Engine Unit Sample Program The MMU is set to manage the 4 GB area in 1MB unit from the address H 0000 0000 in response to the memory map of the hardware resource used for the GENMAI board Set by the ttb init s file The minimum Table 6 4 lists the Setting for MMU Definition Name M SIZE NOR Setting for MMU Contents CSO and CS1 spaces NOR flash memory Address H 0000 0000 to H O7FF FFFF Memory Type L1 cache enable Normal
7. 16 bit booting Board used GENMAI board RTK772100BC00000BR R7S72100 CPU board RTK7721000B00000BR Option board for the R7S72100 CPU board Device used functionality to be Camera module I F option board J17 used on the board MT9V024 1 3 inch Wide VGA Digital Image Sensor 752H x 480 V 10 bit column parallel Display Out Analog RGB D sub 15 Option board J16 Serial interface connected with a Dsub 9 connector Note The operating frequency used in clock mode 0 Clock input of 13 33MHz from EXTAL pin RO1AN1824EJ0100 Rev 1 00 Page 4 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 3 Related Application Notes For additional information associated with this document refer to the following application note RZ A1H Group Example of Initialization ROI AN1864EJ RZ A1H Group Video Display Controller 5 VDC5 Sample Driver RO1 AN1822EJ RZ A1H Group I O definition header file lt iodefine h gt R01 AN1860EJ 4 Peripheral Functions The basic functions of the CEU and VDC4 are described in the RZ A1H Group User s Manual Hardware R01AN1824EJ0100 Rev 1 00 Page 5 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 5 Hardware 5 1 Hardware Configuration Figure 5 1 shows Examples of Hardware Devices Connected CAMERA MT9V024 CEU On chip RAM PIXCLK Capture FLAME_VALID Buffer LINE_VALID DOUTS 0 RESET_BAR Figure 5 1 Exampl
8. 21 NE S AS APPLICATION NOTE RZ A1H Group R01AN1824EJ0100 Rev 1 00 Capture Engine Unit Sample Program Mav 28 2014 Introduction This application note describes the program which captures image data from an external camera module and transfers the data to memory by using the RZ AIH s Capture Engine Unit CEU Capture Engine Unit Sample Program offers the following features e Captures image data a single frame from the camera module e Uses the data enable fetch mode for capturing image data e Connects to the camera module via 16 bit I F Note that the low order 10 bits constitute effective data on the camera module e Converts the 10 bit data into 8 bit data by software processing which treats the high order 8 bits as effective data e Always uses the A side of the CEU registers e Uses the Video Display Controller 5 VDC5 to display 8 bit data as conversion results on the LCD e Displays a monochrome LCD image through the VDC5 CLUT Target Device RZ A1H When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN1824EJ0100 Rev 1 00 Page 1 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program Contents PEE Ouen 3 2 Operation Confirmation Conditions sssssssssssssseseen enne en nentes nnns nenne
9. FrameBuffer CEU SAMPLE CeuConvertbitRgbData uint32 t g ceu complete flag 1 frame capture end report uint32 t g ceu error flag Unused interrupt report 6 7 List of Functions Table 6 10 shows List of Functions Table 6 10 List of Functions Function name RH CEU Modulelnit CEU SAMPLE CeuSingleCapture CEU SAMPLE CeuSingleCapture Page number 18 R CEU Configlnit R CEU SetMemoryAddress 18 R CEU CallbackISR RH CEU CaptureStart R CEU InterruptEnable R CEU InterruptDisable CEU SAMPLE CeuSingleCapturelnit CEU SAMPLE CeuSingleCapture CEU SAMPLE CeuConvert8bitRgbData R01AN1824EJ0100 Rev 1 00 May 28 2014 RENESAS Page 17 of 26 RZ A1H Group Capture Engine Unit Sample Program 6 8 Function Specifications This section contains the specifications for the functions that are implemented in the sample code 6 8 1 R CEU Modulelnit R CEU Modulelnit Synopsis CEU module pre initialization Header r ceu h Declaration void R CEU Modulelnit void init func void Description In this function the operations are performed as below The specified user defined function is executed Clock supply to CEU is enabled Arguments init func Pointer to the user defined function Return value None 6 8 2 R CEU COonfiglnit R_CEU_ConfigInit Synopsis CEU module initialization Header r_ceu h Declaration void R_CEU_ConfigInit void Description In this function t
10. SWAP CEU DATAOUT _ SWAP ENABLE CEU DATAOUT _ SWAP ENABLE Capture Data Output Control Register CDOCR COLS Swap of 32 bit units Capture Data Output Control Register CDOCR COWS Swap of 16 bit units CEU CONFIG 8BIT DATA SWAP CEU DATAOUT _ SWAP DISABLE Capture Data Output Control Register CDOCR COBS Swap of 8 bit units CEU CONFIG CEU SIGNAL Capture Interface Control Register CAMERA SIGNAL HIGH ACTIVE CAMCR VDPOL POLARITY VD Polarity of the sync signal positive polarity CEU CONFIG CEU SIGNAL Capture Interface Control Register CAMERA SIGNAL HIGH ACTIVE CAMCR HDPOL POLARITY HD Polarity of the sync signal positive polarity R01AN1824EJ0100 Rev 1 00 May 28 2014 Page 15 of 26 RENESAS RZ A1H Group Capture Engine Unit Sample Program CEU CONFIG CEU SINGLE Capture Control Register CAPTURE MODE CAPTURE CAPCR CTNCP frame capture mode Table 6 8 Error Codes for the Sample Code CEU ERROR OK Success CEU ERROR PARAM E Parameter error R01AN1824EJ0100 Rev 1 00 Page 16 of 26 May 28 2014 RENESAS RZ A1H Group 6 6 List of Variables Table 6 9 lists the static variables Table 6 9 static Variables Contents CEU capture buffer for captured image data Variable Name CaptureBuffer uint16 t Capture Engine Unit Sample Program Function Used CEU SAMPLE CeuConvertbitRgbData VDC5 LCD display buffer for output from the VDC5 uint8 t
11. ata type sections which do not define section names with C source area assigned in this area Display Buffer RW Data Zl Data CEU BUFFER Capture Buffer Notes 1 FLASH and LRAM shown in Loading Area and Execution Area indicate the NOR flash memory area and the large capacity on chip RAM area respectively 2 Basically the section name is set to be the same as the region s however it consists of some sections in the areas of RESET HANDLER InRoot CODE FPU INIT CODE RESET CODE CONST CODE HANDLER DATA and BSS Refer to the ARM compiler toolchain manual about the region and the section R01AN1824EJ0100 Rev 1 00 May 28 2014 RENESAS Page 11 of 26 RZ A1H Group Capture Engine Unit Sample Program RZ A1H group Section assignment Section assignment Address space Load view Execution view Memory allocation after H FFFF FFFF H 209F FFFF executing scatter loading Clear to zero Initialize data with initial value H 200B 8000 ARM_LIB_HEAP H 2003 8000 Secure area such H 2003 4000 as stack area H 2003 2000 ABT STACK H 2003 0000 SVC STACK H 2002 E000 FIQ STAC H 2002 C000 IRQ STACK TTB H 2002 4000 ARM LIB STACK Initialize data with initial value DATA HANDLER JMPTBL CODE HANDLER H 2002 0100 CODE HANDLER JMPTBL H 2002 0000 VECTOR MIRROR TABLE H 2000 000
12. chain ARM DS 5 etc can be downloaded from the ARM website The latest version can be downloaded from the Renesas Electronics website R01AN1824EJ0100 Rev 1 00 Page 23 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN1824EJ0100 Rev 1 00 Page 24 of 26 May 28 2014 RENESAS REVISISON HISTORY RZ A1H Group Capture Engine Unit Sample Program Description Summary May 28 2014 First edition issued All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an in
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14. e and is transferred to memory by using the RZ A1H s Capture Engine Unit CEU The data is displayed on the LCD by VDC5 It is converted by the software and is displayed by VDC5 on the LCD Table 1 1 shows Peripheral Functions and Their Applications Table 1 1 Peripheral Functions and Their Applications Peripheral Functions Application CEU Captures image data INTC interrupt ID CEUI 364 CEU interrupt VDC5 ch1 layer 2 Displays an image on the LCD R01AN1824EJ0100 Rev 1 00 Page 3 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 2 Operation Confirmation Conditions The sample code accompanying this application note has been run and confirmed under the conditions below Table 2 1 Operation Confirmation Conditions MCU used RZ A1H Operating frequency CPU clock I 400MHz Image processing clock Go 266 67MHz Internal bus clock Bo 133 33MHz Peripheral clock 1 P14 66 67MHz Peripheral clock 0 P06 33 33MHz Operating voltage Power supply voltage I O 3 3V Power supply voltage Internal 1 18V Integrated development ARM integrated development environment environment ARM Development Studio 5 DS 5 Version 5 16 C compiler ARM C C Compiler Linker Assembler Ver 5 03 Build 102 Compiler options excluding additional directory path O3 Ospace cpu Cortex A9 littleend arm apcs interwork no unaligned access fpu vfpv3 fp16 g asm Operating mode Boot mode 0 CSO space
15. e eee eet ertt RE DIRE Ru a EXON a EEUU RR QR eben 18 6 8 2 R CEU Conigli sssri tertie exte eth aene en ee og RR Rao e aeXRi do e RARI an e RR aae AREAS eX ada 18 06 8 0 R CEU SetMemoryAddress i cte eterne eei rt tad anta Rena ku eV n nu pra gn ua RE uae 18 68 4 R CEU CallbacklSR eret ien tease peor E HR FR adS a XR RU HERE aaa Eaa 19 6 8 5 R CEU CaptureSIart vise uci ettet ettet pde ee auk Ga ea eaae daga nee Axa tu rada erbe nra ca eR Edd 19 6 86 R_ CEU InterruptEnable teint thure eene Ente kan Ene on RR S Enron ARR on eae AR AARAA 19 6 87 R CEU InterruptDisable cette ennt nn tn nn n rn e en n rn xa da a 19 6 8 8 CEU SAMPLE CeuSingleCapturelnit ssssssssseeeneee enne 20 6 8 9 CEU SAMPLE CeuSingleCapture esses nnne nne nnn snnt nennen 20 6 8 10 CEU SAMPLE _CeuConvert8bitRgbData esses enne 21 6 9 le eiit M 22 6 9 1 Main Processing ieri erint lect E itc dris ena dee uie as 22 7 Sample Code sien iiiki aiian dyads ipic epp ee A aiana Huan ERR Pena tege Ree ERE aeu ep aaa euge ERE ERE oie 23 8 Documents for Reference ccecseccceesenceeeeeeeee teense ERA Aa ERE 23 R01AN1824EJ0100 Rev 1 00 Page 2 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 1 Specifications The sample code in this application note One frame of Image data is captured from an external camera modul
16. es of Hardware Devices Connected R01AN1824EJ0100 Rev 1 00 Page 6 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 5 2 Pins Used Table 5 1 lists Pins Used and Their Functions Table 5 1 Pins Used and Their Functions Pin Name Function VIO CLK 6th alternative function PIXCLK on the camera VIO VD 6th alternative function FLAME VALID on the camera VIO HD 6th alternative function LINE VALID on the camera General purpose output RESET BAR on the camera VIO DO 6th alternative function DOUTO on the camera VIO D1 6th alternative function DOUT1 onthe camera VIO D2 6th alternative function DOUT2 on the camera 6th alternative function on the camera 6th alternative function on the camera 6th alternative function on the camera eth alternative function on the camera TR JR J BS ES ES SS fF PL J LS YS Y SS YS YS P10 11 Input VIO D7 6th alternative function DOUT7 onthe camera P10 12 Input VIO D8 6th alternative function DOUT8 onthe camera P10 13 Input VIO D9 6th alternative function DOUT9 onthe camera P10 14 NC General purpose output low P10 15 NC General purpose output low P11 0 NC General purpose output low P11 1 NC General purpose output low P11 2 NC General purpose output low P11 3 NC General purpose output low R01AN1824EJ0100 Rev 1 00 Page 7 of 26 May 28 2014 RENESAS
17. he operations are performed as below CEU setting for the camera module as below Camera APTINA MT9V024 Spec VD HD signal polarity Active high Bus width 10 bits Pixel output timing Data fetch mode Blank period 0 HD Active pixels 752 H x 480 V Arguments None Return value None 6 8 3 R_CEU_SetMemoryAddress R_CEU_SetMemoryAddress Synopsis The function which sets the address of capture data buffer Header r_ceu h Declaration ceu error tH CEU SetMemoryAddress uint32 t addr Description In this function the operations are performed as below The address of a capture data buffer is set The buffers must be 4 byte boundaries Arguments addr The address of a capture data buffer Return value Error code R01AN1824EJ0100 Rev 1 00 Page 18 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 6 8 4 R CEU CallbacklSR R CEU CallbackISR Synopsis CEU driver set interrupt callback function Header r ceu h Declaration void R CEU CallbacklSR void callback uint32 t Description In this function the operations are performed as below Setting interrupt callback function Arguments callback Pointer to the user defined function Return value None 6 8 5 R CEU CaptureStart R CEU CaptureStart Synopsis The function which start capture Header r ceu h Declaration void R CEU CaptureStart void Description In this function the operations are performed as below This function star
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19. laration void Graphics CeuSingleCapture uint16 t pCapBuff Description In this function the operations are performed as below R CEU SetMemoryAddress Function call R CEU CaptureStart Function call Wait for end of capture Arguments pCapBuff Pointer of capture buffer Return value None RO1AN1824EJ0100 Rev 1 00 Page 20 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 6 8 10 CEU SAMPLE CeuConvert8bitRgbData Graphics CeuConvert8bitRgbData Synopsis Conversion of 16 bit data to 8 bit data Header ceu sample h Declaration void Graphics CeuConvert8bitRgbData uint16 t pSrcBuff uint8 t pDstBuff uint16 t stride Description This function is converted to 8 bit data from 16 bit data CEU is 16 bit mode Camera APTINA MT9V024 is 10bit bus width Capture data is as follows 16bit Data 1 pixel 1 pixel e 1 pixel 0000 00XX XXXX XXxx 0000 00XX XXXX XXxx 0000 00XX XXXX XXxx higher 8 bits bit 10 2 are effective 8bit Data 1pixel pixel pixel XXXX XXXX XXXX XXXX XXXX XXXX Arguments pSrcBuff capture data 16 bit bus width pDstBuff VRAM buffer 8 bit data after conversion stride pDstBuff stride Return value None RO1AN1824EJ0100 Rev 1 00 Page 21 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 6 9 Flowcharts 6 9 1 Main Processing Figure 6 4 shows the main processing described in this app
20. le 6 8 lists the error codes for the sample code Table 6 7 Constants for the Sample Program Constant Capture Engine Unit Sample Program Description CEU CONFIG 752u Horizontal effective data area for Camera module CAPTURE_SCREEN_ In this sample don t change value HSYNC NUM PXL CEU CONFIG 480u Vertical effective data area for Camera module In CAPTURE SCREEN this sample don t change value VSYNC NUM PXL CEU INTERRUPT 5u CEU interrupt priority PRIORITY CAPTURE_END tu 1 frame capture end flag CEU_CAPTUER_ BUFF_STRIDE CEU CONFIG CA PTURE SCREEN H SYNC NUM PXL 31u amp 0x001Fu CEU capture buffer stride 32 byte unit CEU CAPTUER BUFF HEIGHT CEU CONFIG CAPT URE SCREEN VSY NC NUM PXL Height of capture buffer CEU BURST MODE X1 Ou Data transfer unit to the bus bridge Transfer to bus 32 bytes CEU_SIGNAL_ HIGH_ACTIVE Ou Polarity of the sync signal positive polarity CEU_SIGNAL_ LOW_ACTIVE 1u Polarity of the sync signal negative polarity CEU DATAOUT _ SWAP DISABLE Ou Data is not swapped CEU_DATAOUT_ SWAP_ENABLE du Data is swapped CEU_INT_ ONE_FRAME_ CAPTUER_END 0x00000001uL One Frame Capture End Interrupt Enable CEU CONFIG BURST MODE CEU BURST MODE X1 Capture Control Register CAPCR MTOM 0 Transferred to the bus in 32 byte units CEU CONFIG 32BIT DATA SWAP CEU CONFIG 16BIT DATA
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22. lication note o T omm T o Sn T o T secures T omm T 5 E CEU Initialization B 6 g CEU Single Caputure Start 7 a Capture data Convert E Figure 6 4 Main Processing 1 5 CEU initialization 6 Capturing one frame image data output from the camera 7 Converts the data captured Transfers it to the display buffer memory RO1AN1824EJ0100 Rev 1 00 Page 22 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 7 Sample Code The sample code is available on the Renesas Electronics Website 8 Documents for Reference User s Manual Hardware RZ A1H Group User s Manual Hardware The latest version can be downloaded from the Renesas Electronics website R7S72100 RTK772100BC00000BR GENMAI User s Manual The latest version can be downloaded from the Renesas Electronics website R7S72100 CPU GENMAJ Optional Board RTK7721000B00000BR User s Manual The latest version can be downloaded from the Renesas Electronics website ARM Architecture Reference Manual ARMv7 A and ARMv7 R edition Issue C The latest version can be downloaded from the ARM website ARM Generic Interrupt Controller Architecture Specification Architecture version 1 0 The latest version can be downloaded from the ARM website Technical Update Technical News The latest information can be downloaded from the Renesas Electronics website User s Manual Development Tools ARM Software Development Tools ARM Compiler tool
23. memory M SIZE SDRAM CS2 and CS3 spaces SDRAM H 0800 0000 to H OFFF FFFF L1 cache enable Normal memory M SIZE CS45 CS4 and CS5 spaces H 1000 0000 to HH7FF FFFF Strongly ordered memory L1 cache disable M SIZE SPI SPI multi IO bus space 1 and 2 serial flash memory H 1800 0000 to HHMFFF FFFF L1 cache enable Normal memory M SIZE RAM Large capacity on chip RAM space H 2000 0000 to H 209F FFFF L1 cache enable Normal memory M SIZE IO 1 On chip peripheral module and reserved area H 20A0 0000 to H SFFF FFFF Strongly ordered memory L1 cache disable M M SIZE NOR M M SIZE SDRAM CSO and CS1 mirror spaces CS2 and CS3 mirror spaces H 4000 0000 to H 47FF FFFF H 4800 0000 to H AFFF FFFF L1 cache disable Normal memory L1 cache disable Normal memory M SIZE C845 M CS4 and CS5 mirror spaces H 5000 0000 to H 57FF FFFF Strongly ordered memory L1 cache disable M SIZE SPI M SPI multi IO bus mirror space 1 and 2 H 5800 0000 to H 5FFF FFFF L1 cache disable Normal memory M SIZE RAM M Large capacity on chip RAM mirror space H 6000 0000 to H 609F FFFF L1 cache disable Normal memory M SIZE IO 2 On chip peripheral module and reserved area R01AN1824EJ0100 Rev 1 00 May 28 2014 H 60A0 0000 to H FFFF FFFF RENESAS 2550MB Strongly ordered memory L1 cache disable
24. n 4 3 Related Application Notes sesira E EE nn nnne ensi er nnne nrtr inneren nitens 5 4 JPernpherabFUurctiols ott io Dee iso eei ene eet paca S 5 b JBardware iiec ERRORS NN EUREN aaa aa ear ERRORS ESL a URD snseccenestumsacecdeunas osacenedecetias 6 5 1 Hardware Configuration is 2 eerte etn fretta edd tere et nett esee en a LU Y epe an eines 6 5 2 PINS USOC EE 7 Gi SOMWALG seniii E a AEAEE A E 8 6 1 Operational OVEMIOW sisis asantas ia aatan Aiea eaa aa aaa Eaa aaia adios aieeaa adah 8 6 1 1 Dette Capote timing ses A R T x Pure Ra Er n 8 6 1 2 Conversion of 10 bit data into 8 bit data ssssssssssseeeseneeeeen nnns 8 6 2 Memon urisenmcc cas sh cece aoc xd accep cite va xeag dec saGeevace acidic sade seacdecasagecdeesacraeesecdunays 9 6 2 1 Section Assignment in Sample Code ssssssssssssssseeeee enne 10 6 2 2 Setting tor MM iet d eene uet REOR esie eng aeie tee nb Proper beredis 13 6 3 nire Y 14 6 4 Fixed Widtli Integets s 1 2 ierit eter E melon steep oe 14 6 5 List of Constants and Error CodeS cre ient Cette aedes ue taut be eed Git tanec 15 6 6 Histor Variables uo pene R an tient ees eund 17 6 7 EISEOT FURCEOFIS cte terrere eren en hen exer gua deg et ex reir pa ve Ue Fee vete pue su gra egere gag EE 17 6 8 Function Specifications eese sess aaa Taa a ensi a R enne sinn sss n tnnt nnne neas 18 68 1 AR GEU Modulelnit r
25. nductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicab
26. nesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transpor
27. put signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is onl
28. tation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which itis not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semico
29. to 8 bit data This sample program captures the low order 10 bits of the 16 bit I F as effective data from the camera module MT9V024 It converts these 10 bits of data into 8 bit data to display 256 gradation monochrome data R01AN1824EJ0100 Rev 1 00 Page 8 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 6 2 Memory Mapping Figure 6 2 shows the Address Space of the RZ A1H group and the Memory Mapping of the GENMAI board In this sample code the code and data used in the ROM area is located in the NOR flash memory connected to the CSO space and the code and data used in the RAM area is located in the large capacity on chip RAM Figure 6 2 R01AN1824EJ0100 Rev 1 00 May 28 2014 Mirror space Normal space Memory Mapping H FFFF FFFF H 60A0 0000 H 6000 0000 H 5C00 0000 H 5800 0000 H 5000 0000 H 4C00 0000 H 4800 0000 H 4400 0000 H 4000 0000 H 20A0 0000 H 2000 0000 H 1C00 0000 H 1800 0000 H 1000 0000 H 0C00 0000 H 0800 0000 H 0400 0000 H 0000 0000 RZ A1H group Address space Others 2550MB GENMAI board Memory map Others 2550MB Large capacity on chip RAM 10MB Large capacity on chip RAM mirror space SPI multi I O bus space 2 64MB SPI multi I O bus mirror space 2 SPI multi I O bus space 1 64MB SPI multi I O bus mirror space 1 CS5 space 64MB CS4 space 64MB CS5 mirror space CS4 mirror space
30. ts CEU capture Arguments None Return value None 6 8 6 R CEU InterruptEnable R CEU InterruptEnable Synopsis The function which enables interrupt for data enable capture mode Header r ceu h Declaration void R CEU InterruptEnable uint32 t flag Description In this function the operations are performed as below This function enables CEU interrupt Arguments Flag CEIER reg set value Return value None 6 8 7 R CEU InterruptDisable R CEU InterruptDisable Synopsis The function which disables interrupt for data enable capture mode Header r ceu h Declaration void R CEU InterruptDisable void Description In this function the operations are performed as below This function disables CEU interrupt Arguments None Return value None R01AN1824EJ0100 Rev 1 00 Page 19 of 26 May 28 2014 RENESAS RZ A1H Group Capture Engine Unit Sample Program 6 8 8 CEU SAMPLE CeuSingleCapturelnit Graphics CeuSingleCapturelnit Synopsis CEU module initialization Header ceu sample h Declaration void Graphics CeuSingleCapturelnit void Description In this function the operations are performed as below R CEU Modulelnit Function call R CEU Oonfiglnit Function call R CEU CallbackISR Function call R CEU InterruptEnable Function call Registration of the interrupt function Arguments None Return value None 6 8 9 CEU SAMPLE CeuSingleCapture Graphics CeuSingleCapture Synopsis CEU Single Capture Start Header ceu sample h Dec
31. y released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Re
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