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660x Register-Level Programmer Manual

1. Address Offset 0x016 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 Serial SW Serial Serial HW Serial Start Strobe Timebase Enable 7 6 5 4 3 2 1 0 OE7 OE 6 OE5 OE 4 OE 3 OE 2 OE 1 OE 0 Bits Name Description 11 Serial SW Strobe Serial Software Strobe When HW Serial is disabled Serial SW Strobe can toggle the serial clock 10 Serial Timebase 0 Serial clock is Timebase 1 24 1 2 us 1 Serial clock is Timebase 2 100 KHz 9 Serial HW Enable Serial Hardware Enable Setting this bit enables hardware parallel to serial conversion Setting this bit causes serial clock to be driven on STC DOUT 4 and serial data out to be driven on STC DOUT 0 8 Serial Start Setting Serial Start initiates parallel to serial conversion of the Serial DOUT register starting with bit O It also captures serial input into the serial input register This bit automatically clears when the conversion completes The Serial I O Progress bit can monitor the conversion progress 7 0 OE lt 7 0 gt Output Enable These bits control the output enable for the STC DIO lines when using I O pins 7 through 0 if these pins are programmed as inputs in the I O configuration registers This setting makes the port compatible with the DAQ STC The I O configuration registers also control the output enables in which case these bits are ignored 660x Register Level Programmer Manual 3 38 ni com
2. Chapter 3 Register Maps STC DIO Serial Input Address Offset 0x038 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 Serial Serial Serial Serial Serial Serial Serial Serial DIN 7 DIN 6 DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN O Bits Description National Instruments Corporation 7 0 Serial DIN lt 7 0 gt Serial Digital Input These bits store the serial input data after hardware serial to parallel conversion completes 3 39 660x Register Level Programmer Manual Chapter 3 Register Maps 1 0 Connection Registers The NI TIO has a 40 pin I O connector interface These 40 bidirectional signals control most of the NI TIO operations The direction and output signals are programmable Ej Pin Usage Note When the NI TIO powers up all I O pins are in the common input usage state Table 3 3 lists output sources and common inputs for each I O connection pin Table 3 3 1 0 Connection Pin Usage Pin Number Common Input Usage Counter Output PFI O STC DIN 0 STC DOUT 0 PFI 1 STC DIN 1 STC DOUT 1 PFI2 STC DIN 2 STC DOUT 2 PFI3 STC DIN 3 STC DOUT 3 PFI 4 STC DIN 4 STC DOUT 4 PFI 5 STC DIN 5 STC DOUT 5 PFI 6 STC DIN 6 STC DOUT 6 PFI 7 STC DIN 7 STC DOUT 7 PFI 8 Cntr 7 Output PFI 9 Up Down 7 PFI 10 Gate 7 Cntr 7 Selected Gate PFI 11 Source 7 Cntr 7 Selected Src PFI 12 Cntr 6 Output PFI 13
3. 23 22 21 20 19 18 17 16 Load A 23 Load A 22 Load A 21 Load A 20 Load A 19 Load A 18 Load A 17 Load A 16 15 14 13 12 11 10 9 8 Load A 15 Load A 14 Load A 13 Load A 12 Load A 11 Load A 10 Load A 9 Load A 8 7 6 5 4 3 2 1 0 Load A 7 Load A 6 Load A 5 Load A 4 Load A 3 Load A 2 Load A 1 Load A 0 Bits Name Description 31 0 Load A 31 0 The Load A field is for loading the counter with Gi Load or for reloading on gate or TC conditions This field can alternate with Load B by using Reload Source Switching The A and B registers are actually two banks of load registers X and Y which are controlled by the bank switching attributes in the Gi Command register 660x Register Level Programmer Manual 3 20 ni com Chapter 3 Register Maps Gi Load B Register Address Offsets 0x03C GO 0x044 G1 0x13C G2 0x144 G3 Type Write Size 32 bit Bit Map 31 30 29 28 27 26 25 24 Load B 31 Load B 30 Load B 29 Load B 28 Load B 27 Load B 26 Load B 25 Load B 24 23 22 21 20 19 18 17 16 Load B 23 Load B 22 Load B 21 Load B 20 Load B 19 Load B 18 Load B 17 Load B 16 15 14 13 12 11 10 9 8 Load B 15 Load B 14 Load B 13 Load B 12 Load B 11 Load B 10 Load B 9 Load B 8 7 6 5 4 3 2 1 0 Load B 7 Load B 6 Load B 5 Load B 4 Load B 3 Load B 2 Load B 1 Load B 0 Bits Name Descri
4. e Read from determined by Gi DMA Status register Interrupt on DMA interrupt Count once false 660x Register Level Programmer Manual 2 10 ni com Chapter 2 General Purpose Counter Timers Selected Gate o Selected Source Counter Value 0 HW Save Register 3 2 Figure 2 9 Buffered Pulse Width Measurement Pulse Generation In pulse generation functions the counter generates a single pulse of specified duration following the software arm The software arm occurs when software sets the counter arm bit in the command register The following actions are available in pulse generation e The counter uses the Selected Source as a timebase to generate the pulse e The user specifies the pulse parameters in terms of periods of the Selected Source input e The Selected Gate can serve as a trigger signal to generate a pulse after the first active gate edge or after each active gate edge Single Pulse Generation The single pulse generation function generates a single pulse with programmable delay and programmable pulse width following the software arm Because the counter uses the Selected Source as a timebase to generate the pulse specify the pulse parameters in terms of periods of the Selected Source input Software implements pulse generation by loading the delay value into the counter loading the pulse width value into the load register and programming the c
5. Chapter 3 Register Maps Address Offsets OxOBO GO 0x0B2 G1 Ox1BO G2 Ox1B2 G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 Gi Gi Prescale 0 0 0 0 Alternate Sync 7 6 5 4 3 2 1 0 0 Gi Index Gi Index Gi Index 0 Gi Gi Gi Phase 1 Phase 0 Mode Counting Counting Counting Mode 2 Mode 1 Mode 0 Bits Name Description 13 Gi Alternate Sync 12 Gi Prescale National Instruments Corporation Alternate Synchronization When synchronizing a signal the NI TIO uses the falling edge of the clock when an internal timebase is chosen For other signals the clock may free run in which case the selected source synchronizes the signal and a delayed version clocks the counter Setting the Gi Alternate Sync bit adds an additional synchronization bit to the NI TIO When set the rising source edge synchronizes the signal and clocks the counter which gives a full state of setup and delays the reaction one clock This mode must be enabled if the counter is clocked above 40 MHz including cases in which TIMEBASE 3 is implicitly selected such as in synchronous counting and quadrature modes When this bit is enabled the high speed counter divides the selected source by eight before clocking the counter This mode allows signal frequency to be measured even when the frequency is above the 80 MHz limit for the counters 3 9 660x Register Level Programmer Manu
6. RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYIN
7. Description 31 0 SW Save lt 31 0 gt 660x Register Level Programmer Manual Software Save This value is latched on the next source edge following the assertion of the Save Trace bit When the bit is clear the counter value is transparent through the SW Save register This register is also part of the buffer for DMA operations When Gi DMA Enable in the Gi DMA Config register is set the SW Save register is used as a HW Save register In DMA mode the save value alternates between the HW Save register and the SW Save register 3 34 ni com Chapter 3 Register Maps Simple Digital Input Output An 8 bit DIO port is available for simple unstrobed read and write operations STC Digital Input Output The 8 bit digital port provides individual control over the direction and state of each bit This port is located on pins 0 through 7 STC Digital Input Output Registers Table 3 2 shows the STC digital input output register map The table provides the register name the register address offset from the device base address Base Address Register 1 the type of register read only and write only and the size of the register in bits Registers are grouped in the table by offset Table 3 2 STC Digital Input Output Register Address Map Register Name Offset Hex Type Size STC DIO Parallel Input Ox00E Read only 16 bit STC DIO Output 0x014 Write only 16 bit STC DIO Control 0x016 Write only 16 bit
8. Instruments Corporation Chapter 3 Register Maps G01 Joint Status 2 Register G23 Joint Status 2 Register Address Offsets 0x03A G01 0x13A G23 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gl GO GI HW GO HW X X X X Permanent Permanent Save Save Stale Data Stale Data 7 6 5 4 3 2 1 0 X X X X X X G1 Output GO Output Bits Name Description 15 14 Gi Permanent Stale Data This bit is set if the Gi Stale Data bit is set at any time during counter operation A counter reset clears this bit Hardware Save This bit indicates that it latched valid data and is ready to read This bit allows the counter output state to be read back The read occurs after the polarity selection 660x Register Level Programmer Manual Chapter 3 Register Maps Gi SW Save Register Address Offsets 0x018 GO 0x01C G1 0x118 G2 Ox11C G3 Type Read Size 32 bit Bit Map 31 30 29 28 27 26 25 24 SW SW SW SW SW SW SW SW Save 31 Save 30 Save 29 Save 28 Save 27 Save 26 Save 25 Save 24 23 22 21 20 19 18 17 16 SW SW SW SW SW SW SW SW Save 23 Save 22 Save 21 Save 20 Save 19 Save 18 Save 17 Save 16 15 14 13 12 11 10 9 8 SW SW SW SW SW SW SW SW Save 15 Save 14 Save 13 Save 12 Save 11 Save 10 Save 9 Save 8 7 6 5 4 3 2 1 0 SW SW SW SW SW SW SW SW Save 7 Save 6 Save 5 Save 4 Save 3 Save 2 Save 1 Save 0 Bits Name
9. This bit uses DMA mode to implement PIO operations When set the counter interrupt asserts with the counter DRQ signal indicating that service is needed If reading data the software reads either the HW Save or SW Save register as determined by the Gi Read Bank bit Write data to the appropriate A or B register 1 Gi DMA Write Direct Memory Access Write This bit indicates the direction of the DMA operation 0 DMA controller reads data from the NI TIO save registers 1 DMA controller writes data to the NI TIO load registers 0 Gi DMA Enable Direct Memory Access Enable When this bit is set the NI TIO adds a new DMA mode for streaming counts into or out of the counters The read mode uses both the hardware and the SW Save registers as a two element FIFO in order to increase the rate at which pulse or period measurements are made When using a DMA controller asserted DACK the DACK reads are automatically routed to the proper register and data is alternately stored 660x Register Level Programmer Manual 3 12 ni com National Instruments Corporation Chapter 3 Register Maps on gate edges When using PIO the Gi Read Bank bit indicates the register at the head of the FIFO For pulse generation DMA can reload the load register when a bank switch occurs DRQ asserts on the bank switch and clears when the last load register is written Gi Write Switch and Gi Little Big Endian determine the last load register If Gi Write Switch
10. Write only 16 bit G1 Input Select Register 0x04A Write only 16 bit G01 Joint Reset Register 0x090 Write only 16 bit GO Interrupt Enable 0x092 Write only 16 bit GI Interrupt Enable 0x096 Write only 16 bit GO Counting Mode Register OxOBO Write only 16 bit G1 Counting Mode Register 0x0B2 Write only 16 bit GO Second Gate Register 0x0B4 Write only 16 bit Gl Second Gate Register Ox0B6 Write only 16 bit G0 DMA Config Register OxOB8 Write only 16 bit G0 DMA Status Register OxOB8 Read only 16 bit G1 DMA Config Register OxOBA Write only 16 bit G1 DMA Status Register OxOBA Read only 16 bit G2 Interrupt Acknowledge 0x104 Write only 16 bit G2 Status Register 0x104 Read only 16 bit G3 Interrupt Acknowledge 0x106 Write only 16 bit 660x Register Level Programmer Manual 3 2 ni com Chapter 3 Register Maps Table 3 1 TIO Register Address Map Continued Register Name Offset Hex Type Size G3 Status Register 0x106 Read only 16 bit G23 Status Register 0x 108 Read only 16 bit G2 Command Register Ox10C Write only 16 bit G3 Command Register Ox10E Write only 16 bit G2 HW Save Register 0x110 Read only 32 bit G3 HW Save Register 0x114 Read only 32 bit G2 SW Save Register 0x118 Read only 32 bit G3 SW Save Register Ox11C Read only 32 bit G2 Mode Register 0x134 Write only 16 bit G23 Joint Status 1 Register 0x136 Read only 16 bit G3 Mode Register 0x136 Write only 16 bit G2 Load A Register 0x138
11. Write only 32 bit G23 Joint Status 2 Register Ox13A Read only 16 bit G2 Load B Register 0x13C Write only 32 bit G3 Load A Register 0x140 Write only 32 bit G3 Load B Register 0x144 Write only 32 bit G2 Input Select Register 0x148 Write only 16 bit G3 Input Select Register 0x14A Write only 16 bit G23 Joint Reset Register 0x190 Write only 16 bit G2 Interrupt Enable 0x192 Write only 16 bit G3 Interrupt Enable 0x196 Write only 16 bit G2 Counting Mode Register Ox1BO Write only 16 bit G3 Counting Mode Register 0x1B2 Write only 16 bit G3 Second Gate Register Ox1B6 Write only 16 bit G2 Second Gate Register 0x1B4 Write only 16 bit O National Instruments Corporation 3 3 660x Register Level Programmer Manual Chapter 3 Register Maps Table 3 1 TIO Register Address Map Continued Register Name Offset Hex Type Size G2 DMA Config Register Ox1B8 Write only 16 bit G2 DMA Status Register Ox1B8 Read only 16 bit G3 DMA Config Register OxIBA Write only 16 bit G3 DMA Status Register Ox1BA Read only 16 bit Clock Config Register 0x73C Write only 32 bit 660x Register Level Programmer Manual 3 4 ni com Chapter 3 Register Maps Clock Config Register Address Offset 0x73C Type Write Size 32 bit Bit Map 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0
12. an inadequately terminated endpoint This phenomenon is referred to as reflection reserved ground Pins that are marked RG on the I O connector are no connects if you use the SH6868 D1 shielded cable while they are ground pins if you use the R6868 unshielded ribbon cable a flat cable in which the conductors are side by side the oscillation of a signal about a high voltage or low voltage state immediately following a transition to that state real time system integration bus the National Instruments timing bus that connects DAQ boards directly by means of connectors on top of the boards for precise synchronization of functions seconds a register inside the NI TIO ASIC that stores the result of a measurement in the counter context source refers to the signal that causes the counter to increment or decrement In the context of signals source refers to the device that drives a signal 660x Register Level Programmer Manual Glossary SOURCE start trigger synchronous T TC termination timebase trigger tri state TTL two pulse encoder U unstrobed digital I O UP_DOWN 660x Register Level Programmer Manual G 8 the signal that causes the counter to increment or decrement a TTL level signal having two discrete levels a high and a low level that starts an operation a property of an event that is synchronized to a reference clock terminal count a strobe that occurs when a counter reaches zer
13. counter When set the SW Save register goes into the latched mode after the next clock edge to assure valid data was latched The latching process is complete when Gi Save is set The copy bits allow a single write to perform a command on both counters in the pair 13 Gi Arm Copy Setting this bit arms the other counter in the pair The counter remains armed until disabled in hardware or by Gi Disarm Copy 12 Gi Bank Switch Enable 660x Register Level Programmer Manual Setting this bit enables bank switching When the counter is armed this bit enables switching between the two banks of A and B Load registers referred to as X and Y If the counter is disarmed this bit selects the bank written when accessing the Load A and Load B registers 3 6 ni com Chapter 3 Register Maps 0 Writes Bank X 1 Writes Bank Y 11 Gi Bank Switch Mode If bank switching is enabled this bit selects the source that causes a bank switch to occur during operation 0 Gate 1 Software 10 Gi Bank Switch Start Setting this bit causes a bank switch on the condition determined by Bank Switch Mode The bit automatically clears after the bank switch 9 Gi Little Big Endian When using automatic interrupt acknowledgement the Gi Little Big Endian bit determines which segment of the load or save register triggers the acknowledgement 0 Low register bits 15 0 1 High register bits 31 16 8 Gi Synchronize Gate Setting this bit synchronizes
14. is clear writes are directed to Load B and DRQ clears on a write to the half of Load B as determined by Gi Little Big Endian If Gi Write Switch is true the first write goes to Load B DRQ remains asserted and the second write goes to Load A which clears DRQ 3 13 660x Register Level Programmer Manual Chapter 3 Register Maps Gi DMA Status Register Address Offsets 0x0B8 GO OxBA G1 Ox1B8 G2 Ox1BA G3 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gi DRQ Gi DRQ Gi DMA X X X X X Status Error Readbank 7 6 5 4 3 2 1 0 X X X X X X X X Bits Name Description 15 Gi DRQ Status DMA Request Status This bit is set when the counter needs DMA service and clears automatically when the request is serviced 14 Gi DRQ Error DMA Request Error This bit is set when a DMA overflow error occurs on a read operation and when an underflow error occurs on a write operation When reading this bit sets if a save request occurs when the FIFO is full and another DMA read follows The save request does not corrupt the data when the FIFO is received after completion When writing an error is set if the bank switches while DRQ is still set which indicates that the two switches occurred before the load registers were serviced 13 Gi DMA Readbank 660x Register Level Programmer Manual When implementing the PIO for read DMA the DMA Readbank indicates which sav
15. on DMA interrupt Count once false National Instruments Corporation 2 9 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers Selected Gate L EN Selected Source L Counter Value 0 HW Save Register 3 3 Figure 2 8 Buffered Period Measurement Buffered Pulse Width Measurement Buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses The counter uses the Selected Source to measure the pulse width of the signal present on the Selected Gate input counting the number of rising edges that occur on the Selected Source while the Selected Gate remains in an active state At the completion of each pulse width interval for the Selected Gate the HW Save or SW Save register latches the counter value for software read An interrupt notifies the CPU after each period so that the interrupt software can read the value in the HW Save register Figure 2 9 shows two pulse widths of a buffered pulse width measurement in which the first pulse width is three Selected Source rising edges and the second pulse width is two Selected Source rising edges The counter configuration is as follows e Source internal e Gate external signal e Gate mode level e Gate polarity inverted e Second gate selected gate e Second gate mode on e Second gate polarity inverted
16. the GATE signal to the counter clock This bit should be enabled unless the gate signal is definitely synchronized to the SRC and there is sufficient setup time 7 Gi Write Switch This setting automatically directs load register writes to the inactive bank When the bit is clear writes to Load A always change A When the bit is set writes to Load A are directed to the inactive bank 6 5 Gi Up Down This bit determines the counting direction 00 Always down 01 Always up 10 Hardware selected based on the UP DOWN I O pin 0 2 down 1 2 up 11 Hardware selected based on the internal GATE 0 down 1 up 4 Gi Disarm Setting this bit disarms the counter National Instruments Corporation 3 7 660x Register Level Programmer Manual Chapter 3 Register Maps 2 Gi Load 1 Gi Save Trace 0 Gi Arm 660x Register Level Programmer Manual This strobe bit uses software to load the initial counter value When the bit is asserted the selected load register A or B transfers to the counter This bit controls the SW Save register When Gi Save Trace is clear the SW Save register is open and tracing the counter When set the SW Save register goes into the latched mode after the next clock edge to assure valid data was latched The latching process is complete when Gi Save is set Setting this bit arms the counter The counter remains armed until disabled in hardware or by Gi Disarm 3 8 ni com Gi Counting Mode Register
17. 0 Counter 0 0 0 0 0 Swap 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Bit Name Description 21 Counter Swap Setting this bit swaps the dedicated counter pins SRC GATE UP DOWN OUT between counter locations 0 through 3 and 4 through 7 This setting allows two NI TIO ASICs to be configured to use all eight dedicated counter locations The addressing of the counters remains the same This setting also applies to dedicated pins such as the Quadrature and Output The mapping is as follows 0 lt gt 4 1 lt gt 5 2 lt gt 6 3 lt gt 7 National Instruments Corporation 3 5 660x Register Level Programmer Manual Chapter 3 Register Maps Gj Command Register Address Offsets 0x00C GO Ox00E G1 Ox10C G2 Ox10E G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gi Disarm Gi Save Gi Arm Gi Bank Gi Bank Gi Bank Gi Little Gi Copy Trace Copy Copy Switch Switch Switch Big Endian Synchronized Enable Mode Start Gate d 6 2 4 3 2 1 0 Gi Write Gi Up Gi Up Gi Disarm 0 Gi Load Gi Save Gi Arm Switch Down 1 Down 0 Trace Bits Name Description 15 Gi Disarm Copy Setting this bit disarms the other counter in the pair The copy bits allow a single write to perform a command on both counters in the pair 14 Gi Save Trace Copy This bit controls the SW Save register When Gi Save Trace Copy is clear the SW Save register is open and tracing the
18. 15 660x Register Level Programmer Manual Chapter 3 Register Maps 0 Source Pin i the source pin dedicated to this counter 1 Gate Pin i the gate pin dedicated to this counter 2 Gate Pin 0 I O Pin 38 3 Gate Pin 1 I O Pin 34 4 Gate Pin 2 I O Pin 30 5 Gate Pin 3 I O Pin 26 6 Gate Pin 4 I O Pin 22 7 Gate Pin 5 I O Pin 18 8 Gate Pin 6 I O Pin 14 9 Gate Pin 7 I O Pin 10 10 Next Src the selected source of the adjacent counter 11 RTSIO 12 RTSI 1 13 RTSI 2 14 RTSI3 15 RTSI 4 16 RTSI 5 17 RTSI 6 20 Next Out the counter of the adjacent counter 30 Logic low 31 Logic low 6 2 Gi Source Select lt 4 0 gt This bit selects the signal the counter uses as the source 0 Timebase 1 the internal timebase 20 MHz 1 Source Pin i the source pin dedicated to this counter 2 Source Pin 0 I O Pin 39 3 Source Pin 1 I O Pin 35 4 Source Pin 2 I O Pin 31 5 Source Pin 3 I O Pin 27 6 Source Pin 4 I O Pin 23 7 Source Pin 5 I O Pin 19 8 Source Pin 6 I O Pin 15 9 Source Pin 7 I O Pin 11 10 Next Gate the selected gate of the adjacent counter 11 RTSIO 12 RTSI 1 13 RTSI 2 14 RTSI 3 15 RTSI 4 16 RTSI 5 17 RTSI 6 660x Register Level Programmer Manual 3 16 ni com Chapter 3 Register Maps 18 Timebase 2 the internal timebase 100 KHz 19 Next TC the adjacent counter s terminal count 30 Timebase 3 the internal time
19. DAQ 660x Register Level Programmer Manual Q7 NATIONAL J April 2002 Edition y INSTRUMENTS Part Number 370505A 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 3262 3599 Canada Calgary 403 274 9391 Canada Montreal 514 288 5722 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 Canada Toronto 905 785 0085 China Shanghai 021 6555 7838 China ShenZhen 0755 3904939 Czech Republic 02 2423 5774 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91 80 535 5406 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 3390 150 Portugal 351 210 311 210 Russia 095 238 7139 Singapore 6 2265886 Slovenia 386 3 425 4200 South Africa 11 805 8197 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support and Professional Services appendix To comment on the documentation send email to techpubs ni com 2002 National Instruments Corpora
20. G AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Contents About This Manual Using the Manual Set dte ette me HE S e UR NRI eh ix CONVENIOS A aui da mu ede ed x Related Documentation ss 2 32 8 metet reete ar epe eU reri ee x Chapter 1 About the 660x Devices Structural Overview E EEE EEA E E EEA 1 1 MITEPCLIInterface ASIC i RR BIA E dd 1 2 NI TIO General Purpose Counter Timer ASIA 1 3 NETO GPCI S asada tias 1 3 EAU iii ii 1 3 simplified Model ii terea Hep caidas 1 4 Pulse Generation uev ne iE ede er 1 5 Measures 1 6 Ee ET 1 6 EEPROM 3 3 2 rte Ie Vie iui in NUI 1 7 RS ta in or re ege 1 7 Other Features 2 53 do ias 1 7 Using PXI with CompactPCl eet eet to re teret 1 7 Chapter 2 General Purpose Counter Timers Functional OVervie waa na tei pei teg deme erased diee 2 1 Reading Counter Values necne aee ete eat e aie e UR whee 2 2 Disarmed COUNCILS Jr eee aep OIN p E e anges 2 2 Armed Counters 2 ao Gades ee E 2 2 Buftered R ading uie tee ra echte rete e eT 2 2 Counter Timer Functions and Examples sese 2 2 ELSE E dius 2 3 Simple Event Counting eese 2 3 Simple Gated Event Counting esee 2 4 Buffered Cumulative Event Cou
21. Level Programmer Manual with other 660x device components 1 2 ni com Chapter 1 About the 660x Devices NI TIO General Purpose Counter Timer ASIC Each National Instruments NI TIO GPCT ASIC contains four general purpose counters that are independent of one another Each counter has a source two gates an output and multiple load registers The 6601 device has one NI TIO NI TIO 0 while the 6602 and 6608 devices have two NI TIOs NI TIO 0 and NI TIO 1 N Caution To avoid double driving the counter outputs on the 6602 and 6608 devices use Counter Swap in the Clock Config Register to configure the second NI TIO to use counters 4 through 7 If configured incorrectly both NI TIOs will use the I O connectors for counters 0 through 3 which could permanently damage the device NI TIO GPCTs Each NI TIO consists of four independent 32 bit up down counters These counters are identical except for the internal routing of the counter outputs and inputs Each counter has associated load and save registers and a control structure for implementing some common counting and timing I O functions The timing functions include period measurement pulse width measurement event counting single pulse generation and pulse train generation with programmable frequency and duty cycle hy Note Most functions can operate using only one general purpose counter Measurement functions have two operational modes single mode and buffered mode Sin
22. STC DIO Serial Input 0x038 Read only 16 bit O National Instruments Corporation 3 35 660x Register Level Programmer Manual Chapter 3 Register Maps STC DIO Parallel Input Address Offset Ox00E Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 DIN 7 DIN 6 DIN 5 DIN 4 DIN 3 DIN 2 DIN 1 DIN O Bits Name Description 7 0 DIN lt 7 0 gt Digital Input This field reads the state of the STC DIO pins 660x Register Level Programmer Manual 3 36 ni com Chapter 3 Register Maps STC DIO Output Address Offset 0x014 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Serial Serial Serial Serial Serial Serial Serial Serial DOUT 7 DOUT 6 DOUT 5 DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 7 6 3 4 3 2 1 0 Parallel Parallel Parallel Parallel Parallel Parallel Parallel Parallel DOUT 7 DOUT 6 DOUT 5 DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 Bits Name Description 15 8 Serial DOUT lt 7 0 gt Serial Digital Input This field loads the output register to be shifted on the next serial start 7 0 Parallel DOUT lt 7 0 gt Parallel Digital Output This field immediately updates the STC DOUT pins when they are enabled for output drive National Instruments Corporation 3 37 660x Register Level Programmer Manual Chapter 3 Register Maps STC DIO Control
23. Selected Gate the SW Save register contains the last counter value Figure 2 6 shows a single period measurement in which the period of the Selected Gate is five Selected Source rising edges The counter configuration is as follows Source internal clock e Gate external signal National Instruments Corporation 2 7 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers e Gate mode falling edge e Second gate selected gate e Second gate mode on e Second gate polarity non inverted Count once true Selected Gate M Selected Source o Counter Value 0 1 2 3 4 Figure 2 6 Single Period Measurement Single Pulse Width Measurement In single pulse width measurement the counter uses the Selected Source to measure the pulse width of the signal present on the Selected Gate input The counter counts the number of rising edges occurring on the Selected Source while the Selected Gate signal remains in an active state At the completion of the pulse width interval for the Selected Gate the SW Save register retains the counter value for software read Figure 2 7 shows a single pulse width measurement in which the pulse width of the Selected Gate is five Selected Source rising edges The counter configuration is as follows Source internal e Gate external signal Gate mode level Gate polarity inverted e Second gate selecte
24. Time Measurement Buffered period measurement continuous Buffered semiperiod measurement continuous Buffered pulse width measurement continuous Buffered two signal edge separation measurement continuous Position Measurement Quadrature encoders Miscellaneous Functions Digital I O National Instruments Corporation 2 1 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers Reading Counter Values This section explains how to read the values for disarmed and armed counters and how to take buffered readings from counters Disarmed Counters Read the SW Save register to determine the counter value on a disarmed counter Use this method for single period and single pulse measurements Armed Counters Values for armed counters can change during the register read If disarming the counter is impractical as with simple event counting or position measurement read the SW Save register twice If both reads are the same their value indicates the counter value If the two reads are different the counter value changed during one of the register reads In this case read the SW Save register a third time The third read is the correct counter value Buffered Readings During a buffered measurement the counter must save a value and continue counting Setting the Gi DMA Enable bit in the Gi DMA Config register tells the counter to save the counter contents in either the HW Save or SW Save
25. Up Down 6 Kees PFI 14 Gate 6 Cntr 6 Selected Gate PFI 15 Source 6 Cntr 6 Selected Src PFI 16 Cntr 5 Output 660x Register Level Programmer Manual 3 40 ni com National Instruments Corporation Chapter 3 Register Maps Table 3 3 1 0 Connection Pin Usage Pin Number Common Input Usage Counter Output PFI 17 Up Down 5 PFI 18 Gate 5 Cntr 5 Selected Gate PFI 19 Source 5 Cntr 5 Selected Src PFI 20 Cntr 4 Output PFI21 Up Down 4 PFI 22 Gate 4 Cntr 4 Selected Gate PFI 23 Source 4 Cntr 4 Selected Src PFI 24 Cntr 3 Output PFI 25 Up Down 3 EE PFI 26 Gate 3 Cntr 3 Selected Gate PFI 27 Source 3 Cntr 3 Selected Gate PFI 28 Cntr 2 Output PFI 29 Up Down 2 PFI 30 Gate 2 Cntr 2 Selected Gate PFI31 Source 2 Cntr 2 Selected Src PFI 32 Cntr 1 Output PFI 33 Up Down 1 PFI 34 Gate 1 Cntr 1 Selected Gate PFI 35 Source 1 Cntr 1 Selected Src PFI 36 Cntr 0 Output PFI 37 Up Down 0 PFI 38 Gate 0 Cntr 0 Selected Gate PFI 39 Source 0 Cntr 0 Selected Src 3 41 660x Register Level Programmer Manual Chapter 3 Register Maps Registers Register Name Offset Hex Type Size I O Config Reg 0 3 OxT7C Read and Write 32 bit T O Config Reg 4 7 0x780 Read and Write 32 bit I O Config Reg 8 11 0x784 Read and Write 32 bit I O Config Reg 12 15 0x788 Read and Write 32 bit I O Config Reg 16 19 0x78C Read and Write 32 bit I O C
26. Up Down Pin 0 I O Pin 37 3 Up Down Pin 1 I O Pin 33 4 Up Down Pin 2 I O Pin 29 5 Up Down Pin 3 I O Pin 25 6 Up Down Pin 4 I O Pin 21 7 Up Down Pin 5 I O Pin 17 8 Up Down Pin 6 I O Pin 13 9 Up Down Pin 7 I O Pin 9 10 Next Src the adjacent counter s selected source 11 RTSIO 12 RTSI 1 13 RTSI 2 3 26 ni com Chapter 3 Register Maps 14 RTSI 3 15 RTSI 4 16 RTSI 5 17 RTSI 6 20 Next Out the adjacent counter s output 30 Selected gate the output of the gate selection and not the selected gate I O pin For example if the gate is set to 1 Gate Pin i and if Gi Output Polarity is set the alternate gate is an inverted Gate Pin i signal This gate is useful for pulse measurement 31 Logic low 0 Gi Second Gate Mode National Instruments Corporation The second gate feature allows one signal to start the counter and another to stop it for two edge separation measurements When set Gi Second Gate Mode modifies the actual gate signal with a combination of the first and second gate An assertion of the second gate signals asserts the counter gate and an assertion of the gate signal deasserts the gate You can then use this new gate signal for start and stop operations Gi Second Gate Mode is also useful in pulse width measurements The level gating mode starts counting if the counter is armed while the gate is high so the first measurement may be too short Using the sele
27. a motion encoder indicate information about movement and direction of movement of an external device Decoding refers to extracting this information from the signals on these channels a plug in data acquisition board card or pad that can contain multiple channels and conversion devices Plug in boards PCMCIA cards and DAQ devices that connect to your computer parallel port are all examples of DAQ devices digital input output dynamic link library a software module in Microsoft Windows containing executable code and data that can be called or used by Windows applications or other DLLs Functions and data in a DLL are loaded and linked at run time when they are referenced by a Windows application or other DLLs direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory software that controls a specific hardware device such as a DAQ board the percentage of the cycle in which the pulse is high National Instruments Corporation G 3 660x Register Level Programmer Manual Glossary E EEPROM EISA encode ETS FSK GATE glitch GND H hardware HW HW Save Register Hz 660x Register Level Programmer Manual G 4 electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogr
28. al Chapter 3 Register Maps 6 5 Gi Index Phase 4 Gi Index Mode The index phase field determines the state of the A and B quadrature signals and is where the index or Z signal is acted upon The Z index can span multiple phases of the quadrature but it is recommended that you reload the counter in only one of the phases 00 A low B low 01 A low B high 10 A high B low 11 A high B high Index mode affects the new counting modes in the following ways Quadrature mode The Z input signal or index can reload the counter in a particular phase The counter reloads when this bit is set A and B match the index phase and the Z input is high Two pulse mode The counter reloads while Z is loaded Source synchronous mode Setting this bit disables the edge detector on the source signal that requires it to be synchronous 2 0 Gi Counting Mode 660x Register Level Programmer Manual This field adds counting modes to the NI TIO GPCT for interfacing to encoders and other new applications 000 One Normal counting mode 001 Quadrature Mode X1 This mode allows direct interfacing to quadrature encoders for position and velocity measurement The encoder has two and sometimes three signals signal A connects to the dedicated source pin of the counter signal B connects to the UP DOWN pin and signal Z connects to the GATE pin Signals A and B pulse with each movement and are 90 degrees out of phase to indica
29. ammed extended industry standard architecture used in the context of motion encoders Motion encoders provide information about movement and direction of movement of an external device The process of producing the pulses that contain this information is called encoding equivalent time sampling frequency shift keying the signal that controls the operation of a counter This signal may start or stop the operation of a counter reload the counter or save the results of a counter a brief unwanted change or disturbance in a signal level ground the physical components of a computer system such as the circuit boards plug in boards chassis enclosures peripherals cables and so on hardware a register inside the NI TIO ASIC that stores the result of a measurement hertz a unit of frequency One hertz corresponds to one cycle or event per second National Instruments Corporation in interrupt interrupt level I O LabVIEW m max maximum timebase min MITE National Instruments Corporation G 5 Glossary inches a computer signal indicating that the CPU should suspend its current task to service a designated activity the relative priority at which a device can interrupt input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low in
30. anual 2 6 ni com Chapter 2 General Purpose Counter Timers Ch A eee xi ChB 1 i ses LL Mode Counter Value 6 7 7 6 5 ChA x2 ChB i t i i Mid oy Mode Counter i MM NE NE Value 9 6 7 8 9 9 8 7 6 5 ChA a A A ee ee Mode Counter Pd WII Value 5 6 7 8 9 10 11 12713 13 12 11 10 9 8 7 6 5 Time Measurement Figure 2 5 Relative Position Sensing In time measurement functions the counter uses the Selected Source as a timebase to measure the time interval between events on the Selected Gate signal The following actions are available in time measurement Rising edges on the Selected Source can increment or decrement the counter during the measurement interval Counting can begin and end on any two of the Selected Gate edges rising falling or both The HW Save register or the SW Save register can save the counter value upon completion of the measurement Single Period Measurement In single period measurement the counter uses the Selected Source to measure the period of the signal present on the Selected Gate input The counter counts the number of rising edges occurring on the Selected Source between two active edges of the Selected Gate At the completion of the period interval for the
31. base the maximum frequency 31 Logic low National Instruments Corporation 3 17 660x Register Level Programmer Manual Chapter 3 Register Maps GO Interrupt Enable G2 Interrupt Enable Address Offsets 0x092 GO 0x192 G2 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 G0 TC 0 0 0 0 0 0 Interrupt Enable Bit Name Description 6 GO TC Interrupt Enable GO Terminal Count Interrupt Enable Setting this bit allows a terminal count interrupt to assert the counter interrupt 660x Register Level Programmer Manual 3 18 ni com Chapter 3 Register Maps G1 Interrupt Enable G3 Interrupt Enable Address Offsets 0x096 G1 0x196 G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 0 0 G1 TC 0 Interrupt Enable 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Bit Name Description 9 G1 TC Interrupt Enable G1 Terminal Count Interrupt Enable Setting this bit allows a terminal count interrupt to assert the counter interrupt National Instruments Corporation 3 19 660x Register Level Programmer Manual Chapter 3 Register Maps Gi Load A Register Address Offsets 0x038 G0 0x040 G1 0x138 G2 0x140 G3 Type Write Size 32 bit Bit Map 31 30 29 28 27 26 25 24 Load A 31 Load A 30 Load A 29 Load A 28 Load A 27 Load A 26 Load A 25 Load A 24
32. by step troubleshooting wizards hardware schematics and conformity documentation example code tutorials and application notes instrument drivers discussion forums a measurement glossary and so on Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email e Training Visitni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world e System Integration lf you have time constraints limited in house technical resources or other project challenges NI Alliance Program members can help To learn more call your local NI office or visit ni com alliance If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporation A 1 660x Register Level Programmer Manual Glossary Prefix Meaning Value u micro 1075 k kilo 10 M mega 106 Symbols deg
33. cted gate input to the second gate and inverting both gate and second gate polarity forces a rising edge to occur before the gate asserts As a result the first pulse is measured Gi Second Gate Mode is also used for two edge separation measurements 3 27 660x Register Level Programmer Manual Chapter 3 Register Maps Gi Status Register Address Offsets 0x004 GO 0x006 G1 0x104 G2 0x106 G3 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gi Interrupt X X X X X X X 7 6 5 4 3 2 1 0 x X X X Gi TC X X X Status Bits Name Description 15 Gi Interrupt This counter asserts an interrupt TC GATE or DMA Interrupt is true and enabled 3 Gi TC Status Terminal Count Status This bit indicates that the counter has reached terminal count Setting Gi TC Interrupt Ack clears this bit TC Status is useful for generating interrupts at a constant frequency 660x Register Level Programmer Manual 3 28 ni com G01 Status Register Chapter 3 Register Maps Address Offset 0x008 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gl Gate GO Gate Gl TC GO TC G1 No G0 No G1 Armed GO Armed Error Error Error Error Load Load Between Between Gates Gates GI Stale GO Stale G1 Next GO Next Gl GO Gl Save GO Save Data Data Load Load Counting Counting Source Source Bits Name Description 15 14 Gi Gate Error Gi Gate Error sets when a second gate in
34. d gate e Second gate mode on e Second gate polarity inverted Count once true 660x Register Level Programmer Manual 2 8 ni com Chapter 2 General Purpose Counter Timers Selected Gate PLS Selected Source Counter Value 0 1 l Cl Figure 2 7 Single Pulse Width Measurement Buffered Period Measurement Buffered period measurement is similar to single period measurement except that buffered period measurement takes measurements for multiple periods The counter uses the Selected Source to measure the time interval between two active edges of the signal present on the Selected Gate input counting the number of rising edges that occur on the Selected Source between each pair of active edges of the Selected Gate At the completion of each period interval for the Selected Gate the HW Save or SW Save register latches the counter value for software read An interrupt notifies the CPU after each period so that the interrupt software can read the value in the HW Save register Figure 2 8 shows two periods of a buffered period measurement in which the period is three Selected Source rising edges The counter configuration is as follows e Source internal clock e Gate external signal e Gate mode falling edge e Second gate selected gate e Second gate mode on e Second gate polarity non inverted e Read from determined by Gi DMA Status register e Interrupt
35. device is still compatible with the CompactPCI chassis if the pins on the sub bus are disabled by default Refer to Table 1 1 for a list of the J2 pins the PXI 6602 device uses Table 1 1 Pins Used by PXI 660x Devices PXI 6602 6608 Signal PXI Pin Name PXI J2 Pin Number RTSI Trigger PXI Trigger 0 5 B16 A16 A17 A18 0 5 B18 C18 RTSI Trigger 6 PXI Star D17 RTSI Clock PXI Trigger 7 E16 Reserved LBR 7 8 10 A3 C3 E3 A2 B2 11 12 660x Register Level Programmer Manual 1 8 ni com General Purpose Counter Timers This chapter contains a functional overview of the GPCT as well as register level programming examples that illustrate the functions described in this chapter Functional Overview You can use the 660x device in the counter based applications outlined in Table 2 1 For more detailed descriptions of each application refer to Chapter 3 Device Overview of the 6601 6602 User Manual Table 2 1 Counter Based Applications Application Class Application Simple Counting Simple event counting Gated event counting Time Measurement Single period measurement Single pulse width measurement Two signal edge separation measurement Simple Pulse and Single pulse generation Pulse Train Generation Single triggered pulse generation Retriggerable single pulse generation Continuous pulse train generation Buffered Counting and Buffered event counting continuous
36. devices have two NI TIO ASICs they are particularly subject to this kind of damage If using both ASICs configure the second NI TIO to use the I O pins for the second NI TIO Doing so prevents both NI TIOs from connecting to the same I O pins Structural Overview The following functional groups make up the 660x circuitry e MITE PCI interface ASIC e NI TIO 0 general purpose counter timer GPCT ASIC e NI TIO 1 general purpose counter timer ASIC available on the 6602 and 6608 devices only National Instruments Corporation 1 1 660x Register Level Programmer Manual Chapter 1 About the 660x Devices Figure 1 1 illustrates the data flow of the 660x devices Address DN Decoder 6602 80 MHz Osc EEPROM f 6601 20 MHz Address 2 3 __ Gi MITE KD x lt Qa hu Control nteriace 5 e a L NETIO 0 K 6602 devices only gt NI TIO 1 Interrupt PFI Lines A 1 0 Connector A Lines f RTSI PXI interrupt Vv M RTSI PXI Trigger Bus Figure 1 1 660x Device Data Flow MITE PCI Interface ASIC The MITE PCI Interface ASIC is the interface for register accesses interrupts and DMA The MITE enables communication between the 660x device and the PCI or PXI bus Once initialized the MITE enables communication 660x Register
37. e register contains the next data to be transferred This bit alternates with each read 0 HW save 1 SW save 3 14 ni com Chapter 3 Register Maps Gi Input Select Register Address Offsets 0x048 GO 0x04A G1 0x148 G2 Ox14A G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gi Source Gi Output Gi OR Gate Gi Gate Gi Gate Gi Gate Gi Gate Gi Gate Polarity Polarity Select Load Select 4 Select 3 Select 2 Select 1 Source 7 6 5 4 3 2 1 0 Gi Gate Gi Source Gi Source Gi Source Gi Source Gi Source 0 0 Select 0 Select 4 Select 3 Select 2 Select 1 Select 0 Bits Name Description 15 Gi Source Polarity Set this bit to invert the selected source signal changing the polarity of the active edge 14 Gi Output Polarity Set this bit to invert the counter output signal 13 Gi OR Gate Set this bit to OR the output of the adjacent counter with the selected gate When the counter is not counting only the adjacent counter output is the gate Clearing this bit removes the effect on the gate 12 Gi Gate Select Load Source When this bit is set the selected gate signal chooses the load source for the counter An active gate level chooses Load A while an inactive level chooses Load B The Gi Gating mode must be set to Level mode 11 7 Gi Gate Select lt 4 0 gt This bit selects the signal to serve as the gate for the counter National Instruments Corporation 3
38. ead only and write only and the size of the register in bits Registers are grouped in the table by offset and the register descriptions following the table are organized alphabetically Table 3 1 TIO Register Address Map Register Name Offset Hex Type Size GO Interrupt Acknowledge 0x004 Write only 16 bit GO Status Register 0x004 Read only 16 bit GI Interrupt Acknowledge 0x006 Write only 16 bit G1 Status Register 0x006 Read only 16 bit G01 Status Register 0x008 Read only 16 bit GO Command Register 0x00C Write only 16 bit G1 Command Register Ox00E Write only 16 bit G0 HW Save Register 0x010 Read only 32 bit G1 HW Save Register 0x014 Read only 32 bit GO SW Save Register 0x018 Read only 32 bit National Instruments Corporation 3 1 660x Register Level Programmer Manual Chapter 3 Register Maps Table 3 1 TIO Register Address Map Continued Register Name Offset Hex Type Size G1 SW Save Register 0x01C Read only 32 bit GO Mode Register 0x034 Write only 16 bit G01 Joint Status 1 Register 0x036 Read only 16 bit G1 Mode Register 0x036 Write only 16 bit GO Load A Register 0x038 Write only 32 bit G01 Joint Status 2 Register 0x03A Read only 16 bit GO Load B Register 0x03C Write only 32 bit Gl Load A Register 0x040 Write only 32 bit G1 Load B Register 0x044 Write only 32 bit GO Input Select Register 0x048
39. es the mode in which the hardware stops the counter 00 Stop on gate condition 01 Stop on gate or first TC 10 Stop on gate or second TC 11 Reserved ei Note To make these conditions TC only use Gi Trigger Mode for Edge Gate to turn off the edge gate stopping 4 3 Gi Trigger Mode for EdgeGate This field determines how a gate edge affects the counting when gating is enabled 00 The first gate edge starts and the next gate edge stops the counting 01 The first gate edge stops and the second gate edge starts the counting National Instruments Corporation 3 23 660x Register Level Programmer Manual Chapter 3 Register Maps 10 The gate edge that always starts the counting TC normally stops this mode 11 The gate not used for starting or stopping This gate may still save reload or load select Selections 0 and 1 are valid when Gi Stop Mode is 0 and selection O through 2 are only valid for edge gating and level gating 2 Gi Gate on Both Edges When Gi Gate on Both Edges is set and Gi Gating Mode is set to rising mode the edge gating modes operate on both the rising and falling edges 1 0 Gi Gating Mode This field determines how the gate signal is interpreted for gating operations 00 Gating disabled 01 Level gating 10 Rising edge gating 11 Falling edge gating Ei Note Gi Gate Polarity can change the edge for modes 2 and 3 When gating is disabled you can use the gate for counting directi
40. evice Window Base Size Register IODWBSR Address Offset OxCO Type Read and Write Size 32 bit Bit Map 31 30 29 28 27 26 25 24 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 23 22 21 20 19 18 17 16 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 15 14 13 12 11 10 9 8 BA15 BA14 BA13 BA12 X X X X 7 6 5 4 3 2 1 0 WENAB X X X X X X WSIZE Bits Name Description 31 12 BA lt 31 12 gt Base Address These bits indicate base address of the 8 KB device window in CPU address space and are only valid when WENAB 1 and WSIZE 0 7 WENAB Window Enable Setting this bit enables the window Clearing this bit disables the window 11 8 6 1 X X should always be written with a 0 and ignored when read 0 WSIZE Window Size If WSIZE is set the window size is 4 GB National Instruments Corporation If WSIZE is clear the device region is 8 KB 660x Register Level Programmer Manual Technical Support and Professional Services Visit the following sections of the National Instruments Web site at ni com for technical support and professional services e Support Online technical support resources include the following Self Help Resources For immediate answers and solutions visit our extensive library of technical support resources available in English Japanese and Spanish at ni com support These resources are available for most products at no cost to registered users and include software drivers and updates a KnowledgeBase product manuals step
41. gle mode functions obtain only one measurement while buffered mode functions obtain a series of consecutive gap free measurements You can select the GPCT input signals from the external timing I O pins on the 660x devices Available input options depend on the type of GPCT input Output generation and timing measurement are the two primary GPCT modes Features The NI TIO has the following features e Four independent 32 bit binary up down counters e Count up count down control through hardware or software e Programmable counter source and gate selection from 19 signal sources e Programmable input and output signal polarities National Instruments Corporation 1 3 660x Register Level Programmer Manual Chapter 1 About the 660x Devices e Single pulse or continuous pulse generation output e nter event relative timestamping e Two sets of save registers to save the counter value through an external control signal or through software command e Current count value readings that do not affect circuit operation e Interrupts based on terminal count TC rising edge falling edge or any edge e Quadrature encoder position measurements EI Note The 660x devices do not support BCD counting and time of day counting Selected Gate Selected Source Simplified Model The GPCT contains four identical 32 bit binary up down counters Figure 1 2 shows a simplified model of the GPCT G OUT Load Registers Star
42. he counter value In the latter case interrupts notify the software that a save has occurred e AUS LINE UP DOWN controls the direction of the counting Simple Event Counting In simple event counting the counter counts the number of pulses occurring on the Selected Source signal after the software arm Software can read the counter contents at any time without disturbing the counting process Figure 2 1 shows an example of simple event counting in which the counter counts five events on the Selected Source The counter configuration is as follows e Source external signal e Gate disabled e Read from SW Save register e Direction up Software Arm Selected Source U Counter Value 0 Figure 2 1 Simple Event Counting National Instruments Corporation 2 3 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers Simple Gated Event Counting Simple gated event counting is similar to simple event counting but the counting process in simple gated event counting is gated halted and resumed through the Selected Gate When the Selected Gate is active the counter counts pulses occurring on the Selected Source signal after the software arm When the Selected Gate is inactive the counter retains the current count value Figure 2 2 shows an example of simple gated event counting in which the gate action allows the counter to count only five of the pulses on the Se
43. installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQ STC LabVIEW Measurement Studio MITE National Instruments ni com and NI DAQ are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE
44. iod or pulse width the counter uses a known timebase usually the fastest internal timebase for clocking and the Gate signal starts and stops the counter while latching the measurement With event counting and frequency measurements an unknown signal applied to the source and the gate is of a fixed time to create a window of measurement Figure 1 4 illustrates the measurement data flow Source _ gt P Counter Save Register Gate Gate Detection Figure 1 4 Measurement Data Flow The signal from the oscillator is the internal timebase for the 660x devices The 6601 device uses 20 MHz oscillators and the 6602 and 6608 devices use an 80 MHz oscillator 660x Register Level Programmer Manual 1 6 ni com EEPROM RTSI Chapter 1 About the 660x Devices The EEPROM stores PCI plug and play configuration information The MITE reads this memory during system boot The NI TIO ASICS can access the RTSI bus to share triggers or to clock signals between DAQ devices The RTSI on 6602 and 6608 devices can share triggers between the two NI TIOs ei Note Only one NL TIO or 660x device should drive a RTSI line at a time Double driving a RTSI line can damage the 660x device Other Features The NI TIO includes several other features for specific measurement or generation cases including an interface to quadrature encoders for position and velocity
45. lected Source The counter configuration is as follows e Source external signal e Gate external signal e Read from SW Save register e Direction up Software Arm Selected Gate Selected Source Counter Value 0 Figure 2 2 Simple Gated Event Counting Buffered Cumulative Event Counting Buffered cumulative event counting is similar to simple event counting but the Selected Gate signal in buffered cumulative event counting indicates when to save the counter value to the HW Save register The active Selected Gate edge latches the count value into the HW Save register Counting continues uninterrupted regardless of the Selected Gate activity An interrupt notifies the CPU after each active Selected Gate edge so that the interrupt service routine can read the result from the HW Save register Figure 2 3 shows cumulative event counting in which the gate action causes the HW Save register to save the counter contents twice The counter configuration is as follows e Source external signal e Gate external signal Trigger mode gate ignored 660x Register Level Programmer Manual 2 4 ni com Chapter 2 General Purpose Counter Timers Interrupt on DMA interrupt Read from determined by Gi DMA Status register Direction up Load on gate do not reload on gate UN Caution Reading the value of a counter outside the interrupt service routine ISR may result in da
46. load on gate Software Arm Selected Gate Selected Source P WEE o mi E Counter Value 0 1 2 3 1 2 3 1 HW Save Register X 3 3 Figure 2 4 Buffered Noncumulative Event Counting Position Measurement In position measurement functions the counter tracks the position of a quadrature encoder Relative Position Measurement In relative position sensing the counter tracks the relative position of the position encoder Two types of events are possible movement in the positive direction and movement in the negative direction When Channel A leads Channel B the counter increments When Channel B leads Channel A the counter decrements The number of increments and decrements per cycle depends on the type of encoding X1 X2 or X4 On NI TIO counters Channel A is hardwired to the default counter source pin Channel B is hardwired to the AUS LINE pin and Channel Z is hard wired to the gate pin The software initially loads the counter with a value corresponding to the initial position of the object Upon reaching terminal count TC the counter rolls over You can obtain the relative object position at any time by asynchronously reading the counter value Figure 2 5 shows an example of relative position sensing The counter configuration is as follows Encoder counting mode X4 e Source select internal timebase e Read from SW Save register 660x Register Level Programmer M
47. measurement of rotating devices Additionally the NI TIO second gate allows edge separation measurements Using PXI with CompactPCI Using PXI compatible products with standard CompactPCI products is an important feature of the PXI Specification revision 1 0 Using a PXI compatible plug in device in a standard CompactPCI chassis enables you to use basic plug in device functions but PXI specific functions are not available For example the RTSI bus on PXI 660x devices is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification enables vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses or between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses The PX1 6602 and PXI 6608 devices work in any standard CompactPCI chassis adhering to the PICMG CompactPCI 2 0 R2 1 specification The J2 connector of the CompactPCI bus implements the PXI specific features The PXI device is compatible with any CompactPCI chassis whose sub bus does not drive these lines UN Caution Driving these lines with the sub bus may cause damage to the 660x device National Instruments Corporation 1 7 660x Register Level Programmer Manual Chapter 1 About the 660x Devices Even if the sub bus is capable of driving these lines the PXI
48. mmable parameters in terms of periods of the Selected Source input Pulse train generation is implemented in software by loading the pulse parameters into the counter and load registers and by programming the counter to switch load registers on every counter TC Figure 2 11 shows the generation of three pulses with a delay from trigger of three a pulse interval of four and a pulse width of three The counter configuration is as follows Source internal Gate none e Output mode toggle on TC 660x Register Level Programmer Manual 2 12 ni com Chapter 2 General Purpose Counter Timers e Direction down e Count once false e Load on TC Trigger mode only gate edge starts e Reload source switching true Selected Source Counter Value Counter TC GD OUT Figure 2 11 Continuous Pulse Train Generation Single Triggered Pulse Generation Single triggered pulse generation is similar to single pulse generation the Selected Gate in single triggered pulse generation provides a trigger function An active Selected Gate edge following the software arm causes the counter to generate a single pulse with programmable delay and programmable pulse width Specify the programmable parameters in terms of periods of the Selected Source input Single triggered pulse generation is impleme
49. nted in software by loading the delay value into the counter loading the pulse width value into the load register programming the counter output G OUT to change states on counter TC and configuring the Selected Gate as the trigger signal Figure 2 12 shows the generation of a single pulse with a pulse delay of four and a pulse width of three The counter configuration is as follows e Source internal e Gate external signal e Output mode toggle on TC e Direction down e Count once true Load on TC e Trigger mode gate edge only starts National Instruments Corporation 2 13 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers Selected Gate Selected Source Counter Value 3 3 Counter TC GD OUT Figure 2 12 Single Triggered Pulse Generation 660x Register Level Programmer Manual 2 14 ni com Register Maps This chapter contains NI TIO and MITE register maps and register descriptions NI TIO The NI TIO 0 location is PCI Buffer Address Register BAR 1 offset 0x0 The NI TIO 1 location on the 6602 and 6608 devices is PCI BARI offset 0x800 Register Map and Descriptions This section includes a register map and a bit by bit description of each register in the NI TIO Table 3 1 provides the register name the register address offset from the device base address BARI the type of register r
50. nting eee 2 4 Buffered Noncumulative Event Counting eese 2 5 Position Measurement ene ete eere era feb eene eee p ERE 2 6 Relative Position Measurement esee 2 6 National Instruments Corporation V 660x Register Level Programmer Manual Contents Time Measurement aat ti RIO 2 7 Single Period Measurement sese 2 7 Single Pulse Width Measurement eee 2 8 Buffered Period Measurement essen 2 9 Buffered Pulse Width Measurement cccoooooccncconononnnnnononnnnnncnnnonnnnnnos 2 10 Pulse Genera tion e eee dida ZER een 2 11 Single Pulse Generation esee nennen 2 11 Pulse Train Generation te eee tort vo era ego eene ela teo gea deeds 2 12 Continuous Pulse Train Generation ooooonccnnnooonnncnonnnannncnonanannnnnonnnnns 2 12 Single Triggered Pulse Generation esee 2 13 Chapter 3 Register Maps NETO init rete A 3 1 Register Map and Descriptions nene 3 1 Clock Config Register bib 3 5 Gi Command Register 3 6 Gi Counting Mode Register essere 3 9 Gi DMA Config Register c ooooccnocnnoninncnoncnnnnnncnnannncnnonnnonnncncnnccncnnnono 3 12 Gi DMA Status Register 3 14 Gi Input Select Regtoter eee sess 3 15 GO Interrupt Enable G2 Interrupt Enable eee ete eerte 3 18 G1 Interrupt Enable G3 interrupt Enable 5 obe i dee hs 3 19 Gi Load A Register ege ea teste ie 3 20 G
51. o from either direction matching of impedances at the end of a signal path to minimize reflections another term used for the SOURCE of a counter Usually indicates an internal SOURCE provided by or derived from an onboard oscillator any event that causes starts or stops some form of data capture a third output state other than high or low in which the output is undriven transistor transistor logic a motion encoder that has two channels channels A and B Pulses on channel A indicate movement in one direction while pulses on channel B indicate movement in the opposite direction This type of encoder is also referred to as up down encoder a type of digital input or output in which software reads or writes the digital line or port states directly without using any handshaking or hardware controlled timing functions Also called immediate nonhandshaking or unlatched digital I O the signal that determines whether a counter increments or decrements National Instruments Corporation Glossary V volts VDC volts direct current Vin volts in VI Virtual Instrument A LabVIEW program so called because it models the appearance and function of a physical instrument wire data path between nodes National Instruments Corporation G 9 660x Register Level Programmer Manual
52. of the 660x devices and is necessary for programmers using platforms not supported by NI DAQ This manual contains the following information necessary to perform register level programming for the 660x devices e Address and function 660x device registers for reading and writing data and for configuring the input lines and the general purpose counter timers GPCTs e Overview of several common GPCT operations e Guidelines for configuring GPCTs hy Note Use the change notification feature only if you are familiar with writing installing and uninstalling interrupt service routines National Instruments recommends programming the 660x device using NI DAQ with application development environment software such as LabVIEW LabWindows CVI or Measurement Studio Application software provides easier programming with the same flexibility as register level programming and much faster development time Using the Manual Set The 660x Register Level Programmer Manual is one piece of the documentation set for your data acquisition system For information about a specific 660x device refer to the user manual for that device The user manual provides installation procedures connection requirements programming options specifications and guidelines for operating the 660x devices Consult the accessory installation guides or manuals for information about accessory products The terminal block and cable assembly installation guides or accesso
53. on only 660x Register Level Programmer Manual 3 24 ni com G01 Joint Reset Register G23 Joint Reset Register Chapter 3 Register Maps Address Offsets 0x090 G01 0x190 G23 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 GI Reset GO Reset 0 0 Bits Name Description 3 2 Gi Reset Writing this strobe bit to 1 resets the counter This bit National Instruments Corporation automatically clears and the counter is disarmed 3 25 660x Register Level Programmer Manual Chapter 3 Register Maps Gi Second Gate Register Address Offsets 0x0B4 GO 0x0B6 G1 Ox1B4 G2 Ox1B6 G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 Gi Second 0 Gi Second Gi Second Gi Second Gi Second Gate Gate Select Gate Select Gate Select Gate Select Polarity 4 3 2 1 7 6 5 4 2 1 0 Gi Second 0 0 0 0 0 Gi Second Gate Select Gate Mode 0 Bits Name Description 13 Gi Second Gate Polarity 11 7 Setting this bit inverts the selected second gate changing the polarity Gi Second Gate Select lt 4 0 gt This field selects the signal used as the second gate for the 660x Register Level Programmer Manual counter 0 Source Pin i the source pin dedicated to this counter 1 Up Down Pin i the Up Down pin dedicated to this counter 2
54. onfig Reg 20 23 0x790 Read and Write 32 bit T O Config Reg 24 27 0x794 Read and Write 32 bit I O Config Reg 28 31 0x798 Read and Write 32 bit I O Config Reg 32 35 0x79C Read and Write 32 bit I O Config Reg 36 39 Ox7A0 Read and Write 32 bit 660x Register Level Programmer Manual ni com Chapter 3 Register Maps 1 0 Config Register Pins A through D Address Offset Ox77C 0x780 0x784 0x788 0x78C 0x790 0x794 0x79C Ox7A0 Type Read and Write Size 32 bit Bit Map 31 30 29 28 27 26 25 24 X A Input A Input A Input X X A Output A Output Select 2 Select 1 Select 0 Select 1 Select 0 23 22 21 20 19 18 17 16 X B Input B Input B Input X X B Output B Output Select 2 Select 1 Select 0 Select 1 Select 0 15 14 13 12 11 10 9 8 X C Input C Input C Input X X C Output C Output Select 2 Select 1 Select 0 Select 1 Select 0 7 6 5 4 3 2 1 0 X D Input D Input D Input X X D Output D Output Select 2 Select 1 Select 0 Select 1 Select 0 Bits Name Description 25 24 Output Select lt 1 0 gt 17 16 9 8 1 0 This field determines if the I O pin is driven and what signal is driven into the pin 00 Pin is input only driver tristates 01 Normal counter output 30 28 Input Select lt 2 0 gt 22 20 14 12 6 4 This field allows each input pin to be passed through or digitally filtered to remove noise The digital filters sample the signal
55. ounter output G_OUT to change states on counter terminal count TC Figure 2 10 shows the generation of a single pulse with a pulse delay of four and a pulse width of three The counter configuration is as follows e Source internal Gate none e Output mode toggle on TC e Direction down O National Instruments Corporation 2 11 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers Count once true Load on TC Software Arm Selected Source Counter Value 3 3 Counter TC G_OUT Figure 2 10 Single Pulse Generation Pulse Train Generation In the pulse train generation functions the counter generates a continuous stream of pulses of specified interval and duration following the software arm and an optional hardware trigger The software arm occurs when software sets the counter arm bit in the NI TIO register The following actions are available in pulse train generation The pulse parameters can be specified in terms of periods of the Selected Source input e The Selected Gate input can serve as a trigger signal to generate a stream of pulses only after the active gate edge occurs Continuous Pulse Train Generation This function generates a sequence of pulses with programmable pulse interval and pulse width Because the counter uses the Selected Source as a timebase to generate the pulses specify the progra
56. ource may be a known frequency in which case both the duty cycle and the output frequency are known The source may also be an input that needs to be divided by an integer The operation may be single shot repetitive or triggered from the gate signal The NI TIO has four available load registers Load A and Load B in two X and Y bank cells With this flexibility you can generate any duty cycle and reprogram the load registers to change the properties on the fly The output is typically programmed to alternate on each terminal count but it can be programmed to toggle on the terminal count signal to create the smallest pulse or highest frequency output Figure 1 3 illustrates the pulse generation data flow Output gt Generation Output lt 2 xe o be a 5 ESCH 3 M o 2 G E 3 3 e O Load B Source J 9 Figure 1 3 Pulse Generation Data Flow National Instruments Corporation 1 5 660x Register Level Programmer Manual Chapter 1 About the 660x Devices Oscillator Measurement In measurement modes the counter measures the source or the gate properties Source edges increment or decrement the counter and the gate signal stops and starts the counter During buffered acquisitions the gate signal also latches the counter state for either a software or DMA reading of the measurement For measurements such as period semi per
57. pactPCI 2 0 R2 1 660x Register Level Programmer Manual X ni com About the 660x Devices This chapter provides a summary of the National Instruments 660x devices and includes a brief overview of the MITE and NI TIO components The National Instruments 660x devices are timing and digital I O boards for use with the PCI bus in PC compatible computers and PXI or CompactPCI chassis The 6601 device features four 32 bit counter channels and eight lines of individually configurable TTL CMOS compatible digital I O The 6602 and 6608 devices have the same capabilities as the 6601 device but feature eight 32 bit counter channels and an 80 MHz clock The 6608 device features an oven controlled crystal oscillator OCXO for greater timing accuracy Refer to the 6601 6602 User Manual or the Note to Users About Your 6608 Device for more information about device functionality installation connections and safety guidelines N Caution Using the 660x devices in a way inconsistent with the 6601 6602 User Manual and the Note to Users About Your 6608 Device can cause injury or equipment damage National Instruments is not liable for damage or injury resulting from incorrect use UN Caution Incorrectly programming the 660x devices can cause permanent damage to the devices For example some I O pins can be driven from several outputs Two sources driving the same I O pin could burn out the I O pin and destroy one of the ASICs Because 6602 and 6608
58. ption 31 0 Load B lt 31 0 gt The Load B field is for loading the counter with Gi Load National Instruments Corporation or for reloading on gate or TC conditions It can alternate with Load B by using Reload Source Switching in the Gi Mode register The A and B registers are actually two banks of load registers X and Y which are controlled by the bank switching attributes in the Gi Command register 3 21 660x Register Level Programmer Manual Chapter 3 Register Maps Gi Mode Register Address Offsets 0x034 GO 0x036 G1 0x134 G2 0x136 G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 Gi Reload Gi Loading Gi Gate Gi Loading Gi Gi Gi Output Gi Output Source on Gate Polarity on TC Counting Counting Mode 1 Mode 0 Switching Once 1 Once 0 7 6 5 4 3 2 1 0 Gi Load Gi Stop Gi Stop Gi Trigger Gi Trigger Gi Gate on Gi Gating Gi Gating Source Mode 1 Mode 0 Mode for Mode for Both Edges Mode Mode Select Edge Gate 1 Edge Gate 0 Bits Name Description 15 Gi Reload Source Switching 14 13 12 When Gi Gate Select Load Source is 0 the Gi Reload Source Switching bit determines if the reloading always comes from the same load register 0 or if it alternates between the two 1 Gi Loading on Gate When this bit is set the gate edge reloads the counter on the next source edge Set the Gi Trigger Mode for Edge Gate to 3 to reload the counte
59. r Load B Register eee e ERR ESN 3 21 Gr Mode Register 3 22 G01 Joint Reset Register G23 Joint Reset Register eo erret ees 3 25 Gi Second Gate Reatster sess 3 26 Gr Status Register outs io ate mim tei ten 3 28 GOL Status Register out he ceo aii 3 29 G01 Joint Status 1 Register seen 3 31 G23 Joint Status 1 Register ooonncninninnnonnnononononnnoncnancnnnonncrnncanarnncnnnns 3 32 G01 Joint Status 2 Register G23 Joint Status 2 Register 3 33 Gr SW Save Register ninia rettet eis 3 34 Simple Digital Input Output esent rennen ementi 3 35 STE Digital Input Output rere etre Rer Rer exei 3 35 STC Digital Input Output Registers esee 3 35 STCJOIO Parallel Input ima 3 36 SIC DIO Output 2 anm ene ed ed eae 3 37 660x Register Level Programmer Manual vi ni com Contents STC DIO Control 1 tede eie reti ei eerte 3 38 STC DIO Serial Input ue o eer ee eben 3 39 I O Connection Registers ere eterni entr eee reete eur 3 40 Pin Usage tas n GS 3 40 Repita ta a ech eege eegene 3 42 T O Config Register Pins A through D 3 43 MITE D titi Eeer 3 44 T O Device Window Base Size Register IODWBSR eene 3 45 Appendix A Technical Support and Professional Services Glossary National Instruments Corporation Vii 660x Register Level Programmer Manual About This Manual The 660x Register Level Programmer Manual describes the programmable features
60. r on each selected edge Otherwise the counter reloads on the gate that stops the counter You can also use Gi Loading on Gate with Gi Loading on TC Gi Gate Polarity Setting the bit inverts the gate signal making it active low rather than the normal active high Gi Loading on TC Loading on Terminal Count If this bit is clear the counter rolls over when it reaches TC When set the counter reloads from a Load register on TC You can also use 660x Register Level Programmer Manual Gi Loading on TC with Gi Loading on Gate 3 22 ni com Chapter 3 Register Maps 11 10 Gi Counting Once This field determines whether the counter disarms when the counter stops for a hardware condition 00 No hardware disarm 01 Disarm at the TC that stops counting 10 Disarm at the gate that stops counting 11 Disarm at the first TC or gate that stops counting 9 8 Gi Output Mode Gi Output Mode determines the counter output type 00 Reserved 01 The counter TC is the output it asserts for one clock at TC 10 Output toggles value on each TC 11 Output toggles on TC or gate 7 Gi Load Source Select When the counter is disarmed this bit determines which load register Load A 0 or Load B 1 loads the counter in response to a Gi Load Once the counter is armed the Gi Reload Source Switching bit determines the load source After the counter is armed writing this bit has no effect 6 5 Gi Stop Mode This bit determin
61. ree H ANSI API arm ASIC asynchronous negative of or minus per percent plus or minus positive of or plus amperes American National Standards Institute application programming interface to enable a counter to application specific integrated circuit a property of an event that occurs at an arbitrary time without synchronization to a reference clock National Instruments Corporation start an operation If the application requires a trigger an armed counter waits for the trigger to begin the operation G 1 660x Register Level Programmer Manual Glossary base address buffer buffered bus clock cm CMOS CompactPCI crosstalk current drive capability current sinking current sourcing 660x Register Level Programmer Manual G 2 bit one binary digit either O or 1 byte eight related bits of data an eight bit binary number Also used to denote the amount of memory required to store one byte of data a memory address that serves as the starting address for programmable registers All other addresses are located by adding to the base address a block of memory used to store measurement results a type of measurement in which multiple measurements are made consecutively and measurement results are stored in a buffer the group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other device
62. register The counter uses the Gi DMA Read bitin the Gi DMA Status register to tell the software which register to read When Gi DMA Read is 0 the most recent buffered counter value is in the HW Save register When Gi DMA Read is 1 the most recent buffered counter value is in the SW Save register Counter Timer Functions and Examples The GPCT provides counter timer functions that are improved over those available on Am9513 based DAQ devices Event counting period measurement pulse generation and pulse train generation are examples of existing counter timer functions the NI TIO supports Enhancements to the existing counter timer functions include quadrature encoder support and the ability to perform buffered mode operations 660x Register Level Programmer Manual 2 2 ni com Chapter 2 General Purpose Counter Timers Event Counting In event counting functions the counter counts events on the Selected Source input following the software arm The software arm occurs when software sets the counter arm bit in the command register The following actions are available in event counting e The Selected Source increments or decrements the counter e The Selected Gate indicates when to start and stop counting intervals or when to save the counter contents to the save register e The software either reads the counter value asynchronously from the Gi Save register or it reads the HW Save or SW Save register each time the hardware latches t
63. ry board user manuals explain how to connect system parts National Instruments Corporation ix 660x Register Level Programmer Manual About This Manual Conventions lt gt bold italic monospace This manual uses the following conventions Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIG 0 lt 3 0 gt This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Bold text denotes items that you must select or click on in the software such as menu items and dialog box options Bold text also denotes parameter names Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Text in this font denotes sections of code programming examples and syntax examples This font is also used for the proper names of programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts Related Documentation The following documents contain information that you might find helpful as you read this manual e 6601 6602 User Manual Note to Users About Your 6608 Device e PXI Specification Revision 1 0 e PICMG Com
64. s are connected Examples of PC buses are the AT EISA and PCI bus Celsius hardware component that provides timing for various device operations centimeters complementary metal oxide semiconductor an electrical superset of the PCI bus architecture with a mechanical form factor suited for industrial applications an unwanted signal on one channel due to activity on a different channel the amount of current a digital or analog output channel is capable of sourcing or sinking while still operating within voltage range specifications the ability of a DAQ board to dissipate current for analog or digital output signals the ability of a DAQ board to supply current for analog or digital output signals National Instruments Corporation DAQ DAQ STC DC decode device DIO DLL DMA driver duty cycle Glossary data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer a custom ASIC developed by National Instruments that provides timing information and general purpose counter timers on National Instruments E Series boards direct current used in the context of motion encoders The two channels of
65. t Tri art Trigger Source Line A AUX LINE B q Gate Line Z 32 Bit Up Down Counter INTERRUPT Save Registers Figure 1 2 General Purpose Counter Timer Simplified Model Each GPCT counter has a source input Selected Source a gate input Selected Gate and a second gate input AUX_LINE that doubles as an up down control input When the counter is enabled rising edges on the Selected Source input cause the counter to increment or decrement The Selected Gate input acts as a general purpose control signal and can operate as a counter trigger signal a counter enable a save signal a reload signal an interrupt an output control signal a load register select signal or a counter disarm The AUX_LINE can determine whether the counter counts up or down 660x Register Level Programmer Manual 1 4 ni com Chapter 1 About the 660x Devices The counter outputs are the signals labeled G_LOUT and INTERRUPT G_OUT is acounter TC related signal that can toggle on every counter TC or output the counter TC signal directly INTERRUPT is an interrupt signal routed to the MITE The load registers reload the counter with new count values and the save registers save the counter contents until the software can read them Pulse Generation In pulse generation mode the counter decrements until reaching terminal count the output of the counter changes and a load register reloads the counter The s
66. t sets when the SW Save Register is latched for reading 660x Register Level Programmer Manual 3 30 ni com Chapter 3 Register Maps G01 Joint Status 1 Register Address Offset 0x036 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X Serial In X X X X Progress 7 6 5 4 3 2 1 0 X X X X G1 Gate G0 Gate G1 Bank GO Bank Bits Name Description 12 Serial in Progress This bit indicates that hardware serial to parallel conversion is in progress 3 2 Gi Gate This bit reads the state of the selected gate signal after polarity selection 1 0 Gi Bank This bit indicates which bank of A and B registers the counter is using 0 Bank X Bank Y National Instruments Corporation 3 31 660x Register Level Programmer Manual Chapter 3 Register Maps G23 Joint Status 1 Register Address Offset 0x136 Type Read Size 16 bit Bit Map 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X G3 Gate G2 Gate G3 Bank G2 Bank Bits Name Description 3 2 Gi Gate This bit reads the state of the selected gate signal after polarity selection 1 0 Gi Bank This bit indicates which bank of A and B registers the 660x Register Level Programmer Manual counter is using 0 Bank X Bank Y 3 32 ni com 13 12 Gi HW Save Gi Output National
67. ta loss Selected Source Counter Value HW Save Register Software Arm CLL DLA 1 2 3 4 5 6 7 3 6 Figure 2 3 Cumulative Event Counting Buffered Noncumulative Event Counting Buffered noncumulative event counting is similar to simple event counting but buffered noncumulative event counting has multiple counting intervals The Selected Gate signal indicates the boundary between consecutive counting intervals The counter counts the number of pulses occurring on the Selected Source signal after the software arm Each active edge of the Selected Gate signal latches the count value for the current counting interval into either the HW Save or SW Save register and reloads the counter with the initial value to begin the next counting interval An interrupt notifies the CPU after each counting interval so that the interrupt software can read the result from the HW Save register Figure 2 4 shows buffered noncumulative event counting with two counting intervals Three events are counted in each of the two counting intervals The counter configuration is as follows e Source external signal e Gate external signal Trigger mode gate ignored e Load on gate National Instruments Corporation 2 5 660x Register Level Programmer Manual Chapter 2 General Purpose Counter Timers e Interrupt on gate e Read from determined by Gi DMA Status register e Direction up Load on gate re
68. te direction The Z signal reloads the counter when Index Mode is enabled The X1 mode increments or decrements the counter once per total phase 3 10 ni com National Instruments Corporation Chapter 3 Register Maps 010 Quadrature Mode X2 This mode counts on both edges of the A signal Two counts per cycle are recorded 011 Quadrature Mode X4 This mode counts on both edges of the A and B signals Four counts per cycle are recorded 100 Two Pulse Mode In this mode a rising edge on the A signal increments the counter and a rising edge on the B signal decrements the counter The counter reloads while the Z signal is high and enabled 110 Synchronous Source Mode Several counter features such as hardware save and load depend on source edges to operate However it is sometimes necessary to measure event rates down to 0 Hz Synchronous Source Mode runs the counter at maximum timebase but enables it on a source edge to mimic running off that source while providing a free running clock 3 11 660x Register Level Programmer Manual Chapter 3 Register Maps Gi DMA Config Register Address Offsets Ox0B8 GO OxOBA G1 Ox1B8 G2 OxIBA G3 Type Write Size 16 bit Bit Map 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 Gi DMA Int Gi DMA Gi DMA Write Enable Bits Name Description 2 Gi DMA Int Direct Memory Access Interrupt
69. terrupt is detected before the previous one has been acknowledged Gi Gate Error Confirm clears this bit 13 12 Gi TC Error Terminal Count Error This bit sets when two terminal count interrupts occur without an acknowledgment Gi TC Error Confirm clears this bit 11 10 Gi No Load Between Gates This bit indicates that a load did not occur between the selected gate edges Gi Load or Gi Reset clears this bit 9 8 Gi Armed This bit sets when the counter is armed 7 6 Gi Stale Data This error bit sets if two relevant GATE edges occur National Instruments Corporation without a SRC edge between them Because reaction to GATE edges depends on the SRC edges it may have generated incorrect data The synchronous counting mode is one way to prevent this error In this mode the Stale bit updates on each GATE edge and reflects the state of the HW Save register The Permanent Stale Data bit located 3 29 660x Register Level Programmer Manual Chapter 3 Register Maps in the Joint Status 2 register records the error until it is cleared 5 4 Gi Next Load Source This bit indicates which load bank to load from next 0 Load register A Load register B 3 2 Gi Counting Gi Counting is asserted when the counter is armed and enabled for counting It reflects the state of the terms used for GATE or TC disabling the counter When the counter is not armed the bit is ignored 1 0 Gi Save Gi Save indicates the state of the SW Save register I
70. terrupt request signal industry standard architecture Laboratory Virtual Instrument Engineering Workbench a National Instruments graphical programming application meters maximum the fastest internal timebase available on a device For 6601 devices the maximum timebase is 20 MHz For 6602 devices the maximum timebase is 80 MHz minimum a custom ASIC designed by National Instruments that implements the PCI bus interface The MITE supports bus mastering for high speed data transfers over the PCI bus 660x Register Level Programmer Manual Glossary motion encoders NI DAQ NI TIO noise 0 operating system transducers that generate pulses to indicate the physical motion of a device The most common type of motion encoders are quadrature encoders Two pulse encoders also referred to as up down encoders are another example NI driver software for DAQ hardware a custom ASIC developed by National Instruments that provides counter and digital I O functionality an undesirable electrical signal noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send Or receive base level software that controls a computer runs programs interacts with users and comm
71. tion All rights reserved Important Information Warranty The PCI 6601 PCI 6602 PXI 6602 and PXI 6608 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the e
72. unicates with installed hardware or peripheral devices PCI Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 Mbytes s PFI programmable function input port 1 a communications connection on a computer or a remote controller 2 a digital port consisting of lines of digital input and or output ppm parts per million prescaling the division of frequency of an input signal that is to be used as SOURCE of a counter 660x Register Level Programmer Manual G 6 National Instruments Corporation programmed I O PXI Q quadrature encoders R reflection RG ribbon cable ringing RTSI Bus HW Save register source National Instruments Corporation G 7 Glossary a data transfer method in which the CPU reads or writes data as prompted by software modular instrumentation standard based on CompactPCI developed by National Instruments with enhancements for instrumentation a motion encoder that has two channels channels A and B Pulses and phases of pulses on channels A and B carry information about degree and direction of movement A third channel channel Z may also exist that provides a reference point for position a high speed signal transition behaves like a wave and is reflected like a wave at
73. using Timebase 3 and upon detecting National Instruments Corporation 3 48 660x Register Level Programmer Manual Chapter 3 Register Maps a state change require it to be in the same state for a minimum pulse width either internally generated or selected from a RTSI line 000 Input signal unchanged 001 Input synchronized to Timebase 3 010 Digital filter minimum pulse width is 100 assertions of Timebase 1 011 Digital filter minimum pulse width is 20 assertions of Timebase 1 100 Digital filter minimum pulse width is 10 assertions of Timebase 1 101 Digital filter minimum pulse width is 2 assertions of Timebase 1 110 Digital filter minimum pulse width is 2 assertions of Timebase 3 MITE The MITE is located on PCI BARO offset 0x0 To enable the BARI address space where the NI TIOs are located write to the I O Device Window Base Size Register IODWBSR on the MITE The IODWBSR determines the location of the I O device window in the CPU address space This window is used to access the DEVICE address space on the I O port For example if the PCI PXI device base address range 0 is BARO and the card base address range 1 is BARI enable BARI with the following Write32 BARO OxCO BAR1 amp OxFFFFFFOOL 0x80 660x Register Level Programmer Manual 3 44 ni com Chapter 3 Register Maps 1 0 D
74. vent that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments

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