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SH7455 Group, SH7456 Group Example of EEPROM Control Using

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1. Transmit receive end No Communication timeout v e SPOSR MIDLE 1b e Has 50 us or more elapsed after transmission of READ instruction SPODCR SPFC 11b SPOSCR SPSLN 11b SPOCMDi SPB 1111b SPOCMDk SSLKP 1b SPOCMDi CPHA 1b i 0 to 3 k 1 to 3 e SPOSR SPTEF 1b SPODR Returns dummy data 4 times in succession serial transfer clock output Is data read processing of EEPROM addresses H 38 to H 3B in progress e SPOSR SPTEF 1b e Has 100 us or more elapsed after transmission of dummy data e SPOCMD3 SSLKP 0b e SPOSR SPRF 1b e Has 100 us or more elapsed after transmission of dummy data Error handler Notes 1 See 4 5 1 Timeout Durations 2 During communication set the RSPI transfer format to read data from EEPROM addresses H 3C to H SF final 64 bits of data Figure 4 4 Function read 2 3 RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 RENESAS Page 20 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Yes Overrun error occurred e SPOSR OVRE 1b No Overrun error handler before reading receive data Repeat store SPODR Read receive data register read data in RAM four times Increment read address by 4 Yes Overrun error occurred SPOSR OVRF 1b m4 Overrun err
2. Error handler Notes 1 See 4 5 1 Timeout Durations 2 Maximum chip erase duration see EEPROM datasheet Figure 4 9 Function erase 3 4 RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 27 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 Transmission of write disable instruction EWDS instruction To disable writing to the EEPROM the function transmits a write disable instruction EWDS instruction to the EEPROM An overview of the operation is shown below Figure 4 10 is a flowchart of the function An EWDS instruction is transmitted The SSLOO signal is asserted H output during transmission of the EWDS instruction After transmission of the EWDS instruction the SSLO0 signal is negated L output The same RSPI transfer format shown in table 4 7 of 1 Transmission of write enable instruction EWEN instruction is used to transmit the EWDS instruction RO1AN0191EJ0100 Rev 1 00 Page 28 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI No e SPOSR SPTEF 1b Transmit buffer empty o e Transmit EWDS instruction Transmit receive end Communication timeout Yes SPODR H 100 SPOSR SPRF 1b Has 50 us or more elapsed after transmission of EWDS instruction Overrun error occurred Clear RSPI receive
3. vY Clear receive buffer full flag SPOSR SPRF Ob Clearing of overrun No error flag complete e SPOSR OVRF 0b Clearing of receive No buffer full flag complete d SPOSR SERE ON No Transmit buffer empty e SPOSR SPTEF 1b Yes af Disable RSPI functions and x1 initialize internal sequencer SPOCR SPE 0b Enable RSPI functions SPOCR SPE 1b 2 Send the address where error occurred by WRITE instruction 4 a End of overrun error handler Error handler transmitting the WRITE instruction Notes 1 The SSLOO signal is negated L output by disabling RSPI functions 2 Processing of the write function is halted when the SSLOO signal is negated L output as referenced in note 1 so a WRITE instruction must be transmitted after RSPI functions are enabled Figure 4 23 Overrun Error Handler Transmitting the WRITE Instruction RO1AN0191EJ0100 Rev 1 00 Page 48 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 5 Reference Documents SH7455 Group SH7456 Group User s Manual Hardware Rev 1 10 RO1UH0030EJ0110 The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com inquiry RO1AN0191EJ0
4. e SSL signal level hold Negation of all SSL signals at transfer end e RSPCK phase Data change at odd edge data sampling at even edge Port G settings e Input threshold value CMOS input 0 70 Vcc e PG3 SSLOO output PG2 RSPCKO output PG1 MISOO input PGO MOSIO output TMU channel 0 settings e Counter input clock Pck 4 e Interrupt at underflow Disabled e TMOCNT counter value H FFFF FFFF e TMOCNT counter setting value at underflow H FFFF FFFF e TMO counter start Counter operates RO1AN0191EJ0100 Rev 1 00 Page 14 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI CG Start of function rspi_ini E pi_init lt l d Initialize RSPIO control register SPOCR H 00 v oe SPOPCR H 20 Initialize RSPIO SPOBR H 09 SPODCR H 00 SPOCKD H 00 SPOSSLND H 00 SPOND H 00 SPOCMDi H E701 i 0 to 3 SPOSSLP H 01 v PGLVR H 000B Initialize I O ports PGCR1 H 3111 vY T TMOCR H 0000 Initialize TMU TMOCOR H FFFF FFFF TMOCNT H FFFF FFFF v Start TMU count operation TMSTR H 01 v Initialize error code to H 00 no error x1 v Select RSPIO master mode SPOCR H 08 Aa A End of function rspi_init D d Note 1 See 4 5 2 Error Handling Figure 4 1 Function rspi_init Function R01AN0191EJ0100 Rev 1 00 Pag
5. 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 2 EEPROM Instruction Set Table 3 1 lists the EEPROM instructions used in the sample code The instruction set codes are taken from the EEPROM datasheet Table 3 1 EEPROM Instruction Set Instruction Data Length Code Description EWEN 9 bits H 130 Write enable EWDS 9 bits H 100 Write disable READ 9 bits H 180 Read data lower 6 bits are address data WRITE 9 bits H 140 Write data lower 6 bits are address data ERAL 9 bits H 120 Chip erase erases entire address space 3 3 RSPI Register Settings Table 3 2 lists the RSPI channel 0 settings used in the sample code The setting values listed are the values used in the sample code and differ from the initial settings When changing setting values set values according to the standards for the target device In the text the names of the bits in the registers are notated in the format register name dot bit name Example SPB bit in the SPOCMD0 register gt SPOCMD0 SPB RO1AN0191EJ0100 Rev 1 00 Page 5 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Table 3 2 RSPI Operation Overview Example of EEPROM Control Using the RSPI Function Setting Master slave mode Master mode RSPI mode SPI operation four wire Serial transfer clock frequency RSPCK 2 MHz Data format MSB first Data length 9 bits EEPROM instruction transmit 16 bits E
6. Clearing of overrun error flag complete SPOSR OVRF 0b Clearing of receive No SPOSR SPRF 0b buffer full flag complete gt Yes Disable RSPI functions and SPOCR SPE 0b initialize internal v Enable RSPI functions SPOCR SPE 1b Send the address where error occurred by READ instruction v a End of overrun error handler N _ before reading receive data d Error handler Notes 1 The SSLOO signal is negated L output by disabling RSPI functions 2 Processing of the read function is halted when the SSLOO signal is negated L output as referenced in note 1 so a READ instruction must be transmitted after RSPI functions are enabled Figure 4 21 Overrun Error Handler Before Reading Receive Data RO1AN0191EJ0100 Rev 1 00 Page 46 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 6 Overrun Error Handler After Reading Receive Data Figure 4 22 illustrates the process for recovering from an overrun error that occurs after reading receive data C Start of overrun error handler after reading receive data v Clear overrun error flag v Clear receive buffer full flag Clearing of overrun No error flag complete Clearing of receive No buffer full flag complete Y
7. G H and J Setting Address Value Bit Description H FFFF 5B00 H 0OOB 15to12 0 Reserved bits The write value should always be 0 11 PJPIEN 0000 Input prohibited state 10 PJSCSEL 9 PJSELO 8 PJSEL1 7 PHPIEN 0000 Input prohibited state 6 PHSCSEL 5 PHSELO 4 PHSEL1 3 PGPIEN 1011 Port G input level CMOS input 0 70 Vcc 2 PGSCSEL 1 PGSELO 0 PGSEL1 2 Port G Control Register 1 PGCR1 PGCR1 is used to select RSPI related settings as the functions of the multiplexed pins of port G Setting Address Value Bit Description H FFFF 5816 H 3111 15 0 Reserved bit The write value should always be 0 14t012 PG3MD 011 SSLOO input output RSPI 11 0 Reserved bit The write value should always be 0 10 to 8 PG2MD 001 RSPCKO input output RSPI 7 0 Reserved bit The write value should always be 0 6 to 4 PG1MD 001 MISOO input output RSPI 3 0 Reserved bit The write value should always be 0 2to0 PGOMD 001 MOSIO input output RSPI RO1AN0191EJ0100 Rev 1 00 Page 11 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 5 TMU Register Settings The register settings used in the sample code with relation to TMU channel 0 are described below The setting values listed are the values used in the sample code and differ from the initial settings 1 TM Start Register TMSTR TMSTR selects whether the
8. H FFFF FFFF 31to0 TMOCOR 32 bit value that will be loaded into the TMOCNT counter when the TMOCNT counter underflows RO1AN0191EJ0100 Rev 1 00 Page 12 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 6 File Composition Table 3 5 lists the files used in the sample code Table 3 5 Files Used in the Sample Code File Name Outline dbsct c Section B and section D setting file env inc Exception event register and interrupt event register address definition file main c Main function program resetprg c Reset program rspi c rspi h RSPI control program and header file sh7455_iodefine_20101029 h SH7455 Group and SH7456 Group peripheral function register definition file stacksct h Stack size definition file typedefine h Type declaration file vect inc Vector definition file vecttbl src Interrupt vector table definition file vhandler src Interrupt handler program 3 7 Section Information Table 3 6 lists section information Table 3 6 Section Information Address Description H 0000 0000 RSTHandler Reset handler H 0000 0800 INTHandler Exception interrupt handler VECTTBL Vector table INTTBL Interrupt mask table H 0000 1000 PResetPRG Reset program H 0000 3000 P Program area C Constant area C BSEC Section B initialization table C DSEC Section D initialization table D Initialization data area H E500 E000 B Varia
9. Serial data input MISOO RSPIO data input input DO Serial data output Note SSL00 RSPCKO MOSIO and MISOO must be connected to external pull down resistors Figure 1 1 RSPI and EEPROM Connection Example 1 2 Operation Confirmation Conditions Table 1 1 lists the conditions that apply to the sample code Table 1 1 Operation Confirmation Conditions Item Contents MCU SH7455 Group SH7456 Group Input clock frequency 20 MHz Internal clock frequency CPU clock Ick 160 MHz setting SHwy clock SHck 80 MHz Peripheral clock Pck 40 MHz Operating mode Single chip mode Development tool Renesas Electronics High performance Embedded Workshop Version 4 08 00 011 C C Compiler Renesas Electronics C C Compiler Package for SuperH RISC Engine Family V 9 03 Release 02 RO1AN0191EJ0100 Rev 1 00 Page 2 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 2 Hardware 2 1 Pins Used Table 2 1 lists the pin functions when RSPI channel 0 is set to single master mode which is used by the sample code Pins SSLO1 to SSLO3 are not used Table 2 1 Pins Used and Their Functions Pin Name 1 0 Function RSPCKO Output RSPIO clock output MOSIO Output RSPIO data output MISOO Input RSPIO data input SSLOO Output RSPIO slave select 2 2 Renesas Serial Peripheral Interface RSPI The RSPI in the SH7455 Group and SH7456 Group has three channels RSPIO to RSPI2 enabling hi
10. TMOCNT counter operates or is stopped Setting Address Value Bit Description H FFFF D004 H 01 7to3 0 Reserved bits The write value should always be 0 2 STR2 0 The TM2CNT counter is stopped 1 STR1 0 The TM1CNT counter is stopped 0 STRO 1 The TMOCNT counter operates 2 TMO Control Register TMOCR TMOCR selects the counter clock and controls the generation of interrupts Setting Address Value Bit Description H FFFF D010 H 0000 15to9 0 Reserved bits The write value should always be 0 8 UNF 0 Indicates that a TMOCNT counter underflow has not occurred 1 Indicates that a TMOCNT counter underflow has occurred 7 6 0 Reserved bits The write value should always be 0 5 UNIE 0 The underflow interrupt TUNI is disabled 4 3 0 Reserved bits The write value should always be 0 2 to 0 TPSC 000 Set Pck 4 as the TMOCNT count clock 3 TMO Counter TMOCNT TMOCNT is a down counter that is decremented by the input clock signal selected by the TPSC bits in the TMOCR register Address Setting Value Bit Description H FFFF DOOC H FFFF FFFF 31to0 TMOCNT 32 bit counter value 4 TMO Constant Register TMOCOR The value of the TMOCOR register is loaded into the TMOCNT counter when an underflow occurs as the result of decrementing the TMOCNT counter and decrementing of the TMOCNT counter then continues from the loaded value Address Setting Value Bit Description H FFFF D008
11. at even edge SPOCMDO CPHA 0b Set RSPCKO phase data change at odd edge and data sampling at even edge SPOCMDi CPHA 1b i 0 to 3 RSPCKO A Set RSPI data length to 9 bits SPOCMDO SPB 1000b Set RSPI data length to 16 bits SPOCMDi SPB 1111b i 0 to 3 READ M F 5 OE Dummy data 16 bits x 4 Dummy data 16 bits x 4 Dummy data 16 bits x 4 MOSIO K gt Hi Z MISOO Read data 16 bits x 4 Read data 16 bits x 4 Read data 16 bits x 4 lt 2 gt Processing 1 3 Process descriptions 1 Transmission of data read instruction READ instruction 2 Continuous data read Figure 4 2 RSPI Timing Chart Overview of Function read RO1AN0191EJ0100 Rev 1 00 Page 16 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 1 Transmission of data read instruction READ instruction To read data from the EEPROM the function transmits a data read instruction READ instruction and read address to the EEPROM An overview of the operation is shown below Figure 4 3 is a flowchart of the function e H 00 EEPROM start address is specified as the read address e A READ instruction is transmitted to the EEPROM e While transmitting the READ instruction the SSLOO signal H output is asserted e After transmitting the READ instruction assertion of SSLOO signal H output is maintained e The RSPI transfer format shown in table 4 3 is used to tra
12. buffer full flag Overrun error occurred b d Overrun error handler no retransmission necessary No RSPI in idle state Yes RSPI idle timeout v SPOSR OVRF 1b SPOSR SPRF 0b Discard unneeded data received from EEPROM SPOSR OVRF 1b SPOSR MIDLE 1b Has 50 us or more elapsed after transmission of EWDS instruction Disable RSPI functions Y SPOCR SPE Ob v End of function erase gt Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 10 Function erase 4 4 RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 29 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 4 Function write Table 4 8 shows an overview of function write and figure 4 11 is an RSPI timing chart overview of the function Before using this function it is necessary to execute function rspi_init once User defined data H ASAS in the sample code this value has no particular significance is written to the entire address space of the EEPROM Table 4 8 Overview of Function write Return Function Arguments values Description write Write data None Writes the write data stored at the address specified by the argument address sequentially to the entire address space of the EEPROM from the start address H 00 to the end address H 3F Function write pe
13. e The RSPI transfer format shown in table 4 12 is used while waiting for the data write to complete Items that differ from table 4 11 are shown in bold text e When data writing continues to the next address the RSPI transfer format table 4 10 is set for 2 Transmission of data write instruction WRITE instruction after waiting for the data write to complete Notes 1 The data H 000 transmitted when checking the EEPROM s data write state is the value specified in the EEPROM datasheet 2 The EEPROM outputs L data when data writing is in progress and H data after the data write completes Table 4 12 RSPI Transfer Format for Waiting for the Data Write to Complete Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data SPOCMD0 SPB 1000b Set data length to 9 bits length SSL signal SPOCMDO SSLKP 0b Negate all SSL signals at transfer end level hold RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge Note 1 This RSPI transfer format is set in 3 Transmission of write data RO1AN0191EJ0100 Rev 1 00 Page 37 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 No Transmit buffer empty SPOSR SPTEF 1b Yes e SPODR H 000 Output serial transfer clock w
14. error flag complete SPOSR OVRF 0b Clearing of receive buffer full flag complete N p SPOSR SPRF 0b No Transmit buffer empty SPOSR SPTEF 1b yes Disable RSPI functions and x initialize internal sequencer SPOCR SPE 0b Enable RSPI functions e SPOCR SPE 1b Send the address where error occurred by READ instruction 4 End of overrun error handler bo A p Error handler transmission of READ instruction Notes 1 The SSLOO signal is negated L output by disabling RSPI functions 2 Processing of the read function is halted when the SSLOO signal is negated L output as referenced in note 1 so a READ instruction must be transmitted after RSPI functions are enabled Figure 4 20 Overrun Error Handler Transmission of READ Instruction RO1AN0191EJ0100 Rev 1 00 Page 45 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 5 Overrun Error Handler Before Reading Receive Data Figure 4 21 illustrates the process for recovering from an overrun error that occurs before reading receive data a Start of overrun error handler N before reading receive data A v Clear overrun error flag SPOSR OVRF 0b vy Read receive data from before error occurred Update read data storage address No
15. mode e CMOS open drain output switching function e RSPI disable initialization function Note RSPCK Serial transfer clock RO1AN0191EJ0100 Rev 1 00 Page 3 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 Software 3 1 Operation Overview The sample code uses the RSPI to read erase and write to the entire address space of the EEPROM Figure 3 1 outlines the overall process g Start D a v Initialize settings e Execute function rspi_init v Read EEPROM Execute function read read EEPROM data v Erase EEPROM e Execute function erase v Execute function read 3 0 Gonfimisrasure ot If data read from the EEPROM is all H FFFF EEPROM A chip erasure was completed successfully Write to EEPROM e Execute function write v 2 Execute function read Confirm write to EEPROM Read the EEPROM data and compare it with the write source data If there are no differences the write was completed successfully v End Notes 1 This process is included with general applications in mind but it is not essential 2 Confirmation processes are included with general applications in mind but the sample code does not implement error handling The user should add error handler code when necessary Figure 3 1 Outline of the Overall Process RO1AN0191EJ0100 Rev 1 00 Page 4 of 49 Mar
16. more elapsed after transmission of write data Communication timeout Overrun error occurred SPOSR OVRF 1b e SPOSR SPRF 0b Clear RSPI receive buffer Discard unneeded data received from full flag EEPROM Overrun error occurred SPOSR OVRE 1b D a Overrun error handler no retransmission necessary v 4 Error handler Notes 1 See 4 5 1 Timeout Durations 2 During communication the RSPI transfer format is set to that for waiting for the data write to complete as described in 4 Waiting for data write to complete Figure 4 14 Function write 3 6 RO1AN0191EJ0100 Rev 1 00 Page 36 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 Waiting for data write to complete The function waits for writing of data to the EEPROM to complete An overview of the operation is shown below Figures 4 15 and 4 16 are flowcharts of the function e All L data H 000 is transmitted to the EEPROM e The SSLOO signal is asserted H output during transmission of all L data H 000 e After transmission of all L data the SSLOO signal is negated L output e During writing of the data data other than all H data H 1FF is received from the EEPROM e After writing of the data is completed all H data H 1FF is received from the EEPROM
17. of function rspi_init and H EF81 when reading data from the EEPROM refer to section 4 1 for details on the rspi_init function For details of the register configuration and the functions of the bits see 7 RSPIO Command Register 0 SPOCMD0 Setting Address Value Bit Description H FFFF B012 H E701 See 7 RSPIO Command Register 0 SPOCMDO or H EF81 9 RSPIO Command Register 2 SPOCMD2 SPOCMD2 sets the transfer format of RSPI command register 2 The setting value is H E701 after execution of function rspi_init and H EF81 when reading data from the EEPROM refer to section 4 1 for details on the rspi_init function For details of the register configuration and the functions of the bits see 7 RSPIO Command Register 0 SPOCMD0 Setting Address Value Bit Description H FFFF B014 H E701 See 7 RSPIO Command Register 0 SPOCMDO or H EF81 RO1AN0191EJ0100 Rev 1 00 Page 8 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 10 RSPIO Command Register 3 SPOCMD3 SPOCMD3 sets the transfer format of RSPI command register 3 The setting value is H E701 after execution of function rspi_init 4 1 and H EFO1 when reading final address data from the EEPROM and H EF81 when reading data from the EEPROM refer to section 4 1 for details on the rspi_init function For details of the register configuration and the functions of the bits see 7 RSPIO Command Register 0 SPOCMD0 Settin
18. serial transfer clock RSPCKO is output If the SSLOO signal is in the asserted state H output after receiving a READ instruction the EEPROM automatically increments the address by 1 each time 16 bits of data is output It is therefore not necessary to specify the read address with subsequent READ instructions To negate the SSLOO signal L output after the final 64 bits of data have been read the RSPI transfer format for the data the final 64 bits of data at EEPROM addresses H 3C to H 3F table 4 5 is set while the data at EEPROM addresses H 38 to H 3B is being read To control the continuous data read process the read address is incremented by 4 each time 64 bits of data is read The RSPI transfer format shown in table 4 4 is used to read the data at EEPROM addresses H 00 to H 3B Items that differ from table 4 3 are shown in bold text The RSPI transfer format shown in table 4 5 is used to read the data at EEPROM addresses H 3C to H 3F the final 64 bits of data Items that differ from table 4 4 are shown in bold text Table 4 4 RSPI Transfer Format for Reading Data at EEPROM Addresses H 00 to H 3B Setting Item Register Value Description Frame count SPODCR SPFC 11b Set frame count to 4 Sequence length SPOSCR SPSLN 11b Set sequence length to 4 SPOCMDi Datalength SPOCMDi SPB 1111b Set data length to 16 bits i 0 to 3 SSL signal SPOCMDi SSLKP 1b Hold SSLOO signal level after transfer level hold end t
19. 00b SPOSCR SPSLN 00b CMDO CMDO CMDO CMDO CMDO Make setting to negate all SSL signals at transfer end SPOCMD SSLKP 0b ah nn nann Set RSPCKO phase to data sampling at odd edge and data change at even edge SPOCMDO CPHA Ob Set RSPI data length to 9 bits SPOCMDO SPB 1000b EWEN ERAL EF L EWDS instruction instruction data data instruction MOSIO K gt Execution of ERAL instruction completed Waiting for execution of l k ERAL instruction to gt gt complete data data S Processing 11 11 110 Processing descriptions 1 Transmission of write enable instruction EWEN instruction 2 Transmission of chip erase instruction ERAL instruction 3 Waiting for chip erase to complete 4 Transmission of write disable instruction EWDS instruction Figure 4 6 RSPI Timing Chart Overview of Function erase RO1AN0191EJ0100 Rev 1 00 Page 22 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 1 Transmission of write enable instruction EWEN instruction To enable writing to the EEPROM the function transmits a write enable instruction EWEN instruction to the EEPROM An overview of the operation is shown below Figure 4 7 is a flowchart of the function e An EWEN instruction is transmitted to the EEPROM e The SSLOO signal is asserted H output during transmission of the EWEN instruction e After transmission of the EWEN instruction the SS
20. 1 0 Reserved bit The write value should always be 0 0 SPLP 0 Normal mode 4 RSPIO Clock Delay Register SPOCKD Sets the period RSPCK delay from the beginning of SSL signal assertion to RSPCK oscillation Setting Address Value Bit Description H FFFF BOOC H 00 7to3 0 Reserved bits The write value should always be 0 2to0 SCKDL 000 1RSPCK 5 RSPIO Slave Select Negation Delay Register SPOSSLND SPOSSLND sets the period SSL negation delay from the transmission of the final RSPCK edge to the negation of the SSL signal during a serial transfer by the RSPIO in master mode Setting Address Value Bit Description H FFFF BOOD H 0O 7to3 0 Reserved bits The write value should always be 0 2to0 SLNDL 000 1RSPCK 6 RSPIO Next Access Delay Register SPOND Specifies the non active period next access delay of the SSL signal after the end of a serial transfer Setting Address Value Bit Description H FFFF BOOE H 00 7to3 0 Reserved bits The write value should always be 0 2to0 SPNDL 000 1 RSPCK 2 Pck RO1AN0191EJ0100 Rev 1 00 Page 7 of 49 Mar 2 2012 7tENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 7 RSPIO Command Register 0 SPOCMD0 SPOCMD0 sets the transfer format of RSPI command register 0 The setting value is H E701 after execution of function rspi_init H E800 during transmission of the EWEN instruction during transmission of the EWDS
21. 100 Rev 1 00 Page 49 of 49 Mar 2 2012 RENESAS Revision History Example of EEPROM Control Using the RSPI Rev Date Description Page Summary 1 00 Mar 2 2012 First edition issued All trademarks and registered trademarks are the property of their respective owners General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of int
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23. EPROM data read write Frame count sequence length 1 EEPROM instruction transmit EEPROM data write 4 EEPROM data read RSPI data register access width 16 bits RSPI data register read value Receive buffer RSPI output pins CMOS output SSL signal active polarity H Idle time RSPCK polarity L Idle time MOSI fixed value L RSPCK delay 1 RSPCK SSL negation delay 1 RSPCK Next access delay 1 RSPCK 2 Pck RSPCK phase Master transmit SPOCMDi CPHA 0 i 0 to 3 Data change Even edge falling edge Data sampling Odd edge rising edge Master receive SPOCMDi CPHA 1 i 0 to 3 Data change Odd edge rising edge Data sampling Even edge falling edge SSL signal level hold During READ instruction transmit processing During EEPROM data read processing During WRITE instruction transmit processing From transfer end to the next access start the SSL signal level from the previous data transfer is maintained Other than the above All SSL signals are negated at transfer end Generation of RSPI interrupts 1 RSPIO Control Register SPOCR Disabled The SPOCR register sets the operating mode of RSPIO The setting value is H 00 when SPOCR is initialized in function rspi_init H 08 when RSPI functions are disabled after execution of function rspi_init and H 48 when RSPI functions are enabled after execution of function rspi_init refer to section 4 1 for details on t
24. Frame C Frame D A yY Y y y Data length 8 bits Data length 9 bits Data length 10 bits Data length 11 bits SPOCMDO SPB 0100b to 0111b SPOCMD1 SPB 1000b SPOCMD2 SPB 1001b SPOCMD3 SPB 1010b Figure 3 2 Frame Configuration Example Table 3 4 Setting Value Combinations for SPSLN and SPFC Bits Transfer Transfer Frame Transfer SPSLN Bits SPFC Bits Frame Count Sequence Bit Count 00b 00b frame count 1 1 A 8 bits sequence length 1 01b frame count 2 2 A gt A 16 bits 10b frame count 3 3 A gt A gt A 24 bits 11b frame count 4 4 A gt A gt A A 32bits 01b 01b frame count 2 2 A gt B 17 bits sequence length 2 11b frame count 4 4 A gt B gt OA gt B 34bits 10b 10b frame count 3 3 A gt B gt C 27 bits sequence length 3 11b 11b frame count 4 4 A gt B gt C gt D 38bits sequence length 4 RO1AN0191EJ0100 Rev 1 00 Page 10 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 4 1 0 Port Register Settings The register settings used in the sample code with relation to I O port G are described below The setting values listed are the values used in the sample code and differ from the initial settings When changing setting values make settings according to the standards for the target device 1 Port GHJ Input Threshold Value Switching Register PGLVR PGLVR sets the input threshold values of ports
25. LOO signal is negated L output e The RSPI transfer format shown in table 4 7 is used to transmit the EWEN instruction Table 4 7 RSPI Transfer Format for Function erase Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data length SPOCMDO SPB 1000b Set data length to 9 bits SSL signal SPOCMDO SSLKP Ob Negate all SSL signals at transfer end level hold RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge RO1AN0191EJ0100 Rev 1 00 Page 23 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI g Start of function erase No RSPI functions disabled SPOCR SPE 0b Yes SPODCR SPFC 00b Set RSPIO transfer format SPOSCR SPSLN 00b e SPOCMDO SPB 1000b e SPOCMDO SSLKP Ob e SPOCMDO CPHA 0b Enable RSPI functions e SPOCR SPE 1b Clear receive buffer full flag SPOSR SPRF 0b Valid data found in data register No receive data in data register SPOSR SPRF 0b No valid data in data register No i Transmit buffer empty gt SpoR SPTE zib Yes Transmit EWEN instruction e SPODR H 130 No SPOSR SPRF 1b Transmit receive end Has 50 us or more elapsed after Communicatio
26. RENESAS OO APPLICAToNnoTE SH7455 Group SH7456 Group ROTAN01910100 Example of EEPROM Control Using the RSPI Mata 2012 Abstract This application note describes using the Renesas Serial Peripheral Interface RSPI in the SH7455 Group and SH7456 Group to control the S 93C46B serial EEPROM manufactured by Seiko Instruments Inc An explanation of the sample code for controlling the EEPROM when connected to the four wire serial interface of the RSPI is provided below Products SH7455 Group SH7456 Group Contents 1 OVOIVIOW 2 ce eeeccccc cece cece cece cece cnet eet ee ee aeee cnet ee cae aa aeeeeeee es cae aaaanaeceeeeecggeaaaeaeeeeeeesggecaaeeeceeeeeseeecsaeeeseseeseesineeeeees 2 1 1 Specifications siiacrsaidnnire tua cnenvandsaavn tad duvdcadaucened endvessatlawsnin eddie a a a a a i a A aa 2 1 2 Operation Contirmation Conditions c ssssoseossse iesi aaa N NAE NER 2 2 HardWare seisonnan a a E E E a A AEE E ANE B 3 2 1 Pins USCC viccacecsananadcanceaveds a a a a aa aa aaa a a aE A E REA 3 2 2 Renesas Serial Peripheral Interface RSPI esssesssrressennansnnnnneennannnnnaaetnnaanannnneennadnannaattnnaanannnaaeennaa 3 Da SOfIWaTE octet a eaaa ENE AAEE nA EAA EE eas EDANE EAA Aa EEKE A TEKKE EEEE EAA AEE OERE EE DEEE EA a 4 3 1 Operation OVerviS W rodina aan a a a aaa a aa a aaa aa Saa aaaea aaa 4 32 EEPROM Instruction Sebrsa REE EE 5 39 RSP Ragistor SOUINGS asririorirhin rania EAE EE REEN 5 34 VO Pot Register SettingS sesuneriiisi
27. ROM start address H 00 SPOSR SPRF 1b Has 50 us or more elapsed after transmission of READ instruction Overrun error occurred Clear receive buffer full flag Yes Overrun error occurred vy Overrun error handler transmit READ instruction e SPOSR OVRF 1b e SPOSR SPRF 0b Discard unneeded data received from EEPROM e SPOSR OVRF 1b v Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 3 Function read 1 3 R01AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 18 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 2 Continuous data read The function outputs the serial transfer clock RSPCKO and reads data from the entire address space of the EEPROM An overview of the operation is shown below Figures 4 4 and 4 5 are flowcharts of the function After the final 64 bits of data are read the RSPI transfer format is changed during communication to negate the SSLOO signal L output Data is read in 64 bit units 16 bits x 4 from the entire address space of the EEPROM from the start address H 00 to the end address H 3F Assertion of the SSL00 signal H output is maintained during continuous data read and the SSLOO signal L output is negated after the end of continuous data read To read data dummy data user defined value is transmitted and the
28. ansmit buffer empty and RSPI transfer format cannot be switched H 4 Cannot enter state valid receive data in SPODR register H 5 RSPI cannot enter idle state H 6 After clearing RSPI receive buffer full flag cannot enter state no valid receive data in SPODR register H 7 EEPROM chip erase did not complete within the specified time H 8 EEPROM data write did not complete within the specified time H 9 After overrun error flag cleared by overrun error handler cannot enter state no overrun error H A After RSPI receive buffer full flag cleared by overrun error handler cannot enter state no valid receive data in SPODR register Note 1 This error is specific to the sample source code and is not listed in the hardware manual R01AN0191EJ0100 Rev 1 00 Page 42 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI lt Start of error handler gt Disable RSPI functions e SPOCR SPE Ob Save error code gucErrCode error code n Halt program infinite loop RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 Figure 4 18 Error Handler Page 43 of 49 7tENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 3 Overrun Error Handler No Retransmission Necessary Case Where Retransmission of EEPROM Command Instruction Not Needed Figure 4 19 illustrates the process for recove
29. ata Processing k 1 k 2 f 3 y 14 K l 5 gt lt Processing descriptions 1 Transmission of write enable instruction EWEN instruction Repeat processes 2 to 4 until 2 Transmission of data write instruction WRITE instruction writing of data to entire EEPROM 3 Transmission of write data address space is complete 4 Waiting for data write to complete 5 Transmission of write disable instruction EWDS instruction Figure 4 11 RSPI Timing Chart Overview of Function write RO1AN0191EJ0100 Rev 1 00 Page 30 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 1 Transmission of write enable instruction EWEN instruction To enable writing to the EEPROM the function transmits a write enable instruction EWEN instruction to the EEPROM An overview of the operation is shown below Figure 4 12 is a flowchart of the function e An EWEN instruction is transmitted to the EEPROM e The SSLOO signal is asserted H output during transmission of the EWEN instruction e After transmission of the EWEN instruction the SSLOO signal is negated L output e The RSPI transfer format shown in table 4 9 is used to transmit the EWEN instruction e During transmission of the EWEN instruction the RSPI transfer format table 4 10 is set for 2 Transmission of data write instruction WRITE instruction Table 4 9 RSPI Transfer Fo
30. ations error handler and overrun error handler are described below 4 5 1 Timeout Durations The timeout durations related to the RSPI are designed to provide sufficient time while taking into account the serial transfer clock frequency data length RSPCK delay SSL negation delay and next access delay When making changes to the RSPI transfer settings the timeout durations should be modified as needed The value of the EEPROM chip erase and data write timeout durations are taken from the EEPROM datasheet If the EEPROM is changed the timeout durations should be modified after referring to the datasheet 4 5 2 Error Handler After disabling the RSPI functions the error handler stores the error code in a global variable gucErrCode and halts the program with an infinite loop The error codes are listed in tables 4 14 and 4 15 Error codes not listed in these tables are reserved values Figure 4 18 is a flowchart of the error handler Table 4 14 Error Codes Upper 4 Bits Error Code Process Generating Error H O No error H 1 read processing H 2 erase processing H 3 write processing Table 4 15 Error Codes Lower 4 Bits Error Code Process Generating Error H O No error H1 RSPI functions already enabled at start of processing of function read function erase or function write H 2 Buffer state other than transmit buffer empty before transmission H 3 Buffer state other than tr
31. ble area R Initialized variable area H E501 1C00 S Stack address area R01AN0191EJ0100 Rev 1 00 Mar 2 2012 Page 13 of 49 7tENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 RSPI Functions The functions defined in the file rspi c for initialization rspi_init reading read erasing erase writing write and error handling are described below To use these functions it is necessary to include the file rspi h 4 1 Function rspi_init Table 4 1 provides an overview of function rspi_init and figure 4 1 is a flowchart of the function It is necessary to execute function rspi_init once before using function read function erase or function write Table 4 1 Overview of Function rspi_init Return Function Arguments values Description rspi_init None None RSPI channel 0 settings e Master slave mode Master mode e RSPI mode SPI operation four wire e Serial transfer clock frequency RSPCK 2 MHz e Data format MSB first e RSPI data register access width 16 bits e RSPI data register read value Receive buffer e RSPI output pins CMOS output e SSL signal active polarity H e Assert settings for SSLO1 to SSLOO signals SSLOO setting e Idle time RSPCK polarity L e Idle time MOSI fixed value L e RSPCK delay 1 RSPCK e SSL negation delay 1 RSPCK e Next access delay 1 RSPCK 2 Pck e Generation of RSPI interrupts Disabled e Frame count 1 e Data length 8 bits
32. e falling edge phase Data sampling Odd edge rising edge Note 1 This table is identical to table 4 12 RO1AN0191EJ0100 Rev 1 00 Page 40 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Transmit buffer empty No e SPOSR SPTEF 1b Yes Transmit EWDS instruction Transmit receive end No Communication timeout Yes SPODR H 100 e SPOSR SPRF 1b e Has 50 us or more elapsed after transmission of EWDS instruction Overrun error occurred Clear RSPI receive buffer full flag Overrun error occurred vw Overrun error handler no retransmission necessary No RSPI in idle state Yes RSPI idle timeout wv e SPOSR OVRF 1b SPOSR SPRF Ob Discard unneeded data received from EEPROM SPOSR OVRF 1b e SPOSR MIDLE 1b Has 50 yus or more elapsed after transmission of EWDS instruction Disable RSPI functions v SPOCR SPE Ob v 4 Q End of function write Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 17 Function write 6 6 R01AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 41 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 Regarding Error Handling The timeout dur
33. e 15 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 2 Function read Table 4 2 provides an overview of function read and figure 4 2 is an RSPI timing chart overview of the function Before using this function it is necessary to execute function rspi_init once Table 4 2 Overview of Function read Return Function Arguments values Description read Storage address None e Reads the entire address space of the EEPROM from the for read data start address H 00 to the end address H 3F e Stores the read data at the address specified by the argument Function read performs the following two processes 1 Transmits the data read instruction READ instruction 2 Performs continuous data read Set frame count and sequence length to 1 SPODCR SPFC 00b SPOSCR SPSLN 00b iia frame count and sequence length setting to 4 SPODCR SPFC 11b SPOSCR SPSLN 11b St ae emool omy omoe cw cmoal cwos cmoo cog om couoe cw ovo2lfouos emod emool omo lowe cw coal cog Set a value so the SSLOO signal level is held until the start of the next access after transfer end SPOCMDO SSLKP 1b Set a value so the SSLOO ae level is held until the start of the next access after transfer end SPOCMDk SSLKP 1b k 1 to 3 Set a value so all SSL signals are negated after the next transfer end SPOCMD3 SSLKP 0b SSLOO a Set RSPCKO phase to data sampling at odd edge and data change
34. e RSPI transfer format shown in table 4 11 is used to transmit the write data Items that differ from table 4 10 are shown in bold text During transmission of the write data the RSPI transfer format table 4 12 is set for 4 Waiting for data write to complete Table 4 11 RSPI Transfer Format for Transmission of the Write Data Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data SPOCMD0 SPB 1111b Set data length to 16 bits length SSL signal SPOCMDO SSLKP 0b Negate all SSL signals at transfer end level hold RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge Note 1 This RSPI transfer format is set in 2 Transmission of data write instruction WRITE instruction RO1AN0191EJ0100 Rev 1 00 Page 35 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI No Transmit buffer empty SPOSR SPTEF 1b Yes Transmit write data e SPODR user defined write data Transmit buffer empty e SPOSR SPTEF 1b No e Has 50 us or more elapsed after Transmit buffer empty timeout transmission of write data Change SPOCMDO transfer format of RSPIO SPOCMDO SPB 1000b 4 Transmit receive end e SPOSR SPRF 1b Has 50 us or
35. e enable instruction EWEN instruction is used to transmit all L data H 000 Notes 1 The data H 000 transmitted when checking the EEPROM s chip erase state is the value specified in the EEPROM datasheet 2 The EEPROM outputs L data when the chip erase is in progress and H data after the chip erase is completed RO1AN0191EJ0100 Rev 1 00 Page 26 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Transmit buffer empty Yes No Transmit all L data H 000 Transmit receive end Overrun error occurred No Communication timeout Read receive data Overrun error occurred Yes v v Overrun error handler no retransmission necessary Overrun er no retransmission necessary ror handler Chip erase complete Yes No Chip erase timeout Yes v e SPOSR SPTEF 1b e SPODR H 000 Output serial transfer clock with MOSIO in L state e SPOSR SPRF 1b Has 50 us or more elapsed after transmission of all L data H 000 SPOSR OVRF 1b Read SPODR register clear receive buffer full flag e SPOSR OVRF 1b ls the value read from the SPODR register H 1FF Has 8 ms or more elapsed after transmission of ERAL instruction 3
36. enesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 5 When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations 6 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in o
37. ernal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is s
38. es v Disable RSPI functions and initialize internal sequencer v Enable RSPI functions v Send next read address by READ instruction C End of overrun error handler y after reading receive data xi 2 v SPOSR OVRF 0b SPOSR SPRF 0b SPOSR OVRF 0b SPOSR SPRF 0b SPOCR SPE 0b SPOCR SPE 1b The next address has already been specified by incrementing the address by 4 before the overrun error handler runs so this next address is transmitted by the read instruction Error handler Notes 1 The SSLOO signal is negated L output by disabling RSPI functions 2 Processing of the read function is halted when the SSLOO signal is negated L output as referenced in note 1 so a READ instruction must be transmitted after RSPI functions are enabled Figure 4 22 Overrun Error Handler After Reading Receive Data RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 47 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 7 Overrun Error Handler Transmitting the WRITE Instruction Figure 4 23 illustrates the process for recovering from an overrun error that occurs when transmitting of the WRITE instruction a Start of overrun error handler N transmitting the WRITE instruction v Clear overrun error flag SPOSR OVRF 0b
39. g Address Value Bit Description H FFFF B016 H E701 See 7 RSPIO Command Register 0 SPOCMDO or H EF01 or H EF81 11 RSPIO Bit Rate Register SPOBR SPOBR sets the bit rate when the RSPIO is in master mode Setting Address Value Bit Description H FFFF BOQA H 09 7 to0 SPR7 to These bits set the bit rate in master mode The setting SPRO value specifies a serial transfer clock frequency of 2 MHz Pck 40 MHz An equation for calculating the bit rate from the SPOBR setting value and the setting value of the BRDV bits in RSPIO command registers 0 to 3 SPOCMD0 to SPOCMD3 is given below f Pck 2 x SPOBR 1 x 28R0V Bit rate The relationship between the SPOBR setting value the setting value of the BRDV bits and the bit rate when Pck equals 40 MHz is shown in table 3 3 Table 3 3 Relationship between SPOBR Setting Value Setting Value of BRDV Bits and Bit Rate Pck 40 MHz SPOBR Register Setting Value of Setting Value BRDV Bits Division Ratio Serial Transfer Clock Frequency 1 0 4 10 MHz 2 0 6 6 67 MHz 3 0 8 5 MHz 4 0 10 4 MHz 5 0 12 3 33 MHz 1 24 1 67 MHz 2 48 0 83 MHz 3 96 0 42 MHz 9 0 20 2 MHz 255 3 4096 9 77 kHz RO1AN0191EJ0100 Rev 1 00 Page 9 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 12 RSPIO Sequence Control Register SPOSCR SPOSCR sets the sequence control method when the RSPI operates in master mode The setti
40. ge caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 10 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electro
41. gh speed serial communication in full duplex synchronous mode between multiple processors and peripheral devices Table 2 2 provides an overview of the RSPI Table 2 2 Overview of the RSPI Item Description Transfer functions e Selectable between SPI four wire and clock synchronous three wire serial communication e Selectable between master and slave mode e Mode fault error and overrun error detection e Selectable serial transfer clock polarity and phase Data format e Switchable between MSB first and LSB first e Variable transfer bit length selectable among 8 to 16 20 24 and 32 bits e 128 bit transmit and receive buffers e Transfer of up to four frames maximum frame size 32 bits in a single transmit or receive operation Buffer configuration e Double buffer transmit and receive buffer configuration SSL control functions e Four SSL signals for each RSPI channel e RSPCK output and SSL assert negate delay setting Setting range 1 to 8 RSPCK cycles setting unit 1 RSPCK cycle e Selectable SSL polarity Control during master mode e Transfers composed of up to four commands can be executed transfer sequentially as loops e Initiation of transfers by the CPU or DMAC e Setting of MOSI signal level at SSL negation Interrupt sources e Maskable interrupt sources RSPI receive interrupt receive buffer full RSPI transmit interrupt transmit buffer empty RSPI error interrupt mode fault overrun Other e Loopback
42. he rspi_init function Setting Address Value Bit Description H FFFF B000 H 00 7 SPRIE 0 Disables generation of RSPIO receive interrupt requests or 6 SPE 0 Disables RSPIO functions H 08 1 Enables RSPIO functions or 5 SPTIE 0 Disables generation of RSPIO transmit interrupt requests H 48 4 SPEIE 0 Disables generation of RSPIO error interrupt requests 3 MSTR 0 Slave mode 1 Master mode 2 MODFEN _ 0 Disables mode fault error detection 1 0 Reserved bit The write value should always be 0 0 SPMS 0 SPI operation four wire RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 Page 6 of 49 7tENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 2 RSPIO Slave Select Polarity Register SPOSSLP SPOSSLP sets the polarity of the SSLOO and SSLO1 signals of RSPIO Setting Address Value Bit Description H FFFF B001 H 01 7t02 0 Reserved bits The write value should always be 0 1 SSL1P 0 SSLO1 signal is L active 0 SSLOP 1 SSLOO signal is H active 3 RSPIO Pin Control Register SPOPCR SPOPCR sets the modes of the RSPIO pins Setting Address Value Bit Description H FFFF B002 H 20 7 6 0 Reserved bits The write value should always be 0 5 MOIFE 1 MOSIO output value equals MOIFV bit setting value 4 MOIFV 0 MOSIO idle fixed value equals L level 3 0 Reserved bit The write value should always be 0 2 SPOM 0 CMOS output
43. instruction during transmission of the ERAL instruction or during transmission of data H 000 for EEPROM chip erase and obtaining the data write status H E880 during transmission of the READ instruction or WRITE instruction H EF00 when writing data to the EEPROM and H EF81 when reading data from the EEPROM refer to section 4 1 for details on the rspi_init function Setting Address Value Bit Description H FFFF B010 H E701 15 SCKDEN 1 RSPCK delay equals the RSPIO clock delay register or SPOCKD setting value H E800 14 SLNDEN 1 SSL negation delay equals the RSPIO slave select or negation delay register SPOSSLND setting value H E880 13 SPNDEN 1 Next access delay equals the RSPIO next access delay or register SPOND setting value H EFOO 12 LSBF 0 MSB first or 11to8 SPB 0100 to 0111 RSPI transfer data length 8 bits H EF81 1000 RSPI transfer data length 9 bits 1111 RSPI transfer data length 16 bits 7 SSLKP 0 Negate all SSL signals at transfer end 1 Maintain the SSL signal level from transfer end until the start of the next access 6to4 SSLA 000 SSLOO setting 3 2 BRDV 00 Select the base bit rate 1 CPOL 0 RSPCK equals 0 when idle 0 CPHA 0 Data sampling at odd edge data change at even edge 1 Data change at odd edge data sampling at even edge 8 RSPIO Command Register 1 SPOCMD1 SPOCMD sets the transfer format of RSPI command register 1 The setting value is H E701 after execution
44. ith Transmit all L data H 000 MOSIO in an L state e SPOSR SPRF 1b Transmit receive end e Has 50 us or more elapsed after transmission of all L data H 000 Communication timeout Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 15 Function write 4 6 RO1AN0191EJ0100 Rev 1 00 Page 38 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Yes Overrun error occurred No v Read receive data Overrun error occurred v Overrun error handler no retransmission necessary Yes v No Overrun error handler no retransmission necessary Data write complete No Yes v Increment write address by 1 Write address gt H 3F Transmit buffer empty No Change format of RSPIO SPOCMDO transfer Data write timeout Yes v 2 4 Error handler SPOSR OVRF 1b e Read SPODR register Clear receive buffer full flag SPOSR OVRF 1b e Is the value read from the SPODR register H 1FF Has 8 ms or more elapsed after transmission of write data Is writing to the entire address space of the EEPROM complete SPOSR SPTEF 1b SPOCMDO SSLKP 1b No
45. n timeout transmission of EWEN instruction Yes e SPOSR OVRF 1b Overrun error occurred Clear RSPI receive buffer e SPOSR SPRF 0b full flag Discard unneeded data received from EEPROM Yes SPOSR OVRF 1b Overrun error v Overrun error handler no retransmission necessary wv Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 7 Function erase 1 4 RO1AN0191EJ0100 Rev 1 00 Page 24 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 2 Transmission of chip erase instruction ERAL instruction To erase the entire address space of the EEPROM the function transmits a chip erase instruction ERAL instruction to the EEPROM An overview of the operation is shown below Figure 4 8 is a flowchart of the function e An ERAL instruction is transmitted to the EEPROM e The SSLOO signal is asserted H output during transmission of the ERAL instruction e After transmission of the ERAL instruction the SSLOO signal is negated L output e The same RSPI transfer format shown in table 4 7 of 1 Transmission of write enable instruction EWEN instruction is used to transmit the ERAL instruction No Transmit buffer empty Yes Transmit ERAL instruction No Transmit receive end Communication time
46. ng value is H 00 during EEPROM instruction transmission or when writing data to the EEPROM and H 03 when reading data from the EEPROM Setting Address Value Bit Description H FFFF B008 H 0O 7t02 0 Reserved bits The write value should always be 0 or 1 0 SPSLN 00 Sequence length 1 H 03 referenced SPOCMD register 0 0 11 Sequence length 4 referenced SPOCMD register 0 gt 1 gt 2 gt 3 0 13 RSPIO Data Control Register SPODCR SPODCR specifies the function of the RSPI data register SPODR The setting value is H 00 during EEPROM instruction transmission or when writing data to the EEPROM and H 03 when reading data from the EEPROM Setting Address Value Bit Description H FFFF BOOB H 00 7 6 0 Reserved bits The write value should always be 0 or 5 SPLW 0 Word 16 bit access to SPODR register H 03 4 SPRDTD 0 Reading SPODR register returns receive buffer value 3 2 0 Reserved bits The write value should always be 0 1 0 SPFC 00 Number of frames that can be stored in SPODR 1 11 Number of frames that can be stored in SPODR 4 Table 3 4 lists the setting value combinations for the SPFC bits and the SPSLN bits in the RSPIO sequence control register SPOSCR using the frame configuration example shown in figure 3 2 Subsequent operation cannot be guaranteed if a setting value combination other than those listed in table 3 4 is used Frame A Frame B
47. nics product s means any product developed or manufactured by or for Renesas Electronics 2tENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886
48. nir nina E EE 11 35 TMU Register Settings eee cece ee enn reenter een uA Annna EA AAA NANNA AEANAE KAANAA AENA ARANAN NA AAAA AEKA ARA AAEE AN 12 3 6 File COmpPosS t ON eiior nananana akai acak anaa KE Aak Cae Aeka rE a AKKE a E EEE EE 13 3 7 Section Informati n 0 eee cent ee etee rete ee ee eee ae ee tenet nan EAN ENEA TEKEE ERA KANANEN KAEA EERE 13 A RSPIFRURCIONS merdin da a a a a a a lia aaa 14 4 1 F nctionrspi Mites e ea ete EAE E E EE E OE A E ted aE i 14 42 Function tedd sesaat aea AE EEE EATE KEE EAEE edadveuthesteaeanae 16 AS Function erase siie ae A e a E gabe Eaa ENEE AE EERE EEA EE EE ea ANE E 22 4d Function Wite oroesi niea aia E dase AEAN EAE EE EAE ENa ANE 30 4 5 Regarding Eror Handling eacccnnesrorcaitairai anaE A EEE EE EEE steal E EES 42 4 5 1 Timeout D rations srra e EEE ETE A E a a 42 4 5 2 Error Handler ci cccecavccstehecsecetaszcesdulen ti cata veces tustageceeaak E AE E a EE EN a 42 4 5 3 Overrun Error Handler No Retransmission Necessary Case Where Retransmission of EEPROM Command Instruction Not Needed 0 ecececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeesenaeeesenanees 44 4 5 4 Overrun Error Handler Transmission of READ Instruction ceeeeeeeeeeeeeeeeenneeeeeeneeeeeeenaaes 45 4 5 5 Overrun Error Handler Before Reading Receive Data ecceeeeeeeeeeteneeeeeneeeeeeeneeeeeeaes 46 4 5 6 Overrun Error Handler After Reading Receive Data 0 eee ceeeceeeeeneeeeenneeeeeeneeeeeeeneeeeeeaae
49. nsmission of WRITE instruction Transmit buffer empty timeout Change SPOCMDO transfer SPOCMDO SSLKP Ob format of RSPIO e SPOCMDO SPB 1111b 4 Transmit receive end SPOSR SPRF 1b e Has 50 us or more elapsed after transmission of WRITE instruction Communication timeout Overrun error occurred SPOSR OVRF 1b SPOSR SPRF 0b Discard unneeded data received from EEPROM Clear RSPI receive buffer full flag Overrun error occurred SPOSR OVRF 1b Overrun error handler transmit WRITE instruction v Error handler Notes 1 See 4 5 1 Timeout Durations 2 During communication the RSPI transfer format is set to that for write data transmission as described in 3 Transmission of write data Figure 4 13 Function write 2 6 RO1AN0191EJ0100 Rev 1 00 Page 34 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 Transmission of write data The function transmits the write data to the EEPROM An overview of the operation is shown below Figure 4 14 is a flowchart of the function 16 bits of user defined write data H ASAS in the sample code is written to the EEPROM The SSLOO signal is asserted H output during transmission of the write data After transmission of the write data the SSLOO signal is negated L output Th
50. nsmit the READ instruction Table 4 3 RSPI Transfer Format for Transmission of READ Instruction Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data length SPOCMDO SPB 1000b Set data length to 9 bits SSL signal SPOCMDO SSLKP 1b Hold SSLOO signal level between transfer level hold end and start of next access RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge RO1AN0191EJ0100 Rev 1 00 Page 17 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Start of function read No RSPI functions disabled SPOCR SPE 0b Yes wv Set RSPIO transfer format v Initialize read address to H 00 wv Enable RSPI functions v Clear receive buffer full flag Forenede Valid data found in data register SPODCR SPFC 00b e SPOSCR SPSLN 00b e SPOCMDO SPB 1000b e SPOCMDO SSLKP 1b SPOCMDO CPHA Ob e SPOCR SPE 1b SPOSR SPRF Ob gt SPOSR SPRF 0b data register No valid data in data register gt SPOSR SPTEF 1b No Transmit buffer empty Yes Transmit READ instruction No Transmit receive end Communication timeout Yes SPODR H 180 Read address is EEP
51. nues to be asserted H output even after transmission of the WRITE instruction completes The RSPI transfer format shown in table 4 10 is used to transmit the WRITE instruction Items that differ from tables 4 9 and 4 12 are shown in bold text During transmission of the WRITE instruction the RSPI transfer format table 4 11 is set for 3 Transmission of write data Table 4 10 RSPI Transfer Format for Transmission of the WRITE Instruction Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data length SPOCMDO SPB 1000b Set data length to 9 bits SSL signal SPOCMDO SSLKP 1b Hold SSLO0 signal level after transfer level hold end to start of next access RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge Note 1 This RSPI transfer format is set in 1 Transmission of write enable instruction EWEN instruction and 4 Waiting for data write to complete RO1AN0191EJ0100 Rev 1 00 Page 33 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI No Transmit buffer empty e SPOSR SPTEF 1b Yes Transmit WRITE instruction SPODR H 140 write address No Transmit buffer empty SPOSR SPTEF 1b No e Has 50 us or more elapsed after tra
52. o start of next access RSPCK SPOCMDi CPHA 1b Data change Odd edge rising edge phase Data sampling Even edge falling edge Table 4 5 RSPI Transfer Format for Reading Data at EEPROM Addresses H 3C to H 3F Final 64 Bits of Data Setting Item Register Value Description Frame count SPODCR SPFC 11b Set frame count to 4 Sequence length SPOSCR SPSLN 11b Set sequence length to 4 SPOCMDj Data length SPOCMDj SPB 1111b Set data length to 16 bits j 0 to 2 SSL signal SPOCMDj SSLKP 1b Hold SSLOO signal level after transfer level hold end to start of next access RSPCK SPOCMDj CPHA 1b Data change Odd edge rising edge phase Data sampling Even edge falling edge SPOCMD3 Data length SPOCMD3 SPB 1111b Set data length to 16 bits SSL signal SPOCMD3 SSLKP 0b Negate all SSL signals at transfer end level hold RSPCK SPOCMD3 CPHA 1b Data change Odd edge rising edge phase Data sampling Even edge falling edge RO1AN0191EJ0100 Rev 1 00 Page 19 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI RSPI in idle state Yes RSPI idle timeout vY Set RSPIO transfer format Transmit buffer empty Yes Transmit dummy data Yes Read address H 38 No Transmit buffer empty No Transmit buffer empty timeout Change transfer format in SPOCMD3 of RSPIO
53. or handler after reading receive data Ne Completed reading the entire address space of the EEPROM Read address gt H 3F No RSPI in idle state SPOSR MIDLE 1b Yes N RSPI idle timeout 2 Has 100 ps or more elapsed after transmission l of dummy data Disable RSPI functions SPOCR SPE Ob A End of function read Error handler Note 1 See 4 5 1 Timeout Durations Figure 4 5 Function read 3 3 R01AN0191EJ0100 Rev 1 00 Page 21 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 3 Function erase Table 4 6 provides an overview of function erase and figure 4 6 is an RSPI timing chart overview of the function Before using this function it is necessary to execute function rspi_init once Table 4 6 Overview of Function erase Return Function Arguments values Description erase None None Erases the entire address space of the EEPROM After erasure the data value of the entire address space of the EEPROM is H FFFF Function erase performs the following four processes 1 Transmission of write enable instruction EWEN instruction 2 Transmission of chip erase instruction ERAL instruction 3 Waiting for chip erase to complete 4 Transmission of write disable instruction EWDS instruction Set frame count and sequence length to 1 SPODCR SPFC
54. ortation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life 8 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 9 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or dama
55. out Overrun error occurred Clear RSPI receive buffer full flag Yes Overrun error occurred v Overrun error handler no retransmission necessary Note 1 See 4 5 1 Timeout Durations e SPOSR SPTEF 1b e SPODR H 120 e SPOSR SPRF 1b e Has 50 us or more elapsed after transmission of ERAL instruction SPOSR OVRF 1b SPOSR SPRF 0b Discard unneeded data received from EEPROM SPOSR OVRF 1b v Error handler Figure 4 8 Function erase 2 4 R01AN0191EJ0100 Rev 1 00 Mar 2 2012 RENESAS Page 25 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 3 Waiting for chip erase to complete The function waits for erasure of the EEPROM chip to complete An overview of the operation is shown below Figure 4 9 is a flowchart of the function e All L data H 0000 is transmitted to the EEPROM e The SSLOO signal is asserted H output during transmission of all L data H 000 e After transmission of all L data H 000 the SSLOO signal is negated L output e When the chip erase is in progress data other than all H data H IFF is received from the EEPROM e After the chip erase is completed all H data H 1FF is received from the EEPROM e The same RSPI transfer format shown in table 4 7 of 1 Transmission of writ
56. r omissions from the information included herein 7 Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transp
57. rforms the following five processes 1 Transmission of the write enable instruction EWEN instruction 2 Transmission of the data write instruction WRITE instruction 3 Transmission of the write data 4 Waiting for data write to complete 5 Transmission of write disable instruction EWDS instruction Set frame count and sequence length to 1 SPODCR SPFC 00b SPOSCR SPSLN 00b CMDO CMDO Negate all SSL signals at transfer end SPOCMD SSLKP 0b v CMDO CMDO CMDO CMDO Make setting to maintain SSLOO signal level from after next transfer end to start of next access GPOCMDO SSLKP 1b Set so that all SSL signals are negated after next transfer end SPOCMDO SSLKP 0b Set so that SSLOO signal level is held until start of next access after transfer end SPOCMDO SSLKP 1b wnt l U m Set RSPCKO phase to data sampling at odd edge and data change at even edge SPOCMDO CPHA Ob Y seo M M M MA MA s Ml Set RSPI data length to 9 bits SPOCMDO SPB 1000b Set RSPI data length to 16 bits for next transfer SPOCMDO SPB 1111b Set RSPI data length to 9 bits for next transfer SPOCMDO SPB 1000b zy EWEN WRITE LY L EWDS instruction instruction Write data data data MOSIO K Waiting for execution of WRITE instruction to complete Execution of WRITE instruction ___ 4 4 completed MISOO0 Hi Z L H i data K d
58. ring from an overrun error when retransmission is not necessary Start of overrun error handler no retransmission necessary Y Clear overrun error flag v Clear receive buffer full flag Clearing of overrun error flag complete Yes Clearing of receive buffer full flag complete Transmit buffer empty No SPOSR OVRF 0b SPOSR SPRF Ob SPOSR OVRF 0b No SPOSR SPRF 0b No v Yes Disable RSPI functions and initialize internal sequencer v Enable RSPI functions 4 of overrun error handler no retransmission necessary SPOSR SPTEF 1b SPOCR SPE Ob SPOCR SPE 1b v Error handler Figure 4 19 Overrun Error Handler No Retransmission Necessary R01AN0191EJ0100 Rev 1 00 Mar 2 2012 7tENESAS Page 44 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 4 5 4 Overrun Error Handler Transmitting the READ Instruction Figure 4 20 illustrates the process for recovering from an overrun error that occurs during transmission of the READ instruction a Start of overrun error handler N transmitting the READ instruction v Clear overrun error flag SPOSR OVRF 0b v Clear receive buffer full flag SPOSR SPRF Ob Clearing of overrun No
59. rmat for Transmission of the EWEN Instruction Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data length SPOCMDO SPB 1000b Set data length to 9 bits SSL signal SPOCMDO SSLKP Ob Negate all SSL signals at transfer end level hold RSPCK SPOCMDO CPHA Ob Data change Even edge falling edge phase Data sampling Odd edge rising edge RO1AN0191EJ0100 Rev 1 00 Page 31 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI Start of function write D A d z No lt RSPI functions disabled SPOCR SPE 0b Yes SPODCR SPFC 00b SPOSCR SPSLN 00b Set RSPIO transfer format SPOCMDO SPB 1000b SPOCMDO SSLKP Ob SPOCMDO CPHA Ob Initialize write address to H 00 E2 Enable RSPI functions SPOCR SPE 1b v Clear receive buffer full flag SPOSR SPRF Ob _ Valid data found in data register oe No valid data in data register e SPOSR SPRF 0b v SPOSR SPTEF 1b v Transmit EWEN instruction SPODR H 130 k VA lt n buffer empty Yes No 1 P Has 50 us or more elapsed after ae a p transmission of EWEN instruction 2 Change SPOCMDO transfer 7 format of RSPIO Yes R e SPOCMDO SSLKP 1b SPOSR SPTEF 1b
60. s 47 4 5 7 Overrun Error Handler Transmission of WRITE Instruction 0 ccseeeeeseeeeeeeseeeeeeenneeeeeenaaes 48 5 Reference DOCUMENS ix ciecsacesdecisetect seee ceed ceree accede Hales EEEE EROE EE EO 49 RO1AN0191EJ0100 Rev 1 00 Page 1 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 1 Overview 1 1 Specifications The sample code uses the RSPI in the SH7455 Group and SH7456 Group to read erase and write to the entire address space 16 bits x 64 of the EEPROM connected externally according to the specifications listed below Timeouts are provided for read erase and write operations The timer unit TMU of the SH7455 Group and SH7456 Group is used as the timeout counter e A single master single slave configuration is used with the SH7455 Group and SH7456 Group as the master device and the EEPROM as the slave device e The RSPI of the SH7455 Group and SH7456 Group is connected to the EEPROM via a four wire serial interface Figure 1 1 shows a connection example e The EEPROM S 93C46B has a capacity of 1 kilobits configured as 16 bits x 64 Master Slave SH7455 Group SH7456 Group EEPROM SSLOO CS RSPCKO SK MOSIO DI MISOO DO GND GND GND GND e RSPIO pin assignments in single master mode SSLOO RSPIO slave select output CS Chip select input RSPCKO RSPIO clock output output SK Serial clock input MOSIO RSPIO data output output DI
61. table Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products Notice 1 All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website 2 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any R
62. tes 1 To continue writing to the next address the RSPI transfer format is set to that for transmission of the WRITE instruction as described in 2 Transmission of data write instruction WRITE instruction 2 Maximum data write duration see EEPROM datasheet RO1AN0191EJ0100 Rev 1 00 Mar 2 2012 Figure 4 16 Function write 5 6 7tENESAS Page 39 of 49 SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 5 Transmission of write disable instruction EWDS instruction To disable writing to the EEPROM the function transmits a write disable instruction EWDS instruction to the EEPROM An overview of the operation is shown below Figure 4 17 is a flowchart of the function e AnEWDS instruction is transmitted e The SSLOO signal is asserted H output during transmission of the EWDS instruction e After transmission of the EWDS instruction the SSLOO signal is negated L output e The RSPI transfer format shown in table 4 13 is used to transmit the EWDS instruction Table 4 13 RSPI Transfer Format for Transmission of the EWDS Instruction Setting Item Register Value Description Frame count SPODCR SPFC 00b Set frame count to 1 Sequence length SPOSCR SPSLN 00b Set sequence length to 1 SPOCMDO Data length SPOCMDO SPB 1000b Set data length to 9 bits SSL signal SPOCMDO SSLKP 0b Negate all SSL signals at transfer end level hold RSPCK SPOCMDO CPHA Ob Data change Even edg
63. zee SPOSR SPRF 1b esii n o Has 50 us or more elapsed after ag a transmission of EWEN instruction Yi es Overrun error occurred Yes SPOSR OVRF 1b e SPOSR SPRF 0b Discard unneeded data received from EEPROM Clear RSPI receive buffer full flag Yes lt i error i SPOSR OVRF 1b v Overrun error handler No no retransmission necessary v Error handler Notes 1 See 4 5 1 Timeout Durations 2 During communication the RSPI transfer format is set for 2 Transmission of data write instruction WRITE instruction Figure 4 12 Function write 1 6 RO1AN0191EJ0100 Rev 1 00 Page 32 of 49 Mar 2 2012 RENESAS SH7455 Group SH7456 Group Example of EEPROM Control Using the RSPI 2 Transmission of data write instruction WRITE instruction To write data to the EEPROM the function transmits a data write instruction WRITE instruction to the EEPROM An overview of the operation is shown below Figure 4 13 is a flowchart of the function A WRITE instruction is transmitted to the EEPROM Each time 16 bit data is write completed the write address increments by 1 with the specified write address changing sequentially from the start address of the EEPROM H 00 to the end address H 3F The SSLOO signal is asserted H output during transmission of the WRITE instruction The SSLOO signal conti

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