SMT6040 “Sundance Simulink Toolbox”
Contents
1. 32 Figure 28 output of the MIMO LTE demo e eeeeeeeee seine eene ne eene tenen etna eta seno stn seta sena eta 32 Figure 29 RadioGiga demo FPGA tasks in red DSP tasks in yellow 33 Figure 30 SMT6040 diagram for RadioGiga demo essere 34 Figure 31 logical connections between DSP tasks RadioGiga demo 35 Figure 32 output of the RadioGiga demo eese eee eese eee eee eee nennen etae ta sena ota 35 Figure 33 the SMT6040 Package ccsscsscsssssessessssssescessesscsssesessesaessesseeseeaeseeseeessessesesneeeses 37 Figure 34 a SMT6040 DSP FPGA ADC DAC design essere 41 Figure 35 root DEP sub system da 42 Figure 36 DSP hardware interface s sseoesesseseessesossosseroesosseseesorsessossenoesossesseseeseesessesseseesese 43 Figure 37 Diamond channel hardware interface esee 44 Figure 38 model DSP SUD 44 Figure 39 SMT350 FPGA ADC DAC sub system ooooccccnocoonconnononnnoncnnnnanononononnnnannnon cnn enene 45 Fiqure 10 LEDS OU P 45 Figure 41 DAC configuration PR 46 Figure 42 simulation TESSA ctp eds 48 Figure 43 SDR demo SMT6040 diagram esee eee eee esee eee cnn nonoconc tns etn sense ta sena sta 49 Figure 44 SMT8036E demo RR 51 Figure2. 20 Figure 13 Video demo FPGA tasks in red DSP tasks in yellow sss 21 Figure 14 logical connections between DSP tasks Video demo usus 22 Figure 15 Simulink diagram Video demo eres noo occo nooo coocon ccoo non oros 22 Figure 16 basic Video processing example sess 29 Figure 17 DVIP demo FPGA tasks in red DSP tasks in yellow esses 24 Figure 18 logical connections between DSP tasks DVIP demo eese 25 Figure 19 Simulink diagram DVIP demo 4 eeeeeeeeee e esee eese entente tne nonocos 25 Figure 20 basic Video processing example on DVIP s sssssssssessssssssssesssssersesersssssssrserssesesseseese 26 Figure 21 WiMAX demo FPGA tasks in red DSP tasks in yellow ss 27 Figure 22 SMT6040 diagram for WiMAX demo eerie eee ettet ette nn etna aeta enata cenae 28 Figure 23 logical connections between DSP tasks WiMAX demo sess 29 Figure 24 output of the WiMAX demo ivonne r ctn et err rete a br HR EYE daa 29 Figure 25 MIMO LTE demo FPGA tasks in red DSP tasks in yellow 30 Figure 26 SMT6040 diagram for MIMO LTE demo sees 31 Figure 27 logical connections between DSP tasks MIMO LTE demo
3. Unit Module Description Sundance Simulink Toolbox for DSP FPGA code generation Unit Module Number SMT6040 Document Issue Number 3 10 Issue Date 8 J anuary 2009 Original Author Simone Boragno SMT6040 Sundance Simulink Toolbox Abstract This document describes the SMT6040 a flexible tool for the co design and co generation of DSP and FPGA code from Simulink diagrams The SMT6040 specifically targets Sundance boards and comes with a number of demos for different systems The SMT6040 also allows the integration of Simulink designs with C code VHDL code and System Generator diagrams thus giving the maximum flexibility to the user Sundance Italia SRL This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission O Sundance Italia SRL 2009 Coriiicata Humber FM SHAT Revision History 10 1 Minor updates to demo descriptions 21 07 09 10 2 Added pictures and further information on the demos 06 08 09 3 0 1 Added description of SMT8036E and SMT8096 demo 18 11 09 3 0 0 New Version 3 0 12 10 09 3 10 New SDR RF MIMO and WiMAX demos 08 01 10 Table of Contents 1 The SMT6040 Toolbox ains ica Ea IR EAE M XY a F R oa 7 2 How to use the SMETBUAUD iisravera ei Reno REI FRNER ER F Aa a 7 2 1 Integrate a SMT6040 Simulink DSP design into Diamond sss 9 PNE S Uic
4. Figure 40 LEDs output This sub system is composed of three parts e LEDS thesim repeating sequence threesim digout SMT351T LEDx which make the LEDS the FPGA blink thus getting the results in Figure 40 e DAC the sim comport2FPGA sim demux2 two sim unit delay sim repeating sequence two sim sum2 sim DAC5686 SMT351T AC coupling SMT3950 e ADC the AC coupling two sim ADS5500 SMI351T ADCA B two sim zero order sim_mux2 sim FPGA2comport SMT35IT Exbended Block Parameters test SMTIJDITSXBU SMT352 5 speci lock parameters E Clock Frequency Hz 1440000 C Full typos made DAC reda dual DAC Filler rrtam elateen rali zx 15 E Land Mor Emi WOO Lane Frirguescy Rr Eidin Carrie Phase 2 38 degran 180 DDS gun D 203125 Paris spacinm use dual clack PLL dride mio PLL as 4 Counter moda anusad tard amp interius Eran PLL dithering Enable FETA synch inert Viel casual ramar IAS Gain ganire 1321 1 IDA Ofaa control 115 148 n ODAC Gain control 132 T 1 DDAC Offset corral PTE 14165 o gramar ranga 9 Ta Dipun eel v 7 Duft Prapertesa Pin mapping Call nad WHOL pa name Pert gin Connecter pin Da DAC pA MAA EE hac 041 E Carr ATI raf po T Figure 41 DAC configuration The DAC part does the following O O O It takes data coming from nodel via comport Demux data into two individual scalar channels Oversample both signals a
5. Asum ofthe two inputs is outputted on Diamond write Channel 0 The second input is passed through to Diamond write Channel 1 The sentence SMT6040 task is printed on the screen To compile the DSP6040 mdl design the following two steps are necessary 1 Double click on Digital HW Interface then click on Compile To HW SW Analog and Overall Build 2 Run the MATLAB command Diamond DSP6040 This command creates the file T6040 root tsk and runs a Diamond application that is not important in this case as the task will be used within a different Diamond project 2 12 Diamond project The original fpga example1 Diamond project had only one DSP task named driver In this case another DSP task is added named T6040 root Took Help Format Dic B X850 es tl o fitted Normal Gg d Simulation sim digHwinteiface SMT310Q psP6040 root File Edit View Simulation Format Tools Help DISES tSeleo tl 2 foes Normal J Rane Scope1 sim printf sim_digHvdntertace_SMT362 SMT6040 task sim_printt fim Diamond read 0 sim Diamond write O sim Diamond read 1 sim Diamond write 1 Figure 2 sample DSP diagram 10096 ode5 This additional task must have two input and two output ports to match the Simulink diagram in Figure 2 Moreover the Create Main Source File checkbox must not be ticked when creating the task
6. Each channel will be then mapped onto a comport or a SHB connection thus fully exploiting Sundance communication resources The SMT6040 will automatically configure the hardware and then manage the inter processor communication So the user does not need to worry about interrupts data flow etc This makes development much easier and faster To explain how SMT6040 and Diamond are combined to build a unique and powerful development environment we remind that Diamond users can divide the application into different logical tasks and assign each task to the processor DSP or FPGA on which they would like the task to be executed 5MT6040 Sonulink diagram DSP System Generator diagram FPGA FPGA code Diamond IDE Figure 1 integration of Simulink diagrams in Diamond A DSP task can be implemented in C but also generated from a Simulink Diagram thanks to the SMT6040 Similarly a FPGA task can be implemented in VHDL but also generated from a Simulink Diagram thanks to System Generator This procedure is shown in Figure 1 Section 2 1 describes how to integrate a Simulink DSP task into Diamond Section 2 2 describes how to integrate a Simulink FPGA task 2 1 Integrate a SMT6040 Simulink DSP design into Diamond The SMT6040 allows generating full applications targeting Sundance HW but it also supports Diamond DSP and it can be used to generate a DSP task This is very useful as it adds flexibility and it makes it
7. This task can be added to the SDR Diamond project as explained in Chapter 3 This new task can communicate for example with the smt350 DSP task For this purpose two input and one output ports have to be added to the smt350 task gt e 7 F o gi Fem on D Simulink diagram T6040 roottsk DSP task gJ Ua d II we How Andlog input Veen cee ee i i i I L L 1 L I LI l 1 I t L 1 1 4 z z L4 hj ul x H LE A m x o A A aa a a ee H Hd i 1 e ee as FEE aae i System Generator FPGA task he Ho DSo ume Figure 8 SMT8246 SDR demo FPGA tasks in red DSP tasks in yellow Fie Edt View ewisen Format Took Hep Dgu ve ee elo S fiie Nome EE wo EM iim degree ie EUITIO ra Tk Oud a iam b x ioe Nomai Fhag RDE Beso dab dig ky AEN asm Dileep adsl i wm C amiusd saria O Figure 9 SMT6040 diagram for SDR demo These ports need to be connected to the input output ports of the T6040 root task as shown in Figure 10 Figure 10 Logical connections between DSP tasks SDR demo Sundance Multiprocessor Technology Limited RD OARS SMT6040 Sundance Simulink Toolbox P e 6July 2006 In the main function in smt350 c the functions chan out message and ch
8. can be used respectively to send data to T6040 root and to receive the processed data from it Displays and printf statements will allow simple verification of the behaviour of the T6040_ root task designed in Simulink The folder WiMAXDemo contains a Simulink example which is used to generate a Diamond DSP task with two inputs and one output and the Diamond WiMAX demo to which the T6040 root DSP task is added Sundance Multiprocessor Technology Limited n SMT6040 Sundance Simulink Toolbox Pe 6Juy2006 MyDSPapp SMT6040 diagram T6040_root tsk DSP task i I 1 I BA Diamir why 0 1 I I Figure 23 logical connections between DSP tasks WiMAX demo r 2 Time domain Channel 2 SH m4 Ts Time domain Channel 1 3 Oo X Channel 1 FFT E Channel 2 FFT Figure 24 output of the WiMAX demo The SMT6040 task is dedicated to process the incoming data from the main task and to output again to the main task the processing results The diagram generating the task is represented in Figure 22 and the processing results of the WiMAX Diamond demo when calling the T6040 root task are pictured in Figure 24 In this picture it appears clear that SMT6040 Sundance Simulink Toolbox Page 29 of 53 Last Edited 08 01 2010 15 42 the Time domain Channel 1 output is equal to the sum of two signals identical to the one displayed as Time domain Channe
9. inserted into Diamond DVIP Demo 3 4 WiMAX demo gt Demo Release 3 0 pplications SundanceWiMAXWIiMAXDemo Same requirements as described in Chapter 2 This is the recommended demo for Special University Offer WiMAX users The diagram represented in Figure 21 pictures the structure of the demo gt Analog Lt eutput amma Ta Figure 21 WiMAX demo FPGA tasks in red DSP tasks in yellow The WiMAX demo is composed by a number of DSP and FPGA tasks The DSP task SMT903 DSP CONTROL sends control information to the FPGA and receives sends data to the FPGA task that deals with RF transmission As described in paragraph 3 1 1 a Diamond DSP task e g named T6040 root tsk can be created by the SMT6040 This task can be added to the WiMAX Diamond project as explained in Chapter 3 This new task can communicate for example with the SMT903_DSP CONTROL DSP task For this purpose two input and one output ports have to be added to the S5MT903 DSP CONTROL task Fie EJE Wew Simulation Format Took Hep sua belies pool Fere ABI wem tigre RATIO mea dipiin STIS zer Digyresrod rmand d mre Dire wanbg Di mer Diamard read Figure 22 SMT6040 diagram for WiMAX demo These ports need to be connected to the input output ports of the T6040 root task as shown in Figure 23 In the update thread function in SMT903 DSP CONTROL c the functions chan out message and chan in message
10. ru Molin MAD 0 Q T u ees EN Fars j an i d dec i Connections H a e ifi bute Correct Clicking tt z B ipgaexample 1 I correct connection bete El reach tet and destination Di node geste a connect n dhig the iem Q adn directly A adidone vhd Ej acidorge cf zi addone pkg vici hie current connections sap noct x 7 50d Name From Source Ta Demali Tyre B disc t5 clever 106040102 THOS unramed 1 lt Detaut gt h el tirer cx Or TO unnamed D Def gt ca TeO4D root urramed 1 deer Tamen 1 27 Defwit ia 9 TEMG root cz TE040_ root urramed 0 diver foms048 oii lt Deat gt SN Teo eth ll es mide DOUT der DINI Deni Ej T dd _roottsk a imer DET E akikre DIN ith Detail it Connectors w vrm ti 3 E Connections Figure 3 Diamond project and connections F2 3L Diamond Fpiga examgple T objec ling V driver amp IL Diamond Me oe uo bm EH 5 O0 G 6 H Taa E B 3 Damend M Diamond sowrc E O ia uu o o o z a7 temp inlei a ipgaczample 1 benp ineei E peace tet bg Hi z ride d ir siir peint Before SMT6040 processing sum td inletd inZ E addon uct chan out message eizeof Eleat temp inz stoplo m B adima vhd chan out message sizasf Flsat zrtemp inl amp to560J0 1 By addona xcf chan in message a31zaof float
11. DSP FPGA ADC DAC design Be pk ee Pee Fiat Too dep One PB Wt e ftom wr Dama il mm degbiedrinFuca id Te a DiE janpi Balabenal Digauriss mm D arsanred s ad SATIN mem seed mal Figure 35 root DSP sub system The sim digHwInterface block represents the Sundance carrier board generally a SMT310Q but thanks to Sundance modularity this same demo can be run on a SMT148 FX carrier without changing any SMT6040 parameters only the wires will need to be re defined in case different hardware links are in place Each processor is associated with a sim system block whose name will automatically be given to the corresponding Diamond nodes or FPGA configuration file It is important that one of the DSPs on the board located on TIM1 of the carrier is given the name root All the others may have any valid name alphanumeric characters no blank Inside each DSP that is inside each sim system there is a SMT6040 model of the algorithm that shall be placed onto that DSP For instance in node root double click on block root there is the sub system pictured in Figure 35 This shows how to use Diamond channels and how to process the data received by another processor Where the sim digHwInterface block represents one of the two DSPs of the SMT362 board so it is configured as in Figure 36 Please notice that the scrolldown menu allows selecting the target board among several Sundance boards so users can configure the a
12. ETT Figure 15 Simulink diagram Video demo The whole Simulink diagram top view and detail of the root subsystem is pictured in Figure 15 It is easy to understand the two simple processing steps applied by the SMT6040 task The result of the element by element subtraction of the input vectors is sent to output 1 Output 2 is a simple passthrough of input 2 However the second output of the Simulink task becomes the first input of the Diamond demo pal DSP task So the processing has two results the second line of the image is copied in place of the first line while the result of the subtraction replaces the second line passed to the Simulink task This process is executed on each of the three frames loaded by the DVL This is better explained by Figure 16 which shows on the left the original image and on the right the results of its binarization to black amp white and of the processing on the two lines in particular a white line replaces a line in the top half of the image while a dark line is drawn in the bottom half of the video Figure 16 basic Video processing example By using a similar procedure it is possible to add a DSP task created in Simulink to any of the DVL demos More complex application can easily be designed thanks to the integration of SMT6040 and Diamond The folder VideoDemo includes the Simulink project represented in Figure 15 that has been used to generate a DSP task named T6040
13. described below but these explanations apply also to the SMT8146 SMT8096 demos A similar structure is the base of the SMR8036E For this system the few differences with respect to the SMT8246 demo are explained in Paragraph 3 LT Same requirements apply as the ones described in Chapter 2 This is the recommended demo for Special University Offer SDR users This demo targets the SMT8246 system but it can be easily changed to target other SDR systems These demos have the structure described in Chapter 2 Therefore they are made of Simulink projects implementing DSP FPGA tasks and a Diamond IDE project that acts as integrator In particular in this same Diamond workspace different projects are available in order to target different SDR systems SMT8146 and SMT8246 with SMT350 or SMT950 and with optional SMT349 SMT8096 Each project can be considered separately and the same Simulink diagram is valid for all the demos only the DSP processor type should be changed to match the one of the system in use i e SMT362 SM374 or SMT395 The diagram in Figure 8 represents a more detailed structure of the demo The SDR 2 demo is composed by a number of DSP and FPGA tasks The main function is in the DSP task named smt350 This task receives the data from the FPGA and sends the proper data to the display and FFT processing tasks As described in Chapter 2 a Diamond DSP task e g named T6040 root tsk can be created by the SMT6040
14. instructions in the previous chapters The main demos included in Version 2 are described from paragraph 5 3 onwards The SMT6040 takes advantage of Sundance modularity and scalability to generate multi DSP multi FPGA applications from Simulink diagrams The same application can target different systems by few changes in the configuration Moreover the SMT6040 uses Diamond channels to implement the communication between processors So the user just needs to set up these virtual channels Each channel will be then mapped onto a comport or a SHB connection thus fully exploiting Sundance communication resources The SMT6040 will automatically configure the hardware and then manage the inter processor communication So the user does not need to worry about interrupts data flow etc This makes development much easier and faster We use now a sample application to demonstrate the SMT6040 features and to describe how to generate an application targeting a DSP FPGA ADC DAC system We consider the system diagram represented in Figure 34 This is composed by three main blocks each related to a processor and a number of other blocks that we will now outline A similar structure can be used for many different systems and applications Di dk gem Dmdanon Pyma foo feb D aud m BRE p Homai 3 Lj mmm prm Wgtuisiecyss EUITIO darum Baniera DEP FEA Tas s 10608 BER dim simil diae Figure 34 a SMI6040
15. system e Split each subsystem into a digital HW a SW and an analog HW part if any e Compile each part independently To build and execute the application on the hardware a wir file is necessary to define the hardware connections implemented as users might connect different comports or SHBs The followingis an example of wir file wire root CP 0 node1 CP 3 Internal connection between the two processors of SMT362 wire root CP 1 node1 CP 4 Internal connection between the two processors of SMT362 The following assume a physical comport cable from T1C2 TIM1 to T1C5 TIM2 wire nodel CP 2 root CP 5 Requires connection between T1C2 to T1C5 connect T6040 nodel 1 node1 CP 1 Requires connection between T1C1 to T2C4 connect root CP 4 T6040 root 0 Requires connection between T1C4 to T2C 1 The instruction Diamond modelname Builds the application composed by DSP program and FPGA bitstream download it onto the hardware and runs it Results can be verified from the data printed on the screen and by connecting the DAC output to an oscilloscope Sundance Multiprocessor Technology Limited Form QCF32 SMT6040 Sundance Simulink Toolbox P e 6July 2006 un E e a6 2S AGH ST Figure 42 simulation results 5 3 SDR demo No Sysgen Version 2 gt Demo Release_3 0 Applications Sundance SDR Version2 SMT8096_ noSysGen For these demos the SMT6040 require
16. 45 Video demo 2 DSP diaQram sssssessssscesssessssccsssessssscesssessssscescssaseeseseeesasenees 52 1 The SMT6040 Toolbox The SMT6040 is a MATLAB toolbox that allows generating DSP and FPGA code for Sundance boards from a Simulink diagram The users can describe their projects by means of a set of interconnected blocks which are functionally identical to those from the Simulink library math and logical operators non linear and trigonometric functions vector and matrix operations modulators etc The Sundance provided blocks have a Data Flow calculation paradigm just like Simulink blocks The SMT6040 blocks accurately simulate their digital and analog counterparts at the same time the entire system is kept hardware independent Together with Sundance Lego like modular approach the SMT6040 lets users port the same high level Simulink project to many different Sundance systems quickly and easily An advanced user can utilise the SMT6040 toolbox with all Sundance boards however a number of demos targeting the most common Sundance systems are provided to make the understanding and the use of the SMT6040 easier These ready and working diagrams give customers a great starting point for their projects The following chapter describes the SMT6040 functionalities Chapter 3 provides an overview of the main demos SDR Video DVIP MIMO LTE WiMAX RadioGiga Chapter 4 describes the structure of the package and how to navig
17. a demo testing the leds of the SMT365 board The other demos should only be used as examples for custom designs Version2_OLD SDR_SMT8036E SignalGenerator this folder contains a useful demo to test the SMT370 module Please follow the instructions provided with the SMT6040 The other folders in Version2 OLD SDR_SMT8036E DownConversion FMtransmitter FrequencyModulation include examples that advanced users can take as reference diagrams for their designs 4 5 Video To design complete applications including Video I O targeting Sundance Video kit and Sundance VisionMax kit the SMT6040 has to be used together with Diamond Video Library VideoDemo it includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project VideoDemo that uses this task More details in this regard in Chapters 3 and 4 It should be considered as the main Getting Started demo for the Video kit Version2 test_SMT8039 it contains an example targeting the SMI8039 system It illustrates how to create a DSP application using the SMT6040 and a default FPGA firmware without Diamond It is a simple example and is not optimised so performance is low 4 6 DVIP To design complete applications including Video I O targeting Sundance DVIP kit the SMT6040 has to be used together with Diamond Video Library DVIPDemo It includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project that uses this t
18. al to the sum of two signals identical to the one displayed as Time domain Channel 2 3 6 RadioGiga demo gt Demo Release_3 0 Applications Sundance R adioGiga R adioG igaDemo Same requirements as described in Chapter 2 This is the recommended demo for Special University Offer RadioGiga users o gumulink diagram 1604 D ronttzk DSP tak ra A a a 4 T 1 Analog m 1 Linger i comntpaat Analog e s input ouput Figure 29 RadioGiga demo FPGA tasks in red DSP tasks in yellow The diagram represented in Figure 29 pictures the structure of the demo The RadioGiga demo is composed by a number of DSP and FPGA tasks The main function is in the DSP task named root This task receives the data from the FPGA and sends the proper data to the display tasks As described in paragraph 3 1 1 a Diamond DSP task e g named T6040 root tsk can be created by the SMT6040 This task can be added to the SDR Diamond project as explained in Chapter 3 This new task can communicate for example with the root DSP task For this purpose two input and one output ports have to be added to the root task Wr He Ede Wew Simulation Format Took Hep mr Riad Miet sil Delay wm gar RATIO So pa7 Wes Wen Unit Dalap L7 DSPa 4d raot um dighzdrlartace ZBTORI zen Dime red rmad Hd mr Durs wacby Ti mer Ceara ned read A Figure 30 SMT6040 diagram for RadioGiga de
19. alities uiu sd RPM PR ERE FHEH EP REQUE RPISHA EHE UU DEDERE UR DEP I 41 5 2 Simulate and run an applicatiON cooocnooccconononononnnnonnconnocononnnnncnnncnono ene 47 5 3 SDRdemo No Sysgen Version 2 o usd dk pP v FARMER CO lia 48 5 4 SDR demo SMT8036E No Sysgen Version 2 eese 50 5 5 MIRO OO Version Lin ni i n 52 Lselul PESTO A A A it AREA 53 DL TOS tin 53 A STI e A 53 Table of Figures Figure 1 integration of Simulink diagrams in Diamond eese 8 Figure 2 sample DSP diagram i jacuacscutserinancisasdavesessecunnpeesdesonbensnccandasivsedssadeovssecauaasapeeedesontemasaees 10 Figure 3 Diamond project and connections sessi sees eene eene 11 Figure4 data transfer 11 Figure 5 channel configuration in System Generator esee 13 Figure 6 System Generator configuralion eese e eese ee eee eene tnt nette tasto ene etas enoen 15 Figure 7 netlist DIOSES riada FOR V d 15 Figure 8 SMT8246 SDR demo FPGA tasks in red DSP tasks in yellow 17 Figure 9 SMT6040 diagram for SDR demo esee 18 Figure 10 Logical connections between DSP tasks SDR demo sess 18 Figure 11 output of the SDR demo aaa 19 Figure 12 SMT8036E SDR demo FPGA tasks in red DSP tasks in blue
20. all users of the SMT8036E SDR Special University Offer Version2 SMT8096_noSysGen this folder includes obsolete demos targeting systems composed by SMT395 or SMT362 as DSP board and by SMT368 or SMT351T as FPGA board plus the SMT350 as DAQ module These demos are not supported but they can be utilized by advanced users for their custom developments These demos fully demonstrate the functionality of the hardware processing on the DSP and data acquisition from ADC DAC board through the FPGA These demos target a number of Sundance SDR systems as highlighted in the table below For more accurate descriptions please read Chapter 4 Please notice that these demos are designed for a PCI carrier SMT310Q Users of stand alone carriers e g SMT148 FX can easily modify these demos in particular comport connections to adapt them to their needs Demo System SMT8096 ADC DSP DAC mdl SMT8096 SMT395 SMT368 SMT350 SMT8096 DSP only mdl SMT8096 SMT395 SMT368 SMT350 test SMI368 SMI362 mdl SMT362 SMT368 SMT350 test SMT351TSX95_ SMT395VP30 mdl SMT395 SMT351TSX95 SMT350 test SMT351TSX50_ SMT395VP30 mdl SMT395 SMT351TSX50 SMT350 test SMI351TSX95 SMT362 mdl SMT3624SMT351TSX9545MT350 test SMI351ISX50 SMT362 mdl SMT362 SMT351TSX50 SMT350 test_SMT395 this folder contains a test demo for the SMT395 DSP Version2_OLD test_SMT368 this folder contains a demo that tests the SMT368 leds testLeds mdl and a d
21. an in message can be used respectively to send data to I 6040_ root and to receive the processed data from it Displays and printf statements in the main function will allow simple verification of the behaviour of the T6040_ root task designed in Simulink The folder SMT8246 SDRDemo contains a Simulink example which is used to generate a Diamond DSP task with two inputs and one output and the Diamond SDR demo to which the T6040 root DSP task is added The SMT6040 task is dedicated to process the incoming data from the main task and to output again to the main task the processing results The diagram generating the task is represented in Figure 9 and the processing results of the SDR Diamond demo when calling the T6040 root task are pictured in Figure 11 In this picture it appears clear that the Time domain Channel 1 output is equal to the sum of two signals identical to the one displayed as Time domain Channel 2 74 Time domain Channel 2 2 XX 7 Time domain Channel 1 m x IDE NM Ld AI MENTA MI MM LAM MA HARI MA lu I ae TURA TIT i WW 77 Channel 1 FFT Amplitude Amplitude i 100000 180088 Frequency Frequency Figure 11 output of the SDR demo 3 SMT6040 Sundance Simulink Toolbox Page 19 of 53 Last Edited 08 01 2010 15 42 3 11 SMI8036E SDR demo Demo A Release_3 01 Applications _ Sundance SDR1 SMT8036E_SDRDemo There are few differences be
22. ask More details in this regard in Chapters 3 and 4 It should be considered as the main Getting Started demo for the DVIP Version2 test_SMT8039 it contains an example targeting the SMI8039 system It illustrates how to create a DSP application using the SMT6040 and a default FPGA firmware without Diamond It is a simple example and is not optimised so performance is low test SMT362 this demo demonstrates the behaviour of the SMT362 DSP board when using only one or both DSPs 4 7 MIMO LTE MIMODemo It includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project that uses this task More details in this regard in Chapters 3 and 4 test SMT362 this demo demonstrates the behaviour of the SMT362 DSP board when using only one or both DSPs Version21test_SMT351T here are a demo to test the SMT351T alone testLeds mdl and two demos to be used as examples for the SMT351T SMT350 combination 4 8 WiMAX WiMAXDemo It includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project that uses this task More details in this regard in Chapters 3 and 4 test SMT362 this demo demonstrates the behaviour of the SMT362 DSP board when using only one or both DSPs Version21test_SMT351T here are a demo to test the SMT351T alone testLeds mdl and two demos to be used as examples for the SMT351T SMT350 combination 4 9 RadioGiga RadioGigaDemo It inclu
23. ate its folders Chapter 5 is dedicated only to the users of Version 2 1 which has now been replaced by the current Version 3 0 All demos and SMT6040 functionalities are accurately documented in the SMT6040 package This manual aims to give an overview of the SMT6040 useful Getting Started instructions for the main demo applications and a description of the main procedure to generate complex SMT6040 Simulink designs 2 How to use the SMT6040 This chapter describes how to benefit of the SMT6040 to design DSP FPGA applications from Simulink diagrams targeting Sundance hardware For this purpose the SMT6040 requires the following SW tools e Matlab 7 5 0 and Simulink 7 0 e Real Time Workshop version found in Matlab 7 5 0 e TI Code Composer Studio 3 3 e Xilinx ISE Foundation 10 1 e Xilinx System Generator 10 1 e Diamond 3 1 10 or Diamond 3 2 DSP amp FPGA licenses The SMT6040 allows using 3L Diamond the main development environment for Sundance hardware as the integrator of Simulink diagrams targeting DSP FPGA multi processor systems In fact the SMT6040 takes advantage of Sundance modularity and scalability to generate multi DSP multi FPGA applications from Simulink diagrams The same application can target different systems by few changes in the configuration Moreover the SMT6040 uses Diamond channels to implement the communication between processors So the user just needs to set up these virtual channels
24. blocks ADC2SHB and SHB2DAC ADE DSB BAC root Dd sb eg oc thm uns Pune RpEme VEN Pra TX am CPi aad EMT ME id Dela Tees Corse Ll Bt Par Ca pei The F Earatani Bata Tena Corsa Verbo ra emg inal Epurakas rie Feti Eris Typs Carrer mmn pia TT m L Danis Tapa Larrain gum CPI madg OE HO bats Haba Conner Go Lipas paigqhaiz Figure 44 SMT8036E demo Inside the ADC2SHB hierarchical block there are e The two ADC s configured to output 2 16 bits data integer 32768 to 432767 sampling at 50MHz e Two sub samplers at 10MHz as the DSP won t be able to process more than this rate e Bit concatenation to pack two 16 bits data into one 32 bits data e The FPGA2SHBA block e Some scopes to see internal data e Manual selectors that allow sending a synthetic sine wave instead of the ADC signal to the SHB gt DSP Inside the SHB2DAC hierarchical block there are e TheSHBB2FPGA block e Anup sampler at 50MHzto achieve the original rate e Bit de concatenation to unpack one 32 bits data into two 16 bits data e The dual DAC s sampling at 5OMHz e Some scopes to see internal data For compilation and execution please follow the usual procedure outlined in section 1 3 In particular after having clicked on the Overall Build button launch the following Matlab command Diamond ADC_DAC_DSP This instruction builds a Diamond appl
25. des a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project that uses this task More details in this regard in Chapters 3 and 4 test_SMT362 this demo demonstrates the behaviour of the SMT362 DSP board when using only one or both DSPs Version21test_SMT351T here are a demo to test the SMT351T alone testLeds mdl and two demos to be used as examples for the SMT351T SMT350 combination 4 10 SMT6040_ generic This folder contains a simple example for the development procedure described in Chapter 2 One folder SimulinkProject contains the SMT6040 diagram used to create a DSP task The other folder features a simple DSP FPGA Diamond example using this DSP task 4 11 Miscellanea In the generic folder there are some demos for data transfer in particular via comport or SHB Boards targeted are SMT370 and SMT368 These demos should be used as examples and as general reference for custom designs They are not meant to demonstrate full functionality of Sundance systems The obsolete folder contains a number of obsolete demos that could be taken as examples for custom designs However their use is not supported and we suggest focusing on the other demos 5 Version 2 5 1 Version 2 functionalities This section describes the main functionalities of the Version 2 from the basic operations to the most advanced features We recommend new customers using Version 3 0 to follow the
26. eed to double click the Digital HW Interface block under the main system then Compile to HW SW Analog finally Overall build This procedure will generate C files from the DSP diagrams and a bitstream from the FPGA diagram To build and run the demo on the HW the users need to call the SMT6040 MATLAB instruction Diamond test_SMT368_SMT362 This command builds a Diamond DSP task per each DSP processor it creates a Diamond application test_SMT368_SMT362 app and it runs it via Diamond Server Diamond Server automatically downloads and runs the DSP tasks and the FPGA bitstream on the hardware The user can verify the behaviour of the demo by checking the output messages printed on the screen and by connecting an oscilloscope to the SMT350 DAC channels 5 4 SDR demo SMT8036E No Sysgen Version 2 gt Demo Release_3 0 Applications Sundance SDR Version2 SDR_SMT8036E test_ SMT8036 ADC_DSP_DAC m dl Same requirements as for section 5 3 This demo targets the SMT8036E system and it is represented in Figure 44 where the top left diagram represents the top level complete system the diagram on the right is the SMT370 ADC DAC sub system and the diagram on the bottom is the root sub system SMT365E This application demonstrates data transfer between ADC DAC module and DSP module via SHB and data processing on the DSP Focusing particularly on the data acquisition the SMT370 sub system contains two main
27. ely to send data to T6040 root and to receive the processed data from it This is done during normal operation when the user selects option number 6 ofthe MIMO LTE menu Displays and printf statements in the main function will allow simple verification of the behaviour of the T6040_ root task designed in Simulink Sundance Multiprocessor Technology Limited RD OARS SMT6040 Sundance Simulink Toolbox Pe 6Juy2006 MyDSPapp SMT6040 diagram T6040 root tsk DSP task zr D rssed mas D Figure 27 logical connections between DSP tasks MIMO LTE demo 4 Time domain Channel 2 m x a Time domain Channel 1 a x 7 Channel 1 FFT f Channel 2 FFT Amplitude Amplitude Frequency Frequency Figure 28 output of the MIMO LTE demo The folder MIMODemo contains a Simulink example which is used to generate a Diamond DSP task with two inputs and one output and the Diamond SDR demo to which the T6040 root DSP task is added SMT6040 Sundance Simulink Toolbox Page 32 of 53 Last Edited 08 01 2010 15 42 The SMT6040 task is dedicated to process the incoming data from the main task and to output again to the main task the processing results The diagram generating the task is represented in Figure 26 and the processing results of the MIMO Diamond demo when calling the T6040 root task are pictured in Figure 28 In this picture it appears clear that the Time domain Channel 1 output is equ
28. em Generator supports only those types defined in the IEEE STD package in particular it does not support record types This means that you cannot use the convenient Diamond types described in Diamond User Guide to create a channel you must implement all of the signals explicitly The simplest approach is to name the signals in the same way as you would using record types but replacing with For example the data bus would be x chan in 0 Data The ports are implemented using Gateway In and Gateway Out elements Each input channel is specified as follows Gateway In Bus Size x chan in index data 64 bits x chan in index ready 1 bit x chan in index write 1 bit x chan in index validwords 2 bits Gateway Out Bus Size y chan in index ready 1 bit Each output channel is specified as follows Gateway In Bus Size y chan out index ready 1bit Gateway Out Bus Size x chan out index data 64 bits x chan out index ready 1 bit x chan out index write 1 bit x chan out index validwords 2 bits Task File Figure 5 channel configuration in System Generator Task File Application File index represents the channel number the only variable part of the name Both input and output are numbered from zero and the channel numbers must be continuous You must still provide a package file that declares the task s component this declaration must use a record type it is not l
29. emo that can be used as an example design for the SMT368 SMT350 combination test SMT362 these demos demonstrate the behaviour of the SMT362 DSP board when using only one or both DSPs Version2 OLDWMest SMT351T here are a demo to test the SMT35IT alone testLeds mdl and two demos to be used as examples for the SMT351T SMT350 combination Version2_OLD test_SMT350 this folder contains a number of designs that target the SMT350 board they should be utilised by advanced users Version2 OLDISDR_SMT8036E This folder is divided in a number of subfolders each containing demos targeting the whole system or the single boards that compose the SDR_SMT8036E kit SMT365E and SMT370 The SMT365 was featured in the SMT8036 and has now been replaced by the SMT365E so its demos are not relevant for new users Version2_OLD SDR_SMT8036E test_SMT8036 this folder contains a number of demos that target both the SMT8036 and SMT8036E systems All SMT8036E users should use the ADC DSP DAC mdl as a reference demo for this system and as a starting point for their projects Version2_OLD SDR_SMT8036E test_SMT370 this folder contains demos that test the leds and the DAQ functionalities of the SMT370 board Version2 OLD SDR_SMT8036E test_SMT365E this folder contains a demo testing the leds of the SMT365E board The other demos should only be used as examples for custom designs Version2 OLD SDR_SMT8036E test_SMT365 this folder contains
30. g is overwritten by Diamond with the frequency of the clock domain to which the task belongs e Clock Pin Location must be left unspecified Diamond connects the clock to the task according to the clock domain specified in the configuration file Server Driver Figure 6 System Generator configuration 2 2 6 Synthesizing the Task with XST Creating the task The VHDL files produced by System Generator may be synthesized with XST to produce a netlist PC i DSP Figure 7 netlist properties The netlist generated must not have any I O buffers since the task will be used in a higher level design In most cases it shouldn t implement any clock buffers since Diamond will implement them for you The configuration XST is shown in Figure 7 Add I O buffers must not be ticked all the other options can be set to values you choose 3 Main demo applications This chapter illustrates the main demos targeting some of Sundance most common systems Please notice that these demos can easily be changed to target other systems For a complete list of examples please see Chapter 4 More detailed instructions can be found in the SMT6040 package 3 1 SDR and SDR RF front end demos gt Demo ARelease 3 0VApplications Sundance SDRASDR 8146 8246 8096 gt Demo ARelease 3 0VApplications Sundance SDR SMT8036E_SDRDemo The demos targeting SMT8096 SMT8146 and SMT8246 are identical with the exception of the DSP type The SMT8246 demo is
31. iagram DVIP demo It is easy to understand the two simple processing steps applied by the SMT6040 task The result of the element by element subtraction of the input vectors is sent to output 1 Output 2 is a simple passthrough of input 2 However the second output of the Simulink task becomes the first input of the Diamond demo pal DSP task So the processing has two results the second line of the image is copied in place of the first line while the result of the subtraction replaces the second line passed to the Simulink task This process is executed on each of the three frames loaded by the DVL This is better explained by Figure 20 which shows on the left the original image and on the right the results of its binarization to black amp white and of the processing on the two lines in particular a white line replace a line in the top half of the image while a dark line is drawn in the bottom half of the video Figure 20 basic Video processing example on DVIP By using a similar procedure it is possible to add a DSP task created in Simulink to any of the DVL demos More complex applications also targeting multi DSPs can easily be designed thanks to the integration of SMT6040 and Diamond The folder DVIPDemo includes the Simulink project represented in Figure 19 that has been used to generate a DSP task named T6040 root tsk The DVIPDemo folder contains the DVL workspace project where this task has been
32. ication that is run via Diamond Server 5 5 Video demo Version 2 Demo Release 3 0M pplications Sundance Video Version2 test_ S MT8039 Same requirements as for section 5 3 prm mH ER 1 lil Ead ange prm web prs apa ETE Fama lato 25 Sal 3 J uim pw scam d Ekai Estres TZ mim Cima DL miie mm Ham D sl a Loma ii Figure 45 Video demo 2 DSP diagram This demo targets the DSP on the SMT339 and loads a default bitstream on the FPGA The DSP diagram is represented in Figure 45 and it applies a simple processing operation on the video input The Diamond DVL write block sends the processed image to the FPGA The default FPGA bitstream allows this image to be sent to the SMT339 output channel 6 Useful resources 6 1 Links SMT6040 Webpage htt p www sundance com web f iles product page asp S TRFilter S5MT6040 3L Diamond Introduction htt p www 3l com what is 3l diamond User Guide htt p www 3l com user guides 3l diamond f or sundance 6 2 Contacts Contact Persons Simone Boragno email simone boragno sundanceitalia 191 it Dr Fabio Ancona email fabio ancona sundanceitalia 191 it
33. ir iier uere 9 2 12 Diamond PO Pi is 10 2 2 Integrate a Simulink FPGA design into Diamond esse 12 2 2 1 Reguired signale 200 cu vod ve Ek dai anne 12 fA BD m n 12 2 2 9 DUIVIDG DIA ii ences ert pisc co AAA UC Hua AAA AA AAA 14 2 2 4 Chest the Tai iii sii 14 2 2 5 System Generator configuration esses eene eene nennen 14 2 2 6 Synthesizing the Task with XST Creating the task esses 15 3 Main demo applications ecee eee ee eee ee ee eee nenne nente sees estos esteso eon eue 16 31 SDR and SDR RF front end demos sisie csessscccetsseseaissesenonssnasdacsnnnonsentaddnsvoceosssobanenend 16 3 11 SMT8036E SDR OSTHD usi ae eR ai 20 32 VICO CO a 20 o A E Ra DU cdm eTe R Lee A pret ear Wines dtu etd 23 34 WiMAX deM ii A A AA AA A A dic 26 35 MIMO ETE dem a a aid 30 36 RadioGiga deM O ar dad 33 4 The SMT6040 Pack ic 36 4l S AAA iatadbeslnebinmesanaibstenseien 36 La SMT6040 DSP url odio 37 4 3 d UII NIC 37 4A SDR c Tc TEES 37 D MER UI occ densvesetoeetiass 39 4e DVP a te Dre a ore rer em rene Teor errr ene 39 47 MIMO TST ope P 40 48 WIMAX c 40 Z9 60 2 a a dau ue DM Dae err NTs ene abe mes pat NDS D Dd dem A eM Dua TE ME CUR 40 4 10 SMTOUAD elTe aiii id iia 40 411 i n 40 9 Version La ada 41 5 1 Version 2 function
34. l 2 3 5 MIMO LTE demo gt Demo Release 3 0 pplications Sundance MIMO LTE MIMODemo Same requirements as described in Chapter 2 This is the recommended demo for Special University Offer MIMO LTE users The diagram in Figure 25 represents the structure of the MIMO LTE demo F Analog i input 1 output Figure 25 MIMO LTE demo FPGA tasks in red DSP tasks in yellow The MIMO LTE demo is composed by two projects one for TX and one for RX each made of a number of DSP and FPGA tasks The main function is in the DSP task named Dual TX of the TX project This task sends receives control information and data to from the FPGA As described in paragraph 3 1 1 a Diamond DSP task e g named T6040 root tsk can be created by the SMT6040 This task can be added to the MIMO LTE Diamond project as explained in Chapter 3 This new task can communicate for example with the Dual TX DSP task For this purpose two input and one output ports have to be added to the Dual TX task p A ala Took Hab MT Nome E TEN Ee pc ee ee TUTTI aa 71 Peano e wem Daewared rwued U mm Jarne mew U j um Distar red i Figure 26 SMT6040 diagram for MIMO_ LTE demo These ports need to be connected to the input output ports of the T6040 root task as shown in Figure 27 In the main function in Dual TX c the functions chan out message and chan in message can be used respectiv
35. mo These ports need to be connected to the input output ports of the T6040 root task as shown in Figure 31 Sundance Multiprocessor Technology Limited SMT6040 Sundance Simulink Toolbox Form QCF32 Date 6 July 2006 My DSPapp Sh IT6040 diag am C T6040 1 oot tsk DSP task PP E m X Time damain Channel 1 4 Time domain Channel 2 Amplitude 156 188 58 188888 Frequency Amplitude 158 1368 B 190009 Frequency Figure 32 output of the RadioGiga demo SMT6040 Sundance Simulink Toolbox Page 35 of 53 Last Edited 08 01 2010 15 42 In the main function in rootc the functions chan out message and chan in message can be used respectively to send data to T6040 root and to receive the processed data from it Displays and printf statements in the main function will allow simple verification of the behaviour of the T6040_ root task designed in Simulink The folder RadioG igaDemo contains a Simulink example which is used to generate a Diamond DSP task with two inputs and one output and the Diamond RadioGiga demo to which the T6040 root DSP task is added The SMT6040 task is dedicated to process the incoming data from the main task and to output again to the main task the processing results The diagram generating the task is represented in Figure 30 and the processing results of the RadioGiga Diamond demo
36. nnel This procedure can be applied to any Diamond demo Of course the SMT6040 DSP task can be modified in Simulink as for the users processing algorithms 2 2 Integrate a Simulink FPGA design into Diamond System Generator is a popular design tool from Xilinx that allows designing Simulink diagrams targeting Xilinx FPGAs As previously pointed out it is possible to create a Diamond FPGA task from a System Generator project Therefore similarly to the DSP case described in the previous chapter it is possible to modify a Diamond project or a Diamond demo e g SDR or Video demos by adding FPGA tasks generated from a Simulink diagram This section describes how to use System Generator with Diamond to create and integrate a Diamond FPGA task These instructions are extracted from Diamond User Guide Please check it for more information htt p www 3l com user quides 3l diamond for sundance 2 2 1 Required signals System Generator will automatically add the following ports for you if there is at least one synchronous element in the task If your processing is purely asynchronous you can add a register on the validwords signal to force system generator to implement these ports e ck e ce e rst Port ce cir is not added by System Generator You should add an input gateway to your model called ce cir to ensure this signal is present on the interface on the core created by System Generator 2 2 2 Channels Unfortunately Syst
37. ooked at by System Generator You shouldn t specify any IOB Location Constraints when using System Generator 2 2 3 Driving pins A System Generator task can connect to the pins of the FPGA Gateways In and Out are used to implement the I O buffers The pin location the electric standard and any other constraint must be specified in a UCF file accompanying the task 2 2 4 Creatingthe task When you hit the Generate button System Generator compiles the Simulink model into a number of HDL files and netlists These files should be added to the FCD file of your task along with the Diamond package file that you must create yourself The following snippet shows an example of a System Generator task called addone cw We have pre synthesized the HDL files produced by System Generator to obtain the netlist addone cw ngc Note that we used the syntax edn to gather all the netlists produced by System Generator PACKAGE addone_cw_pkg vhd FILE netlist addone_cw ngc FILE netlisti edn 2 2 5 System Generator configuration System Generator is configured as in Figure 6 this is an example please change the configuration according to your HW e Compilation must be set to HDL netlist e Part must be set to the FPGA type you are targeting e Synthesis Tool must be set to XST e Hardware Description Language must be set to VHDL e FPGA Clock Period ns must be the frequency at which the task will be clocked This settin
38. possible to integrate a Simulink design into a Diamond project and also into the Diamond demos provided by Sundance Therefore users can combine their Simulink algorithms with C VHDL projects developed in Diamond e g they can add their tasks designed with the SMT6040 to Diamond SDR or Video demos which are provided by 3L The design process for a combined SMT6040 Diamond application requires only the following simple steps 1 Create a SMT6040 design that targets a DSP 2 Compile the SMT6040 project this will create the T6040 root tsk DSP task 3 Select the Diamond project of your interest and add the T6040 root tsk task to it 4 Connect the input output ports of the I6040 root tsk task and the ports of the Diamond task of your interest 5 Setupthe data transfer between the two tasks 6 Build and run the demo in Diamond IDE An example that explains this procedure is provided in the SMT6040 generic directory This folder contains the Diamond project based on the fpga examplel demo and the Simulink project represented in Figure 2 Please notice that this package targets the SMT362 DSP If you need to target another board you can select the correct module type by double clicking on the Digital HW Interface block under the DSP6040 root sub system Please check that you are targeting the proper DSP module also in Diamond 2 11 SMT6040 project The Simulink diagram is in this case performs three operations
39. pplication to target their hardware Eride Slack Parameters teat SATIS TESO S Dew ard clock sagrada apanata 2 Thair dign al alin bese Derduiy clack equam y Toe Choc prim RT P Exsh rn clack frag eara amne SET perimeters Dhi SELECTED SET parcenter DH SELECTED COMPLE TD MOTA MAMA O cowexr ro remos GENERATE SHOL SIMAO Target sedat bon Target toari Sundance HTE Taiga coria nien CFumsP Tera THES CEA 5h ee Pa mapper Cob pee Nel m Fon an Cn ee al Non und Fad tape P Set ai any pum Ce E E eet jura pin CD om com Figure 36 DSP hardware interface Other blocks generate two sequences of data e A Ramp on Diamond output channel 0 write which goes to node nodel as described in the top diagram e A Sine on Diamond output channel 1 write which goes to node nodel as described in the top diagram The remaining blocks receive data from e Diamond input channel 0 read which comes from the FPGA module as described in the top diagram data is a 2 dimensional vector formatted as shown in the Input Digital HW Parameters dialog box of the sim Diamond channel block Configuration can be changed as shown in Figure 37 e Diamond input channel 1 read which comes from node nodel as described in the top diagram process them and occasionally printf to the console Figure 37 Diamond channel hardware interface The second node node1 is shown in Figure 38 P DR pe Jen
40. r types which can be configured from a scroll down menu Pm Dk cem limon foe Top rw Dok Lac bo FULL SYSTEM SMT362 DSP A Figure 43 SDR demo SMT6040 diagram The demo described in the paragraph 1 2 targets the SMT3624SMT351T SMT350 system and is therefore very similar Figure 43 represents the SMT6040 Simulink diagram test SMT368 SMT362 mdl top left and the three Simulink subsystems one per each processor The full system also depicts the connections between the processors the input sine wave blocks and the scopes that are used during simulation to verify the behaviour of the system There are two DSP sub systems one per each DSP of the SMT362 and one sub system dedicated to the SMT368 SMT350 combination Each sub system uses Diamond channel blocks to communicate with the other processors The DSPs are dedicated to signal processing while the FPGA ADC DAC combination acquires and samples data from the ADC and send data to the DAC The demo can be simulated in Simulink The scopes can be used to view the signals and verify the behaviour of the demo which will be similar to the one represented in Chapter 1 in Figure 42 Each demo has a corresponding list of connections described in a wir file The test SMT368 SMT362 wir file describes for example the necessary physical links between processors in this case comports and the required connections between Diamond channels To compile the demo the users n
41. root tsk The VideoDemo folder contains the DVL workspace where this task has been inserted into Diamond Video Demo demo2 3 3 DVIP demo gt Demo Release 3 0Mpplications Sundance DVIP DVIP Demo This demo requires the use of Diamond Video Library DVL One of the sample applications included in the DVL is integrated with the SMT6040 by following the procedures previously described The resulting structure of the demo is represented in Figure 17 In particular this basic demo performs some DSP operations on two lines of the image to show how it is possible to use the SMT6040 to process the video acquired by a camera The DVL deals with data acquisition Once a video frame has been captured two lines of the image are passed to a Simulink task as outlined in Figure 18 e Gremis diagram Tot ront tsk DSF task en a T on ae a I a i PTEE E LL 2 i amp 4 Video SMT338 ouput OSP a ou is 4 4 ii SMT338 i E i FPGA J Lo h SMT362 Ha i ai z EPGA 1 ae UT y Figure 17 DVIP demo FPGA tasks in red DSP tasks in yellow The whole Simulink diagram top view and detail of the root subsystem is pictured in Figure 19 Figure 18 logical connections between DSP tasks DVIP demo A aaa Deng i ce rer ac fee pora Am RA RS Pla Edt we Format Toca Hen ee aa ca ss moi fir ume Se hd RE n_n RTIIR Figure 19 Simulink d
42. s E Howe bo Ada LE hits Mew Current Directory 04 CLEEF Es SUR j SMITE generic j Video jr VA Figure 33 the SMT6040 Package 4 2 SMT6040_ DSP These demos demonstrate the behaviour of multi DSP application targeting DSP boards like SMT362 SMT395Q SMT363 SMT374 SMT365 SMT365E SMT395VP30 4 3 SMT6040 FPGA This folder contains a number of generic demos that can be used as examples for FPGA programming via Simulink these examples are not supported anymore 4 4 SDR Several demos are divided in a number of sub folders SDR 8146 8246 8096 it includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond workspace SDR that uses this task More details in this regard in Chapters 3 and 4 The Diamond workspace includes different projects targeting the following possible systems SMT8246 SMT350 version SMT8246 SMT950 version SMT8146 SMT350 version SMT8146 SMT950 version SMT8246 SMT350 version SMT349 SMT8246 SMT950 version SMT349 SMT8146 SMT350 version SMT349 SMT8146 SMT950 version SMT349 SMT8096 These demos are recommended as starting points for customers developments on these systems SMT8036E_ SDRDemo it includes a SimulinkProject that creates a DSP task from a SMT6040 diagram and a Diamond project that uses this task More details in this regard in Chapters 3 and 4 This demo is recommended as starting point for
43. s the following SW tools Matlab 7 5 0 and Simulink 7 0 Real Time Workshop version found in Matlab 7 5 0 TI Code Composer Studio 3 3 Xilinx ISE Foundation 10 1 Diamond 3 1 10 DSP license This section generally illustrates the following demos Demo System test SMT368_SMT362 mdl SMT8246 SMT362 SMT368 SMT350 test SMT351TSX95_ SMT395VP30 mdl SMT395 SMT351TSX95 SMT350 test SMT351TSX50_ SMT395VP30 mdl SMT395 SMT351TSX50 SMT350 test SMT351TSX95_SMT362 mdl SMT3624SMT351TSX9545MT350 test SMI351ISX50 SMT362 mdl SMT362 SMT351TSX50 SMT350 SMT6040 Sundance Simulink Toolbox Page 48 of 53 Last Edited 08 01 2010 15 42 Comport connections required by this demo can be implemented on a SMT3100 carrier board As the SMT148 FX stand alone carrier implements comports via firmware SMT148 FX users should match comport connections used in the demo with the ones implemented by their firmware Please notice also that users with Diamond DSP single processor license need to modify the SMT362 demos by moving the design onto one SMT362 DSP only to be able to run it For this reason University customers with a Diamond 1xDSP license are recommended to use SDR demo 3 paragraph 3 1 as starting point for their developments We now focus in particular on the test SMT368_SMT362 mdl demo but it is easy to verify that these explanations apply to the other demos too apart from the different processo
44. sen fuma xx pem Du he wet ue sl pm Pummi siad AT mm haraur mat ATTE J Figure 38 node1 DSP sub system It receives two sequences of data from Diamond channel 0 read and Diamond channel 1 read respectively which receive data from node root as shown in the top diagram These are summed up together and the result is e Printed sim_ printf to the console e Sent to the Diamond channel 0 write which is connected to the node root as shown in the top diagram e Muxed into a 2 elements vector and sent via Diamond channel 1 write to the FPGA module as shown in the top diagram The sim_ digHwInterface is exactly as in node root as this is the second DSP of the same SMT362 board The third node SMT350 implements the Simulink diagram that programs the FPGA ADC DAC combination in this example SMT351T SMT350 board The SMT350 diagram is shown in Figure 39 This demonstrates how the SMT6040 can be used to program FPGA modules and also to configure the SMT350 DAQ board tesi SIET3STTEXSO SRTIAI MTISO Fle Edit view Gmin Format Took Hen Dou Pes do fl ume Am Bum Tasa s ra I PEA CE LOS YT z ELOCH EN TEA Mad Bu Le PPC ipm Sa pr pija AT feet Eig A at dd A par s Lepr Cai iLE PI BS miu mg iiim e dba Bud LEDI ire dpl Bia PO T cam d i ps Lesser qup tee iw dua B TERR LBG Tir nl BE sasp si EMIJE dab T3 Am Fecd pa Cristi RATISIT P vi mem pru maii de A Bai umi acd
45. t 61 440 000 samples s as required by the DAC Generate a 61 440 000 8 Hz 7 68 MHz sinewave Sum input signals to the sinewave Send both signals to the DAC which is configured as in Figure 41 to operate as a normal two independent channels DAC Output signals via the AC coupling to the coax connectors During simulation the analog outputs are visible on the dual channel scope present in the root model The ADC part does the following o Sample the two input analog channels at 61 440 000 samples s double click on the ADCs to see sample frequency and other parameters During simulations data come from two signal generators present in the root model o Sub sample both channels with period STime a variable from the MATLAB workspace set by the sim_ setParam block in the root model o Muxthem together into a 2 dimensional vector sim mux2 o Sendthevectorto the root via a comport sim FPGA2comport block 5 2 Simulate and run an application The SMT6040 application can be first verified during Simulation Data printed on the screen and the graphs displayed by the scopes Figure 42 can be used both for debugging and to verify the algorithm results Compilation is very simple users need to double click on the sim digHwlInterface in the top diagram then click on COMPILE TO HW SW ANALOG Clicking on OVERALL BUILD shall trigger compilation which will in the sequence e Split the whole system into subsystems one for each sim
46. tween the SMT8246 SDR demo described in Section 3 1 and the SMT8036E demo The structure of the SMT8036E demo is highlighted in Al t m mmmmmms of iso lay Display D e TETAS Figure 12 SMT8036E SDR demo FPGA tasks in red DSP tasks in blue We recommend customers to check the Diamond project for further details 3 2 Video demo gt Demo Release 3 0 pplications Sundance Video VideoDemo This demo targets the Video kit and the VisionMax kit and requires the use of Diamond Video Library DVL One of the sample applications included in the DVL is integrated with the SMT6040 by following the procedures previously described The resulting structure of the demo is represented in Figure 13 Tne glee diagram T il rocttsk DEP task a 522s a r 1 d A A a DSP Tam m l Y F Fr f i Video input 4 mom aum a ge a A Figure 13 Video demo FPGA tasks in red DSP tasks in yellow In particular this basic demo performs some DSP operations on two lines of the image to show how it is possible to use the SMT6040 to process the video acquired by a camera The DVL deals with data acquisition Once a video frame has been captured two lines of the image are passed to a Simulink task as outlined in Figure 14 pem tee _ EE pa Ha bd Ve Gnien Formar Took Ha Dg Bi es F O S F s mei Paxman Bey Se bane mre dip Hairi iare
47. when calling the T6040 root task are pictured in Figure 32 In this picture it appears clear that the Time domain Channel 1 output is equal to the sum of two signals identical to the one displayed as Time domain Channel 2 4 The SMT6040 package 4 1 Overview The SMT6040 is provided with instructions that guide the user through the software installation Once the toolbox is correctly installed two directories will be loaded in MATLAB Sundance and Miscellaneous demos In Miscellaneous demos there are many general purpose Simulink diagrams that do not specifically target the latest Sundance hardware but they could be used as examples for custom designs However we invite customers to focus on the folder Sundance which is specifically dedicated to Sundance systems and provides many working applications useful demos and examples accurate instructions By double clicking on Sundance a number of folders each containing a group of demos targeting Sundance boards will be visualized as in Figure 33 The following paragraphs list all the demos The main demo applications for Sundance SDR Video DVIP MIMO WiMAX RadioGiga systems are more accurately described in Chapter 4 These examples are very useful as starting points They can then be changed by the user both to implement new algorithms and to target different systems MATLAB 7 5 0 KZDO7b Fie Edit Debug Detibuted Desktop Ue 59 E m Shertout
48. zzsum amp from DAn El add H chan in message sizeof float amp temp cut focal an 1 j 3p m printf After 5Mr5l4 processing sum td outridin sun 5 4 driver E m o ooo Ej dire F H Kilu E r m H770 EP aver samumo 3 Diamond FPGA example 1 SUM l x B Te0e0_pooth l amp e rere SHT6040 ing sum Q inia3 ina z E processing sums inls3 inzez outs ETE rootEk euraid task d Connection fter 35eT 040 processing sum 5 out 3 E i 5 LB sgh oO DJ IS Figure 4 data transfer By right clicking on I 6040 root clicking on Add Existing Files and browsing to T6040 root tsk it is possible to add the tsk file to the new task which therefore will behave as the SMT6040 diagram To let the T6040 root task communicate with the driver task the driver task needs to have two additional output ports named to6040 0 and to6040 1 respectively and two additional input ports named from6040 0 and from6040 1 respectively Connections are created as in Figure 3 Finally the data transfer between the two DSP tasks can be set up thanks to the functions chan out message and chan in message as in Figure 4 The printed output of the demo demonstrates the behaviour of the task created by the SMT6040 the sum of the two inputs is calculated while the second input is passed through to the second output cha
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