SH67P33
Contents
1. 3 0V Built in RC fosc vs Temperature 4 09 4 07 4 05 4 03 401 ge 3 99 3 97 3 95 3 93 45 30 15 0 15 30 45 60 75 Temperature Graph 1 Built in RC fosc vs Temperature VDD 3 0V 2 0V Built in RC fosc vs Temperature 4 03 4 01 3 99 3 97 gt 365 3 93 3 91 3 89 45 30 15 0 15 30 45 60 75 Temperature Graph 2 Built in fosc vs Temperature VDD 2 0V 3 6V Built in RC fosc vs Temperature 4 10 4 08 4 06 4 04 9 N 4 02 4 00 3 98 3 96 3 94 3 92 45 30 15 0 15 30 45 60 75 Temperature C Graph 3 Built in RC fosc vs Temperature VDD 3 6V SH67P33 SH67P33 In System Programming Notice for OTP The In System Programming technology is valid for OTP chip The Programming Interface of the OTP chip must be set on the user s application PCB and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip Of course it s accessible bonding OTP chip only first and then programming code and finally assembling other components Since the programming timing of Programming Interface is very sensitive therefore four jumpers are needed VDD VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram Application PCB OTP Chip2. jintemuptrequestfags When IEx is set to 1 and the interrupt request is generated IRQx is 1 the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources When an interrupt occurs the PC and CY flag will be saved into stack memory and jump to interrupt service vector address After the interrupt occurs all interrupt enable flags IEx are reset to 0 automatically thus when IRQx is 1 and IEx is setto 1 again the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources Interrupt Servicing Sequence Diagram 1 2 3 4 5 Inst cycle Instruction Instruction Instruction Execution Execution Execution N 11 12 Vector Generated Fetch Vector address Interrupt Generated Interrupt Accepted Stacking Reset IE X Start at vector address During the SH6610C CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences If the interrupt request is ready and the instruction of execution N is IE enable then the interrupt will start immediately after the next two instruction executions However if instruction 11 or instruction I2 disables the interrupt request or enable flag then the interrupt service will be terminated 9 HALT and STOP Mode After the
3. GND 20 Bonding Diagram PORTE 0 OSCI PORTE 1 OSCO PORTD 2 PORTC 0 PORTC 1 PORTC 2 SH67P33 Q OdZZOov 02070 1630 Substrate connects to GND Pad Location 6 2 24500 32550 8 Poroa 7450 55250 9 PoRrcz 73400 70750 REM Veo 21 PORTA 3 PORTA 2 PORTA 1 PORTA 0 PORTB 3 PORTB 2 15 70um unit 733 00 700 50 618 00 700 50 SH67P33 SH67P33 Ordering Information SH67P33H Chip Form SH67P33X 20L TSSOP SH67P33 20L DIP SH67P33M 20L SOP 22 SH67P33 Package Information TSSOP 20L Outline Dimensions unit inches mm Dimensions in mm Dimensions in inch Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlaid protrusions of 0 25 mm maximum per side are not included 23 SH67P33 DIP 20L Outline Dimensions unit inches mm D Plane Seating Plane a 0 002 0 05 _ 0 002 0 05 0 002 05 e E 0250 Typ 0 262 Max 635Typ 665 zem 1 ewe 08
4. 16 PACR 0 PORTA input output control 17 PBCR O PORTB input output control 18 PCCR 0 PORTC input output control 19 PDCR2 PDCR PORTD input output control PECRO PORTE input output control control register PACR X PBCR X PCCR X X 0 1 2 3 PDCR 2 PDCR 1 PECR 1 PECR O 1 Set I O as an output buffer 0 Set as an input buffer power on initial Controlling the pull low MOS These ports contain pull low MOS controlled by the program PPULL register controls On Off of all pull low MOS simultaneously Pull low MOS is controlled by the port data registers PA PB PC PD and PE of each port also Thus the pull low MOS can be turned on and off individually Port Function Control PMOD is below mes mz mu m RW Romane PPULL Port Pull low MOS enables control 0 Disable PORT MOS power on initialization 1 Enable PORT pull low MOS SH67P33 Port Interrupt The PORTB PORTC and PORTD can be used as port interrupt sources Since PORT is a bit programmable I O therefore only the input port can generate an external interrupt Any one of PORTB and PORTC input pins from GND to will generate an interrupt request Default when opt pint is HIGH PORTB and PORTD as the port interrupt source Thus further rising edge transitions can not be able to make interrupt request until all of the pins return to GND The following is
5. 4 SINO WEALIH Features SH6610C based single chip 4 bit micro controller W ROM 1K X 16 bits OTP ROM B RAM 48 X4 bits RAM Data Memory Operation voltage 1 8V 3 6V Typical 3 0V 16 CMOS bi directional I O pins and 1 COMS input pin E 4 level subroutine nesting including interrupts One 8 bit auto re loadable timer counter B Warm up timer for power on reset W Powerful interrupt sources Internal interrupt TimerO External interrupts rising edge PORTB amp PORTC or PORTB PORTC amp PORTD Code Option General Description SH67P33 OTP 4 bit Micro controller E Remote control programmable carrier synthesizer Oscillator Code Option External Ceramic Resonator Crystal Oscillator 400kHz 4MHz Built in RC Oscillator 4MHz typical W Instruction cycle time 4 455kHz 8 79hs for 455kHz OSC clock 4 4MHz 1us for AMHz OSC clock W Two low power operation modes HALT and STOP E Built in watchdog timer W OTP type Code protection W 20 pin DIP TSSOP SOP package SH67P33 is dedicated to infrared remote control transmitter applications This chip integrates the SH6610C 4 bit CPU core with RAM program ROM one 8 bit timer and programmable input output pins and carrier synthesizer When in standby function system will stop oscillator and remain low power dissipation Pin Configuration GND PORTD 0 PORTD 1 PORTE 0 OSCI PORTE 1 OSCO PORTD 2 PORTC 0 PORTC 1 PORTC 2 PORTC 3 2
6. Ems Crystal OSCO OSCO 2 Internal oscillator 4MHz PORTE 0 OSCI and PORTE 1 OSCO are used as ports PORTE 0 PORTE 1 5 5 1 Configuration and Operation TimerO consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH The counter and load register both have low order digits and high order digits Writing data into the timer load register TLOL TLOH can initialize the timer counter Load register programming Write the low order digit first and then the high order digit The timer counter is automatically loaded with the contents of the load register when the high order digit is written or counter counts overflow from FF to 00 Timer Load Register Since register H controls the physical READ WRITE operations follow the following rules Write Operation Low nibble first High nibble to update the counter 5 2 TimerO Interrupt SH67P33 Read Operation High nibble first Followed by Low nibble Load Reg L Load Reg H amp bittimer counter bit timer counter Fh Reg EN L Figure 1 Timer Load register Configure The timer overflow will generate an internal interrupt request when the counter counts overflow from FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will start This can also be used to wake CPU from HALT mode 5 3 Timer0 Mode Register The timer can be p
7. VPP VDD SCK OTP Writer SDA GND The recommended steps are as following 1 The jumpers are open to separate the programming pins from the application circuit before programming the chip 2 Connect the programming interface with OTP writer and begin programming 3 Disconnect OTP writer and short these jumpers when programming is complete For more detail information please refer to the OTP writer user manual 19 e SH67P33 Application Circuit for reference only AP1 Remote Control 48 Keys 1 Oscillator Ceramic 455kHz PORTEO 1 SHARED TO OSCI amp OSCO 2 PORTA PORTD 1 PORTD 2 1 0 Buffers 3 PORTB C and PORTD 0 Input Buffers 4 R1 0 is possible but the REM specification is revised to reduce power consumption 5 Since PORTD 0 is input only PORTB or PORTC be scanned out to detect PORTD 0 option PORTD 0 PORTC 3 REM SH67P33 PORTB 2 PORTB 1 PORTB 0 PORTA 3 PORTA 2 PORTA 1 PORTE 0 OSC1 PORTA 0 1 05 Simplified Custom Code Selection only one Switch can be closed AP2 Remote Control 81 Keys 1 Oscillator Built in RC 2 PORTA PORTD 1 PORTD 2 PORTE I O Buffers 3 PORTB C and PORTD 0 Input Buffers VDD PORTD 2 PORTD 1 PORTD 0 PORTC 3 PORTC 2 PORTC 1 REM 0 PORTB 3 SH67P33 PORTB 2 PORTB 1 PORTB 0 PORTA 3 PORTA 2 PORTE 1 OSCO PORTA 1 PORTE 0 OSCI
8. 3 4 5 6 7 8 9 VDD REM PORTA 3 PORTA 2 PORTA 1 PORTA 0 PORTB 3 PORTB 2 PORTB 1 PORTB 0 dZ9HS V2 0 Block Diagram OSCI OSCO WATCHDOG PRESCALER 8 BIT TIMER CTL REG UP COUNTER ROM TIMER 1K X 16BIT INTERRUPT DATA RAM 48 X 4 BIT PORTA 4 BITS PORTB 4 BITS 1 PORTC 4 BITS PORTD 3 BITS 2 BITS CONTROL SYNTHESIZER SH67P33 PORTA 0 3 PORTB 0 3 PORTC 0 3 PORTD 0 2 PORTE 0 1 REM SH67P33 Pin Descriptions uo Bes 10 r PORTE 0 lt Te Bit programmable pin shared with oscillator input pin connected to ceramic resonator or crystal oscillator 5 PORTE 1 OSCO Bit programmable shared with oscillator output pin connected to ceramic resonator or crystal oscillator s 15 18 0 31 Bit programmable I O pins 11 14 PORTB 0 3 Bit programmable I O pins Vector Interrupt Active rising edge VDD m permoro 55 omms programmino high votage Power supe TN e e PORTA 0 Programming Data pin Functional Description 1 CPU The CPU contains the following functional blocks Program Counter Arithmetic Logic Unit ALU Carry Flag Accumulator Table Branch Register Data Pointer
9. INX DPH DPM and DPL and Stacks 1 1 PC The PC is used for ROM addressing consisting of 12 bits Page Register PC11 and Ripple Carry Counter PC10 PC9 PC8 PC7 PC6 PC5 PCA PC3 PC2 PC1 PCO The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP can be set at 1 bit page register for higher than 2K The program counter cans only 4K program ROM address Refer to the ROM description 1 2 ALU and CY The ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustments for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decisions BA0 BA1 BA2 BA3 BAZ BNZ BC BNC Logic Shift SHR The Carry Flag CY holds the ALU overflow that the arithmetic operation generates During an interrupt service or CALL instruction the carry flag is pushed into the stack and recovered from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator AC The accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data is transferred between the accumulator and system register or data memory can be performed 2 ROM SH67P33 1 4 Table Branch Register TBR Table Data can be stored in program memory and can be referenced by using Table Branc
10. LVR Disable 15 is din Else LVR Enable Power on initial 0000 12 Watchdog Timer Watchdog timer is a 16 bit down count counter and its clock source is internal RC oscillator The watchdog timer automatically generates a device reset when it overflows To prevent it timing out and generating a device RESET condition users should write bit3 of system register 14 as 1 before timing out The WDT has a time out period of approx 16ms WDT bit3 is watchdog timer overflow flag System Register 14 WDT The WDT bit is cleared only if the Watchdog Timer time out occurred both in normal operation mode and in the HALT mode The Watchdog Timer is cleared when the device wakes up from the STOP mode regardless of the source of wake up 13 Reset Function The SH67P33 has the power on reset circuit though it does not have RESET pin System reset is performed automatically at power on and software starts program from address 000 In order to make the built in power on reset circuit operate efficiently set the voltage rising time until VDD OV to 2 2V is obtained at power on 1ms or less VDD Power on reset circuit output voltage Reset state Internal reset signal Reset released Power on 13 SH67P33 14 Initial State There are 3 types of system resets 1 Power on reset 2 Low Voltage Reset 3 Watchdog reset Undefined Unchanged Unchanged Undefined Unchanged Unchanged Undefined Unchanged
11. Unchanged 0000 0000 Unchanged Carrier low level timer load data register mw 9 15 Code Option 15 1 Oscillator Select 0 4MHz built in RC oscillator default 1 External Ceramic resonator Crystal Oscillator 400kHz 4AMHz PORTE should be set as output high before enabling PPULL 1 at the program initialization 15 2 Port Interrupt Source Select 0 PORTB PORTC interrupt default 1 PORTB PORTC PORTD interrupt 14 SH67P33 Instruction Set All instructions are one cycle and one word instructions The characteristics are memory oriented operation Arithmetic and Logical Instructions Accumulator Type Meemonc Instruction Code Function Flag Change xee 00100 08bb wxxroox AC we EORM X 8 00100 1Bbb AGNKEM AC FOR xes 00101 AC wm Omw xee 00101 Acme mjas AND xee 00110 00bb x000 Aac Anom 8 0 gt 3 AC 0 11110 0000 000 0000 AC shift right one bit CY Immediate Type Meemonc Instruction Code Function Flag Change Xi AGM Mer omw xi AGM ANDI oo Decimal Adjust Mnemonic Instruction Code Function Flag Change 11001 0110 AC Mx lt Decimal adjust for add DAS X 11001 1010 xxxx AC Mx lt Decimal adjust for sub Transfer Instru
12. 05 s e Notes 1 The maximum value of dimension D includes end flash 2 Dimension E4 does not include resin fins 3 Dimension S includes end flash 24 2 SH67P33 SOP 20L W B Outline Dimensions unit inches mm 0 004 Min 0 10 Min 0 092 0 005 2 33 0 13 0 016 0 004 0 41 0 10 0 002 0 05 0 010 0 004 0 25 0 10 0 002 0 05 5 0 106 Max 2 69 Max 0 032 0 008 0 81 0 20 0 055 0 008 1 40 0 20 0 042 1 07 0 004 0 10 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e is for PC Board surface mount pad pitch Designer reference only 4 Dimension S includes end flash 25 SH67P33 Data Sheet Revision History Tu 1 Add Reset Function Description Page 13 2 0 2 Add Power on reset circuit valid power source rising time specification Page 17 3 Simplify Ordering Information Page 22 26
13. OP Current MEHR ALL output pins unload LVR on IREML REM sink current m 0 3V Input Low Voltage X 0 2 ports Schmitt Trigger input VIH Input High Voltage VDDX 0 8 v I O ports Schmitt Trigger input liL Input Leakage Current 02 02 ports GND High level Input Current ESRB 10 pull low Vio excluding High level Input Current 6 0 input with pull low VDD Output High Voltage IVn 07 v ports loH 1mA Output Low Voltage 6 0 6 V VO ports oL 5mA o jebete power source rising time LVR Circuitry TA 10 C to 70 C Symbol Parameter we Wax AC Electrical Characteristics VDD 3 0V GND OV TA 25 C built in RC oscillator unless otherwise specified Symbol Parameter __ ne Mex Unt tosc Oscillator Start time 20 ms Ceramic Resonator 455kHz fosc1 Frequency Variation 2 0 to 3 6V TA 5 C to 45 C fosc2 Frequency Variation 2 0 to 3 6V 10 to 45 C fosc3 Frequency Variation 400 2 0 to 3 6V TA 45 to 70 17 Oscillator Characteristics Graphs for reference only Built in RC oscillator Frequency vs Operating Ambient Temperature
14. and it has two reload data register The counter and load registers both have low order digits and high order digits Writing data into the timer load registers 1B 1C 1D 1E can initialize the counter After system reset the counter is automatically loaded with the contents of high level timer load data register 1E 1D and output high level at the same time Following when counter counts overflow from FF to 00 the counter is automatically loaded with the contents of low level timer load data register 1C 1B and output low level at the same time When counter counts overflow again from FF to 00 again the counter will be loaded with the contents of high level timer load data register again The above sequences make up a complete loop So the carrier synthesizer can output continuous carrier wave of certain duty and certain period Load register programming User can modify low level timer load data register 1B 1C to change the width of the low level User can also modify high level timer load data register 1D 1E to change the width of high level In the way the carrier synthesizer can output carrier wave of different duty and different period Carrier load data register address Bir CFL3 CFL2 CFLO Carrier low level timer load data register low nibble CFL7 CFL6 cFL5 CFL4 Carrier low level timer load data register high nibble 1D CFH3 CFH2 CFH1 CFHO Carrier high leve
15. ble Branch Register INX3 INX2 INX4 INX 0 Pseudo index register 10 DPL3 DPL2 DPL1 DPLO Data pointer for INX low nibble IW IW W 1 DPM2 DPM 1 DPMO Data pointer for INX middle nibble 12 DPH2 Data pointer for INX high nibble Bit2 0 Carrier count source pre divider 13 FEMME Port Pull low MOS Control R Watchdog timer WDT Write 1 to reset WDT timer LVR Enable Control LVR3 0 LVR3 LVR2 LVR1 LVRO R W 1010 LVR Disable Else LVR Enable Power on initial 0000 16 PACR3 2 PACR 1 PACR 0 PORTA input output control 17 PBCR3 PBCR2 PBCR 1 PBCR 0 PORTB input output control 18 PCCR3 PCCR2 PCCR 1 PCCR 0 PORTC input output control 2 PDcR1 RW PORTDipulupuconto 1A PECR 1 PECR 0 R W PORTE input output control 31 1 ee SH67P33 4 System Clock and Oscillator The System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals 4 1 Instruction Cycle Time 1 4 455kHz 8 79 6 for 455kHz system clock 2 4 AMHz 1us for AMHz system clock 4 2 Oscillator 1 Ceramic resonator Crystal Oscillator 400kHz 4MHz PORTE should be set as output high before enabling pull low PPULL 1 at the program initialization OSCI OSCI
16. ction Mnemonic __ instruction Gode Function Fiag Change Mx STA X B 00111 1bbb wx Mx ACT LDI 01111 AC Mx lt BEEN 15 SH67P33 Control Instruction ST CY PC 1 X Notinclude p NENNEN RTNW L 11010 000h hhh Ill TBR lt hhhh AC ll TJMP PC PC11 PC8 TBR AC Where Te e 16 SH67P33 Electrical Characteristics Absolute Maximum Ratings Comments DC Supply Voltage 0 3V to 6 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input Voltage 0 3V to VDD 0 3V These are stress ratings only Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is Operating Ambient Temperature 10 C to 70 C ene not implied or intended Exposure to the absolute maximum 5 rating conditions for extended periods may affect device Storage Temperature 55 Cto 125 reliability DC Electrical Characteristics VDD 3 0V GND OV TA 10 to 70 C fosc 4MHz unless otherwise specified Symbol Parameter win ue wax unk cm 5 output pins unload E Execute instruction 1581 HALT Current 20 pa CPU in HALT mode ALL output pins unload OSC STOP ST
17. execution of HALT instruction SH67P33 will enter HALT mode In HALT mode the CPU will stop operating however the peripheral circuit timer will keep operating After the execution of STOP instruction SH67P33 will enter STOP mode In STOP mode the entire chip including oscillator will stop operating In HALT mode SH67P33 can be woken up if an interrupt occurs In STOP mode SH67P33 be woken up if a port interrupt occurs 10 Warm up Timer The SH67P33 has a built in oscillator warm up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the following conditions Power on reset Wake up from STOP mode Low voltage reset The warm up counter pre scaler is divided by 213 8192 1 When SH67P33 operates in 455kHz frequency the warm up time interval is about 18 ms 2 When SH67P33 operates in 4MHz frequency the warm up time interval is about 2 ms Interrupt Nesting 12 SH67P33 11 Low Voltage Reset LVR The LVR function monitors the supply voltage and applies an internal reset in the micro controller at battery replacement If the applied circuit satisfies the following conditions the LVR can be incorporated by the software control The LVR circuit has the following functions Generates an internal reset signal when lt VLvR typ 1 5V System Register 15 Address Bit Bito RW 7 Remaks LVR Enable Control LVR3 0 1010
18. h TJMP and Return Constant RTNW instructions The TBR and AC are placed by an offset address in program ROM TJMP instruction branch into address PC11 PC8 X 2 TBR AC The address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bitO into AC 1 5 Data Pointer The Data Pointer can indirectly address data memory Pointer address is located in register DPH 3 bits DPM 3 bits and DPL 4 bits The addressing range can have 3FFH locations Pseudo index address is used to read or write Data memory then RAM address bit9 comes from DPH DPM and DPL 1 6 Stack The stack is a group of registers used to save the contents of CY amp PC 11 0 sequentially with each subroutine call or interrupt The MSB is saved for CY and itis organized into 13 bits X 4 levels The stack is operated on a first in last out basis and returned sequentially to the PC with the return instructions RTNI RTNW Note The stack nesting includes both subroutine calls and interrupts requests The maximum allowed for subroutine calls and interrupts are 4 levels If the number of calls and interrupt requests exceeds 4 then the bottom of stack will be shifted out that program execution may enter an abnormal state The ROM can address 1K X 16 bits of program area from 000 to 3FF 2 1 Vector Address Area 000 to 004 The program is sequentially executed There i
19. l timer load data register low nibble 1E 7 CFH6 5 CFH4 Carrier high level timer load data register high nibble 10 M SH67P33 Low level timer load data register SYSTEM CLOCK divider High level timer load data register CARRIER SYNTHESIZER Figure 4 Remote Control Functional Block Diagram COUNTER SOURCE RESET SIGNAL REMO COUNTER OVERFLOW A 1 2 3 2 3 2 1 2 3 2 3 2 3 1 load high level data register 2 High level counter overflow and load lowlevel data register 3 Low level counter overflow and load high level data register MODIFY HIGH amp LOW DATA REGISTER CARRIER OUTPUT i OUTPUT OUTPUT HIGH HIGH 255 LEVEL OUTPUT LEVEL OUTPUT n1 clock LOW LOW LEVEL LEVEL menal 255 4 n1Dec 1E 1D Hex 2 clock interval n2Dec 1C 1B Hex J carrier i period 4 Figure 5 Synthesize Wave 11 SH67P33 8 Interrupt Two interrupt sources are available on SH67P33 TimerO overflow interrupt Port s rising edge detection interrupt PBC Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 through 01 of the system register They can be accessed or tested by the program These flags are cleared to 0 at initialization by chip reset amp m 01 IRQTO Interrupt request flags
20. rogrammed in several different pre scaler ratios by setting Timer Mode Register TMO The 8 bit counter counts pre scaler overflow output pulses The TIMER mode registers TMO are 3 bit registers used for timer control as shown in Table 1 These mode registers select the input pulse sources into the timer Table 1 Timer0 Mode Register 0 2 0 1 0 0 Pre scaler Divide Ratio Clock Source gt S SH67P33 6 PORT The SH67P33 provides 17 I O pins Each I O pin contains pull Iow MOS controllable by the program When every I O is used as an input port the port control register PCR controls ON OFF of the output buffer Sections below show the circuit configuration of I O ports PORTA PORTB PORTC PORTD and PORTE Each of these ports contains 4 bit I O pins PORTD contains 2 bit I O pins and 1 input pin PORTE contains 2 bit I O pins ON OFF of the output buffer for port can be controlled by the port control register PACR PBCR PCCR PDCR and PECR Port I O mapping address is shown as follows The following is the circuit configuration diagram PORT CONTROL REGISTER PORT DATA REGISTER DATA INPUT PULL LOW Figure 2 Port Configuration Function Block Diagram Port I O Control Register
21. s an area address 000 through 004 that is reserved for a special interrupt Service routine such as starting vector address Address 000 JMP instruction Jump to RESET service routine 001 NOP 003 NOP Reserved Reserved 002 JMP instruction Jump to TIMERO interrupt service routine 004 JMP instruction Jump to PORT interrupt service routine JMP instruction can be replaced by any instruction SH67P33 3 RAM Built in RAM contains of general purpose data memory and system register Because of its static nature the RAM can keep data after the CPU enters STOP or HALT 3 1 RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing The following is the memory allocation map System register and I O 00 Data memory 020 04F 3 2 Configuration of System Register System Register 00 1F RAM Map Address xm Two MERE sc m3 Interrupt flags TM0 0 0 Mode register Prescaler TH0 3 2 TH0 0 Timer0 load counter register high nibble 00 01 02 03 04 05 i 508 509 OA OD OE OF 14 15 RW RW REM R Bit0 REM pin output status TBR 3 TBR1 RW TBR 3 TBR 2 TBR 1 TBR 0 R W Ta
22. the port interrupt function block diagram PORTC 3 PCCR 3 PORTC 2 PCCR 2 PORTC 1 PCCR 1 PORTC 0 0 RISING EDGE PORT DETECTION INTERRUPT PBCR 3 PORTB 2 PBCR 2 PORTB 1 PBCR 1 Default opt pint 0 PORTB 0 PBCR 0 PORTD 2 PDCR 2 PORTD 1 PDCR 1 PORTD 0 PORTC 3 PCCR 3 PORTC 2 PCCR2 4_ RISING EDGE PORT PORTC 1 PCCR 1 IA 22 DETECTION INTERRUPT PORTC 0 PCCR 0 PORTB 3 PBCR3 4_ PORTB 2 Option set opt pint 1 PBCR 2 PORTB 1 PBCR 1 4_ PORTB 0 PBCRO d4 Figure 3 PORT Interrupt Block Diagram SH67P33 7 Remote Control Synthesizer SH67P33 has a carrier synthesizer for infrared or RF remote control circuits Bia 0D REMO output data REM pin output status Bit2 0 Carrier count source pre divider PPULL CPS2 CPST CPSO Bits Port Pul low MOS Control REMO Remote output data control The REM pin output status can be ready by instruction CPS2 0 Carrier counter source pre divider control Register The carrier synthesizer can be programmed in several different pre scaler ratios by setting CPS2 0 Carrier source pre divider control Register CPS2 CPS1 50 Clock Source wm 1 3 1 1 0 System clock 2 System Clock System clock 2 System Clock System clock 12 System Clock The carrier generating counter is an 8 bit count up counter
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