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RX63T Group Renesas Peripheral Driver Library User`s Manual

1. PDL_INTC_REG_IPR_BSC_BUSERR PDL_INTC_REG_IPR_MTUO_TGIAD PDL_INTC_REG_IPR_FCU_FIFERR PDL_INTC_REG_IPR_MTUO_TGIVEF PDL_INTC_REG_IPR_FCU_FRDYI PDL_INTC_REG_IPR_MTU1_TGIAB PDL_INTC_REG_IPR_ICU_SWINT PDL_INTC_REG_IPR_MTU1_TCIVU PDL_INTC_REG_IPR_CMTO_CMI PDL_INTC_REG_IPR_MTU2_TGIAB PDL_INTC_REG_IPR_CMT1_CMI PDL_INTC_REG_IPR_MTU2_TCIVU PDL_INTC_REG_IPR_CMT2_CMI PDL_INTC_REG_IPR_MTU3_TGIAD PDL_INTC_REG_IPR_CMT3 CMI PDL_INTC_REG_IPR_MTU3_TCIV PDL_INTC_REG_IPR_USBO_DOFIFOO PDL_INTC_REG_IPR_MTU4_TGIAD PDL_INTC_REG_IPR_USBO_D1FIFOO PDL_INTC_REG_IPR_MTU4_TCIV PDL_INTC_REG_IPR_USBO_USBIO PDL_INTC_REG_IPR_MTU5 PDL_INTC_REG_IPR_USBO_USBRO PDL_INTC_REG_IPR_MTU6_TGIAD PDL_INTC_REG_IPR_CAC PDL_INTC_REG_IPR_MTU6_TCIV PDL_INTC_REG_IPR_SPIO_SPRI PDL_INTC_REG_IPR_MTU7_TGIAB PDL_INTC_REG_IPR_SPIO_SPTI PDL_INTC_REG_IPR_MTU7_TGICD PDL_INTC_REG_IPR_SPIO_SPIl PDL_INTC_REG_IPR_MTU7_TCIV PDL_INTC_REG_IPR_SPI1_SPRI PDL_INTC_REG_IPR_POE PDL_INTC_REG_IPR_SPI1_SPTI PDL_INTC_REG_IPR_CMPO PDL_INTC_REG_IPR_SPI1_SPIl PDL_INTC_REG_IP
2. PDL_INTC_REG_IR_BSC_BUSERR PDL_INTC_REG_IR_MTU1_TGIA PDL_INTC_REG_IR_FCU_FIFERR PDL_INTC REG IR MTU1 TGIB PDL_INTC_REG IR FCU_FRDYI PDL_INTC_REG_IR MTU1_TCIV PDL_INTC_REG IR ICU_SWINT PDL_INTC_REG IR MTU1 TCIU PDL_INTC_REG IR CMTO CMI PDL_INTC_REG IR MTU2 TGIA PDL_INTC_REG IR CMT1 CMI PDL_INTC_REG IR MTU2 TGIB PDL_INTC_REG IR CMT2 CMI PDL_INTC_REG IR MTU2 TCIV PDL_INTC_REG IR CMT3 CMI PDL_INTC REG IR MTU2 TCIU PDL_INTC_REG IR USBO_DOFIFO PDL_INTC_REG IR MTU3 TGIA PDL_INTC_REG IR USBO D1FIFO PDL_INTC_REG IR MTU3 TGIB PDL_INTC_REG IR USBO_USBI PDL_INTC_REG IR _MTU3 TGIC PDL_INTC_REG IR _USBO_USBR PDL_INTC_REG IR _MTU3 TGID PDL_INTC_REG IR CAC FERRF PDL_INTC REG IR MTU3 TCIV PDL_INTC_REG_IR_CAC_MENDF PDL_INTC_REG_IR MTU4 TGIA PDL_INTC_REG IR CAC OVFF PDL_INTC_REG IR MTU4 TGIB PDL_INTC_REG IR SPIO SPRI PDL_INTC_REG IR _MTU4 TGIC PDL_INTC REG IR SPIO SPTI PDL_INTC REG IR MTU4 TGID PDL_INTC REG IR SPIO SPII PDL_INTC_REG IR MTU4 TCIV PDL_INTC_REG IR SPI1_SPRI PDL_INTC_ REG IR MTU5 TGIU PDL_INTC_ REG _IR SPI1_SPTI PDL_INTC_REG IR MTU5 TGIV PDL
3. void main void uint16_t mode_status uintl6_t reset_status uint32_t ofs0_copy uint32_t ofsl_copy Read the MCU status registers R_MCU_Get Status mode_status reset_status ofs0_copy ofsl_copy i Is this a Cold start if reset_status amp BIT_8 0 Set the warm start indicator R_MCU_Control PDL_MCU_WARM_START USER Handle cold start Figure 5 4 Example of MCU Operation R20UT2201EE0211 Rev 2 11 RENESAS Page 342 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 5 Voltage Detection Circuit Figure 5 5 shows an example of Voltage detection circuit usage An NMI is generated if the supply voltage drops below 2 95V Peripheral driver function prototypes include r_pdl_lvd h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h static void Callback_NMI void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Configure the NMI to be triggered by the LVD1 signal only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_LVD1_ENABL Callback_NMI PDL_NO_DATA y Setup VDET1 to callback if VCC drops below 2 95V R_LVD_Create PDL_LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD_FILTER_DISABL
4. Return value True if all parameters are valid and exclusive otherwise false Category DOC References None Remarks In Addition Mode an interrupt is generated if the result of the addition exceeds FFFFh In Subtraction Mode an interrupt is generated if the result of the subtraction is less than zero In Comparison Mode an interrupt is generated when the comparison criteria Match or Mismatch is met e This function brings the DOC module out of the power down state e If a callback function is specified then interrupts will be automatically enabled After calling a callback function the DOC flag is automatically cleared R20UT2201EE0211 Rev 2 11 RENESAS Page 327 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void Callback void void func void Setup DOC in addition mode R_DOC_Create PDL_DOC_MODE_ADD 0 Callback LS i R20UT2201EE0211 Rev 2 11 EN ESAS Page 328 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_DOC Destroy Synopsis Disable the Data Operation Circuit Prototype bool R_DOC_Destroy void Description Put the DOC module into the power down state Return value True Category DOC Reference Remarks Program example RPDL defi
5. PDL_INTC_REG_DTCER_CMP_CMP6 PDL_INTC_REG_DTCER_GPT6_GTCIV6 PDL_INTC_REG_DTCER_ICU_IRQO PDL_INTC_REG DTCER _IIC1_RXI PDL_INTC_REG_DTCER_ICU_IRQ1 PDL INTC_REG_DTCER _IIC1 TXI PDL_INTC_REG_DTCER_ICU_IRQ2 PDL_INTC_REG_DTCER_IICO_RXI PDL_INTC_REG_DTCER_ICU_IRQ3 PDL_INTC_REG_DTCER_IICO_TXI PDL_INTC_REG_DTCER_ICU_IRQ4 PDL_INTC_REG_DTCER_ICU_IRQ5 PDL_INTC_REG_DTCER_DMAC_DMACOI PDL_INTC_REG DTCER DMAC_DMACII PDL_INTC_REG_DTCER_ICU_IRQ6 PDL_INTC_REG DTCER DMAC_DMAC2I PDL_INTC_REG DTCER_ICU_IRQ7 PDL_INTC_REG_DTCER_DMAC_DMAC3I PDL_INTC_REG_DTCER_AD_ADI PDL_INTC_REG_DTCER_SCIO_RXI PDL_INTC_REG DTCER S12AD S12ADI PDL_INTC_REG DTCER S12AD_S12GBADI PDL_INTC REG DTCER SCIO TXI PDL_INTC_REG DTCER SCI1_RxI PDL_INTC_REG DTCER S12AD1_S12ADI PDL_INTC_REG DTCER SCI1_TXI PDL_INTC_REG DTCER S12AD1_S12GBADI PDL_INTC_REG DTCER SCl2 RxI PDL_INTC_REG DTCER MTUO TGIA PDL_INTC_REG DTCER SCI2 Tx PDL_INTC_REG_DTCER_MTUO_TGIB PDL_INTC_REG_DTCER_SCI3_RXI PDL_INTC_REG_DTCER_MTUO_TGIC PDL_INTC_REG_DTCER_SCI3_TXI PDL_INTC_REG DTCER MTUO TGID PDL_INTC_REG_DTCER_GPTO_GTCIAO PDL_INTC_REG_DTCER_MTU1_TGIA PDL_INTC_REG_DTCER_GPTO_GTCIBO PDL INTC REG DTCER MTU1 TGIB PDL_INTC_ REG DTCER MTU2 TGIA PDL_INTC_REG DTCER MTU2 TGIB PDL_INTC_REG_DTCER_GPT0_GTCICO PDL_INTC_REG_DTCER_GPTO
6. Y Setup master to receive Non polling NOTE No clocks pulses will be generated until R_SCI_Send is called data_received false R_SCI_Receive MASTER_CHANNEL PDL_NO_DATA rx_buffer DATA_LENGTH SCI_Rx _Callback PDL_NO_FUNC y Dummy send so the Slave Tx and Master Rx will happen R_SCI_Send MASTER_CHANNEL PDL_NO_DATA Dummy gt DATA_LENGTH PDL_NO_FUNC Wait for the Rx to finish while data_received false R20UT2201EE0211 Rev 2 11 AS Page 375 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples Check we got the data we expected if 0 strncmp const char rx_buffer Slave 5 while 1 Process the received data here while 1 Callback function for Rx static void SCI_Rx_Callback void data_received true Callback function for Tx static void SCI_Tx_Callback void data_sent true Figure 5 24 Example of Synchronous Full Duplex operation R20UT2201EE0211 Rev 2 11 AS Page 376 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 17 6 SCI Reception in Asynchronous Multi Processor mode This shows the setting of a SCI channel and the Multi Processor mode reception of data using interrupts and polling Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_io_port h PDL
7. data3 The registers to be modified All selections are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required The registers to be modified PDL_GPT_REGISTER COUNTER Timer counter PDL_GPT_REGISTER_A PDL_GPT REGISTER B General register A General register B PDL_GPT_REGISTER_C General register C PDL_GPT REGISTER D General register D PDL_GPT REGISTER E General register E PDL_GPT REGISTER F General register F PDL GPT REGISTER CYCLE Cycle setting register PDL_GPT_ REGISTER CYCLE BUFFER Cycle setting buffer register PDL_GPT_REGISTER_ CYCLE DOUBLE Cycle setting double buffer register PDL_GPT_ REGISTER ADC TRIG A ADC start request register PDL_GPT REGISTER ADC TRIG A BUFFER ADC start request buffer register PDL_GPT REGISTER ADC TRIG A DOUBLE ADC start request double buffer register PDL GPT REGISTER ADC TRIG B ADC start request register PDL_GPT_REGISTER_ADC_TRIG_B_BUFFER ADC start request buffer register PDL_GPT_ REGISTER ADC TRIG B DOUBLE ADC start request double buffer register PDL_GPT_REGISTER_DEAD_TIME_UP Dead time up counting register PDL_GPT_REGISTER_DEAD_TIME_UP_BUFFER Dead time up counting buffer register PDL_GPT_REGISTER_DEAD_
8. PD PDL PD PD L Rev 2 11 GPT_PWM_DELAY_ENABLE GPT_PWM_DELAY_DISABLI GPT_PWM_DELAY_ENABLE GPT_PWM_DELAY_DISABLE stENESAS Page 214 of 418 RX63T Group 4 Library Reference 10 R_GPT_EdgeDelay_Control Synopsis Prototype Description Return value Control the PWM Edge Delay circuit bool R_GPT_EdgeDelay_Control uint8_t data1 uint8_t data2 R_GPT_EdgeDelay_Times_ structure Apointer to a structure R_GPT_EdgeDelay_Times_structure members uint8_t GTIOCA_Rising_Delay GTIOCA Rising Edge Delay Time uint8_t GTIOCA_Falling Delay GTIOCA Falling Edge Delay Time uint8_t GTIOCB_Rising_Delay GTIOCB Rising Edge Delay Time uint8_t GTIOCB_Falling_Delay GTIOCB Falling Edge Delay Time Control the PWM Edge Delay circuit including setting adjusting the delay times data1 The channel number n where n 0 to 3 data2 Control option To set multiple options at the same time use to separate each value e Time adjustment Update the delay times with those specified in PDL_GPT_PWM_DELAY_TIME data3 to data6 e Activate this is not required for normal use but provides control of GTDLYCR DLYEN PDL_GPT_PWM_DELAY_ACTIVE or Activate the delay circuit PDL_GPT_PWM_DELAY_INACTIVE Inactivate bypass the delay circuit e Reset This is not required for normal use
9. Configure the IWDT R_IWDT_Set PDL_IWDT_TIMEOUT_1024 PDL_IWDT_CLOCK_OCO_256 i Start the IWDT R_IWDT_Control PDL_IWDT_REFRESH i Figure 5 19 Example of Independent Watchdog Timer use R20UT2201EE0211 Rev 2 11 RENESAS Page 365 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 Serial Communication Interface 5 17 1 SCI Asynchronous Using Polling This shows the setting of a SCI channel and the transmission and reception of data using polling Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h if defined DEVICE_PACKAGE_64_PIN amp amp defined D E_PACKAGI define CHANNEL_SCI 1 else define CHANNEL SCI 0 endif void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set pin options R_SCI_Set CHANNEL SCI if defined DEVICE_PACKAGE 64 PIN amp amp defined DEVICE _PACKAG PDI SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1 TXD1_PD3 else PDL_SCI_PIN_SCIO_RXDO_P24 PDL_SCI_PIN_SCIO_TXDO_P30 fendif Set up SCI channel Async 8N1 38400 baud R_SCI_Create CHANNEL_SCI
10. Set the IR for IRQO to 0 R_INTC_Write PDL_INTC_REG_IR_ICU_IROO 0 R20UT2201EE0211 Rev 2 11 EN ESAS Page 74 of 418 Sept 12 2014 RX63T Group 4 Library Reference 10 R_INTC_ Modify Synopsis Modify an interrupt register Prototype bool R_INTC_Modify uint16_tdata1 Register selection uint8_t data2 Logical operation uint8_t data3 Modification value Description Update the value in an interrupt register data1 e The register to be updated PDL_INTC_REG_IR_ register or Select the Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR register Interrupt Priority register data2 The logical operation to be applied to the register contents PDL_INTC_AND or PDL_INTC_OR or Select between AND 3 OR or Exclusive OR PDL_INTC_XOR data3 The value to be used by the logical operation Return value True if the parameter is within range otherwise false Category Interrupt control Reference None Remarks e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 69 Program ex
11. Description 2 2 func2 The function to be called if an error occurs Specify PDL_NO_FUNC to ignore errors data7 The interrupt priority level for error detection Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 Use the same error interrupt priority level as R_SCI_Create parameter data5 Program example R20UT2201EE0211 Sept 12 2014 Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks The amount of data for must match the total number of transfer frames refer to parameter data3 in R_SPI_Create If a callback function is specified and DMAC DTC control is not used interrupts are used to handle the data transfer Please see the notes on callback function usage in 6 If an error interrupt function is specified for parameter func 2 while PDL_NO FUNC is specified for parameter func 1 the error flag is polled without using an interrupt and the error interrupt function will be called when an error occurs After using this function use R_SPI_GetStatus to check for and clear any error flags RPDL definitions tinclude r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t transmit_data 8 uint32_t receive_data 8 Transmit and receive a
12. Operation Mode Description Comparison The comparison value Addition The initial output value before additions are made Subtraction The initial output value before subtractions are made Return value True if all parameters are valid and exclusive otherwise false Category DOC References R_DOC_Create Remarks e Interrupts can only be enabled if a callback was registered using R_DOC_Create R20UT2201EE0211 Rev 2 11 EN ESAS Page 330 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void Change to subtraction mode with initial value 500 R_DOC_Control PDL_DOC_MODE_SUBTRACT PDL_DOC_DATA_UPDATE 500 Y R20UT2201EE0211 Rev 2 11 EN ESAS Page 331 of 418 Sept 12 2014 RX63T Group 4 R_DOC_Read Synopsis Prototype Description 4 Library Reference Read the Data Operation Circuit result bool R_DOC_Read uint8_t data1 uint16_t data2 Pointer to status storage location Pointer to value storage location Read the DOC status and output data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b7 b1 bO Flag see remarks data2 This meaning of this parameter depends upon the Operation Mode as specified in
13. i Rev 2 11 ENESAS Page 65 of 418 RX63T Group 6 R_INTC_ControlExtInterrupt Synopsis Prototype Description Return value External interrupt control bool R_INTC_ControlExtinterrupt uint8_t data1 uint32_t data2 Control Modifies the specified external interrupt data1 Pin selection 4 Library Reference Choose the interrupt pin to be controlled PDL_INTC_IRQn or IRQn n 0 to 5 for 64 and 48 pin package n 0 to 7 PDL_INTC_NMI for 144 120 112 and 100 pin package interrupt pin or NMI interrupt pin data2 Select the controls If multiple selections are required use to separate each selection e Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin e Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC_FILTER_DIV_64 Disable the filter or select PCLKB divided by 1 8 32 or 64 e Detection sense selection for the IRQ pins PDL_INTC_LOW or PDL_INTC_FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection e Interrupt request clearing PDL_INTC_CLEAR_IR_FLAG Clear the IRQ or NMI int
14. Data length is 2 less than we want to read as first dummy byte is written out by R_SCI_IIC Read function and last one when we use R_SCI_IIC_ReadLastByte R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_FIXED PDL_DTC_SIZ PDL_DTC_IRQ COMPLETE PDL_DTC_TRIGGER_SCI1_TX dtc_iicl_tx transfer _data amp IIC_Dummy_value Source uint8_t SCI1 TDR Destination 3 Data length PDL_NO_DATA Y Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Y Start the IIC Read R_SCI_IIC_Read CHANNEL SCI_IIC PDL_SCI_IIC_RESTART PDL_SCI_IIC_DTC_TRIGGER_ SLAVE_ADDRESS PDL_NO_DATA No data length as using DTC PDL_NO_DATA No buffer as using DTC CallbackRx R20UT2201EE0211 Rev 2 11 AS Page 387 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples Wait for rx while data_received false Because using DMAC need to manually get the last byte This will also generate the stop condition R_SCI_IIC_ReadLastByte CHANNEL_SCI_IIC IIC_Buffer 4 Callback function for Rx static void CallbackRx void data_received true Figure 5 30 Example of SCI in IIC mode using DTC R20UT2201EE0211 Rev 2 11 RENESAS Pa
15. Description Write data into the backup registers data1 The data to be written to the backup area data2 The number of bytes to be written to the backup area Valid from 1 to 32 Return value True if all parameters are valid otherwise false Category LPC References None Remarks The ee R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data_to_save R_PDL_LPC_BACKUP_AREA_SIZE Write data into the backup registers R_LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AREA_SIZE R20UT2201EE0211 Rev 2 11 RENESAS Page 118 of 418 Sept 12 2014 RX63T Group 4 R_LPC_ReadBackup Synopsis Read from the Backup registers Prototype bool R_LPC_ReadBackup uint8_t data1 Data pointer uint8_t data2 Data count Description data1 The storage area for the data read from the backup area data2 Read data from the backup registers 4 Library Reference The number of bytes to be read from the backup area Valid from 1 to 32 Return value Category LPG References R_LPC_WriteBackup Remarks available Program example R20UT2201EE0211 Sept 12 2014 RPDL defini
16. Disable or enable start control from another peripheral If enabled select a start source using parameter data5 PDL_ GPT HW STOP DISABLE or PDL_GPT_HW_STOP_RISING or PDL_GPT_HW_STOP_FALLING or PDL_GPT_HW_STOP_BOTH PDL_GPT_HW_CLEAR_DISABLE or PDL_GPT_HW_CLEAR_RISING or PDL_GPT_HW_CLEAR FALLING or PDL_GPT_HW_CLEAR BOTH Disable or enable stop control from another peripheral If enabled select a stop source using parameter data5 Disable or enable counter clearing control from another peripheral If enabled select a clear source using parameter data5 data5 Hardware control selections If multiple selections are required use to separate each selection e Hardware start source selection Ignored if hardware start control is disabled PDL_GPT_HW_START_ANODOO or PDL_GPT_HW_START_ANO01 or PDL_GPT_HW_START_ANO02 or PDL_GPT_HW_START_AN100 or PDL_GPT_HW_START_AN101 or PDL_GPT_HW_START_AN102 or Comparator detection on 12 bit ADC input ANxxx PDL_GPT_HW_START_GTIOC3A_IN or PDL_GPT_HW_START_GTIOC3B_IN or A valid edge on the GPT pin PDL_GPT_HW_START_GTIOC3A_OUT PDL_GPT_HW_START_GTIOC3B_OUT or or A valid edge on the GPT output compare Not valid for channel 3 PDL_GPT_HW_START_GTETRGO or PDL_GPT_HW_START_GTETRG1 A valid edge on the GTETRGn pin e Hardware stop clear selection Ignored if both hardware
17. Figure 5 29 Example of SCI in IIC mode using DMAC R20UT2201EE0211 Rev 2 11 AS Page 385 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 17 11 SCI in IIC Mode using DTC This shows the setting of SCI channel 1 in to IIC mode and then a read from an IIC EEPROM using the DTC PDL functions tinclude r_pdl_sci h tinclude r_pdl_cgc h tinclude r_pdl_dtc h PDL device specific definitions include r_pdl_definitions h static void CallbackRx void SCI IIC Channel define CHANNEL_SCI_IIC 1 IIC Slave address of EEPROM define SLAVE_ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 Flag volatile uint8_t data_received Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 void main void Data Buffer volatile uint8_t IIC_Buffer 10 DTC needs to write dummy data to SCI TDR when reading uint8_t IIC_Dummy_value OxFF Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set Channel 1 pin options R_SCI_Set 1 if defined DEVICE PACKAG
18. The master has sent us data now in the Rx_Buffer store it in the data_storage array static void StoreData uint16_t count uint16_t index 0 Update data_storage_index data_storage_index Rx_Buffer index count index Store any data R20UT2201EE0211 Rev 2 11 RENESAS Page 402 of 418 Sept 12 2014 RX63T Group 5 Usage Examples while count 0 data_storage data_storage_index Rx_Buffer index count index data_storage_index if data_storage_index STORAGE Wrap around data_storage_index 0 Figure 5 40 Virtual IIC Slave memory R20UT2201EE0211 Rev 2 11 AS Page 403 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 19 Serial Peripheral Interface 5 19 1 Master operation with multiple slaves This is an example of Serial Peripheral Interface usage where one SPI master communicates with four SPI slaves Each slave requires different data bit lengths RSPCKA SPI channel 0 MOSIA MISOA Master SSLAO SSLA1 SSLA2 SSLA3 Slave 0 8 bit data words Slave 1 9 bit data words Slave 2 15 bit data words 7 Slave 3 24 bit data words Figure 5 41 shows how data of appropriate bit lengths is transferred to each SPI slave Commands 0 to 3 are executed in sequence with each command asserting the appropriate SSL pin Peripheral driver function prototypes include r_pdl_spi h include r_pdl_cgc h
19. Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Parameters data3 and data4 contain the positive and negative tolerances Parameters data3 and data4 contain the register values PDL_GPT_IWDTCLK_DEVIATION_TOLERANCE or PDL_GPT_IWDTCLK_DEVIATION_REGISTER data3 If required either the maximum positive deviation for the main clock ICLK as a percentage or the LCNTDU register value If the IWDTCLK count deviation update is not required specify PDL_NO_DATA data4 If required either the maximum negative deviation for the main clock ICLK as a percentage or the LCNTDL register value If the IWDTCLK count deviation update is not required specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false General PWM Timer unit R_GPT_CreateUnit R_IWDT_Set R_IWDT_Control The Stop operations are executed at the start of this function The Start operations are executed at the end Both options can be selected together with other changes in one function call e If Stop or Start control is selected any channel that has hardware start or stop control enabled may change state in error Ifthe IWDTCLK counter is enabled the Independent Watchdog Timer IWDT should also be enabled The following sequence is recommended a Use R_GPT_CreateUnit to configure the IWDTCLK counter b Use R_IWDT_Set and R_IWDT_Control t
20. ENESAS Page 285 of 418 RX63T Group Description 2 2 4 Library Reference data4 Extended timing control If multiple selections are required use to separate each selection The default settings are shown in bold For Slave mode select PDL_NO_DATA Extended timing selection PDL_SPI_CLOCK_DELAY MINIMUM or Select the minimum or extended delay between PDL_SPI_CLOCK DELAY EXTENDED the assertion of the SSL pin and the start of RSPCK oscillation SSL negation delay Select the minimum or extended delay between PDL_SPI_SSL_DELAY_MINIMUM or Sat E PDL SPI SSL DELAY EXTENDED the end of RSPCK oscillation and the negation of the active SSL pin Next access delay PDL_SPI_NEXT DELAY MINIMUM or Select the minimum or extended delay between PDL SPI NEXT DELAY EXTENDED oe of one frame and the start of the next Program example Return value True if all parameters are valid otherwise false Category SPI Reference R_SPI_Create Remarks For Slave mode operation configure command 0 e When Clock synchronous Slave mode is used avoid selecting mode 0 or mode 2 e If parity is enabled while in Master mode both the frame data length and data transfer format should be the same for each command RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configur
21. ENESAS Page 72 of 418 RX63T Group 4 Library Reference 8 R_INTC_Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Read an interrupt register bool R_INTC_Read uint16_tdata1 Register selection uint8_t data2 Data storage location Read an interrupt register and store the value data1 The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register DTC Activation Enable register data2 The location where the register s value shall be stored True if all parameters are valid and exclusive otherwise false Interrupt control None For register select one of the registers listed in the tables starting on page 69 RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t ipl Read the IPL bits R_INTC_Read PDL_INTC_REG_IPL amp ipl Y Rev 2 11 ENESAS Page 73 of 418 RX63T Group 9 R_INTC_Write Synopsis Prototype Descript
22. If a callback function was specified in the call to R_IIC_SlaveMonitor then this transfer shall be completed using interrupts and the callback function shall be called when the transfer ends If a callback function was not specified in the call to R_IIC_SlaveMonitor then this function will not return until the transfer has ended lf the master requires more data than is supplied this function shall loop back to the start of the data e Channel 1 is supported on 120 pin 144 pin packages only Program example R20UT2201EE0211 Sept 12 2014 RPDL definitions tinclude r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Assign 5 bytes to be read by a master on channel 0 R_IIC_SlaveSend 0 data_array 5 i Rev 2 11 EN ESAS Page 275 of 418 RX63T Group 8 R_IIC_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 12 channel control bool R_IIC_Control uint8_t data1 uint8_t data2 4 Library Reference Channel selection Control options Modify the operation of the selected I2C channel data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for devic
23. The rest is interrupt driven while 1 R_IIC SlaveMonitor or R_IIC_SlaveSend callback static void slave_callback void uint32_t status_flags 0 uint16_t tx_count 0 uintl6_t rx_count 0 R20UT2201EE0211 Rev 2 11 RENESAS Page 401 of 418 Sept 12 2014 RX63T Group 5 Usage Examples bool bStartMonitor true Read the status R_IIC_GetStatus SLAVE_CHANNEL amp status_flags amp tx_count rx_count y Has the master just completed a write if rx_count 0 StoreData rx_count Start monitoring again bStartMonitor true Has the master just completed a read else if tx_count 0 Increment the current index by the amount the master read data_storage_index tx_count Start monitoring again bStartMonitor true Is the master starting a read Check this by seeing if in transmit mode else if 0 status_flags BIT_6 Send data to master based on current address R_IIC_SlaveSend SLAVE_CHANNEL amp data_storage data_storage_index uint16_t STORAGE_SIZE data_storage_index y Don t start monitoring again until the R_IIC_SlaveSend completes bStartMonitor false if true bStartMonitor Continue monitoring R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZ slave_callbac 7
24. Get the value of register PFCSE R_MPC_Read PDL_MPC_REG_P40PFS amp data Rev 2 11 ENESAS Page 93 of 418 RX63T Group 2 R_MPC Write Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference Write to a MPC register bool R_MPC_Write uint8_t data1 MPC register selection uint8_t data2 Data to be written to the MPC register Write the value to an MPC register data1 One of the definition values from 4 2 4 data2 The value to be written to the register True if a valid MPC register is specified otherwise false MPC registers None The MPC registers are modified by other driver functions Take care to not overwrite existing settings Refer to the hardware manual for valid values for each register RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void Write data to register PD3PFS R_MPC_Write PDL_MPC_REG_PD3PFS OxFF Rev 2 11 ENESAS Page 94 of 418 RX63T Group 4 Library Reference 3 R_MPC_Modify Synopsis Prototype Description Return value Category References Remarks Program example R20
25. PDL_ADC_10_TRIGGER_GPT2 CM Bor GPT2 GTADTRB compare match PDL_ADC_10_TRIGGER_GPT3_CM Aor GPT3 GTADTRA compare match PDL_ADC_10_TRIGGER_GPT3_CM Bor GPT3 GTADTRB compare match PDL_ADC_10_TRIGGER_GPTO_CM_AB or GPTO GTADTRA compare match or GPTO GTADTRB compare match PDL_ADC_10_TRIGGER_GPT1_CM_AB or GPT1 GTADTRA compare match or GPT1 GTADTRB compare match PDL_ADC_10_TRIGGER_GPT2_CM_AB or GPT2 GTADTRA compare match or GPT2 GTADTRB compare match Rev 2 11 ENESAS Page 315 of 418 RX63T Group Return value Category References Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference GPT3 GTADTRA compare match or PDL_ADC_10_TRIGGER_GPT3_CM_AB or GPT3 GTADTRB compare match PDL_ADC_10_TRIGGER_GPT4_CM Aor OTADITRATGPTAGTADIIRA compare match GTADTRB4 GPT4 GTADTRB PDL_ADC_10_TRIGGER_GPT4_CM Bor iaa PDL_ADC_10 TRIGGER_GPT5_CM Aor GTADTRAS GPT5 GTADTRA compare match PDL_ADC_10_TRIGGER_GPT5_CM Bor GTADTRB5 GPT5 GTADTRB compare match GTADTRA6 GPT6 GTADTRA PDL_ADC_10_TRIGGER_GPT6_CM Aor a PDL_ADC_10_TRIGGER_GPT6_CM_B or GLAD FRED GPT6 GTADTRE compare match PDL_ADC_10_TRIGGER_GPT7_CM Aor GI ADEA GP T7 GTADTRA compare match GTADTRB7 GPT7 GTADTRB PDL_ADC_10_TRIGGER_GPT7_CM Bor sonnei mate GPT4 GTADTRA compare match or GPT4 GTADTRB compare match GPT4 GTADTRA compare match or GPT4 GTADTRB compare match GPT6 GTADTRA
26. PDL_MTU3_CONTROL_CH_34 Configure the operation of channels 3 and 4 PDL_MTU3_CONTROL_CH_67 Configure the operation of channels 6 and 7 Select the controls All selections are optional If identical controls are required for both pairs use to separate each selection Specify PDL_NO_DATA if no change is required e Register protection PDL_MTU3_ACCESS DISABLE PDL_MTU3 ACCESS ENABLE Control the access to some control registers and counters Dead time generation control PDL_MTU3_DEAD_TIME_DISABLE or PDL_MTU3_DEAD_TIME_ENABLE Disable or enable dead time generation Waveform retention control PDL_MTU3_WAVEFORM_RETAIN_ENABLE PDL_MTU3_WAVEFORM_RETAIN_DISABLE or Disable or enable waveform output retention Synchronous clearing control Applies only to channel pair 6 and 7 PDL_MTU3_SYNC_CLEAR_DISABLE or PDL_MTU3_SYNC_CLEAR_ENABLE Disable or enable synchronous clearing Compare match clearing control PDL_MTU3_CNT_CLEAR_CM_A_ENABLE PDL_MTU3_CNT_CLEAR_CM_A_DISABLE or Disable or enable counter clearing on TGRA compare match This must not be enabled if not in Complementary PWM Mode 1 Reset synchronised or complementary PWM control PDL_MTU3_PWM_RS_COMP_ENABLE Enable reset synchronised or complementary PWM mode Registers to be modified PDL_MTU3_REGISTER_DEAD_TIME Update the dead
27. T T uint8_t 1 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_NORMAL PDL_DMAC_SIZE_8 PDL_DMAC_SOURCE_ADDRESS_PLUS PDL _DMAC_DESTINATION_ADDRESS_FIXED PDL_DMAC_IRQ_END PDL_DMAC_TRIGGER_IICO_TX eeprom_data_array_l uint8_t amp RIICO ICDRT ARRAY _1_SIZE PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA lic_tx_dmac_end handler 7 i Set up a DMAC channel for IIC reception This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DMAC_Create 2 PDL_DMAC_NORMAL PDL_DMAC_SIZE_8 PDL_DMAC_SOURCE_ADDRESS_FIXED R20UT2201EE0211 Rev 2 11 RENESAS Page 393 of 418 Sept 12 2014 RX63T Group 5 Usage Examples PDL _DMAC_DESTINATION_ADDRESS PLUS PDL_DMAC_IRQ_END DL_DMAC_TRIGGER_IICO_RX uint8_t amp RIICO ICDRR ta_storage RRAY_1_SIZE 2 Array size written sub address byte last byte DL_NO_DATA DL_NO_DATA D D i w L_NO_DATA L_NO_DATA c_rx_dmac_end_handler mH y A O o td Y Pp Select I C mode at 100kHz 300ns rise time 200ns fall time R_
28. include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void main void if defined DEVICE_PACKAGE_64_PIN defined DEVICE_PACKAGE_48_PIN Set the LOCO clock settings the clock source used after a power on reset ICLK 125 kHz PCLKA 125 kHz PCLKB 125 kHz PCLKD 125 kHz FCLK 125 kHz R_CGC_Set PDL_CGC_CLK_LOCO PDL_NO_DATA 125E3 125E3 125E3 125E3 PDL_NO_DAT 125E3 125E3 PDL_NO_DAT PDL_NO_DAT Y Configure main clock operation using a 16 0 MHz crystal ICLK 4 MHz PCLKA 4 MHz PCLKB 4 MHz PCLKD 4 MHz FCLK 4 MHz R_CGC_Set CGC_CLK_MAIN TA PD PD 16 4E 4E 4E PD 4E 4E PD PD Y Configure PLL operation The PLL will be set to 200 MHz ICLK 100 MHz PCLKA 100 MHz PCLKB 50 MHz PCLKD 50 MHz FCLK 50 MHz R_CGC_Set PDL_CGC_CLK_PLL PDL_NO_DATA 200E6 100E6 100E6 50E6 PDL_NO_DATA 50E6 50E6 R20UT2201EE0211 Rev 2 11 AS Page 335 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples L_NO_DA L_NO_DAT else Set the LOCO clock settings the clock source used after a power on reset ICLK 125 kHz PCLKA 125 kHz PCLKB 125 kHz PCLKD 125 kHz FOLK 125 kHz R_CGC_Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DIS
29. ty R20UT2201EE0211 Sept 12 2014 Rev 2 11 Page 397 of 418 ENESAS RX63T Group PDL_NO_DAT Set up a DTC channel for IIC reception 5 Usage Examples This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_ FIXED PDL _DTC_DESTINATION_ADDR PDL_DTC_SIZE_8 PDL_DTC_IRO_COMPLETE PDL_DTC_TRIGGER_IICO_RX dtc_iicl_rx_transfer_data uint8_t RIICO ICDRR data_storage ESS_PLUS ARRAY_1_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create TIC_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 1001 30 y Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Y Write the data into the EEPROM write _eeprom_data Prepare the next data to write to the EEPROM R_DTC_Control PDL_DTC_UPDATE_SOURCE PDL_DTC_UPDATE_COUNT dtc_iicl_tx transfer data eeprom_data_array_2 PDL_NO_PTR ARRAY_2_SIZE PDL_NO_DATA Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 2
30. Comparison value void func Function pointer Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin func The function to be called if a match occurs True if the parameters are valid otherwise false I O port R_IO_PORT_Set f an invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions tinclude r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void IoHandlerl void void IoHandler2 void void func void Call function IoHandlerl if port pin P22 is high R_IO_PORT_Compare PDL_IO_PORT_2_2 1 ToHandlerl Call function IoHandler2 if port 4 reads as 0x55 R_IO_PORT_Compare PDL_IO_PORT_4 0x55 ToHandler2 Rev 2 11 ENESAS Page 88 of 418 RX63T Group 4 Library Reference 7 R_IO PORT Modify Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Modify the pin st
31. ENESAS 0 D ae 0 lt D C V Renesas Peripheral Driver Library User s Manual RX63T Group All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com oe Rev 2 11 Sept 2014 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents c
32. PDL device specific definitions include r_pdl_definitions h define MASTER_CHANNEL 0 void main void const uint32_t master tx data 4 0x000000A4 8 bit data 0x00000132 9 bit data 0x00007F34 15 bit data 0x00345678 24 bit data uint32_t master_rx_data 4 R20UT2201EE0211 Rev 2 11 RENESAS Page 404 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 0x00000000 0x00000000 0x00000000 0x00000000 y Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure SPI Pin R_SPI_Set MASTER_CHANNEL PDL_SPI_RSPCKA_P24 PDL_SPI_MOSIA_P23 PDL_SPI_MISOA_P22 PDL_SPI_SSLAO_P30 PDL_SPI_SSLA1_P31 PDL_SPI_SSLA2_P32 PDL_SPI_SSLA3_P33 PDL_NO_DATA Configure the master SPI channel R_SPI_Create MASTER_CHANNEL L_SPI_MODE_SPI 1 SP1_PIN_SS f L SPI_PIN_SSL L_SPI_PIN_SS f E SPI_PIN_SSL L_SPI_FRAME_ L_NO_DATA E6 Prepare the transfer with slave 0 R_SPI_Command MASTER_CHANNEL 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LSB_FIRST PDL_SPI_ASSERT_SSLO PDL_SPI_LENGTH_8 PDL_NO_DATA y Prepare the transfer with slave 1 R_SPI_Command MASTER_CHANNEL 1 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LSB_FIRST PDL_SPI_ASSERT_SSL1
33. PDL_DMAC_UPDATE_REPEAT_DESTINATION Destination address extended repeat area using parameter data9 data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required ENESAS Page 139 of 418 RX63T Group Description 2 2 4 Library Reference data6 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode Specify PDL_NO_DATA if not required data7 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected Specify PDL_NO_DATA if not required data8 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required data9 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_ Create Remarks The Software trigger control is valid only if the Software trigger option has been selected This function must be called in order to start the DMAC e The Suspend Enable and Start control is executed at the end of
34. Program example R20UT2201EE0211 Sept 12 2014 Wait for a match on an I O port bool R_IO_PORT_Wait uint16_tdata1 Output port or port pin selection uint8_t data2 Comparison value Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port R_IO_PORT_Set If an invalid port or pin is specified the operation of the function cannot be guaranteed This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Wait until pin P22 reads as 0 R_IO_PORT_Wait PDL_IO PORT 2 2 0 i Wait until port 4 reads as 0x55 R_IO PORT Wait PDL_IO_PORT_4 0x55 Rev 2 11 ENESAS Page 90 of 418 RX63T Group 4 Library Reference 9 R_IO_PORT_NotAvailable Synopsis Prototype Description Return value Category
35. Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Read the last byte of an IIC read transfer bool R_SCI_IIC_ReadLastByte uint8_t data1 Channel selection uint8_t data2 Buffer to receive byte If R_SCI_IIC_Read has been used to start an IIC read where the DMAC or DTC will read all the data except for the last byte this function can be used to read the last byte ANACK will then be generated followed by a stop condition unless the original transfer request asked for the stop condition to be omitted data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 The address of the buffer that will receive the byte True SCI R_SCI_IIC_Read RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 1 Buffer for IIC data volatile uint8_t IIC_Buffer 10 void func void Read the last byte of the IIC read operation R_SCI_IIC_ReadLastByte CHANNEL SCI_IIC TIIC_Buffer 9 Rev 2 11 EN ESAS Page 257 of 418 RX63T Group 4 Library Reference 10 R_SCI_Control Synopsis Prototype Description Return value
36. RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Clear the bus error signals R_BSC_Control PDL_BSC_ERROR_CLEAR Y Rev 2 11 ENESAS Page 131 of 418 RX63T Group 4 Library Reference 6 R_BSC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Read the Bus Controller status registers bool R_BSC_GetStatus uint8_t data1 The status register 1 storage location uint16_t data2 The status register 2 storage location Read the BSC status registers data1 The status flags shall be stored according to register BERSR1 format as below Specify PDL_NO_PTR if this information is not required b7 b6 b4 b3 b2 b1 bO The bus master that caused the error Timeout Illegal address access 0 000 CPU 0 0 None 011 DTC or DMAC 1 Occurred data2 The status flags shall be stored according to register BERSR2 format as below Specify PDL_NO_PTR if this information is not required b15 b3 b2 b0 The upper 13 bits of the address that was accessed when the bus error occurred 0 in units of 512 Kbytes True Bus Controller R_BSC_Control e Call R_BSC_Control to clear the status registers after reading t
37. R_IO_PORT_Write PDL _IO PORT 2 2 1 i Invert pin P22 R_IO_PORT_Modify PDL_IO PORT 2 2 PDL_IO_PORT_XOR 1 And the value on port 4 with 55h R_IO_PORT_Modify PDL_IO_PORT_4 PDL_IO_PORT_AND 0x55 Read the direction for pin P22 R_IO_PORT_ReadControl PDL_IO_PORT_2_ 2 PDL_IO_PORT_DIRECTION amp control_register R20UT2201EE0211 Rev 2 11 AS Page 340 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples Set the lower 4 bits on port P3 to output R_IO_PORT_ModifyControl PDL_IO_PORT_3 PDL_IO_PORT_DIRECTION PDL_IO_PORT_OR Ox0F Figure 5 3 Example of I O Port Operations R20UT2201EE0211 Rev 2 11 RENESAS Page 341 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 4 MCU Operation This sample sets the Option Setting Memory and then detects if a Cold start has occurred Peripheral driver function prototypes include r_pdl_mcu h include r_pdl_mcu_ofs h PDL device specific definitions include r_pdl_definitions h Set the Option Setting Memory Enable the IWDT auto start mode Leave the WDT disabled Enable reset at Vdet0 R_MCU_OFS PDL_MCU_OFS_IWD AR PDL_MCU_OFS_IWDT_TIMEOUT_4096 PDL_MCU_OFS_IWD1 1 LOCO_16 PDL_MCU_OFS_IWDT_WIN_END_50 PDL_MCU_OFS_IWD ART_75 PDL_MCU_OFS_IWDT_NMI PDL_MCU_OFS_IWDI P_DISABLE PDL_MCU_OFS_WDT_HALTED PDL_MCU_OFS_LVD_0_ENABL
38. 9 Configuring the pins that are not available on smaller packages to the required state R20UT2201EE0211 Rev 2 11 LEN ESAS Page 21 of 418 Sept 12 2014 RX63T Group 2 Driver 2 6 Multifunction Pin Controller Driver The driver functions support access to the Multifunction Pin Controller MPC registers which select the mode of operation for some I O pins The other driver functions modify the MPC registers automatically For peripherals that are not supported by the driver library these functions support 1 Reading from an MPC register 2 Writing to an MPC register 3 Modifying an MPC register R20UT2201EE0211 Rev 2 11 RENESAS Page 22 of 418 Sept 12 2014 RX63T Group 2 Driver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the MCU features and on chip ROM and RAM 2 Reading the MCU status flags 3 Setting the MCU start up options R20UT2201EE0211 Rev 2 11 AS Page 23 of 418 Sept 12 2014 RENES RX63T Group 2 Driver 2 8 Voltage Detection Circuit Driver The driver function supports configuration of VDET1 and VDET2 voltage detection circuits This function supports 1 Configuring the detection circuits for use including a Setting voltage thresholds b Defining a voltage event c Setting up interrupts when a voltage event is detected d Configuring a reset when supply
39. Configure the SCI IIC Channel R_SCI_Create CHANNEL SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 0 Y Set up data buffer for the write Address in EEPROM TIIC_Buffer 0 EEPROM_ADDRESS Data to write TIC_Buffer 1 EEPROM_VALUE IIC write R_SCI_IIC Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 2 TIC_Buffer PDL_NO_FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 382 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot r E 3 DL_NO_FUNC Confirm this write worked by reading back the data from the EEPROM 1 Set current EEPROM address TIC_Buffer 0 EEPROM_ADDRESS R_SCI_IIC_Write CHANNEL SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 IIc_Buffer PDL_NO_FUNC Y 2 Read data from current address R_SCI_IIC_Read CHANNEL SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 1 TIC_Buffer PDL_NO_FUNC Confirm the value written is the same as the value read if IIC_Buffer 0 EEPROM_VALUE User Handle Error Figure 5 28 Example of SCI in IIC mode R20UT2201EE0211 Rev 2 11 RENESAS Page 383 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 10 SCI in IIC Mode using DMAC This shows the setting of SCI channe
40. Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes in the storage area If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC If not using the DMAC or DTC this function will continue until a Stop or Re Start condition is detected or the master tries to read Polling data from this slave If using the DMAC or DTC the function will return after detecting a slave address match so that the DTC DMAC can complete the transfer The function to be called when a Stop or Re Start condition is detected or Interrupts the master tries to read data from this slave DMAC or DTC The function to be called when a Stop or Re Start is detected data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false 12C Reference R_IIC_Create R_IIC_GetStatus R_IIC_SlaveSend R20UT2201EE0211 Rev 2 11 LEN ESAS Page 273 of 418 Sept 12 2014 RX63T Group 4 Li
41. During execution of this function the ICLK frequency is temporarily halved in value Therefore it is recommended to call this function before enabling other modules that rely on ICLK Ifthe GPT module is in the stopped state the stop state will be cancelled If a delay is going to be enabled for a channel then the counter for that channel will be stopped Function R_CGC_Set must be called before any use of this function ICLK must be 2 80MHz to enable the Delay circuit This function will return false if this is not the case The initialisation process of the delay circuit includes a waiting time that this function automatically provides If this function is used to enable all of the required delay channels at the same time then this delay period is shared thus minimising the overall initialisation time When a channel is first enabled this function will set the delay time to zero no delay Use function R_GPT_EdgeDelay_Control to set the required delay time e It is recommended to use this function before using R_GPT_CreateChannel Rev 2 11 EN ESAS Page 213 of 418 RX63T Group 4 Library Reference Program example R20UT2201EE0211 Sept 12 2014 RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void Enable the PWM delay circuit for channels 0 and 2 L EdgeDelay_Create L
42. PDL_IO _PORT_2 2 PDL_IO_PORT_INPUT ENESAS Page 81 of 418 RX63T Group 2 R_IO_PORT_ReadControl Synopsis Read an I O port s control register Prototype bool R_IO_PORT_ReadControl uint16_t data1 uint8_t data2 uint16_t data3 Description data1 Read an I O port pin control setting 4 Library Reference Port or port pin selection Control register selection Data storage location Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 e Select the register to be read PDL_IO_PORT DIRECTION or Data direction PDL_IO_PORT_MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_DRIVE_BUS or PDL_IO_PORT_DRIVE_SPI Drive capacity control related to external bus pins Valid on packages with 100 pins or more Drive capacity control related to SPI pins Valid on packages with 100 pins or more data3 The address where the register value shall be stored using one of the formats below Pin control b15 b1 bO 0 Oor1 Port not open drain control b15 b8 b7 b0 0 Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO Port Driving Ability control for option PDL_IO_PORT_DRIVE_BUS b15 b8 b7 b0 0
43. PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 0 Wait while send message R_SCI_Send CHANNEL_SCI PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 PDL_NO_FUNC y Wait for 5 characters to be read R_SCI_Receive CHANNEL_SCI PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC PDL_NO_FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 366 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Echo the 5 characters back R_SCI_Send CHANNEL_SCI PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC Figure 5 20 Example of SCI asynchronous operation using polling R20UT2201EE0211 Rev 2 11 AS Page 367 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 17 2 SCI Asynchronous Using Interrupts This shows the setting of a SCI channel and the transmission and reception of data using interrupts Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h if defined DEVICE_PACKAGE_64_PIN amp amp defined D E_PACKAG define CHANNEL_SCI 1 else define CHANNEL SCI 0 endif void SCIrx void void SCItx void volatile bool data_received volatile bool data_sent void main void volatile uint8_t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_
44. Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Change channel 2 to Ims period R_CMT_Control r DL_CMT_STOP PDL_CMT_PERIOD PDL_CMT_START E 3 rtd dD R20UT2201EE0211 Rev 2 11 RENESAS Page 224 of 418 Sept 12 2014 RX63T Group 5 R_CMT_Read Synopsis Prototype Description Return value Category Reference 4 Library Reference Read CMT channel status and registers bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Read and store the counter value and status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid otherwise false Compare Match Timer R_CMT_Create Remarks R20UT2201EE0211 Sept 12 2014 Program example If the flag is read and is set to 1 it shall be automatically cleared to O by this function RPDL definition
45. RX63T Group 4 Library Reference Description 4 9 ADC _irigger_operation Configure the ADC trigger operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e ADC conversion trigger control Valid for n 5 unless stated otherwise PDL_MTU3 ADC TRIG TGRA DISABLE or Disable or enable ADC start requests PDL_MTU3_ADC_TRIG_TGRA_ENABLE Gre TORA compare imate or input capture Disable or enable ADC start requests on a TGRE compare match or input capture Valid only for n 0 Disable or enable ADC start requests on a TCNT underflow Valid for n 4 and 7 in complementary PWM mode PDL_MTU3_ADC_TRIG_TGRE_DISABLE or PDL_MTU3_ADC_TRIG_TGRE_ENABLE PDL_MTU3_ADC_TRIG_TROUGH_DISABLE or PDL_MTU3_ADC_TRIG_TROUGH_ENABLE e Control ADC trigger interrupt skipping Valid for n 4 and 7 in complementary PWM mode Disable or link interrupt PDL_MTU3_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU3_ADC_TRIG_A_TROUGH_INT_SKIP_ENABLE TRGnAN on a TCNT underflow Disable or link interrupt PDL_MTU3_ADC_TRIG_B_TROUGH_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU3_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE TRGnBN on a TCNT underflow Disable or link interrupt PDL_MTU3_ADC_TRIG_A_CREST_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU3_ADC_TRIG_A_CREST_INT_SKIP_ENABLE TRGnAN on
46. R_SCI_Send CHANNEL_SCI 0 PDL_NO_DATA Hello from Renesas RX63T SCI Polling r n PDL_NO_DATA PDL_NO_FUNC y while 1 Figure 5 22 Example of SCI Asynchronous operation using DMAC R20UT2201EE0211 Rev 2 11 AS Page 371 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 17 4 Synchronous Transmission and Reception This shows the configuration of SCI channel 0 as the clock master and channel 1 as the slave The master transmits data to the slave The slave receive function call uses interrupts to call a callback function on completion Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h SCI channel selection define MASTER_CHANNEL 0 define SLAVE _CHANNEL 1 Rx complete flag volatile uint8_t data_received Callback function prototype static void SCIORxFunc void void main void volatile uint8_t rx_buffer 5 0 0 0 0 O Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set pin options R_SCI_Set 0 if defined DEVICE_PACKAGE_64_PIN amp amp defined DEVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCIO_TXDO_PB2 PDL_SCI_PIN_SCIO_SCKO_P
47. Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 PDL_SCI_PIN_SCI12_RXD12 PB6 ae PDL_SCI_PIN SCI12_RXD12 P80 PDL_SCI_PIN SCI12_SMISO12 PB6 PDL_SCI_PIN_SCI12_SMISO12 P80 SMISO12 PDL SCI PIN SCI12 SSCL12 PB6 re PDL_SCI_PIN SCI12 SSCL12 P80 PDL_SCI_PIN SCH2_TXD12 PB5 as PDL_SCI_PIN SCI12_TXD12 P81 PDL_SCI_PIN SCI12 SMOSI2 PBS SMOSI12 PDL SCI PIN SCI12_SSDA12 PB5 sci12 Sau PDL SCI PIN SCI12_SSDA12 P81 PDL_SCI_PIN SCI12 SCK12_PB7 ace PDL_SCI_PIN SCI12_SCK12 P82 PDL_SCI_PIN SCI12 CTS12 PB4 nee PDL_SCI_PIN SCI12_CTS12 PE1 PDL_SCI_PIN SCI12_RTS12 PB4 Saas PDL_SCI_PIN SCI12_RTS12 PE1 PDL SCI PIN SCI12 5512 PB4 e PDL_SCI_PIN SCI12_SS12 PE1 True if all parameters are valid and exclusive otherwise false SCl R_SCI_Create Before calling R_SCI_Create call this function to configure the relevant pins e Please refer to the Multifunction Pin Controller MPC section in the RX63T Hardware Manual for details of SCI pin selection e Pins which are not used for the SCI functions may be omitted e This function configures each specified SCI pin It also disables the alternative modes on those pins Not all device packages have all of the pin options RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_defi
48. data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10 BIT SLAVE ADDRESS Specify the slave address width Repeated Start PDL SCI_IIC_ RESTART The transfer will start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that contains the data to be written Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to send the data Rev 2 11 EN ESAS Page 253 of 418 RX6
49. data5 The storage location for the number of characters that are have been received in the current reception process Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available Return value True if all parameters are valid and the operation completed false if a parameter was out of range or the RX pin has not been selected by using the R_SCI_Set and or R_SCI_Create functions Category SCI R20UT2201EE0211 Rev 2 11 EN ESAS Page 260 of 418 Sept 12 2014 RX63T Group 4 Library Reference Reference R_SCI_Receive R_SCI_Set Remarks The error flags are not modified by this function They are cleared when a new reception process is started Program example RPDL definitions tinclude r_pdl_sci h RPDL device specific definitions tinclude r_pdl_definitions h uint8_t StatusValue uint16_t TxChars uint16_t RxChars void func void Read the status of SCI channel 0 R_SCI_Get Status 0 amp StatusValue PDL_NO_PTR amp TxChars amp RxChars R20UT2201EE0211 Rev 2 11 RENESAS Page 261 of 418 Sept 12 2014 RX63T Group 4 2 20 1 R_IIC_Create Synopsis Prototype Description 1 3 R20UT2201EE0211 Sept 12 2014 Rev 2 11 12C Bus Interface 12C channel setup bool R_IIC_Create uint8_t data1 uint32_t data2 ui
50. include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Configure ANOOO R_ADC_12_CreateChannel 0 0 PDL_ADC_12_CH_GROUP_A PDL_ADC_12_CH_ADSSTR_CALCULATE PDL_NO_DATA 5E 6 PDL_NO_FUNC PDL_NO_DATA i R20UT2201EE0211 Rev 2 11 ENESAS Page 306 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 R_ADC 12 Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Shut down the ADC unit bool R_ADC_12 Destroy uint8 tdata ADC unit selection Put the ADC including the Comparator into the Power down state with minimal power consumption data Select the ADC unit to be shut down For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 True if a valid unit is selected otherwise false 12 bit ADC R_ADC_12 CreateUnit This function includes a 1 ms delay to allow the ADC to stop any current scan cycle RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the ADC 0 unit R_ADC_12_Destroy 0 Y Rev 2 11 EN ESAS Page 307 of 418 RX63T Group 4 Library Reference 5 R_ADC 12 Control Synopsis Start or
51. include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void Assign a handler for group 12 R_INTC_CreateGroup 12 CallBackFunc 10 3 R20UT2201EE0211 Rev 2 11 EN ESAS Page 76 of 418 Sept 12 2014 RX63T Group 4 Library Reference 12 R_INTC_ControlGroup Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Control an interrupt request group bool R_INTC_ControlGroup uint8_t data1 Group selection uint8_t data2 Interrupt control operation uint32_tdata3 Interrupt source selection Control an interrupt request group data1 The interrupt request group n to be configured For 64 and 48 pin packages n must be 12 for other pin packages n can be 0 or 12 data2 The logical operations to be applied to the interrupt request group If multiple selections are required use to separate each selection PDL_INTC_GROUP_DISABLE Disable the interrupt requests Clear the interrupt request flags This option does not PDL_INTC_GROUP_CLEAR exist in group 12 PDL_INTC_GROUP_ENABLE Enable the interrupt requests data3 Choose the peripheral interrupt request sources for the group specified in parameter data1 to be
52. 4 R_IO_PORT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read data from an I O port bool R_IO_PORT_Read uint16_t data1 Port or port pin selection uint8_t data2 Pointer to the variable in which the value shall be stored Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value will be between 0x00 and OxFF for a port O or 1 for a pin If the I O port specification is incorrect false is returned otherwise true is returned I O port R_IO_PORT_Set If an invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions tinclude r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of port pin P22 R_IO_PORT_Read PDL_IO_PORT_2_ 2 amp data i Get the value of port 4 R_IO_PORT_Read PDL_IO_PORT_4 data R20UT2201EE0211 Rev 2 11 EN ESAS Page 86 of 418 Sept 12 2014 RX63T Group 4 Library Reference 5 R_IO_PORT_Write Synopsis Prototype Description Ret
53. 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 12F 234 Teheran ro Gangnam Ku Seoul 135 920 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2014 Renesas Electronics Corporation All rights reserved Colophon 3 0 RX63T Group ENESAS Renesas Electronics Corporation R20UT2201EE0211
54. ICBRH value ICBRL value Rev 2 11 EN ESAS Page 263 of 418 RX63T Group Description 3 3 4 Library Reference data8 Rise and fall time compensation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use 0 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 b31 b16 b15 b0 The SCL rise time in nanoseconds The SCL fall time in nanoseconds Valid from 0 to 65535 Valid from 0 to 65535 True if all parameters are valid exclusive and achievable otherwise false 12C R_CGC_Set Function R_CGC_Set must be called with the current clock source selected before using this function This function configures each l C pin that is required for operation It also disables the alternative modes on those pins The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO 7 7 bit address b15 b11 b10 b1 bO 10 bit address Channel 1 is supported on 120 pin 144 pin packages only The timing limits depend on the frequency of the internal reference clock IRC 1 tse t an UCBRH Dtree CBRL Dt rc The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH ICBRL 31 Transfer _ rate When the digital noise filter circuit is enable
55. If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required 4 Library Reference Input configuration selection High impedance control High impedance control for MTU67 and GPT67 Output pin selection Output short detection and response PDL_POE_0 MODE EDGE or PDL_POE_0 MODE LOW 8 or PDL_POE_0 MODE LOW_16 or PDL_POE 0 MODE LOW_128 PDL POE 4 MODE EDGE or PDL_POE_4 MODE LOW 8 or PDL POE 4 MODE LOW 16 or PDL_POE 4 MODE LOW _128 PDL_POE 8 MODE EDGE or PDL POE 8 MODE LOW 8 or PDL POE 8 MODE LOW 16 or PDL_POE 8 MODE LOW 128 PDL_POE_10_MODE_EDGE or PDL_POE_10_MODE_LOW_8 or PDL_POE_10_MODE_LOW_16 or PDL_POE 10 MODE_LOW_128 PDL_POE_11 PDL_POE_11 PDL_POE_11_MODE PDL_POE_11_MODE_LOW_128 MODE MODE EDGE or LOW_8 or LOW_16 or PDL_POE_12_MODE_EDGE or PDL_POE_12_MODE_LOW_8 or PDL_POE_12_MODE_LOW_16 or PDL_POE 12 MODE LOW_128 For each pin of POEO POE4 POE8 POE10 POE11 and POE12 select falling edge or low level for 16 samples at PCLK 8 16 or 128 Pin selection PDL_POE_PIN_POE10_PE2 or PDL_POE_PIN_POE10_PE4 Select the PE2 or PE4 pin for POE10 Not required if input POE10 is disabled data2 High impedance control selections If multiple selections are required use to separate eac
56. PDL_DTC_TRIGGER_GPTBO or PDL_DTC_TRIGGER_GPTB1 or PDL_DTC_TRIGGER_GPTB2 or PDL_DTC_TRIGGER_GPTB3 or PDL_DTC_TRIGGER_GPTB4 or PDL_DTC_TRIGGER_GPTB5 or PDL_DTC_TRIGGER_GPTB6 or PDL_DTC_TRIGGER_GPTB7 or Compare match or input capture B on GPT channel n n 0 to 7 PDL_DTC_TRIGGER_GPTCO or PDL_DTC TRIGGER GPTC1 or PDL_DTC TRIGGER _GPTC2 or PDL_DTC_TRIGGER_GPTC3 or PDL_DTC_TRIGGER_GPTC4 or PDL_DTC_TRIGGER_GPTC5 or PDL_DTC_TRIGGER_GPTC6 or PDL_DTC_TRIGGER_GPTC7 or Compare match C or D on GPT channel n n 0 to 7 PDL_DTC_TRIGGER_GPTEO or PDL_DTC_TRIGGER_GPTE1 or PDL_DTC_TRIGGER_GPTE2 or PDL_DTC_TRIGGER_GPTES3 or PDL_DTC_TRIGGER_GPTE4 or PDL_DTC_TRIGGER_GPTE5 or PDL_DTC_TRIGGER_GPTEE6 or PDL_DTC_TRIGGER_GPTE7 or Compare match E or F on GPT channel n n O to 7 PDL_DTC_TRIGGER_GPTVO or PDL_DTC_TRIGGER_GPTV1 or PDL_DTC_TRIGGER_GPTV2 or PDL_DTC_TRIGGER_GPTV3 or PDL_DTC_TRIGGER_GPTV4 or PDL_DTC_TRIGGER_GPTV5 or PDL_DTC_ TRIGGER GPTV6 or PDL_DTC_TRIGGER_GPTV7 or Counter limit match V on GPT channel n n O to 7 PDL_DTC_TRIGGER_LOCOIO or PDL_DTC_TRIGGER_LOCOI4 or LOCO count function event PDL_DTC_TRIGGER_SCIO_RX or PDL_DTC_TRIGGER SCI1_RX or PDL_DTC_TRIGGER SCI2_RX or Receive buffer full on SCI channel n PDL_DTC_TRIGGER_SCI3_RX or PDL_DTC_TR
57. PDL_MTU3_BUFFER_DOUBLE_DISABLE or PDL_MTU3_ BUFFER DOUBLE ENABLE Disable or enable the double buffer function Control the cycle set buffer transfer timing Valid for n 4 and 7 PDL_MTU3_CSB_DISABLE or PDL_MTU3_CSB_CREST or PDL_MTU3_CSB_TROUGH or PDL_MTU3 CSB BOTH Select no transfer transfer on crest detection transfer on trough detection or transfer on crest and trough detection PDL_MTU3_CSB_TROUGH and PDL_MTU3_CSB_BOTH are available only in complementary PWM mode Buffer operation PDL_MTU3_BUFFER_AC_DISABLE or PDL_MTU3_BUFFER_AC ENABLE Disable or enable buffer operation for registers TGRA and TGRC Valid for n 0 3 4 6 and 7 PDL_MTU3_BUFFER_BD_DISABLE or PDL_MTU3 BUFFER _BD ENABLE Disable or enable buffer operation for registers TGRB and TGRD Valid for n 0 3 4 6 and 7 PDL_MTU3_BUFFER_EF_ DISABLE or PDL_MTU3_BUFFER_EF ENABLE Disable or enable buffer operation for registers TGRE and TGRF Valid for n 0 Buffer data transfer Valid in PWM mode PDL_MTU3_BUFFER_AC_CM_A or PDL_MTU3_BUFFER_AC_TCNT_CLR Transfer the data from TGRC to TGRA when a compare match A occurs or when TCNT is cleared in each channel Valid for n 0 3 4 6 and 7 PDL_MTU3_BUFFER_BD_CM Bor PDL_MTU3_BUFFER_BD_TCNT_CLR PDL_MTU3_BUFFER_EF_CM_E or PDL_MTU3_BUFFER_EF_TCNT_CLR Transfer the data from TGRD to TGRB when a compare match B occurs or when TCNT is cleared in each
58. PDL_POE_SHORT_P71_HIGH PDL_POE_SHORT_P7X_H1_Z i ENESAS Page 183 of 418 RX63T Group 2 R_POE Create Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Rev 2 11 4 Library Reference Configure the Port Output Enable event handling bool R_POE_Create uint16_t data1 void funci Callback function void func2 Callback function void func3 Callback function void func4 Callback function void func5 Callback function uint8_t data2 Interrupt priority level Input configuration selection Enable interrupts and register callback functions data1 Interrupt selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e High impedance request response PDL_POE_IRQ_HI_Z_0_DISABLE or PDL_POE _IRQ_HI_Z 0 ENABLE Disable or enable an interrupt on detection of any high impedance request on pin POEO PDL_POE_IRQ_HI_Z_4 DISABLE or PDL_POE_IRQ_HI_Z_4 ENABLE Disable or enable an interrupt on detection of any high impedance request on pin POE4 PDL_POE_IRQ_HI_Z_8 DISABLE or PDL_POE_IRQ_HI_Z_8 ENABLE Disable or enable an interrupt on detection of any high impedance request on pin POE8 PDL_POE_IRQ_HI_Z_10_DISABLE or PDL_POE_IRQ_HI_Z_10 ENABLE PDL_POE_IRQ_HI_Z_11_DISABLE or PDL_POE_IRQ_HI_Z
59. Parameter data3 contains the frequency of the signal applied to this pin PDL_CAC_CACREF_FILTER_DISABLE or PDL_CAC_CACREF_FILTER_DIV_1 or PDL_CAC_CACREF_FILTER_DIV_4 or PDL_CAC_CACREF_FILTER_DIV_16 If used the CACREF signal can be unfiltered or sampled using the clock to be measured divided by 1 4 or 16 ENESAS Page 106 of 418 RX63T Group Description 2 2 Return value 4 Library Reference data3 If the CACREF input will be used specify the input clock frequency in Hz Use PDL_NO_DATA if not required data4 Specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 data5 Specify either a the maximum negative deviation for the measured clock as a percentage or b the lower count limit for the measured clock where the maximum value is 65535 func1 The function to be called if a frequency error is detected Specify PDL_NO_FUNC if not required func2 The function to be called when the measurement has ended Specify PDL_NO_FUNC if not required func3 The function to be called if the measurement counter overflows Specify PDL_NO_FUNC if not required data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_ FUNC is specified for parameters func
60. Program example RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure for the selected channel R_MTU3_ControlChannel_structure ch3_parameters Set the control options for channel 3 ch3_parameters control_setting PDL_MTU3_START ch3_parameters register_selection PDL_MTU3_REGISTER_COUNTER PDL_MTU3_REGISTER_TGRB ch3_parameters TCNT_TCNTU_value OxFFDD ch3_parameters TGRB_TCNTW_value 0x0020 Modify the operation of channel 3 R_MTU3_ControlChannel 3 amp ch3_parameters R20UT2201EE0211 Rev 2 11 AS Page 169 of 418 Sept 12 2014 RENES RX63T Group 5 R_MTU3_ControlUnit Synopsis Prototype uint8_t data1 R_MTU3_ControlUnit_structure ptr Control a Multi function Timer Pulse Unit bool R_MTU3_ControlUnit R_MTU3_ControlUnit_structure members uint16_t simultaneous_control uint16_t pair_control uint32_t BDCM_sync_conirol uint32_t output_control uint32_t buffer_control uint32_tint_skip_control uint16_t DT_data_value uint16_t data_value uint16_t buffer_value Description 1 6 R20UT2201EE0211 Sept 12 2014 data1 The unit number n where n 0 Modify a timer unit s registers simultaneous_control Simultaneous stop start control All selections ar
61. Program example Shut down a SCI channel bool R_SCI_Destroy uint8 tdata Channel selection Stop data flow and shutdown the selected SCI channel data The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages True if all parameters are valid otherwise false SCI None The SCI channel is put into the power down state RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SCI channel 1 R_SCI_Destroy 1 R20UT2201EE0211 Rev 2 11 EN ESAS Page 243 of 418 Sept 12 2014 RX63T Group 4 R_SCI_Send Synopsis Prototype Description Return value Category Reference R20UT2201EE0211 Sept 12 2014 4 Library Reference Transmit data on a SCI channel bool R_SCI_Send uint8_t data1 uint16_t data2 uint8_t data3 uint16_t data4 void func Channel selection Channel configuration and Target Station ID Data start address Data count Callback function Transmit data on the specified serial channel data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Control options The default options are shown in bold Specify PDL_NO_DATA t
62. RRAY_2_SIZE 2 Array size written sub address byte last byte DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA Read data from the EEPROM using the DMAC read_eeprom_data static void write_eeprom_data void bus_busy true Send data EPROM using the DMAC if false de terSend TIC_CHANN PDL_IIC_DMAC_TRIGGER_ENABL EEPROM_ADDRESS PDL_NO_PTR 0 PDL_NO_FUNC 0 while 1 while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 5E 3 PDL_NO_FUNC 0 Y static void read_eeprom_data void bus_busy true Read data from the EEPROM using the DMAC if false R_IIC_MasterReceive IIC_CHANNEL PDL_IIC_DMAC_TRIGGER_ENABL PROM_ADDRESS DL_NO_PTR PDL_NO_FUNC 1 while 1 while bus_busy true void iic_tx_dmac_end_handler void uint32_t status_flags 0 Wait for the transmission to complete do R20UT2201EE0211 Rev 2 11 RENESAS Page 395 of 418 Sept 12 2014 RX63T Group 5 Usage Examples R_IIC_GetStatus IIC_CHANNEL status_flags PDL_NO_PTR PDL_NO_PTR Y while status_flags 0x0080u 0x0u Issue a Stop condition R_IIC_ Control IIC_CHANNEL PDL_IIC_STOP bus_busy false
63. RX63T Group 4 Library Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 The fast interrupt processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector used in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_IRQ2 This will direct the compiler to generate the instructions required for a fast interrupt vector This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 Y Remember to edit r_pdl_user_definitions h see remark 2 Rev 2 11 ENESAS Page 64 of 418 RX63T Group 4 Library Reference 5 R_INTC_CreateExceptionHandlers Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Assign handlers for the fixed vector interrupts bool R_INTC_CreateExceptionHandlers
64. SCIEr i while data_received false data_received false Receive data ID 0x0A by CPU R_SCI_Receive CHANNEL SCI PDL_NO_DATA receive_data 10 SCIrx SCIEr Y while data_received fals Async MP mode data Reception by polling id_received fals Wait by polling until receive matching Station ID 0x01 id_received R_SCI_Receive CHANNEL_SCI 0x0100 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC SCIEr if id_received true Receive data ID 0x01 by polling R_SCI_Receive CHANNEL_SCI PDL_NO_DATA receive_data 10 PDL_NO_FUNC SCIEr void SCIrx void data_received true void SCIEr void error_happen true Figure 5 25 Example of SCI Reception code in Asynchronous Multi Processor mode R20UT2201EE0211 Rev 2 11 RENESAS Page 378 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 7 SCI Transmission in Asynchronous Multi Processor mode This shows the setting of a SCI channel and the Multi Processor mode transmission of data using interrupts and polling PDL functions include r_pdl_sci h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h void SCItx void uint8_t send_data0 Welcome to the Renesas RX63T uint8_t send_data testing ASYNC MP mode bool tx_end void main void Initialise the
65. Valid when n 1 PDL_MTU3_PIN_1B_PA4 PDL_MTU3_PIN_1A_PA5 Select the PAS pin for MTIOC1A Select the PA4 pin for MTIOC1B Valid when n 2 PDL_MTU3_PIN_2A PA3 Select the PA3 pin for MTIOC2A PDL_MTU3 PIN 2B PA2 Select the PA2 pin for MTIOC2B e Valid when n 3 PDL_MTU3_PIN_3A_P33 Select the P33 pin for MTIOC3A PDL_MTU3 PIN 3B P71 Select the P71 pin for MTIOC3B PDL_MTU3_PIN_3C_P32 Select the P32 pin for MTIOC3C PDL_MTU3_PIN_3D _P74 Select the P74 pin for MTIOC3D Valid when n 4 PDL_MTU3 PIN 4A P72 Select the P72 pin for MTIOC4A PDL_MTU3_PIN_4B_ P73 Select the P73 pin for MTIOC4B PDL_MTU3_PIN_4D_P76 PDL_MTU3_PIN_4C_P75 Select the P75 pin for MTIOC4C Select the P76 pin for MTIOC4D e Valid when n 5 PDL_MTU3_PIN_5U_P24 or PDL _MTU3 PIN _5U P82 Select the P24 or P82 pin for MTIOC5U PDL_MTU3_PIN_5V_P23 or PDL_MTU3_PIN_5V_P81 Select the P23 or P81 pin for MTIOC5V PDL_MTU3_PIN_5W_P22 or PDL_MTU3_PIN_5W_P80 Select the P22 or P80 pin for MTIOC5W e Valid when n 6 PDL_MTU3_PIN_6A_P33 or PDL_MTU3_PIN_6A_PA1 Select the P33 or PA1 pin for MTIOC6A PDL_MTU3_PIN_6B_P71 or PDL_MTU3_PIN_6B_P95 Select the P71 or P95 pin for MTIOC6B PDL_MTU3_PIN_6C_P32 or PDL_MTU3_PIN_6C_PAO Select the P32 or PAO pin for MTIOCEC PDL_MTU3_PIN_6D_P74 or
66. or by internal polling operation without specifying func1 For Data reception it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to the usage example in Section 5 17 6 For the ID cycle the DMAC DTC trigger control will be ignored In synchronous mode if both the Tx Data and the Rx Data pins have been enabled when R_SCI_Create was called then a reception must be performed in conjunction with a corresponding transmission This is achieved by calling R_SCI_ Receive in non polling mode and then R_SCI_ Send Please refer to the usage example in Section 5 17 5 Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_ Read If using the DMAC or DTC this module does not know when the reception has ended Therefore when it has completed the user must call the R_SCl_ Control function with option PDL_SCI_STOP_RX to manually disable the reception If a callback function func 1 is specified and the interrupt priority level is zero this function will return false If PDL_SCI_RX_CONTINUOUS_ENABLE is selected when next group of data is received after callback frunction the data will be stored to the top of receive buffer data3 Rev 2 11 EN ESAS Page 248 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include
67. to return to the main HEW window R20UT2201EE0211 Rev 2 11 RENESAS Page 6 of 418 Sept 12 2014 RX63T Group 1 Introduction 5 Include the new source files Use the key sequence Alt P A to open the Add files to project lt your project gt window Double click on the RPDL folder From the Files of type drop down list select C source file C Use the key sequence Cirl A to select all of the files as shown below Look in Ji RPDL e Ee c Interrupt_ADC_12 c Interrupt_IIC c c Interrupt_BSC c c Interrupt_INTC c c Interrupt_CAC c c Interrupt MTU3 c c Interrupt_CMT c c Interrupt_not_RPDL c c Interrupt DMAC c C Interrupt_POE c c Interrupt_DOC c le Interrupt_SCl c c Interrupt_GPT c i a File name interupt_SPl c Interupt_ADC_12 c Interupt_BSC c Interup Files of type C source file C y Cancel IV Relative Path Click on Add Click on OK to return to the main HEW window 6 Peripherals that are not required If a peripheral module is not required the interrupt handler file does not need to be included If the unused interrupts still require entries in the interrupt vector table edit the file Interrupt_not_RPDL c to uncomment the define for the unused peripherals For example tdefine RPDL_ADC_12_ not_used Becomes define RPDL_ADC_12_not_used The file Interrupt_INTC c must be included 7 Peripherals that are not
68. void iic_rx_dmac_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR PDL_NO_PTR i Read one more byte with NACK condition and stop R_IIC_MasterReceiveLast IIC_CHANNEL uint8_t DestAddr i bus_busy false Figure 5 38 An example of writing data to and reading data from an EEPROM using two DMAC channels R20UT2201EE0211 Rev 2 11 RENESAS Page 396 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 18 3 Master mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer The same EEPROM address locations are then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h tinclude r_pdl_cmt h include r_pdl_dtc h RPDL device specific definitions tinclude r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx end _handler void void iic rx end handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM_MEMORY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPPER define IIC_CHANNEL 0 volatile uint
69. 0 PDL_ADC_10_SCAN_SINGLE PDL_ADC_10_TRIGGER_SOFTWARI 0 PDL_NO_FUNC 0 Configure sampling time for AN0 R_ADC_10_CreateChannel 0 0 PDL_ADC_10_CH_VALUE_ADDITION_DISABLI 5E 6 Y Wait 10 ms for the ADC to stabilise R_CMT_CreateOneShot 0 0 10E 3 PDL_NO_FUNC PDL_NO_DATA Start conversion on the ADC R_ADC_10_Control PDL_ADC_10_0_ON Fetch the results R_ADC_10_Read 0 adc_results amp diag_result Shut down ADC R20UT2201EE0211 Rev 2 11 RENESAS Page 410 of 418 Sept 12 2014 RX63T Group 5 Usage Examples R_ADC_10_Destroy Figure 5 44 Example of ADC_10 R20UT2201EE0211 Rev 2 11 RENESAS Page 411 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 23 10 bit Digital to Analog Converter Figure 5 45 shows an example of DAC_10 usage Peripheral driver function prototypes tinclude r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void main void Test normal DAC_10 operation VREF 5 0V Expected output voltages are shown in comments Test align right default R_DAC_10_Create PDL_DAC_10_CHANNEL_1 0x0 0x0 0 0V Write new data to both DAC channels R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0x0 0x200 ff 25V Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_CHA
70. 0 PDL_ADC_12_CH_SAMPLE_AND_HOLD PDL_NO_DATA 5E 6 P P DL_NO_FUNC DL_NO_DATA Wait 10 ms for the ADC to stabilise R_CMT_CreateOneShot 0 0 10E 3 PDL_NO_FUNC PDL_NO_DATA Y Start Trigger the ADC R_ADC_12 Control PDL_ADC_12_0_ON R20UT2201EE0211 Rev 2 11 RENESAS Page 408 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Fetch the results R_ADC_12_Read 0 adc_results PDL_NO_DATA PDL_NO_DATA 3 Shut down ADC R_ADC_12_Destroy Figure 5 43 Example of ADC_12 R20UT2201EE0211 Rev 2 11 EN ESAS Page 409 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 22 10 bit Analog to Digital Converter Figure 5 44 shows ADC_10 used in single scan mode with a software trigger and a specified sampling time Peripheral driver function prototypes include r_pdl_adc_10 h include r_pdl_cmt h include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h Array used to read the ADC results uint16_t adc_results 20 uintl6_t diag_result void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure analog input for ANO R_ADC_10_Set PDL_ADC_10_PIN_ANO_P60 Configure ADC in single scan mode R_ADC_10_CreateUnit
71. 2014 4 Library Reference data10 Negate and Dead time control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Negate control selection PDL_GPT_NEGATE_A_DISABLE or PDL_GPT_NEGATE_A_LOW or PDL_GPT_NEGATE_A_HIGH Disable negate operation or set the negate state for pin GTIOCnA PDL_GPT_NEGATE_B_DISABLE or PDL_GPT_NEGATE_B_LOW or PDL_GPT_NEGATE B HIGH Disable negate operation or set the negate state for pin GTIOCNB PDL_GPT_NEGATE_ANO00 or PDL_GPT_NEGATE_ANO01 or PDL_GPT_NEGATE_AN002 or PDL_GPT_NEGATE_AN100 or PDL GPT NEGATE AN101 or If negate operation is enabled select the negate PDL_GPT_NEGATE_AN102 or oe PDL_GPT_NEGATE_GTETRGO or PDL_GPT_NEGATE_GTETRG1 or PDL_GPT_NEGATE_SOFTWARE PDL_GPT_NEGATE_0 or If negate operation is enabled select operation when PDL_GPT_ NEGATE 1 the source becomes 0 or 1 e Dead time control selection Ignored in saw wave PWM mode PDL_GPT_DEAD_TIME_DISABLE or Disable or enable dead time PDL_GPT_DEAD_TIME_ENABLE control PDL_GPT_DEAD_TIME_UP_BUFFER_DISABLE or Disable or enable buffer PDL_GPT_DEAD_TIME_UP_BUFFER_ENABLE operation for up counting Disable or enable buffer operation for down counting or select loading of the up counting value PDL_GPT_DEAD_TIME_DOWN_BUFFER_DISABLE or PDL_GPT_DEAD_TIME_DOWN_ BUFFER ENABLE or PDL
72. 3 2 2 PDL_NO_PTR Used as a parameter when there is no applicable data location 3 2 3 PDL_NO_DATA Used as a parameter when there is no applicable data value 3 2 4 PDL_MCU_GROUP The MCU group supported by this build of the driver library It is defined as RX63T A usage example is if PDL_MCU_GROUP RX63T terror Wrong RPDL tendif 3 2 5 PDL_VERSION The version number of the RPDL library The number is stored in BCD format xx xx For example 0100h is v1 00 A usage example is const uint16_t rpdl_version_number PDL_VERSION 3 2 6 Bit definitions The definitions BIT_n and INV_BIT_n where n 0 to 31 are available to the user R20UT2201EE0211 Rev 2 11 AS Page 45 of 418 Sept 12 2014 RENES RX63T Group 4 Library Reference 4 Library Reference 4 1 API List by Peripheral Function Table 4 1 lists the Renesas Embedded APIs by peripheral function Table 4 1 Renesas Embedded API List Category Number Name Description Clock 1 R_CGC_Set Configure the clock generation circuit Generation 2 R_CGC_Control Modify the clock generation circuit operation Circuit 3 R_CGC_GetStatus Read the status of the clock generation circuit 1 R_INTC_SetExtInterrupt Select the external interrupt pins 2 R_INTC_CreateExtInterrupt C
73. 300 311 Feb 01 2013 395 396 128 130 267 279 389 110 118 335 61 62 78 82 122 130 104 R20UT2201EE0211 Rev 2 11 Sept 12 2014 Revision History Description Date Summary Corrected the equation for achievable PLL frequencies R_CGC_Control Added support for packages with 100 pins or more I O Port Added support for packages with 100 pins or more R_IO_PORT_Set Added support for packages with 100 pins or more R_IO_PORT_ReadControl Added support for packages with 100 pins or more R_IO_PORT_ModifyControl Added support for packages with 100 pins or more R_LVD_Create Added voltage level configuration for packages with 100 pins or more R_POE_Set Updated the description for data4 R_SCI_Set Added extra pin definitions availble on larger pin packages SCI Added support for the extra channels availble on larger pin packages ADC_12 Added unit for packages with 100 pins or more R_RWP_Control Update description for Register write control option in data1 R_RWP_GetStatus Update data1 data2 description Change PDL_NO_DATA to PDL_NO_PTR DAC_10 Added description for overview DAC_10 Added description for R_DAC_10 Create R_DAC_10_Destroy R_DAC_10 Write DAC_10 Added detail for R_DAC 10 Create R_DAC 10 Destroy R_DAC_10 Write DAC_10 Added the program example Update DMAC usage examples to be compatible with RSK ADC_10 Added description for overview ADC_10 Added description for R_ADC_10_Contr
74. DESTO szecitsunet A Ba lente ei els ae ee E 293 R CRGEWitte ta A nen i ih i en ee Ieee 294 RiGRG Read iia ti DIOSA ets eta A a ie es 295 12 bit Analog to Digital Converter cccccecceeeceeceneeeeeaeeeeeee cents ceaeeeeaaeseeeeeeeeeeseaeeesaeeseeeseneees 296 RADO 122 Sc AN A SS 296 R ADC 12 Create Uli A A A E 297 RADO 1 2 CreateChannel Ac were cnt a A ae ida 304 RADCU12 DESUIO Y reiii a a a ai fii testes Mee AAA ii ons Restarts 307 RADO 12 CONO e A A A ad a 308 5 6 RZADG 12 R di hie Raveena den Ge Ai A ail ind evn 310 4 2 24 10 bit Analog to Digital Converter ceccceccseeeeeeceeeeeeeaeeeeeae scenes seaeeeeaaeeeeeeseeeeeseaeeesaeeseneeseaees 312 1 RADCA TO Setii e E Ava DE a E vies 312 2 RU ADGC 10 Created ali A a A IA a 314 3 ReADG 1 02CreateC Meliana A A da a lah 318 4 RAUC IA NA O 320 5 READ TO CONTO La dE A a a Da EA 321 6 DAA O iera dee edna dada a A epee nn ae a 322 4 2 25 10 bit Digital to Analog Converter eeccceccseeeseeceeeeecaeeeeaeeseeeeeceaeeeeaaeeseeeseeeeeseaeeesaeeseneeenaees 323 1 RADAG HAO Create ii A A A A A SS 323 7 A A A queeveatey d a ge 325 3 R DAC 10 Write ctra yen ences dea ta a ana deena 326 42 26 Data Operati0hGIrCUlt scsi pati 327 1 Re DOG Create tepcitadas atada sida cid 327 21 Ae DOG Des ita dada 329 3 Re DOG Coto liar atado ici 330 A Re DOG A iii tai 332 5 REDOG Wisteria E iii did 333 Usage vEXain pl OS vico lla lila iia
75. High 1 Rising 1 Detected True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_ControlExtInterrupt Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS e The MPC registers are used to determine which pin is used for IRQn e If this function is called from within a callback function the input detection status will be 0 Clear the NMI status flags using R_INTC_ControlExtInterrupt RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t irq_status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_IRQ5 amp irq_status Y Page 68 of 418 RX63T Group The INTC Read Write and Modify functions use one of the following register definitions 4 Library Reference IR register definitions Some IR registers are not existed in 64 and 48 pin packages Refer to Hardware manual section 15 Interrupt controller Table 15 3 Interrupt Vector Table for details
76. Input capture or compare match with MTU7 TGRA or in PDL_ADC_ 12 GP_TRIGGER_MTU3_TRGA7N or complementary PWM mode an underflow of MTU7 TCNT in the trough Compare match with PDL_ADC_12 GP_TRIGGER_MTU3_TRGON or MTUO TGRE Compare match between PDL_ADC_ 12 GP_TRIGGER_MTU3_TRG4AN or MTU4 TADCORA and MTU4 TCNT Compare match between PDL_ADC_12 GP_TRIGGER_MTU3_TRG4BN or MTU4 TADCORB and MTU4 TCNT Compare match between MTU4 TADCORA and PDL_ADC_ 12 GP_TRIGGER_MTU3_TRG4AN_4BN or MTU4 TCNT or between MTU4 TADCORB and MTU4 TCNT Compare match between MTU4 TADCORA and MTU4 TCNT or between MTU4 TADCORB and MTU4 TCNT when interrupt skipping function 2 is in use Compare match between PDL_ADC_12_GP_TRIGGER_MTU3_TRG7AN or MTU7 TADCORA and MTU7 TCNT Compare match between PDL_ADC_12_GP_TRIGGER_MTU3_TRG7BN or MTU7 TADCORB and MTU7 TCNT Compare match between MTU7 TADCORA and PDL_ADC_12_GP_TRIGGER_MTU3_TRG7AN_7BN or MTU7 TCNT or between MTU7 TADCORB and MTU7 TCNT Compare match between MTU7 TADCORA and MTU7 TCNT and between MTU7 TADCORB and MTU7 TCNT when interrupt skipping function 2 is in use PDL_ADC_12 GP_TRIGGER_MTU3_TRG4ABN or PDL_ADC_12 GP_TRIGGER_MTU3_TRG7ABN R20UT2201EE0211 Rev 2 11 RENESAS Page 299 of 418 Sept 12 2014 RX63T Group Description 4 6 DTC DMAC trigger control 4 Library Reference R20UT2201EE0211 Rev 2 11 Sept 12 2014 PDL_ADC_12 GP_DMA
77. One channel is used to generate interrupts at regular intervals Peripheral driver function prototypes include r_pdl_cmt h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t Flags uint16_t Counter Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL O0 Configure a port pin for output R_IO_PORT_Set PDL_IO_PORT_7_1 PDL_1O_PORT_OUTPUT R_IO_PORT_Set PDL_IO_PORT_7_2 PDL_1O_PORT_OUTPUT f R_IO_PORT_Write PDL_IO_PORT O off LEDO _1_1 R_IO_PORT_Write PDL_IO_PORT_7_2 0 on LED1 Configure CMT channel 0 for 1kHz operation but not start CMT first R_CMT_Create 0 PDL_CMT_FREQUENCY PDL_CMT_STOP 1E3 CMTO_handler 15 y Configure CMT channel 1 in 0 1sec period and start CMT R_CMT_Create 1 PDL_CMT_PERIOD 1E 1 CMT1_handler 15 Y Change the frequency to 10kHz R_CMT_Control 0 PDL_CMT_FREQUENCY 10E3 R_CMT_Read 0 PDL_NO_PTR PDL_NO_PTR R_CMT_Read 1 Flags Counter Wait for 0 5sec R_CMT_CreateOneShot 2 PDL_NO_DATA 0 5 PDL_NO_
78. PDL_DTC_UPDATE SOURCE a ae Address register using parameter PDL_DTC_UPDATE DESTINATION e Address register using parameter PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE The Block Size register using parameter data6 e Transfer trigger control When the transfer count specified in R_DTC_Create is completed the DTC will ignore further interrupts from that trigger source If you require the interrupt to trigger another transfer specify the trigger used in the relevant call of R_DTC_Create data2 If transfer registers are to be modified specify the start address of the transfer data area the same as that declared in R_DTC_Create If no registers are to be modified specify PDL_NO_PTR data3 The new source start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data4 The new destination start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data5 The new number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers Specify PDL_NO_DATA if not required data6 The new size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode Specify PDL_NO_DATA if not required True if a
79. PDL_INTC_IRQO_P10 or PDL_INTC_IRQO_PE5 or PDL_INTC_IRQO_PGO PDL_INTC_IRQ1_P11 or PDL_INTC_IRQ1_PE4 or PDL_INTC_IRQ1_PG1 PDL_INTC_IRQ2_PE3 or PDL_INTC_IRQ2_PB6 or PDL_INTC_IRQ2_PG2 PDL_INTC_IRQ3_PB4 or PDL_INTC_IRQ3_P34 or PDL_INTC_IRQ3_ P82 Select the pins to be used for signals IRQO to IRQ7 for 144 PDL_INTC_IRQ4 P96 or 120 112 and 100 pin packages PDL_INTC_IRQ4_PB1 or PDL_INTC_IRQ4 P24 PDL_INTC_IRQ5_P70 or PDL_INTC_IRQ5_PF2 or PDL_INTC_IRQ5_ P80 PDL_INTC_IRQ6_P21 or PDL_INTC_IRQ6_PD5 or PDL_INTC_IRQ6_PG4 PDL_INTC_IRQ7_P20 or PDL_INTC_IRQ7_P03 or PDL_INTC_IRQ7_PEO True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_CreateExtInterrupt Rev 2 11 ENESAS Page 56 of 418 RX63T Group 4 Library Reference Remarks Before calling R_INTC_CreateExtInterrupt call this function to select the required pins The Multifunction Pin Control registers are modified to enable each selected IRQ pin and the 1 0 Port PMR and PDR registers are modified to set the pin as an input Apin can be used both as an interrupt input and a peripheral or general purpose input or output apart from an analog input If the dual operation is required call this function before configuring the peripheral or I O port operation Some pin options are not available on smaller device packages Some IRQ pins labelled in the hardware manua
80. PDL_MTU3_PIN_6D_P92 Select the P74 or P92 pin for MTIOC6D Rev 2 11 ENESAS Page 154 of 418 RX63T Group Description 2 2 4 Library Reference e Valid when n 7 Return value Category Reference Remarks Program Example R20UT2201EE0211 Sept 12 2014 PDL_MTU3_PIN_7A_P72 or PDL_MTU3 PIN 7A P94 PDL_MTU3_PIN 7B P73 or PDL_MTU3 PIN _7B P93 PDL_MTU3_PIN_7C_P75 or PDL_MTU3 PIN _7C_P91 PDL_MTU3_PIN_7D_P76 or PDL_MTU3_PIN_7D_P90 Select the P72 or P94 pin for MTIOC7A Select the P73 or P93 pin for MTIOC7B Select the P75 or P91 pin for MTIOC7C Select the P76 or P90 pin for MTIOC7D Valid when n 0 to 4 PDL_MTU3_ PIN CLKA_P22 or PDL_MTU3_ PIN _CLKA_PB3 or PDL_MTU3_ PIN CLKA_P33 or PDL_MTU3_PIN_CLKA P21 PDL_MTU3_ PIN CLKB_P23 or PDL_MTU3_ PIN CLKB_PB2 or PDL_MTU3_ PIN CLKB_ P82 or PDL_MTU3_ PIN _CLKB_ P20 Select the P22 PB3 P33 or P21 pin for MTCLKA Select the P23 PB2 P32 or P20 pin for MTCLKB e Valid when n 0 or 2 PDL_MTU3_PIN_CLKC_P11 or PDL_MTU3_ PIN CLKC_P24 or PDL_MTU3_ PIN CLKC_P31 or PDL_MTU3_ PIN CLKC_PE4 PDL_MTU3_PIN_CLKD_P10 or PDL MTU3 PIN CLKD P30 or Select the P10 P30 or E3 pin for MTCLKD PDL MTU3 PIN CLKD PE3 When n 2 required in Phase Counting Mode only Select the P11 P24 P31 or E4 pin for MTCLKC Tr
81. PDL_SPI_LENGTH_9 PDL_NO_DATA y Prepare the transfer with slave 2 R_SPI_Command MASTER_CHANNEL 2 PDL_SPI_CLOCK_MODE_0O PDL_SPI_LSB_FIRST PDL_SPI_ASSERT_SSL2 PDL_SPI_LENGTH_15 PDL_NO_DATA Y Prepare the transfer with slave 3 R_SPI_Command MASTER_CHANNEL 3 PDL_SPI_CLOCK_MODE_0 PDL_SPI_LSB_FIRST PDL_SPI_ASSERT_SSL PDL_SPI_LENGTH_24 PDL_NO_DATA Transfer all the data once R_SPI_Transfer R20UT2201EE0211 Rev 2 11 RENESAS Page 405 of 418 Sept 12 2014 RX63T Group MASTER_CHANNE PDL_NO_DATA master_tx_da master_rx_da 1 PDL_NO_FUNC 0 PDL_NO_FUNC Figure 5 41 Example of multiple slave Serial Peripheral Interface use R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS 5 Usage Examples Page 406 of 418 RX63T Group 5 Usage Examples 5 20 CRC calculator Figure 5 42 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes tinclude r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void main void uint16_t crc_result Configure the CRC to use the CCITT polynomial R_CRC_Create PDL_CRC_POLY_CRC_CCITT PDL_CRC_LSB_FIRST Write the payload data
82. R_BSC_CreateArea 2 PDL_BSC_WIDTH_16 PDL_BSC_WRIT 0 sy so o no NON OO 0 CO O O O 0 00 0090 Configure area 3 R_BSC_CreateArea 3 PDL_BSC_WIDTH_16 15 15 7 7 Configure the bus controller R_BSC_Create PDL_BSC_CS0_P26 PDL_BSC_CS1_PF2 PDL_BSC_CS2_PD2 PDL_BSC_CS3_P12 PDL_BSC_WAIT_P82 PDL_BSC_ALE ENABLE PDL_BSC_A9 DISABLE PDL_BSC_RCV_SRRS_ENABLE PDL_BSC_ERROR_ILLEGAL_ADDRESS_ E PDL_BSC_ERROR_TIM ENABL BSC_error_handler 5 dF Enable the bus controller R_BSC_Control PDL_BSC_ENABL Y Write to external areas R20UT2201EE0211 Rev 2 11 AS Page 350 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples cs0_location_8 0x23u csl_location_8 OxAAu cs2_location_16 0x3344u cs3_location_16 OxAA55u Disable area CS1 R_BSC_Destroy 1 This should generate an illegal address error csl_location_8 OxAAu void BSC_error_handler void Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR Y Figure 5 10 Example of Bus Controller use for the external bus R20UT2201EE0211 Rev 2 11 AS Page 351 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 9 DMA controller The following example shows the use of triggers by software and IRQ pin edge detectio
83. References Remarks Program example R20UT2201EE0211 Sept 12 2014 Configure I O port pins that are not available bool R_IO_PORT_NotAvailable void No parameter is required Set the port pins that are not available on smaller packages to the recommended state True I O port All pins that are not available on the selected package will be configured for CMOS type low level output RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable Rev 2 11 ENESAS Page 91 of 418 RX63T Group 4 2 4 Multifunction Pin Controller 4 Library Reference The peripheral functions can be assigned to different pins controlled by the Multifunction Pin Controller The definitions available to the MPC functions are listed below MPC register definitions PDL_MPC_REG_POOPFS PDL_MPC_REG_P60PFS PDL_MPC_REG_PCOPFS PDL_MPC_REG_P01PFS PDL_MPC_REG_P61PFS PDL_MPC_REG_PC1PFS PDL_MPC_REG_P02PFS PDL_MPC_REG_P62PFS PDL_MPC_REG_PC2PFS PDL_MPC_REG_P0O3PFS PDL_MPC_REG_P63PFS PDL_MPC_REG_PC3PFS PDL_MPC_REG_P10PFS PDL_MPC_REG_P11PFS PDL_MPC_REG_P64PFS PDL_MPC_REG_P65PFS PDL_MPC_REG_PC4PFS PDL_MPC_REG_PC5PFS PDL_MPC_REG_P12PFS PDL_MPC_REG_P70PFS PDL_MPC_REG_PDOPFS
84. TIC_Buffer 5 r Y R20UT2201EE0211 Rev 2 11 RENESAS Page 384 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Setup DMAC to write data to IIC Configure channel 3 of DMAC to be triggered by SCI1 Tx R_DMAC_Create 3 PDL_DMAC_REPEAT PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIXED PDL_DMAC_SIZE_8 PDL_DMAC_IRO 1 PDL_DMAC_TRIGGER_SCI1_TX IIC_Buffer Source uint8_t SCI1 TDR Dest 1 6 Data length Address in EEPROM 5 Data PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback Callback done function 7 Interrupt priority Y Enable DMAC channel 3 R_DMAC_Control 3 Pp _DMAC_ENABL L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA p P p Er RA G G U G A Clear flag data_sent false Start IIC Write R_SCI_IIC_ Write CHANNEL SCI_IIC PDL_SCI_IIC_DMAC_TRIGGER_ENABLE SLAVE_ADDRESS PDL_NO_DATA No data length as using DMAC PDL_NO_DATA No buffer as using DMAC PDL_NO_FUNC 5 Wait for write to complete while false data_sent Because using DMAC need to manually send a stop to end the transfer R SCI Control CHANNEL_SCI_IIC PDL_SCI_IIC_STOP Y Callback done static void Callback void data_sent true
85. include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h ADC callback function void ADCIntFunc void void func void Set up the ADC in single mode R_ADC_12_CreateUnit 0 PDL_ADC_12_SCAN_SINGLE PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA ADCIntFunc 2 PDL_NO_FUNC PDL_NO_DATA Rev 2 11 EN ESAS Page 303 of 418 RX63T Group 4 Library Reference 3 R_ADC 12 CreateChamnel Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Configure 12 bit ADC analog channels bool R_ADC_12_CreateChannel uint8_t data1 ADC unit selection uint8_t data2 Analog channel selection uint32_t data3 Channel configuration uint16_tdata4 Comparator configuration double data5 Sampling time void func Callback function for comparator on the channel uint8_t data6 Interrupt priority level for comparator on the channel Channel specific control Used to complement R_ADC_12_CreateUnit to configure 12 bit ADC analog channels if analog channels are selected as the input source data1 Select the ADC unit For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Select the analog input channel This must be from 0 to 7 for device packages with 48 or 64 pin otherwise 0 to 3 data3 Channel opt
86. include r_pdl_definitions h define EEPROM_ADDRESS 0xA0 void main void const uint8_t eeprom_data_array_1 5 0x00 0x01 0x02 0x03 0x04 uint8_t data_storage 5 uint32_t status_flags 0 uint16_t TxChars uint16_t RxChars Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 300 lt lt 16 200 Send the sub address and 3 bytes to the EEPROM using polling if R_IIC_MasterSend 0 PDL_NO_DATA EEPROM_ADDRESS eeprom_data_array_l 4 PDL_NO_FUNC 0 false Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags amp TxChars PDL_NO_PTR Review the flags and transmit count to decide on the next action else R20UT2201EE0211 Rev 2 11 RENESAS Page 390 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 5E 3 PDL_NO_FUNC Figure 5 33 Configure the I C channel and write 3 data bytes to the first locations 2 Reception Continuing from above The 1 C in master is now used to read 4 bytes from a sl
87. r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO y Rev 2 11 ENESAS 4 Library Reference Page 294 of 418 RX63T Group 4 R_CRC_Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference Read the CRC calculation result bool R_CRC_Read uint8_t data1 Control uint16_t data2 Data storage location Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default e Result register clearing PDL_CRC_CLEAR_RESULT or PDL_CRC_RETAIN_RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are stored in the lower order byte True CRC R_CRC_Create R_CRC_Write None RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t CRCresult Read the CRC result and clear it R_CRC_Read PDL_CRC_RETAIN RESULT amp CRCresult Y Rev 2 11 EN ESAS Page 295 of 418 R
88. re enable the trigger PDL_ADC 12 0 OFF Stop the conversion and disable all triggers e On off control for ADC unit 1 PDL_ADC_12 1 ONor Start a software triggered conversion or re enable the trigger PDL_ADC_12_1_OFF Stop the conversion and disable all triggers Scan priority control for Group B for ADC unit 0 disable restarted and scan PDL_ADC_12 0 GPB_RESTART_CONTINUOUS_OFF or continuous in Single cycle for Group B Set Group B to be restarted PDL_ADC 12 0 GPB_RESTART_ON or after getting discontinued due to Group A priority control Set Group B to be PDL_ADC 12 0 GPB_CONTINUOUS_ON continuously activated for single cycle scan Rev 2 11 EN ESAS Page 308 of 418 RX63T Group Description 2 2 4 Library Reference Scan priority control for Group B for ADC unit 1 Return value Category Reference Remarks Program example disable restarted and scan PDL_ADC_12 1 GPB_RESTART_CONTINUOUS_OFF or continuous in Single cycle for Group B Set Group B to be restarted PDL_ADC 12 1 GPB_RESTART_ON or after getting discontinued due to Group A priority control Set Group B to be PDL_ADC 12 1 GPB_CONTINUOUS_ON continuously activated for single cycle scan e Control the CPU during the ADC conversion Stop the CPU when the scan conversion process starts PDL_ADC_12_CPU_OFF The CPU
89. to reduce the current consumption RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void Disable the CAC R_CAC_Destroy di Rev 2 11 ENESAS 4 Library Reference Page 109 of 418 RX63T Group 4 Library Reference 3 R_CAC_Control Synopsis Control the clock accuracy circuit Prototype bool R_CAC_Control uint8_t data1 Control options uint32_t data2 Operation changes uint16_t data3 Upper limit value uinti6_tdata4 Lower limit value Description 1 2 Modify the Clock frequency accuracy measurement circuit operation data1 Control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Flag clearing control PDL_CAC_CLEAR_FREQUENCY_ERROR PDL_CAC_CLEAR_MEASUREMENT Clear any selected flag PDL_CAC_CLEAR_OVERFLOW e Operation control PDL_CAC_DISABLE Stop the measurement operation PDL_CAC_ENABLE Re start the measurement operation data2 Operation control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Reference signal selection PDL_CAC_REFERENCE_MAIN or Select the Main clock oscillator PDL_CAC_R
90. where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 The status flags shall be stored in one of the following formats depending on the current mode Note Some bits are Not Applicable NA in all modes see descriptions Asynchronous or Synchronous modes Not IIC Mode b7 b6 b5 b4 b3 b2 b1 bO Reception error detection Overrun Framing Parity Transmit RxD pin level 0 Async Async status 0 NA to SPI mode Mode Only Mode Only 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High Smart card mode b7 b6 b5 b4 b3 b2 b1 bO Error detection T RxD pin ransmit status 0 Overrun Error signal Parity 0 level 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High lIC Mode b7 b1 bO ACK NACK flag This is updated every time an ACK or NACK is received 0 ACK received 1 NACK received data3 The storage location for the last byte that was received Specify PDL_NO_PTR if this information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available
91. 10 bit ADC unit PDL DTC TRIGGER _S12ADI or Conversion completed on the 12 bit ADC unit 0 PDL_DTC_TRIGGER_S12GBADI or Conversion completed on group B of the 12 bit ADC unit 0 PDL_DTC_TRIGGER_S12ADI1 or Conversion completed on the 12 bit ADC unit 1 PDL_DTC_TRIGGER_S12GBADI1 or Conversion completed on group B of the 12 bit ADC unit 1 PDL_DTC_TRIGGER_MTUAO or PDL_DTC_TRIGGER_MTUA1 or PDL_DTC_TRIGGER_MTUA2 or PDL_DTC_TRIGGER_MTUA3 or PDL_DTC_TRIGGER_MTUA4 or PDL_DTC_TRIGGER_MTUA6 or PDL_DTC_TRIGGER_MTUA7 or Compare match or input capture A on MTU channel n n 0 to 4 or 6 to 7 PDL_DTC_TRIGGER_MTUBO or PDL_DTC_TRIGGER_MTUB2 or PDL DTC TRIGGER MTUB1 or PDL_DTC_TRIGGER_MTUB3 or PDL_DTC_TRIGGER_MTUB4 or PDL_DTC_TRIGGER_MTUB6 or PDL_DTC_TRIGGER_MTUB7 or Compare match or input capture B on MTU channel n n 0 to 4 or 6 to 7 PDL_DTC_TRIGGER_MTUCO or PDL_DTC_TRIGGER_MTUC3 or PDL_DTC_TRIGGER_MTUC4 or PDL_DTC_TRIGGER_MTUCE6 or PDL_DTC_TRIGGER_MTUC7 or PDL_DTC_TRIGGER_MTUDO or PDL_DTC_TRIGGER_MTUD3 or PDL DTC TRIGGER _MTUD4 or PDL_DTC_TRIGGER_MTUD6 or PDL_DTC_TRIGGER_MTUD7 or Compare match or input capture C on MTU channel n n 0 3 4 6 or 7 Compare match or input capture D on MTU channel n n 0 3 4 6 or 7 PDL_DTC_TRIGGER_MTUU5 or Compa
92. 1024 4096 8192 16384 Period pcik 4 81 9 us 328 us 735 us 1 31 ms Period pcik 64 1 31 ms 5 24 ms 11 8 ms 21 0 ms Period pcik 128 2 62 ms 10 5 ms 23 5 ms 41 9 ms Period pcik 512 10 5 ms 41 9 ms 94 1 ms 168 ms Period PcLk 2048 41 9 ms 168 ms 377 ms 671 ms Period PCLK 8192 168 ms 671 ms 1 51s 2 68s Rev 2 11 ENESAS RPDL definitions tinclude r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the watchdog timer for PCLKB 4 Timeout cycles 4096 no windowing and reset operation R_WDT_Set PDL_WDT_PCLK_DIV_4 PDL_WDT_TIMEOUT_4096 PDL_WDT_TIMEOUT_RESET y Configure the watchdog timer for PCLKB 128 Timeout cycles 8192 windowing 50 to 25 and reset operation R_WDT_Set PDL_WDT_PCLK_DIV_128 PDL_WDT_TIMEOUT_8192 PDL_WDT_TIMEOUT_RESET PDL_WDT_WI START_50 PDL_WDT_WIN_END_25 Page 227 of 418 RX63T Group 4 Library Reference 2 R_WDT_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Control the Watchdog operation bool R_WDT_Control uint8 tdata Control selection Modify the operation of the Watchdog timer data Control the Watchdog timer e Counter update PDL_WDT_RE
93. 12 2014 Rev 2 11 ENESAS Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 Channel number uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint16_t data6 Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b5 b4 b3 b2 me A Interrupt Transfer Escape Transfer End Status pase 0 request End interrupt ESIF interrupt DTIF ACT DTE IR 0 Idle 0 Idle 0 Idle 1 Generated 1 Generated 0 Disabled 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required Wee current repeat or block size count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false DMA controller R_DMAC_ Create Ifthe Interrupt request flag is set to 1 the flag will be cleared to O b
94. 2 11 ENESAS Page 51 of 418 RX63T Group 4 Library Reference Program example RPDL definitions tinclude r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void Configure main clock operation using a 12 0 MHz crystal ICLK 3 MHz PCLKA 3 MHz PCLKB 3 MHz PCLKC 3 MHz PCLKD R_CGC_Set PDL_CGC_CLK_MAIN PDL_CGC_BCLK_DISABL 12E6 3E6 3E6 3E6 3E6 PDL_NO_DATA 3E6 3E6 PDL_NO_DATA PDL_NO_DATA y 3 MHz FCLK 3 MHz E PDL_NO_DATA for 64 and 48 pin package for 64 and 48 pin package Configure PLL operation The PLL will be set to 120 MHz ICLK 60 MHz PCLKA 60 MHz PCLKB 15 MHz PCLKC 15 MHz PCLKD 15 MHz FCLK 15 MHz R_CGC_Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DISABLE PDL_NO_DATA for 64 and 48 pin package 120E6 60E6 60E6 15E6 15E6 PDL_NO_DATA for 64 and 48 pin package 15E6 15E6 PDL_NO_DATA PDL_NO_DATA i R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS Page 52 of 418 RX63T Group 2 R_CGC_Control Synopsis Modify the clock generation circuit operation Prototype bool R_CGC_Control Clock selection Clock control option Clock control option uint8_t data1 uint32_t data2 uint8_t data3 Description Modify the clock control registers R20U
95. 353 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples Invert the LED port pin R_IO_PORT_Modify PDL_IO_PORT_7_1 PDL_IO_PORT_XOR 1 y Stop channel 0 R_DMAC_Control 0 DL_DMAC_SUSPI DL_NO_PTR DL_NO_PTR DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA T U ee TU TU TO Shutdown channel 0 R_DMAC_Destroy 0 y Figure 5 11 Two examples of DMAC use R20UT2201EE0211 Rev 2 11 AS Page 354 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 10 Data Transfer Controller 5 10 1 Block transfer mode Figure 5 12 shows an example of Data Transfer Controller usage with a single block transfer Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt if defined DEVICE_PACKAGE_64_PIN amp amp defined D E_PACKAGI define PDL_INTC_IRO2_ PIN PDL_INTC_IRO2_PE3 else define PDL_INTC_IRO2_ PIN PDL_INTC_IRO2_P00 endif Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve 16 bytes for the IRQ2 triggered transfer data area uint32_t dtc_irg_transfer_data 4 Data source and destination declaration
96. 5 7 Example of Software Standby Mode R20UT2201EE0211 Rev 2 11 AS Page 346 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 7 2 Deep Software Standby Mode Figure 5 8 shows an example of entering Deep Software Standby mode through Low Power Consumption control PDL functions include r_pdl_lpc h include r_pdl_intc h PDL device specific definitions include r_pdl_definitions h void NMI_handler_lpc void void main void const uint8_t data_to_save Hello_World_1234567890_abcdefghi uint8_t data_to_restore R_PDL_LPC_BACKUP_AREA SIZE uint32_t status_flags Read the LPC status R_LPC_GetStatus status_flags Check if this is an exit from deep software standby BIT_23 if status_flags amp 0x00800000 0 Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_AR Y Have exited deep standby sample finishes here while 1 Configure the NMI pin interrupt R_INTC_CreateExtInterrupt PDL_INTC_NMI DL_INTC_FALLING I_handler_lpc i Allow a falling edge on NMI to cancel deep software standby R_LPC_Create PDL_NO_DATA DL_NO_DATA DL_LPC_CANCEL_NMI_FALLING DI DI L_NO_DATA L_NO_DATA y Write data into the backup registers LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AR Enter deep software standby mode
97. 5V products Specify PDL_NO_DATA to use the default PDL_LVD_VOLTAGE_LEVEL_450 or PDL_LVD_VOLTAGE_LEVEL_423 or PDL _LVD_ VOLTAGE LEVEL_477 Set the voltage detection level data3 Monitor 2 voltage detection configurations If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection e Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or PDL_LVD_INTERRUPT_NMI_DETECT_RISE or PDL_LVD_INTERRUPT_NMI_DETECT_FALL or PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_ FALL Select no action a reset on low voltage detection or non maskable interrupt when a specified voltage event is detected Rev 2 11 EN ESAS Page 102 of 418 RX63T Group Description 1 2 4 Library Reference Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD_FILTER_LOCO DIV_8 data4 Monitor 2 voltage detection levels For device packages with 48 or 64 pins this fixed at 2 95V specify PDL_NO_DATA Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Voltage levels applicable for 3V products Specify PDL_NO_DATA to use the default PDL_LVD_VOLTAGE_LEVEL_288 or PDL_LVD_VOLTAGE_LEVEL_285 or P
98. Control the SCI channel bool R_SCI_Control uint8_t data1 Channel selection uint16_t data2 Channel control Control the SCI channel data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Not IIC Mode Control the channel If multiple selections are required use to separate each selection e Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If a reception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags may be set erroneously These can be ignored and will be cleared when a new reception process is started PDL_SCI_STOP_RX The option PDL_SCI_STOP_TX_AND_RX can be used to select both processes If both processes are selected transmission and reception will stop immediately e Generate a Space or Mark signal when idle Only applicable in Async and Async Multi Processor Modes Set the idle output to Space logic 0 PDL SCI OU TPUT SPACE This can be used to generate a Break condition PDL_SCI_OUTPUT_MARK Set the idle output to Mark logic 1 e Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags e Manual SCK control PDL_SCI_GSM_SCK_STOP or Disab
99. DOS TOY iii lolita eta dd 130 5 AUBSCTCONTO Maa A E A ITT 131 6 RBSC GetStatus vainas ardid Daiana tae deity a Ad csnses E te see sess 132 AQ A MC SAA O O 133 1 ARO A A 133 2 Re DMAGs DOSIOY aseeto ea Aer a A Add Ud AS AAA ad 138 3 R DMAG Contour as 139 4 R_DMAC _ GetStatus cocoocococcncnnnnonooooncncnnononanoanononcnnnnonnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnronenennnnnnnnnn 142 4 2 12 Data Transfer Controller cccccccccccccecsesssesecececeesseaeseseseeeceeseeaeseceeseseseseaaeceeeeseeeseaaeseeeeseeeses 144 Di RAD TCS Stig si a a as 144 2 PeeBT Ge Create ya ca E T are Sess ath oe T eee eet ae 145 3 REIO BY 1 1 0 iia a Aa Da AD tc a DA 149 My CORDIC Comro aci aid Dias 150 5 PAPILONE IT TEE A E E A A T E E EA 152 4 2 13 Multi Function Timer Pulse Uniit cc cccccccceceeeeeceeeeeeeeeceeeeeeeeseeeeeeeseseseseseeeseseeeeeseeeeeeeseeees 154 De RAUMTUS Sti ss ts as a a a a as 154 2 PIM TUS Create a e dec 156 3 RM TUS DESMOY cas io aa da e a eta ad decos e 166 4 R_MTU3_ControlChamel cccnnnnccoccccnncnnnonocoonnnnnnonononononnnnnnnnnononononnnnnnnnnnnnnnnnnnnnnnnnnnnnonnnnnnnnnnnnn 167 5 R_MTU3_ControlUnit cconoonccnnnncccnnonoccccnononcnnnanoncnnnnnonnncnononnnnnnnnnnnnnnn nn E nn rr naar nn nn naar nn rrnnarnnnnins 170 6 RUMTUS ReadChannel iio A iaa 177 Tu MIUS ReadUn ita A A ieee a ee eee Raa 179 4 2 14 PortOUlputEnable tii ia a nthe Ri EE pia dio 180 Wy RLPOE Sehonnan ra ea T
100. IIC master read 9 R_SCI_IIC_ReadLastByte Finish an SCI master read if using DMAC or DTC 10 R_SCI_Control Control the SCI channel 11 R_SCI_GetStatus Check the status of an SCI channel R20UT2201EE0211 Rev 2 11 LEN ESAS Page 47 of 418 Sept 12 2014 RX63T Group 4 Library Reference 12 bit Analog to Digital converter 1 R_IIC_Create 12C channel setup 2 R_IIC_ Destroy Disable an 12C channel 3 R_IIC_MasterSend Write data to a slave device 4 R_IIC_MasterReceive Read data from a slave device 12C bus interface 5 R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process 6 R_IIC_SlaveMonitor Monitor the bus and receive data from a master 7 R_IIC_SlaveSend Write data to a master device 8 R_IIC_Control 12C channel control 9 R_IIC_GetStatus Read the status for an 12C channel 1 R_SPI_Set Configure the SPI pin selection 2 R_SPI_Create Configure an SPI channel Serial 3 R_SPI_Destroy Shutdown an SPI channel Peripheral 4 R_SPI_Command Configure an SPI command Interface 5 R_SPI_Transfer Transfer data over an SPI channel 6 R_SPI_Control Control an SPI channel 7 R_SPI_GetStatus Check the status of an SPI channel 1 R_CRC_ Create Configure the CRC calculator 2 R_CRC Destroy Shut down the CRC calculator CRC calculator R_CRC Write Write data into the CRC calculation register R_CRC_Read Read the CRC calculation result R_ADC_12 Set Select the I O
101. IWDT underflow interrupt occurs PDL_INTC_LVD1_ DISABLE or PDL_INTC_LVD1_ ENABLE Disable or enable the NMI signal when a low voltage detection 1 interrupt occurs PDL_INTC_LVD2_DISABLE or PDL_INTC_LVD2 ENABLE Disable or enable the NMI signal when a low voltage detection 2 interrupt occurs 11 ENESAS Page 58 of 418 RX63T Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI data3 The IRQn interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI and is ignored True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_SetExtInterrupt Function R_INTC_SetExtInterrupt must be called before any use of this function The selected interrupt is enabled automatically Please see the notes on callback function use in 86 The NMI callback function should not return It should stop operation or reset the system e Ifthe NMI interrupt fails to initialise this function will return false R
102. LPC_Control PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY An internal reset will occur when exiting from deep software standby The program counter will not return to here while 1 void NMI_handler_lpc void nop Figure 5 8 Example of Deep Software Standby Mode R20UT2201EE0211 Rev 2 11 RENESAS Page 347 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 8 Bus Controller 5 8 1 Bus controller for the 64 pin and 48 pin package Figure 5 9 shows an example of bus controller usage Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void BSC_error_handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 y Configure the bus controller R_BSC_Create PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL _BSC_ERROR_ILLEGAL_ADDRE BSC_error_handler 5 y Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit void BSC_error_handler void Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR y Figure 5 9 Example of Bus Controller use R20UT220
103. MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take acopy of the ACC register and restore it before exiting the callback function R20UT2201EE0211 Rev 2 11 RENESAS Page 418 of 418 Sept 12 2014 RX63T Group Revision History Revision History RX63T Group User s Manual A Dat Description ev ate Summary 1 00 Aug 09 2012 Fs Edition issued Developed using MCU hardware manual Rev 1 00 R_INTC_SetExtInterrupt Amended the program example R_INTC_Modify Amended the program example R_IO_PORT_Set Modified the program example R_IO_PORT_Read Modified the program example R_IO_PORT_Write Modified the program example R_IO_PORT_Compare Modified the program example R_IO_PORT_Modify Modified the program example R_IO_PORT_Wait Modified the program example R_MPC_Read Amended the program example R_MPC_Write Amended the program example R_MPC_Modify Amended the program example R_CAC_Create Added remarks that callbacks must clear flags as interrupt is level based R_CAC_Control Added remark about avoiding lockup by not doing enable disable rom in
104. N a A NA aa es ee 180 2 R POE Crea A AA AA dz 184 3 REPOE Conta A A eat nee Se A A aa a eaea 186 4 R POE GetStatus ini A A ee da 188 4215 General PWM Timer ui A A A id 189 Di ROGP T Sia A A a des 189 2 R GPT Create Uli AA seid A A A a eaa 191 3 RUGPTCreateCh ame A A A i ee es 193 4 ReGPT Destroy cti A dae 201 5 RAGPT ControlCharinel uso A A A AE 202 6 REGPTECON TO liada ii de thee hatin ins CEE AAA A A A 206 2 mk N AROMA MpAwWNMANNATARWNHNANOANDOTAWNANAARDOANDKORWNHNANWDNANwWnNANnanwnaManwoon o A YU UU S UU UU OS a Dre UU S Ri GPT ReadGhannel ii A a vids Bel AA ts AD A ddan 208 R2aGPT Ready si A A A tang eel a AA A aS 211 R GPT EdgeDelay Create aeaeyae anden caves ais Dada deltas falta ada aiii Da ead 213 R GPT BdgebDelay Controleren ia i a a a a 215 R GPT EdgeDelay Destroy ciooimicoonii tics cia adi aiid iaidd aa iiaia 217 Gompate Match TIMEt irei iiinisiiidiiiiniani ci it Oe Ae etre a iiidid di 218 ReiGM TC re ate er oui Festi A a a aaia ds tts A A a clash 218 REGMT Create ONES a i a AA a 220 R CMT DESTO corintio AE AN EREET TEETE ESEESE REEERE E E OE E A 222 REGMT Control ii ni a i ia ta AAA a E 223 R CMT REAO u e AA caus ds tli ta ADA GE 225 Watchdog Time sias oria dd dE dt dad AN E a ata N a EAE 226 AS A A EAA A E 226 AZWDT_Gontrol A A aaa AA 228 Re WwDT EY o title 229 Independent Watchdog TIMET ne aarne aaa aeaa eaa aaa cnn 230 RAIWDT Stata daa dei 230 R IWDTE Co
105. Number of 16 bit words to write data1 The start address of the data to be written data2 The number of 16 bit words to write True DOC None e This function will not return until all the supplied data has been written to the DOC The DMAC DTC can be used to write data to the DOC independently of this function RPDL definitions tinclude r_pdl_doc h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint16_t data 10 1 2 3 4 5 6 7 8 9 10 Write 10 numbers to the DOC R_DOC_Write data 10 Rev 2 11 EN ESAS Page 333 of 418 RX63T Group 5 Usage Examples 5 Usage Examples This chapter shows programming examples for each driver in this library R20UT2201EE0211 Rev 2 11 EN ESAS Page 334 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 1 Clock Generation Circuit Figure 5 2 shows an example of configuring the clock generation circuit After a power on reset both the PLL and the main clock oscillator which drives the PLL circuit are switched off The MCU is using the LOCO as the clock source The calls to R_CGC_Set configure the LOCO dividers and enable the main clock oscillator and the PLL circuit After an appropriate time to allow for the crystal based main clock oscillator and the PLL circuit to stabilise a call to R_CGC_Control is used to select the PLL circuit as the clock source Peripheral driver function prototypes
106. PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA y NMI Callback function static void Callback_NMI void uint8_t status 0 Read the NMI status R_INTC_GetExtInterruptStatus PDL_INTC_NMI amp status y Did an LVD1 trigger occur if status amp BIT_6 0 Clear the LVD monitor 1 flag R_LVD_Control PDL_LVD_CLEAR_DETECTION PDL_NO_DATA y Clear the NMI LVD1 flag R_INTC_ControlExtInterrupt PDL_INTC_NMI PDL_INTC_CLEAR_LVD1_FLAG Figure 5 5 Example of Voltage Detection Circuit use R20UT2201EE0211 Rev 2 11 RENESAS Page 343 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 6 Clock Frequency Accuracy Measurement Circuit The main clock is used as the reference to measure the IWDTLOCO frequency Peripheral driver function prototypes include r_pdl_cac h include r_pdl_cgc h PDL device specific definitions include r_pdl _definitions h Callback functions void CAC_frequency_error void void CAC_overflow void Expected Clock values define FREQ _IWDTLOCO 125E3 define FREQ MAIN 12E6 void main void Configure the IWDTLOCO clock settings R_CGC_Set PDL_CGC_CLK_IWDTLOCO NO_DATA Reserved IWDTLOCO IWDTLOCO L_NO_DATA ICLK L_NO_DATA PCLKA L_NO_DATA PCLKB L_NO_DATA Reserved L
107. POE SAORI 6 Elo circuits nared if the MTU settings for channel PDL_POE SHORT 67 P91_LOWor gt ete 9 PDL_POE_SHORT_67 P91 HIGH PDL_POE_SHORT_67_P93_LOW or PDL_POE_SHORT_67_P93_ HIGH PDL_POE_SHORT_67_P90_ LOW or PDL_POE_SHORT_67_P90_HIGH R20UT2201EE0211 Rev 2 11 Page 182 of 418 Sept 12 2014 ENESAS RX63T Group Description 4 4 4 Library Reference Output short response Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 include If a short is detected place the all the selected MTU channel 3 and 4 or GPT channel 0 to 2 pins in the high impedance state PDL_POE_SHORT_P7X_HI_Z If a short is detected place the all the selected MTU channel 6 and 7 or GPT channel 4 to 6 pins in the high impedance state PDL_POE_SHORT_MTU_67_HI_Z True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE_ Control R_POE_GetStatus R_MTU3_Set Pins POE4 POE10 E4 and POE12 are not available on the 64 and 48 pin packages Pin POE12 is not available on the 100 pin package The pin selection for POE10 is available on the package larger than 64 pin Do not select M
108. POOPFS R_MPC_ Write PDL_MPC_REG_POOPFS OxC5 Set bit 3 in POOPFS to 1 R_MPC_Modify PDL_MPC_REG POOPFS PDL_MPC_OR 0x08 y Get the value of register POOPFS R_MPC_Read PDL_MPC_REG_POOPFS amp data y while 1 Figure 5 47 Example of MPC R20UT2201EE0211 Rev 2 11 AS Page 415 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 26 Multi Function Timer Pulse Unit Figure 5 48 Example of MTU show an example multi function timer pulse unit usage Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_mtu3 h PDL device specific definitions tinclude r_pdl_definitions h static void Callback_Match_TGRA void static void Callback_Match_TGRE void Allocate structures R_MTU3_Create_structure create_parameters volatile int Counter_Callback_Match_TGRA volatile int Counter_Callback_Match_TGRE void main void Parameters that are structures R_MTU3_Create_structure create_parameters R_MTU3_ControlChannel_structure control_parameters Load the Create defaults R_MTU3_Create_load_defaults amp create_parameters NOTE The code to initialise the system clock is omitted here Please refer to 5 1 Clock Generation Circuit Set Create options create_parameters channel_mode PDL_MTU3_MODE_NORMAL Clock slow down from defualt create_parameters
109. Page 12 of 418 RX63T Group 1 Introduction 11 Using library with debug information RPDL library with debug information should be chosen in order to step in the RPDL source code for debugging Unzip the RPDL source zip file e g RPDL_RX63T_CS x xx_source zip into a folder e g c my_project_folder Set a breakpoint at the RPDL API to be debugged When the program breaks at the RPDL API press F11 key to step in the function A pop up window will appear to request for the location of the corresponding RPDL source file Open Lo RPDL_RX63T_CS x2 source Filename R_ADC_10_CreateUnitAll Files of type Source File c y Cancel SS Select the folder where you unzip the RPDL source file and open the source file under respective module folder Once the correct source file is selected user could step in to the file and step through the function R20UT2201EE0211 Rev 2 11 AS Page 13 of 418 Sept 12 2014 RENES RX63T Group 1 Introduction 1 3 3 Header file inclusion The RPDL folder contains a header file iodefine_RPDL h This file is included by the RPDL source files and will also be included by any user generated files that call RPDL functions The main HEW project folder may contain the header file iodefine h This file is normally used if access to the I O registers in the MCU is required For any user generated files that call RPDL functions there is no nee
110. Portpin P5o PDL_IO PORT B 2 Port pin PB2 PDL_IO_PORT_5 1 Port pin P54 PDL_IO PORT_B 3 Port pin PB3 PDL_IO PORT 5 2 PortpinP52 PDL_ IO PORT_B 4 Port pin PB PDL_IO PORT 5 3 PortpinP53 PDL_IO PORT_B 5 Port pin PBs PDL IO PORT_5 4 PortpinP54 PDL IO PORT_B 6 Port pin PBe PDL_IO PORT 5 5 PortpinP5s PDL_ IO PORT_B 7 Port pin PB7 PDL_IO PORT 5 6 Port pin P56 PDL_IO PORT 5 7 Port pin P57 Note Refer to the hardware manual for the port pins which are available on the device that you have selected R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS Page 80 of 418 RX63T Group 1 R_IO_PORT_Set Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Configure an I O port bool R_IO_PORT_Set uint16_t data1 Port pin selection uint16_tdata2 Configuration Set the operating conditions for I O port pins data1 4 Library Reference Select the port pins to be configured from 84 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin if any pins of PORT 4 5 6 or C are selected these pins will not be used as analog pins data2 Choose the pin settings Use to separate each selection Each selection is optional If a
111. R_CRC_Write OxFO i Write the first half of the CRC checksum R_CRC_Write 0x8F Write the second half of the CRC checksum R_CRC_Write 0xF7 y Read the CRC calculation result Expected result is 0 R_CRC_Read PDL_NO_DATA amp crc_result Shutdown the CRC unit R_CRC_Destroy Figure 5 42 Example of CRC calculation R20UT2201EE0211 Rev 2 11 RENESAS Page 407 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 21 12 bit Analog to Digital Converter This example shows ADC_12 used in single scan mode with a software trigger and a specified sampling time Peripheral driver function prototypes tinclude r_pdl_adc_12 h tinclude r_pdl_cmt h tinclude r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h Array used to read the ADC results uint16_t adc_results 8 void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure analog input for ANOOO R_ADC_12_Set PDL_ADC_12_ PIN_ANOOO_P40 Y Configure ADC in single scan mode R_ADC_12_CreateUnit 0 PDL_ADC_12 SCAN_SINGLI PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 0 0 PDL_NO_FUNC 0 PDL_NO_FUNC 0 i Configure ADC on AN000 R_ADC_12_CreateChannel 0
112. R_INTC_ControlGroup 1 PDL_INTC_GROUP_ENABLE PDL_INTC_GRP12_ALL R20UT2201EE0211 Rev 2 11 RENESAS Page 78 of 418 Sept 12 2014 RX63T Group 4 Library Reference 13 R_INTC_GetStatusGroup Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Read the status of an interrupt request group bool R_INTC_GetStatusGroup uint8_t data1 Group selection uint32_t data2 Data storage location Read the grouped interrupt request status flags data1 The interrupt request group n to be configured For 64 and 48 pin packages n must be 12 for other pin packages n can be 0 or 12 data2 The status flags shall be stored in the format below e Group 0 b31 b2 B1 bO CAN error interrupts 0 Channel 1 0 0 Not requested 1 Requested e Group 12 b31 b7 b6 b5 SPI error 0 Channel 1 Channel 0 0 Not requested 1 Requested b4 b3 b2 b1 bO SCI reception error Channel 12 Channel 3 Channel 2 Channel 1 Channel 0 0 Not requested 1 Requested True if all parameters are valid otherwise false Interrupt control R_INTC_ControlGroup For 64 and 48 pin packages SCI channel 2 and 3 and SPI channel 1 are not available RPDL definitions include r_p
113. Reference R_IIC_Create Remarks The flags are not modified by this function The event detection flags are cleared as required by the driver for correct operation The transfer count values are cleared when a new transfer is started e If using the DTC or DMAC to transfer data the transfer count values will not be valid The R_DTC_GetStatus or R_DMAC_GetStatus can be used to calculate the transfer count Note If the DTC DMAC transfer does not fully complete then the count reported by the DTC DMAC for a slave transmission will be one greater than the actual number of bytes read by the master Transmit mode is set when the master has started a master read transfer e Channel 1 is supported on 120 pin 144 pin packages only R20UT2201EE0211 Rev 2 11 RENESAS Page 277 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions tinclude r_pdl_iic h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint32_t status_flags uint16_t tx_count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags amp tx_count PDL_NO_PTR R20UT2201EE0211 Rev 2 11 RENESAS Page 278 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 2 21 Serial Peripheral Interface 1 R_SPI_Set Synopsis Configure the SPI pin selection Prototype bool R_SPI_Set uint8_t data1 Channel selection
114. Register DSCR1 Port Driving Ability control for option PDL_IO_PORT_DRIVE_SPI b15 b8 b7 b0 0 Register DSCR2 Return value True if all parameters are valid and exclusive otherwise false Ensure that the specified register is valid for the selected port or port pin If port is input for the data1 PDL_IO_PORT_DRIVE_BUS or PDL_IO_PORT_DRIVE_SPI is selected for data2 data3 will read whole register value for Driving Ability Control Register Refer to register DSCR1 and DSCR2 description in hardware manual Category I O port References None Remarks R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS Page 82 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t result Read the direction register for port B R_IO_PORT_ReadControl PDL_IO_PORT_B PDL_IO_PORT_DIRECTION result Read the output type for pin P30 R_IO_PORT_ReadControl PDL_IO_PORT_3_0 PDL_IO PORT TYPE result R20UT2201EE0211 Rev 2 11 EN ESAS Page 83 of 418 Sept 12 2014 RX63T Group 3 R_IO_PORT_ModifyControl Synopsis Prototype Description Return value Modify an I O port s control registers bool R_IO_P
115. Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control e This function will also shut down the DMAC e Before calling this function i If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral ii Use R_DTC_Control to stop the DTC iii Stop the DMAC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the DTC amp DMAC R_DTC_Destroy Rev 2 11 EN ESAS Page 149 of 418 RX63T Group 4 Library Reference 4 R_DTC_Control Synopsis Prototype Description Return value Category R20UT2201EE0211 Sept 12 2014 Control the Data Transfer Controller bool R_DTC_Control uint32_t data1 Control options uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 Block size Modify the operation of the Data Transfer Controller data1 Control the operation If multiple selections are required use to separate each selection e Stop Start control PDL_DTC_STOP or PDL_DTC_START Enable re enable or suspend DTC transfers e The transfer registers to be modified using the selected parameters
116. VECTOR DES Enable comparison detection PDL_INTC_VECTOR_CMPO PDL_INTC_VECTOR_CMP1 PDL_INTC_VECTOR_GTCIA4 PDL_INTC_VECTOR_GTCIB4 PDL_INTC_VECTOR_GTCIC4 PDL_INTC_VECTOR_GTCIE4 PDL_INTC_VECTOR_GTCIV4 PDL_INTC_ VECTOR LOCOI4 12 bit ADC unit 0 PDL_INTC_VECTOR_CMP2 Comparator event on input ANOO2 General PWM timer channel 4 Comparator event on input ANOOO Comparator event on input ANOO1 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match LOCO count function event PDL_INTC_VECTOR_GTCIA5 PDL_INTC_VECTOR_GTCIB5 PDL_INTC_VECTOR_GTCIC5 PDL_INTC_VECTOR_GTCIE5 PDL_INTC_VECTOR_GTCIV5 General PWM timer channel 5 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match Rev 2 11 ENESAS Page 62 of 418 RX63T Group 4 Library Reference Description 3 3 PDL_INTC_VECTOR_GTCIA6 PDL_INTC_VECTOR_GTCIB6 PDL_INTC_VECTOR_GTCIC6 PDL_INTC_VECTOR_GTCIE6 PDL_INTC_VECTOR_GTCIV6 PDL_INTC_VECTOR_ICEEI1 PDL_INTC_VECTOR_ICRXI1 PDL_INTC_VECTOR_ICTXI1 PDL_INTC_VECTOR_ICTEI1 General PWM timer channel 6 12C bus interface channel 1 Compare match or input capture A Compare match or input capture B Compare match C or D Compare ma
117. Valid between 0 and 7 data6 The number of wait cycles used for second and subsequent accesses during a page write sequence CSPWWAIT Valid between 0 and 7 data7 The number of wait cycles for the first access during a normal or page read sequence CSRWAIT Valid between 0 and 31 data8 The number of wait cycles for the first access during a normal or page write sequence CSWWAIT Valid between 0 and 31 data9 The number of cycles that the CS signal is left asserted after the read strobe is negated CSROFF Valid between 0 and 7 data10 The number of cycles that the CS signal is left asserted after the write strobe is negated CSWOFF Valid between 0 and 7 data11 The number of cycles that the data output is left asserted after the write strobe is negated WDOFF Valid between 0 and 7 data12 The number of wait cycles to be inserted into a multiplexed address output cycle AWAIT Valid between 0 and 3 data13 The number of cycles before the read strobe is asserted RDON Valid between 0 and 7 data14 The number of cycles before the write strobe is asserted WRON Valid between 0 and 7 data15 The number of cycles before the write data is output WDON Valid between 0 and 7 data16 The number of cycles before the chip select is asserted CSON Valid between 0 and 7 True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create e Use this function to set
118. action PDL_MCU_OFS_WDT_NMI or Select an NMI or reset when the WDT PDL_MCU_OFS_WDT_RESET down counter underflows data3 Select the post reset LVD configuration settings e Auto start control PDL_MCU_OFS_LVD_0_DISABLE or Disable or enable the Voltage monitor 0 auto start PDL_MCU_OFS LVD_ 0 ENABLE mode Category MCU registers References R_IWDT_Set R_WDT_Set R_CGC_Set Remarks This is a macro not a function call There is no error checking or return value The auto start setting for each parameter must be selected R20UT2201EE0211 Rev 2 11 RENESAS Page 100 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_mcu_ofs h Enable the IWDT auto start mode Leave the WDT disabled Enable reset at Vdet0 R_MCU_OFS PDL_MCU_OFS_IWDT_AUTOSTAR PDL_MCU_OFS_IWDT_TIMEOUT_4096 PDL_MCU_OFS_IWDT_CLOCK_LOCO_16 PDL_MCU_OFS_IWDT_WIN_END_50 PDL_MCU_OFS_IWDT_WIN_START_75 PDL_MCU_OFS_IWDT_NMI PDL_MCU_OFS_IWDT_STOP_DISABLE PDL_MCU_OFS_WDT_HALTED PDL_MCU_OFS_LVD_0_ ENABLE i R20UT2201EE0211 Rev 2 11 ENESAS Page 101 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 2 6 Voltage Detection Circuit 1 R_LVD_Create Synopsis Prototype Description 1
119. are shown in bold Specify PDL_NO_DATA to use the defaults e TCNT counter clock source selection Valid for n 5 unless stated otherwise PDL_MTU3_CLK_PCLKA_DIV_1 or PDL_MTU3_CLK_PCLKA_DIV_4 or PDL_MTU3_CLK PCLKA DIV_16 or PDL_MTU3_CLK PCLKA DIV_64 or PDL_MTU3_CLK PCLKA DIV_256 or PCLKA 256 Valid for n 1 3 4 6 and 7 PDL_MTU3 CLK PCLKA DIV 1024 or PCLKA 1024 Valid for n 2 3 4 6 and 7 The internal clock signal PCLKA 1 4 16 or 64 PDL_MTU3_CLK_MTCLKA or MTCLKA pin input Valid for n O to 4 PDL_MTU3_CLK_MTCLKB or MTCLKB pin input Valid for n 0 to 4 PDL_MTU3_CLK_MTCLKC or MTCLKC pin input Valid for n O and 2 PDL_MTU3_CLK_MTCLKD or MTCLKD pin input Valid for n O The overflow underflow signal from channel 2 PDL_MTU3_CLK_CASCADE Valid forn 1 TCNT counter clock edge selection Valid for n 5 PDL_MTU3_CLK_RISING or PDL_MTU3_CLK_FALLING or PDL_MTU3_CLK_BOTH The TCNT counter clock signal shall be counted on rising falling or both edges TCNT counter clearing Valid for n 5 unless stated otherwise PDL_MTU3_CLEAR_DISABLE or Clearing is disabled PDL_MTU3_CLEAR_TGRA or Cleared by TGRA compare match or input capture PDL_MTU3_CLEAR_TGRB or Cleared by TGRB compare match or input capture PDL_MTU3 CLEAR SYNC or Cleared by counter clearing on another channel configured for synchronous operation Cleared by TGRC compar
120. buffer register GTDBU value data22 The dead time down counting register GTDVD value data23 The dead time down counting buffer register GTDBD value True if all parameters are valid and exclusive otherwise false General PWM Timer unit R_GPT_CreateChannel e The Stop operation is executed at the start of this function The Start operation is executed at the end Both options can be selected together with other changes in one function call The buffer operation disable control is executed at the start of this function The buffer operation enable control is executed at the end Both options can be selected together with buffer register access in one function call e If Stop or Start control is selected any channel that has hardware start or stop control enabled may change state in error The IWDTCLK counter Stop operation is executed at the start of this function The Start operation is executed at the end Both options can be selected together with other changes in one function call Rev 2 11 EN ESAS Page 204 of 418 RX63T Group 4 Library Reference Program example R20UT2201EE0211 Sept 12 2014 RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void Rev 2 11 Allocate a copy of the structure for the selected channel R_GPT_ControlChannel_structure gpt_l_control_parameters Set the register va
121. but provides control of GTDLYCR DLYRST PDL GPT PWM DELAY RESET oe reset by setting the DLYRST bit high GTIOCA_Rising_Delay The delay to be applied to the rising edge of GTIOCA The delay is specified in fractions of the ICLK period 0 no delay 1 1 32 of ICLK 2 2 32 of ICLK 30 30 32 of ICLK 31 31 32 of ICLK GTIOCA_Falling_Delay The delay to be applied to the falling edge of GTIOCA See data3 for format GTIOCB_Rising_Delay The delay to be applied to the rising edge of GTIOCB See data3 for format GTIOCB_Falling_Delay The delay to be applied to the falling edge of GTIOCB See data3 for format True if all parameters are valid and exclusive otherwise false Category General PWM Timer unit Reference None R20UT2201EE0211 Rev 2 11 2tENESAS Page 215 of 418 Sept 12 2014 RX63T Group 4 Library Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Call R_GPT_EdgeDelay_Create to enable a channel before using this function If a delay time adjustment is made the actual adjustment will take place on overflows in up counting or underflows in down counting for saw waves and in the troughs of triangle waves Adjustments should not be made to the delay time when the relevant compare match value falls in the range in the follo wing table Mode Counting Direction Compare Match Value
122. bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master read data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10 BIT SLAVE ADDRESS Specify the slave address width Repeated Start PDL SCI_IIC_ RESTART The transfer will start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address gt data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The
123. ci n 334 5 1 Clock Generation GirC t riii aane adai ea eaaa adana ea aaee aaa aaae raa aien aeea eataa 335 520 A a a a a a a a a a a a beaten 338 Da MO POR sh ti A A A a aa RICA 340 54 MCU OperatiO iii A a a cnet dave 342 5 5 Voltage Detection Circuit sssi aa a eaaa a aa aa aa aia aaa aat 343 5 6 Clock Frequency Accuracy Measurement Circuit c cceccceeeeeeeeeeeeeeeee cae eeeeaeeeeeeeseaeeesaaeeseaeeeeenees 344 5 7 LOW Power CONSUMPTION eximio 346 STk Software Standby Mode ciclo aa a aaa SA Taa tail 346 5 7 2 Deep Software Standby Mode cccccccsecsesceceeeeeeeeeeesaeeeeneeceaeeeceaeseeaaesgeeecaeeesaaeseeaeesseeeessaes 347 5 8 Bus Controllers ti A Alley decd Aes adh Ale eee 348 5 8 1 Bus controller for the 64 pin and 48 pin package cccececeeeceseeeeeeeeeeseeseeeeeseaeeesaeeneneeesaees 348 5 8 2 Bus controller for the 100 pin 112 pin 120 pin and 144 pin package cccccsteeeeeeeeees 349 Dg DMA controller ta riolts E A EA 352 5 10 Data Transfer Controller ooonnconnnninnnninncnnnncconnconnccnnanncnrnrn nana 355 50 1 Block transter Molereien denrea ride nets adaa e a aeiiae a ad aani aa eee elt weer eeed 355 5 10 2 Chain transfer operation cccccccceceeeceeeeeeeeseeceeeeeceaeeeeaaeceeneecaeeecaaeeseaaeseeeeeseaeeesaeeeeeeseneeseaees 357 5 11 Port Output Enable kiitotie a A aie 359 5 12 Genera PWM Timer Drivers laeni e tet Aaa 360 5 13 Register Write Protect
124. complement R_ADC_10_CreateUnit to configure 10 bit ADC analog channels if analog channels are selected as the input source data1 Select the ADC unit This must be 0 for All device packages data2 Select the analog input channel This must be 0 to 19 for 144 pin package and 0 to 12 for others data3 Channel options To set multiple options at the same time use to separate each value The default settings are shown in bold Value addition control PDL_ADC 10_CH_VALUE ADDITION DISABLE or PDL_ADC_10 CH VALUE ADDITION ENABLE Enable or disable value addition e Sampling time calculation PDL_ADC_10_ADSSTR_CALCULATE or PDL_ADC_10_ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR data4 The data to be used for the sampling state register value calculations lf PDL_ADC_10_ADSSTR_SPECIFY is selected for data3 specify the value to be written to the sampling state register The value should not be less than 7 or more then 255 If PDL_ADC_10_ADSSTR_CALCULATE is selected for data3 specify the required sampling time in seconds This value must be more than 0 25 us for channel 0 to 7 and more than 0 5 us for others Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t True if a valid unit is selected otherwise false 10 bit ADC R_ADC_10 C
125. cycle end the output is retained set low PDL_GPT_B_CYCLE_HIGH or set high or PDL_GPT_B CYCLE _INVERT toggled ENESAS Page 196 of 418 RX63T Group Description 5 7 R20UT2201EE0211 Sept 12 2014 data8 4 Library Reference ADC trigger and skipping control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults ADC conversion trigger selection PDL_GPT_ADC_TRIG_A_UP_DISABLE or PDL_GPT_ADC_TRIG_A_UP_ENABLE PDL_GPT_ADC_TRIG_A_DOWN_ENABLE PDL_GPT_ADC_TRIG_A_DOWN_DISABLE or Disable or enable ADC start requests on a GTADTRA compare match during up and or down counting PDL_GPT_ADC_TRIG_B_UP_DISABLE or PDL_GPT_ADC_TRIG_B_UP_ENABLE Disable or enable ADC start requests on a PDL_GPT_ADC_TRIG_B_DOWN_DISABLE or PDL_GPT_ADC_TRIG_B_DOWN_ENABLE GTADTRB compare match during up and or down counting e Interrupt and ADC trigger skipping control PDL_GPT_INT_SKIP_OU_DISABLE or Disable skipping or select skipping for PDL_GPT_INT_SKIP_OU_OVER or overflow crest PDL_GPT_INT_SKIP_OU_UNDER or underflow trough or PDL_GPT_INT_SKIP_OU_BOTH both overflow crest and underflow trough PDL_GPT_INT_SKIP_1 or PDL_GPT_INT_SKIP_2 or PDL_GPT_INT_SKIP_3 or PDL_GPT_INT_SKIP_5 or PDL_GPT_INT_SKIP_6 or PDL_GP
126. dn aves Ae alee 96 TY SREMCU Control ives iss ied cit cine Mivua te ausccdviscedea iis de Adabel edad e ld 96 2 RUMGUW Gattaca id LA dd hace 97 AO NN 99 4 2 6 Voltage Detection Circuit cee cccsceeeceeceeeceeceeeeaeeeeeeeeseaeeeeaaeseeneecnaeeesaaeseeaaesseeeceaeeeeaaesseneeeeaees 102 1 R VD Creaton mrna cade Dict dd dad Se Aya ceed a td A E da 102 ar ARVD COnTOl rines orenen a e a Siu iccausllleccdaataadeadvvdes cavadee e 104 3 RLV Ds GOMAS AA a EEN e a e Mae 105 4 2 7 Clock Frequency Accuracy Measurement CitCuit c cccceceeeeeeceeeeeeeeeeeeeeseeeeeseaeeesaaeeneneeeeaees 106 1 REGAC Create dl A Ea A da Ea 106 2 RCAC Destroy pta ii a td aa at a ta Ltd A al age 109 3 R CAC CONTO ii id a ie E A aa IA Eta id 110 4 RaGAG GetStatus diia letrada elias ett ces 112 4 2 8 Low Power CONSUMPION vcd peca 113 1 REE PCsGre ate cesado at da datada dci 113 2 REPE CONTOR Aken er ere E rita ci asia dalt te ta E AE ANERER 116 2o R EPC WriteBackuDe isis lili sit A ES EENAA AEE EEEREN SEA 118 4 Re EPC ReadBaG kDa e ee r eea r Lre E EE E dd eE SEEE E a ba ESAERATAN A 119 5 TALA AE E A chests hes 120 4 2 9 Register Write Protection site a ea a a aaar aa aaa a Ta aaa a aaa aae aaraa ana ai deaa OTA aa iakaat 121 1 o E A Controls ETAETA a T E I E EA E A EEE 121 2 RREI a AEE A T E AAT A E E T 122 AAO A AT AA E A T A A EEN 123 A A nE Aa E E A AEREA devas E A EE NO 123 2 AAA E A AO 124 3 Re BSC uGreateAre IO an I T 127 A y ASBSG
127. function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data5 The start address of the storage area for the expected data Specify PDL_NO_PTR if not receiving data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data Rev 2 11 EN ESAS Page 250 of 418 RX63T Group Description 2 2 Return value 4 Library Reference func2 Receive callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been received The function to be called when the number of received bytes reaches the Interrupts threshold number Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create func3 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range R_SCI_Control R_SCI_GetS
128. guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass
129. in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create Rev 2 11 ENESAS Page 268 of 418 RX63T Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable and a normal transfer completed otherwise false l2C R_IIC_Create R_IIC_GetStatus e If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 e If the Start condition is enabled and the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated e Ifthe Start condition is disabled the slave address will not be transmitted e If no callback function is specified for transmission completion this function will monitor the status flags to manage the data transmission If the 12 channel s registers are modified directly by the user this function may lock up e If false is returned use R_IIC_GetStatus to check if an unexpected event on 1 C bus was the cause of the failure If the transfer has ended prematurely use R_IIC_Control to issue a Stop cond
130. interrupts and try to clear the flag R_POE_Control PDL_NO_DATA PDL_POE_FLAG_POE8_CLEAR PDL_POE_TRO_HI_Z_8_DISABL Figure 5 14 Example of Port Output Enable function R20UT2201EE0211 Rev 2 11 RENESAS Page 359 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 12 General PWM Timer Driver Figure 5 15 shows a usage example of General PWM Timer Driver Peripheral driver function prototypes tinclude r_pdl_gpt h tinclude r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void main void R_GPT_ControlChannel_structure gpt_ch_control_parameters R_GPT_Create_structure ch_create_parameters Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Configure GPT pins R_GPT_Set 0 PDL_GPT_PIN_GTIOCOA_P71 PDL_GPT_PIN_GTIOCOB_P74 di Power on the GPT unit R_GPT_CreateUnit 0 PDL_NO_DATA Y Load the defaults R_GPT_Create_load_defaults amp ch_create_parameters Set the non default options ch_create_parameters data2 PDL_GPT_MODE_ PT_CLK_PCLK_DIV_1 ch_create_parameters data6 PDL_GPT_A CM_ PDL_GPT_A LOW_LOW L_GPT_A_CYC ch_create_parameters data7 PDL_GPT_B C L_GPT_B_LOW_LOW PDL_GPT_B_CYC Configure cha
131. irq_status Falling edge detected if irq status amp 0x0C 0x04 Disable and invert the edge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IROO PDL_INTC_RISING PDL_INTC_DISABLE 3 else if irq status amp 0x0C 0x08 Disable and invert the edge interrupt R_INTC_ControlExtInterrupt PDL_INTC_IROO PDL_INTC_FALLING PDL_INTC_DISABLE y void SW2_handler void Handle the interrupt void SW3_handler void Handle the interrupt Figure 5 2 Example of External Interrupt R20UT2201EE0211 Rev 2 11 EN ESAS Page 339 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 3 1 0 Port Figure 5 3 shows examples of I O port configuration reading and writing Peripheral driver function prototypes tinclude r_pdl_io_port h RPDL device specific definitions tinclude r_pdl_definitions h void main void uint8_t result uintl6_t control_register Set all reserved I O port pins to the recommended state R_IO_PORT_NotAvailable Configure port 4 as an input R_IO_PORT_Set PDL_IO_PORT_4 PDL_IO_PORT_INPUT Configure port pin P22 as an open drain output R_IO_PORT_Set PDL_IO_PORT_2_2 PDL_IO_PORT_OUTPUT PDL_IO_PORT_TYPI y Read the value of all the pins on port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp result Set pin P22 to output high
132. kbps to 977 bps to dial 195 kbps 187 5 kbps 48 8 kbps 46 875 kbps 125 kbps 31 3 kbps The actual rise and fall times will not be zero Using the limits from the 12C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Fall time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are frcike MHz IRC 50 48 12 5 12 32 8 PCLKB 1 658 kbps to 635 6 kops 175 kbps to 168 5 kbps to 446 kbps to 116 kbps to 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB 2 316 kbps to 306 kbps to 86 7 kbps to 83 6 kbps to 217 kbps to 57 8 kbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps 1 Mbps PCLKB 4 175 kbps to 168 5 kbps 45 9 kbps to 44 2 kbps to 116 kbps to 30 0 kbps to i 1 Mbps to 1 Mbps 1 Mbps 1 Mbps 1 Mbps 806 kbps PCLKB 8 86 7 kbps to 83 6 kbps to 23 7 kbps to 22 7 kbps to 57 8 kbps to 15 3 kbps to i 1 Mbps 1 Mbps 658 kbps 635 6 kbps 1 Mbps 446 kbps PCLKB 16 45 9 kbps to 44 2 kbps to 12 0 kbps to 11 5 kbps to 30 0 kbps to 7 73 kbps to i 1 Mbps 1 Mbps 316 kbps 306 1 kbps 806 kbps 217 kbps PCLKB 32 23 7 kbps to 22 7 kbps to 6 06 kbps to 5 8 kbps to 15 3 kbps to 3 89 kbps to i 658 kbps 635 6 kbps 175 kbps 168 5 kbps 446 kbps 116 kbps PCLKB 64 12 0 kbps to 11 5 kbps to 3 04 kbps to 2 9kbpsto 7 73 kbps to 1 95 kbps to i 316 kbps 306 1 k
133. lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid otherwise false Category Interrupt control Reference R_INTC_Write Remarks Please see the notes on callback function use in 86 Specifying PDL_NO_FUNC for the callback function allows the software interrupt to be used as a DTC trigger Use R_INTC_Write to generate the software interrupt Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the software interrupt handler R_INTC_CreateSoftwarelnterrupt PDL_NO_DATA CallBackFunc 7 R20UT2201EE0211 Rev 2 11 EN ESAS Page 60 of 418 Sept 12 2014 RX63T Group 4 R_INTC_CreateFastinterrupt Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Rev 2 11 Enable faster interrupt processing for one interrupt bool R_INTC_CreateFastinterrupt uint8_t data data The interrupt to be selected 4 Library Reference Choose the interrupt vector to be processed using the fast interrupt process Some interrupt vectors are not existed in 64 and 48 pin packages Refer to Hardware manual section 15 Interrupt
134. mode is selected the source or destination side can be selected as the Repeat or Block area This selection is optional PDL_DMAC_SOURCE or PDL_DMAC_DESTINATION Address direction selection PDL_DMAC_SOURCE_ADDRESS_ FIXED or PDL_DMAC_SOURCE_ADDRESS PLUS or PDL_DMAC_SOURCE_ADDRESS_MINUS or Leave the source address unchanged increment it decrement it or modify it by the value specified in parameter data8 Rev 2 11 PDL_DMAC_ SOURCE ADDRESS OFFSET Address offset is valid only for n 0 PDL_DMAC_DESTINATION_ ADDRESS FIXED or meee ee ae PDL_DMAC_DESTINATION_ADDRESS_PLUS or nchanged increment it decrement PDL_DMAC_DESTINATION_ADDRESS_MINUS or y toy P parameter data8 PDL_DMAC_DESTINATION_ADDRESS_OFFSET Address offset is valid only for n 0 Transfer data size PDL_DMAC_SIZE_8 or PDL_DMAC_SIZE_16 or PDL_DMAC_SIZE_32 Select 8 16 or 32 bits for the data to be transferred Interrupt generation optional PDL_DMAC_IRQ_END Transfer completion PDL_DMAC_IRQ_ESCAPE END Escape end PDL_DMAC_IRQ_REPEAT_SIZE_END 1 repeat size or 1 block data transfer completion PDL_DMAC_IRQ_EXT_SOURCE Extended repeat area overflow on the source PDL DMAC IRQ EXT DESTINATION Extended repeat area overflow on the destination ENESAS Page 133 of 418 RX63T Group 4 Library Reference Description 2 4 Start trigger forwarding PDL_DMAC_TRIGGE
135. n 5 unless stated otherwise PDL_MTU3_MODE_ NORMAL or Normal operation PDL_MTU3_MODE_PWM1 or Pulse Width Modulation PWM mode 1 PDL_MTU3_MODE PWM2 or Pulse Width Modulation PWM mode 2 Valid for n 0 1 and 2 PDL_MTU3_MODE _PHASE1 or PDL_MTU3_MODE_PHASEZ2 or PDL_MTU3_MODE_PHASES3 or PDL_MTU3_MODE _PHASEA4 or Phase counting mode 1 2 3 or 4 Valid for n 1 and 2 Reset synchronised PWM mode Valid for n 3 and 6 See Remarks for setting up associate channels 4 and 7 PDL_MTU3_MODE_PWM_RS or PDL_MTU3_MODE_PWM_COMP1 or PDL_MTU3_MODE_PWM_COMP2 or PDL_MTU3_MODE_PWM_COMP3 Complementary PWM mode 1 2 or 3 Valid for n 3 and 6 See Remarks for setting up associate channels 4 and 7 e Synchronous mode Valid for n 5 PDL_MTU3_SYNC_DISABLE or PDL_MTU3_SYNC_ENABLE Disable or enable synchronous presetting clearing event_trigger_operation Configure the event trigger operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Rev 2 11 DMAC DTC event trigger control Valid for n 5 unless stated otherwise PDL_MTU3_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRA_DMAC_ TRIGGER ENABLE or PDL_MTU3_TGRA_DTC_ TRIGGER ENABLE TGRA compare match or input capture PDL_MTU3_TGRB_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRB_DMAC_ TRIGGER ENABL
136. or PDL_MCU_OFS_WDT_AUTOSTART Disable or enable the WDT auto start mode If auto start mode is enabled select one setting from each of the following e Timeout period PDL_MCU_OFS_WDT_TIMEOUT_1024 or PDL_MCU_OFS_WDT_TIMEOUT_4096 or PDL_MCU_OFS_WDT_TIMEOUT_8192 or PDL_MCU_OFS_WDT_TIMEOUT_ 16384 Timeout period specified in cycles of the divided clock as specified in the Clock Selection below e Clock division PDL MCU_OFS WDT_CLOCK_PCLK_4 or PDL_MCU_OFS_WDT_CLOCK_PCLK_64 or PDL MCU_OFS WDT_CLOCK _PCLK_ 128 or PDL MCU_OFS WDT_CLOCK PCLK_ 512 or PDL MCU_OFS WDT_CLOCK _PCLK_2048 or PDL MCU_OFS WDT_CLOCK PCLK_ 8192 The selected clock The PCLKB 4 64 128 512 2048 or 8192 e Window end position PDL_MCU_OFS_WDT_WIN_END_75 or The window end position specified as a PDL_MCU_OFS_WDT_WIN_END_50 or percent of the down counter 0 is when the PDL_MCU_OFS_WDT_WIN_END_25 or down counter would underflow Selecting 0 PDL_MCU_OFS_WDT_WIN_END_0 is equivalent to no window end position e Window start position PDL_MCU_OFS_WDT_WIN_START_25 or PDL_MCU_OFS_WDT_WIN_START_50 or PDL_MCU_OFS_WDT_WIN_START_75 or PDL_MCU_OFS_WDT_WIN_START_100 The window start position specified as a percent of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position e Underflow
137. pin PE2 PDL_IO PORT 2 6 Portpin P26 PDL_ IO PORT 9 0 Port pin P9 PDL_IO PORT_E 3 Port pin PE PDL_IO PORT 9 1 Port pin P94 PDL IO PORT_E 4 Port pin PE PDL_IO PORT_3 0 PortpinP3 PDL IO PORT 9 2 Port pin P92 PDL_ IO PORT_E 5 Port pin PEs PDL_IO_PORT_3 1 Port pin P34 PDL_IO_PORT_9 3 Port pin P93 PDL IO PORT 3 2 PortpinP32 PDL IO PORT_9 4 Port pin P94 PDL_IO PORT_F_O Port pin PFo PDL_IO PORT 3 3 PortpinP33 PDL_ IO PORT_9 5 Port pin P95 PDL_IO PORT_F 1 Port pin PF PDL_IO PORT_3 4 PortpinP3 PDL_IO PORT 9 6 Port pin P96 PDL_IO_PORT_F 2 Port pin PF gt PDL_IO PORT 3 5 Port pin P35 PDL_IO_PORT_F_3 Port pin PFs PDL_IO PORT_A O Port pin PAo PDL_IO _PORT_F 4 Port pin PF PDL_IO PORT 4 0 Portpin P4o PDL_IO PORT_A 1 Port pin PA PDL_IO_PORT_4 1 Port pin P44 PDL_IO PORT_A 2 Port pin PA2 PDL_IO PORT _G_O Port pin PGo PDL_ IO PORT_4 2 PortpinP42 PDL_IO PORT A 3 Port pin PAs PDL_ IO PORT_G 1 Port pin PG PDL_LIO PORT 4 3 PortpinP43 PDL IO PORT_A 4 Portpin PA PDL_IO PORT_G 2 Port pin PG2 PDL_IO PORT 4 4 Portpin P44 PDL_IO PORT_A 5 Port pin PAs PDL_IO PORT _G_3 Port pin PGs PDL_IO PORT 4 5 PortpinP4s5 PDL_IO PORT A 6 Port pin PAs PDL_IO PORT _G 4 Port pin PG PDL_IO PORT 4 6 Port pin P46 PDL_IO PORT _G_5 Port pin PGs PDL_IO PORT_4 7 PortpinP47 PDL_IO PORT B 0 Port pin PBo PDL_IO_PORT_G_6 Port pin PGs PDL IO PORT B 1 Port pin PB PDL_IO PORT_5 0
138. pins for the 12 bit ADC R_ADC_12 CreateUnit R_ADC_12 CreateChannel Configure the 12 bit ADC unit Configure 12 bit ADC analog channels R_ADC_12 Destroy Shut down the ADC unit R_ADC_12 Control Start or stop the ADC unit R_ADC_12 Read Read the ADC conversion results 10 bit Analog to Digital converter R_ADC_10_Set Select the I O pins for the 10 bit ADC R_ADC_10_CreateUnit Configure the 10 bit ADC unit R_ADC_10 CreateChannel Configure 10 bit ADC analog channels R_ADC_10_Destroy Shut down the ADC unit R_ADC_10_Control Start or stop the ADC unit R_ADC_10_Read Read the ADC conversion results 10 bit Digital to Analog converter R_DAC_10_Create Configure the 10 bit DAC module R_DAC_10_Destroy Disable a DAC channel R_DAC_10 Write Write data to a DAC channel Data Operation Circuit R20UT2201EE0211 Sept 12 2014 R_DOC Create Configure the Data Operation Circuit R_DOC_Destroy Disable the Data Operation Circuit R_DOC_Control Control the Data Operation Circuit AJOIN H PO H HD OT BH PO fH oO BR Go Po BR R_DOC_Read Read the Data Operation Circuit result 5 R_DOC_Write Write data to the Data Operation Circuit Rev 2 11 ENESAS Page 48 of 418 RX63T Group 4 Library Reference 4 2 Description of Each API This se
139. pointer to the data storage location A pointer to the data storage location A pointer to the data storage location A pointer to the data storage location Description 1 2 R20UT2201EE0211 Sept 12 2014 Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 7 data2 The status flags shall be stored in the format below The input capture compare match flags will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read Rev 2 11 Forn 0 b7 b6 b5 b4 b3 b2 b1 bO Detection 0 Overflow Input capture compare match V F E D C B A Forn 1 and 2 b7 b6 b5 b4 b2 b1 bO Count Detection direction Overflow Underflow Input capture compare match 0 down 0 1 up V U B A For n 3 and 6 b7 b6 b5 b4 b3 b2 bi bO Count Detection direction Overflow Input capture compare match 0 down V 0 D c B A 1 up For n 4 and 7 b7 b6 b5 b4 b3 b2 b1 bO Count Detection direction Overflow or underflow Input capture compare match 0 down 0 1 up V D C B A Forn 5 b7 b3 b2 bi bO Detection 0 Input capture compare match U V W data3 For n 5 A pointer to where the TCNT register value shall be stored For n 5 A pointer to where the TCNTU registe
140. priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Rev 2 11 EN ESAS Page 270 of 418 RX63T Group 4 Library Reference Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 True if all parameters are valid exclusive and achievable otherwise false 12C R_IIC_Create R_IIC_GetStatus R_IIC_MasterReceiveLast If a callback function is specified reception interrupts are used Please see the notes on callback function usage in 6 If the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated The last byte to be read shall be completed with a NACK signal If no callback function is specified this function will operate in polling mode The status flags will be used to manage the data reception If the 12C channel s control registers are directly modified by the user this function may lock up If an error occurs during this polling process the function will terminate If the DMAC or DTC is used use R_IIC_MasterReceiveLast to complete the transfer Use R_IIC_GetStatus to determine if the transfer was successful False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create False will be returned if the bus is busy due to another master on the bus Channel 1 is supported on 120 pin 144 pin packages only RPDL d
141. r_pdl_definitions h volatile uint8_t SCI1RxBuffer 9 SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCIlErrFunc void void func void uint8_t temp Wait for 1 character to be received on channel 0 R_SCI_Receive 0 PDL_NO_DATA amp temp 1 PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA SCI1RxBuffer 9 SCI1RxFunc SCI1ErrFunc R20UT2201EE0211 Rev 2 11 RENESAS Page 249 of 418 Sept 12 2014 RX63T Group 4 Library Reference 6 R_SCI_SPI_Transfer Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Perform an SPI transfer on an SCI channel bool R_SCI_SPI_Transfer uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Number of bytes to transfer uint8_t data4 Data transmit buffer void func Callback function Transmit Done uint8_t data5 Data receive buffer void func2 Callback function Receive Done void func3 Callback function Error Perform an SPI transfer This may be sending receiving or both sending and receiving data data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Control options The default options are
142. selection is not made the control setting will be left unchanged Specify PDL_NO_DATA if any pins of PORT 4 5 6 or C are selected for data1 Direction control PDL_IO_PORT_INPUT or PDL_IO_PORT_OUTPUT Input or output e Output type control PDL_IO_PORT_TYPE_CMOS or PDL_IO_PORT_TYPE_NMOS Select CMOS push pull output or N channel open drain Drive capacity control PDL_IO_PORT_DRIVE_BUS_NORMAL or PDL_IO_PORT_DRIVE_BUS_HIGH or PDL_IO_PORT_DRIVE_SPI_NORMAL or PDL_IO_PORT_DRIVE_SPI_HIGH Normal or high current drive Valid on packages with 100 pins or more Multiple pins may be affected Refer to the I O Port DSCR1 and DSCR2 register descriptions in the hardware manual True if all parameters are valid and exclusive otherwise false I O port R_IO_PORT_NotAvailable Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver functions Take care to not overwrite existing settings e Pin PE2 is fixed as an input and cannot be modified All pins that are not available on the selected package can be set to the required state using the R_IO_PORT_NotAvailable function RPDL definitions tinclude r_pdl_io_port h RPDL device specific definitions tinclude r_pdl_definitions h void func void Set up port P22 as an input port R_IO_PORT_Set
143. settings are shown in bold Transfer mode selection PDL_DTC_NORMAL or Normal or PDL_DTC_REPEAT or Repeat or PDL_DTC_BLOCK Block mode PDL_DTC_SOURCE or PDL_DTC DESTINATION If Repeat or Block mode is selected select the source or destination side to be the Repeat or Block area Address direction selection PDL_DTC_SOURCE_ADDRESS FIXED or PDL_DTC_SOURCE_ADDRESS PLUS or PDL_DTC_ SOURCE ADDRESS MINUS After a data transfer leave the source address unchanged increment it or decrement it PDL_DTC_DESTINATION_ADDRESS_FIXED or PDL_DTC_ DESTINATION ADDRESS PLUS or After a data transfer leave the destination address unchanged Rev 2 11 PDL_DTC_DESTINATION_ADDRESS_MINUS increment it or decrement it Transfer data size PDL_DTC_SIZE 8 or PDL_DTC_SIZE 16 or PDL_DTC SIZE 32 Select 1 2 or 4 bytes to be transferred in one operation Chain transfer control PDL_DTC_CHAIN_DISABLE or PDL_DTC_CHAIN_ CONTINUOUS or PDL_DTC_CHAIN_0 Disable chain transfer operation Perform continuous chain transfers or Perform a chain transfer when the transfer counter is changed from 1 to 0 or 1 to transfer size block size e Interrupt generation PDL_DTC_IRQ_COMPLETE or PDL_DTC_IRQ TRANSFER Select interrupt request generation when the transfer sequence completes or for every transfer Trigger selection Some triggers are not existed in 64 and 48
144. start address of the buffer that will receive the data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data Rev 2 11 EN ESAS Page 255 of 418 RX63T Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been transferred or an error occurs The function to be called when the transfer has completed or an error Transfer method Interrupts detected Either the function to be called when each byte is transferred or DMAC PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCI_GetStatus R_SCI_IIC_ReadLastByte R_SCI_Control The maximum number of characters to be received is 65535 e Wait until a transmission on the sam
145. the RX Standard Toolchain window In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you use this product a Set the optimisation To avoid linking unused RPDL functions adjust the Compiler and Linker settings i Compiler Select the C C tab Use the key sequence Y O O to show the optimisation options Ensure that the Inter module optimization option is enabled Configuration C C Assembly Link Library Standard Library RTOS 4 gt Debug_RX_E1_E20_ SYSTEM v Category Optimize gt y Fey All Loaded Projects a ipdl_lib M Optimize level H C source file 2 y Details H E C source file H Assembly source file Speed or size H E Linkage symbol file Optimize for size y IV Inter module optimization o external variables None y lt pu rx600 endian big dbl_size 8 include PROJDIR RPDL include S PROJDIR output obj CONFIGDIR S FILELEAF obj debug R20UT2201EE0211 Rev 2 11 AS Page 10 of 418 Sept 12 2014 RENES RX63T Group 1 Introduction ii Linker Select the Link Library tab Use the key sequence Y O O to show the optimisation options If the Eliminate dead code option is not enabled from the Optimize drop down list select Custom and enable the option Configuration Debug_RX_E1_E 20_SYSTEM v Cat E
146. the 12 bit ADC conversion result within the 16 bit register Ignored for channels using value addition mode the 14 bit result is always left aligned e Data accuracy PDL_ADC_12 PRECISION _12 or PDL_ADC_12 PRECISION_10 or PDL_ADC_12 PRECISION 8 Set the date accuracy of the 12 bit ADC conversion result to 12 bit 10 bit or 8 bit e Analog pin discharging PDL_ADC_12 DISCHARGE_DISABLE or PDL_ADC_12 DISCHARGE ENABLE Disable or enable analog pin discharging on completion of A D conversion Rev 2 11 ENESAS Page 297 of 418 RX63T Group Description 2 6 Result register clearing 4 Library Reference R20UT2201EE0211 Sept 12 2014 PDL_ADC_12 _ RETAIN_RESULT or PDL_ADC_12 CLEAR RESULT Retain or clear the value in each result register after it has been read Scan priority control for Group A valid on group s can mode PDL_ADC_12 GPA_PRIORITY_DISABLE or PDL_ADC_12 GPA PRIORITY ENABLE Disable or enable Group A priority control Sampling time PDL_ADC_12 ADSSTR_CALCULATE or PDL_ADC_12 ADSSTR_SPECIFY Select whether parameter data7 is used to calculate the ADSSTRO value or contains the value to be stored in register ADSSTRO Sampling time calculation for sample and hold circuit PDL_ADC_12 ADSHCR_ CALCULATE or PDL_ADC_12 ADSHCR_SPECIFY Select whether parameter data6 is used to calculate the ADSHCR value or contains the value to b
147. the ADC mode and operating condition data1 Select the ADC unit to be configured For all device packages this must be 0 data2 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Scan mode PDL_ADC_10_SCAN_SINGLE or PDL_ADC_10_SCAN_CONTINUOUS Select Single scan Continuous scan mode ADC value addition count selection PDL_ADC_10_VALUE_ADD_TIME_1 or PDL_ADC_10_VALUE_ADD_TIME_2 or PDL_ADC_10_VALUE_ADD_TIME_3 or PDL_ADC_10_VALUE_ADD_TIME_4 No addition Addition once Addition twice Addition three times Data alignment PDL_ADC_10_DATA_ALIGNMENT_RIGHT or PDL_ADC_10_DATA_ALIGNMENT_LEFT Data Register Bit Precision The alignment of the 10 bit ADC conversion result within the 16 bit register Ignored for channels using value addition mode the 12 bit result is always left aligned PDL_ADC_10_DATA_ACCURACY_10_BIT or PDL_ADC_10_ DATA ACCURACY 8 BIT Set the data accuracy of the 10 bit ADC conversion result to 10 bit or 8 bit Automatic clearing control PDL_ADC_10_RETAIN_RESULT or PDL_ADC_10_CLEAR_RESULT Disable or enable automatic clearing of ADDRy and ADRD after the register has been read Self diagnostic control PDL_ADC_10_DIAG_DISABLE or PDL_ADC_10_DIAG_VREFHO_ZERO or PDL_ADC_10_DIAG_VREFHO_HALF or PDL_ADC_10_DIAG_VREFHO_FULL or PDL_ADC_10_DIAG_V
148. the table below Specify PDL_NO_PTR if this information is not required Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Operation Mode Description Comparison The set comparison value Addition The addition result Subtraction The subtraction result True DOC None In Addition Mode the flag is set if the result of the addition exceeds FFFFh In Subtraction the flag is set if the result of the subtraction is less than zero In Comparison Mode the flag is set when the comparison criteria Match Mismatch is met If the flag is set it is automatically cleared by this function If using interrupts the flag is automatically cleared when the interrupt is handled RPDL definitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t status uint16_t result Read result R_DOC_Read amp status amp result ztENESAS Page 332 of 418 RX63T Group 5 R_DOC Write Synopsis Prototype Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference Write data to the Data Operation Circuit bool R_DOC_Write uint16_t data1 Pointer to buffer holding data to write uint16_t data2
149. time data register TDDR using the value supplied in parameter data8 PDL_MTU3_REGISTER_CYCLE_DATA PDL_MTU3_REGISTER_CYCLE_BUFFER the value supplied in parameter data9 Update the cycle data register TCDR using Update the cycle buffer register TCBR using the value supplied in parameter data10 ENESAS Page 171 of 418 RX63T Group Description 3 6 R20UT2201EE0211 Sept 12 2014 BDCM_sync_control The control settings which are specific to one pair of channels All settings are optional If multiple selections are required use to separate each selection Applies only to reset synchronised or complementary PWM modes 4 Library Reference e Brushless DC motor control applies only to channel pair 3 and 4 PDL_MTU3_BDCM_ENABLE or PDL_MTU3_BDCM DISABLE Enable or disable brushless DC motor control PDL_MTU3_BDCM_P_PHASE_ENABLE or Enable or disable PWM outputs on the PDL_MTU3_ BDCM_P_PHASE_DISABLE positive phase output pins PDL_MTU3_BDCM_N_PHASE_ENABLE or Enable or disable PWM outputs on the PDL_MTU3_BDCM_N_PHASE DISABLE negative phase output pins PDL MTU3 BDCM OPS FB or Use input capture signals for output switch control or PDL_MTU3_BDCM_OPS_000 or PDL_MTU3_BDCM_OPS_001 or PDL_MTU3_BDCM_OPS_010 or PDL_MTU3_BDCM_OPS_011 or Set the outputs according to table 22 46 in the PDL_MTU3_BDCM_OPS_100 or hardware manua
150. use this product Add the 11 Using library with debug information 103 R_LVD_Create User wants to use both LVD1 and LVD2 user must configure both LVD1 and LVD2 simultaneously 108 R_CAC_Create Remove extern in sample code 153 R_DTC_Getstatus Remove extern in sample code 155 R_MTU3_ Set Revise MTCLKA MTCLKB Valid when n 0 to 4 171 R_MTU3_ControlUnit Disable or enable counter clearing on TGRA compare match This must not be enabled if not in Complementary PWM Mode 1 176 R_MTU3_ControlUnit Add remark for PWM waveforms generation and output protection function in complementary PWM mode 213 214 Add R_GPT_EdgeDelay_Create 215 216 Add R_GPT_EdgeDelay_Control 2 10 Nov 08 2013 217 Add R_GPT_EdgeDelay_Destroy 247 257 SCI Correct sample code 264 R_IIC_Create Add remark When the digital noise filter circuit is enabled the ICBRL ICBRH register value should be equal or greater than lt the number of noise ilter steps 1 gt 309 R_ADC_12 Control Add remark Do not select CPU Off unless there is any interrupt to wake up the CPU 321 R_ADC_10_Control Add remark Do not select CPU Off unless there is any interrupt to wake up the CPU 361 Replace usage example of TPU by RWP 415 417 Add usage example for MTU and MPC 96 R_MCU_Control Remove On chip RAM control 230 R_IWDT_Set Add remark The IWDT counter frequency must not be greater than the PCLKB 4 2 11 Sept 12 2014 T i e S
151. valid otherwise false Category SPI Reference None Remarks Ifthe status flags are read and an error or fault flag is set to 1 the flag will be cleared to 0 by this function Program example RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t StatusValue Read the status of channel 0 R_SPI_GetStatus 0 amp StatusValue PDL_NO_PTR R20UT2201EE0211 Sept 12 2014 Rev 2 11 EN ESAS Page 291 of 418 RX63T Group 4 Library Reference 4 2 22 CRC calculator 1 R_CRC_Create Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Configure the CRC calculator bool R_CRC_Create uint8_t data Configuration Enable the CRC and set the operating conditions data Calculation options To set multiple options at the same time use to separate each value e Polynomial selection PDL_CRC_POLY CRC _8or XXX 1 PDL_CRC_POLY CRC _16or xe x4 XP pi PDL CRC POLY CRC CCITT X8 X X 1 Bit order PDL_CRC_LSB FIRST or PDL_CRC_MSB FIRST Select LSB or MSB first operation True if all parameters are valid and exclusive otherwise false CRC None None RPDL definitions inclu
152. valid unit is selected otherwise false Category 10 bit ADC Reference Remarks e This function includes a 1 ms delay to allow the ADC to stop any current scan cycle e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the ADC 0 unit R_ADC_10_Destroy 0 Y R20UT2201EE0211 Rev 2 11 EN ESAS Page 320 of 418 Sept 12 2014 RX63T Group 4 Library Reference 5 R_ADC 10 Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Start or stop an ADC unit bool R_ADC_10_Control uint8_t data Conversion unit control Start stop operation of the specified ADC data To select multiple options at the same time use to separate each value e On off control for unit O PDL_ADC 100 ON or Start a software triggered conversion PDL ADC _10_0 OFF Stop the undergoing conversion Control the CPU during the ADC conversion Stop the CPU when the conversion process starts POLAR Pear The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false 10 bit ADC R_AD
153. value uint16_t TADCOBRA_value uint16_t TADCOBRB_ value void func1 void func2 void func3 void func4 uint8_tinterrupt_priority_1 void func5 void func6 void func7 void func8 uint8_t interrupt_priority_2 uint8_t interrupt_priority_3 Set up a 16 bit MTU3 channel data1 The channel number n where n 0 to 7 Rev 2 11 Channel selection Apointer to the structure Configuration selection Configuration selection Configuration selection Configuration selection Configuration selection Configuration selection Configuration selection Configuration selection Register value Register value Register value Register value Register value Register value Register value Register value Register value Register value Register value Callback function Callback function Callback function Callback function Interrupt priority level Callback function Callback function Callback function Callback function Interrupt priority level Interrupt priority level ENESAS 4 Library Reference Page 156 of 418 RX63T Group Description 2 9 R20UT2201EE0211 Sept 12 2014 4 Library Reference channel_mode Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold e Operation mode Valid for
154. void func1 Callback function void fune2 Callback function void func3 Callback function void func4 Callback function Register the user functions to be called by the fixed vector and software interrupts func1 The function to be called when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an access exception is detected Specify PDL_NO_FUNC if no callback function is required func3 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required func4 The function to be called when a floating point exception is detected Specify PDL_NO_FUNC if no callback function is required True Interrupt control Please see the notes on callback function use in 86 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void UndefinedInstruction void void FloatingPointError void void func void Add a function to manage undefined instruction errors R_INTC_CreateExceptionHandlers PDL_NO_FUNC PDL_NO_FUNC UndefinedInstruction FloatingPointError
155. voltage drops below a voltage threshold 2 Controlling the detection circuits 3 Reading the status of the detection circuits R20UT2201EE0211 Rev 2 11 AS Page 24 of 418 Sept 12 2014 RENES RX63T Group 2 Driver 2 9 Clock Frequency Accuracy Measurement Circuit Driver The driver functions support access to the registers which control the Clock Frequency Accuracy Measurement Circuit These functions support 1 Configuring the operation 2 Stopping the operation 3 Modifying the operation 4 Reading the status R20UT2201EE0211 Rev 2 11 RENESAS Page 25 of 418 Sept 12 2014 RX63T Group 2 Driver 2 10 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation 2 Selecting one of the low power modes 3 Writing data to the backup memory area 4 Reading data from the backup memory area 5 Determining the cause of the exit from the lowest power mode R20UT2201EE0211 Rev 2 11 RENESAS Page 26 of 418 Sept 12 2014 RX63T Group 2 Driver 2 11 Register Write Protection Driver The driver functions support the control of the Register Write Protection providing the following operations 1 Enabling or disabling writing to the registers 2 Reading the status of the write protection R
156. width PDL_BSC_WIDTH 8 or PDL_BSC_WIDTH_16 Select 8 16 bit data bus width Endian mode PDL_BSC_ENDIAN_SAME or PDL_BSC_ENDIAN_OPPOSITE Set the bus endian mode to be the same or opposite to that of the CPU e Multiplexed mode PDL_BSC_SEPARATE or PDL_BSC_MULTIPLEXED Select separate or multiplexed address and data pins e Write access mode PDL_BSC_WRITE_BYTE or PDL_BSC_WRITE_SINGLE Select byte or single write strobe mode External wait control PDL_BSC_WAIT_DISABLE or PDL_BSC_WAIT_ENABLE Disable or enable external wait control using the WAIT signal e Page access control PDL_BSC_PAGE_READ_DISABLE or PDL_BSC_PAGE_READ_NORMAL or PDL_BSC_PAGE_READ_CONTINUOUS Disable or enable page read accesses using normal access compatible mode or continuous assertion mode PDL_BSC_PAGE_WRITE_DISABLE or PDL_BSC_PAGE WRITE ENABLE Disable or enable page write accesses data3 The number of read recovery cycles RRCV Valid between 0 and 15 data4 The number of write recovery cycles WRCV Valid between 0 and 15 Rev 2 11 ENESAS Page 127 of 418 RX63T Group Description 2 2 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference data5 The number of wait cycles used for second and subsequent accesses during a page read sequence CSPRWAIT
157. will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false 12 bit ADC R_ADC_12 CreateUnit and R_ADC_12_CreateChannel For single scan mode the ADC will stop automatically when the conversion is complete Set Group B to be restarted after getting discontinued due to Group A priority control must be work on the group scan with option PDL_ADC_12_GPA_PRIORITY_ENABLE Single cycle scans through group B are continuously activated must be work on the group scan with option PDL_ADC_12_GPA_PRIORITY_ENABLE The Unit 1 is valid on device packages with 100 pins or more Do not select CPU Off unless there is any interrupt to wake up the CPU RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Start the ADC conversion process R_ADC_12 Control PDL_ADC_12_0_ON i R20UT2201EE0211 Rev 2 11 EN ESAS Page 309 of 418 Sept 12 2014 RX63T Group 4 Library Reference 6 R_ADC 12 Read Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Read the ADC conversion results bool R_ADC_12 Read uint8_t data1 ADC unit selection uinti6_t data2 Pointer to the address where the results are to be stored uint16_t data3 Pointer to the address where t
158. writing to LPC Main clock oscillator forced oscillation Mode and Reset registers PDL_RWP_ENABLE_LVD_WRITE or PDL_RWP_DISABLE_LVD_WRITE Enable or disable writing to LVD registers PDL_RWP_ENABLE_MPC_WRITE or PDL_RWP_DISABLE_MPC_WRITE Enable or disable MPC Register access True if the parameter is valid otherwise false RWP Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 To allow for nested function calls the access to the enabling disabling of register protection is done using a reference counting method Hence a call to disable a register access may only decrement a reference counter and not actually apply the write protection Other RPDL functions automatically enable and disable access to registers as required so this function is normally not required RPDL definitions include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void func void Enable access to the LVD registers R_RWP_Control PDL_RWP_ENABLE LVD_WRITE Y ENESAS Page 121 of 418 RX63T Group 4 Library Reference 2 R_RWP_GetStatus Synopsis Get the status of the register protection Prototype bool R_RWP_GetStatus uint8_t data1 Status flags pointer uint8_t data2 Status flags pointer Description Get the status of the register pr
159. 0 3 4 6 or 7 Compare match or input capture U on MTU channel 5 PDL_DMAC_TRIGGER_MTUVA or PDL_DMAC_TRIGGER_MTUV5 or PDL_DMAC_TRIGGER_MTUV7 or Compare match or input capture V on MTU channel 5 Counter over or underflow V on MTU channel 4 and 7 PDL_DMAC_TRIGGER_MTUW5 or Compare match or input capture W on MTU channel 5 PDL_DMAC_TRIGGER_CMPO or Interrupt request from Comparator 0 PDL_DMAC_TRIGGER_CMP1 or Interrupt request from Comparator 1 PDL_DMAC_TRIGGER_CMP2 or Interrupt request from Comparator 2 PDL_DMAC_TRIGGER_CMP4 or Interrupt request from Comparator 4 PDL_DMAC_TRIGGER_CMP5 or Interrupt request from Comparator 5 PDL_DMAC_TRIGGER_CMP6 or Interrupt request from Comparator 6 PDL_DMAC_TRIGGER_IICO_RX or PDL_DMAC_TRIGGER_IIC1_RX or Receive buffer full on 12C channel n n 0 to 1 PDL_DMAC_TRIGGER_IICO_TX or PDL_DMAC_TRIGGER_IIC1_TX or Transmit buffer empty on I12C channel n n 0 to 1 PDL_DMAC_TRIGGER GPTAO or PDL_DMAC_TRIGGER_GPTA1 or PDL_DMAC_TRIGGER_GPTA2 or PDL_DMAC_TRIGGER_GPTA3 or PDL_DMAC_TRIGGER_GPTA4 or PDL_DMAC_ TRIGGER GPTA5 or PDL_DMAC_ TRIGGER GPTAG or PDL_DMAC_TRIGGER_GPTA7 or Compare match or input capture A on GPT channel n n 0 to 7 PDL_DMAC_TRIGGER_GPTBO or PDL_DMAC_TRIGGER_GPTB1 or PDL
160. 0 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend IIC_CHANNEL PDL_IIC_STOP_DISABLI EPROM _ADDRESS eprom_data_array_l e 1 P r DL_NO_FUNC R20UT2201EE0211 Rev 2 11 AS Sept 12 2014 RENES Page 398 of 418 RX63T Group 5 Usage Examples Read data from the EEPROM using the DTC read_eeprom_data Prepare to read the next data R_DTC_Control PDL_DTC_UPDATE DESTINATION PDL_DTC_UPDATE_COUNT dtc_iicl_rx_transfer_data PDL_NO_PTR amp data_storage ARRAY_1_SIZE 1 ARRAY_2_SIZE 2 Array size written sub address byte last byte PDL_NO_DATA Read data from the EEPROM using the DTC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM using the DTC R_IIC_MasterSend IIC_CHANNEL PDL _IIC_DTC_TRIGG EEPROM _ADDRESS PDL_NO_PTR 0 iic_tx_end_handler 7 di while bus_busy true uint32_t iic_flags uintl6_t flags uint32_t sre uint32_t dest uint16_t counter R_DTC_Get Status dtc_iicl_tx_transfer_data amp flags E SIC dest amp counter PDL_NO_PTR Y R_IIC_GetStatus IIC_CHANNEL amp iic_flags PDL_NO_PTR PDL_NO_PTR Y Wait for 5ms while the EEPROM updates R_CMT_CreateOneS
161. 1 2 Driver 2 23 Serial Peripheral Interface Driver The driver functions support the use of the SPI channel providing the following operations 1 Selection of the SPI pins for use 2 Configuration for use including e Automatic clock setting using transfer rate as an input 3 Disabling channels that are no longer required and enabling low power mode 4 Configuration of command sequence settings 5 Managing the transfer of data on the interface including e Automatic interrupt control e Automatic DMAC DTC control 6 Control of special modes such as loopback 7 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any SPI channel Rev 2 11 EN ESAS Page 39 of 418 Sept 12 2014 RX63T Group 2 Driver 2 24 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Preparation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R20UT2201EE0211 Rev 2 11 RENESAS Page 40 of 418 Sept 12 2014 RX63T Group 2 Driver 2 25 12 bit Analog to Digital Converter Driver The driver functions support the use of the 12 bit ADC unit providing the following operations 1 2 6 I O pin configuration Unit specific configuration
162. 1 EN ESAS Page 369 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 3 SCI Asynchronous Using DMAC This shows the setting of a SCI channel and transmission of data using the DMAC Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h PDL device specific definitions Pp include r_pdl_definitions h include lt stddef h gt include lt string h gt if defined DEVICE_PACKAGE_64_PIN amp amp defined D E_PACKAG define CHANNEL_SCI 1 else define CHANNEL SCI 0 endif const uint8_t string Hello from Renesas RX63T SCI DMAC r n void main void uint8_t SCI_status Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set up SCI Async 8N1 19200 baud R_SCI_Create CHANNEL SCI PDL_SCI_ASYNC PDL_SCI_8N1 19200 1 0 Configure channel 3 of DMAC to be triggered by SCI Tx R_DMAC_Create 3 PDL_DMAC_ REPEAT PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_ FIXED PDL_DMAC_SIZE_8 if defined DEVICE PACKAGE 64 PIN amp amp defined DEVICE _PACKAGE PDL_DMAC_TRIGGER_SCI1_TX string Source const char SCIl TDR Destination else PDL_DMAC_TRIGGER_SCIO_TX string Source const char SCIO TDR
163. 1 func2 and funcs True if all parameters are valid and exclusive and the selected clocks have been set otherwise false Clock frequency accuracy measurement circuit e If the external input CACREF pin is selected the Multifunction Pin Control registers are modified to enable the selected pin Before using this function call R_CGC_Set for each clock that will be measured or used as a If both edges are selected the clock duty cycle is assumed to be 50 The PDL_CAC_CACREF_PORT_0_0 pin is valid on packages with 100 pins or more The PDL_CAC_CACREF_PORT_0_1 pin is valid on packages with 64 pins There is a CACREF pin restriction when using the 48 pin device package After applying the selected dividers the clock to be measured divided by the reference clock must be gt 0 and lt h 10000 Furthermore if specifying a permissible deviation the resulting permissible range must also fit within these limits This function will return false if this is not the case If a frequency error callback function is specified then it must clear the error flag using R_CAC_ Control to prevent continuous interrupts callbacks If a measurement complete callback function is specified then it must clear the measurement flag using R_CAC_Control to prevent continuous interrupts callbacks e f an overflow callback function is specified then it must clear the overflow flag using R_CAC_ Control to prevent continuous interrup
164. 11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for parameter func2 Return value Sept 12 2014 True if all parameters are valid and exclusive otherwise false Category 12 bit ADC References R_CGC_ Set R20UT2201EE0211 Rev 2 11 LEN ESAS Page 302 of 418 RX63T Group 4 Library Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 6 If an external trigger is used the low level pulse width must be at least 1 5 PCLK cycles This function brings the converter unit out of the power down state A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Function R_CGC_Set must be called with the current clock source selected before using this function In group scan mode the two ADC groups should not share the same trigger source For more details of the MTU or GPT trigger options please refer to the RX63T hardware manual This function will return false if an invalid unachievable sampling time is specified Make sure sampling time calculated or specified for channel O and self diagnosis are the same RPDL definitions
165. 12 CreateUnit and R_ADC_12 CreateChannel From 1 to 8 valid conversion results will be read and stored to the array specified by data2 The number depends on the parameters supplied to R_ADC_12_CreateUnit and R_ADC_12 CreateChannel for configuration The values stored to the array specified by data3 depend on the ADC mode In self diagnostic mode the diagnostic result is stored into the first place In double trigger mode the double trigger result is store into the first place In extended double trigger mode the result from synchronous trigger A is stored into the second place and that from synchronous trigger B is stored into the third place The data alignment is controlled using the R_ADC_12_CreateUnit e If no callback function is used this function waits for the IR flag to indicate that conversion is complete before reading the results If the ADC unit s control registers are directly modified by the user this function may lock up Rev 2 11 EN ESAS Page 310 of 418 RX63T Group 4 Library Reference Program example RPDL definitions tinclude r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t ADCresult 8 Read the ADC R_ADC_12_Read 0 ADCresult PDL_NO_DATA PDL_NO_DATA R20UT2201EE0211 Rev 2 11 Sept 12 2014 7 ENESAS Page 311 of 418 RX63T Group 4 2 24 10 bit Analog to Dig
166. 16_t data2 Configuration selection double data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Control the CPU during the one shot operation PDL_CMT_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts Ia rar The CPU will re start when any valid interrupt occurs DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNC this function will wait for the timer to complete before returning You should always specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC_ Se
167. 1EE0211 Rev 2 11 QEN ESAS Page 348 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 8 2 Bus controller for the 100 pin 112 pin 120 pin and 144 pin package Figure 5 10 shows an example of external bus controller usage Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void BSC_error_handler void void main void volatile uint8_t cs0_location_38 volatile uint8_t csl_location_8 volatile uint16_t cs2_location_16 volatile uint16_t cs3_location_16 Point to respective external memory areas cs3_location_16 uint16_t 0x05000000ul cs2_location_16 uint16_t 0x06000000ul csl_location_8 uint8_t 0x07000000ul cs0_location_8 uint8_t 0xFFO00000ul Initialise the system clocks including the external bus clock NOTE The code to initialise the system clocks using R_CGC_Set is omitted here Configure the bus priority R_BSC_Set PDL_BSC_PRIORITY_PB1_MB1 i Configure area 0 R_BSC_CreateArea 0 PDL_BSC_WIDTH_8 15 15y 7 7 31 31 7 Configure area 1 R_BSC_CreateArea 1 PDL_BSC_WIDTH_8 PDL_BSC_WRITE_ R20UT2201EE0211 Rev 2 11 RENESAS Page 349 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Y Configure area 2
168. 2 R20UT2201EE0211 Sept 12 2014 Configure the voltage detection circuit bool R_LVD_Create uint16_t data1 Monitor 1 Configuration selection uint8_t data2 Monitor 1 Voltage selection uint16_t data3 Monitor 2 Configuration selection uint8_t data4 Monitor 2 Voltage selection Set the voltage detection configuration data1 Monitor 1 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection e Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or PDL_LVD INTERRUPT_NMI_DETECT_RISE or PDL_LVD INTERRUPT_NMI_DETECT_FALL or PDL_LVD INTERRUPT_NMI_DETECT_RISE_AND_FALL Select no action a reset on low voltage detection or non maskable interrupt when a specified voltage event is detected Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD FILTER_LOCO DIV_8 data2 Monitor 1 voltage detection level For device packages with 48 or 64 pins this fixed at 2 95V specify PDL_NO_DATA e Voltage levels applicable for 3V products Specify PDL_NO_DATA to use the default PDL_LVD_VOLTAGE_LEVEL_288 or PDL_LVD_VOLTAGE_LEVEL_285 or PDL _LVD_ VOLTAGE LEVEL 290 Set the voltage detection level e Voltage levels applicable for
169. 201EE0211 Rev 2 11 LEN ESAS Page 137 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_DMAC_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Disable the DMA controller bool R_DMAC_Destroy uint8_t data Channel number Shutdown the DMAC module data The channel number n where n 0 to 3 True if the shutdown succeeded otherwise false DMA controller R_DMAC_Create e If all channels have been suspended the DMAC module will be shut down Disabling the DMAC module will also shut down the DTC e If another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown DMAC channel 2 R_DMAC_Destroy 2 Rev 2 11 ENESAS Page 138 of 418 RX63T Group 4 Library Reference 3 R_DMAC_Control Synopsis Control the DMA controller Prototype bool R_DMAC_ Control uint8_t data1 Channel number uint16_t data2 Control options void data3 Source start address void data4 Destination start address uint16_t data5 Transfer cou
170. 20UT2201EE0211 Rev 2 11 RENESAS Page 27 of 418 Sept 12 2014 RX63T Group 2 12 Bus Controller Driver The driver functions support the control of the internal bus providing the following operations R20UT2201EE0211 Sept 12 2014 i 2 Setting the internal and External bus operation Configuration of the controller Configuration of the eight address space areas Disabling an area that is not required Controlling the bus controller Reading the status of the controller Rev 2 11 ENESAS 2 Driver Page 28 of 418 RX63T Group 2 Driver 2 13 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of a channel 4 Reading the status and operation registers of a channel R20UT2201EE0211 Rev 2 11 AS Page 29 of 418 Sept 12 2014 RENES RX63T Group 2 Driver 2 14 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations R20UT2201EE0211 Sept 12 2014 As 2 Setting the central options Configuration for use including support for chain transfers Disabling the controller Starting stopping or modifying the operation of the c
171. 3T Group 4 Library Reference Description 2 2 Return value Category Reference Remarks Program example func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer Parameter method PDL_NO_FUNC This function will continue until the required number of bytes Pollin 9 has been transferred or an error occurs Interrupts The function to be called when the transfer has completed or an error detected Either the function to be called when each byte is transferred or PDL_NO_FUNC DMAG if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_DMAC_Create R_DTC_Create R_SCI_ Control The maximum number of characters to be transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed e This function unless configured not to will by default automatically star
172. 4 Library Reference Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Declared in the R_DTC_Create example uint32_t dtc_cmt0_ transfer _datal void func void uint16_t StatusValue uint32_t SourceAddr Read the status and current source address for the CMTO transfer E R_DTC_GetStatus dtc_cmt0_transfer_data amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT2201EE0211 Rev 2 11 EN ESAS Page 153 of 418 Sept 12 2014 RX63T Group 4 2 13 Multi Function Timer Pulse Unit 1 R_MTU3_Set Synopsis Prototype bool R_MTU3_Set uint8_t data1 uint32_t data2 Description 1 2 Set up the global MTU options R20UT2201EE0211 Sept 12 2014 data1 4 Library Reference Configure the Multi function Timer Pulse Unit Channel selection Configuration for a channel The channel number n where n 0 to 7 data2 Pin configuration for the channel Use to separate each selection Valid when n 0 PDL_MTU3_PIN_0A_P31 or PDL_MTU3_PIN_OA_PB3 Select the P31 or PB3 pin for MTIOCOA PDL_MTU3_PIN_0B_P30 or PDL_MTU3_PIN_O0B_PB2 Select the P30 or PB2 pin for MTIOCOB PDL_MTU3 PIN 0C PB1 Select the PB1 pin for MTIOCOC PDL_MTU3_PIN_OD_PBO Select the PBO pin for MTIOCOD
173. 5 or PDL SPI FRAME 6 or PDL SPI FRAME 7 or PDL_SPI FRAME 8 1 ONOaRWNNH HH 2a 32424 anNaaAg0on ONODOARWANARWND Parity bit control PDL_SPI_PARITY_NONE or PDL_SPI_PARITY_EVEN or PDL_SPI_PARITY_ODD Disable or enable the addition of the parity bit data4 Extended timing control optional All items apply only to Master mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA if not required e Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or PDL_SPI_SSL_DELAY_4 or PDL_SPI_SSL_DELAY_5 or PDL_SPI_SSL_DELAY_6 or PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY 8 The number of bit clock periods between the end of RSPCK oscillation and the negation of the active SSL pin Ignored in Slave mode Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or The number of bit clock periods plus t
174. 6 and MTU7 in data4 RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure R_MTU3_ControlUnit_structure unit_parameters Load the defaults R_MTU3_ControlUnit_load_defaults amp unit_parameters Set the control options for unit 0 unit_parameters simultaneous_control PDL_MTU3_START_CH_O PDL_MTU3_START_CH_1 unit_parameters pair_control PDL_MTU3_DEAD_TIME_ENABLE PDL_MTU3_REGISTER_DEAD_TIME PDL_MTU3_REGISTER_CYCLE_DATA unit_parameters output_control PDL_MTU3_OUT_P_PHASE_ALL_HIGH_LOW unit_parameters DT_data_value OxFFDD unit_parameters data_value 0x0100 Modify the operation of unit 0 R_MTU3_ControlUnit 0 amp unit_parameters Rev 2 11 EN ESAS Page 176 of 418 RX63T Group 4 Library Reference 6 R_MTU3_ReadChannel Synopsis Prototype Read from MTU channel registers bool R_MTU3_ReadChannel uint8_t data1 uint8_t data2 uint16_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 Channel selection Apointer to the data storage location Apointer to the data storage location Apointer to the data storage location Apointer to the data storage location A
175. 7 and PDL POE _HI_ Z MT67_ADD_POE8 A valid POE8 GPT channel 4 to 6 PDL POE HI Z MT67_ADD_POE10 edge on POE10 outputs PDL POE_HI_Z MT67_ADD POE11 the pin POE11 PDL POE_HI_Z MT67_ADD_POE12 POE12 data4 Select the output pins to be controlled If multiple selections are required use to separate each selection All selections are optional Specify PDL_NO_DATA if none are required PDL_POE_HI_Z ENABLE _MTIOCOA PDL POE HI Z ENABLE MTIOCOB PDL POE _HI Z ENABLE MTIOCOC PDL POE HI Z ENABLE MTIOCOD MTU channel 0 Input pin or event high impedance request software control or the oscillation stop detection flag Rev 2 11 ENESAS Page 181 of 418 RX63T Group 4 Library Reference Description 3 4 PDL_POE_HI_Z ENABLE _MTIOC7BD MTU channel 6 and 7 GPT channel 4 5 and 6 PRE FOE Hl Z ENABLE MTIOCTAC Input pin or event high impedance request output PDL POE HI Z ENABLE MTIOC6BD short detection software control or the oscillation ahaa a stop detection flag PDL_POE_HI_Z ENABLE _MTIOC4BD MTU channel 3 and 4 PDL_POE_HI_Z ENABLE _MTIOC4AC GPT channel 0 1 and 2 Input pin or event high impedance request output PDL POE HI Z ENABLE MTIOC3BD short detection software control or the oscillation 7 stop detection flag PDL_POE_HI_Z ENABLE _GTIOCO PDL POE HI Z ENABLE _GTIOC1 GPT channel pins A and B PDL_POE HI Z ENABLE_GTIOC2 Input pin or event high impedance request PDL_POE_HI_
176. 8 RX63T Group 4 Library Reference Program example RPDL definitions include r pdl_isei h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t SCIlRxBuffer 9 SCI channel 1 receive data handler void SCI1 RxFunc void SCI channel 1 error handler void SCIlErrFunc void void func void Wait while send 5 characters on channel 0 R_SCI_SPI_Transfer 0 PDL_NO_DATA 5 512345 PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC Start the transmission and reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA SCI1RxBuffer 9 SCI1RxFunc SCI1ErrFunc R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS Page 252 of 418 RX63T Group 4 Library Reference 7 R_SCI_IIC_Write Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Perform an IIC master write on an SCI channel bool R_SCI_IIC_Write uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave Address uint16_t data4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master write data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages
177. 8_t bus_busy volatile uint8_t data_storage 20 Reserve an area for the DIC vector table pragma address dtc_vector_table 0x00002000 uint32_t dtc_vector_table 256 Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 void main void define ARRAY 1 SIZ define ARRAY 2 SIZI 6 5 Data 1 address 11 10 Data 1 address ry aly const uint8_t eeprom_data_array_1 ARRAY_1_SIZE EEPROM_MEMORY_ADDRESS_LOWER 0x11 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 ARRAY_2_ SIZE EEPROM_MEMORY_ADDRESS_LOWER 5 0x66 0x77 0x88 0x99 OxAA OxBB OxCC OxDD OXEE OxFF uint8_t 1 Initialise the system clocks NOTI The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Dis Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table Set up a DTC channel for IIC transmission R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_ FIXED PDL_DTC_SIZE_8 PDL_DTC_IRQ COMPLETE PDL_DTC_TRIGGER_IICO_TX dtc_iicl_tx_transfer_data eeprom_data_array_l uint8_t amp RIICO ICDRT ARRAY_1_SIZI
178. A if not required Valid on packages with 100 pins or more Pin selection for channel 1 PDL_SPI_RSPCKB_P24 or PDL_SPI_RSPCKB_PA4 or PDL_SPI_RSPCKB_PDO Select the RSPCKB pin PDL_SPI_MOSIB_P23 or PDL_SPI_MOSIB_PBO or PDL_SPI_MOSIB_PD2 Select the MOSIB pin PDL_SPI_MISOB_P22 or PDL_SPI_MISOB_PA5 or PDL_SPI_MISOB PD1 Select the MISOB pin PDL_SPI_SSLBO_P30 or PDL_SPI_SSLBO_PA3 or PDL_SPI_SSLBO_PD6 Select the SSLBO pin optional PDL_SPI_SSLB1_P31 or PDL_SPI_SSLB1_PA2 or PDL_SPI_SSLB1_PD7 Select the SSLB1 pin optional PDL_SPI_SSLB2_P32 or PDL_SPI_SSLB2_PEO or PDL_SPI_SSLB2_PA1 Select the SSLB2 pin optional PDL_SPI_SSLB3_P33 or PDL_SPI_SSLB3_PE1 or PDL_SPI_SSLB3_PAO Select the SSLB3 pin optional True if all parameters are valid otherwise false SPI R_SPI_ Create Before calling R_SPI_Create call this function to configure the relevant pins e Please refer to the Multifunction Pin Controller MPC section in the RX63T Hardware Manual for details of SPI pin selection Pins which are not used for the SPI functions may be omitted Same pin cannot be used for different pin functions Not all device packages have all of the pin options RPDL definitions tinclude r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Configure the applicable SPI pin
179. ABLI 125E3 125E3 125E3 125E3 125E3 125E3 125E3 PDL_NO_DAT PDL_NO_DA1 y Configure main clock operation using a 12 0 MHz crystal ICLK 3 MHz PCLKA 3 MHz PCLKB 3 MHz PCLKC 3 MHz PCLKD 3 MHz FCLK 3 MHz R_CGC_Set L_CGC_CLK_MAIN L_CGC_BCLK_DISABLI Oo x DOAODO O Fl L_NO_DAT L_NO_DAT VUHAHAHAAANUDI P P jl 3 3 3 3 3 3 P P Configure PLL operation The PLL will be set to 150 MHz ICLK 75 MHz PCLKA 75 MHz PCLKB 37 5 MHz PCLKC 37 5 MHz PCLKD 37 5E6 MHz FCLK 37 5E6 MHz _Set PDL_CGC_CLK_PLL PDL_CGC_BCLK_DISABLI 150 751 75 Hao es endif Allow time for the main clock and PLL oscillator to stabilise This example uses the CMT timer running from the LOCO to generate a 100us delay Generate the 100us delay R_CMT_CreateOneShot 0 PDL_NO_DATA 100E 6 PDL_NO_FUNC R20UT2201EE0211 Rev 2 11 AS Page 336 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples Select the PLL as the clock source R_CGC_Control PDL CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Figure 5 1 Example of Clock configuration and control R20UT2201EE0211 Rev 2 11 AS Page 337 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 2 Interrupt control Figure 5 2 shows an example of exte
180. AC trigger is enabled remember to enable the appropriate interrupt request Return value True if all parameters are valid and exclusive otherwise false Category General PWM Timer unit R20UT2201EE0211 Rev 2 11 ENESAS Page 191 of 418 Sept 12 2014 RX63T Group 4 Library Reference Reference R_GPT_CreateChannel Remarks The callback function for external trigger and IWDTCLK event interrupts is specified using function func6 when R_GPT_CreateChannel is used to configure GPT channel 0 or 4 Program example RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void R_GPT_CreateUnit 0 PDL_GPT_IWDTCLK_INT_RISING_ENABLE R20UT2201EE0211 Rev 2 11 AS Page 192 of 418 Sept 12 2014 RENES RX63T Group 3 R_GPT_CreateChannel Synopsis Prototype uint8_t data1 4 Library Reference Configure a GPT channel bool R_GPT_CreateChannel Channel selection R_GPT_Create_structure ptr A pointer to the structure R_GPT_Create_structure members uint32_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint32_t data6 uint32_t data7 uint32_t data8 uint32_t data9 uint32_t data10 void func1 void func2 void func3 uint8_t data11 void func4 void func5 void func6 uint8_t data12 Description 1 7 Setup a GPT channel R20
181. ADC 12 CH GAIN 10 000 or PDL ADC 12 CH GAIN 13 333 Rev 2 11 EN ESAS Page 304 of 418 RX63T Group Description 2 2 4 Library Reference data4 Comparator options Valid for Channel 0 1 and 2 only To set multiple options at the same time use to separate each value The default settings are shown in bold e Comparator mode PDL_ADC_12_CMP_OFF or PDL_ADC_12_CMP_LOW or PDL_ADC_12_CMP_HIGH or PDL_ADC_12_CMP_WINDOW Set the comparator on the channel to be inactive or working in low high or window mode Sampling frequency for Comparator PDL_ADC_12 CMP_SAMPLE_DISABLE or PDL_ADC_12 CMP_SAMPLE_PCLK or PDL_ADC_12 CMP_SAMPLE_PCLK_1_2or PDL_ADC_12 CMP_SAMPLE_PCLK_1_4 or PDL_ADC_12 CMP_SAMPLE_PCLK_1_8or PDL_ADC_12 CMP_SAMPLE_PCLK_1_16 or PDL ADC _12 CMP_SAMPLE _PCLK 1 128 Diable sampling of comparator detection result or set the sampling frequency to be PCLK PCLK 2 PCLK 4 PCLK 8 PCLK 16 or PCLK 128 POE trigger by Comparator PDL_ADC_12_CMP_POE_DISABLE or Disable or enable activation PDL_ADC_12_CMP_POE_ENABLE of POE by Comparator e DTC DMAC trigger by Comparator PDL_ADC_12 CMP_DMAC_DTC_TRIGGER_DISABLE or PDL_ADC_12 CMP_DMAC_TRIGGER_ENABLE or PDL ADC 12 CMP_DTC_TRIGGER_ENABLE Disable or enable activation of DMAC or DTC data5 The data to be used for the sampling st
182. ASCADE_AL_IC_INC_H input capture conditions for channel n 1 Exclude or include pin MTIOCnA in the TGRA Exclude or include pin MTIOCnB in the TGRB input capture conditions for channel n 1 PDL MTU3 CASCADE AH IC EXC Lor PDL_MTU3_CASCADE_AH IC_INC_L Exclude or include pin MTIOC n 1 A in the TGRA input capture conditions for channel n PDL MTU3 CASCADE BH _IC_ EXC Lor PDL_MTU3_ CASCADE BH_IC_INC_L Exclude or include pin MTIOC n 1 B in the TGRB input capture conditions for channel n Rev 2 11 ENESAS Page 161 of 418 RX63T Group Description 7 9 TGR_C_D operation R20UT2201EE0211 Sept 12 2014 4 Library Reference Configure the operation for general registers TGRC and TGRD Valid for n 0 3 4 6 and 7 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture output compare control for register TGRC PDL_MTU3_C_OC_DISABLED or PDL_MTU3_C_OC_LOW or PDL_MTU3_C_OC_LOW_CM_HIGH or PDL_MTU3_C_OC_LOW_CM_INV or PDL_MTU3_C_OC_HIGH_CM_LOW or PDL_MTU3_C_OC_HIGH or PDL_MTU3_C_OC_HIGH_CM_INV or MTIOCHNC output disabled MTIOCHNC output low MTIOCHC initial output low goes high at compare match MTIOCHKC initial output low toggles at compare match MTIOCnC initial output high goes low at compare match MTIOCnC output high MTIO
183. A_IC_BOTH_EDGES both edges Additional output settings for pin GTIOCnA Required only if Compare match is enabled PDL_GPT_A LOW LOW or PDL_GPT_A_LOW_HIGH or PDL_GPT_A HIGH LOW or PDL_GPT_A_ HIGH HIGH or PDL_GPT A RETAIN PDL GPT A CYCLE RETAIN or PDL _GPT_A CYCLE LOW or PDL_GPT_A CYCLE HIGH or PDL_GPT_A_CYCLE_INVERT Set the output states at counter start and stop At the timer cycle end the output is retained set low set high or toggled data7 I O pin control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Compare match Input capture selection for pin GTIOCnB PDL_GPT_B_DISABLED or Not used or PDL_GPT_B_CM_RETAIN or PDL_GPT_B_CM_LOW or PDL_GPT_B_CM_HIGH or PDL_GPT_B_CM_INVERT or At a compare match the output is retained set low set high or toggled or PDL_GPT_B_IC_RISING_EDGE or PDL_GPT_B_IC_FALLING_EDGE or PDL_GPT_B_IC_BOTH EDGES Input capture at rising edge falling edge or both edges e Additional output settings for pin GTIOCnB Required only if Compare match is enabled PDL_GPT_B_LOW_LOW or PDL_GPT_B_LOW_HIGH or PDL_GPT_B_HIGH LOW or PDL_GPT_B_ HIGH HIGH or PDL_GPT_B_RETAIN Set the output states at counter start and stop PDL_GPT_B_CYCLE_RETAIN or PDL_GPT_B_CYCLE_LOW or At the timer
184. Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test f
185. B3 else PDL_SCI_PIN_SCIO_TXDO_P30 PDL_SCI_PIN_SCIO_SCKO_P23 endif R_SCI_Set 1 if defined DEVICE_PACKAGE_64_PIN amp amp defined DEVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1_SCK1_PD4 else PDL_SCI_PIN_SCI1_RXD1_P93 PDL_SCI_PIN_SCI1_SCK1_P92 endif Y Create Master Channel R_SCI_Create MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_RX DISCONNECTED PDL _SCI_CLK_INT_OUT 19200 1 0 R20UT2201EE0211 Rev 2 11 RENESAS Page 372 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Create Channel slave NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R_SCI_Create SLAVE_CHANNEL PDL_SCI_SYNC PDL_SCI_TX_DISCONN PDL_SCI_CLK_EXT 0x80000000 19200 1 0 y Set flag to wait on data_received false Setup a read on channel slave R_SCI_Receive SLAVE_CHANNEL PDL_NO_DATA rx_buffer 5 SCIORxFunc PDL_NO_FUNC di Send the data from the master R_SCI_Send MASTER_CHANNEL PDL_NO_DATA 12345 5 PDL_NO_FUNC Y Wait for channel slave to receive while data_received false Process the received data here while 1 SCI channel 0 receive complete handler static void SCIORxFunc v
186. BCLK_DIV_2 or BCLK 2 or PDL_CGC_BCLK_DISABLE disable the BCLK signal data3 The frequency of the selected clock source in Hertz data4 The desired frequency of the System clock ICLK in Hertz data5 The desired frequency of the Peripheral module A clock PCLKA in Hertz data6 The desired frequency of the Peripheral module B clock PCLKB in Hertz data7 The desired frequency of the Peripheral module C clock PCLKC in Hertz Ignored for packages with 48 or 64 pins data8 The desired frequency of the Peripheral module D clock PCLKD in Hertz data9 The desired frequency of the Flash memory interface clock FCLK in Hertz data10 The desired frequency of the External Bus clock BCLK in Hertz If the external bus will not be used specify PDL_NO_DATA Ignored for packages with 48 or 64 pins R20UT2201EE0211 Rev 2 11 2tEN ESAS Page 50 of 418 Sept 12 2014 RX63T Group Description 2 2 4 Library Reference data11 The desired frequency of the USB clock UCLK in Hertz If the USB will not be used specify PDL_NO_DATA Ignored for packages with 48 or 64 pins Return value True if all parameters are valid and exclusive otherwise false For RX63T the following rules are checked where applicable Category References Remarks R20UT2201EE0211 Sept 12 2014 e For 48 and 64 pin packages fmain_cLo
187. BLE or PDL_GPT_CMICA_DMAC_TRIGGER_ENABLE or PDL_GPT_CMICA DTC TRIGGER ENABLE GTCCRA compare match or input capture PDL_GPT_CMICB_DMAC_DTC_TRIGGER_DISABLE or PDL_GPT_CMICB_DMAC_TRIGGER_ENABLE or PDL_GPT_CMICB DTC TRIGGER ENABLE GTCCRB compare match or input capture PDL_GPT_CMCDDTE_DMAC_DTC_TRIGGER_DISABLE or PDL_GPT_CMCDDTE_DMAC_TRIGGER_ENABLE or PDL_GPT_CMCDDTE_DTC_TRIGGER_ENABLE GTCCRC or GTCCRD input capture or Dead time error PDL_GPT_CMEF_DMAC_DTC_TRIGGER_DISABLE or PDL_GPT_CMEF_DMAC_TRIGGER_ENABLE or PDL_GPT_CMEF_DTC_TRIGGER_ENABLE GTCCRE or GTCCRF input capture PDL_GPT_OU_DMAC_DTC_TRIGGER_DISABLE or PDL_GPT_OU_DMAC_TRIGGER_ENABLE or PDL_GPT_OU_DTC_TRIGGER_ENABLE Counter overflow or underflow If a DTC or DMAC trigger is enabled remember to enable the appropriate interrupt request data3 Interrupt and data transfer options If multiple selections are required use to separate each selection The default settings are shown in bold Event interrupt request selection PDL_GPT_IRQ_A_DISABLE or PDL_GPT_IRQ_A_ENABLE GTCCRA input capture or compare match PDL_GPT_IRQ_B_DISABLE or PDL_GPT_IRQ_B_ENABLE GTCCRB input capture or compare match PDL_GPT_IRQ_C _DISABLE or PDL_GPT_IRQ_C ENABLE GTCCRC compare match PDL_GPT_IRQ_D_DISABLE or PDL_GPT_IRQ_D ENABLE GTCCRD compare match PDL_GPT_IRQ_E_DISABLE or PDL_GPT_IR
188. CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Initialise flags data_sent false data_received false Set pin options R_SCI_Set CHANNEL SCI if defined DEVICE_PACKAGE 64 PIN amp amp defined DEVICE _PACKAG PDL_SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1_TXD1_PD3 telse PDL_SCI_PIN_SCIO_RXDO_P24 PDL_SCI_PIN_SCIO_TXDO_P30 tendif i Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create CHANNEL SCI PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 0 Y Send message register callback to say when sent R_SCI_Send CHANNEL_SCI PDL_NO_DATA r nHello Type 5 characters and I will echo them back r n 0 SCItx Y Wait for message to be sent while false data_sent R20UT2201EE0211 Rev 2 11 EN ESAS Page 368 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Start a pending read of 5 characters R_SCI_Receive CHANNEL_SCI PDL_NO_DATA rx_buffer 5 SCIrx PDL_NO_FUNC Y Wait for characters to be received while false data_received Echo the 5 characters back R_SCI_Send CHANNEL_SCI PDL_NO_DATA rx_buffer 5 PDL_NO_FUNC void SCIrx void data_received true void SCItx void data_sent true Figure 5 21 Example of SCI Asynchronous operation using interrupts R20UT2201EE0211 Rev 2 1
189. CHKC initial output high toggles at compare match PDL_MTU3_C_IC_RISING_EDGE or PDL_MTU3_C_IC_FALLING_EDGE or PDL_MTU3_C_IC_BOTH_EDGES or Input capture at MTIOCnC rising edge Input capture at MTIOCnC falling edge Input capture at MTIOCnC both edges PDL_MTU3_C_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 Input capture output compare control for register TGRD PDL_MTU3_D_OC_DISABLED or PDL_MTU3_D_OC_LOW or PDL_MTU3_D_OC_LOW_CM_HIGH or PDL_MTU3_D_OC_LOW_CM_INV or PDL_MTU3_D_OC_HIGH_CM_LOW or PDL_MTU3_D_OC_HIGH or PDL_MTU3_D_OC_HIGH_CM_INV or MTIOCHND output disabled MTIOCHND output low MTIOCHKD initial output low goes high at compare match MTIOCHKD initial output low toggles at compare match MTIOCHKD initial output high goes low at compare match MTIOCHND output high MTIOCHKD initial output high toggles at compare match PDL_MTU3_D_IC_RISING_EDGE or PDL_MTU3_D_IC_FALLING_EDGE or PDL_MTU3_D IC _BOTH_EDGES or Input capture at MTIOCnD rising edge Input capture at MTIOCnD falling edge Input capture at MTIOCnD both edges PDL_MTU3_D_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 TGR_U_V_W_ operation Configure the input capture compare match control for general registers TGRU TRGV and TGRW Valid for n 5 The default settings are shown in bo
190. CNTU_value Register value uint16_t TGRA_TCNTV_value Register value uint16_t TGRB_TCNTW_value Register value uint16_t TGRC_TGRU_value Register value uint16_t TGRD_TGRV_value Register value uint16_t TGRE_TGRW_value Register value uint16_t TGRF_value Register value uint16_t TADCOBRA_value Register value uint16_t TADCOBRB_ value Register value Modify a timer channel s registers data1 The channel number n where n 0 to 7 control_setting The channel settings to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop start Valid for n 5 PDL_MTU3_STOP Stop the count operation PDL_MTU3_START Start the count operation e Counter stop Start Valid for n 5 PDL_MTU3_STOP_U PDL_MTU3 STOP_V Stop the count operation PDL_MTU3 STOP_W PDL_MTU3 START _U PDL MTU3_START_V Start the count operation PDL_MTU3 START _W register_selection The channel registers to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no register change is required The registers to be modified Forn 5 PDL_MTU3 REGISTER_COUNTER Timer counter register TCNT PDL_MTU3_REGISTER_TGRA General register A PDL_MTU3_REGISTER_TGRB General register B PDL_MTU3_REGISTER_TGRC G
191. C_10 CreateUnit R ADC_10 CreateChannel e For single scan mode the ADC will stop automatically when the conversion is complete e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only e Do not select CPU Off unless there is any interrupt to wake up the CPU RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Start the ADC conversion process R_ADC_10_Control PDL_ADC_10_0_ON Y Rev 2 11 EN ESAS Page 321 of 418 RX63T Group 4 Library Reference 6 R_ADC_10_ Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Read the ADC conversion results bool R_ADC_10_Read uint8_t data1 ADC unit selection uint16_t data2 Pointer to the address where the results are to be stored uint16_t data3 Pointer to the buffer where the self diagnostic result is to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit This must be 0 for all device packages data2 Specify a pointer to an array where the converted values for analog input channels are to be stored The array length must gt the number of channels 20 for device packages with 144 pin otherwise 12 Specify PDL_NO_PTR if this information is not req
192. C_ADDRESS_SHORT Select 32 bit full or 24 bit short address mode data2 The first address of the area of on chip RAM where the DTC vector table shall be stored The address must be on a 1 kB boundary True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Before calling R_DTC_Create call this function RPDL definitions tinclude r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00000400 uint32_t dtc_vector_table 256 void func void Configure the controller R_DTC_Set PDL_DTC_ADDRESS_SHORT dtc_vector_table Rev 2 11 EN ESAS Page 144 of 418 RX63T Group 2 R_DTC_ Create Synopsis Prototype Description 1 4 R20UT2201EE0211 Sept 12 2014 Configure the Data Transfer Controller for a transfer bool R_DTC_Create uint32_t data1 uint32_t data2 void data3 void data4 uint16_t data5 uint8_t data6 Configuration selection Source start address Transfer count Block size Configure DTC activation for one trigger source data1 Configuration selections Destination start address 4 Library Reference Transfer data start address If multiple selections are required use to separate each selection The default
193. C_DTC_TRIGGER_DISABLE or PDL_ADC_12 GP_DMAC_TRIGGER_ENABLE or PDL_ADC_12 GP_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC data4 data6 Additional options for two ADC groups in group scan mode In other operating modes only data4 is valid applying to all the working ADC channels GPT trigger source selection Valid only if PDL_ADC_12_SYNC_TRIGGER_ENABLE is selected and no MTU trigger source is specified in data3 data5 otherwise the following options are ignored Trigger source for the GPTO GPT3 PDL_ADC_12 GP_TRIGGER_GPT_GTADTRAON or PDL_ADC_12_GP_TRIGGER_GPT_GTADTRBON or Compare match with GPTO GTADTRA Compare match with GPTO GTADTRB PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA1N or Compare match with GPT1 GTADTRA PDL_ADC_12 GP_TRIGGER_GPT_GTADTRB1N or Compare match with GPT1 GTADTRB PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA2N or Compare match with GPT2 GTADTRA PDL_ADC_12 GP_TRIGGER_GPT_GTADTRB2N or Compare match with GPT2 GTADTRB PDL_ADC_12_GP_TRIGGER_GPT_GTADTRASN or Compare match with GPT3 GTADTRA PDL_ADC_12_GP_TRIGGER_GPT_GTADTRB3N or Compare match with GPT3 GTADTRB PDL_ADC_12_GP_TRIGGER_GPT_GTADTRAON_BON or Compare match with GPTO GTADTRA or with GPTO GTADTRB PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA1N_B1N or PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA2N_B2N or Compare match with GPT1 GTADTRA or with GPT1 GTADTRB Compare match with GPT2
194. Control e Use R_POE_Control to clear the flags The status flags of POE4 and MTU6 7 are not available on the 64 and 48 pin packages The status flag of POE12 is not available on the 100 64 and 48 pin packages RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t StatusFlags Read the POE status R_POE_GetStatus amp StatusFlags ENESAS Page 188 of 418 RX63T Group 4 2 15 General PWM Timer 1 R_GPT Set Synopsis Select the I O pins for the GPT unit Prototype bool R_GPT_Set uint8_t data1 uint16_t data2 Description 1 2 Set up the global GPT options R20UT2201EE0211 Sept 12 2014 data1 4 Library Reference Channel selection Configuration options The channel number n where n 0 to 3 for 64 and 48 pin packages n 0 to 7 for 144 120 112 100 pin packages data2 Pin configuration for the channel To set multiple options at the same time use to separate each value e Valid when n 0 PDL_GPT_PIN_GTIOCOA_P71 or PDL_GPT_PIN_GTIOCOA_PD7 Select P71 or PD7 for GTIOCOA PDL_GPT_PIN_GTIOCOB_P74 or PDL_GPT_PIN_GTIOCOB_PD6 Select P74 or PD6 for GTIOCOB e Valid when n 1 PDL_GPT_PIN_GTIOC1A_P72 or PDL_GPT_PIN_GTIOC1A_PD5 Select P72 or PD5 for GTIOC1A PDL_GPT_PIN_GTIOC1B_P75 or PDL_G
195. DC_10 PIN AN19 PC5 Select PC5 for AN19 BL e n ai pales ae Select P22 or PG5 for ADTRG Return value False if an invalid pin selection is made otherwise True Category 10 bit ADC Reference R_ADC_10_CreateUnit Remarks e If there are I O pins to be used call this function before calling R_ADC_10_CreateUnit Not all device packages have all of the pin options Do not specify an option that does not exist for the device package being used e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS Page 312 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Set analog channel ANO R_ADC_10_Set PDL_ADC_10_PIN_ANO_P60 Y R20UT2201EE0211 Rev 2 11 EN ESAS Page 313 of 418 Sept 12 2014 RX63T Group 2 R_ADC 10 CreateUnit Synopsis Prototype Description 1 3 R20UT2201EE0211 Sept 12 2014 Configure the 10 bit ADC unit bool R_ADC_10_CreateUnit Unit selection Unit specific options uint8_t data1 uint32_t data2 4 Library Reference uint32_t data3 Options for trigger double data4 Sampling time for self diagnosis void func Callback function uint8_t data5 Interrupt priority level Set
196. DL_LVD VOLTAGE LEVEL 290 Set the voltage detection level Voltage levels applicable for 5V products Specify PDL_NO_DATA to use the default PDL_LVD_VOLTAGE_LEVEL_450 or PDL_LVD_VOLTAGE_LEVEL_ 423 or PDL_LVD_VOLTAGE LEVEL 477 Set the voltage detection level True if the parameters are valid otherwise false Voltage detection circuit R_INTC_CreateExtInterrupt R_CGC_Set R_LPC_Create R_CGC_Control If a non maskable interrupt will be generated call R_INTC_CreateExtInterrupt to set up the NMI handler and to accept LVD based interrupt signals If using the digital filter function R_CGC_Set must be called with the current clock source selected before using this function If using the digital filter the LOCO clock must be enabled Use R_CGC_Set with the LOCO selected Following a reset function R_LPC_GetStatus can be used to see what caused the reset If using a delay on Reset negation then the LOCO clock must be enabled See R_CGC_Set or R_CGC_Control Ensure Monitor 1 and 2 are in PDL_LVD_MONITOR_ONLY during flash memory programming erasure Disable the digital filter circuit when using voltage monitoring 1 and 2 circuit in software standby mode or deep software standby mode Do not use the voltage detection 1 and 2 circuit in deep software standby mode with PDL_LPC_DEEPCUT_RAM_USB_LVD See function R_LPC_Create If using both LVD1 and LVD2 must configure both LVD1 and LVD2 simultaneously RPDL
197. DL_NO_DATA if the extended repeat function is not required for the destination address func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false DMA controller None If another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral Some peripheral channels are not available on some device packages Please check the hardware manual Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Rev 2 11 EN ESAS Page 136 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void Configure DMA channel 2 R_DMAC_Create 2 PDL_DMAC_NORMAL PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZE_8 PDL_DMAC_TRIGGER_IROO void 0x0000AA00 void 0x0000BBOO 10 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 R20UT2
198. DL_NO_FUNC PDL_NO_FUNC 6 Rev 2 11 EN ESAS Page 185 of 418 RX63T Group 3 R_POE_Control Synopsis Control the Port Output Enable module Prototype bool R_POE_Control uint16_t data1 uint16_t data2 uint16_t data3 Control options Control options Control options Description 1 2 Change the state of output pins status flags and interrupt control R20UT2201EE0211 Sept 12 2014 data1 Manual high impedance control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required MTU GPT channel output high impedance control 4 Library Reference PDL_POE_MTU34_HI_Z_ON or PDL_POE_MTU34_HI_Z_OFF channel 3 4 outputs Control the high impedance state of the MTU PDL_POE_MTU67_HI_Z_ON or PDL_POE_MTU67_HI_Z_OFF channel 6 7 outputs Control the high impedance state of the MTU PDL_POE_MTUO_HI_Z_ON or PDL_POE MTUO HI Z OFF channel 0 outputs Control the high impedance state of the MTU PDL_POE_GPT01_HI_Z ON or Control the high impedance state of the GPT PDL_POE_GPT01_HI_Z OFF channel 0 and 1 outputs PDL_POE_GPT23_HI_Z ON or Control the high impedance state of the GPT PDL_POE GPT23 HI Z OFF channel 2 and 3 outputs PDL_POE_GPT67_HI_Z_ ON or Control the
199. Destination endif 1 uint16_t strlen char string PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PD 0 L_NO_FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 370 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Enable DMAC R_DMAC_Control 3 PDL_DMAC_ENABL PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Start transmission R_SCI_Send CHANNEL_SCI PDL_SCI_DMAC_TRIGGER_ENABLE PDL_NO_PTR PDL_NO_DATA No data as using DMAC PDL_NO_FUNC BRK k ke k ke k de ke He ke He e He KKK He e He e He e He de He KEK KKK KKK He e He e He e He e He He He e He He He He ke He ke He ke He ke He e He e He e He e ke e ke e ke IMPORTANT The SCI module does not know when the DMAC has finished therefore we must tell it using the R_SCI_Control function HK e He e KKK IK KK KK KKK He e KKK KKK KK KKK KK KKK KK e He e He KKK KKK KKK ke He e He e He e He e He KARA ke ke k ke Wait for the SCI transmission to end do R_SCI_GetStatus CHANNEL _ SCI amp SCI_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR While the Transmit status BIT_2 is not reporting idle while SCI_status amp 0x04 0 Stop the SCI R_SCI_Control CHANNEL_SCI PDL_SCI_STOP_TX Send using polling mode
200. E 64 PIN amp amp defined DEVICE_PACKAGI PDL_SCI_PIN_SCI1_SSCL1_PD5 PDL_SCI_PIN_SCI1_SSDA1_PD3 else PDL_SCI_PIN_SCI1_SSCL1_P93 PDL_SCI_PIN_SCI1_SSDA1_P94 endif Y Setup the SCI IIC channel R_SCI_Create CHANNEL SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 0 Y Configure the DTC controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table R20UT2201EE0211 Rev 2 11 RENESAS Page 386 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Set current EEPROM address TIC_Buffer 0 EEPROM_ADDRESS Use blocking function for this DTC will be used for the data part R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_SCI_IIC_NOSTOP SLAVE_ADDRESS 1 TIC_Buffer PDL_NO_FUNC Y Set flag data_received false Read data from current EEPROM address using DTC Start with an IIC Re start DTC on Rx R_DTC_Create PDL_DTC_NORMAL PDL_DTC_DESTINATION_ADDRESS_PLUS PDL _DTC_SOURCE_ADDRESS_ FIXED PDL _DTC_SIZE_8 PDL_DTC_IRQ COMPL PDL_DTC_TRIGGER_SCI1_RX dtc_iicl_rx transfer _data uint8_t SCI1 RDR Source IIC_Buffer Destination Data length is one less than we want to read as use R_SCI_IIC_ReadLastByte 4 PDL_NO_DATA Y DTC on Tx To write the dummy data out
201. E Control interrupts on detection of a high PDL_POE_IRQ_HI_Z_11_ENABLE impedance request on pin POE11 PDL_POE IRQ HI Z 12 DISABLE Control interrupts on detection of a high PDL_POE_IRQ_HI Z 12 ENABLE impedance request on pin POE 12 Rev 2 11 ENESAS Page 186 of 418 RX63T Group Description 2 2 4 Library Reference Output short detection response Return value Category Reference Remark Program example R20UT2201EE0211 Sept 12 2014 PDL_POE IRQ SHORT_34 DISABLE Control interrupts on detection of a short on any PDL_POE_IRQ_SHORT_34 ENABLE MTU channel 3 4 two phase output pair PDL POE IRQ _SHORT_67 DISABLE Control interrupts on detection of a short on any PDL_POE_IRQ_SHORT_67 ENABLE MTU channel 6 7 two phase output pair True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE_Create Call R_POE_Create before using this function Clearing a level triggered event flag will fail if the trigger is still asserted Interrupt disabling is processed at the start of the function and enabling is processed at the end This allows a flag to be cleared and the interrupt re enabled in one function call All settings related to POE4 GPT6 7 and MTU6 7 are not available on the 64 and 48 pin packages All settings related to POE12 are not available on the 100 64 and 48 pin packages The settings PDL_POE_MTU34_HI_Z_ ON OFF PD
202. E or PDL_MTU3_ TGRB_DTC_ TRIGGER ENABLE TGRB compare match or input capture PDL_MTU3_TGRC_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRC_DMAC_TRIGGER_ENABLE or PDL_MTU3_TGRC_DTC_TRIGGER_ENABLE TGRC compare match or input capture Valid for n 0 3 4 6 and 7 PDL_MTU3_TGRD_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRD_DMAC_TRIGGER_ENABLE or PDL_MTU3_TGRD_DTC_TRIGGER_ENABLE TGRD compare match or input capture Valid for n 0 3 4 6 and 7 PDL_MTU3_TCIV_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TCIV_DMAC_TRIGGER_ENABLE or PDL_MTU3 TCIV DTC TRIGGER ENABLE DMAC DTC event trigger control Valid for n 5 Counter overflow or underflow Valid for n 4 and 7 PDL_MTU3_TGRU_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRU_DMAC_TRIGGER_ENABLE or PDL_MTU3_TGRU_DTC_TRIGGER_ENABLE TGRU compare match or input capture PDL_MTU3_TGRV_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRV_DMAC_TRIGGER_ENABLE or PDL_MTU3_TGRV_DTC_TRIGGER_ENABLE TGRV compare match or input capture PDL_MTU3_TGRW_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU3_TGRW_DTC_TRIGGER_ENABLE or PDL_MTU3_TGRW_DTC_TRIGGER_ENABLE TGRW compare match or input capture ENESAS Page 157 of 418 RX63T Group 4 Library Reference Description 3 9 counter_operation Configure the counter operation If multiple selections are required use to separate each selection The default settings
203. EFERENCE_PCLK or Peripheral module clock PDL_CAC_REFERENCE_IWDTLOCO or IWDT low speed on chip oscillator or PDL_CAC_REFERENCE_CACREF input to pin CACREF as the reference signal Reference signal edge selection PDL_CAC_REFERENCE_RISING or Select rising edges PDL_CAC_REFERENCE_FALLING or falling edges or PDL_CAC_ REFERENCE _BOTH both rising and falling edges to be valid Reference signal division selection PDL_CAC_REFERENCE_DIV_32 or PDL_CAC_REFERENCE_DIV_128 or PDL_CAC_REFERENCE DIV_1024 or PDL_CAC REFERENCE DIV_ 8192 If an internal clock is used as the reference signal divide it by 32 128 1024 or 8192 Ignored if the CACREF input is selected Measured clock selection PDL_CAC_MEASURE_MAIN or Select the Main clock oscillator PDL_CAC_MEASURE_PCLK or Peripheral module clock or PDL_CAC_MEASURE_IWDTLOCO IWDT low speed on chip oscillator for measurement e Measured clock division selection PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or Divide the clock to be measured by 1 4 8 or PDL_CAC_MEASURE_DIV_8 or 32 PDL_CAC_ MEASURE DIV_32 R20UT2201EE0211 Rev 2 11 RENESAS Page 110 of 418 Sept 12 2014 RX63T Group 4 Library Reference Description 2 2 Limit value calculation Return value Category References PDL_CAC_LIMIT_TOLERANCE or Parameters data3 and data4 will contain either PDL_CAC_LIMIT_REGISTER the tolerance
204. FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 363 of 418 Sept 12 2014 RX63T Group 5 Usage Examples R_CMT_Control 0 PDL ART 0 now start CMTO R_CMT_Control 1 PDL now stop CMT1 while 1 void CMTO_handler void Toggle the LEDO state R_IO_PORT_Modify PDL_IO_PORT_7_1 PDL_IO_PORT_XOR 1 void CMT1_handler void Toggle the LED1 state R_IO_PORT_Modify PDL_IO_PORT_7_2 PDL_IO_PORT_XOR 1 Figure 5 18 Example of Compare Match Timer use R20UT2201EE0211 Rev 2 11 AS Page 364 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 16 Independent Watchdog Timer Figure 5 19 shows an example of Independent Watchdog timer usage At start up the underflow is checked to identify if the the reset was caused by the Independent Watchdog timer The watchdog timer is then configured for a 1024 count timeout period and started Because the watchdog timer is not refreshed after two seconds this depends on the frequency of the on chip oscillator the MCU is reset and the underflow condition is detected Peripheral driver function prototypes include r_pdl_iwdt h PDL device specific definitions include r_pdl_definitions h void main void uint16_t Status Read the timer status R_IWDT_Read Status Y Has an underflow occurred if Status BIT_14 0x0u Handle the watchdog induced reset here
205. G All Loaded Projects 5 5 MEMES Show entries for E C source file Optimize items al C source file Assembly source file Optimize Custom v Eliminated size 0x001E H E Linkage symbol file iminate dead code iminate same code DOptimize branches Use short dispeimm om D R D_1 R_1 D_2 R_2 nomessage noprelink ist CONFIGDIR S PROJECTNAME map show all optimize symbol_delete R20UT2201EE0211 Rev 2 11 AS Page 11 of 418 Sept 12 2014 RENES RX63T Group b Set the floating point precision 1 Introduction The wide range of possible internal clock frequencies requires double precision floating point number storage Select the CPU tab Click on the Details button to open the CPU details window Use the drop down menu to select Double precision Double precision KA Sign of char unsigned y Sign of bit field unsigned y Bit field order Rott y Width of divergence of function 24bt v Denomalized number allower as a result enum size is made the smallest Pack struct union and class J Use try throw and catch of C Use dynamic_cast and typeid of C The saved and restored code of the accumulator in interrupt function Click on OK to close the window Click on OK to return to the main HEW window 10 Build the project No further configuration should be required Simply build the project R20UT2201EE0211 Rev 2 11 AS Sept 12 2014 RENES
206. GTADTRA or with GPT2 GTADTRB PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA3N_B3N or Compare match with GPT3 GTADTRA or with GPT3 GTADTRB ENESAS Page 300 of 418 RX63T Group Description 5 6 4 Library Reference e Trigger source selection for the GPT4 GPT7 valid on packages with 100 pins or more R20UT2201EE0211 Sept 12 2014 PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA4N or Compare match with GPT4 GTADTRA Compare match with PDL_ADC_12_GP_TRIGGER_GPT_GTADTRBAN or GPT4 GTADTRB PDL_ADC_12_GP_TRIGGER_GPT_GTADTRASN or Compare match with GPT5 GTADTRA PDL_ADC_12 GP_TRIGGER_GPT_GTADTRB7N or Compare match with GPT7 GTADTRB Compare match with PDL_ADC_ 12 GP_TRIGGER_GPT_GTADTRA4N_B4N or GPT4 GTADTRA or with GPT4 GTADTRB Compare match with PDL_ADC_12_GP_TRIGGER_GPT_GTADTRAS5N_BS5N or GPT5 GTADTRA or with GPT5 GTADTRB Compare match with PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA6N_B6N or GPT6 GTADTRA or with GPT6 GTADTRB Compare match with PDL_ADC_12 GP_TRIGGER_GPT_GTADTRA7N_B7N GPT7 GTADTRA or with GPT7 GTADTRB data7 Camparator control selection If multiple selections are required use to separate each selection Specify PDL_NO_DATA if not required Comparator internal REFL selection PDL_ADC_12_CMP_VSELLO_ANO003 or PDL_ADC_12_CMP_VSELLO_INTERNAL Set the voltage on ANOO3 or the selected internal voltage as the REFL for comparator PDL_ADC_12_CMP_VSELHO_ANO07 or PDL_ADC_12_CM
207. GTCIB PDL_INTC_REG_IR_SCI1_RXI PDL_INTC_REG_IR_GPT2_GTCIC PDL_INTC_REG_IR_SCI1_TXI PDL_INTC_REG_IR_GPT2_GTCIE PDL_INTC_REG_IR_SCI2_RXI PDL_INTC_REG_IR_GPT2_GTCIV PDL_INTC_REG_IR_SCl2_TXl PDL_INTC_REG_IR_GPT3_ GTCIA PDL_INTC_REG_IR_SCI2 TEI PDL_INTC_REG_IR_GPT3_GTCIB PDL_INTC_REG_IR_SCI3_RXI PDL_INTC_REG_IR_GPT3_GTCIC PDL_INTC_REG_IR_SCI3_TXI PDL_INTC_REG_IR_GPT3_GTCIE PDL_INTC_REG_IR_SCI3_TEI PDL_INTC_REG_IR_GPT3_GTCIV PDL_INTC_REG_IR_GPTO_GTCIA PDL_INTC_REG_IR_SCI12_RXI PDL_INTC_REG_IR_GPTO_GTCIB PDL_INTC_REG_IR_SCI12 TXI PDL_INTC_REG_IR_GPTO_GTCIC PDL_INTC_REG_IR_SCI12 TEI IER register definitions PDL_INTC_REG_IERO2 PDL_INTC_REG_IER12 PDL_INTC_REG_IEROS PDL_INTC_REG_IER13 PDL_INTC_REG_IER04 PDL_INTC_REG_IER14 PDL_INTC_REG_IERO5 PDL_INTC_REG_IER15 PDL_INTC_REG_IERO7 PDL_INTC_REG_IER18 PDL_INTC_REG_IERO8 PDL_INTC_REG_IER19 PDL_INTC_REG_IEROB PDL_INTC_REG_IER1A PDL_INTC_REG_IEROC PDL_INTC_REG_IER1B PDL_INTC_REG_IEROE PDL_INTC_REG_IER1C PDL_INTC_REG_IEROF PDL_INTC_REG IER1D PDL_INTC_REG_IER10 PDL_INTC_REG_IER1E PDL_INTC_REG IER11 PDL_INTC_REG IERIF R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS Page 70 of 418 RX63T Group 4 Library Reference IPR register definitions Some IPR registers are not existed in 64 and 48 pin packages Refer to Hardware manual section 15 Interrupt controller Table 15 3 Interrupt Vector Table for details
208. G_PG6PFS PDL_MPC_REG_P47PFS PDL_MPC_REG_PA6PFS PDL_MPC_REG_P50PFS PDL_MPC_REG_PBOPFS PDL_MPC_REG_P51PFS PDL_MPC_REG_PB1PFS PDL_MPC_REG_P52PFS PDL_MPC_REG_PB2PFS PDL_MPC_REG_P53PFS PDL_MPC_REG_PB3PFS PDL_MPC_REG_P54PFS PDL_MPC_REG_PB4PFS PDL_MPC_REG_P55PFS PDL_MPC_REG_PB5PFS PDL_MPC_REG_P56PFS PDL_MPC_REG_PB6PFS PDL_MPC_REG_P57PFS PDL_MPC_REG_PB7PFS Note Refer to the hardware manual for MPC register which are available on the device that you have selected R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS Page 92 of 418 RX63T Group 1 R_MPC_Read Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference Read an MPC register bool R_MPC_Read uint8_t data1 MPC register selection uint8_t data2 Pointer to the variable where the MPC register s value shall be stored Get the value of an MPC register data1 One of the definition values from 4 2 4 data2 The value read from the register True if a valid MPC register is specified otherwise false MPC registers None None RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data
209. IGGER_SCI12_RX or n 0 1 2 3 12 PDL_DTC TRIGGER SCIO_TX or PDL_DTC TRIGGER SCI1_TX or PDL_DTC TRIGGER SCI2_TX or Transmit buffer empty on SCI channel n PDL_DTC TRIGGER SCI3_TX or PDL_DTC_TRIGGER_SCI12_TX n 0 1 2 3 12 data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3 The source start address The valid range depends on the address mode short or full Rev 2 11 ENESAS Page 147 of 418 RX63T Group 4 Library Reference Description 4 4 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Set R_DTC_Control If address increment or decrement is selected the address changes according to the number of bytes 1 2 o
210. IIC Mode option will be ignored PDL_SCI_LSB_FIRST or PDL_SCI_MSB_FIRST Select least or most significant bit first Options which are available in Asynchronous mode or Multi Processor Asynchronous mode e Noise Filter PDL_SCI_RX_FILTER_DISABLE or Enable or disable the Digital Noise Filter on the PDL_SCI_RX_FILTER ENABLE RXDn pin e Hardware Flow Control PDL_SCI_HW_FLOW_NONE or Select the Hardware Flow Control Option PDL_SCI_HW_FLOW_CTS or Note CTS and RTS functions can not both be used PDL_SCI_HW_FLOW_RTS as they share the same pin Data clock source selection PDL_SCI_CLK_INT_IO or Select the on chip SCKn pin available as an I O pin PDL_SCI_CLK_INT_OUT or baud rate generator SCKn pin SCI bit clock output Input a clock of 8 or 16 times the desired bit rate to the SCKn PDL SCI OLK EXT pin See parameter data3 for the multiplier selection The base clock to be input from MTU3 must be set to a PDL_SCI_CLK_MTU3 frequency no greater than 1 4 that of PCLK Not valid in 64 and 48 pin packages e Data length PDL_SCI_8_BIT_LENGTH or F R20UT2201EE0211 Rev 2 11 EN ESAS Page 238 of 418 RX63T Group Sept 12 2014 4 Library Reference Description 2 4 Parity mode PDL_SCI_PARITY_NONE or No parity bit even parity bit or odd pa
211. IIC_Create TIC_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Y Write the data into the ay write_eeprom_data Prepare the next data for writing to the EEPROM R_DMAC_Control 3 _DMAC_SUSPEND PDL_DMAC_ENABLE DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_COUNT PDL_DMAC_CLEAR_DTIF om_data_array_2 DL_NO_PTR RRAY_2_SIZE DL_NO_DATA DL_NO_DATA DL_NO_DATA DL_NO_DATA epr P P e P A P P P P Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend TIC_CHANNEL PDL_IIC_STOP_DISABLI EPROM_ADDRESS eprom_data_array_l e al PDL_NO_FUNC 0 Y Read data from the EEPROM using the DMAC read_eeprom_data Prepare to read the next data This will read back the bytes previously written except the last one which will be read using R_IIC_MasterReceiveLast R_DMAC_Control 2 R20UT2201EE0211 Rev 2 11 AS Page 394 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples PDL_DMAC_ENABLE _DESTINATION PDL_DMAC_UPDATE_COUNT DL_DMAC_ SUSPEND PDL_DMAC_UPDATE DL_NO_PTR data_storage ARRAY_1_SIZE 1
212. ISABLE or PDL_GPT_BUFFER_CYCLE_SINGLE or PDL_GPT BUFFER CYCLE DOUBLE Disable or select single or double buffer operation for register GTPR GTADTRA buffer operation PDL_GPT_BUFFER_ADC_TRIG_A_DISABLE or Disable buffer operation for register GTADTRA or select one of the following PDL_GPT_BUFFER_ADC_TRIG_A CREST or PDL_GPT_BUFFER_ADC_TRIG_A TROUGH or PDL_GPT_BUFFER_ADC_TRIG_A BOTH or Triangle waves Select transfer at crest trough or crest and trough PDL_GPT_BUFFER_ADC_TRIG_A_SAW Saw waves Select transfer at underflow or overflow PDL_GPT_BUFFER_ADC_TRIG_A_SINGLE or PDL_GPT_BUFFER_ADC_TRIG_A_DOUBLE If GTADTRA buffer operation is enabled select single or double buffer operation GTADTRB buffer operation PDL_GPT_BUFFER_ADC_TRIG_B_DISABLE or Disable buffer operation for register GTADTRB or select one of the following PDL_GPT_BUFFER_ADC_TRIG_B CREST or Triangle waves Select transfer at crest PDL_GPT_BUFFER_ADC_TRIG_B_ TROUGH or trough or PDL_GPT_BUFFER_ADC_TRIG_B_BOTH or crest and trough Saw waves PDL_GPT_BUFFER_ADC_TRIG_B_SAW Select transfer at underflow or overflow PDL_GPT_BUFFER_ADC_TRIG_B SINGLE or PDL_GPT_BUFFER ADC_TRIG_B DOUBLE If GTADTRB buffer operation is enabled select single or double buffer operation ENESAS Page 198 of 418 RX63T Group Description 7 7 R20UT2201EE0211 Sept 12
213. ISING Prevent or allow an edge on the IRQ4 DS pin to cancel deep software standby mode Prevent or allow an edge on the IRQ5 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ6_DISABLE or PDL_LPC_CANCEL_IRQ6_FALLING or PDL_LPC_CANCEL_IRQ6_RISING Prevent or allow an edge on the IRQ6 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ7_DISABLE or PDL_LPC_CANCEL_IRQ7_FALLING or PDL_LPC_CANCEL_IRQ7_RISING Prevent or allow an edge on the IRQ7 DS pin to cancel deep software standby mode Rev 2 11 ENESAS Page 113 of 418 RX63T Group Description 2 2 Return value Category References R20UT2201EE0211 Sept 12 2014 data3 Select the interrupt to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults 4 Library Reference Deep software standby cancel control PDL_LPC_CANCEL_LVD1_DISABLE or PDL_LPC_CANCEL_LVD1_FALLING or PDL_LPC_ CANCEL LVD1_ RISING PDL_LPC_CANCEL_LVD2_DISABLE or PDL_LPC_CANCEL_LVD2_ FALLING or PDL_LPC_CANCEL_LVD2 RISING Prevent or allow an edge on the LVD1 pin to cancel deep software standby mode Prevent or allow an edge on the LVD2 pin to cancel deep software standby mode PDL_LPC_CANCEL_NMI_DISABLE or PDL_LPC_CANCEL_NMI_FALLING or PDL_LPC CANCEL _NMI_RISING data4 Select the main clock oscillator waiting times If no
214. IV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC FILTER DIV 64 The interrupt pin input can be unfiltered or sampled using the peripheral clock PCLKB divided by 1 8 32 or 64 For the NMI signal this selection is ignored if the NMI pin is not enabled Options which only apply to the IRQ pins Input sense selection PDL_INTC_LOW or PDL_INTC_FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection DMAC DTC trigger control Not enabled if low level detection is selected PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or PDL_INTC_DMAC_TRIGGER_ENABLE or PDL_INTC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a valid edge transition is detected on a valid IRQn pin Options which only apply to the NMI Rev 2 Pin enable and input sense selection PDL_INTC_FALLING or PDL_INTC_RISING Enable the NMI pin and select falling or rising edge detection Required only if the NMI pin is to be used Internal detection control PDL_INTC_OSD_DISABLE or PDL_INTC_WDT_DISABLE or PDL_INTC_WDT_ ENABLE Disable or enable the NMI signal when the oscillation stop PDL_INTC_OSD_ENABLE detection interrupt occurs Disable or enable the NMI signal when a WDT underflow interrupt occurs PDL_INTC_IWDT_DISABLE or PDL_INTC_IWDT ENABLE Disable or enable the NMI signal when an
215. L ADC 12 PIN ADTRGO P20 Select P20 for ADTRGO PDL_ADC_12_PIN_ADTRGO_PA4 Select PA4 for ADTRGO PDL_ADC_12_PIN_ADTRG1_P21 Select P21 for ADTRG1 PDL_ADC_12_PIN_ADTRG1_PA5 Select PA5 for ADTRG1 Return value Category Reference False if an invalid pin selection is made otherwise True 12 bit ADC R_ADC_12_CreateUnit Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 e If there are I O pins to be used call this function before calling R_ADC_12_CreateUnit e Not all device packages have all of the pin options Do not specify an option that does not exist for the device package being used RPDL definitions include r_pdl_adc_12 h RPDL device specific definitions include r_pdl_definitions h void func void Set analog channel ANOOO R_ADC_12_Set PDL_ADC_12 PIN_ANO00_P40 ENESAS Page 296 of 418 RX63T Group 2 R_ADC_12 CreateUnit Synopsis Configure the 12 bit ADC unit Prototype bool R_ADC_12 CreateUnit uint8_t data1 Unit selection uint32_t data2 Unit specific options uint32_t data3 Options for Group A uint32_t data4 uint32_t data5 uint32_t data6 uint32_t data7 Options for Group B Options for Camparator 4 Library Reference Additional options for Group A Additional options for Group B doubl
216. L_GPT_STOP_CH 6 in unit 1 The stop operation will be simultaneous PDL_GPT_STOP_CH_7 e Counter start PDL_GPT_START_CH_0 PDL_GPT_START_CH_1 Start the count operation for the selected channels PDL_GPT_START_CH 2 in unit O The start operation will be simultaneous PDL_GPT_START_CH_3 PDL_GPT_START_CH 4 PDL_GPT_START_CH_5 Start the count operation for the selected channels PDL_GPT_START_CH_6 in unit 1 The start operation will be simultaneous PDL_GPT_START_CH_7 e Counter clearing PDL_GPT_CLEAR_CH_0 PDL_GPT_CLEAR_CH_1 Clear the counters for the selected channels in unit PDL_GPT_CLEAR_CH _ 2 0 The clear operation will be simultaneous PDL_GPT_CLEAR_CH_3 PDL_GPT_CLEAR_CH_4 PDL_GPT_CLEAR_CH_5 Clear the counters for the selected channels in unit PDL_GPT_CLEAR_CH 6 1 The clear operation will be simultaneous PDL_GPT_CLEAR_CH_7 IWDTCLK counter stop start PDL_GPT_IWDTCLK_COUNT_DISABLE Stop the IWDTCLK count operation PDL_GPT_IWDTCLK_COUNT_ENABLE Start the IWDTCLK count operation e IWDTCLK counter clearing PDL_GPT_IWDTCLK_COUNT_CLEAR Clear the IWDTCLK counter LCNT to 0 e IWDTCLK count result initialisation Initialise the IWDTCLK count result registers PDL_GPT_IWDTCLK_RESULTS_INIT LCNT01 to LCNT15 using the first count LCNTOO value Rev 2 11 ENESAS Page 206 of 418 RX63T Group Description 2 2 4 Library Reference IWDTCLK count deviation update Return value
217. L_INTC_VECTOR_SCIX2 PDL_INTC_VECTOR_SCIX3 SCI channel 12 Extended serial mode Break field Extended serial mode Control field Extended serial mode Bus collision Extended serial mode Valid edge PDL_INTC_VECTOR_TGIAO PDL_INTC_VECTOR_TGIBO PDL_INTC_VECTOR_TGICO PDL_INTC_VECTOR_TGIDO PDL_INTC_VECTOR_TCIVO PDL_INTC_VECTOR_TGIFO PDL_INTC_VECTOR_TGIEO Multi function Timer Pulse Unit channel 0 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow Compare match E Compare match F PDL_INTC_VECTOR_TGIA1 PDL_INTC_VECTOR_TGIB1 PDL_INTC_VECTOR_TCIV1 PDL_INTC_VECTOR_TCIU1 Multi function Timer Pulse Unit channel 1 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR_TGIA2 PDL_INTC_VECTOR_TGIB2 PDL_INTC_VECTOR_TCIV2 PDL_INTC_VECTOR_TCIU2 Multi function Timer Pulse Unit channel 2 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR_TGIA3 PDL_INTC_VECTOR_TGIB3 PDL_INTC_VECTOR_TGIC3 PDL_INTC_VECTOR_TGID3 PDL_INTC_VECTOR_TCIV3 Multi function Timer Pulse Unit channel 3 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overfl
218. L_POE HI Z MTO_ ADD _POE10 edge on POE10 outputs PDL_POE HI Z MTO ADD_POE11 the pin POE11 PDL_POE HI Z MTO _ ADD _POE12 POE12 PDL POE _HI Z GPT01_ADD_CFLAG Comparator detection PDL_POE_HI_Z_GPT01_ADD_POEO POEO PDL_POE_HI_Z_GPT01_ADD_POE4 A valid POE4 GPT channel 0 and 1 PDL_POE HI Z GPT01_ADD_POE8 edge on POE8 outputs PDL_POE HI Z GPTO1_ADD POE11 the pin POE11 PDL_POE HI Z GPTO01_ADD POE12 POE12 PDL_POE HI_Z GPT23_ADD_CFLAG Comparator detection PDL_POE HI Z GPT23 ADD _POEO POEO PDL_POE HI Z GPT23 ADD _POE4 A valid POE4 GPT channel 2 and 3 PDL_POE HI Z GPT23 ADD _POE8 edge on POE8 outputs PDL_ POE HI Z GPT23 ADD POE10 the pin POE10 PDL_POE_HI_Z GPT23_ADD_POE12 POE12 data3 High impedance control selections for MTU67 and GPT67 If multiple selections are required use to separate each selection All selections are optional Specify PDL_NO_DATA if none are required e Select any event flags to be added to the high impedance control for MTU67 and GPT67 PDL POE HI Z GPT67 ADD CFLAG Comparator detection PDL POE_HI_Z GPT67_ADD_POEO POEO PDL POE_HI Z GPT67_ADD_POE4 A valid POE4 GPT channel 6 and 7 PDL_POE_HI_Z_GPT67_ADD_POE8 edge on POE8 outputs PDL_POE_HI_Z GPT67_ADD_POE10 the pin POE10 PDL_POE _HI_Z GPT67_ADD _POE11 POE11 PDL_POE _HI_Z MT67_ADD_CFLAG Comparator detection PDL_POE _HI_Z MT67_ADD POEO POEO MTU channel 6
219. L_POE_IRQ_SHORT_34_ENABLE DISABLE PDL_POE_FLAG_SHORT_34_CLEAR also support to control the outputs of MTU channel 6 7 on the 64 and 48 pin packages RPDL definitions include r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Select high impedance on the MTUO I O pins R_POE_Control PDL_POE_MTUO_HI_Z_ON PDL_NO_DATA PDL_NO_DATA Rev 2 11 EN ESAS Page 187 of 418 RX63T Group 4 R_POE GetStatus Synopsis Prototype Description 4 Library Reference Check the Port Output Enable module status bool R_POE_GetStatus uint16_t data Return the status flags Status flags pointer Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 data The status flags shall be stored in the following format b15 b14 B13 b12 b11 b10 b9 b8 Output short Output short 0 detection detection High impedance request detection more MTU6 or MTU3 or MTU7 MTU4 OSTSTF POE12 POE11 POE10 POE8 0 Not detected 0 Not detected 0 No request 1 Detected 1 Detected 1 Requested b7 b6 b5 b4 b3 b2 b1 bO High impedance request detection on pin POEn POE4 POEO 0 No request 1 Requested True Port Output Enable R_POE_
220. MTU3_CH_34 or Read the A registers used with channels 3 and 4 PDL_MTU3_CH_67 or the B registers used with channels 6 and 7 data3 A pointer to where the Timer subcounter register TCNTS value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the Timer Interrupt Skipping Counters TITCNT1 or TITCNT2 register value shall be stored The choice of register depends on the type on interrupt skipping control selected by function R_MTU3_ControlUnit Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU3_ControlUnit None RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h uint16_t Sub_count uint8_t Skip_count void func void Read the counter registers for channels 3 and 4 R_MTU3_ReadUnit 0 PDL_MTU3_CH_34 Sub_count amp Skip_count Rev 2 11 EN ESAS Page 179 of 418 RX63T Group 4 2 14 1 R_POE Set Synopsis Prototype Description 1 4 R20UT2201EE0211 Sept 12 2014 Configure the Port Output Enable module Port Output Enable bool R_POE_Set uint32_t data1 uint32_t data2 uint16_t data3 uint16_t data4 uint32_t data5 Initialise the POE pins data1 Configure the input detection for pins of POEO POE4 POE8 POE10 POE11 and POE12
221. NC PDL_NO_FUNC Y Wait for data to be sent while data_sent false Close this channel R_SCI_Destroy 0 static void SCItx void data_sent true Figure 5 27 Example of SCI in SPI mode R20UT2201EE0211 Rev 2 11 RENESAS Page 381 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 9 SCI in IIC Mode This shows the setting of SCI channel 1 in to IIC mode and then a write and read to an IIC EEPROM PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h SCI IIC Channel define CHANNEL_SCI_1IIC 1 IIC Slave address of EEPROM define SLAVE_ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 Value to be written to the EEPROM define EPROM VALUE OxAA void main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set Channel 1 pin options R_SCI_Set 1 if defined DEVICE PACKAGE 64 PIN amp amp defined DEVICE_PACKAGI PDL_SCI_PIN_SCI1_SSCL1_PD5 PDL_SCI_PIN_SCI1_SSDA1_PD3 else PDL_SCI_PIN_SCI1_SSCL1_P93 PDL_SCI_PIN_SCI1_SSDA1_P94 endif di
222. NNEL_1 Test align left R_DAC_10_Create PDL_DAC_10_CHANNEL_1 PDL _DAC_10_ALIGN_LI 0x0 OxffcO 5 0V y Write new data to both DAC channels R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0x0 0x8000 2 5V y Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_CHANNEL_1 y while 1 Figure 5 45 Example of DAC_10 R20UT2201EE0211 Rev 2 11 RENESAS Page 412 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 24 Data Operation Circuit Figure 5 46 Example of DOC shows an example Data Operation Circuit usage Peripheral driver function prototypes include r_pdl_cgc h include r_pdl_doc h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h define DMAC_CHANNEL 0 define DATA_COUNT 10 static void SetClocks void static void Callback_Done void Data to calculate sum of static uint16_t data DATA_COUNT 1 2 3 4 5 6 7 8 9 10 Callback Flag static volatile bool g_bCallbackDone false void main void uint8_t status uint16_t result Initialise the system clocks NOTE The code to initialise the system clock is omitted here Please refer to 5 1 Clock Generation Circuit Setup the DOC in addition mode initial value 0 R_DOC_Create PDL_DOC_MODE_ADD 0 PDL_NO_FUNC 0 y Setup DMAC to write data to the 16bit DOC Input register R_DMAC
223. NO_DATA 1E 3 PDL_NO_FUNC 0 ENESAS Page 221 of 418 RX63T Group 3 R_CMT_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Disable a CMT unit bool R_CMT_Destroy uint8_tdata Unit selection Shut down a CMT unit data The timer unit n where n 0 or 1 Unit O comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 True if the unit selection is valid otherwise false Compare Match Timer R_CMT_Create The timer unit is put into the stop state to reduce power consumption RPDL definitions tinclude r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT_Destroy 0 4 Library Reference Page 222 of 418 Rev 2 11 ENESAS Sept 12 2014 RX63T Group 4 Library Reference 4 R_CMT_ Control Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Control CMT operation bool R_CMT_Control uint8_t data1 Channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data Modify the operation of a CMT channel data1 The channel
224. ORT_ModifyControl uint16_t data1 Port or port pin selection uint8_tdata2 Control register and logical operation selection uint16_t data3 Modification value Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 4 Library Reference Select the register to be modified and the logical operation using to separate the selections e The control register to be modified PDL_IO_PORT_DIRECTION or Data direction PDL_IO_PORT_MODE or General or Peripheral I O mode control PDL_IO_PORT_TYPE or Open drain control PDL_IO_PORT_DRIVE_BUS or Drive capacity control related to external bus pins Valid on packages with 100 pins or more PDL_IO_PORT_DRIVE_SPI Drive capacity control related to SPI pins Valid on packages with 100 pins or more e The logical operation to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR data3 The value to be used for the modification using one of the formats below Pin control b15 b1 bO Do not care Oori Port not open drain control b15 b8 b7 b0 Do not care Register Port open drain control b15 b8 b7 b0 Register ODR1 Registe
225. OUP12 PDL_INTC_REG IR GPT5 GICIE PDL_INTC_REG IR SCI12 SCIXO PDL_INTC_REG IR _GPT5 GTCIV PDL_INTC REG IR SCI12 SCIX1 PDL_INTC_ REG IR GPT6 GTCIA PDL_INTC_REG_IR SCI12 SCIX2 PDL_INTC_ REG IR GPT6 GICIB PDL_INTC_REG IR SCI12 SCIX3 PDL_INTC_REG IR GPT6 GICIC PDL_INTC_REG IR MTUO TGIA PDL_INTC_REG IR GPT6 GICIE PDL_INTC_REG IR MTUO TGIB PDL_INTC_REG IR_GPT6 GTCIV PDL_INTC REG IR MTUO TGIC PDL_INTC_REG_IR_IIC1_EEl PDL_INTC_REG IR MTUO TGID PDL_INTC REG IR IIC1 RXI PDL_INTC_REG IR MTUO_TCIV PDL INTC_REG_IR_IIC1 TXI PDL_INTC_REG IR MTUO TGIE PDL_INTC REG _IR IIC1 TEI PDL_INTC_REG IR MTUO TGIF PDL_INTC REG IR ICO EEI R20UT2201EE0211 Rev 2 11 Sept 12 2014 RENESAS Page 69 of 418 RX63T Group 4 Library Reference PDL_INTC_REG_IR_IICO_RXI PDL_INTC_REG_IR_GPTO_GTCIE PDL_INTC_REG_IR_IICO_TXI PDL_INTC_REG_IR_GPTO_GTCIV PDL_INTC_REG_IR_IICO_TEI PDL_INTC_REG_IR_GPTO_LOCO PDL_INTC_REG_IR_DMAC_DMACOI PDL_INTC_REG_IR_GPT1_GTCIA PDL_INTC_REG_IR_DMAC_DMACi1I PDL_INTC_REG_IR_GPT1_GTCIB PDL_INTC_REG_IR_DMAC_DMAC2I PDL_INTC_REG_IR_GPT1_GTCIC PDL_INTC_REG_IR_DMAC_DMAC3I PDL_INTC_REG_IR_GPT1_GTCIE PDL_INTC_REG_IR_SCIO_RXI PDL_INTC_REG_IR_GPT1_GTCIV PDL_INTC_REG_IR_SCIO_TXI PDL_INTC_REG_IR_GPT2_GTCIA PDL_INTC_REG_IR_SCIO_TEI PDL_INTC_REG_IR_GPT2_
226. PDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function void CallBackFunc void void func void Configure the IRQ1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRO1 PDL_INTC_FALLING CallBackFunc 7 Y Configure the NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING CallBackFunc 15 y Configure the NMI triggered by the WDT only no NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_WDT_ENABLE CallBackFunc 10 y Rev 2 11 ENESAS Page 59 of 418 RX63T Group 4 Library Reference 3 R_INTC_CreateSoftwarelnterrupt Synopsis Enable use of the software interrupt Prototype bool R_INTC_CreateSoftwarelnterrupt uint8_t data1 Configuration void func Callback function uint8_t data2 Interrupt priority level Description Configure and enable the software interrupt data1 Choose the pin settings The default setting is shown in bold e DTC trigger control PDL_INTC_DTC_SW_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_INTC_DTC_SW_TRIGGER_ENABLE when a software interrupt is generated func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no interrupt is required data2 The interrupt priority level Select between 1
227. PDL_MPC_REG_P13PFS PDL_MPC_REG_P71PFS PDL_MPC_REG_PD1PFS PDL_MPC_REG_P14PFS PDL_MPC_REG_P72PFS PDL_MPC_REG_PD2PFS PDL_MPC_REG_P20PFS PDL_MPC_REG_P73PFS PDL_MPC_REG_PD3PFS PDL_MPC_REG_P21PFS PDL_MPC_REG_P74PFS PDL_MPC_REG_PD4PFS PDL_MPC_REG_P22PFS PDL_MPC_REG_P75PFS PDL_MPC_REG_PD5PFS PDL_MPC_REG_P23PFS PDL_MPC_REG_P76PFS PDL_MPC_REG_PD6PFS PDL_MPC_REG_P24PFS PDL_MPC_REG_P80PFS PDL_MPC_REG_PD7PFS PDL_MPC_REG_P25PFS PDL_MPC_REG_P81PFS PDL_MPC_REG_PEOPFS PDL_MPC_REG_P26PFS PDL_MPC_REG_P82PFS PDL_MPC_REG_PE1PFS PDL_MPC_REG_P30PFS PDL_MPC_REG_P90PFS PDL_MPC_REG_PE2PFS PDL_MPC_REG_P31PFS PDL_MPC_REG_P91PFS PDL_MPC_REG_PE3PFS PDL_MPC_REG_P32PFS PDL_MPC_REG_P92PFS PDL_MPC_REG_PE4PFS PDL_MPC_REG_P33PFS PDL_MPC_REG_P93PFS PDL_MPC_REG_PE5PFS PDL_MPC_REG_P34PFS PDL_MPC_REG_P94PFS PDL_MPC_REG_PF2PFS PDL_MPC_REG_P35PFS PDL_MPC_REG_P95PFS PDL_MPC_REG_PF3PFS PDL_MPC_REG_P40PFS PDL_MPC_REG_P96PFS PDL_MPC_REG_PGOPFS PDL_MPC_REG_P41PFS PDL_MPC_REG_PAOPFS PDL_MPC_REG_PG1PFS PDL_MPC_REG_P42PFS PDL_MPC_REG_PA1PFS PDL_MPC_REG_PG2PFS PDL_MPC_REG_P43PFS PDL_MPC_REG_PA2PFS PDL_MPC_REG_PG3PFS PDL_MPC_REG_P44PFS PDL_MPC_REG_P45PFS PDL_MPC_REG_PA3PFS PDL_MPC_REG_PA4PFS PDL_MPC_REG_PG4PFS PDL_MPC_REG_PG5PFS PDL_MPC_REG_P46PFS PDL_MPC_REG_PA5PFS PDL_MPC_RE
228. PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR Increment count Counter_Callback_Match_TGRA static void Callback_Match_TGRE void Counter_Callback_Match_TGRE Figure 5 48 Example of MTU R20UT2201EE0211 Rev 2 11 AS Page 417 of 418 Sept 12 2014 RENES RX63T Group 6 RX specific notes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two processor modes supervisor and user The API driver functions may be executed by the CPU in either mode However any callback functions which are called by the API interrupt handlers will always be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE instructions These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following instructions i DSP
229. PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode e Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or The number of bit clock periods between the end of PDL_SPI_SSL_DELAY_4 or RSPCK oscillation and the negation of the active SSL PDL_SPI_SSL_DELAY_5 or pin PDL_SPI_SSL_DELAY_6 or Ignored in Slave mode PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY_8 e Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or The number of bit clock periods plus two cycles of the PDL_SPI_NEXT_DELAY_4 or peripheral clock between the end of one frame and the PDL_SPI_NEXT_DELAY_5 or start of the next frame PDL_SPI_NEXT_DELAY_6 or Ignored in Slave mode PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 True if all parameters are valid otherwise false SPI Rev 2 11 QEN ESAS Page 289 of 418 RX63T Group 4 Library Reference Reference R_SPI_Create Remarks e Ifa channel is disabled using PDL_SPI_DISABLE call R_SPI_Create to resume channel operations Program example RPDL definitions tinclude r_pdl_spi h RPDL device specific definitions include r_pdl_definitio
230. PT pins for use 2 Configuration of a GPT unit the IWDTCLK count module 3 Configuration of a GPT channel including e Access to all control bits e Automatic interrupt control 4 Disabling channels that are no longer required and enabling low power mode 5 Control of a GPT channel 6 Control of a GPT unit 7 Reading the status flags and registers of a GPT channel 8 Reading the status flags and registers of a GPT unit 9 Enable the PWM Edge Delay circuit 10 Control the PWM Edge Delay circuit 11 Disable the Edge Delay circuit R20UT2201EE0211 Rev 2 11 LEN ESAS Page 33 of 418 Sept 12 2014 RX63T Group R20UT2201EE0211 2 Driver 2 18 Compare Match Timer Driver The driver functions support the use of the two 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates change of frequency 5 Reading the counter value and status flag Note The Clock Generation Circuit must be configured before configuring any timer channel Rev 2 11 EN ESAS Page 34 of 418 Sept 12 2014 RX63T Group 2 Driver 2 19 Watchdog Timer Driver The driver functions support the us
231. PT_PIN_GTIOC1B_PD4 Select P75 or PD4 for GTIOC1B e Valid when n 2 PDL_GPT_PIN_GTIOC2A_P73 or PDL_GPT_PIN_GTIOC2A_PD3 PDL_GPT_PIN_GTIOC2B_P76 or PDL_GPT_PIN_GTIOC2B_PB7 or PDL_GPT_PIN_GTIOC2B_PB6 or PDL_GPT_PIN_GTIOC2B_PD2 Select P73 or PD3 for GTIOC2A Select P76 PB7 PB6 or PD2 for GTIOC2B Valid when n 3 PDL_GPT_PIN_GTIOC3A_P00 or PDL_GPT_PIN_GTIOC3A_PD1 Select POO or PD1 for GTIOC3A PDL_GPT_PIN_GTIOC3B_P01 or PDL_GPT_PIN_GTIOC3B_PDO Select P01 of PDO for GTIOC3B e Valid when n 4 PDL_GPT_PIN_GTIOC4A_P95 Select P95 for GTIOC4A PDL_GPT_PIN_GTIOC4B_P92 Select P92 for GTIOC4B e Valid when n 5 PDL_GPT_PIN_GTIOC5A_P94 Select P94 for GTIOC5A PDL_GPT_PIN_GTIOC5B_P91 e Valid when n 6 Select P91 for GTIOC5B PDL_GPT_PIN_GTIOC6A_P93 or PDL_GPT_PIN_GTIOC6A_PG3 Select P93 or PG3 for GTIOC6A PDL_GPT_PIN_GTIOC6B_P90 or PDL_GPT_PIN_GTIOC6B_PG4 Select P90 of PG4 for GTIOC6B e Valid when n 7 PDL_GPT_PIN_GTIOC7A_PGO Select PGO for GTIOC7A PDL_GPT_PIN_GTIOC7B_PG1 Select PG1 for GTIOC7B Rev 2 11 ENESAS Page 189 of 418 RX63T Group 4 Library Reference Description 2 2 e Valid always PDL_GPT_PIN_GTETRGO_PB4 Select PB4 for GTETRGO PDL_GPT_PIN_GTETRG1_P34 Select PB4 for GTETRG1 Return value True if all parameters are valid and exclusive otherwise false Cat
232. P_VSELHO_ INTERNAL Comparator REFH selection valid on device packages with 48 or 64 pin Set the voltage on ANO07 or the selected internal voltage as the REFL for comparator Comparator REFH selection valid on device packages with 100 112 120 and 144 pin PDL_ADC_12 CMP_VSELHO_AN103 or PDL_ADC_12 CMP_VSELHO_ INTERNAL Set the voltage on AN103 or the selected internal voltage as the REFL for comparator Comparator input selection valid on device packages with 100 112 120 and 144 pin PDL_ADC_12 CMP_ANXOX_BEFORE_AMPLIFIER or PDL_ADC_12 CMP_ANXOX_AFTER_AMPLIFIER Rev 2 11 ENESAS Before or after amplified by the programmable gain amplifier Page 301 of 418 RX63T Group 4 Library Reference Description 6 6 Comparator internal REFL selection PDL_ADC_12_CMP_REFL_DISABLE or PDL_ADC_12 CMP_REFL_AVCCO_1_8or PDL_ADC_12 CMP_REFL_AVCCO_2 8or PDL_ADC_12 CMP_REFL_AVCCO_3 8or PDL_ADC_12 CMP_REFL_AVCCO_ 4 8or PDL_ADC_12 CMP_REFL_AVCCO_5 8or PDL_ADC_12 CMP_REFL_AVCCO_6 8or PDL_ADC 12 CMP_REFL_AVCCO 7_ 8 Disable the internal REFL for comparator or set it as AVCCO 1 8 2 8 3 8 4 8 5 8 6 8 or 7 8 Comparator internal REFH selection PDL_ADC_12_CMP_REFH_DISABLE or PDL_ADC_12 CMP_REFH_AVCCO_1_8or PDL_ADC_12 CMP_REFH_AVCCO_2 8or PDL_ADC_12 CMP_REFH_AVCCO_3 8or PDL_ADC_12 CMP_REFH_AVCCO_4 8or PDL_ADC_12 CMP_REFH_AVCCO_5 8or PDL_ADC_12 CMP
233. Page 184 of 418 RX63T Group Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 to func4 True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE_Set R_POE_GetStatus Use R_POE_GetStatus to determine the interrupt cause Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed All settings related to POE4 and MTU6 7 are not available on the 64 and 48 pin packages All settings related to POE12 are not available on the 100 64 and 48 pin packages The settings PDL_POE_IRQ_SHORT_34_ENABLE DISABLE also support to control an interrupt on detection of a short on any MTU channel 6 7 two phase output pair on the 64 and 48 pin packages RPDL definitions tinclude r_pdl_poe h RPDL device specific definitions include r_pdl_definitions h void POEO_handler void void func void Assign the callback function for pin POEO R_POE_Create PDL_POE_IRQ_HI_Z_0_ENABLE POEO_handler PDL_NO_FUNC PDL_NO_FUNC P
234. Please refer to the notes of SCKCR register in the hardware manual The registers MOSCWTCR main clock and PLLWTCR PLL provide stabilisation delays for the respective oscillator and must be written to while that clock is stopped If any of these registers needs to be modified stop the clock using R_CGC_Control and call R_LPC_Create to set the new value If the PLL will be used first use this function to configure the main clock oscillator settings If the PLL will be used the frequencies of the internal clocks ICLK PCLKA PCLKB PCLKC PCLKD FCLK and BCLK must be no more than the PLL output clock frequency 2 If the main clock will be used the frequencies of the internal clocks ICLK PCLKA PCLKB PCLKC PCLKD FCLK and BCLK must be no more than the main clock frequency 4 If the PLL output frequency is to be changed while the PLL is enabled before calling this function use R_CGC_Control to select another clock source and stop the PLL If the IWDTLOCO is selected specify PDL_NO_DATA for parameters data2 and data4 to data11 The external bus is not available on the 48 and 64 pin packages The BCLK pin output will not be active until the external bus is enabled using R_BSC_Control When operation of the external bus clock is selected the PE5 I O port pin function is not available If low speed operating mode 1 is selected do not call this function to configure the PLL When USB module is used UCLK must be set to 48MHz Rev
235. Q E ENABLE PDL_GPT_IRQ_F_DISABLE or PDL_GPT_IRQ_F_ENABLE GTCCRE compare match GTCCRF compare match PDL_GPT_IRQ_DEADTIME_DISABLE or PDL_GPT IRQ DEADTIME ENABLE ad time error PDL_GPT_IRQ_OU_DISABLE or PDL_GPT_IRQ_OU_OVER or PDL_GPT_IRQ_OU_UNDER or PDL_GPT_IRQ_OU_BOTH Select the Overflow underflow detection Rev 2 11 ENESAS Page 194 of 418 RX63T Group Description 3 7 R20UT2201EE0211 Sept 12 2014 data4 4 Library Reference Automatic clearing and hardware control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Automatic counter clearing PDL_GPT_CLEAR_DISABLE or Automatic clearing is disabled PDL_GPT_CLEAR Aor PDL_GPT_CLEAR Bor Cleared by GTCCRA or GTCCRB input capture PDL_GPT_CLEAR_SYNC_CH Oor PDL_GPT_CLEAR_SYNC_CH_1or PDL_GPT_CLEAR_SYNC_CH_2 or PDL_GPT_CLEAR_SYNC_CH_3 Clearing at the same time as another channel m where m n in unit O PDL GPT CLEAR SYNC CH 4 or PDL _GPT_CLEAR_SYNC_CH_5 or PDL_GPT_CLEAR_SYNC_CH 6 or PDL_GPT_ CLEAR SYNC_CH 7 Clearing at the same time as another channel m where m n in unit 1 e Hardware counter start stop and clearing PDL_GPT_HW_START_DISABLE or PDL_GPT_HW_START_RISING or PDL_GPT_HW_START_FALLING or PDL_GPT_HW_START_BOTH
236. R registers are not existed in 64 and 48 pin packages Refer to Hardware manual section 15 Interrupt controller Table 15 3 Interrupt Vector Table for details PDL_INTC_REG DTCER ICU_SWINT PDL_INTC_REG_DTCER_CMP_CMPO PDL_INTC_REG_DTCER_CMTO_CMI PDL_INTC_REG_DTCER_CMP_CMP1 PDL_INTC_REG_DTCER_CMT1_CMI PDL_INTC_REG DTCER CMP_CMP2 PDL_INTC_REG_DTCER_CMT2_CMI PDL_INTC_REG_DTCER_GPT4 GTCIA4 PDL_INTC_REG DTCER CMT3 CMI PDL_INTC_REG_DTCER_GPT4_GTCIB4 PDL_INTC_REG_DTCER_USBO_DOFIFO PDL_INTC_REG_DTCER_GPT4_GTCIC4 PDL_INTC_REG_DTCER_USBO_D1FIFO PDL_INTC_REG_DTCER_GPT4_GTCIE4 PDL_INTC_REG_DTCER_SPI1_SPRI PDL_INTC_REG_DTCER_GPT4_ GTCIV4 PDL_INTC_REG DTCER SPI1_SPTI PDL_INTC_REG DTCER SPIO SPRI PDL_INTC_REG_DTCER_GPT4_ LOCO PDL_INTC_REG_DTCER_GPT5_GTCIA5 PDL_INTC_REG DTCER SPIO SPTI PDL_INTC_REG_DTCER_GPT5_GTCIB5 PDL_INTC_REG DTCER GPT7 GTCIA7 PDL_INTC_REG_DTCER_GPT5_GTCIC5 PDL_INTC_REG_DTCER_GPT7_GTCIB7 PDL_INTC_REG_DTCER_GPT5_GTCIE5 PDL_INTC_REG DICER GPT7_GTCIC7 PDL_INTC_REG_DTCER_GPT5_GTCIV5 PDL_INTC_REG DTCER GPT7 GTCIE7 PDL_INTC_REG_DTCER_GPT6_GTCIA6 PDL_INTC_REG DTCER GPT7 GTCIV7 PDL_INTC_REG_DTCER_GPT6_GTCIB6 PDL_INTC_REG_DTCER_CMP_CMP4 PDL_INTC_REG_DTCER_GPT6_GTCIC6 PDL_INTC_REG_DTCER_CMP_CMP5 PDL_INTC_REG_DTCER_GPT6_GTCIE6
237. REFHO_ROTATED Disable the self diagnostic function or enable and use the voltage on pin VREFHO x 0 X Ye x1or automatically rotated voltage Sampling time PDL_ADC_10_ADSSTR_CALCULATE_UNIT or PDL_ADC_10_ADSSTR_SPECIFY_UNIT Select whether parameter data4 is used to calculate the ADSSTRO value or contains the value to be stored in register ADSSTRO Rev 2 11 ENESAS Page 314 of 418 RX63T Group Description 2 3 DMAC or DTC trigger control 4 Library Reference R20UT2201EE0211 Sept 12 2014 PDL_ADC_10_DMAC_DTC_TRIGGER_DISABLE or PDL_ADC_10_DTC_TRIGGER_ENABLE or PDL_ADC_10_DMAC_TRIGGER_ENABLE Enable or disable activation of the DMAC or DTC data3 Condition to start ADC conversion PDL_ADC_10 TRIGGER _ SOFTWARE or Software trigger PDL_ADC_10_TRIGGER_ADTRG or A D conversion start trigger pin PDL_ADC_10_TRIGGER_MTUO_CMIC or TRGA compare match input capture from MTUO PDL_ADC_10_TRIGGER_MTU1_CMIC or TRGA compare match input capture from MTU1 PDL_ADC_10_ TRIGGER _MTU2_CMIC or TRGA compare match input capture from MTU2 PDL_ADC_10_TRIGGER_MTU3_CMIC or TRGA compare match input capture from MTU3 PDL_ADC_10_ TRIGGER _MTU4_CMIC or MTU4 TRGA compare match input capture or MTU4 TCNT underflow trough in complementary PWM mode PDL_ADC_10_ TRIGGER _MTU6_CMIC or TRGA compare match input capture from MT
238. RIGGER_DISABLE or Disable or enable activation of the PDL_SPI_DMAC_TRIGGER_ENABLE or DMAC or DTC for data transmission PDL_SPI_DTC_TRIGGER_ENABLE and reception data3 The start address of the data to be transmitted The data must be stored as 32 bit values Specify PDL_NO_PTR if no data is to be transmitted or if the data content is not important or if the DMAC or DTC shall be used to handle the data transfer data4 The start address of the data to be received The data will be stored as 32 bit values Specify PDL_NO_PTR if no data is to be received or if the DMAC or DTC shall be used to handle the data transfer data5 The number of times that the command sequence will be executed If the DMAC or DTC shall be used to handle the transfer specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Pollin PDL_NO_FUNC R_SPI Transfer will handle the data transfer until 9 completion Interrupts The function to be called when the transfer has completed DMAC or DTC The function to be called when the DMAC or DTC passes on the transfer interrupt data6 The interrupt priority level for data transmission Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 Rev 2 11 EN ESAS Page 287 of 418 RX63T Group 4 Library Reference
239. ROM sub address and then read 2 bytes R20UT2201EE0211 Rev 2 11 RENESAS Page 392 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 18 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer PDL functions include r_pdl_cgc h include r_pdl_iic h tinclude r_pdl_cmt h include r_pdl_dmac h PDL device specific definitions tinclude r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM MEMORY _ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM MEMORY _ADDRESS_UPPER define IIC_CHANNEL 0 volatile uint8_ volatile uint8_ bus_busy data_storage 20 cr ct void main void define ARRAY_1 SIZE 6 5 Data bytes 1 address define ARRAY_2 SIZE 11 10 Data bytes 1 address const uint8_t eeprom_data_array_1 ARRAY_1_SIZE EEPROM_MEMORY_ADDRESS_LOWER 0x11 0x22 0x33 0x44 0x55 const uint8_t eeprom_data_array_2 ARRAY_2_ SIZE EEPROM_MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 Ox0A Ox0B Ox0C Ox0D Ox0E Ox0F
240. R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set pin options R_SCI_Set 0 if defined DEVICE_PACKAGE_64_PIN amp amp defined DEVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCIO_RXDO_PB1 PDL_SCI_PIN_SCIO_TXDO_PB2 PDL_SCI_PIN_SCIO_SCKO_PB3 else PDL_SCI_PIN_SCIO_RXDO_P24 PDL_SCI_PIN_SCIO_TXDO_P30 PDL_SCI_PIN_SCIO_SCKO_P23 endif R20UT2201EE0211 Rev 2 11 RENESAS Page 374 of 418 Sept 12 2014 RX63T Group 5 Usage Examples R_SCI_Set 1 if defined DEVICE_PACKAGE_64_PIN amp amp defined DEVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1_TXD1_PD3 PDL_SCI_PIN_SCI1_SCK1_PD4 else PDL_SCI_PIN_SCI1_RXD1_P93 PDL_SCI_PIN_SCI1_TX PDL_SCI_PIN_SCI1_SCK1_P92 endif y Create Clock master channel for Rx and Tx R_SCI_Create MASTER_CHANNEL PDL_SCI_SYNC PDL_SCI_CLK_INT_OUT 19200 1 0 Create Slave Channel NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R_SCI_Create SLAVE_CHANNEL PDL_SCI_SYNC PDL_SCI_CLK_EXT 0x80000000 19200 1 0 Y First setup the slave to send data_sent false R_SCI_Send SLAVE_CHANNEL PDL_NO_DATA Slave DATA_LENGTH SCI_Tx_Callback
241. R_CLEAR or When the DMAC transfer is complete clear the PDL_DMAC_TRIGGER_FORWARD DMAC activation trigger or pass it on to the CPU e DTC trigger control PDL_DMAC_DTC_ TRIGGER DISABLE or Disable or enable activation of the DTC when PDL DMAC DTC TRIGGER ENABLE an event specified in the Interrupt e gt generation options occurs data3 Select one activation source for channel DMAn e Trigger selection Name Trigger cause PDL_DMAC_TRIGGER_SW or By software PDL_DMAC_TRIGGER_CMTO or PDL_DMAC_TRIGGER_CMT1 or Compare match on channel CMTn PDL_DMAC_TRIGGER_CMT2 or n 0 to 3 PDL_DMAC_TRIGGER_CMTS3 or PDL_DMAC_TRIGGER_USBO_DO or DOFIFO transfer request on USB port 0 PDL_DMAC_TRIGGER_USBO_ Di or D1FIFO transfer request on USB port 0 PDL_DMAC_TRIGGER_SPIO_RX or PDL_DMAC_TRIGGER_SPI1_RX or PDL_DMAC_TRIGGER_SPIO_TX or Transmit buffer empty on SPI channel n PDL_DMAC_TRIGGER_SPI1_TX or n 0 to 1 PDL_DMAC_TRIGGER_IRQO or PDL_DMAC_TRIGGER_IRQ1 or PDL_DMAC_TRIGGER_IRQ2 or PDL_DMAC_TRIGGER_IRQ3 or Valid edge detected on pin IRQn PDL_DMAC_TRIGGER_IRQ4 or n 0 to 7 PDL_DMAC_TRIGGER_IRQ5 or PDL_DMAC_TRIGGER_IRQ6 or PDL_DMAC_TRIGGER_IRQ7 or Receive buffer full on SPI channel n n 0 to 1 PDL_DMAC_TRIGGER_ADC10 or Conversion completed on the 10 bit ADC unit PDL_DMAC_TRIGGER_S12ADI
242. R_CMP1 PDL_INTC_REG_IPR_CAN1 PDL_INTC_REG_IPR_CMP2 PDL_INTC_REG_IPR_GPT7_GTCIAC PDL_INTC_REG_IPR_GPT4_ GTCIAC PDL_INTC_REG_IPR_GPT7_GTCIEV PDL_INTC_REG_IPR_GPT4_GTCIEVLOCO PDL_INTC_REG_IPR_CMP4 PDL_INTC_REG_IPR_GPT5_GTCIAC PDL_INTC_REG_IPR_CMP5 PDL_INTC_REG_IPR_GPT5_GTCIEV PDL_INTC_REG_IPR_CMP6 PDL_INTC_REG_IPR_GPT6_GTCIAC PDL_INTC_REG_IPR_DOC PDL_INTC_REG_IPR_GPT6_GTCIEV PDL_INTC_REG_IPR_ICU_IRQO PDL_INTC_REG_IPR_IIC1 PDL_INTC_REG_IPR_ICU_IRQ1 PDL_INTC_REG_IPR_IICO PDL_INTC_REG_IPR_ICU_IRQ2 PDL_INTC_REG_IPR_DMAC_DMACOI PDL_INTC_REG_IPR_ICU_IRQ3 PDL_INTC_REG_IPR_DMAC_DMAC1I PDL_INTC_REG_IPR_ICU_IRQ4 PDL_INTC_REG_IPR_DMAC_DMAC2I PDL_INTC_REG_IPR_ICU_IRQ5 PDL_INTC_REG_IPR_DMAC_DMAC3I PDL_INTC_REG_IPR_ICU_IRQ6 PDL_INTC_REG_IPR_SCIO PDL_INTC_REG_IPR_ICU_IRQ7 PDL_INTC_REG_IPR_SCI1 PDL_INTC_REG_IPR_ICU_GROUPO PDL_INTC_REG_IPR_SCI2 PDL_INTC_REG_IPR_ICU_GROUP12 PDL_INTC_REG_IPR_SCI3 PDL_INTC_REG_IPR_AD ADI PDL_INTC_REG_IPR_GPTO_GTCIAC PDL_INTC_REG_IPR_S12AD_S12ADI PDL_INTC_REG_IPR_GPTO_GTCIEVLOCO PDL_INTC_REG_IPR_S12AD_S12GBADI PDL_INTC_REG_IPR_GPT1_GTCIAC PDL_INTC_REG_IPR_S12AD_S 12ADI1 PDL_INTC_REG_IPR_GPT1_GTCIEV PDL_INTC_REG_IPR_S12AD_S12GBADI1 PDL_INTC_REG_IPR_GPT2_GTCIAC PDL_INTC_REG_IPR_SCI12_SCIX PDL_INTC_REG_IPR_GPT2_GTCIEV PDL_INTC_REG_IPR_GPT3_GTCIAC PDL_INTC_REG_IPR_GPT3_GTCIEV PDL_INTC_REG_IPR_SCI12 R20UT2201EE0211 Rev 2 11 ENESAS Page 71 of 418 Sept 12 2014 RX63T Group 4 Library Reference DTCER register definitions Some DTCE
243. SCI RXI interrupt routine See source file Interrupt_SCl c for details The range of achievable bit rates bps is listed below e MTU3 clock can not be used on some device pin packages Data frcLkB voae clock erat 50 MHz 32 MHz 12 5 MHz 12 MHz 8 MHz source infernal Minimum 96 62 24 23 16 Asynchronous Maxinum 3 125 000 2 000 000 781 250 750 000 500 000 External 1 562 500 1 000 000 390 625 375 000 250 000 inte nal Minimum 763 489 191 184 123 Synchronous Maximum 6 250 000 4 000 000 1 562 500 1 500 000 1 000 000 External 8 333 333 5 333 333 2 083 333 2 000 000 1 333 333 Smart card Internal Minimum E 2 1 L L Maximum 781 250 500 000 195 312 187 500 125 000 Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Configure SCIO for asynchronous 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC 38400 1 0 PDL_SCI_8N1 i Configure SCI1 for asynchronous 8N1 register values supplied R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 BIT_31 PDL_SCI_PCLK_DIV_1 PDL_SCI_CYCLE_BIT_16 115200 amp OxOOFFFFOO 0x50 1 0 R20UT2201EE0211 Rev 2 11 ENESAS Page 242 of 418 Sept 12 2014 RX63T Group 4 Library Reference 3 R_SCI_ Destroy Synopsis Prototype Description Return value Category Reference Remarks
244. SET_COUNTER Refresh the counter True if all parameters are valid and exclusive otherwise false Watchdog Timer R_WDT_Set R_WDT_Set must be called first to configure the timer unless using Initial Setting Memory using R_MCU_OFS to enable the WDT from reset RPDL definitions tinclude r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h void func void Prevent the watchdog timer from overflowing R_WDT_Control PDL_WDT_RESET_COUNTER Y Rev 2 11 EN ESAS Page 228 of 418 RX63T Group 3 R_WDT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference Read the Watchdog timer status bool R_WDT_Read uinti6_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 b13 b0 Refresh Error Flag Underflow Flag 1 Refresh error 1 Underflow Down Counter Value 0 No refresh error 0 No underflow True Watchdog Timer f the Underflow flag is set to 1 it shall be automatically cleared to 0 by this function e Ifthe Refresh flag is set to 1 it shall be automatically cleared to O by this function RPDL definitions
245. Saw Counting up GTPR 2 or more Counting down 2 or less Triangle Counting down 2 or less The GTPR register is loaded from the Cycle setting register value set in data11 of R_GPT_ControlChannel RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h R_GPT_EdgeDelay_Times_structure Delay2 void func void Adjust channel 2 delay times Delay2 GTIOCA_Rising_Delay 1 Delay2 GTIOCA_Falling_Delay 2 Delay2 GTIOCB_Rising_Delay 3 Delay2 GTIOCB_Falling_Delay 4 R_GPT_EdgeDelay_Control ELAY TIME 2 PDL_GPT_PWM_D amp Delay2 ENESAS Page 216 of 418 RX63T Group 11 R_GPT_EdgeDelay_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Disable the Edge Delay circuit bool R_GPT_EdgeDelay_Destroy uint8_t data Unit selection Disable the edge delay circuit on all channels data The unit number n where n 0 True General PWM Timer unit None RPDL definitions tinclude r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void Disable the Edge Delay circuits R_GPT_EdgeDelay_Destroy 0 Y Rev 2 11 ENESAS 4 Library Reference P
246. Select the operation states All selections are optional If multiple selections are required use to separate each selection e On chip ROM control 4 Library Reference PDL_MCU_ROM_ENABLE or PDL_MCU_ ROM DISABLE Enable or disable the on chip ROM e Software reset control PDL_MCU_RESET_START Start a software reset of the MCU e Start type flag control PDL_MCU_WARM_START Set the Start type status flag to Warm True if a valid register is specified otherwise false MCU registers None e None RPDL definitions tinclude r_pdl_mcu h RPDL device specific definitions tinclude r_pdl_definitions h void func void Modify the MCU operation R_MCU_Control PDL_MCU_ROM_DISABLE Rev 2 11 ENESAS Page 96 of 418 RX63T Group 4 Library Reference 2 R_MCU_GetStatus Synopsis Read the MCU status Prototype bool R_MCU_GetStatus uint16_t data1 The location where the mode status flags shall be stored uint16_t data2 The location where the reset status flags shall be stored uint32_t data3 The storage location for the Option Function Select Register O uint32_t data4 The storage location for the Option Function Select Register 1 Description Read the status registers for the MCU data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required For pac
247. T2201EE0211 Sept 12 2014 data1 4 Library Reference S S Clock source selection If no change is required specify PDL_NO_DATA e Clock source selection PDL_CGC_CLK_LOCO or PDL_CGC_CLK_MAIN or PDL_CGC_CLK_PLL main clock os Phase locked Select the low speed on chip oscillator LOCO cillator or loop PLL circuit data2 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection e BCLK pin output control ignored if the device package does not support the external bus PDL_CGC_BCLK_ENABLE or PDL_CGC_BCLK DISABLE Enable or disable the BCLK pin output e Low speed on chip oscillator control PDL_CGC_LOCO_ENABLE or PDL_CGC_LOCO_DISABLE Enable or disable the LOCO e Main clock oscillator control PDL_CGC_MAIN_ENABLE or PDL_CGC_MAIN_DISABLE Enable or disable the main clock oscillator Main clock oscillator forced oscillation cont rol PDL_CGC_MAIN_FORCED_ENABLE or PDL_CGC_MAIN_FORCED_ DISABLE Enable or disable forced oscillation of the main clock oscillator e Main clock Oscillation Stop Detection contr O PDL_CGC_OSC_STOP_ENABLE or PDL_CGC_OSC_STOP_INTERRUPT or PDL_CGC_OSC STOP _DISABLE Enable without or with interrupt request output or disable the oscillation stop detection function for the main clock
248. TC_Create func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors Rev 2 11 EN ESAS Page 247 of 418 RX63T Group Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference True if all parameters are valid and the operation completed false if a parameter was out of range SCI R_SCI_Control R_SCl_GetStatus R_SCI_Create R_SCI_Send The maximum number of characters to be received is 65535 Wait until a transmission on the same channel is complete before calling this function If callback function func1 is specified reception interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed In Multi processor mode R_SCI_ Receive is to be called in a pair the first one is to receive ID ID cycle the second one is to receive data Data cycle For ID reception it could be done by reception interrupt by specifying func1
249. TC_VECTOR_GTCICO PDL_INTC_VECTOR_GTCIEO PDL_INTC_VECTOR_GTCIVO PDL_INTC_VECTOR_LOCOIO General PWM timer channel 0 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match LOCO count function event PDL_INTC_VECTOR_GTCIA1 PDL_INTC_VECTOR_GTCIB1 PDL_INTC_VECTOR_GTCIC1 PDL_INTC_VECTOR_GTCIE1 PDL_INTC_VECTOR_GTCIV1 General PWM timer channel 1 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match PDL_INTC_VECTOR_GTCIA2 PDL_INTC_VECTOR_GTCIB2 PDL_INTC_VECTOR_GTCIC2 PDL_INTC_VECTOR_GTCIE2 PDL_INTC_VECTOR_GTCIV2 General PWM timer channel 2 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match PDL_INTC_VECTOR_GTCIA3 PDL_INTC_VECTOR_GTCIB3 PDL_INTC_VECTOR_GTCIC3 PDL_INTC_VECTOR_GTCIE3 PDL_INTC_VECTOR_GTCIV3 General PWM timer channel 3 Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match Return value Category Reference R20UT2201EE0211 Sept 12 2014 Rev 2 11 True Interrupt control ENESAS Page 63 of 418
250. TIME_DOWN a downr counting PDL_GPT_REGISTER_DEAD_TIME_DOWN_BUFFER se down counting butter The following register values will be ignored if they have not been selected above data4 The timer counter GTCNT value data5 The general register A GTCCRA value data6 The general register B GTCCRB value data7 The general register C GTCCRC value data8 The general register D GTCCRD value R20UT2201EE0211 Rev 2 11 RENESAS Sept 12 2014 Page 203 of 418 RX63T Group Description 3 3 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference data9 The general register E GTCCRE value data10 The general register F GTCCRF value data11 The cycle setting register GTPR value data12 The cycle setting buffer register GTPBR value data13 The cycle setting double buffer register GTPDBR value data14 The ADC start request register GTADTRA value data15 The ADC start request buffer register GTADTBRA value data16 The ADC start request double buffer register GTADTDBRA value data17 The ADC start request register GTADTRB value data18 The ADC start request buffer register GTADTBRB value data19 The ADC start request double buffer register GTADTDBRB value data20 The dead time up counting register GTDVU value data21 The dead time up counting
251. TU pins that are not used Using R_POE_GetStatus to get the oscillation stop detection flag All settings related to POE4 of data2 are not available on the 64 and 48 pin packages All settings related to POE 12 of data2 are not available on the 100 64 and 48 pin packages All settings related to GPT6 7 MTU6 7 MTIOC7n m AC BD GTIOCn n 6 7 are not available on the 64 and 48 pin packages The settings PDL_POE_HI_Z_ MT34_ADD_CFLAG and PDL_POE_HI_Z_MT34_ADD_POEn n 8 10 11 also support to control Hi z for MTU6 7 on the 64 and 48 pin packages The setting PDL_POE_SHORT_MTUm m 34 67 is available on 64 and 48 pin packages The settings PDL_POE_SHORT_USE_MTU PDL_POE_SHORT_SPECIFY and PDL_POE_SHORT_Pm_HIGH LOW m 71 to 76 also support to set active level for MTU6 7 on the 64 and 48 pin packages RPDL definitions r pdl_poe h RPDL device specific definitions include r_pdl_definitions h void func void Rev 2 11 Configure POE pins R_POE_Set PDL_POE_0_MODE_EDGE PAN PDL_POE_8_MODE_LOW_16 PDL_POE_10_MODE_LOW_128 PDL_POE_HI_Z_REQ_8_ENABLE PDL_POE_H1_Z_MT34_ADD_CFLAG PDL_POE_H1_Z_GPTO1_ADD_POE11 PDL_NO_DATA PDL_POE_H1I_Z_ENABLE_MTIOCOA PDL_POE_HI_Z ENABLE _MTIOC3BD PDL_POE_HI_Z ENABLE_GTIOC3 PDL_POE_SHORT_SPECIFY
252. T_50 or PDL_IWDT_WIN_START_75 or PDL_IWDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_IWDT_WIN_END_0 or PDL_IWDT_WIN_END_25 or PDL_IWDT_WIN_END_50 or PDL_IWDT_WIN_END 75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifiying 0 is equivalent to no window end position Sleep Mode Count Stop PDL_IWDT_STOP_DISABLE or PDL_IWDT_STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode True if all parameters are valid and exclusive otherwise false Independent Watchdog Timer R MCU_OFS R_CGC_Set R_CGC_Control R_INTC_CreateExtInterrupt Rev 2 11 If using the Initial Setting Memory using R_MCU_OFS to enable the IWDT from reset this function will have no affect and can be omitted The IWDTCLK must be enabled using R_CGC_Set or R_CGC_Control If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for IWDT The IWDT counter frequency must not be greater than the PCLKB 4 Set the IWDTCLK division ratio accordin
253. T_INT_SKIP PDL_GPT_INT_SKIP_4 or If skipping is enabled select the skipping count PDL_GPT_INT_SKIP GTCCRA Compare Match or Input Capture GTCCRB Compare Match or Input Capture GTCCRC Compare Match PDL_GPT_INT_SKIP If O PDL_GPT_INT_SKIP 6 ales ed PDL_GPT_INT_SKIP SEGG other GTCCRD Compare Match PDL_GPT_INT_SKIP PDL_GPT_INT_SKIP THM OO QO gt N events to GTCCRE Compare Match GTCCRF Compare Match PDL_GPT_ADC_TRIG_SKIP_A ee GTADTRAADC converter start request PDL_GPT_ADC_TRIG_SKIP_B GTADTRB ADC converter start request Rev 2 11 EN ESAS Page 197 of 418 RX63T Group Description 6 7 R20UT2201EE0211 Sept 12 2014 data9 Buffer control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Rev 2 11 GTCCRA buffer operation 4 Library Reference PDL_GPT_BUFFER_CMIC_A DISABLE or PDL_GPT_BUFFER_CMIC_A SINGLE or PDL_GPT BUFFER CMIC_A DOUBLE Disable or select single or double buffer operation for register GTCCRA GTCCRB buffer operation PDL_GPT_BUFFER_CMIC_B_DISABLE or PDL_GPT_BUFFER_CMIC_B SINGLE or PDL_GPT BUFFER CMIC_B DOUBLE GTPR buffer operation Disable or select single or double buffer operation for register GTCCRB PDL_GPT_BUFFER_CYCLE_D
254. U3_V_IC_PWM_HIGH_BOTH both for high pulse width measurement Input capture compare match control for register TGRW PDL_MTU3_W_CM or Compare match PDL_MTU3_W_IC_RISING_EDGE or PDL_MTU3_W_IC_FALLING_EDGE or Input capture at MTICnW rising edge Input capture at MTICnW falling edge PDL_MTU3_W_IC_BOTH_EDGES or Input capture at MTICnW both edges PDL_MTU3_W_IC_PWM_LOW_TROUGH or Input capture at trough PDL_MTU3_W_IC_PWM_LOW_CREST or crest or PDL_MTU3_W_IC_PWM_LOW_ BOTH or both for low pulse width measurement PDL_MTU3_W_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU3_W_IC_PWM_HIGH_CREST or crest or PDL_MTU3_W_IC_PWM_HIGH_BOTH both for high pulse width measurement TCNT_TCNTU_value For n 5 The timer counter TCNT value For n 5 The timer counter TCNTU value TGRA_TCNTV_value For n 5 The register TGRA value For n 5 The timer counter TCNTV value TGRB_TCNTW_value For n 5 The register TGRB value For n 5 The timer counter TCNTW value TGRC_TGRU_value For n 0 3 4 6 and 7 The register TGRC value For n 5 The register TGRU value Ignored for other channel TGRD_TGRV_value For n 0 3 4 6 and 7 The register TGRD value For n 5 The register TGRV value Ignored for other channel TGRE_TGRW_value For n 0 3 4 6 and 7 The register TGRE value For n 5 The register TGRW value Ignored for other chan
255. U6 PDL_ADC_10_ TRIGGER _MTU7_CMIC or MTU7 TRGA compare match input capture or MTU7 TCNT underflow trough in complementary PWM mode PDL_ADC_10_TRIGGER_MTUO_CM_E or TRGE compare match from MTUO PDL_ADC_10_ TRIGGER MTU4_CM_ Aor MTU4 TADCORA and MTU4 TCNT compare match PDL_ADC_10_ TRIGGER _MTU4_CM Bor MTU4 TADCORB and MTU4 TCNT compare match PDL_ADC_10_TRIGGER_MTU4_CM_AB or MTU4 TADCORA and MTU4 TCNT compare match or MTU4 TADCORB and MTU4 TCNT compare match PDL_ADC_10_ TRIGGER MTU4_CM_AB IS or MTU4 TADCORA and MTU4 TCNT compare match and MTU4 TADCORB and MTU4 TCNT compare match interrupt skipping function 2 PDL_ADC_10_TRIGGER_MTU7_CM_Aor MTU7 TADCORA and MTU7 TCNT compare match PDL_ADC_10_TRIGGER_MTU7_CM_B or MTU7 TADCORB and MTU7 TCNT compare match PDL_ADC_10_ TRIGGER _MTU7_CM_AB or MTU7 TADCORA and MTU7 TCNT compare match or MTU7 TADCORB and MTU7 TCNT compare match PDL_ADC_10_ TRIGGER _MTU7_CM_AB IS or MTU7 TADCORA and MTU7 TCNT compare match and MTU7 TADCORB and MTU7 TCNT compare match interrupt skipping function 2 PDL_ADC_10_ TRIGGER _GPTO_CM Aor GPTO GTADTRA compare match PDL_ADC_10_TRIGGER_GPTO_CM Bor GPTO GTADTRB compare match PDL_ADC_10_ TRIGGER GPT1_CM Aor GPT1 GTADTRA compare match PDL_ADC_10_ TRIGGER GPT1 CM Bor GPT1 GTADTRB compare match PDL_ADC_10 TRIGGER GPT2_CM_Aor GPT2 GTADTRA compare match
256. UT2201EE0211 Sept 12 2014 data1 Control and DTC DMAC options Interrupt options Automatic clearing and hardware control options Hardware control selections VO pin control options VO pin control options ADC trigger and skipping control options Buffer control options Negate and Dead time control options Callback function Callback function Callback function Interrupt priority level Callback function Callback function Callback function Interrupt priority level The channel number n where n 0 to 3 for 64 and 48 pin packages n 0 to 7 for 144 120 112 100 pin packages data2 Control options If multiple selections are required use to separate each selection e Operation mode PDL_GPT_MODE_SAW or Saw wave mode PDL_GPT_MODE_SAW_ONE_SHOT or Saw wave one shot pulse mode PDL_GPT_MODE_TRIANGLE_1 or PDL_GPT_MODE_TRIANGLE_2 or Triangle wave PWM mode 1 2 or 3 PDL_GPT_MODE_TRIANGLE_3 e Counter clock source selection PDL_GPT_CLK_PCLK_DIV_1 or PDL_GPT_CLK_PCLK_DIV_2 or PDL_GPT_CLK_PCLK_DIV_4 or The internal clock signal PCLKA 1 2 4 or 8 PDL_GPT_CLK_PCLK_DIV_8 Rev 2 11 ENESAS Page 193 of 418 RX63T Group Description 2 7 DTC DMAC event trigger control 4 Library Reference R20UT2201EE0211 Sept 12 2014 PDL_GPT_CMICA_DMAC_DTC_TRIGGER_DISA
257. UT2201EE0211 Sept 12 2014 Modify an MPC register bool R_MPC_Modify uint8_t data1 MPC register selection uint8_t data2 Logical operation uint8_tdata3 Modification value Write the value to an MPC register data1 One of the definition values from 4 2 4 data2 e The logical operation to be applied to the register contents PDL_MPC_AND or PDL_MPC_OR or Select between AND amp OR or Exclusive OR PDL_MPC_XOR data3 The value to be used for the modification True if a valid MPC register is specified otherwise false MPC registers None The MPC registers are modified by other driver functions Take care to not overwrite existing settings Refer to the hardware manual for valid values for each register RPDL definitions include r_pdl_mpc h RPDL device specific definitions include r_pdl_definitions h void func void Set bit 7 in P72PFS to 1 R_MPC_Modify PDL_MPC_REG_P72PFS PDL_MPC_OR 0x80 Rev 2 11 ENESAS Page 95 of 418 RX63T Group 4 2 5 MCU operation 1 R_MCU_Control Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Control the operation of the MCU bool R_MCU_Control uint8_tdata Control options Modify the MCU control registers data
258. WDT CLOCK_LOCO 256 The selected clock The LOCO 1 16 32 64 128 or 256 Window end position PDL_MCU_OFS_IWDT_WIN_END_75 or The window end position specified as a PDL_MCU_OFS_IWDT_WIN_END_50 or percent of the down counter 0 is when the PDL_MCU_OFS_IWDT_WIN_END_25 or down counter would underflow Selecting 0 PDL_MCU_OFS_IWDT_WIN_END_0 is equivalent to no window end position Window start position POL MCU OFS WDT_WIN START 250r Test a a aa pit an PDL MGU OFS_IWDT_WIN_START_S00f fe down counter would uindarflow PDL MCU OFSIWDT_WIN_START 75 Or Selecting 100 is equivalent to no window PDL_MCU_OFS_IWDT_WIN_START_100 g 497013 89 start position Underflow action PDL_MCU_OFS_IWDT_NMI or Select an NMI or reset when the IWDT PDL_MCU_OFS_IWDT_ RESET down counter underflows Count stop mode PDL_MCU_OFS_IWDT STOP_DISABLE or PDL_MCU_OFS_IWDT STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode ENESAS Page 99 of 418 RX63T Group 4 Library Reference Description 2 2 data2 Select the post reset WDT configuration settings If multiple selections are required use to separate each selection Auto start control PDL_MCU_OFS_WDT_HALTED
259. X63T Group 4 Library Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Either this function or R_MTU3_ControlChannel must be used to start the timers The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call The register access enable operation is executed at the start of this function The register access disable operation is executed at the end Therefore both options can be selected together with other changes in one function call The enabling of reset synchronised or complementary PWM mode is made after all other configuration settings are made and before the timers are started R_MTU3_Create must be used first to configure the timer channel 3 or 6 A companion function R_MTU3_ControlUnit_load_defaults can be used to load the default values into the structure When generating PWM waveforms in complementary PWM mode 1 to complementary PWM mode 3 set the timer cycle data registers TCDRA or TCDRB and timer dead time data registers TDDRA or TDDRB to values that satisfy the following condition Timer cycle data register value gt Timer dead time data register value x 2 2 Output protection function for complementary PWM mode is enabled at the initial state To disable this function call API R_POE_Set without options settings to MTU3 MTU4 MTU
260. X63T Group 4 2 23 12 bit Analog to Digital Converter 1 R_ADC_12 Set Synopsis Prototype Description Select the I O pins for the 12 bit ADC bool R_ADC_12_Set uinti6 tdata ADC pin selection Select the I O pins for the12 bit ADC data 4 Library Reference Select the pin set options To set multiple options at the same time use to separate each value Pin selection Please refer to Table 21 1 at the Multifunction Pin Controller MPC section in the RX63T Hardware Manual for details of pin package PDL_ADC_12 PIN_ANOOO_P40 Select P40 for ANOOO PDL_ADC_12_PIN_ANOO1_P41 Select P41 for ANOO1 PDL_ADC_12_PIN_ANO02_P42 Select P42 for AN002 PDL_ADC_12_PIN_ANO03_P43 Select P43 for ANOO3 PDL_ADC_12_PIN_AN004 P44 Select P44 for ANO04 PDL_ADC_12_PIN_ANO05_P45 Select P45 for ANOO5 PDL_ADC_12_PIN_ANO06_P46 Select P46 for ANOO6 PDL_ADC_12_PIN_ANO07_P47 Select P47 for ANOO7 PDL_ADC_12_PIN_AN100 P44 Select P44 for AN100 PDL_ADC_12_PIN_AN101_P45 Select P45 for AN101 PDL_ADC_12_PIN_AN102_P46 Select P46 for AN102 PDL_ADC_12_PIN_AN103_P47 Select P47 for AN103 PDL ADC 12 PIN CVREFL_P43 Select P43 for CVREFL PDL ADC 12 PIN CVREFH_P47 Select P47 for CVREFH PD
261. Z ENABLE _GTIOC3 software control or the oscillation stop detection PDL_POE_HI_Z ENABLE_GTIOC6 flag PDL_POE_HI_Z ENABLE _GTIOC7 data5 Output short detection and response All selections are optional If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output short detection channel PDL_POE_SHORT_MTU34 or Selects whether MTU3 4 or MTU6 7 are used as PDL_POE_SHORT_MTU67 the MTU complementary PWM output channel Output short detection level for MTU channel 3 and 4 PDL_POE_SHORT_USE_MTU or Use the active levels specified in the MTU3 PDL_POE_SHORT_SPECIFY functions or enable the settings below PDL_POE_SHORT_P71_LOW or PDL_POE_SHORT_P71_HIGH PDL_POE_SHORT_P74_LOW or PDL_POE_SHORT_P74_HIGH edge heats ai dae rAd or Select the port pin active level for detection of short PDL FOE SHORT Eee circuits Ignored if the MTU settings for channel PDL_POE_SHORT_P75_LOW or 3 4 Aretes d PDL_POE_SHORT_P75_ HIGH PDL_POE_SHORT_P73_LOW or PDL_POE_SHORT_P73_HIGH PDL_POE_SHORT_P76_LOW or PDL_POE_SHORT_P76_HIGH e Output short detection level for MTU channel 6 and 7 Use the active levels specified in the MTU3 Barg etme tH etna bd of alll 6 7 functions or enable the settings PDL_POE_SHORT_67_P95_LOW or PDL_POE_SHORT_67_P95_HIGH PDL_POE_SHORT_67_P92_LOW or PDL_POE_SHORT_67_P92_HIGH FDL FOE SHORT eo Select the port pin active level for detection of short POL
262. _11_ENABLE Disable or enable an interrupt on detection of any high impedance request on pin POE10 Disable or enable an interrupt on detection of any high impedance request on pin POE11 PDL_POE_IRQ_HI_Z 12 DISABLE or PDL_POE_IRQ_HI_Z 12 ENABLE Disable or enable an interrupt on detection of any high impedance request on pin POE12 Output short detection response PDL_POE_IRQ_SHORT_34_DISABLE or PDL_POE_IRQ_SHORT_34 ENABLE Disable or enable an interrupt on detection of a short on any MTU channel 3 4 two phase output pair PDL_POE_IRQ_SHORT_67_DISABLE or PDL_POE_IRQ_SHORT_67_ ENABLE Disable or enable an interrupt on detection of a short on any MTU channel 6 7 two phase output pair funci The function to be called when an enabled request on pins POEO or an output short on MTU channels 3 or 4 occurs Specify PDL_NO_FUNC if not required func2 The function to be called when an enabled request on pin POE4 or an output short on MTU channels 6 or 7 occurs Specify PDL_NO_FUNC if not required func3 The function to be called when an enabled request on pin POE8 occurs Specify PDL_NO_FUNC if not required func4 The function to be called when an enabled request on pin POE10 or POE11 occurs Specify PDL_NO_FUNC if not required func5 The function to be called when an enabled request on pin POE4 or POE12 occurs Specify PDL_NO_FUNC if not required ENESAS
263. _COUNT_CLK_PCLK_DIV_4 or frequency divided IWDTCLK PDL_GPT_IWDTCLK_COUNT_CLK _PCLK DIV_8 clock PDL_GPT_IWDTCLK_CLK_DIV_1 or Select the frequency division ratio PDL_GPT_IWDTCLK_CLK_DIV_16 or 1 16 128 or 256 of the PDL_GPT_IWDTCLK_CLK DIV_128 or frequency divided IWDTCLK PDL_GPT_IWDTCLK_CLK_DIV_256 clock IWDTCLKk derived rising edge skipping control PDL_GPT_IWDTCLK_SKIP_NONE or Select an interrupt request on every PDL_GPT_IWDTCLK_SKIP_8 or every 8th PDL_GPT_IWDTCLK_SKIP_16 or every 16th PDL_GPT_IWDTCLK_SKIP_128 or every 128th or PDL_GPT_IWDTCLK_SKIP_256 every 256th rising edge Disable or enable skipping of count results transfers at the same interval as the interrupt request skipping PDL_GPT_IWDTCLK_RESULT_SKIP_DISABLE or PDL_GPT_IWDTCLK_RESULT_SKIP_ENABLE IWDTCLK event interrupt request selection Each event is disabled by default PDL_GPT_IWDTCLK_INT_RISING ENABLE IWDTCLK derived rising edge using the selected skipping interval The IWDTCLK frequency deviation PDL_GPT_IWDTCLK_INT_DEVIATION ENABLE nas exceeded a permiseble imit PDL_GPT_IWDTCLK_INT_OVERFLOW_ENABLE IWDTCLK counter overflow DTC DMAC event trigger control Activate the DTC or PDL_GPT_EXT_IWDTCLK_DMAC_DTC_TRIGGER_DISABLE or DMAC on a valid PDL_GPT_EXT_IWDTCLK_DMAC_TRIGGER_ENABLE or external trigger or PDL_GPT_EXT_IWDTCLK_DTC_TRIGGER_ENABLE enabled IWDTCLK event interrupt If a DTC or DM
264. _Control R_CGC_Set R_LPC_Create Rev 2 11 ENESAS Page 114 of 418 RX63T Group 4 Library Reference Remarks e If PDL_LPC_IO_DELAY is specified use R_LPC_Control with the PDL_LPC_IO_RELEASE option to cancel the I O port state retention The IRQn DS pins are the only IRQ pins that can be used to exit from deep software standby mode When the flash memory is in program or erase mode do not call this function if it will result in the power mode changing This function will return false is this situation During the period from the time of WAIT instruction issuance for a sleep mode transition to return from sleep mode to normal operation do not call this function Ifthe NMI pin is enabled for cancelling deep software standby mode it cannot be disabled e Use R_CGC_Control to stop and start the clocks as required Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Allow a falling edge on IRQ2 DS to cancel deep software standby R_LPC_Create PDL_NO_DATA PDL_LPC_CANCEL_IRQ2_FALLING PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT2201EE0211 Rev 2 11 RENESAS Page 115 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_LPC_ Control Synopsis Select a low power consumption mode Prototype bool R_LPC_Control uint32_t data Mode selec
265. _Create DMAC_CHANNEL PDL_DMAC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_FIX PDL_DMAC_SIZE_16 PDL_DMAC_IRO_END PDL_DMAC_T ER_SW data Source void amp DOC DODIR Destination It Transfer Count DATA_COUNT Data length PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback_Done Callback done function 15 Interrupt priority y Enable and start the DMAC R_DMAC_Control DMAC_CHANNEL PDL_DMAC_ENABLE PDL_DMAC START PDL_NO_ PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT2201EE0211 Rev 2 11 AS Page 413 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples L_NO_DAT L_NO_DAT y Wait for DMAC to complete while false g_bCallbackDone Read the result including checking for overflow R_DOC_Read amp status result while 1 static void Callback_Done void g_bCallbackDone true Figure 5 46 Example of DOC R20UT2201EE0211 Rev 2 11 AS Page 414 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 25 Multifunction Pin Controller Figure 5 47 Example of MPC show an example multifunction pin controller usage Peripheral driver function prototypes tinclude r_pdl_mpc h PDL device specific definitions tinclude r_pdl_definitions h void main void uint8_t data Write data to register
266. _Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CHAIN dtc_sw_transfer_data 8 source_string_3 destination_string_3 1 uint8_t strlen source_string_3 Start the controller R_DTC Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA y Generate a software interrupt request R_INTC_Write PDL_INTC_REG_SWINTR 1 Figure 5 13 Example of DTC chain transfer R20UT2201EE0211 Rev 2 11 AS Page 358 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 11 Port Output Enable Figure 5 14 shows a usage example of Port Output Enable function PDL functions tinclude r_pdl_poe h PDL device specific definitions tinclude r_pdl_definitions h void POE8_handler void void main void Configure POE mode R_POE_Set PDL_POE_8_MODE_LOW_16 PDL_POE_HI_Z_REQ_8_ENABLE PDL_NO_DATA PDL_NO_DATA PDL_POE_SHORT Y Configure POE event handling R_POE_Create PDL_POE_TRO_HI_Z_8_ENABLE PDL_NO_FUNC PDL_NO_FUNC POE8_handler PDL_NO_FUNC PDL_NO_FUNC 15 Y void POE8_handler void uintl6_t StatusFlags Read the POE status R_POE_Get Status amp StatusFlags y Prevent further
267. _DMAC_TRIGGER_GPTB2 or PDL_DMAC_TRIGGER_GPTB3 or PDL_DMAC_TRIGGER_GPTB4 or PDL_DMAC_TRIGGER_GPTB5 or PDL_DMAC_TRIGGER_GPTB6 or PDL_DMAC_TRIGGER_GPTB7 or Compare match or input capture B on GPT channel n n 0 to 7 PDL_DMAC_TRIGGER_GPTCO or PDL_DMAC_TRIGGER_GPTC1 or PDL_DMAC_TRIGGER_GPTC2 or PDL_DMAC_TRIGGER_GPTC3 or PDL_DMAC_TRIGGER_GPTC4 or PDL_DMAC_TRIGGER_GPTC5 or PDL_DMAC_TRIGGER_GPTC6 or PDL_DMAC_TRIGGER_GPTC7 or Compare match C or D on GPT channel n n O to 7 PDL_DMAC_TRIGGER_GPTEO or PDL_DMAC_TRIGGER_GPTE1 or PDL_DMAC_TRIGGER_GPTE2 or PDL_DMAC_TRIGGER_GPTES or PDL_DMAC_TRIGGER_GPTE4 or PDL_DMAC_TRIGGER_GPTE5 or PDL_DMAC_TRIGGER_GPTE6 or PDL_DMAC_TRIGGER_GPTE7 or Compare match E or F on GPT channel n n 0 to 7 PDL_DMAC_TRIGGER_GPTVO or PDL_DMAC_TRIGGER_GPTV1 or PDL_DMAC_TRIGGER_GPTV2 or PDL_DMAC_TRIGGER_GPTV3 or PDL_DMAC_TRIGGER_GPTV4 or PDL_DMAC_TRIGGER_GPTV5 or PDL_DMAC_TRIGGER_GPTV6 or PDL_DMAC_TRIGGER_GPTV7 or Counter limit match V on GPT channel n n 0 to 7 Rev 2 11 ENESAS Page 135 of 418 RX63T Group 4 Library Reference Description 4 4 PDL_DMAC_TRIGGER_LOCOIO or LOCO count function event on GPT channel 0 Return value Category Referen
268. _GPT_DEAD_TIME_DOWN_MATCH_UP If any callback function is not required specify PDL_NO_FUNC func1 The function to be called when a Compare match Input capture A event occurs func2 The function to be called when a Compare match Input capture B event occurs func3 The function to be called when a Compare match C Compare match D or Dead Time error event occurs data11 The interrupt priority level for the above events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 1 to 3 func4 The function to be called when a Compare match E or Compare match F event occurs func5 The function to be called when an overflow and or underflow occurs func6 The function to be called when an enabled external trigger or IWDTCLK counter interrupt request occurs Ignored for n 0 4 data12 The interrupt priority level for the above events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 4 to 6 Rev 2 11 QEN ESAS Page 199 of 418 RX63T Group 4 Library Reference Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 True if all parameters are valid and exclusive otherwise false General PWM Timer unit R_GPT_CreateU
269. _GTCIEO PDL_INTC_REG_DTCER_GPTO_GTCIVO PDL_INTC_REG DTCER MTU3 TGIA PDL_INTC_REG_DTCER_GPTO_LOCO PDL_INTC_REG DTCER MTU3 TGIB PDL_INTC_REG_DTCER_GPT1_GTCIA1 PDL_INTC_REG_DTCER_MTU3_TGIC PDL_INTC_REG_DTCER_GPT1_GTCIB1 PDL_INTC_REG DTCER MTU3 TGID PDL_INTC_REG_DTCER_GPT1_GTCIC1 PDL_INTC_REG_DTCER_MTU4_TGIA PDL_INTC_REG_DTCER_GPT1_GTCIE1 PDL_INTC_REG_DTCER_MTU4_TGIB PDL_INTC_REG_DTCER_GPT1_GTCIV1 PDL_INTC_REG_DTCER_MTU4 TGIC PDL_INTC_REG DTCER GPT2 GTCIA2 PDL_INTC_REG_DTCER_MTU4_TGID PDL_INTC_REG DTCER GPT2 GTCIB2 PDL_INTC_REG_DTCER_MTU4_TCIV PDL_INTC_REG_DTCER_GPT2_GTCIC2 PDL_INTC_REG_DTCER_MTU5 TGIU PDL_INTC_REG DTCER GPT2 GTCIE2 PDL_INTC_REG DTCER MTU5 TGIV PDL_INTC_REG DTCER GPT2 GTCIV2 PDL_INTC_REG_DTCER_MTU5_TGIW PDL_INTC_REG_DTCER_GPT3_GTCIA3 PDL_INTC_REG DTCER MTU6 TGIA PDL_INTC_REG DTCER MTU6 TGIB PDL_INTC_REG_DTCER_GPT3_GTCIB3 PDL_INTC_REG_DTCER_GPT3_GTCIC3 PDL_INTC_REG_DTCER_MTU6_TGIC PDL_INTC_REG_DTCER_GPT3_GTCIE3 PDL_INTC_REG DTCER MTU6 TGID PDL_INTC_REG_DTCER_GPT3_GTCIV3 PDL_INTC_REG_DTCER_MTU7_TGIA PDL_INTC_REG_DTCER_SCI12_RXI PDL_INTC_REG_DTCER_MTU7_TGIB PDL_INTC_REG DTCER _SCI12_TXI PDL_INTC_REG_DTCER_MTU7_TGIC PDL_INTC_REG DTCER MTU7 TGID PDL_INTC_REG DTCER MTU7_ TCIV R20UT2201EE0211 Sept 12 2014 Rev 2 11
270. _IIC_SDA _DELAY_0 or PDL_IIC_SDA_DELAY_1 or PDL_IIC_SDA_DELAY_2 or PDL_IIC_SDA_DELAY_3 or PDL_IIC_SDA_DELAY_4 or PDL_IIC_SDA_DELAY_5 or PDL_IIC_SDA_DELAY_6 or PDL_IIC_SDA_DELAY_7 SDA output delay count Select the number of cycles for the SDA output delay counter SDA output delay clock source PDL_IIC_SDA_DELAY_DIV_1 or PDL_lIC_SDA DELAY DIV 2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter ENESAS Page 262 of 418 RX63T Group Description 2 3 4 Library Reference e Noise filter control R20UT2201EE0211 Sept 12 2014 PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3 or PDL_IIC_NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults e NACK Transmission Arbitration Lost Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode e Slave Arbitration Lost Detection control PDL_IIC_SALD_ DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE 0 DISABLE or Disable or enable detection o
271. _INTC_REG_IR SPI1_SPTI PDL_INTC_REG IR MTU5 TGIW PDL_INTC_REG IR CAN1 RXF PDL_INTC_ REG IR _MTU6 _TGIA PDL_INTC_REG_IR_CAN1_TXF PDL_INTC_REG_IR_MTU6_TGIB PDL_INTC_REG_IR_CAN1_RXM PDL_INTC_REG_IR_MTU6_TGIC PDL_INTC_REG IR CAN1 TXM PDL_INTC_REG IR _MTU6 TGID PDL_INTC_REG IR GPT7_GICIA PDL_INTC_ REG IR MTU6_TCIV PDL_INTC_REG IR GPT7_GICIB PDL_INTC_REG_IR MTU7 TGIA PDL_INTC_REG_IR_GPT7_GTCIC PDL_INTC REG IR MTU7 TGIB PDL_INTC_REG IR GPT7_GICIE PDL_INTC_REG IR MTU7 TGIC PDL_INTC_REG IR GPT7_GICIV PDL_INTC_REG IR MTU7 TGID PDL_INTC_REG IR CMP4 PDL_INTC_REG IR MTU7_TCIV PDL_INTC_REG IR CMP5 PDL_INTC_REG IR POE OEI1 PDL_INTC_REG IR CMP6 PDL_INTC_REG IR POE OEl2 PDL_INTC_REG IR DOC DOPCF PDL_INTC_REG IR POE OEI3 PDL_INTC_REG IR ICU_IRQO PDL_INTC_REG IR POE OEI4 PDL_INTC_ REG IR ICU_IRQ1 PDL_INTC_REG IR POE OEI5 PDL_INTC_REG IR ICU_IRQ2 PDL_INTC_REG IR_CMPO PDL_INTC_ REG IR ICU_IRQ3 PDL_INTC_REG IR CMP1 PDL_INTC_REG IR ICU_IRQ4 PDL_INTC_REG IR CMP2 PDL_INTC_ REG IR ICU_IRQ5 PDL_INTC_REG IR _GPT4 GTCIA PDL_INTC REG IR ICU IRQ6 PDL_INTC_ REG IR GPT4 GICIB PDL_ INTC REG IR ICU IRQ7 PDL_ INTC REG IR GPT4 GTCIC PDL_INTC_REG_IR AD ADI PDL_INTC_REG IR GPT4 GICIE PDL_INTC_REG IR S12AD_S12ADI PDL_INTC_REG IR GPT4 GTCIV PDL_INTC_REG IR S12AD S12GBADI PDL_INTC_REG IR _GPT4 LOCO PDL_INTC REG IR S12AD1_S12ADI PDL_INTC_ REG IR GPT5 GTCIA PDL_INTC_REG IR S12AD1_S12GBADI PDL_INTC_REG IR GPT5 GICIB PDL_INTC_REG IR_ICU_GROUPO PDL_INTC_REG IR GPT5 GICIC PDL_INTC_REG IR _ICU_GR
272. _INTC_VECTOR_GTCIE7 PDL_INTC_VECTOR_GTCIV7 General PWM timer channel 7 Transmission complete Compare match or input capture A Compare match or input capture B Compare match C or D Compare match E or F Counter limit match PDL_INTC_VECTOR_CMP4 PDL_INTC_VECTOR_CMP5 PDL_INTC_VECTOR_CMP6 12 bit ADC unit 4 Comparator event on input AN100 Comparator event on input AN101 Comparator event on input AN102 PDL_INTC_VECTOR_DOPCF Data operation Condition detection PDL_INTC_VECTOR_IRQO PDL_INTC_VECTOR_IRQ1 PDL_INTC_VECTOR_IRQ2 PDL_INTC_VECTOR_IRQ3 Valid edge or level detected on an PDL_INTC_VECTOR_IRQ4 Interrupt external interrupt pin PDL_INTC_VECTOR_IRQ5 controller PDL_INTC_VECTOR_IRQ6 PDL_INTC_VECTOR_IRQ7 PDL_INTC_VECTOR_GROUPO Group 0 event PDL_INTC_VECTOR_GROUP12 Group 12 event PDL_INTC_VECTOR_ADIO 10 bit ADC Conversion completed PDL_INTC_VECTOR_S12ADI PDL_INTC_VECTOR S12GBADI 12 bit ADC unit 0 Conversion completed Group B conversion completed PDL_INTC_VECTOR_S12ADI1 PDL_INTC_VECTOR S12GBADI 12 bit ADC unit 4 Conversion completed Group B conversion completed ENESAS Page 61 of 418 RX63T Group 4 Library Reference Description 2 3 PDL_INTC_VECTOR_SCIXO R20UT2201EE0211 Sept 12 2014 PDL_INTC_VECTOR_SCIX1 PD
273. _MB1 ENESAS internal peripheral Page 123 of 418 RX63T Group 2 R_BSC_Create Synopsis Prototype Configure the external bus operation bool R_BSC_Create uint32_t data1 uint32_t data2 uint16_t data3 Bus control pin selection Bus address pin selection Recovery cycle insertion 4 Library Reference Description 1 2 R20UT2201EE0211 Sept 12 2014 Rev 2 11 uint8_t data4 void func uint8_t data5 Error control Callback function Interrupt priority level Configure the I O pins cycle insertion error detection and register the callback function data1 Configure the bus control signal Ignored for the 64 pin and 48 pi s Use to separate each selection n device package specify PDL_NO_DATA e Chip select pin selection only required for each external memory area that will be enabled e Please refer to Table 21 39 at the Multifunction Pin Controller MPC section in the RX63T Hardware Manual for details of pin package PDL_BSC_CS0_P26 or PDL_BSC_CS0_PD1 Select the port pin to be used for signal CSO PDL_BSC_CS1_P00 or PDL_BSC_CS1_P25 or PDL_BSC_CS1_PF2 Select the port pin to be used for signal CS1 PDL_BSC_CS2 PD2 or PDL_BSC_CS2 PG6or PDL_BSC_CS2 P05 Select the port pin to be used for signal CS2 PDL_BSC_CS3_P12 or PDL_BSC_CS3_PF4 or PDL_BSC_CS3_PA6 Select the port pin to b
274. _MTU3_INT_SKIP_CREST_DISABLE or PDL_MTU3_INT_SKIP_CREST_1 or PDL_MTU3_INT_SKIP_CREST_2 or PDL_MTU3_INT_SKIP_CREST_3 or PDL_MTU3_INT_SKIP_CREST_4 or PDL_MTU3_INT_SKIP_CREST_5 or PDL_MTU3_INT_SKIP_CREST_6 or PDL_MTU3_INT_SKIP_CREST_7 Disable TCNT underflow TCIV4 or TCIV7 interrupt skipping or set the skip count between 1 and 7 Disable TGRA compare match TGIA3 or TGIA6 interrupt skipping or set the skip count between 1 and 7 e Interrupt skipping control type 2 PDL_MTU3_INT_SKIP_ADC_DISABLE or PDL_MTU3_INT_SKIP_ADC_1 or PDL_MTU3_INT_SKIP_ADC_2 or PDL_MTU3_INT_SKIP_ADC_3 or PDL_MTU3_INT_SKIP_ADC_4 or PDL_MTU3_INT_SKIP_ADC_5 or PDL_MTU3_INT_SKIP_ADC_6 or PDL_MTU3_INT_SKIP_ADC_7 Disable ADC trigger TRGnAN and TRGnBN skipping or set the skip count between 1 and If channels 3 and 4 have been selected n 4 If channels 6 and 7 have been selected n 7 DT_data_value The dead time data register value This will be ignored if the register is not selected data_value The cycle data register value This will be ignored if the register is not selected buffer_value The cycle buffer register value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU3_ControlChannel R_MTU3_Create Rev 2 11 EN ESAS Page 175 of 418 R
275. _NO_DATA PCLKD L_NO_DATA FCLK L_NO_DATA Reserved L_NO_DATA Reserved AE 10 P F P P E P P P P P Configure the main clock settings R_CGC_Set PDL_CGC_CLK_MAIN PDL_NO_DATA Reserved AIN Main QM Q_MAIN 4 ICLK Q Q F F MAIN 4 PCLKA AIN 4 PCLKB PDL_NO_DATA Reserved FREQ _MAIN 4 PCLKD REQ_MAIN 4 FCLK L_NO_DATA Reserved L_NO_DATA Reserved btt I vvv PDI D i Select the main Clock as the clock source and enable the IWDT Clock R_CGC_Control PDL_CGC_CLK_MAIN PDL_CGC_MAIN_ENABL L_CGC_IWDTLOCO_ R20UT2201EE0211 Rev 2 11 RENESAS Page 344 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Use the main clock to check the IWDTLOCO accuracy 10 Register functions that will be called if an error is detected R_CAC_Create PDL_CAC_REFERENCE MAIN PDL_CAC_REFERENCE_ RISING PDL_CAC_REFERENCE_DIV_8192 PDL_CAC_MEASURE_IWDTLOCO PDL_CAC_MEASURE_DIV_1 PDL_CAC_LIMIT_TOLERANCE PDL_NO_DATA Not using CACREF pin PDL_NO_DATA Not using CACREF pin 10 10 tolerance 10 10 tolerance CAC_frequency_error PDL_NO_FUNC CAC_overflow 10 i while 1 void CAC_frequency_error void Handle the fr
276. _PIN_SCI2_SMISO2_P03 or PDL_SCI_PIN_SCI2_SMISO2_PG1 or SMISO2 PDL_SCI_PIN_SCI2_SMISO2_PA2 PDL_SCI_PIN_SCI2_SSCL2_P03 or PDL_SCI_PIN_SCI2_SSCL2_PG1 or SSCL2 PDL_SCI_PIN_SCI2_SSCL2_PA2 PDL_SCI_PIN_SCI2_TXD2_P02 or PDL_SCI_PIN_SCI2_TXD2_PGO or TXD2 PDL_SCI_PIN_SCI2 TXD2 PA1 PDL_SCI_PIN_SCI2_SMOSI2_P02 or PDL_SCI_PIN_SCI2_SMOSI2_PGO or Scl2 SMOSI2 PDL_SCI_PIN_SCI2_SMOSI2_PA1 PDL_SCI_PIN_SCI2_SSDA2_P02 or PDL_SCI_PIN_SCI2_SSDA2_PGO or SSDA2 PDL_SCI_PIN_SCI2_SSDA2 PA1 PDL_SCI_PIN_SCI2_SCK2_P14 or PDL_SCI_PIN_SCI2_SCK2_PG2 or SCK2 PDL_SCI_PIN_SCI2_SCK2_PAO PDL_SCI_PIN_SCI2_CTS2_P13 or CTS PDL_SCI_PIN_SCI2_CTS2_P93 PDL_SCI_PIN_SCI2_RTS2_P13 or RTS2 PDL_SCI_PIN_SCI2_RTS2_P93 or PDL_SCI_PIN_SCI2_SS2_P13 or sso PDL_SCI_PIN_SCI2_SS2 _P93 Valid when n 3 PDL_SCI_PIN_SCI3_RXD3_P34 or RXD3 PDL_SCI_PIN_SCI3_RXD3_PG4 PDL_SCI_PIN_SCI3_SMISO3_P34 or SMISO3 PDL_SCI_PIN_SCI3_SMISO3_PG4 PDL_SCI_PIN_SCI3_SSCL3_P34 or SSCL3 PDL_SCI_PIN_SCI3_SSCL3_PG4 PDL_SCI_PIN_SCI3_TXD3_P35 or TXD3 PDL_SCI_PIN_SCI3_TXD3_PG3 SCI3 PDL_SCI_PIN_SCI3_SMOSI3_ P35 or SMOSI3 PDL_SCI_PIN_SCI3_SMOSI3_PG3 PDL_SCI_PIN_SCI3_SSDA3_P35 or SSDA3 PDL_SCI_PIN_SCI3_SSDA3_PG3 PDL_SCI_PIN_SCI3_SCK3_PG5 SCK3 PDL_SCI_PIN_SCI3_CTS3_PA6 CTS3 PDL_SCI_PIN_SCI3_RTS3_PA6 RTS3 PDL_SCI_PIN_SCI3_SS3_PA6 SS3 EN ESAS Page 236 of 418 RX63T Group Description 4 4 4 Library Reference e Valid when n 12 Return value Category
277. _REFH_AVCCO_6 8 or PDL_ADC 12 CMP_REFH_AVCCO 7 8 Disable the internal REFH for comparator or set it as AVCCO x 1 8 2 8 3 8 4 8 5 8 6 8 or 7 8 data8 The data to be used for the sampling state register value calculations for self diagnosis If PDL_ADC_12_ADSSTR_SPECIFY is selected for parameter data2 the value should not be less than 13 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t data9 The data to be used for the sample and hold circuit control register value calculations If PDL_ADC_12_ADSHCR_SPECIFY is selected for data2 the value should not be less than 4 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSHCR uint8_t func1 The function to be called when the ADC conversion scan cycle is complete in single scan mode and continuous scan mode or when the ADC conversion scan cycle is complete for Group A in group scan mode Specify PDL_NO_FUNC if no callback function is required data10 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called when the ADC conversion scan cycle is complete for Group B in group scan mode Specify PDL_NO_FUNC if no callback function is required data
278. _REFRESH Y Rev 2 11 EN ESAS Page 232 of 418 Sept 12 2014 RX63T Group 4 Library Reference 3 R_IWDT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Read the watchdog timer status and counter bool R_IWDT_Read uinti6_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 Refresh Error Underflow 0 No refresh error 0 No underflow 1 Refresh error 1 Underflow b13 b0 Down Counter Value True Independent Watchdog Timer None If the Underflow flag is set to 1 it shall be automatically cleared to O by this function Ifthe Refresh flag is set to 1 it shall be automatically cleared to 0 by this function RPDL definitions include r_pdl_iwdt h RPDL device specific definitions tinclude r_pdl_definitions h uint16_t Status void func void Read the timer status R_IWDT_Read amp Status Y ENESAS Page 233 of 418 RX63T Group 4 2 19 1 R_SCI_Set Synopsis Prototype Description 1 4 R20UT2201EE0211 Sept 12 2014 Rev 2 11 4 Library Reference Serial Communication Interface Configu
279. _SCI_PIN_SCH SMOSI1_PD3 or PDL_SCI_PIN_SCI1_SMOSI1_ P94 or PDL_SCI_PIN_SCI1_SMOSI1_PF3 or PDL_SCI_PIN_SCI1_SMOSI1_ P95 or PDL_SCI_PIN SCI1_SMOSI1_P26 PDL_SCI_PIN_SCI1 SSDA1_PD3 or PDL_SCI_PIN_SCI1 SSDA1_P94 or PDL_SCI_PIN_SCI1 SSDA1_PF3 or PDL_SCI_PIN_SCI1 SSDA1_P95 or PDL_SCI_PIN_SCI1 SSDA1_P26 PDL_SCI_PIN_SCI1 SCK1_PD4 or PDL_SCI_PIN_SCI1 SCK1_ P92 or PDL_SCI_PIN_SCI1 SCK1_PG6 or PDL_SCI_PIN_SCI1 SCK1_P25 PDL_SCI_PIN_SCI1 CTS1_P70 or PDL_SCI_PIN_SCI1 CTS1_P91 or PDL_SCI_PIN_SCI1 CTS1_P94 PDL_SCI_PIN_SCI1 RTS1_P70 or PDL_SCI_PIN_SCI1 RTS1_P91 or PDL_SCI_PIN_SCI1 RTS1_P94 PDL_SCI_PIN_SCI1 SS1_P70 or PDL_SCI_PIN_SCI1 SS1_P91 or PDL_SCI_PIN_SCI1 SS1_P94 Rev 2 11 ENESAS SCI RXD1 SMISO1 SSCL1 TXD1 SMOSI1 SSDA1 SCK1 CTS1 RTS1 SS1 Page 235 of 418 RX63T Group Description 3 4 Valid when n 2 4 Library Reference R20UT2201EE0211 Sept 12 2014 PDL_SCI_PIN_SCI2_RXD2_P03 or Rev 2 11 PDL_SCI_PIN_SCI2_RXD2_PG1 or RXD2 PDL_SCI_PIN_SCI2_RXD2_PA2 PDL_SCI
280. _parameters TGRC_TGRU_value 50 ch4_parameters TGRD_TGRV_value 100 ch4_parameters TGRE_TGRW_value 0 ch4_parameters TGRF_value 0 R_MTU3_Create 4 amp ch4_parameters 3 ENESAS Page 165 of 418 RX63T Group 3 R_MTU3_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Disable a Multi function Timer Pulse Unit bool R_MTU3_Destroy void No parameter is required Shut down a timer pulse unit True Multi function Timer Pulse Unit None The unit is put into the stop state to reduce power consumption RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown all MTU channels R_MTU3_Destroy Y Rev 2 11 ENESAS 4 Library Reference Page 166 of 418 RX63T Group 4 Library Reference 4 R_MTU3_ControlChannel Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Control an MTU channel bool R_MTU3_ControlChannel uint8_t data1 Channel selection R_MTU3_ControlChannel_structure pir A pointer to the structure R_MTU3_ControlChannel_structure members uint8_t control_setting Control settings uint16_t register_selection Register selection uint16_t TCNT_T
281. _t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint8_t data6 Current block size count pointer Return status flags and current channel registers data1 The start address of the transfer data area If all parameters data3 data4 data5 and data6 are not required specify PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b15 b14 b8 b7 bO 0 The trigger vector valid only when bit b15 1 0 Idle 1 A transfer is in progress data3 Where the current source address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data4 Where the current destination address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data5 Where the current transfer count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data6 Where the current block size count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create The start address of the transfer data area is the same as that declared in R_DTC_Create Rev 2 11 EN ESAS Page 152 of 418 RX63T Group
282. a TGRA compare match Disable or link interrupt PDL_MTU3_ADC_TRIG_B_CREST_INT_SKIP_DISABLE or skipping to ADC trigger PDL_MTU3_ADC_TRIG_B_CREST_INT_SKIP_ENABLE TRGnBN on a TGRA compare match Control ADC triggers Valid for n 4 and 7 in complementary PWM mode unless stated otherwise PDL_MTU3_ADC_TRIG_A_DOWN_DISABLE or PDL_MTU3_ADC_TRIG_A_DOWN_ENABLE Disable or enable ADC trigger TRGnAN requests during down count operation Disable or enable ADC trigger TRGnBN requests during down count operation Disable or enable ADC trigger TRGnAN requests during up count operation This option can be selected in other modes Disable or enable ADC trigger TRGnBN requests during up count PDL_MTU3_ADC_TRIG_B_DOWN_DISABLE or PDL_MTU3_ADC_TRIG_B_DOWN_ENABLE PDL_MTU3_ADC_TRIG_A_UP_DISABLE or PDL_MTU3_ADC_TRIG_A_UP_ENABLE PDL_MTU3_ADC_TRIG_B_UP_DISABLE or PDL_MTU3_ADC_TRIG_B_UP_ENABLE operation R20UT2201EE0211 Rev 2 11 EN ESAS Page 159 of 418 Sept 12 2014 RX63T Group Description 5 9 R20UT2201EE0211 Sept 12 2014 buffer_operation Configure the buffer operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Rev 2 11 4 Library Reference Double buffer control Valid for n 3 and 6 in complementary PWM mode 3
283. able monitor 2 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 2 change detection flag True Voltage detection circuit R_LVD_Create Other operation changes require the shutdown of both voltage monitors If such changes are required call R_LVD_Create with the new settings RPDL definitions include r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void func void Disable monitor 1 clear the monitor 2 flag R_LVD_Control PDL_LVD_DISABLE PDL_LVD_CLEAR_ DETECTION y Rev 2 11 EN ESAS Page 104 of 418 RX63T Group 4 Library Reference 3 R_LVD GetStatus Synopsis Prototype Description Check the status of the voltage detection module bool R_LVD_GetStatus uint8_t data Status flags pointer Return the status flags data se ema 1 and Monitor 2 status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 b1 bO Monitor 2 Monitor 1 Status Change Status Change 0 0 VCC lt Vdet2 0 0 VCC lt Vdet1 1 VCC gt Vdet2 0 None 1 VCC 2 Vdet1 0 None or the monitor is 1 Detected or the monitor is 1 Detected disabled disabled Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 True Voltage
284. age 217 of 418 RX63T Group 4 Library Reference 4 2 16 Compare Match Timer 1 R_CMT_Create Synopsis Prototype Description Return value Configure a CMT channel bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period frequency or register data void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Clock calculation The parameter data3 will specify the timer period PDL_CMT_PERIOD or The counter clock source and compare match value will be calculated by this function The parameter data3 will specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function Select the internal clock signal PCLKB 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 e Counter start control PDL_CMT_START or PDL_CMT_STOP Enable or disable the starting of the timer count operation e DMAC DTC trigger c
285. ages only RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Write new data to DAC channel 1 R_DAC_10_Write PDL_DAC_10_CHANNEL_1 0 100 Rev 2 11 EN ESAS Page 326 of 418 RX63T Group 4 Library Reference 4 2 26 Data Operation Circuit 1 R_DOC_Create Synopsis Configure the Data Operation Circuit Prototype bool R_DOC_Create uint8_tdata1 Configuration uint16_tdata2 Output value void func Callback function uint8_t data3 Interrupt priority level Description Enable the DOC module and set the operating conditions data1 Operation Mode PDL_DOC_COMPARISON_MATCH or PDL_DOC_COMPARISON_MISMATCH or PDL_DOC_MODE_ADD or PDL DOC MODE SUBTRACT Specify the mode of operation data2 This meaning of this parameter depends upon the Operation Mode Operation Mode Description Comparison The comparison value Addition The initial output value before any additions are made Subtraction The initial output value before any subtractions are made func The function to be called when a DOC interrupt is generated Specify PDL_NO_FUNC if no callback function is required data3 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for func
286. ages with 112 pins or less True if the parameter is valid otherwise false 12C R_IIC_Create The l C module is put into the power down state e Channel 1 is supported on 120 pin 144 pin packages only RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown IIC channel 0 R_IIC_Destroy 0 R20UT2201EE0211 Rev 2 11 ENESAS Sept 12 2014 4 Library Reference Page 267 of 418 RX63T Group 4 Library Reference 3 R_IIC_MasterSend Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Write data to a slave device bool R_IIC_MasterSend uint8_t data1 Channel selection uint16_tdata2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Data count void func Callback function uint8_t data6 Interrupt priority level Transmit data on the specified channel data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated S
287. ain to continue monitoring the bus Channel 1 is supported on 120 pin 144 pin packages only RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Monitor channel 0 using polling R_IIC_SlaveMonitor 0 PDL_NO_DATA data_array 5 PDL_NO_FUNC 0 R20UT2201EE0211 Rev 2 11 LEN ESAS Page 274 of 418 Sept 12 2014 RX63T Group 4 Library Reference 7 R_IIC _SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uint16_tdata3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable otherwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will complete when a stop condition is detected Category 12C Reference R_IIC_SlaveMonitor Remarks e Use this function after using R_IIC_SlaveMonitor and detecting that a slave transmission is required
288. al slave memory device on channel 0 It will respond to 7 bit address 0001001b The sample is interrupt driven after the initial setup Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h Define the size of the virtual memory define STORAGE_SIZE 0x100 define RX_BUFFER_SIZE STORAGE_SIZE 1 de de ine SLAVE_CHANNEL 0 ine SLAVE_ADDRESS 0xA0 static void slave_callback void static void StoreData uint16_t count Current memory address volatile uint8_t data_storage_index 0 volatile uint8_t data_storage STORAGE_SIZE volatile uint8_t Rx_Buffer RX_BUFFER_SIZE void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create SLAVE_CHANNEL PDL_IIC_MODE_TIC PDL_IIC_INT_PCLK_DIV_8 PDL_IIC_SLAVE_0_ENABLE_7 SLAVE_ADDRESS P P DL_NO_DATA DL_NO_DATA 100E3 300 lt lt 16 200 Start monitor the channel R_IIC_SlaveMonitor SLAVE_CHANNEL PDL_NO_DATA Rx_Buffer RX_BUFFER_SIZE slave_callback 7
289. all module clock stop mode using a reset from the independent watchdog timer to release the chip from all module clock stop mode is impossible because the independent watchdog timer is stopped The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripherals that were active when that mode was entered will be re activated When the flash memory is in program or erase mode do not call this function if it will result in the power mode changing This function will return false is this situation Rev 2 11 EN ESAS Page 116 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Enter deep software standby mode R_LPC_Control PDL_LPC_MODE_D x EP_SOFTWARE_STANDBY y Clear the 1 0 port state retention R_LPC_Control PDL_LPC_IO_RELEASE R20UT2201EE0211 Rev 2 11 RENESAS Page 117 of 418 Sept 12 2014 RX63T Group 4 Library Reference 3 R_LPC_WriteBackup Synopsis Write to the Backup registers Prototype bool R_LPC_WriteBackup uint8_t data1 Data pointer uint8_t data2 Data count
290. ample RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set bits 6 and 4 in IERO8 to 1 R_INTC_Modify PDL_INTC_REG_IERO8 PDL_INTC_OR 0x50 R20UT2201EE0211 Rev 2 11 RENESAS Page 75 of 418 Sept 12 2014 RX63T Group 4 Library Reference 11 R_INTC_CreateGroup Synopsis Configure a group of peripheral interrupt requests Prototype bool R_INTC_CreateGroup uint8_t data1 Group selection void func Callback function uint8_t data2 Interrupt priority level Description Set up the grouped interrupt request callback function data1 The interrupt request group n to be configured For 64 and 48 pin packages n must be 12 for other pin packages n can be 0 or 12 func The function to be called when a valid condition is detected Sa m priority level Select between 1 lowest priority and 15 highest priority Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Reference R_INTC_ControlGroup Remarks Do not use this function if RPDL functions will be used to configure the applicable peripheral Use R_INTC_ControlGroup to enable the required peripheral interrupt requests Please see the notes on callback function use in 86 Program example RPDL definitions
291. an external bus area 4 R_BSC_Destroy Stop the Bus Controller 5 R_BSC_Control Modify the Bus Controller operation 6 R_BSC_GetStatus Read the Bus Controller status registers 1 R_DMAC _ Create Configure the DMA controller DMA Controller 2 R_DMAC_Destroy Disable a DMA channel 3 R_DMAC_Control Control the DMA controller 4 R_DMAC_GetStatus Check the status of the DMA channel 1 R_DTC_Set Set the Data Transfer Controller options Data Transfer 2 R_DTC_Create Configure the DTC for a transfer Controller 3 R_DTC_Destroy Shutdown the Data Transfer Controller 4 R_DTC_Control Control the Data Transfer Controller 5 R_DTC_GetStatus Check the status of the Data Transfer Controller 1 R_MTU3_ Set Configure the Multi function Timer Pulse Units 2 R_MTU3_Create Configure a MTU channel Multi function 3 R_MTU3_Destroy Disable a Multi function Timer Pulse Unit Timer pulse unit 4 R_MTU3_ControlChannel Control an MTU channel l 5 R_MTU3_ControlUnit Control a Multi function Timer Pulse Unit 6 R_MTU3_ReadChannel Read from MTU channel registers 7 R_MTU3_ReadUnit Read from MTU registers 1 R_POE Set Configure the Port Output Enable module Port Output 2 R_POE Create Configure the Port Output Enable event handling Enable 3 R_POE Control Control the Port Output Enable module 4 R_POE GetStatus Check the Port Output Enable module status 1 R_GPT_Set Select the I O pins for the GPT unit 2 R_GPT_CreateUnit Configure the GPT unit 3 R_GPT_CreateChan
292. and or reception of data across them 20 2C Bus Interface These driver functions are used for controlling the l C bus channels 21 Serial Peripheral Interface These driver functions are used for controlling the SPI channels 22 CRC calculator These driver functions are used for controlling the calculator 23 12 bit Analog to Digital Converter These driver functions are used for configuring the 12 bit ADC units controlling the units and reading the conversion results 24 10 bit Analog to Digital Converter These driver functions are used for configuring the 10 bit ADC units controlling the units and reading the conversion results 25 10 bit Digital to Analog converter These driver functions are used for configuring the DAC module and setting the output voltages 26 Data Operation Circuit These driver functions are used for configuring the data operation circuit R20UT2201EE0211 Rev 2 11 RENESAS Page 18 of 418 Sept 12 2014 RX63T Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions support the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system and peripheral operation 2 Controlling the clock generator operation 3 Reading the Clock generator status flags Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other per
293. andlers cccccecseeceeceeceeeeceeeeeaaeeseeeeceaeeesaaeeseaaeseeeeessaeeesaeeeeneeeeaees 65 6 R_INTC_ConntrolEXxtinterrupt cecccceceeeceeeeeeneeeeeeeceeeeeceaeeeeaaeseeneecaeeesaaeeseaaeseaeeeseaeeesaeeneneeenaees 66 7 R_INTC_GetExtinterruptStatuS 20 0 ceccce cece eeeeeeeeeeee eee eeceaeeeeeeeseeeeeceaeeesaaeseeeeeseaeeeseaesseaeeseeeeesaees 68 8 RUNTE Ri ds 73 o E e NEE EA E T e EE e oie 74 0 RUNTE MO e a 75 11 R_LINTO Create Group iii da 76 12 RUINTE ControlGroUp ci ada 77 13 R_INTC_GetStatuSGrQOUP ccconccnnocinnncccconccononcnononcnoncc cnn nn narran cnn nanncins 79 4 2 3 VUMO Pd A A AA Aena 80 1 RIOSPORT Stiam AA Ii ea eee 81 2 RiJOx PORT ReadControl it AA AA A da 82 3 R_IO_PORT_ModifyContrOl riideid ataiadi anini aieiaa idade ia Taa ania 84 4 RilOsPORT Read icicieaie nae ahv ain atau aie eee a 86 5 RUO PORT Write terinin aa Aia 87 6 R PORT Com Pare cweieiicinih atid aa AAA 88 DD RolOsPORT Modify acia adn ri ad e a aaa 89 8 SRO PORT Walt iii a e Ada aa ar a a a a a eda tele 90 9 sRalO PORT NotAVallable i a ii ia di ee ae 91 4 2 4 Multifunction Pin Controller ecccceesceceeeeceeeeeeneeeeeeee eee eeseaeeeeaeeeeeeeceaeeeeaaesdeeeeseeeetaeeeeeeeeeeees 92 1 REMPE Reads tanih il thas haul ath tite tied eta ais eta Wily tien ae 93 2u SRUMPCLWiiles tacts il a 94 3 RAMPOS MOQINA merrte aaea ia Ai A 95 4 2 5 IMGUOpPeralON tc eevee Anca ay yee a nls Wile devi
294. at channel n 1 up count or down count Valid only for n 0 PDL_MTU3_A_IC_CM_IC Input capture at channel n 1 TGRA compare match or input capture Valid only for n 1 Input capture output compare control for register TGRB PDL_MTU3_B_OC_DISABLED or PDL_MTU3_B_OC_ LOW or PDL_MTU3_B_OC_LOW_CM_HIGH or PDL_MTU3_B_OC_LOW_CM_INV or PDL_MTU3_B_OC_HIGH_CM_LOW or PDL_MTU3_B_OC_HIGH or PDL_MTU3_B_OC_HIGH_CM_INV or PDL_MTU3_B_IC_RISING_EDGE or PDL_MTU3_B_IC_FALLING_EDGE or PDL_MTU3_B_IC_BOTH_EDGES or MTIOCnB output disabled MTIOCnB output low MTIOCnB initial output low goes high at compare match MTIOCnB initial output low toggles at compare match MTIOCnB initial output high goes low at compare match MTIOCnB output high MTIOCnB initial output high toggles at compare match Input capture at MTIOCnB rising edge Input capture at MTIOCnB falling edge Input capture at MTIOCnB both edges PDL_MTU3_B_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU3_B_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 e Cascade input capture control Valid in cascade mode for n 1 Channel n forms the higher 16 bits and channel n 1 forms the lower 16 bits PDL_MTU3_CASCADE_AL_IC_EXC Hor PDL MTU3 CASCADE BL IC EXC Hor PDL_MTU3 CASCADE BL_IC_INC_H PDL_MTU3 C
295. ata12 A pointer to where the Cycle setting double buffer register value shall be stored data13 A pointer to where the ADC start request A register value shall be stored data14 A pointer to where the ADC start request A buffer register value shall be stored data15 A pointer to where the ADC start request A double buffer register value shall be stored data16 A pointer to where the ADC start request B register value shall be stored data17 A pointer to where the ADC start request B buffer register value shall be stored data18 A pointer to where the ADC start request B double buffer register value shall be stored data19 A pointer to where the Dead time up counting register value shall be stored data20 A pointer to where the Dead time up counting buffer register value shall be stored data21 A pointer to where the Dead time down counting register value shall be stored data22 A pointer to where the Dead time down counting buffer register value shall be stored True General PWM Timer unit None e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function Rev 2 11 EN ESAS Page 209 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h uintl6_t Flags uint16_t General_A uint16_t General_D vo
296. ata_store 100 Send a string on channel 1 R_SCI_Send 1 PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC i Send 50 bytes of binary data on channel 1 R_SCI_Send 1 PDL_NO_DATA data_store 50 PDL_NO_FUNC Send the ID byte 0x0A shifted into the upper byte R_SCI_Send 1 PDL_SCI_MP_ID_CYCLE 0x0A00 PDL_NO_PTR 0 PDL_NO_FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 246 of 418 Sept 12 2014 RX63T Group 4 Library Reference 5 R_SCI_Receive Synopsis Prototype Description R20UT2201EE0211 Sept 12 2014 Receive data on a SCI channel bool R_SCI_Receive uint8_t data1 Channel selection uint16_t data2 Channel configuration and Station ID of receiving device uint8_t data3 Data start address uint16_t data4 Receive threshold void func1 Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE received e Continu
297. ate register value calculations If PDL_ADC_12_CH_ADSSTR_SPECIFY is selected for data3 the value should not be less than 13 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t func The function to be called when Comparator detects an event Specify PDL_NO_FUNC if no callback function is required data6 The interrupt priority level for Comparator Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 Return value True if a valid unit is selected otherwise false Category 12 bit ADC Reference R_ADC_12 CreateUnit R_CGC_Set Remarks e If analog channels are used as the input sources call this function after calling R_ADC_12 CreateUnit e Function R_CGC_Set must be called with the current clock source selected before using this function e Make sure no more than 1 channel is configured with the parameter of PDL_ADC_12 CH_DOUBLE_TRIGGER_ENABLE Group A and group B cannot use the same channels Channels with PDL_ADC_12 CH_SAMPLE_AND_HOLD_ENABLE and with programmable gain amplifiers are not selectable for group B e Make sure sampling time calculated or specified for channel 0 and self diagnosis are the same R20UT2201EE0211 Rev 2 11 LEN ESAS Page 305 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions
298. ates on an I O port bool R_IO_PORT_Modify uint16_tdata1 Output port or port pin selection uint16_tdata2 Logical operation uint8_t data3 Modification value Read the output state of an I O port or I O port pin modify the result and write it back to the port data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 e The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or PDL_IO_PORT_XOR Select between AND 8 OR or Exclusive OR data3 The value to be used for the modification Between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port None e f an invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Invert port pin P22 R_IO_PORT_Modi fy PDL_IO_PORT_2 2 PDL_IO_PORT_XOR 1 di And the value port 4 with 0x55 R_IO_PORT_Modi fy PDL_IO_PORT_4 PDL_IO PORT AND 0x55 i ENESAS Page 89 of 418 RX63T Group 4 Library Reference 8 R_IO_PORT_Wait Synopsis Prototype Description Return value Category References Remarks
299. ave device from the current memory address A A A A Aa Figure 5 34 The bus activity showing 4 bytes being transmitted by the EEPROM Read data from the EEPROM using polling if R_IIC_MasterReceive 0 PDL_NO_DATA EEPROM_ADDRESS data_storage 4 P 0 DL_NO_FUNC false Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR amp RxChars Review the flags and transmit count to decide on the next action Figure 5 35 An example of reading data from the EEPROM R20UT2201EE0211 Rev 2 11 RENESAS Page 391 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 3 Repeated Start Continuing from above The memory address pointer of an EEPROM will be modified and then a Repeat Start condition used to change to read the byte at that memory location in the EEPROM Slave address Memory address Slave address AA Figure 5 36 The bus activity showing the Repeated Start condition when switching to the Read process Send 1 byte to the EEPROM to update the sub address bits and do not stop R_IIC_MasterSend 0 r PDL_IIC_STOP_DISABLE EEPROM ADDRESS eeprom_data_array_l 1 ri P 0 DL_NO_FUNC Read data from the EEPROM A repeated start will occur R_IIC_MasterReceive 0 DL_NO_DATA EEPROM_ADDRESS ata_storage DL_NO_FUNC Figure 5 37 Set the EEP
300. bps 86 7 kbps 83 6 kbps 217 kbps 57 8 kbps PCLKB 128 6 06 kbps to 5 82 kbps to 1 52 kbps to 1 5 kbps to 3 89 kbps to 975 bps to i 175 kbps 168 5 kbps 45 9 kbps 44 2 kbps 116 kbps 30 0 kbps R20UT2201EE0211 Rev 2 11 LEN ESAS Page 265 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions tinclude r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h void func void Select I C mode at 100kHz 100ns rise and fall times R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 100 lt lt 16 100 y Select I C mode with two slave addresses R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_SLAVE_O_ENABLE_7 PDL_IIC_SLAVE_1_ENABLE_7 0x0020 0x0056 PDL_NO_DATA 100E3 300 lt lt 16 200 Y R20UT2201EE0211 Rev 2 11 AS Page 266 of 418 Sept 12 2014 RENES RX63T Group 2 R_IIC_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable an I2C channel bool R_IIC_Destroy uint8 tdata Channel selection Shut down the selected 12C channel data Select channel IICn where n 0 orn 1 Channel 1 is not available for device pack
301. brary Reference Remarks Program example If a callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 If using polling mode When the function returns use R_IIC_GetStatus to identify the activity that has occurred Call this function for each transfer required even if the master has ended the previous transfer with a repeat start If the DMAC or DTC is not being used to perform a slave transmission then if a slave transmission is required function R_IIC_SlaveSend must be called to send the data Note If R_IIC_GetStatus reports that the slave is in transmit mode then a slave transmission is required If the master sends more data than is expected and the DMAC DTC trigger is disabled this function will issue a NACK to the master If using the DMAC or DTC for transferring data then ensure they are configured correctly before calling this function False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create Normally bus activity for other slaves is ignored with no CPU involvement However in the specific case where a callback function is specified and the DTC or DMAC is specified for data transmission then any stop condition on the bus will cause the callback function to be called before any data has been transfered This function should then be called ag
302. ce Remarks R20UT2201EE0211 Sept 12 2014 PDL_DMAC_TRIGGER_LOCOI4 or LOCO count function event on GPT channel 4 PDL_DMAC_TRIGGER_SCIO RX or PDL_DMAC_TRIGGER_SCI1_RX or PDL_DMAC_TRIGGER_SCI2_RX or PDL_DMAC_TRIGGER_SCI3 RX or PDL_DMAC_TRIGGER_SCI12_RX or PDL_DMAC_TRIGGER_SCIO_TX or PDL_DMAC_TRIGGER_SCI1_TX or PDL_DMAC_TRIGGER_SCI2_TX or PDL_DMAC_TRIGGER_SCI3_TX or PDL_DMAC_TRIGGER_SCI12_TX Receive buffer full on SCI channel n n 0 1 2 3 12 Transmit buffer empty on SCI channel n n 0 1 2 3 12 data4 The source start address data5 The destination start address data6 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat and block mode valid between 0 and 1023 0 1024 transfers data7 The repeat or block size for each transfer For repeat and block mode valid between 0 and 1023 0 1024 units Ignored in normal mode data8 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data9 o The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat function is not required for the source address data10 The destination address extended repeat value The value can be any power of 2 from 2 to 2 Specify P
303. channel Valid for n 0 3 4 6 and 7 Transfer the data from TGRF to TGRE when a compare match E occurs or when TCNT is cleared in either channel Valid for n 0 Transfer on TCNT clear is available only in PWM mode 1 or 2 ENESAS Page 160 of 418 RX63T Group Description 6 9 TGR_A_B_ operation R20UT2201EE0211 Sept 12 2014 4 Library Reference Configure the operation for general registers TGRA and TGRB Valid for n 5 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Input capture output compare control for register TGRA PDL_MTU3_A OC DISABLED or PDL_MTU3_A_OC_LOW or PDL_MTU3_A_OC_LOW_CM_HIGH or PDL_MTU3_A_OC_LOW_CM_INV or PDL_MTU3_A_OC_HIGH_CM_LOW or PDL_MTU3_A_OC_HIGH or PDL_MTU3_A_OC_HIGH_CM_INV or MTIOCnA output disabled MTIOCnA output low MTIOCnA initial output low goes high at compare match MTIOCnA initial output low toggles at compare match MTIOCnA initial output high goes low at compare match MTIOCnA output high MTIOCnA initial output high toggles at compare match PDL_MTU3_A_IC_RISING_EDGE or PDL_MTU3_A_IC_FALLING_EDGE or PDL_MTU3_A_IC_BOTH_EDGES or Input capture at MTIOCnA rising edge Input capture at MTIOCnA falling edge Input capture at MTIOCnA both edges PDL_MTU3_A_IC_COUNT or Input capture
304. ck_osciLLarorR 20 MHz between 4 and 16 MHz if a resonator is used e For packages with 100 pins or more fMAIN_CLOCK_OSCILLATOR S 14 MHz between 8 and 12 5 MHz if a resonator is used fet 104 to 200 MHz ficik lt 100 MHz froika lt 100 MHz fro ke lt 50 MHz frcikc lt 100 MHz fre ko lt 50 MHz frock lt 50 MHz fec k lt 50 MHz fecik_rin lt 25 MHz fecik lt ficLk fuss_cLock 48 MHz The frequency of the PLL is achievable main clock 1 2 or 4 x 8 10 12 16 20 24 25 or 50 e The frequencies of the internal clocks ICLK PCLKA PCLKB PCLKC PCLKD FCLK and BCLK are achievable selected clock source 1 2 4 8 16 32 or 64 e The frequency of the USB clock UCLK is achievable selected clock source 2 3 or 4 Clock generation circuit R_CGC_Control R_MCU_GetStatus R_LPC_Create Call this function once for each clock source that will be used If the current clock source is selected in parameter data1 the frequencies of the internal clocks will be changed by this function After a power on reset the MCU selects the LOCO as the clock source This function must be called before configuring clock dependent modules This function will enable the selected clock but will not select it as the current clock source After the required settling time use R_CGC_Control to select the desired clock source The ratios of ficik frcika fecike fecikc fectkp and freck have some restrictions
305. compare match or GPT6 GTADTRB compare match GPT7 GTADTRA compare match or GPT7 GTADTRB compare match PDL_ADC_10_TRIGGER_GPT4_CM_AB or PDL_ADC_10_TRIGGER_GPT5_CM_AB or PDL_ADC_10_TRIGGER_GPT6_CM_AB or PDL_ADC_10_TRIGGER_GPT7_CM_AB data4 The data to be used for the sampling state register value calculations for self diagnosis If PDL_ADC_10_ADSSTR_SPECIFY_UNIT is selected for parameter data2 the value should not be less than 7 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTRO uint8_t func The function to be called when the ADC conversion scan cycle is complete in single secan mode and continuous scan mode Specify PDL_NO_FUNC if no callback function is required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 True if all parameters are valid and exclusive otherwise false 10 bit ADC R_CGC_Set Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 86 This function brings the converter unit out of the power down state Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Pin PG5 does not exist in 100 pin device
306. controller Table 15 3 Interrupt Vector Table for details Name Module Interrupt cause PDL_INTC_VECTOR BUSERR External bus Error illegal access or timeout PDL_INTC_VECTOR FIFERR PDL_INTC_VECTOR_FRDYI Flash memory Error Ready PDL_INTC_VECTOR_SWINT Interrupt control Software interrupt PDL_INTC_VECTOR_CMTO PDL_INTC_VECTOR_CMT1 PDL_INTC_VECTOR_CMT2 PDL_INTC_VECTOR_CMT3 PDL_INTC_VECTOR_DOFIFOO PDL_INTC_VECTOR_D1FIFOO PDL_INTC_VECTOR_USBRO PDL_INTC_VECTOR_USBIO Compare match timer USB channel 0 Compare match DOFIFO transfer request D1FIFO transfer request Event detection Resume PDL_INTC_VECTOR_FERRF Clock frequency Frequency error PDL_INTC_VECTOR_SPII1 PDL_INTC_VECTOR_RXF1 PDL_INTC_VECTOR_TXF1 PDL_INTC_VECTOR_RXM1 PDL_INTC_VECTOR_TXM1 CAN channel 1 PDL_INTC_VECTOR_MENDF accuracy Measurement end PDL_INTC_VECTOR_OVFF measurement Overflow PDL_INTC_VECTOR_SPRIO Receive buffer full PDL_INTC_VECTOR_SPTIO SPI channel 0 Transmit buffer empty PDL_INTC_VECTOR_SPIIO Idle PDL_INTC_VECTOR_SPRI1 Receive buffer full PDL_INTC_VECTOR_SPTI1 SPI channel 1 Transmit buffer empty Idle Receive FIFO Transmit FIFO Reception complete PDL_INTC_VECTOR_GTCIA7 PDL_INTC_VECTOR_GTCIB7 PDL_INTC_VECTOR_GTCIC7 PDL
307. counter_operation PDL_MTU3_CLK_PCLKA_DIV_64 Compare match interrupts create_parameters funcl Callback_Match_TGRA create_parameters interrupt_priority_l 5 create_parameters func5 Callback_Match_TGRE create_parameters interrupt_priority_2 7 Count match values create_parameters TGRA_TCNTV_value 0x1111 create_parameters TGRE_TGRW_value OxEEEE Create Channel 0 R_MTU3_Create 0 amp create_parameters Clear flags Counter_Callback_Match_TGRA 0 Counter_Callback_Match_TGRE 0 Set Control options to start the timer control_parameters control_setting PDL_MTU3_START control_parameters register_selection PDL_NO_DATA R_MTU3_ControlChannel 0 amp control_parameters Wait for match while 0 Counter_Callback_Match_TGRA while 0 Counter_Callback_Match_TGRE Stop the counter control_parameters control_setting PDL_MTU3_STOP control_parameters register_selection PDL_NO_DATA R_MTU3_ControlChannel 0 amp control_parameters R_MTU3_Destroy R20UT2201EE0211 Rev 2 11 AS Page 416 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples while 1 static void Callback_Match_TGRA void uint8_t status uint16_t TGRA_count_value uint16_t TCNT_Counter Read the counter value R_MTU3_ReadChannel 0 amp status amp TCNT_Counter amp TGRA_count_value
308. ction describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows assignable parameters separating each argument with argumenf Return value Describes the returned value of the API function Category Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r_pdl_mpc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void bool result Write OxFF to register MPC1 result R_MPC_Write 1 OxFF i if result false Handle th rror here Keep trying to send a string if the channel is busy do result R_SCI_Send 2 Renesas RX NULL PDL_NO_FUNC whil result false For clarity the return value is not checked in the examples used in this manual The RPDL API is implemented using function macros To avoid the possibility of para
309. d the ICBRL ICBRH register value should be equal or greater than lt the number of noise filter steps 1 gt Rev 2 11 EN ESAS Page 264 of 418 RX63T Group The absolute limits with zero rise and fall times are 4 Library Reference frcike MHz finc 50 48 5 12 32 8 f 4 781 kbps to 750 kbps to 195 kbps to 187 5 kbps to 500 kbps to 125 kbps to did 25 0 Mbps 24 0 Mbps 6 25 Mbps 6 0 Mbps 16 0 Mbps 4 00 Mbps f 29 391 kbps to 375 kbps to 97 7 kbps to 93 75 kbps to 250 kbps to 62 5 kbps to cones 12 5 Mbps 12 0 Mbps 3 13 Mbps 3 0 Mbps 8 00 Mbps 2 00 Mbps f za 195 kbps to 187 5 kbps to 48 8 kbps to 46 875 kbps 125 kbps to 31 3 kbps to eee 6 25 Mbps 6 0 Mbps 1 56 Mbps to 1 5 Mbps 4 00 Mbps 1 00 Mbps f 8 97 7 kbps to 93 75 kbps to 24 4 kbps to 23 4 kbps to 62 5 kbps to 15 6 kbps to cinta 3 13 Mbps 3 0 Mbps 781 kbps 750 kbps 2 00 Mbps 500 kbps f 16 48 8 kbps to 46 875 kbps to 12 2 kbps to 11 71 kbps to 31 3 kbps to 7 81 kbps to dd 1 56 Mbps 1 5 Mbps 391 kbps 375 kbps 1 00 Mbps 250 kbps f 30 24 4 kbps to 23 4 kbps to 6 10 kbps to 5 86 kbps to 15 6 kbps to 3 91 kbps to acess 781 kbps 750 kbps 195 kbps 187 5 kbps 500 kbps 125 kbps f 64 12 2 kbps to 11 71 kbps to 3 05 kbps to 2 93 kbps to 7 81 kbps to 1 95 kbps to decia 391 kbps 375 kbps 97 7 kbps 93 75 kbps 250 kbps 62 5 kbps f 128 6 10 kbps to 5 86 kbps to 1 53 kbps to 1 46 kbps to 3 91
310. d for register TGRD If synchronous mode is required at least two channels must be enabled for synchronous operation A companion function R_MTU3_Create_load_defaults can be used to load the default values into the structure If the channel operation mode will be changed ensure that the timer is stopped use R_MTU3_ControlChannel or R_MTU3_ControlUnit If using Complementary PWM mode with Synchronous Clearing and Waveform Retention enabled then be aware of the cautions specified in the Usage Notes section of the hardware manual RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h void func void Rev 2 11 Allocate a copy of the structure for the selected channel R_MTU3_Create_structure ch4_parameters Load the defaults R_MTU3_Create_load_defaults amp ch4_parameters Set the non default options for channel 4 ch4_parameters channel_mode PDL_MTU3_MODE_NORMAL PDL_MTU3_SYNC_ENABLE ch4_parameters event_trigger_operation PDL_MTU3_TGRA_DTC_TRIGGER_ENABLE ch4_parameters counter_operation PDL_MTU3_CLK_PCLKA_DIV_4 ch4_parameters buffer_operation PDL_MTU3_BUFFER_AC_CM_A ch4_parameters TGR_C_D_operation PDL_MTU3_C_OC_HIGH_CM_LOW ch4_parameters TCNT_TCNTU_value 0 ch4_parameters TGRA_TCNTV_value 199 ch4_parameters TGRB_TCNTW_value 99 ch4
311. d the MCU status 3 R_MCU_OFS Configure the device start up operation 1 R_LVD_ Create Configure the voltage detection circuit eA Circuit 2 R_LVD_Control Control the voltage detection circuit 3 R_LVD_GetStatus Check the status of the voltage detection module Clock 1 R_CAC Create Configure the clock accuracy circuit Frequency 2 R_CAC_Destroy Stop the clock accuracy circuit Accuracy 3 R_CAC_Control Modify the clock accuracy circuit operation Measurement e Circuit 4 R_CAC_GetStatus Read the clock accuracy circuit status 1 R_LPC Create Configure the MCU low power conditions Low Power 2 R_LPC_Control Select a low power consumption mode Consumption 3 R_LPC_WriteBackup Write to the Backup registers 4 R_LPC_ReadBackup Read from the Backup registers 5 R_LPC_GetStatus Read the status flags Register Write 1 R_RWP_Control Control register write protection Protection 2 R_RWP_GetStatus Get the status of the register protection R20UT2201EE0211 Rev 2 11 LEN ESAS Page 46 of 418 Sept 12 2014 RX63T Group 4 Library Reference 1 R_BSC_Set Configure the internal bus operation 2 R_BSC_Create Configure the external bus controller Bus Controller 3 R_BSC_CreateArea Configure
312. d to include this file iodefine h 1 3 4 Header file order The file r_pdl_definitions h must be included after any peripheral specific header file For example Peripheral driver function prototypes and definitions include r_pdl_cgc h include r_pdl_cmt h PDL device specific definitions include r_pdl_definitions h 1 3 5 Recommended initialisation code The RX tool chain has a designated function for MCU initialisation HardwareSetup During the the MCU initialisation phase it is recommended that the following functions are placed in this function Note that the file resetprg c supplied when a new project is created requires editing to remove the comment identifiers for the two lines below extern void HardwareSetup void HardwareSetup Initialisation of pins that are not available For pins that are not available on the selected MCU package type set the control registers to the recommended values using R_IO_PORT_NotAvailable This function can be called even if the largest device has been selected This will allow for the user s code to be ported to another project that does use a smaller MCU package R20UT2201EE0211 Rev 2 11 RENESAS Page 14 of 418 Sept 12 2014 RX63T Group 1 Introduction 1 4 Document structure The drivers are summarised in section 2 and explained in detail in section 4 Section 5 provides usage examples Section 6 provides details which are specific to
313. data1 Channel selection uint32_t data2 Status flags uint16_t data3 Transmitted bytes uint16_t data4 Received bytes Description Read the status registers for the selected 12C channel data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b18 b17 b16 Buffer status 0 Transmit Receive 0 Full 0 Empty 1 Empty 1 Full b15 b14 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle sct spa nack _ Stop Start arbitration lost Timeout 1 Busy condition condition b7 b6 b5 b4 b3 b2 bi bO Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive A Slave 1 Idle de Transmit SMBus host Device ID General call gt 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required data4 The address for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are valid otherwise false Category 12C
314. de Data inversion PDL_SCI_INVERSION_OFF or PDL_SCI_INVERSION_ON Control data inversion transmission and reception Base clock pulse cycle count PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL_SCI_BCP_512 PDL_SCI_BCP_128 or The number of base clock cycles in a 1 bit data PDL_SCI_BCP_186 or transfer period Parity selection PDL_SCI_PARITY_EVEN or Block transfer mode selection PDL_SCI_PARITY_ODD Select even or odd parity bit PDL_SCI_BLOCK_MODE_OFF or PDL SCI BLOCK MODE ON Control Block transfer mode GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL_SCI_GSM_MODE ON Control GSM mode SCKn pin output control Note how the default option changes depending upon the mode In Normal Mode the default is an I O Pin In GSM Mode the default is Fixed Low Normal mode GSM mode PDL_SCI_SCK_OUTPUT_OFF or 1 O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCI_SCK_OUTPUT_ON or Outputs the bit clock PDL_SCI SCK_OUTPUT_HIGH Not applicable Fixed high ENESAS Page 240 of 418 RX63T Group Description 4 4 Return value Category Reference R20UT2201EE0211 Sept 12 2014 4 Library Reference data3 Select the SCI transfer rate See the Remarks section for the maximum rate that the device can su
315. de r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL_CRC_POLY_CRC_8 PDL_CRC_LSB_FIRST Rev 2 11 EN ESAS Page 292 of 418 RX63T Group 4 Library Reference 2 R_CRC_Destroy Synopsis Shut down the CRC calculator Prototype bool R_CRC_Destroy void No parameter is required Description Put the CRC calculator into the Power down state with minimal power consumption Return value True Category CRC Reference R_CRC_Create Remarks None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the CRC R_CRC_Destroy R20UT2201EE0211 Rev 2 11 RENESAS Page 293 of 418 Sept 12 2014 RX63T Group 3 R_CRC_Write Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Write data into the CRC calculation register bool R_CRC_Write uint8_t data The data to be used for the calculation Write the data into the data input register data The data to be written into the register True CRC R_CRC_Create None RPDL definitions include
316. definitions tinclude r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void Callback_LowVoltage void void func void Use Monitor 2 to generate an NMI when VCC drops below 2 95 V R_LVD_Create PDL_NO_DATA PDL_NO_DATA PDL_LVD_INTERRUPT_NMI_DETECT_FALL PDL_LVD_FILTER_DISABLE PDL_NO_DATA Rev 2 11 EN ESAS Page 103 of 418 RX63T Group 4 Library Reference 2 R_LVD Control Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Control the voltage detection circuit bool R_LVD_Conirol uint8_t data1 Monitor 1 control uint8_t data2 Monitor 2 control Control the voltage detection configuration data1 Monitor 1 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 1 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 1 change detection flag data2 Monitor 2 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Dis
317. destination_string_l 1 uint16_t strlen source_string_1 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA DMACO_transfer_end_handler R20UT2201EE0211 Rev 2 11 RENESAS Page 352 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Configure channel 1 R_DMAC_Create 1 PDL_DMAC_BLOCK PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_SIZ1 PDL_DMAC_TRIGGER_SW source_string_2 destination_string_2 1 uint16_t strlen source_string_2 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 y Set IRQO pin R_INTC_SetExtInterrupt PDL_INTC_IRQ2_P10 Enable the SW1 IRQO interrupt R_INTC_CreateExtInterrupt PDL_INTC_IROO PDL_INTC_FALLING PDL_INTC_DMAC_TRIGG PDL_NO_FUNC 0 Enable channel 0 IAC_Control 0 DL_DMAC_ENABL DL_NO_PTR DL_NO_PTR DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT TU TO UU OD PT DD Enable and start channel 1 IAC_Control 1 DL_DMAC_ENABLE PDL_DMAC_ START DL_NO_PTR DL_NO_PTR DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT DL_NO_DAT ere PU Ue Ve O Read the status for channel 0 R_DMAC_GetStatus 0 amp StatusValue amp SourceAddr amp DestAddr amp TransferCount amp SizeCount void DMACO_transfer_end_handler void R20UT2201EE0211 Rev 2 11 AS Page
318. destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products c
319. detection Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for error callback function in R_SCI_Receive or R_SCI_SPI_Transfer This parameter may be zero if the following functions will not be used with a callback function R_SCI_Send R_SCI_Receive R_SCI_SPI_Transfer R_SCI_IIC_Write and R_SCI_IIC_Read True if all parameters are valid exclusive and achievable otherwise false SCl R_CGC_ Set R_SCI_Set R_SCI_Send R_SCI_ Receive Rev 2 11 EN ESAS Page 241 of 418 RX63T Group 4 Library Reference Remarks Function R_CGC_Set must be called with the current clock source selected before using this function Function R_SCI_Set must be called before any use of this function e This function configures each SCI pin that is required for operation It also disables the alternative modes on those pins In Async and Async MP modes the Tx pin is initially set to the Mark state The R_SCI_Control function can subsequently be used to set the Space state SPI Multi Master mode is not supported Hence in SPI Master mode the SS pin can not be enabled e Ifthe option of using a delayed clock phase is selected in synchronous mode then a delay is required following the final receive interrupt before the operation can be completed This delay is implemented as a software loop in the
320. detection circuit R_LVD_Control R_LVD_Create Use R_LVD_ Control to clear the detection flags e Adetection flag is not valid if Monitor only operation was selected in R_LVD_Create RPDL definitions tinclude r_pdl_lvd h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusFlags Read the LVD status R_LVD_GetStatus amp StatusFlags y ENESAS Page 105 of 418 RX63T Group 4 2 7 Clock Frequency Accuracy Measurement Circuit 1 R_CAC Create Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Rev 2 11 Configure the clock accuracy circuit bool R_CAC_Create uint32_t data1 uint8_t data2 double data3 uint16_t data4 uint16_t data5 Signal selection External input timing Upper limit value Lower limit value void funci Callback function void func2 Callback function void func3 Callback function uint8_t data6 Interrupt priority level 4 Library Reference External input configuration Configure the operation of the Clock frequency accuracy measurement circuit data1 Choose the reference and measure clock settings Use to separate each selection e Reference signal selection PDL_CAC_REFERENCE_MAIN or PDL_CAC_REFERENCE_PCLK or PDL_CAC_REFERENCE_IWDTLOCO or PDL_CAC_REFERENCE_CACREF Select the Main clock oscillator Pe
321. device specific definitions include r_pdl_definitions h if defined DEVICE_PACKAGE_64_ PIN amp amp defined D E_PACKAG define CHANNEL_SCI 1 else define CHANNEL_SCI 0 endif void SCIrx void void SCIEr void define NUM_DATA 50 volatile uint8_t data_received volatile uint8_t error_happen volatile uint8_t receive_data NUM_DATA void main void uint8_t i bool id_received Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit for i 0 i lt NUM_DATA i receive_data i 0 Set pin options R_SCI_Set CHANNEL_SCI if defined DEVICE_PACKAGE_64_PIN amp amp defined DEVICE_PACKAG PDL_SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1_TXD1_PD3 else PDL_SCI_PIN_SCIO_RXDO_P24 PDL_SCI_PIN_SCIO_TXDO_P30 endif i Configure the RS232 port specify Async MP mode R_SCI_Create CHANNEL_SCI PDL_SCI_8N1 PDL_SCI_ASYNC_MP 57600 Async MP mode data Reception by CPU ISR data_received fals error_happen false Wait by CPU ISR until receive matching Station ID 0x0A R_SCI_Receive R20UT2201EE0211 Rev 2 11 RENESAS Page 377 of 418 Sept 12 2014 RX63T Group 5 Usage Examples CHANNEL_SCI Ox0A00 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 SCIrx
322. dl_iic h RPDL device specific definitions tinclude r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 1 byte on channel 0 and stop R_IIC_MasterReceiveLast 0 amp data_array 4 Rev 2 11 ENESAS Page 272 of 418 RX63T Group 4 Library Reference 6 R_IIC_SlaveMonitor Synopsis Prototype Description Return value Category Monitor the bus bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_t data2 Channel configuration uint8_t data3 Receive data start address uint16_tdata4 Receive threshold void func Callback function uint8_t data5 Interrupt priority level Monitor the bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected 12C channel data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_RX_DMAC_TRIGGER_ENABLE or DMAC or DTC when a byte is PDL_IIC_RX_DTC_TRIGGER_ENABLE received PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_TX_DMAC_TRIGGER_ENABLE or PDL_IIC_TX_DTC_TRIGGER_ENABLE
323. dl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t Status_flags Read the group 12 status flags R_INTC_GetStatusGroup 1D amp Status_flags Y ENESAS Page 79 of 418 RX63T Group 4 2 3 1 O Port 4 Library Reference I O Port functions may operate on a complete port or on individual port pins The available definitions are listed below 1 O port definitions PDL IO PORT 0 Port PO PDL IO PORT 6 Port P6 PDL IO PORT _ C Port PC PDL _ IO PORT 1 Port P1 PDL IO PORT 7 Port P7 PDL IO PORT _ D Port PD PDL _IO PORT 2 Port P2 PDL _IO_ PORT _8 Port P8 PDL_IO_PORT_E Port PE PDL _IO PORT 3 Port P3 PDL _IO_ PORT 9 Port P9 PDL_IO_PORT_F Port PF PDL _IO_ PORT 4 Port P4 PDL_IO_PORT_A Port PA PDL_IO_PORT_G Port PG PDL IO PORT 5 Port P5 PDL IO PORT _ B Port PB Note Refer to the hardware manual for the ports which are available on the device that you have selected I O port pin definitions PDL_IO PORT_0 0 Portpin PO PDL_IO PORT 6 O Port pin P69 PDL_IO PORT _C_0O Port p
324. e 4 R_GPT_Destroy Synopsis Disable the GPT unit Prototype bool R_GPT_Destroy uint8_t data Unit selection Description Shut down the GPT unit and reduce the power consumption data The unit number n where n 0 for 64 and 48 pin packages n 0 1 for 144 120 112 100 pin packages Return value True Category General PWM Timer unit Reference None Remarks The unit is put into the stop state Program example include r_pdl_gpt h void func void Shutdown all GPT channels R_GPT_Destroy 0 i R20UT2201EE0211 Rev 2 11 ENESAS Page 201 of 418 Sept 12 2014 RX63T Group 5 R_GPT_ControlChannel Synopsis Prototype Control a GPT channel 4 Library Reference bool R_GPT_ControlChannel uint8_t data1 uint32_t data2 uint32_t data3 R_GPT_ControlChannel_structure ptr Channel selection Control options Register selection A pointer to the register structure R_GPT_ControlChannel_structure members uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 uint16_t data10 uint16_t data11 uint16_t data12 uint16_t data13 uint16_t data14 uint16_t data15 uint16_t data16 uint16_t data17 uint16_t data18 uint16_t data19 uint16_t data20 uint16_t data21 uint16_t data22 uint16_t data23 Timer counter register value Gen
325. e If this function is used to enable a clock oscillator wait for the required settling time before selecting the clock source Program example RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void Stop the low speed on chip oscillator R_CGC_Control PDL_NO_DATA PDL_CGC_LOCO_DISABLE PDL_NO_DATA Y Select the PLL R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA Y R20UT2201EE0211 Rev 2 11 RENESAS Page 54 of 418 Sept 12 2014 RX63T Group 4 Library Reference 3 R_CGC_GetStatus Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Read the status of the clock generation circuit bool R_CGC_GetStatus uint16_t data Pointer to the variable where the status value shall be stored Read the clock status register data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 Clock control 0 IWDTLOCO LOCO Main clock PLL 0 Operating 1 Stopped b7 b6 b4 b3 b2 b1 bO Selected clock source Main clock oscillation stop detection 0 roe cd 0 0 Disabled 0 Normal operation 100b PLL 1 Enabled 1 Stop d
326. e SPI channel 0 commands 0 and 1 R_SPI_Commanad 0 0 PDL_SPI_CLOCK_MODE_0 PDL_SPI_ASSERT_SSLO PDL_SPI_LENGTH_8 PDL_SPI_MSB_ FIRST PDL_NO_DATA R_SPI_Command 0 1 PDL_SPI_CLOCK_MODE_1 PDL_SPI_ASSERT_SSL1 PDL_SPI_LENGTH_8 PDL_SPI_LSB_FIRST PDL_NO_DATA R20UT2201EE0211 Rev 2 11 EN ESAS Page 286 of 418 Sept 12 2014 RX63T Group 4 Library Reference 5 R_SPI_Transfer Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Transfer data over an SPI channel bool R_SPI_Transfer uint8_t data1 Channel selection uint8_t data2 DMAC DTC control uint32_t data3 Transmit data start address uint32_t data4 Receive data start address uint16_t data5 Sequence loop count void func1 Callback function uint8_t data6 Interrupt priority level void func2 Callback function uint8_t data7 Interrupt priority level In Master mode transfer the data to and or from the Slave device In Slave mode transfer the data under control of the Master device data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Select the automatic data transfer options The default setting is shown in bold Specify PDL_NO_DATA to use the default DMAC DTC trigger control PDL_SPI_DMAC_DTC_T
327. e channel is complete before calling this function Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_IIC_ReadLastByte or R_SCI_Control function to manually generate a stop The last byte of a master read will automatically be NACK d However if using DMAC or DTC this will not happen If a NACK is required then use the DMAC DTC to read all the data except for the last byte and then use function R_SCI_IIC_ReadLastByte to read the last byte lf a callback function is specified and the interrupt priority level is zero this function will return false RPDL definitions tinclude r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 1 define SLAVE_ADDRESS 0xA0 Buffer for IIC data volatile uint8_t IIC_Buffer 10 void func void Wait while read 10 bytes R_SCI_IIC_Read CHANNEL _SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIC_Buffer PDL_NO_FUNC ztENESAS Page 256 of 418 RX63T Group 4 Library Reference 9 R_SCI_IIC_ReadLastByte Synopsis
328. e data8 Sampling time for self diagnosis double data9 Sampling and hold time void func Callback function for Group A uint8_t data10 Interrupt priority level for Group A void func2 Callback function for Group B uint8_t data11 Description 1 6 Set the ADC mode and operating condition R20UT2201EE0211 Sept 12 2014 data1 Select the ADC unit to be configured Interrupt priority level for Group B For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Scan mode PDL_ADC_12 SCAN SINGLE or PDL_ADC_12_SCAN_CONTINUOUS or PDL_ADC 12 SCAN GROUP Select Single scan Continuous scan or Group scan mode e Trigger source enable Not valid if PDL_ADC_12 SCAN GROUP is selected for data2 PDL_ADC_12_ASYNC_TRIGGER_ENABLE or PDL_ADC_12_SYNC_TRIGGER_ENABLE Enable synchronous or asynchronous trigger source ADC value addition selection PDL_ADC_12_VALUE_ADDITION_0 or PDL_ADC_12_VALUE_ADDITION_1 or PDL_ADC_12_VALUE_ADDITION_2 or PDL_ADC_12 VALUE ADDITION 3 No addition Addition once Addition twice Addition three times Data alignment PDL_ADC_12 DATA_ALIGNMENT_RIGHT or PDL_ADC_12 DATA ALIGNMENT_LEFT The alignment of
329. e directory Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test Sub Directory RPDL Cancel Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test Sub Directory Cancel Click on OK to close the window R20UT2201EE0211 Rev 2 11 AS Sept 12 2014 RENES 1 Introduction Page 5 of 418 RX63T Group 1 Introduction 4 Add the RPDL library file The library file is added to the list used by the linker application Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window select Project directory and enter RPDL RX63T_library as the File path Add library fle U e Base path Project directory i WorkSpace rpdl_lib_test rpdl_lib_test File path APD LARX63T_librard cores To use library with debug information enter RPDL RX63T_library_debug as the File path Add library filesi i gt A Base path Project directory v i WorkSpace rpdl_lib_test rpdl_lib_test File path APD LARAX63T_library_debug Cancel Click on OK to close the window Click on OK
330. e frequency of the peripheral module clock PCLKB frcike MHz Equation 50 48 12 5 12 32 8 8 Periodmin 160ns 167ns 640ns 667ns 250ns 1 0us J pckes Period 2 gt EN 671ms 699ms 2 68s 2 79s 1 05s 4 19s x Freixa fmax Lrcrxo 6 25 MHz 6 0 MHz 1 56 MHz 1 5 MHz 4 0 MHz 1 0 MHz 8 fmn f e 1 49Hz 1 43Hz 0 37Hz 0 357 Hz 0 95 Hz 0 24 Hz 2 f the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Configure CMT channel 0 for 10ys operation R_CMT_Create 0 PDL_CMT_PERIOD 10E 6 PDL_NO_FUNC 0 Y Configure CMT channel 1 for 1kHz operation R_CMT_Create 1 PDL_CMT_FREQUENCY 1E3 PDL_NO_FUNC 0 Y Configure CMT channel 2 using register values R_CMT_Create 2 PDL_CMT_PCLK_DIV_32 Ox55AA PDL_NO_FUNC 0 i R20UT2201EE0211 Rev 2 11 LEN ESAS Page 219 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_CMT_CreateOneShot Synopsis Prototype Description Return value Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint
331. e if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit None Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function e f corresponding interrupt source is enabled the input capture compare match status flag will be cleared automatically in interrupt service routine RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint16_t General_A uint16_t General_D void func void Read the status flags and registers of channel 3 R_MTU3_ReadChannel 3 amp Flags PDL_NO_PT amp General_ PDL_NO_PT PDL_NO_PT amp General_ PDL_NO_PT PDL_NO_PT Cae ano Rev 2 11 EN ESAS Page 178 of 418 RX63T Group 4 Library Reference 7 R_MTU3_ReadUnit Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Read from MTU registers bool R_MTU3_ReadUnit uint8_t data1 Unit selection uint8_t data2 Register selection uint16_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location Read any of the timer units s counter registers data1 The unit number n where n 0 data2 e Channel pair selection PDL_
332. e match or input capture Valid for n 0 3 4 6 and 7 Cleared by TGRD compare match or input capture Valid for n 0 3 4 6 and 7 PDL_MTU3_CLEAR_TGRC or PDL_MTU3_CLEAR_TGRD Counter clock source selection Valid for n 5 PDL_MTU3_CLKU_PCLKA_DIV_1 or PDL_MTU3_CLKU_PCLKA_DIV_4 or Counter TCNTU is supplied by the internal PDL_MTU3_CLKU_PCLKA_DIV_16 or clock signal PCLKA 1 4 16 or 64 PDL_MTU3 CLKU_PCLKA_DIV_64 PDL_MTU3_CLKV_PCLKA_DIV_1 or PDL_MTU3_CLKV_PCLKA_DIV_4 or Counter TCNTV is supplied by the internal PDL_MTU3_CLKV_PCLKA_DIV_16 or clock signal PCLKA 1 4 16 or 64 PDL_MTU3_CLKV_PCLKA DIV_64 PDL_MTU3_CLKW_PCLKA DIV_1 or PDL_MTU3_CLKW_PCLKA_DIV_4 or Counter TCNTW is supplied by the internal PDL_MTU3_CLKW_PCLKA_DIV_16 or clock signal PCLKA 1 4 16 or 64 PDL_MTU3 CLKW_PCLKA_DIV_64 Counter clearing U V and W counters Valid for n 5 PDL_MTU3_CLEAR_TGRU_DISABLE or Disable or enable clearing of TCNTU by TGRU PDL_MTU3_CLEAR_TGRU_ENABLE compare match or input capture PDL_MTU3_CLEAR_TGRV_DISABLE or Disable or enable clearing of TCNTV by TGRV PDL_MTU3_CLEAR_TGRV_ENABLE compare match or input capture PDL_MTU3_CLEAR_TGRW_DISABLE or Disable or enable clearing of TCNTW by PDL_MTU3_CLEAR_TGRW_ENABLE TGRW compare match or input capture R20UT2201EE0211 Rev 2 11 EN ESAS Page 158 of 418 Sept 12 2014
333. e of the watchdog timer providing the following operations 1 Configuring the timer for use including Clock selection Time out period Window position Reset or NMI Interrupt selection when timer overflows 2 Control of the timer including e Counter refresh to prevent timeout 3 Reading the timer status including counter value R20UT2201EE0211 Rev 2 11 AS Page 35 of 418 Sept 12 2014 RENES RX63T Group 2 Driver 2 20 Independent Watchdog Timer Driver The driver functions support the use of the independent watchdog timer providing the following operations 1 Configuring the timer for use 2 Refreshing the timer to prevent the reset operation 3 Reading the timer status and counter register R20UT2201EE0211 Rev 2 11 EN ESAS Page 36 of 418 Sept 12 2014 RX63T Group 2 Driver 2 21 Serial Communication Interface Driver The driver functions support the use of the serial communication SCI channels providing the following operations WV 2 8 9 Selection of the SCI pins for use Configuration for use including Automatic baud rate clock calculations Automatic interrupt control Automatic I O pin configuration Supporting the following modes Asynchronous Multi Processor Clock Synchronous Smart Card Interface Simple IIC Simple SPI o0o0000 Disabling channels that are no longer required Transmitting data with polling or interrupt mode automatically selected Receiving data w
334. e optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required Counter stop control Unit selection Apointer to the structure Control selection Control selection Control selection Control selection Control selection Register selection Register value Register value Register value 4 Library Reference PDL MTU3_STOP CH PDL MTU3_STOP CH PDL MTU3_STOP CH PDL MTU3_STOP CH PDL MTU3_STOP CH PDL MTU3_STOP CH PDL MTU3_STOP N O A w0 N 0 CH Stop the count operation for the selected channels Counter start control PDL MTU3_START CH PDL MTU3_START CH PDL MTU3_START CH PDL MTU3_START CH PDL MTU3_START CH PDL MTU3_START CH PDL MTU3_START NO amp Oo Po o CH Start the count operation for the selected channels The start will be simultaneous Rev 2 11 ENESAS Page 170 of 418 RX63T Group Description 2 6 R20UT2201EE0211 Sept 12 2014 Rev 2 11 pair_control Channel pair configuration control 4 Library Reference Select the pair of channels that will be configured by the controls specified below and in parameters data4 to data7 e Channel pair selection
335. e or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to
336. e packages with 112 pins or less data2 Control the channel If multiple selections are required use to separate each selection e Stop generation PDL_IIC_STOP Issue a Stop condition e NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state e Pin control PDL_IIC_SDA_LOW or PDL_IIC_SDA HI_Z Set the SDA pin to low level or high impedance PDL_IIC_SCL_LOW or PDL_IIC_SCL_HI_Z Set the SCL pin to low level or high impedance e Extra clock cycle generat ion PDL_IIC_CYCLE_SCL Generate an extra clock cycle on the SCL pin This can be used in Master mode to try and unlock a slave device that is holding the SDA signal low e Reset control PDL_IIC_ RESET Carry out an internal reset of the 12C module the settings are preserved True if all parameters are valid exclusive and achievable otherwise false 12C R_IIC_Create e Channel 1 is supported on 120 pin 144 pin packages only RPDL definitions include r_pdl_iic h RPDL device specific definitions include void func void r pdl_definitions h Issue a Stop condition on channel 0 R_IIC_Control 0 PDL_IIC_STOP ENESAS Page 276 of 418 RX63T Group 4 Library Reference 9 R_IIC_GetStatus Synopsis Read the status for an l C channel Prototype bool R_IIC_GetStatus uint8_t
337. e power down state Ifthe D A A D synchronous conversion is enabled the 10 bit ADC should not be shut down as it will halt the D A conversion too User should ensure that the 10 bit A D converter remains stopped when setting the D A A D synchronous conversion e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only Rev 2 11 EN ESAS Page 323 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Set up DAC channel 1 with default operation mid voltage R_DAC_10_Create PDL_DAC_10_CHANNEL_1 0 1024 2 R20UT2201EE0211 Rev 2 11 RENESAS Page 324 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_DAC 10 Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Disable a DAC channel bool R_DAC_10_Destroy uint8 tdata Channel selection Disable the channel output data1 Disable selection To set multiple options at the same time use to separate each value PDL DAC_10 CHANNEL 0 Disable channel 0 PDL DAC_10 CHANNEL 1 Disable channel 1 True if the parameter is valid otherwise false DAC None Once both channels a
338. e required source files Add the driver library file to the linked files list 2252 The instructions to follow for stand alone use start are given below 1 Unzip the RPDL files Double click on the file RPDL_RX63T exe to unpack the files The default location is CARenesasIRPDL_RX63T 2 Copy the files into your project area Navigate to where the RPDL files were unpacked e a F C Renes gt J Common J Device specific amp Copy_RPDL_RX63T bat Double click on Copy _RPDL_RX63T bat to start the copy process R20UT2201EE0211 Rev 2 11 RENESAS Page 3 of 418 Sept 12 2014 RX63T Group 1 Introduction Gi EN C Windows system32 cmd exe Renesas RPDL for R amp X63T copy utility Please enter a number to select the device package and endian option pins little endian pins big endian pins little endian pins big endian pins little endian pins big endian pins little endian pins big endian pins little endian pins big endian pins little endian pins big endian 1 2 3 4 5 6 8 9 a 1 2 Select the device package option by pressing a number and then press Enter Fr y aj EN C Windows system32 cmd exe o Renesas RPDL for R amp X63T copy utility Please enter a number to select the device package and endian option 48 pins little endian 48 pins big endian 64 pins little endian 64 pins big endian 166 pins little endian 166 pins big endian 112 pi
339. e stored in register ADSHCR Self diagnostic control PDL_ADC_12 SELF_DIAGNOSTIC_DISABLE or PDL_ADC_12 SELF _DIAGNOSTIC_VREFHO_ZERO or x0 PDL_ADC_12_SELF_DIAGNOSTIC_VREFHO_HALF or x Y PDL_ADC_12_SELF_DIAGNOSTIC_VREFHO_FULL or x 1or PDL_ADC 12 SELF DIAGNOSTIC_VREFHO_ROTATED automatically rotated voltage Disable the self diagnostic function or enable and use the voltage on pin VREFHO Rev 2 11 ENESAS Page 298 of 418 RX63T Group 4 Library Reference Description 3 6 data3 data5 Options for two ADC groups in group scan mode In other operating modes only data3 is valid applying to all the working ADC channels To set multiple options at the same time use to separate each value e MTU trigger source selection Valid only if PDL_ADC_12 SYNC_TRIGGER_ENABLE is selected Input capture or compare match PDL_ADC_12_GP_TRIGGER_MTU3_TRGAON or with MTUO TGRA nput capture or compare match PDL_ADC_12 GP_TRIGGER_MTU3_TRGA1N or with MTU1 TGRA Input capture or compare match PDL_ADC_12 GP_TRIGGER_MTU3_TRGAZ2N or with MTU2 TGRA PDL_ADC_12 GP_TRIGGER_MTU3_TRGASN or Input capture or compare match with MTU3 TGRA Input capture or compare match with MTU4 TGRA or in PDL_ADC_ 12 GP_TRIGGER_MTU3_TRGA4N or complementary PWM mode an underflow of MTU4 TCNT in the trough Input capture or compare match PDL_ADC_12 GP_TRIGGER_MTU3_TRGA6N or with MTU6 TGRA
340. e used for signal CS3 e WAIT pin selection only required if the WAIT signal is to be used PDL_BSC_WAIT_P05 or PDL_BSC_WAIT_P82 or PDL_BSC_WAIT_PEO Select the port pin to be used for signal WAIT NOTE PDL_BSC_WAIT_P05 is only available in the 144 pin and 112 pin package ALE signal control only required if the ALE signal is to be used PDL BSC_ALE ENABLE Enable the ALE signal on pin P11 data2 e Address output control The signals are enabled by default unless the pin is allocated to a bus control signal If multiple selections are required use to separate each selection Specify PDL_NO_DATA for no change Ignored for the 64 pin and 48 pin device package specify PDL_NO_DATA PDL_BSC_A7_A0_ DISABLE Disable the output of the A7 to AO signals PDL_BSC _A8 DISABLE Disable the output of the A8 signal PDL_BSC_A9 DISABLE Disable the output of the A9 signal PDL_BSC_A10_DISABLE Disable the output of the A10 signal PDL_BSC_A11_DISABLE Disable the output of the A11 signal PDL_BSC_A12 DISABLE Disable the output of the A12 signal PDL_BSC_A13_DISABLE Disable the output of the A13 signal PDL_BSC_A14_DISABLE Disable the output of the A14 signal PDL_BSC_A15_ DISABLE Disable the output of the A15 signal PDL_BSC_A16_DISABLE Disable the output of the A16 signal PDL_BSC_A17_DISABLE Disable the output of t
341. ect between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for the corresponding callback functions func5 For n 0 The function to be called when a TGRE event occurs Specify PDL_NO_FUNC if not required func6 For n 0 The function to be called when a TGRF event occurs Specify PDL_NO_FUNC if not required func7 For n 0 to 3 or 6 The function to be called when an overflow occurs For n 4 or 7 The function to be called when an overflow or underflow occurs Specify PDL_NO_FUNC if not required func8 For n 1 and 2 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required interrupt_priority_2 The interrupt priority level for TGRE TGRF overflow and underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 5 to 8 interrupt_priority_3 For n 7 The interrupt priority level for TGRC and TGRD events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO FUNC is specified for parameters func3 and func4 True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU3 Set R_MTU3_ControlChannel R_MTU3_ControlUnit Rev 2 11 EN ESAS Page 164 of 418 RX63T Group 4 Library Reference Remarks Prog
342. ection 0 No activity 1 The exit from deep software standby was caused by one of the following signals IRQ7 DS IRQ6 DS IRQ5 DS IRQ4 DS IRQ3 DS IRQ2 DS IRQ1 DS IRQ0 DS Return value True Category LPC References R_LPC_Create R_LPC_Control Remarks Ifa flag is set to 1 it shall be automatically cleared to O by this function Program example RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint32_t status_flags Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flags i R20UT2201EE0211 Rev 2 11 RENESAS Page 120 of 418 Sept 12 2014 RX63T Group 4 2 9 Register Write Protection 1 R_RWP_Control Synopsis Prototype Description Return value Category References Control register write protection bool R_RWP_Conirol uint8_t data Configuration selection Control register write protection data Write enable control 4 Library Reference To set multiple options at the same time use to separate each value e Register write control PDL_RWP_ENABLE_CGC_WRITE or PDL_RWP_DISABLE_CGC_WRITE Enable or disable writing to CGC registers PDL_RWP_ENABLE_MODE_RESET_WRITE or PDL_RWP_DISABLE_MODE_RESET_WRITE Enable or disable
343. efinitions tinclude r_pdl_iic h RPDL device specific definitions tinclude r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 5 bytes from device OxAA on channel 0 using polling R_IIC_MasterReceive 0 PDL_NO_DATA OxAA data_array 5 PDL_NO_FUNC 0 i Rev 2 11 ENESAS Page 271 of 418 RX63T Group 5 R_IIC_MasterReceiveLast Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast uint8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false 12C R_IIC_GetStatus 4 Library Reference e This function must only be used to terminate a Read process that has used the DMAC or DTC e Use R_IIC_GetStatus to determine if the transfer was successful e Please specify one byte less in the Transfer Count when using with the DMAC or DTC e Channel 1 is supported on 120 pin 144 pin packages only RPDL definitions tinclude r_p
344. egister Write Protection Drivel sm siekme a a a e i 27 2 12 B s Controller Drive seorsan a A iaia A 1 a a AR NE 28 2 13 DMA Controller Dive sorea in EE AAA S E E EAA aAA AE EEE AE e A 29 2 14 Data Transfer Controller Driver 0 cccceesceceeececeneeeeeeeeeeeeceaeeeeaaeseeaeeeeeeeeceaeseeaaesseneeseaeeesaesseaaesseneesaas 30 2 15 Multi Function Timer Pulse Unit Driver oooococonnccnnnnncccnnnneccnnnnccnc narran 31 2 16 Port Output Enable Driver ooooonnnncinncninncconncconncnnnccnnanncnnancnn anna cnn cnn rra 32 2 17 General PWM Timer Driver ooooooccconoccccconoccncnononnconannnnnnanonnncnannnnncnnnn rn ncnnn nn nr nano rn nr ran rn SEEEN rn rrnnnnrnnnnnness 33 2 18 Compare Match Timer Driver ooooninnccnnnccnnnnnnncconnonnnn nc cnnnncn anna rn 34 2 19 Watchdog Timer Drivetime ainai aeaieie iad aia iane ap adaa d e adaa aeiae a ad a 35 2 20 Independent Watchdog Timer Drivefier esercitano a e aea eaei aR EA Ri 36 2 21 Serial Communication Interface Driver cooonccnnnononcccnnnnnnnnnonacannnnnn nono nonanannnn cn nono naar ana nnn nono nananinnannnns 37 2 22 G Bus Interface Drive at ead 38 2 23 Serial Peripheral Interface Driver oonocicccnnnicinnncnnnccnncccnonncnnonn nn nrn crac cnn nn 39 2 24 GRG Calculator Driver ii Aia 40 2 25 12 bit Analog to Digital Converter Driver ooooonnnnninnccnnccnnononnonnnnnccnnoncccnnrnnn nn nn nnnc crac rara ranma 41 2 26 10 bit Analog to Digital Converter DriVeF oooonnn
345. egory General PWM Timer unit Reference R_GPT_CreateUnit Remarks e If there are I O pins to be used call this function before calling R_GPT_CreateUnit Not all device packages have all of the pin options Program example RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void R_GPT_Set 0 PDL_GPT_PIN_GTIOCOA_P71 R20UT2201EE0211 Rev 2 11 RENESAS Page 190 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_GPT_CreateUnit Synopsis Configure the GPT unit Prototype bool R_GPT_CreateUnit uint8_t data1 Unit selection uint32_t data2 Configuration options Description Set up the global GPT options data1 The unit number n where n 0 for 64 and 48 pin packages n 0 1 for 144 120 112 100 pin packages data2 Configure the global options Use to separate each selection External trigger interrupt control PDL_GPT_EXT_TRIGGER_INT_DISABLE or Disable or enable an interrupt request for PDL_GPT_EXT_TRIGGER_INT_RISING or rising edge PDL_GPT_EXT_TRIGGER_INT_FALLING or falling edge or PDL_GPT_EXT_TRIGGER_INT_BOTH falling and rising edge on pin GTETRG IWDTCLK counter control PDL_GPT_IWDTCLK_COUNT_CLK_PCLK_DIV_1 or Select the clock PCLKA 1 2 4 PDL_GPT_IWDTCLK_COUNT_CLK_PCLK_DIV_2 or or 8 for counting PDL_GPT_IWDTCLK
346. eneral register C Valid for n 0 3 4 6 and 7 PDL_MTU3_ REGISTER _TGRD General register D Valid for n 0 3 4 6 and 7 PDL_MTU3_REGISTER_TGRE General register E Valid for n 0 3 4 6 and 7 PDL_MTU3_REGISTER_TGRF General register F Valid for n 0 4 and 7 ADC start request cycle set buffer A PDL_MTU3_REGISTER_TADCOBRA Valid for n 4 and 7 ADC start request cycle set buffer B PDL_MTU3_REGISTER_TADCOBRB Valid for n 4 and 7 Rev 2 11 EN ESAS Page 167 of 418 RX63T Group Description 2 2 4 Library Reference For n 5 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 PDL_MTU3_REGISTER_COUNTER_U Timer counter U register TCNTU PDL_MTU3_REGISTER_COUNTER_V Timer counter V register TCNTV PDL_MTU3_REGISTER_COUNTER_W Timer counter W register TCNTW PDL_MTU3_REGISTER_TGRU General register U PDL_MTU3 REGISTER_TGRV General register V PDL_MTU3_REGISTER_TGRW General register W TCNT_TCNTU_value For n 5 The timer counter TCNT value For n 5 The timer counter TCNTU value This will be ignored if the register is not selected TGRA_TCNTV_value For n 5 The register TGRA value For n 5 The timer counter TCNTV value This will be ignored if the register is not selected TGRB_TCNTW_value For n 5 The register TGRB value For n 5 The timer counter TCNTW value This will be ignored if
347. equency error void CAC_overflow void Handle the overflow error Figure 5 6 Example of Clock Frequency measurement use R20UT2201EE0211 Rev 2 11 RENESAS Page 345 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 7 Low Power Consumption 5 7 1 Software Standby Mode Figure 5 7 shows an example of entering Software Standby mode through Low Power Consumption control Peripheral driver function prototypes include r_pdl_lpc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h if defined DEVICE_PACKAGE_64_PIN amp amp defined DE E_PACKAGE_48_PIN define PDL_INTC_IRO2_ PIN PDL_INTC_IRQ2_PE3 else define PDL_INTC_IRO2_PIN PDL_INTC_IRO2_P00 endif static void SW3_handler void void main void Set IRQ2 interrupt R_INTC_SetExtInterrupt PDL_INTC_IRQ2_PIN Y Enable the IRQ2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRO2 PDL_INTC_FALLING SW3_handler 7 Y Select the default options R_LPC_Create PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA y Enter software standby mode R_LPC_Control PDL_LPC_MODE_SOFTWARE_STANDBY Y Normal execution will resume after IRQ2 falling signal while 1 IRQ2 Falling signal static void SW3_handler void Figure
348. er Mode sic A earn 389 1 Configuration and transmission ooncccnnnninnnnnnnncnnnccnnrcc crac 390 2 ROCA 391 3 Repeat adios 392 5 18 2 Master mode with DMAC oonnnccccnccnnnnicnnccnnnncncanc cnn cnc 393 5 18 3 Master mode with DTC ooonnnnninnccnnccnnnccnnccnnnccnnrncnnrrnn nan rnnnncccrnrrrrrrrrr 397 Dorado Slave Mode aaa la aa 401 5 19 Serial Peripheral InterfaCe oooocnnncinnnininnicnnnccnnnconocnnnnccnnanccnnnr nan nn rana crac ranas 404 5 19 1 Master operation with multiple SlavesS ooonnncccninnciccnnnnccccnnnonnncnanonnnnnnnnnnnncnnn nn nr rana rn rana 404 5 20 4 GRG calcUlalo ta ains 407 5 21 12 bit Analog to Digital Converter ooonnccinnccnnnncnnccnnoncnconccnnnrnnn nn nan cnn rca rana ranma 408 5 22 10 bit Analog to Digital CONVerter oocnnccnncconnncconccnnoncnnonccnnnrn nano nn nano cc nn rca rana ranma 410 5 23 10 bit Digital to Analog Converter occoncccnnccnnonccononnnonenconccnonrnnn nn nn nano cnn rra n nn rana rana cnn 412 5 24 Data Operation GlrCulbiua siii a eatin ese 413 5 25 Multifuncion Pin Controller tao a dc ira 415 5 26 Multi Function Timer Pulse Unit ooocccinnccnnncconccconoccnnccnnonccnnnrn nana nano corn canon 416 6 AX Specific NOS ota 418 6 1 Interrupts and processor Modeen ianaeaiiy TD enn nnnr rca 418 6 2 Interrupts and DSPINStUCIONS dd a ad tian een 418 FRE VISION ISO ana ALE 1 RX63T Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unif
349. eral register A value General register B value General register C value General register D value General register E value General register F value Cycle setting register value Cycle setting buffer register value Cycle setting double buffer register value ADC start request A register value ADC start request A buffer register value ADC start request A double buffer register value ADC start request B register value ADC start request B buffer register value ADC start request B double buffer register value Dead time up counting register value Dead time up counting buffer register value Dead time down counting register value Dead time down counting buffer register value Description 1 3 Modify a timer channel s registers R20UT2201EE0211 Sept 12 2014 data1 The channel number n where n 0 to 3 for 64 and 48 pin packages n 0 to 7 for 144 120 112 100 pin packages data2 The channel settings to be modified All selections are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop start PDL_GPT_STOP Stop the count operation PDL_GPT_ START Start the count operation Counter clearin PDL_GPT_ COUNTER CLEAR Clear the counter Buffer operation control PDL_GPT_BUFFER_CMIC_STOP PDL_GPT BUFFER CMIC START D
350. errupt request flag This is not required if e Acallback function has been specified e The interrupt priority level is higher than 0 e The processor interrupt priority level is lower than the interrupt priority level This operation should not be applied when low level detection is used PDL_INTC_CLEAR_OSD_FLAG Clear the Oscillation Stop detection NMI flag PDL_INTC_CLEAR_WDT_FLAG Clear the WDT event detection NMI flag PDL_INTC_CLEAR_IWDT_FLAG Clear the IWDT event detection NMI flag PDL_INTC_CLEAR_LVD1_FLAG Clear the LVD1 event detection NMI flag PDL_INTC_CLEAR_LVD2_FLAG Clear the LVD2 event detection NMI flag True if all parameters are valid and exclusive otherwise false The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an When disabling an IRQn pin the Interrupt Request flag will be cleared automatically Acallback function may be called once more if a valid event occurs just before the interrupt Category Interrupt control Reference R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus Remarks MCU design feature pin is disabled R20UT2201EE0211 Rev 2 11 Sept 12 2014 ENESAS Page 66 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func v
351. ess mode for the transfer data areas uint32_t dtc_sw_transfer_data 4 3 const char source_string_1 Renesas RX63T const char source_string_2 DTC example const char source_string_3 using chain transfer volatile char destination_string_1 volatile char destination_string_2 volatile char destination_string_3 void main void Enable software interrupts INTC_CreateSoftwarelnterrupt PDL_INTC_DTC_SW_TRIGGER_ PDL_NO_FUNC 0 Configure the controller R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table R20UT2201EE0211 Rev 2 11 RENESAS Page 357 of 418 Sept 12 2014 RX63T Group 5 Usage Examples Configure the DTC for Software trigger R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ ESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_CHAIN_O PDL_DTC_TRIGG dtc_sw_transfer_data source_string_l destination_string_l 1 uint8_t strlen source_string_1 y Configure the DTC for chain transfer R_DTC_Create PDL_DTC_BLOCK PDL_DTC_SOURCE PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_CHAIN_O PDL_DTC_TRIGGER_CHAIN dtc_sw_transfer_data 4 source_string_2 destination_string_2 1 uint8_t strlen source_string_2 y Configure the DTC for chain transfer R_DTC
352. et the IWDTCLK division ratio accordingly This function will return false if this condition is detected Delete remark Call R_CGC_Set to set PCLKB clock frequency gt 4 times R20UT2201EE0211 Rev 2 11 EN ESAS Revision history 4 Sept 12 2014 RX63T Group Revision History Dat Description ate Summary oe clock frequency after division R20UT2201EE0211 Rev 2 11 EN ESAS Revision history 5 Sept 12 2014 Renesas Peripheral Driver Library User s Manual RX63T Group Publication Date Rev 2 11 Sept 12 2014 Published by Renesas Electronics Corporation ENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd Room 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China Tel 86 10 8235 1155 Fax
353. etected True Clock generation circuit R_CGC_Control e Use R_CGC_Control to clear the main clock oscillation stop detection flag RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t Status_flags R_CGC_Get Status amp Status_flags Y ENESAS Page 55 of 418 RX63T Group 4 Library Reference 4 2 2 Interrupt Control Unit 1 R_INTC_SetExtInterrupt Synopsis Prototype Description Return value Category References R20UT2201EE0211 Sept 12 2014 Select the external interrupt pins bool R_INTC_SetExtinterrupt uint32_t data Pin selection Assign the external interrupt pins data Allocate the pins for signals IRQO to IRQ5 for 64 and 48 pin packages Allocate the pins for signals IRQO to IRQ7 for 144 120 112 and 100 pin packages All selections are optional If multiple selections are required use to separate each selection Please refer to Table 21 1 at the Multifunction Pin Controller MPC section in the RX63T Hardware Manual for details of pin package PDL_INTC_IRQO_P10 or PDL_INTC_IRQO_PB5 PDL_INTC_IRQ1_P11 or PDL_INTC_IRQ1_P93 Select the pins to be used for signals IRQO to IRQ5 for 64 and PDL_INTC_IRQ2_P00 48 pin packages PDL_INTC_IRQ3_PB4 PDL_INTC_IRQ4 P01 PDL_INTC_IRQ5_P70
354. f slave address 0 in PDL_IIC_SLAVE_O0_ENABLE_7 or 7 bit or PDL_IIC_ SLAVE 0 ENABLE 10 10 bit format PDL_IIC_ SLAVE _1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE_7 or 7 bit or PDL_IIC_ SLAVE 1 ENABLE 10 10 bit format PDL_IIC_ SLAVE _2 DISABLE or Disable or enable detection of slave address 2 in PDL_IIC_SLAVE_2 ENABLE_7 or 7 bit or PDL_IIC_SLAVE 2 ENABLE 10 10 bit format PDL_IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ENABLE address e Device ID detection control PDL_IIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID PDL_IIC_DEVICE_ID_ ENABLE address 1111 100b Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host PDL_IIC_HOST_ADDRESS_ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Ignored if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 b0 4 i Bit rate high level register Bit rate low level register
355. ferCount Read the status and current source address for the IRO2 transfer R_DTC_GetStatus dtc_irq_transfer_data amp StatusValue amp SourceAddr amp DestAddr amp TransferCount PDL_NO_DATA Invert the LED port pin R_IO_PORT_Modify PDL_IO_PORT_7_1 PDL_IO PORT _XOR 1 Re enable IRQ2 as a DTC trigger R DTC Controli PDL_DTC_TRIGGER_IRQ2 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Figure 5 12 Example of DTC use R20UT2201EE0211 Rev 2 11 AS Page 356 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 10 2 Chain transfer operation Figure 5 13 shows an example of Data Transfer Controller operation using chain transfer of blocks Address space destination_string_3 destination_string_2 destination_string_1 Transfer 1 is triggered by a software interrupt and copies data from ROM into RAM On completion of transfer 1 transfer 2 is started On completion of transfer 2 transfer 3 is started Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve three contiguous groups of 16 bytes full addr
356. ffer register CACNTBR value shall be stored Specify PDL_NO_PTR if it is not required True Clock frequency accuracy measurement circuit None None RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t Status_flags R_CAC_GetStatus amp Status_flags PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR ENESAS Page 112 of 418 RX63T Group 4 2 8 Low Power Consumption 1 R_LPC_Create Synopsis Configure the MCU low power conditions Prototype bool R_LPC_Create uint8_t data1 Configuration options 4 Library Reference uint32_t data2 Select deep standby interrupt uint32_t data3 Select deep standby interrupt uint16_t data4 Main oscillator waiting times uinti6_tdata5 PLL waiting times Description 1 2 R20UT2201EE0211 Sept 12 2014 data1 Select the required settings Load the registers that control module or CPU operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults 1 O port retention control PDL_LPC_IO SAME or PDL_LPC_IO_ DELAY Select whether I O port retention is cancelled when deep software standby mode is ended or when CPU operation has resumed e Output port retention control This function is supp
357. for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control Channel specific configuration for use including Double trigger control Sample and hold control Sampling time control Comparator control Disabling the unit when no longer required and enabling low power mode Control the ADC unit including e CPU sleep option Reading the conversion results with support for polling or interrupts Note The Clock Generation Circuit must be configured before configuring the ADC unit R20UT2201EE0211 Rev 2 11 ENESAS Page 41 of 418 Sept 12 2014 RX63T Group 2 Driver 2 26 10 bit Analog to Digital Converter Driver The driver functions support the use of the 10 bit ADC unit 0 providing the following operations 1 I O configuration 2 Configuration of the ADC unit 3 Channel specific configuration for use including e Value addition control e Sampling time control 4 Disabling the unit when no longer required and enabling low power mode 5 Control the ADC unit including e CPU sleep option 6 Reading the conversion results with support for polling or interrupt Note The Clock Generation Circuit must be configured before configuring the ADC unit R20UT2201EE0211 Rev 2 11 LEN ESAS Page 42 of 418 Sept 12 2014 RX63T Group 2 27 10 bit Digital to Analog Converter Driver The driver functions support the use of the DAC module providing the following operations 1 Confi
358. function This function is not required when using 64 pin and 48 pin package Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Disable the CS3 area R_BSC_Destroy 3 Y R20UT2201EE0211 Rev 2 11 RENESAS Page 130 of 418 Sept 12 2014 RX63T Group 4 Library Reference 5 R_BSC_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Modify the Bus Controller operation bool R_BSC_Control uint8_t data Control options Control the BSC operation data Control the BSC operation e Start stop operation PDL_BSC_ENABLE or Enable or disable BSC operation PDL_BSC_DISABLE Ignored for the 64 pin and 48 pin device package Error clearing PDL_BSC_ERROR_CLEAR Clear the bus error status registers Disable bus error interrupt request PDL_BSC _DISABLE _BUSERR_IRQ Disable bus error interrupt requests True if success False if invalid parameters are selected Bus Controller R_BSC_Create Before enabling the BSC operation call R_BSC_Create e This function can be called from the error handling function assigned in R_BSC_Create e This function will clear the Interrupt Status Flag indirectly
359. ge 388 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 18 12C Bus Interface In the following examples the bus activity will be illustrated using the following format AA el ee AA From the master A Acknowledge SDA held low Not Acknowledge SDA released high Vinee S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 5 31 I C bus activity notation 5 18 1 Master mode In this example an EEPROM device has been connected to channel 0 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write process i The bits xxx represent the EEPROM memory address bits a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycle time of 5 ms The following examples illustrate the use of Master mode R20UT2201EE0211 Rev 2 11 RENESAS Page 389 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 1 Configuration and transmission The MCU s I2C channel 0 will be configured for Master operation and used to send 4 bytes to a slave SS A EN AAA AAA Figure 5 32 The bus activity showing 4 bytes being transmitted to the EEPROM Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h RPDL device specific definitions
360. gly This function will return false if this condition is detected ENESAS Page 230 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Configure the IWDT R_IWDT_Set PDL_IWDT_TIMEOUT_16384 PDL_IWDT_CLOCK_OCO_256 y R20UT2201EE0211 Rev 2 11 RENESAS Page 231 of 418 Sept 12 2014 RX63T Group 4 Library Reference 2 R_IWDT_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Control the Independent Watchdog operation bool R_IWDT_Control uint8 tdata Control selection Modify the operation of the Independent Watchdog timer data Control the timer e Counter start refresh PDL_IWDT_REFRESH Start or refresh the counter by re loading the timeout value True if the parameter is valid otherwise false Independent Watchdog Timer R_IWDT_Set R_IWDT_Set must be used first to configure the timer unless using Initial Setting Memory using R_MCU_OFS to enable the IWDT from reset RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r_pdl_definitions h void func void Refresh the IWDT R_IWDT_Control PDL_IWDT
361. guring a channel for use including e Data alignment D A A D synchronous conversion 2 Disabling channels that are no longer required and enabling low power mode 3 Writing data to a channel R20UT2201EE0211 Rev 2 11 RENESAS Sept 12 2014 2 Driver Page 43 of 418 RX63T Group 2 Driver 2 28 Data Operation Circuit The driver functions support the use of the DOC module providing the following operations 1 Configuring and enabling the DOC 2 Disabling the DOC 3 Controlling operation including switching between comparison addition and subtraction modes 4 Writing data to the DOC 5 Reading result from DOC R20UT2201EE0211 Rev 2 11 RENESAS Page 44 of 418 Sept 12 2014 RX63T Group 3 Types and definitions 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the setting values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types Type Defined in Description Range bool stdbool h Boolean 0 false to 1 true double C Floating point 64 bits uint8_t Unsigned 8 bits 0 to 255 uint16_t sidintih Unsigned 16 bits 0021 int32_t Signed 32 bits 20T to 2 1 uint32_t Unsigned 32 bits 0102 1 3 2 General definitions 3 2 1 PDL_NO_ FUNC Used as a parameter when there is no applicable function
362. h selection All selections are optional Specify PDL_NO_DATA if none are required Rev 2 11 High impedance request detection PDL_POE HI Z REQ 8 ENABLE Enable high impedance requests on pin POE8 PDL_POE HI_Z REQ 10 ENABLE Enable high impedance requests on pin POE10 PDL_POE HI_Z REQ 11_ ENABLE Enable high impedance requests on pin POE11 PDL_POE_HI_Z_ REQ 12 ENABLE Enable high impedance requests on pin POE12 PDL_POE_HI_Z_OSTST_ENABLE If stopped oscillation is detected place the MTU or GPT pins in the high impedance state ENESAS Page 180 of 418 RX63T Group Description 2 4 R20UT2201EE0211 Sept 12 2014 4 Library Reference e Select any event flags to be added to the high impedance control for the specified outputs PDL_POE _HI_Z MT34 ADD _CFLAG Comparator detection PDL_POE HI Z MT34 ADD_POE4 POE4 MTU channel 3 4 and PDL_POE HI Z MT34 ADD _POE8 A valid POE8 GPT channel 0 to 2 PDL_POE HI Z MT34 ADD POE10 edge on POE10 outputs PDL_POE HI Z MT34 ADD POE11 the pin POE11 i PDL_POE HI Z MT34 ADD POE12 POE12 PDL POE HI_Z MTO ADD CFLAG Comparator detection PDL_POE HI Z MTO_ADD_POEO POEO PDL_POE HI Z MTO_ADD_POE4 A valid POE4 MTU channel 0 PD
363. he A17 signal PDL_BSC_A19_DISABLE PDL_BSC_A18 DISABLE Disable the output of the A18 signal Disable the output of the A19 signal ENESAS Page 124 of 418 RX63T Group Description 2 2 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference data3 e Recovery cycle insertion control The controls are disabled by default Specify PDL_NO_DATA to use the defaults If multiple selections are required use to separate each selection Ignored for the 64 pin and 48 pin device package specify PDL_NO_DATA Bus access Bus type Current Next tee PDL_BSC_RCV_SRRS_ ENABLE Read Same PDL_BSC_RCV_SRRD_ENABLE Read Different PDL_BSC_RCV_SRWS_ENABLE Same Write PDL_BSC_RCV_SRWD_ENABLE Separate Different PDL_BSC_RCV_SWRS_ENABLE Read Same PDL_BSC_RCV_SWRD_ENABLE Write Different PDL_BSC_RCV_SWWS_ENABLE Write Same PDL_BSC_RCV_SWWD_ENABLE Different PDL_BSC_RCV_MRRS_ENABLE Read Same PDL_BSC_RCV_MRRD_ENABLE Read Different PDL_BSC_RCV_MRWS_ENABLE Write Same PDL_BSC_RCV_MRWD_ENABLE Different PDL_BSC_RCV_MWRS ENABLE Multiplexed ore Same PDL_BSC_RCV_MWRD_ENABLE Write Different PDL_BSC_RCV_MWWS_ENABLE Write Same PDL_BSC_RCV_MWWD_ENABLE Different data4 e Error monitor
364. he additional results are to be stored uint8_t data4 Pointer to the address where the comparator status is to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit to be configured For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Specify a pointer to an array where the converted values for analog input channels are to be stored The array length must gt the number of channels 8 for device packages with 48 or 64 pin otherwise 3 Specify PDL_NO_PTR if this information is not required data3 Specify a pointer to an array with 1 member or 3 members in double trigger mode only where the diagnostic result or double trigger results are to be stored depending on the ADC mode Specify PDL_NO_PTR if this information is not required Refer to hardware manual Section 34 2 2 for the format of self diagnosis result data4 Specify a pointer to the address where the comparator status is to be stored in the format below Specify PDL_NO_PTR if this information is not required For ADC unit 0 b7 b3 b2 bi bO 0 Specified condition detection 0 Not detected 1 Detected ANO02 ANOO1 AN000 For ADC unit 1 Valid on device packages with 100 pins or more b7 b3 b2 b1 bO 0 Specified condition detection 0 Not detected 1 Detected AN102 AN101 AN100 True if a valid unit is selected otherwise false 12 bit ADC R_ADC_
365. he status RPDL definitions include r_pdl_bsc h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint8_t statusl uintl6_t statusz Read the flags R_BSC_Get Status amp statusl status2 Rev 2 11 EN ESAS Page 132 of 418 RX63T Group 4 2 11 4 Library Reference DMA Controller 1 R_DMAC_Create Synopsis Prototype Description 1 4 R20UT2201EE0211 Sept 12 2014 Configure the DMA controller bool R_DMAC_Create uint8_t data1 uint32_t data2 uint8_t data3 void data4 void data5 uint16_t data6 uint16_t data7 Channel selection Configuration selection Trigger selection Source start address Destination start address Transfer count Repeat or Block size int32_t data8 Address offset uint32_t data9 Source address extended repeat area uint32_t data10 Destination address extended repeat area void func Callback function uint8_t data11 Interrupt priority level Set up a DMA channel data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn If multiple selections are required use to separate each selection The default settings are shown in bold Transfer mode selection PDL_DMAC_NORMAL or Normal or PDL_DMAC_REPEAT or Repeat or PDL_DMAC_BLOCK Block mode If Repeat or Block
366. high impedance state of the GPT PDL_POE _GPT67_HI_Z OFF channel 6 and 7 outputs data2 Event flag control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required PDL PDL PDL PDL PDL PDL PDL PDL PDL POE POE POE POE POE POE POE POE POE FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG FLAG POEO_CLEAR POE4 CLEAR POE8 CLEAR POE10_CLEAR POE11_CLEAR POE12_CLEAR SHORT_34 CLEAR SHORT_67_CLEAR OSTST_CLEAR Select the flags to be cleared data3 Interrupt control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e High impedance request response PDL_POE IRQ HI Z 0 DISABLE Control interrupts on detection of a high PDL_POE_IRQ_HI Z 0 ENABLE impedance request on pin POEO PDL_POE IRQ HI Z 4 DISABLE Control interrupts on detection of a high PDL_POE IRQ_HI Z 4 ENABLE impedance request on pin POE4 PDL_POE IRQ HI Z 8 DISABLE Control interrupts on detection of a high PDL_POE_IRQ_HI_Z 8 ENABLE impedance request on pin POE8 PDL_POE_IRQ_HI_Z_10 DISABLE Control interrupts on detection of a high PDL_POE_IRQ_HI_Z_ 10 ENABLE impedance request on pin POE10 PDL_POE_IRQ_HI_Z_11_DISABL
367. hot d E 3 DL_NO_FUNC R20UT2201EE0211 Rev 2 11 RENESAS Page 399 of 418 Sept 12 2014 RX63T Group 5 Usage Examples static void read_eeprom_data void bus_busy true Read data from the EEPROM using the DTC R_IIC_MasterReceive IIC_CHANNEL PDL_IIC_DTC_TRIGG EEPROM_ADDRESS DL_NO_PTR P 0 iic_rx_end_handler 7 while bus_busy true void iic_tx_end_handler void uint32_t status_flags 0 Wait for the transmission to complete do R_IIC_GetStatus IIC_CHANNEL gstatus_flags PDL_NO_PTR PDL_NO_PTR 3 while status_flags 0x0080u 0x0u Issue a Stop condition R TIC Control IIC_CHANNEL PDL_IIC_STOP di bus_busy false void iic_rx_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DTC_Get Status dtc_iicl_rx transfer_data PDL_NO_PTR PDL_NO_PTR DestAddr PDL_NO_PTR PDL_NO_PTR Y Read one more byte with NACK condition and stop R_IIC_MasterReceiveLast IIC_CHANNEL uint8_t DestAddr Y bus_busy false Figure 5 39 An example of writing data to and reading data from an EEPROM using the DTC R20UT2201EE0211 Rev 2 11 RENESAS Page 400 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 18 4 Slave mode In this example the MCU behaves as a virtu
368. id func void Read the status flags and general registers A and D of channel 3 R_GPT_ReadChannel 3 amp Flags amp General_A PDL_NO_PT L_NO_PT eneral_ L_NO_PT L_NO_PT m R R D R R L_NO_PTR R R R R F a ng T L_NO_PT T L_NO_PT E L_NO_PT F L_NO_PTR L_NO_PTR L_NO_PTR L_NO_PTR L_NO_PTR L_NO_PTR L_NO_PTR L_NO_PTR DL_NO_PTR DL_NO_PTR V G TIIU 2ang W D g o Lv O o a a g o g g o g e R20UT2201EE0211 Rev 2 11 AS Page 210 of 418 Sept 12 2014 RENES RX63T Group 4 Library Reference 8 R_GPT_ReadUnit Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Read the GPT unit flags bool R_GPT_ReadUnit uint8_t data1 Unit selection uint8_t data2 The flag storage location uint16_t data3 The IWDTCLK counter storage location uint16_t data4 The IWDTCLK count result average storage location uint16_t data5 The IWDTCLK count upper permissible deviation location uint16_t data6 The IWDTCLK count lower permissible deviation location uint16_t data7 The IWDTCLK count result storage location Read the GPT unit status and data data1 The unit number n where n 0 for 64 and 48 pin packages n 0 1 for 144 120 112 100 pin packages data2 The detec
369. ied API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics Renesas Peripheral Driver Library Target MCU Figure 1 1 System configuration with all peripherals supported by RPDL Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a A binary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library it is required that the user will have the following documents as a minimum i The hardware schematic diagram ii The RX63T MCU hardware manual jii This RPDL API User s manual The binary file is produced using the Renesas RX C tool chain It should be usable by another linker that conforms to the Renesas Application Binary Interface RPDL has not been designed to be compatible for use with an RTOS The coding standards and naming conventions are specified by Renesas R20UT2201EE0211 Rev 2 11 tENESAS Page 1 of 418 Sept 12 2014 RX63T Group 1 Introduction 1 1 Tool chain requirements This RPDL library has been built and tested using the C C Compiler Package for RX Family V 1 02 Release 01 It cannot be used with older ve
370. in PCo PDL_IO_PORT_O 1 Port pin PO PDL_IO_PORT_6 1 Port pin P64 PDL_IO PORT _C_1 Port pin PC PDL_IO_PORT_0 2 PortpinPO2 PDL_IO PORT 6 2 Port pin P62 PDL IO PORT_C 2 Port pin PC gt PDL_IO PORT_0 3 PortpinPOz PDL_IO PORT_6 3 Port pin P63 PDL_IO PORT _C_3 Port pin PCs PDL_IO PORT _0 4 Portpin PO PDL_IO PORT 6 4 Port pin P64 PDL_IO PORT _C 4 Port pin PC PDL_IO PORT_0 5 PortpinPOs PDL_ IO PORT 6 5 Port pin P65 PDL_IO PORT _C_5 Port pin PCs PDL_IO PORT_1 0 PortpinP1to PDL_IO PORT_7 0 Port pin P7o PDL_IO PORT_D 0 Port pin PDo PDL_IO_PORT_1 1 Port pin P14 PDL_IO_PORT_7_1 Port pin P74 PDL_IO PORT _D_1 Port pin PD PDL_IO PORT_1 2 PortpinPi2 PDL_IO PORT 7 2 Port pin P72 PDL_IO _PORT_D 2 Port pin PD PDL_LIO PORT_1 3 Portpin P13 PDL_IO PORT_7 3 Port pin P73 PDL_IO PORT_D 3 Port pin PD PDL_IO PORT_1 4 PortpinP1 PDL_IO PORT_7 4 Port pin P74 PDL_IO PORT_D 4 Port pin PD PDL IO PORT_7 5 Port pin P75 PDL_IO PORT_D 5 Port pin PDs PDL_IO PORT_2 0 PortpinP2o PDL_IO PORT_7 6 Port pin P76 PDL_IO PORT_D 6 Port pin PD PDL_IO_PORT_2 1 Port pin P2 PDL_IO_PORT_D 7 Port pin PD PDL_IO PORT 2 2 Portpin P22 PDL_ IO PORT 8 0 Port pin P85 PDL_IO PORT 2 3 PortpinP23 PDL_IO PORT 8 1 Port pin P8 PDL_IO_PORT_E_0 Port pin PEo PDL_IO PORT 2 4 Portpin P24 PDL_IO PORT 8 2 Port pin P82 PDL_IO PORT _E 1 Port pin PE PDL_IO PORT 2 5 Port pin P25 PDL_IO_PORT_E 2 Port
371. include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h uint16_t WDT_Status void func void Read the timer values R_WDT_Read amp WDT_Status i Rev 2 11 EN ESAS Page 229 of 418 RX63T Group 4 2 18 1 R_IWDT_Set Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Independent Watchdog Timer 4 Library Reference Configure the Independent Watchdog operation bool R_IWDT_Sei uint32_t data Configuration selection Select the operation of the Independent Watchdog timer and start it data Configure the timer options Use to separate each value Counter selection PDL_IWDT_TIMEOUT_1024 or PDL_IWDT_TIMEOUT_4096 or PDL_IWDT_TIMEOUT_8192 or PDL_IWDT_TIMEOUT_16384 The number of cycles of the selected clock before the reset occurs PDL_IWDT_CLOCK_OCO_1 or PDL_IWDT_CLOCK_OCO_16 or PDL_IWDT_CLOCK_OCO_32 or PDL_IWDT_CLOCK_OCO_64 or PDL_IWDT_CLOCK_OCO_ 128 or PDL_IWDT_CLOCK_OCO_ 256 Clock division ratio selection The IWDTCLK clock 1 16 32 64 128 or 256 Time out control PDL_IWDT_TIMEOUT_NMI or PDL_IWDT_TIMEOUT_RESET If the IWDT times out select if a Reset or an NMI Interrupt will be generated Window Start Position PDL_IWDT_WIN_START_25 or PDL_IWDT_WIN_STAR
372. ing PDL_BSC_ERROR_ILLEGAL_ADDRESS DISABLE or Disable or enable illegal PDL_BSC_ERROR_ILLEGAL_ADDRESS_ ENABLE address access detection PDL_BSC_ERROR_TIME_OUT_DISABLE or Disable or enable bus time out PDL_BSC_ERROR_TIME_OUT_ENABLE detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Set R_BSC_CreateArea R_BSC_Control If required call R_BSC_Set before using this function Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed External Bus is not valid on packages with 64 pin and 48 pin package Call this function after all calls of function R_BSC_CreateArea After calling this function use R_BSC_Control to start the external bus operation Multifunction Pin Control registers are modified by this function o o o Rev 2 11 EN ESAS Page 125 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h Bus error handle
373. ion Return value Category Reference Remarks Program example 4 Library Reference Update an interrupt register bool R_INTC_Write uint16_tdata1 Register selection uint8_t data2 Register value Write the new value to an interrupt register data1 The register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register or DTC Activation Enable register or PDL_INTC_REG_SWINTR Software interrupt activation register data2 The value to be written to the register True if the parameter is within range otherwise false Interrupt control None This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 69 Write 1 to the SWINTR register to generate a software interrupt request RPDL definitions tinclude r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set the IPL to 6 R_INTC_Write PDL_INTC_REG_IPL 6
374. ions To set multiple options at the same time use to separate each value The default settings are shown in bold Group selection PDL_ADC_12 CH_GROUP_A or Assign the channel to Group A PDL_ADC 12 CH GROUP_B or Group B e Value addition control PDL_ADC 12 CH_VALUE_ADDITION_DISABLE or Enable or disable value PDL_ADC 12 CH_VALUE_ADDITION_ENABLE addition e Double trigger control PDL_ADC_12_CH_DOUBLE_TRIGGER_DISABLE or Enable or disable double PDL_ADC 12 CH DOUBLE TRIGGER_ENABLE trigger e Sample and hold circuit control PDL_ADC_12 CH_SAMPLE_AND_HOLD_DISABLE or PDL_ADC_12 CH_SAMPLE_AND_HOLD_ENABLE Enable or disable sample and hold circuit For channels 0 1 and 2 only e Sampling time calculation PDL_ADC_12 CH_ADSSTR_CALCULATE or PDL_ADC_12 CH_ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR Programmale Gain Amplifer configuration Valid for Channel 0 1 and 2 only Valid for packages with 100 pins or more PDL ADC 12 CH GAIN DISABLE or PDL ADC 12 CH GAIN 2 000 or PDL ADC 12 CH GAIN 2 500 or PDL ADC 12 CH GAIN 3 077 or PDL ADC 12 CH GAIN 3 636 or PDL ADC 12 CH GAIN 4 000 or ratita om PDL ADC 12 CH GAIN 4 444 or peely e required PDL ADC 12 CH GAIN 5 000 or PDL ADC 12 CH GAIN 5 714 or PDL ADC 12 CH GAIN 6 667 or PDL
375. ions sissu iieiea asia a iiA A E aN E 361 SAA Watchdog IME a ll te lec do 362 5 15 Gompare Match TIME rd a a dada dnd 363 5 16 Independent Watchdog Timer oonoccccnniccccnnoncccnnnononccnnnncncnnnonecc cnn nnn rn 365 5 17 Serial Communication Interface cccecccceececeeeee cence ceeeeeceeeeeeeaeeeeaeeseeeeeseaeeesaaeseeeeeseeeesaeeseeeseeeeess 366 5 17 1 SCI Asynchronous Using Polling ooooconncnnnnncdnnnnnnnnnnnnncconnncccnnrccn crac rara 366 5 17 2 SCI Asynchronous Using INterruptS cooonnnccinncnnnnccnnnnccnnccnnncccorcc nn nrn cnn 368 5 17 3 SCI Asynchronous Using DMAC ccccncccinnccnnncccconcnnnnnnnnnnnnnnc cnn rre 370 5 17 4 Synchronous Transmission and Reception oooonncccinnccnnccnnnnccnnocnnanccnonrnnn nana corran rra 372 5 17 5 Synchronous Full Duplex Operation ooonnoccinncinnccnnnccnnnccnnnccnconcc nn narrar cc 374 5 17 6 SCI Reception in Asynchronous Multi Processor mode ooncccccccnnonicnocinnnccccorccnonrnc nn cnnancccnnns 377 5 17 7 SCI Transmission in Asynchronous Multi Processor MOG oooccconoccccconoconcconononcconnnonccnnnannccnnnos 379 5178 SEMIN SP MOG vimos ida adria 381 5 17 9 SGIIC Mode sc s ced hi ves ate Wieden Ladin id a te a ee 382 5 17 10 SCI in IIC Mode using DMAC occccncicinoccnnncccconnnnnnnnn arcano cnn rn rn 384 5 17 11 SClin HC Mode using DTC cece ceia a i adii aa aaa iai tad aiia 386 5 187 EC Bus gl i akc et nioa a a A tek a a rent a a a a A R 389 DAB Mast
376. ipherals R20UT2201EE0211 Rev 2 11 RENESAS Page 19 of 418 Sept 12 2014 RX63T Group 2 4 Interrupt Control Driver The driver functions support the use of the interrupt controller providing the following operations R20UT2201EE0211 Sept 12 2014 As 2 10 11 12 13 Selecting the applicable interrupt pins Configuration of an external interrupt signal for use Enabling use of the software interrupt Assigning an interrupt to be processed using the Fast Interrupt route Assigning handlers for the fixed exception interrupts Controlling an external interrupt input Reading the status of an external interrupt Reading an interrupt register Writing to an interrupt register Modifying an interrupt register Configuring a group of interrupt sources Controlling a group of interrupt sources Reading the status of a group of interrupt sources Rev 2 11 ENESAS 2 Driver Page 20 of 418 RX63T Group 2 Driver 2 5 1 O Port Driver The driver functions support the use of the I O port pins providing the following operations i Configuration for use 2 Reading the pin or port configuration 3 Modifying the pin or port configuration 4 Reading a pin or 8 bit port value 5 Writing to a pin or 8 bit port 6 Comparing a pin or 8 bit port with a supplied value 7 Modifying a pin or 8 bit port using a logical operation 8 Waiting until a pin or 8 bit port matches a supplied value
377. isable and or enable buffer operation using Compare match or Input capture PDL_GPT_BUFFER_CYCLE_STOP PDL GPT BUFFER CYCLE START Disable and or enable buffer operation using over under flow PDL_GPT_BUFFER_ADC_TRIG_STOP PDL GPT BUFFER ADC TRIG START Disable and or enable buffer operation using ADC start triggers PDL_GPT BUFFER DEAD TIME STOP PDL_GPT_BUFFER_DEAD_TIME_START Disable and or enable buffer operation using dead time up down compare match Forced buffer operation PDL_GPT_BUFFER_CMIC_FORCE Force a buffer transfer of registers GTCCRA and GTCCRB Rev 2 11 ENESAS Page 202 of 418 RX63T Group 4 Library Reference Description 2 3 e Write protection PDL_GPT_WRITE_ENABLE Allow writing to the channel registers PDL_GPT_WRITE_DISABLE Prevent writing to the channel registers e Count direction PDL_GPT_COUNT_DIRECTION_DOWN or PDL_GPT_COUNT_DIRECTION_UP Set the count direction PDL_GPT_ COUNT DIRECTION FORCE Forcibly set the count direction e Software negate control PDL_GPT_NEGATE_ON or PDL_GPT_NEGATE_OFF state If software negate control has been enabled in parameter data10 of R_GPT_CreateChanmnel control the negate Output protection temporary release control PDL_GPT_OUTPUT_PROTECTION_RELEASE or PDL_GPT OUTPUT PROTECTION RESTORE Release or restore the protected state of the GTIOCnB pin
378. ital Converter 1 R_ADC_10_Set Synopsis Select the I O pins for the 10 bit ADC Prototype bool R_ADC_10_Set uint16_t data ADC pin selection Description Select the I O pins for the10 bit ADC data 4 Library Reference Select the pin set options To set multiple options at the same time use to separate each value Pin selection PDL_ADC_10 PIN ANO P60 Select P60 for ANO PDL_ADC_10 PIN AN1 P61 Select P61 for AN1 PDL_ADC_10 PIN AN2 P62 Select P62 for AN2 PDL_ADC_10 PIN AN3 P63 Select P63 for AN3 PDL_ADC_10 PIN AN4 P64 Select P64 for AN4 PDL_ADC_10 PIN AN5 P65 Select P65 for AN5 PDL_ADC_10 PIN AN6 P50 Select P50 for AN6 PDL_ADC_10 PIN AN7 P51 Select P51 for AN7 PDL_ADC_10 PIN AN8 P52 Select P52 for AN8 PDL_ADC_10 PIN AN9Q P53 Select P53 for AN9 PDL_ADC_10 PIN AN10 P54 Select P54 for AN10 PDL_ADC_10 PIN AN11_ P55 Select P55 for AN11 PDL_ADC_10 PIN AN12 P56 Select P56 for AN12 PDL_ADC_10 PIN AN13 P57 Select P57 for AN13 PDL_ADC_10 PIN AN14 PCO Select PCO for AN14 PDL_ADC_10 PIN AN15 PC1 Select PC1 for AN15 PDL_ADC_10 PIN AN16 PC2 Select PC2 for AN16 PDL_ADC_10 PIN AN17_ PC3 Select PC3 for AN17 PDL_ADC_10 PIN AN18 PC4 Select PC4 for AN18 PDL_A
379. ith polling or interrupt mode automatically selected Transferring data in SPI mode with polling or interrupt mode automatically selected Transmitting data in IIC mode with polling or interrupt mode automatically selected Receiving data in IIC mode with polling or interrupt mode automatically selected Receiving the last byte of data in IIC mode 10 Control the channel operation 11 Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS Page 37 of 418 RX63T Group R20UT2201EE0211 2 Driver 2 22 12C Bus Interface Driver The driver functions support the use of the 12C module providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control 2 Disabling the module that is no longer required and enabling low power mode 3 Transmitting data in Master mode 4 Receiving data in Master mode 5 Completing the reception of data in Master mode 6 Monitoring the bus and handling the reception of data in Slave mode 7 Transmitting data in Slave mode 8 Control of the unit including bus lock up recovery support 9 Reading the status of the module Note The Clock Generation Circuit must be configured before configuring the 12C module Rev 2 11 EN ESAS Page 38 of 418 Sept 12 2014 RX63T Group R20UT2201EE021
380. ition e False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create False will be returned if the bus is busy due to another master on the bus e Channel 1 is supported on 120 pin 144 pin packages only RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Send 5 bytes to device 0x0A0 on channel 0 using polling R_IIC_MasterSend 0 PDL_NO_DATA Ox0A0 data_array 5 PDL_NO_FUNC 0 Rev 2 11 ENESAS Page 269 of 418 RX63T Group 4 Library Reference 4 R_IIC_MasterReceive Synopsis Prototype Description R20UT2201EE0211 Sept 12 2014 Read data from a slave device bool R_IIC_MasterReceive uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Receive threshold void func Callback function uint8_t data6 Interrupt priority level Read data over an 12C channel and store it data1 Select channel IICn where n 0 orn 1 Channel 1 is not available for device packages with 112 pins or less data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e Slave address size override Specify this
381. kages with 100 pins or more in b15 b8 b15 b14 b13 b12 b9 b8 User boot mode 0 0 Other 0 1 1 Selected For packages with 64 pins and 48 pins in b15 b8 b15 b8 0 b7 b5 b4 b1 b0 Endian mode MD pin level at release from reset 000b Big 0 0 Low 111b Little 1 High data2 The reset status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b14 b8 Start type 0 0 Cold 1 Warm b7 b6 b5 b4 b3 b2 bi bO Reset detection flags 0 not detected 1 detected Exit from deep Voltage monitor i E software standby Software WDT IWDT gt 1 0 1 Power on data3 Where the OFSO register contents shall be stored Specify PDL_NO_PTR if they are not required data4 Where the OFS1 register contents shall be stored Specify PDL_NO_PTR if they are not required Return value True Category MCU registers References None Remarks e Ifa reset status flag is set to 1 it shall be automatically cleared to 0 by this function R20UT2201EE0211 Rev 2 11 QEN ESAS Page 97 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t status Read the MCU status registers R_MCU_Get Status amp statu
382. l PDL_MTU3_BDCM_OPS_101 or PDL_MTU3_BDCM_OPS_110 or PDL_MTU3 BDCM_OPS 111 e Synchronous clearing control applies only to channel pair 6 and 7 Disable or enable clearing on channel PDL_MTU3_SYNC_CLEAR _TGRB2 DISABLE or PDL_MTU3_SYNC_CLEAR TGRB2 ENABLE A capture or compare PDL_MTU3_SYNC_CLEAR TGRA2 DISABLE or Bea ps alli ae PDL MTU3 SYNC CLEAR TGRA2 ENABLE a put cap p Disable or enable clearing on channel PDL_MTU3_SYNC_CLEAR_TGRB1_DISABLE or PDL MTU3 SYNC CLEAR TGRB1 ENABLE ci capture orcompare PDL_MTU3_SYNC_CLEAR TGRA1 DISABLE or a leal cil PDL MTU3 SYNC CLEAR TGRA1 ENABLE ktr putcap p PDL_MTU3_SYNC_CLEAR TGRDO DISABLE or ete ae gt pe ect PDL MTU3 SYNC CLEAR TGRDO ENABLE carers li p PDL_MTU3_ SYNC CLEAR TGRCO_ DISABLE or eee A PDL MTU3 SYNC CLEAR TGRCO ENABLE dl put cap p Disable or enable clearing on channel PDL_MTU3_SYNC_CLEAR_TGRBO_DISABLE or PDL MTU3 SYNC CLEAR TGRB0 ENABLE A capture or compare PDL_MTU3_SYNC_CLEAR_TGRAO DISABLE or ek i gai peeled oo PDL MTU3 SYNC CLEAR TGRAO ENABLE saat putcap p Rev 2 11 Page 172 of 418 ENESAS RX63T Group 4 Library Reference Description 4 6 output_control The phase output control settings to be modified All settings are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required Output enable control To appl
383. l 1 in to IIC mode and then a write to an IIC EEPROM using the DMAC PDL functions include r_pdl_sci h include r_pdl_cgc h include r_pdl_dmac h PDL device specific definitions include r_pdl_definitions h static void Callback void SCI IIC Channel define CHANNEL _SCI_IIC 1 IIC Slave address of EEPROM define SLAVE _ADDRESS 0xA0 Address in EEPROM where we will write a byte define EEPROM_ADDRESS 0x01 volatile bool data_sent false void main void Data Buffer volatile uint8_t IIC_Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set Channel 1 pin options R_SCI_Set CHANNEL SCI_IIC if defined DEVICE PACKAGE 64 PIN amp amp defined DEVICE_PACKAGI PDL_SCI_PIN_SCI1_SSCL1_PD5 PDL_SCI_PIN_SCI1_SSDA1_PD3 else PDL_SCI_PIN SCT1 SSCLI POS PDL_SCI_PIN SCII SSDAI P94 endif Y Configure the SCI IIC Channel R_SCI_Create CHANNEL _SCI_IIC PDL_SCI_SYNC PDL_SCI_IIC_MODE PDL_SCI_IIC_DELAY_SDA_20_21 9600 1 0 Setup date to write to EEPROM Address in EEPROM TIC_Buffer 0 EPROM_ADDRESS Data to store in EEPROM IIC_Buffer 1 1 IIC_Buffer 2 TIC_Buffer 3 3 _ TIC_Buffer 4
384. l Serial Bus Watchdog Timer All trademarks and registered trademarks are the property of their respective owners R20UT2201EE0211 Rev 2 11 RENESAS Page 16 of 418 Sept 12 2014 RX63T Group 2 Driver 2 Driver 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and controlling the interrupt priority 3 1 0 Port These driver functions are used to configure the I O pins and provide data read write compare and modify Operations 4 Port Function These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for configuring the MCU operation 6 Voltage Detection Circuit These driver functions are used for configuring the low voltage detection response 7 Clock Frequency Accuracy Measurement Circuit These driver functions are used for configuring and controlling the clock frequency accuracy measurement circuit 8 Low Power Consumption These driver functions are used f
385. l buses d ata Bus priority control If multiple selections are required use to separate each selection The default settings are shown in bold Bus to be accessed Priority PDL_BSC_PRIORITY_RAM_MB2 or PDL_BSC_PRIORITY_RAM_CPU RAM PDL_BSC_PRIORITY_ROM_MB2 or PDL_BSC_PRIORITY_ROM_CPU ROM Fixed to internal main bus 2 or toggled with the CPU bus PDL_BSC_ PRIORITY PB1_MB2 or PDL_BSC_PRIORITY_PB1_MB1 Peripheral 1 PDL_BSC_PRIORITY_PB23_MB2 or PDL_BSC_PRIORITY_PB23_MB1 Peripheral 2 and 3 PDL_BSC_PRIORITY_PB45_MB2 or PDL_BSC_PRIORITY_PB45_MB1 Peripheral 4 and 5 PDL_BSC_PRIORITY_PB6_MB2 or PDL_BSC_PRIORITY_PB6_MB1 Peripheral 6 Fixed to internal main bus 2 or toggled with internal main bus 1 PDL_BSC_PRIORITY_EB_MB2 or PDL_BSC_PRIORITY_EB_MB1 External Fixed to external main bus 2 or toggled with external main bus 1 True if all parameters are valid and exclusive otherwise false Bus Controller None If it is necessary to call this function call it once only Ensure that both the DTC and DMAC are stopped External Bus is not valid on packages with 64 pin and 48 pin package RPDL definitions tinclude r_pdl_bsc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Give internal main bus 1 priority access to th bus 1 Rev 2 11 R_BSC_Set PDL_BSC_PRIORITY_PB23
386. l with the suffix DS can also be used to exit from Deep Software Standby mode Please refer to the Low Power Consumption section for details Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Select P10 for IRQO P11 for IRQ1 and P70 for IRQ5 R_INTC_SetExtInterrupt PDL_INTC_IRQO_P10 PDL_INTC_IRO1_P11 PDL_INTC_IRO5_P70 R20UT2201EE0211 Rev 2 11 RENESAS Page 57 of 418 Sept 12 2014 RX63T Group 2 Synopsis Prototype b Description 1 2 R20UT2201EE0211 Sept 12 2014 R_INTC_CreateExtInterrupt ool R_INTC_CreateExtinterrupt uint8_t data1 uint32_t data2 void func uint8_t data3 data1 Choose the interrupt signal to be configured IRQn n 0 to 5 for 64 and 48 pin package n 0 to 7 for 144 120 112 and 100 pin package interrupt pin or NMI interrupt pin 4 Library Reference Configure an external interrupt signal Signal selection Configuration Callback function Interrupt priority level Sets the specified interrupt detection and control PDL_INTC_IRQn or PDL_INTC_NMI data2 Choose the settings If multiple selections are required use to separate each selection The default settings are shown in bold Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_D
387. ld Specify PDL_NO_DATA to use the defaults e Input capture compare match control for register TGRU PDL_MTU3_U_CM or Compare match PDL_MTU3_U_IC_RISING_EDGE or PDL_MTU3_U_IC_FALLING_EDGE or PDL_MTU3_U_IC PDL_MTU3_U_IC PDL_MTU3_U_IC PWM PWM PWM LOW_BOTH or Input capture at MTICnU rising edge Input capture at MTICnU falling edge PDL_MTU3_U IC _BOTH_EDGES or Input capture at MTICnU both edges LOW_TROUGH or LOW_CREST or Input capture at trough crest or both for low pulse width measurement PDL_MTU3_U_IC PDL_MTU3_U_IC PWM PWM HIGH_TROUGH or HIGH_CREST or Input capture at trough crest or PDL_MTU3_U_IC_PWM_HIGH BOTH both for high pulse width measurement Rev 2 11 EN ESAS Page 162 of 418 RX63T Group Description 8 9 4 Library Reference Input capture compare match control for register TGRV PDL_MTU3_V_CM or Compare match PDL_MTU3_V_IC_RISING_EDGE or PDL_MTU3_V_IC_FALLING_EDGE or Input capture at MTICnV rising edge Input capture at MTICNV falling edge PDL_MTU3_V_IC_BOTH_EDGES or Input capture at MTICnV both edges PDL_MTU3_V_IC_PWM_LOW_TROUGH or Input capture at trough PDL_MTU3_V_IC_PWM_LOW_CREST or crest or PDL_MTU3_V_IC_PWM_LOW_BOTH or both for low pulse width measurement PDL_MTU3_V_IC_PWM_HIGH_TROUGH or Input capture at trough PDL_MTU3_V_IC_PWM_HIGH_CREST or crest or PDL_MT
388. le or enable the clock output can be used while PDL_SCI_GSM_SCK_START GSM mode is enabled data2 IIC Mode only Control the channel e Stop condition generation PDL_SCI_IIC_STOP A stop will be output on the bus e Clock Synchronisation Disable or enable the IIC clock PDL_SCI_IIC_CLOCK_SYNC_DISABLE or synchronisation PDL_SCI_IIC_CLOCK_SYNC_ENABLE Note Clock synchronisation is enabled by default as required for normal operation True if all parameters are valid otherwise false Category SCI Reference Remarks R20UT2201EE0211 Rev 2 11 EN ESAS Page 258 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Terminate SCI reception on channel 0 R_SCI_Control 0 PDL_SCI_STOP_RX R20UT2201EE0211 Rev 2 11 EN ESAS Page 259 of 418 Sept 12 2014 RX63T Group 4 Library Reference 11 R_SCI_GetStatus Synopsis Check the status of an SCI channel Prototype bool R_SCI_GetStatus uint8_t data1 Channel selection uint8_t data2 Status flags uint8_t data3 Last byte received uint16_t data4 Bytes transmitted uint16_t data5 Bytes received Description Acquires the channel status and the byte counts data1 The channel number n
389. lect the respective output pin PDL_SPI_PIN_SSLO_LOW or Select active low or active high PDL_SPI_PIN_SSLO_HIGH or for output signal SSLO PDL_SPI_PIN_SSL1_LOW or Select active low or active high PDL_SPI_PIN_SSL1_HIGH or for output signal SSL1 PDL_SPI_PIN_SSL2_ LOW or Select active low or active high PDL_SPI_PIN_SSL2 HIGH or for output signal SSL2 PDL_SPI_PIN_SSL3_LOW or Select active low or active high PDL_SPI_PIN_SSL3_HIGH or for output signal SSL3 PDL_SPI_PIN_MOSI_IDLE_LAST or Em PDL SPI PIN MOSI IDLE LOW or o output state when no SSLn pin is PDL_SPI_PIN_MOSI_IDLE_HIGH Rev 2 11 EN ESAS Page 281 of 418 RX63T Group Description 2 3 R20UT2201EE0211 Sept 12 2014 data3 Configure the data format If multiple selections are required use to separate each selection The default settings are shown in bold Buffer size 4 Library Reference PDL_SPI_BUFFER_64 or PDL_SPI_BUFFER_128 Select a buffer size of 64 bits up to four 16 bit frames or 128 bits up to four 32 bit frames Frame configuration selection refer to Table 32 4 in the hardware manual Selection Number of command Number of transfer frames Number of frames in each command transfers transfer PDL SPI FRAME 1 1or PDL SPI FRAME 1 2or PDL SPI FRAME 1 3or PDL SPI FRAME 1 40r PDL SPI FRAME 2 1 or PDL SPI FRAME 2 2or PDL SPI FRAME 3 or PDL SPI FRAME 4 or PDL_SPI FRAME
390. ll enabled frames once R_SPI_Transfer 0 PDL_NO_DATA transmit_data receive_data 1 PDL_NO_FUNC 0 PDL_NO_FUNC 0 Rev 2 11 EN ESAS Page 288 of 418 RX63T Group 4 Library Reference 6 R_SPI_Control Synopsis Prototype Description Return value Category R20UT2201EE0211 Sept 12 2014 Control an SPI channel bool R_SPI_Control uint8_t data1 Channel selection uint8_t data2 Control options uint32_tdata3 Extended timing control Modify the operation of the selected SPI channel data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Control the channel If multiple selections are required use to separate each selection All items are optional Specify PDL_NO_DATA if not required e Channel control PDL_SPI_DISABLE Disable and partially initialise the SPI channel e Loopback control PDL_SPI_LOOPBACK_DISABLE or PDL_SPI_LOOPBACK_DIRECT or PDL_SPI_LOOPBACK_REVERSED Disable or enable loopback in direct or reversed mode data3 Extended timing control optional All items apply only to Master mode Specify PDL_NO_DATA if not required If multiple selections are required use to separate each selection Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or
391. ll parameters are valid and exclusive otherwise false Data Transfer Controller Rev 2 11 EN ESAS Page 150 of 418 RX63T Group 4 Library Reference Reference R_DTC_Create Remarks This function must be called in order to start the DTC R_DTC_Create must be called at least once before starting the DTC Start the DTC before generating a transfer trigger Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA y Update the parameters for CMTO triggered transfers R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDATE_COUNT dtc_cmt0_transfer_data PDL_NO_PTR void 0x0000BBOO 100 PDL_NO_DATA R20UT2201EE0211 Rev 2 11 AS Page 151 of 418 Sept 12 2014 RENES RX63T Group 4 Library Reference 5 R_DTC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Check the status of the Data Transfer Controller bool R_DTC_GetStatus uint32_t data1 Transfer data start address uint16_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32
392. lues for channel 1 gpt_l_control_parameters data4 OxFFDD gpt_l_control_parameters data6 0x0020 Load the register values and start channel 1 R_GPT_ControlChannel 1 PDL_GPT_STOP PDL_GPT_START PDL_GPT_REGISTER_COUNTER PDL_GPT_REGISTER_B amp gpt_l_control_parameters ztENESAS Page 205 of 418 RX63T Group 4 Library Reference 6 R_GPT_ControlUnit Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Control the GPT unit bool R_GPT_ControlUnit uint8_t data1 Unit selection uint32_t data2 Control options uint16_t data3 Clock positive tolerance uint16_tdata4 Clock negative tolerance Modify the timer unit registers data1 The unit number n where n 0 for 64 and 48 pin packages n 0 1 for 144 120 112 100 pin packages data2 The unit settings to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop PDL_GPT_STOP_CH_0 PDL_GPT_STOP CH 1 Stop the count operation for the selected channels PDL_GPT_STOP_CH_2 in unit O The stop operation will be simultaneous PDL_GPT_STOP_CH_3 PDL_GPT_STOP_CH 4 PDL_GPT_STOP_CH_5 Stop the count operation for the selected channels PD
393. meters being evaluated more than once do not use operators or function calls within the RPDL API parameter list R20UT2201EE0211 Rev 2 11 RENESAS Page 49 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 2 1 Clock Generation Circuit 1 R_CGC_Set Synopsis Configure the clock generation circuit Prototype Description 1 2 bool R_CGC_Set uint8_t data1 Clock selection uint32_t data2 Configuration Options double data3 Clock frequency double data4 System clock frequency double data5 Peripheral module clock A frequency double data6 Peripheral module clock B frequency double data7 Peripheral module clock C frequency double data8 Peripheral module clock D frequency double data9 Flash interface clock frequency double data10 External bus clock frequency double data11 USB clock frequency Set a clock source frequencies and options data1 Clock source selection e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK_PLL or Phase locked loop PLL circuit or IWDT dedicated PDL_CGC_CLK_IWDTLOCO low speed clock on chip oscillator IWDTLOCO data2 Configuration settings BCLK pin output control ignored if the device package does not support the external bus PDL_CGC_BCLK_DIV_1 or Output the external bus clock BCLK PDL_CGC_
394. modified If multiple selections are required use to separate each selection PDL_INTC_GRPn_ALL can be used to specify all applicable selections e Group 0 selections PDL_INTC_GRPO_ERS1 Error on CAN channel 1 e Group 12 selections PDL_INTC_GRP12_ERIO PDL_INTC_GRP12_ERI1 Reception error on SCI channels 0 1 2 3 or 12 PDL_INTC_GRP12_ERI2 Note SCI channel 2 and 3 are not available for 64 and 48 pin PDL_INTC_GRP12_ERI3 packages PDL_INTC_GRP12_ERI12 PDL_INTC_GRP12_SPEIO Error on SPI channel 0 or 1 PDL_INTC_GRP12_SPEI1 Note SPI channel 1 is not available for 64 and 48 pin packages False if the group number is invalid otherwise true Interrupt control R_INTC_CreateGroup Do not use this function if RPDL functions will be used to control the applicable peripheral Call R_INTC_CreateGroup before calling this function Group 12 interrupts use level detection so clearing must be done by clearing the source of the interrupt Rev 2 11 ENESAS Page 77 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the interrupt for SCI channel 0 R_INTC_ControlGroup 12 PDL_INTC_GROUP_DISABLI PDL_INTC_GRP12_ERIO aa 3 Enable all of the Group 12 interrupt sources
395. n Channel 0 will copy the string Renesas RX63T into the destination area when a falling edge occurs on pin IRQO Channel 1 will copy the string Hello World into the destination area as soon as it is enabled Notes IRQO is connected to SW1 in the RSK press SW1 to generate IRQO trigger When the transfer has completed LEDO s state is inverted PDL functions and definitions include r_pdl_dmac h include r_pdl_intc h include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Callback function prototype void DMACO_transfer_end_handler void Data source and destination declarations const char source_string_1 Renesas RX63T const char source_string_2 Hello World volatile uint8_t destination_string_1 volatile uint8_t destination_string_2 void main void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint16_t TransferCount uint16_t SizeCount Set the CPU s Interrupt Priority Level to 0 INTC_Write PDL_INTC_REG_IPL 0 y Enable control of LED using LEDO to monitor R_IO_PORT_Set PDL_IO_PORT_ PDL_IO_POR Configure channel 0 R_DMAC_Create 0 PDL_DMAC_BLOCK PDL_DMAC_SOURC ESS_PLUS PDL_DMAC_DESTINATION_ADDRESS_PL PDL_DMAC_SIZE_8 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_IROO source_string_l
396. ncinnccnnccnnononnocnnnncnnancccnnrn nono cnn nnc rca cn rara rca 42 2 27 10 bit Digital to Analog Converter Driver oocconnncinnccnnncccnocccnnocnnnncnnn acc rn cn narran cnn rr cnn rra 43 2 28 Data Operation Circula reaa a T aaa aa gee arara a a a r a a cate a aa aAa aa aa aaa aa terns techincal 44 Jypesand deM ONS a ae a a a a pas 45 Si Dalai DOS e A A A 45 3 27 General defintiONS3 id A A winged aes 45 S24 POLENO UNC e rate odo Ahm 45 322 PD NO POR acia dial olaaa 45 32302 PDLNO DATA comodidad lt terete 45 324 PDE MCU GROUP coincidir 45 325o PDE VERSION ocio a ea ed e a adnata e ath a Aa T 45 3 2 6 BIVGSTiNINIONS a tere eraa a atere aae adaa a a aaaea Gna a e a e a T 45 Library Reference a a a ai r e a niaaa ieee 46 4 1 API List by Peripheral Function oooniocincccnnncconnncnnncccnnnnccnonccn ronca 46 4 2 Description of Each AP is areenan A eet ne aiden cee 49 4 2 1 Clock Generation Circulo casada 50 A O Oo 50 2 RICOCC OMA e O dd 53 3 R CGC Gets US e do a a led 55 422 Interrupt Gontrol Unit aa add 56 1 RUINTESetExtAterruptinarnioni aa iaa 56 2 R_INTC_CreateExtlnterrupt iscan a aa aia aae aaa aaa iada aiaa iia 58 3 R_INTC_CreateSoftwarelnterrupt cccccecceeeeeeeceeeeeeeeeeeaaeeeeaeeceeeecaaeeeeaaeeseeeeseaeeesaeeesaeseeneesaas 60 4 RP_INTC_CreateFastinterrupt ccccccccccccseeeceeeeeeeeeeeceeeeeeaaeseeaeeeceeeecaaeeseaaesseneeseaeeesaeseeaaesseneesaas 61 5 R_INTC_CreateExceptionH
397. ndow Start Position PDL_WDT_WIN_START_25 or PDL_WDT_WIN_START_50 or PDL_WDT_WIN_START_75 or PDL_WDT_WIN START 100 The window start position specified as a percent of the down counter 0 is when the downcounter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_WDT_WIN_END_0 or PDL_WDT_WIN_END_25 or PDL_WDT_WIN_END_50 or PDL_WDT WIN _END_75 The window end position specified as a percent of the down counter 0 is when the downcounter would underflow Hence specifying 0 is equivalent to no window end position True if all parameters are valid and exclusive otherwise false Watchdog Timer R_INTC_CreateExtInterrupt R_MCU_OFS Rev 2 11 ENESAS Page 226 of 418 RX63T Group Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference If using the Initial Setting Memory using R_MCU_OFS to enable the WDT from reset this function will have no effect If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for WDT The timing limits depend on the frequency of the peripheral module clock PCLKB nx cycles fieira Period nx cycles or Frequency PCLKB Where n 4 64 128 512 2048 or 8192 cycles 1024 4096 8192 16384 Example periods are given below for fecika 50MHz Time out cycles
398. nel TGRF_value For n 0 4 and 7 The register TGRF value Ignored for other channel TADCORA_value For n 4 and 7 The register TADCORA value TADCORB_value For n 4 and 7 The register TADCORB value TADCOBRA_value For n 4 and 7 The register TADCOBRA value R20UT2201EE0211 Sept 12 2014 Rev 2 11 ENESAS Page 163 of 418 RX63T Group Description 9 9 Return value Category Reference R20UT2201EE0211 Sept 12 2014 4 Library Reference TADCOBRB_ value For n 4 and 7 The register TADCOBRB value func1 For n 5 The function to be called when a TGRA event occurs For n 5 The function to be called when a TGRU event occurs Specify PDL_NO_FUNC if not required func2 For n 5 The function to be called when a TGRB event occurs For n 5 The function to be called when a TGRV event occurs Specify PDL_NO_FUNC if not required func3 For n 0 3 4 6 and 7 The function to be called when a TGRC event occurs For n 5 The function to be called when a TGRW event occurs Specify PDL_NO_FUNC if not required func4 For n 0 3 4 6 and 7 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required interrupt_priority_1 For n A 7 The interrupt priority level for TGR A to D or U to W events For n 7 The interrupt priority level for TGRA and TGRB events See also interrupt_priority_3 Sel
399. nel Configure a GPT channel 4 R_GPT_Destroy Disable the GPT unit General PWM 5 R_GPT_ControlChannel Control a GPT channel Timer 6 R_GPT_ControlUnit Control the GPT unit 7 R_GPT_ReadChannel Read from GPT channel registers 8 R_GPT_ReadUnit Read the GPT unit flags 9 R_GPT_EdgeDelay Create Enable the PWM Edge Delay circuit 10 R_GPT_EdgeDelay_Control Control the PWM Edge Delay circuit 11 R_GPT_EdgeDelay_Destroy Disable the Edge Delay circuit 1 R_CMT_Create Configure a CMT channel Compare Match 2 R_CMT_CreateOneShot Configure a CMT channel as a one shot event Timer 3 R_CMT_Destroy Disable a CMT unit 4 R_CMT_Control Control CMT operation 5 R_CMT_Read Read CMT channel status and registers 1 R_WDT_Set Configure the Watchdog timer operation Watchdog Timer 2 R_WDT_Control Control the Watchdog operation 3 R_WDT_Read Read the Watchdog timer status and registers Independent 1 R_IWDT_Set Configure the Independent Watchdog operation Watchdog Timer 2 R_IWDT_Control Control the Independent Watchdog operation 3 R_IWDT_Read Read the watchdog timer status and counter 1 R_SCI_Set Configure the SCI pin selection 2 R_SCI Create SCI channel setup 3 R_SCI Destroy Shut down a SCI channel 4 R_SCI_Send Send a string of characters Serial 5 R_SCI_Receive Receive a string of characters Communication 6 R_SCI_SPI_Transfer Perform an SCI SPI transfer Interface 7 R_SCI_IIC_Write Perform an SCI IIC master write 8 R_SCI_IIC_Read Perform an SCI
400. nit R_GPT_ControlChannel R_GPT_ControlUnit R_GPT_CreateUnit should be called in advanced of this API Use R_GPT_ControlChannel to load the registers and start the timer If hardware start or stop control is enabled on a channel starting or stopping any channel using R_GPT_ControlChannel or R_GPT_ControlUnit may cause the channels that use hardware start or stop control to change state in error If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed A companion function R_GPT_Create_load_defaults can be used to load the default values into the structure Setting for channel 4 5 6 7 and unit 1 only available in 144 120 112 100 pin packages RPDL definitions tinclude r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void Allocate a copy of the structure R_GPT_Create_structure ch_parameters Load the defaults R_GPT_Create_load_defaults amp ch_parameters Set the non default options for channel 4 ch_parameters data2 PDL_GPT_MODE_SAW PDL_GPT_CLK_PCLK_DIV_1 R_GPT_CreateChannel 2 amp ch_parameters y Rev 2 11 EN ESAS Page 200 of 418 RX63T Group 4 Library Referenc
401. nitions include r_pdl_doc h RPDL device specific definitions include r_pdl_definitions h void func void R_DOC_Destroy R20UT2201EE0211 Rev 2 11 RENESAS Page 329 of 418 Sept 12 2014 RX63T Group 4 Library Reference 3 R_DOC_Control Synopsis Control the Data Operation Circuit Prototype bool R_DOC_Conirol uint8_t data1 Configuration uint16_t data2 Data Description Control the DOC Module data1 Control operation To set multiple options at the same time use to separate each value If no selection is made specify PDL_NO_DATA the control setting will be left unchanged e Operation Mode PDL_DOC_COMPARISON_MATCH or PDL_DOC_COMPARISON_MISMATCH or If required specify a new mode of operation to PDL_DOC_MODE_ADD or change to PDL_DOC_MODE_SUBTRACT DOC Fla Clear the DOC flag If this flag is set when interrupts are enabled an interrupt will be PDL_DOC_FLAG_CLEAR generated Note The DOC flag is automatically cleared when the callback function is called Interrupt control PDL_DOC_INTERRUPT_ENABLE or PDL_DOC_INTERRUPT_DISABLE Enable or disable the DOC interrupt Update the DOC data value PDL_DOC_DATA_ UPDATE Update the DOC with the value specified in data2 See data2 description for meaning data2 This meaning of this parameter depends upon the Operation Mode
402. nitions h void func void Configure RXD1 and TXD1 pins R_SCI_Set 1 PDL_SCI_PIN_SCI1_RXD1_PD5 PDL_SCI_PIN_SCI1_TXD1_PD3 Y ztENESAS Page 237 of 418 RX63T Group 2 R_SCI_Create Synopsis Prototype Description 1 4 Sept 12 2014 4 Library Reference SCI channel setup bool R_SCI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Bit rate or register value uint8_tdata4 Interrupt priority level uint8_t data5 Interrupt priority level Set up the selected SCI channel data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold e Operation mode PDL_SCI_ASYNC or Choose between Asynchronous PDL_SCI_SYNC or Clock synchronous includes SPI and IIC PDL_SCI_SMART or Smart Card Interface or PDL_SCI_ASYNC_MP Multi Processor Asynchronous operation Transmit Receive connections Not applicable in IIC Mode option will be ignored PDL_SCI_TX_CONNECTED or PDL_SCI TX_DISCONNECTED PDL_SCI_RX_CONNECTED or PDL_SCI_RX_DISCONNECTED The TXDn output is required not required The RXDn input is required not required Data transfer format Not applicable in
403. nnel 0 for dual waveform A and B output R_GPT_CreateChannel 0 amp ch_create_parameters di Set the register values for channel 0 gpt_ch_control_parameters data4 0x0000 gpt_ch_control_parameters data5 0x2222 gpt_ch_control_parameters data6 OxBBBB gpt_ch_control_parameters datall OxFFDD Load the register values and start channel 1 R_GPT_ControlChannel 0 PDL_GPT_START PDL_GPT_COUNT_DIRECTION_UP PDL_GPT_REGISTER_CYCLE PDL_GPT_REGISTER_COUNT PDL_GPT_REGISTER_A PDL_GPT_REGISTER_B amp gpt_ch_control_parameters Figure 5 15 Example of General PWM Timer Driver R20UT2201EE0211 Rev 2 11 RENESAS Page 360 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 13 Register Write Protection Figure 5 16 shows a usage example of Register Write Protection Peripheral driver function prototypes tinclude r_pdl_rwp h RPDL device specific definitions tinclude r_pdl_definitions h void main void uint8_t PRCR_value uint8_t PWPR_value Read the protection registers R_RWP_Get Status amp PRCR_value amp PWPR_value Y Enable access to the LVD registers R_RWP_Control PDL_RWP_ENABLE_LVD_WRITI Y Figure 5 16 Example of Register Write Protection R20UT2201EE0211 Rev 2 11 EN ESAS Page 361 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 14 Watchd
404. ns little endian 112 pins big endian 126 pins little endian 126 pins big endian 144 pins little endian 144 pins big endian NE Qwest NA pp 12 Please enter the path where you wish RPDL for RX63T to be installed Type the full path to the folder where you wish RPDL to be copied to and then press Enter NOTE To avoid a problem with long pathnames enclose the path in quotes The utility will create a folder in the location that you specified and copy the files into the new folder E pere e pape 5 EN C Windows system32 cmd exe Lo ae lease enter the path where you wish RPDL for RX63T to be installed WorkS pace My_Pro ject_folder reating the destination directory C WorkSpace My_Project_folder RPDL Copying the generic files opying the files for a 144 pin package with big endian support Finished Press any key to continue Press any key to close the window Copy folder ARPDL into the folder project workspace created Example C WorkSpace rpdl_lib_test rpdl_lib_test R20UT2201EE0211 Rev 2 11 Sept 12 2014 Page 4 of 418 RX63T Group 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to show the included file directories Click on the Add button In the Add include file directory window enter the details as shown Add include fil
405. ns h void func void Enable direct loopback mode R_SPI_Control 0 PDL_SPI_LOOPBACK_DIRECT PDL_NO_DATA Change the extended timings R_SPI_Control 0 PDL_NO_DATA PDL_SPI_CLOCK_DELAY_8 PDL_SPI_SSL_DELAY_5 R20UT2201EE0211 Rev 2 11 RENESAS Page 290 of 418 Sept 12 2014 RX63T Group 4 Library Reference 7 R_SPIGetStatus Synopsis Check the status of an SPI channel Prototype bool R_SPI_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags uint16_t data3 Sequence count Description Acquires the SPI channel status data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b14 b12 b11 b10 b8 0 Error command 0 Command pointer b7 b6 b5 b4 b3 b2 b1 bO Receive Transmit Overrun buffer o buffer Parity error Mode fault Bus state ertor 0 Empty O Full 0 No error 0 No fault 0 Idle 0 No error 1 Full 1 Empty 1 Detected 1 Detected 1 Active 1 Detected data3 The storage location for the number of sequence loops that have been completed in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are
406. nt uint16_t data6 Repeat or Block size int32_t data7 Address offset uint32_t data8 Source address extended repeat area uint32_t data9 Destination address extended repeat area Description 1 2 Change the state of a DMA controller channel data1 The channel number n where n 0 to 3 data2 Control the channel operation If multiple selections are required use to separate each selection e Enable suspend control PDL_DMAC_ENABLE PDL_DMAC_SUSPEND Enable re enable DMA transfers Suspend DMA transfers e Software trigger control PDL_DMAC_START or PDL_DMAC_START_RUN or PDL_DMAC_STOP Start a DMA transfer Start DMA transfers until stopped Stop software triggered transfers e Transfer end interrupt flag control PDL_DMAC_CLEAR_DTIF Clear the Transfer End flag PDL_DMAC_CLEAR_ESIF Clear the Transfer Escape End flag The values to be modified Source address using parameter R20UT2201EE0211 Sept 12 2014 Rev 2 11 PDL_DMAC_UPDATE_SOURCE data3 PDL_DMAC_UPDATE_DESTINATION Destination address using parameter data4 PDL_DMAC_UPDATE_COUNT Transfer count using parameter data5 PDL_DMAC_UPDATE_SIZE Repeat or Block size using parameter data6 PDL_DMAC_UPDATE_OFFSET Address offset using parameter data7 PDL_DMAC_UPDATE_REPEAT_SOURCE Source address extended repeat area using parameter data8
407. nt32_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint32_t data7 uint32_t data8 Set up the selected I2C channel data1 4 Library Reference Channel selection Channel configuration Detection configuration Slave address Slave address Slave address Transfer rate control Rise and fall time correction Select channel IICn where n 0 or n 1 Channel 1 is not available for device packages with 112 pins or less data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold e Bus mode selection PDL_IIC_MODE_IIC or PDL_IIC_MODE_SMBUS or Choose between 12C Bus or SMBus mode Internal reference clock PDL_IIC_INT_PCLK_DIV_1 or PDL_IIC_INT_PCLK_DIV_2 or PDL_IIC_INT_PCLK_DIV_4 or PDL_IIC_INT_PCLK_DIV_8 or PDL_IIC_INT_PCLK_DIV_16 or PDL_IIC_INT_PCLK_DIV_32 or PDL_IIC_INT_PCLK_DIV_64 or PDL_IIC_INT_PCLK_DIV_128 The reference clock source derived from PCLKB used inside the 12 module Timeout detection control PDL_IIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or PDL_IIC_TIMEOUT_BOTH Disable timeout detection or enable for SCL stuck at a low level high level or both low and high level Timeout mode PDL_IIC_TIMEOUT_LONG or PDL_IIC_TIMEOUT_SHORT Select 16 bit long or 14 bit short mode PDL
408. ntrol atestado ci dai 232 A e 233 Serial COMMUNICATION INterface ccoconcccoconnnncnnnonoooonononnnnnnnnononnnnnnnnnononononnnnnnnnnnnnnnnnnnnnnnaninanos 234 A e e A 234 EAN A 238 R SGL DESMEDIDA Adi ia idad 243 A A O 244 A A A A E A E E AEAT 247 ARS A A A ATE E A I 250 AA A 253 ASSCIAMO REA a aria aro did 255 R SC UC ReadLastByle cuicos ia cierren iaeiei andan tia dditedaaartesstdaseestaaastapadeasta Sanai ETEak 257 PSG Control A ATE AE E E A IT 258 A E CTE E EEE EA AT E E T 260 ESA o SEE TA EE TE E E OAE A E E 262 REE EY EEE E a do Les A I A e lle dd 262 PUE Des MOYA a 267 RBs MasterSend tt ln e o cole pec el ele e ast 268 RuG M ster ROCOV O a a aa a a a iaa Dd 270 RIG Mast rRec ivel stin Honana aera aia aa aieri aa aa aia aaea eaaa iian 272 RuG Slave MONO e A a Pc hdl Mist Wat tiie de 273 RBG SlaveSend REAA EEE A A E E dl EAE 275 REEN Ra AEE EE e AET T E ndo a dle 276 Am A EER A E T A 277 Serial Peripheral Interface csccccccceceeeeeeneeeeeneeceaeeeeaaeeeeaeeseeeeeceaeeeaaeseeaeesseeeseaeeesaaesseneessaees 279 FRAO a EET EEE ci A A A E AN T AE E A 279 RESP A CLEE E I E A e o AE AT eat A EA 281 RSF E DESTO an A A A E E thas 284 R SPI COMMANA a a a e a e card de eet e tee e eee 285 RESP Transfer nata a a aa a de A a eA wilt aa 287 ReSPIControllst c nastier AA Ge nee Aes 289 ReSPIlGetStats ii aa eels els Beh ei el eee I aes 291 CRG calctilatorccAcumcix kaneis A ee es 292 RECREO A Nove ene AA ee I es 292 R CRC
409. number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value e Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source e Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will be ignored if a value change is not requested Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in the selected register uint16_t True if all parameters are valid and exclusive otherwise false Compare Match Timer R_CMT_Create R_CMT_Create must be used first to configure the channel The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call To avoid register access conflicts or invalid calls to the callback function use this method when changing any value Ifthe CMCNT register value is changed to the same value as the CMCOR register the CMCNT register will be set to 0 Rev 2 11 EN ESAS Page 223 of 418 RX63T Group 4 Library Reference
410. o configure and start the IWDT If the IWDTCLK frequency division is 16 or more avoid selecting PDL_IWDT_CLOCK_OCO 1 c Use this function to initialise and start the IWDTCLK counter e Setting for channel 4 5 6 7 only available in 144 120 112 100 pin packages RPDL definitions tinclude r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h void func void Stop clear and re start channels 0 and 1 simultaneously R_GPT_ControlUnit 0 PDL_GPT_STOP_CH_0 PDL_GPT_STOP_CH_1 PDL_GPT_CLEAR_CH_0 PDL_GP EAR_CH1 PDL_GPT_START_CH_0 PDL_GPT_START_CH_1 PDL_NO_DATA PDL_NO_DATA Q i Update the IWDTCLK count deviation limits to 10 amp 20 R_GPT_ControlUnit 0 PDL_GPT_IWDTCLK_DEVIATION_TOLERANCE 10 20 Rev 2 11 EN ESAS Page 207 of 418 RX63T Group 4 Library Reference 7 R_GPT_ReadChannel Synopsis Prototype Description 1 2 Read from GPT channel registers bool R_GPT_ReadChannel uint8_t data1 Channel selection uint16_t data2 Flag storage location uint16_t data3 Timer counter register storage location uint16_t data4 General register A storage location uint16_t data5 General register B storage location uint16_t data6 General register C storage location uint16_t data7 General register D st
411. o use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is transmitted e ID transmission control valid only in Multi processor mode Transmit the upper byte as the ID byte PRESO Sere The valid ID range is 0 to 255 data3 The start address of the data to be sent Specify PDL_NO_PTR for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data4 For sending binary data set this to the number of bytes to be sent The valid range is 1 to 65535 Set this to 0 for transmission of a null terminated character string For the ID cycle in Multi processor mode specify 0 If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Use R_SCI_Control to terminate this operation early R_SCI_GetStatus can be used to find out how many characters have been transmitted Transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been sent Interrupts The function to be called when the last byte has been sent DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback f
412. og Timer Here the watchdog is configured to generate an NMI interrupt when the counter underflows Notice how the NMI is enabled for WDT interrupts Peripheral driver function prototypes include r_pdl_intc h include r_pdl_wdt h PDL device specific definitions include r_pdl_definitions h static void NMI_handler void void main void Enable the NMI interrupt for WDT R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_WDT_ENABLE NMI_handler 7 Configure WDT with a 25 to 75 window no reset hence generate NMI R_WDT_Set PDL_WDT_TIMEOUT_1024 PDL_WDT_PCLK_DIV_2048 PDL_WDT_WIN_START_75 PDL_WDT_WIN_END_25 PDL_WDT_TIMEOUT_NMI Y Main program loop while 1 Refresh the watchdog R_WDT_Control PDL_WDT_RESET_COUNTE i User code is omitted here static void NMI_handler void uint16_t Status Read the WDT status R_WDT_Read Status Has an underflow occurred Status BIT_14 0x0u Handle the watchdog underflow here Has a refresh error occurred Status BIT_15 0x0u Handle the watchdog refesh error here Figure 5 17 Example of Watchdog Timer use R20UT2201EE0211 Rev 2 11 AS Page 362 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples 5 15 Compare Match Timer Figure 5 18 shows an example of Compare Match Timer usage
413. oid Set flag data_received true Figure 5 23 Example of Synchronous Transmission and Reception code R20UT2201EE0211 Rev 2 11 RENESAS Page 373 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 5 Synchronous Full Duplex Operation This shows the configuration of SCI channel 1 as a clock master with both Rx and Tx data pins enabled Data is received at the same time as data is transmitted Peripheral driver function prototypes include r_pdl _sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h include lt stddef h gt include lt string h gt For testing connect 2 channels to each other Rx to Tx and clock to clock 1 SCIO RXDO P24 TXDO P30 SCKO P23 Generates clock MASTER 2 SCI1 RXD1 P93 TXD1 P94 SCK1 Uses external clock SLAVE P92 SCI channel selection define MASTER _CHANNEL 1 define SLAVE _CHANNEL 0 define DATA_LENGTH 5 Rx complete flag volatile uint8_t data_received volatile uint8_t data_sent Callback function prototype static void SCI_Rx_Callback void static void SCI_Tx_Callback void NOTE Before adding to the API manual remove the slave side void main void volatile uint8_t rx_buffer DATA_LENGTH 0 0 0 0 0 Initialise the system clocks NOTE The code to initialise the system clock using
414. oid Disable the IRQ1 interrupt pin and clear the flag R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INTC_DISABLE PDL_INTC_CLEAR_IR_FLAG R20UT2201EE0211 Rev 2 11 RENESAS Page 67 of 418 Sept 12 2014 RX63T Group 4 Library Reference 7 R_INTC_GetExtinterruptStatus Synopsis Prototype Description Return value Category Reference Read the external interrupt status bool R_INTC_GetExtinterruptStatus uint8_t data1 Pin selection uint8_t data2 A pointer to the buffer where the status data shall be stored Acquire the status for the specified external interrupt data1 Choose the interrupt pin to be checked PDL_INTC_IRQn or IRQn n 0 to 5 for 64 and 48 pin package n 0 to 7 PDL_INTC_NMI for 144 120 112 and 100 pin package interrupt pin or NMI interrupt pin data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 bi bO Detection condition Current level Status 00 Low level 0 01 Falling edge 0 Low 0 Not detected 10 Rising edge 1 High 1 Detected 11 Both edges For the NMI interrupt b7 b6 b5 b4 b3 b2 b1 bO Other interrupt request NMI pin Underflow Oscillation Current Detection LVD2 VP wor Wor stop level condition Request status 0 Not detected 0 Low 0 Falling 0 Not detected 1 Detected 1
415. olAll R_ADC_10_CreateChannelAll R_ADC_10_CreateUnitAll R_ADC_10_DestroyAll R_ADC_10_ReadAll R_ADC_10_SetAll ADC_10 Added detail for R_ADC_10_ControlAll RK_ADC_10_CreateChannelAll R_ADC_10_CreateUnitAll R_ADC_10_DestroyAll R_ADC_10_ReadAll R_ADC_10_SetAll ADC_10 Added the program example R_DMAC_Create Added trigger source support larger pin packages SPI Add channel 1 support to RSPI and new port allocation of RSPIO SPI Correct pin name of RSPI channel 0 R_LPC_Create Added IRQ6 DS pin and IRQ7 DS pin interrupt selection Added output port retention control function R_LPC_GetStatus Added interrupt flags of IRQ6 DS and IRQ7 DS Revised software standby mode example R_CGC_Set Added remark for UCLK and changed setting range for UCLK R_CGC_Set Update program example IO_PORT remove option PDL_IO_PORT_PULL_UP_ON PDL_IO_PORT_PULL_UP_OFF and PDL_IO_PORT_PULL_UP BSC modified the API R_BSC_Set R_BSC_Create R_BSC_CreateArea R_BSC_Destroy R_BSC_Control CAC add option PDL_CAC_CACREF_PORT_0_0 AZOUT2201EE0211 Rev211 RENESAS O Revisionhistoy 2 ESAS Revision history 2 RX63T Group Revision History Description Summary PO Summary O CGC Update usage example 66 R_INTC_SetExtInterrupt Add pins for high pin packages 180 188 POE3 Added settings of POE4 POE10 E4 POE12 GPT67 and MTU67 into R_POE_Set R_POE Create R_POE Control R POE GetStatus 64 R_INTC_CreateFastinterrupt Update in
416. omplementary PWM modes PDL_MTU3_OUT_TOGGLE_ENABLE or Enable or disable toggle output synchronised PDL_MTU3 OUT TOGGLE_DISABLE with the PWM cycle R20UT2201EE0211 Rev 2 11 RENESAS Page 173 of 418 Sept 12 2014 RX63T Group Description 5 6 R20UT2201EE0211 Sept 12 2014 buffer_control The phase output buffer control settings to be modified All settings are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required 4 Library Reference Output level buffer control applies only to reset synchronised or complementary PWM modes Set the output control to be transferred to the output PDL_MTU3_OUT_BUFFER_P_PHASE_1_LOW or Buffer control for MTIOC3B or PDL_MTU3 OUT _BUFFER_P_PHASE_1_HIGH MTIOC6B PDL_MTU3_OUT_BUFFER_N_PHASE_1_LOW or Buffer control for MTIOC3D or PDL_MTU3_OUT_BUFFER_N_PHASE 1 HIGH MTIOC6D PDL_MTU3_OUT_BUFFER_P_PHASE_2 LOW or Buffer control for MTIOC4A or PDL_MTU3_OUT_BUFFER_P_PHASE 2 HIGH MTIOC7A PDL_MTU3_OUT_BUFFER_N_PHASE_2 LOW or Buffer control for MTIOC4C or PDL_MTU3_OUT_BUFFER_N_PHASE_2 HIGH MTIOC7C PDL_MTU3_OUT_BUFFER_P_PHASE_3 LOW or Buffer control for MTIOC4B or PDL_MTU3_OUT_BUFFER_P_PHASE_3_HIGH MTIOC7B PDL_MTU3_OUT_BUFFER_N_PHASE_3 LOW or Buffer control for MTIOC4D or PDL_MTU3_OUT_BUFFER_N_PHASE _3 HIGH MTIOC7D Set the transfer timing In complemen
417. on it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to the usage example in Section 5 17 7 For ID cycle the DMAC DTC trigger control and the callback function will be ignored Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_Write When using interrupts to manage the transfer if the channel is operating in synchronous mode transmit only and with an external clock the TXD pin may need to be held active for longer up to half a bit period to avoid violating the data hold time for the receiving device If a delay is required the user should refer to the comments in the Transmit End interrupt processing routines in the file interrupt_SCl c in the i_src folder and implement the delay in a way that is suitable for their application If using the DMAC or DTC this module does not know when the transmission has ended Therefore when it has completed the user must call the R_SCI_ Control function with option PDL_SCI_STOP_TX to manually disable the transmission If a callback function is specified and the interrupt priority level is zero this function will return false Rev 2 11 EN ESAS Page 245 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t d
418. onfigure an external interrupt signal 3 R_INTC_CreateSoftwarelnterrupt Enable use of the software interrupt 4 R_INTC_CreateFastinterrupt Assign handlers for the fixed vector interrupts 5 R_INTC_CreateExceptionHandlers Enable faster interrupt processing for one interrupt 6 R_INTC_ControlExtInterrupt External interrupt control Interrupt contro 7 R_INTC_GetExtInterruptStatus Read the external interrupt status unit 8 R_INTC_Read Read an interrupt register 9 R_INTC Write Update an interrupt register 10 R_INTC_Modify Modify an interrupt register 11 R_INTC_CreateGroup Configure an interrupt source group 12 R_INTC_ControlGroup Control an interrupt source group 13 R_INTC_GetStatusGroup Read the status of an interrupt Source group 1 R_IO_PORT_Set Configure an I O port 2 R_IO_PORT_ReadControl Read an I O port s control registers 3 R_IO_PORT_ModifyControl Modify an I O port s control registers 4 R_IO_PORT_Read Read data from an I O port 1 O port 5 R_IO_PORT_Write Write data to an l O port 6 R_IO_PORT_Compare Check the pin states on an I O port 7 R_IO_PORT_Modify Modify the pin states on an I O port 8 R_IO_PORT_ Wait Wait for a match on an I O port 9 R_IO_PORT_NotAvailable Configure I O port pins that are not available Multifunction Pin 1 R_MPC_Read Read a PFC register Controller 2 R_MPC_Write Write to a PFC register 3 R_MPC_Modify Modify a PFC register 1 R_MCU_Control Control the operation of the MCU MCU operation 2 R_MCU_GetStatus Rea
419. ontrol PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CGC_ Set R20UT2201EE0211 Rev 2 11 2tENESAS Page 218 of 418 Sept 12 2014 RX63T Group 4 Library Reference Remarks Function R_CGC_Set must be called with the current clock source selected before using this function e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Ensure that the timer channel is stopped before calling this function The timing limits depend on th
420. ontroller Reading the status flags and data transfer registers Rev 2 11 ENESAS Page 30 of 418 RX63T Group 2 Driver 2 15 Multi Function Timer Pulse Unit Driver The driver functions support the use of the eight 16 bit timers providing the following operations 1 Selection of the MTU pins for use 2 Configuration for use including e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer channel 5 Control of a timer unit 6 Reading the status flags and registers of a timer channel 7 Reading the status flags and registers of a timer unit Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT2201EE0211 Rev 2 11 AS Page 31 of 418 Sept 12 2014 RENES RX63T Group 2 16 Port Output Enable Driver The driver functions support the use of the Port Output module providing the following operations R20UT2201EE0211 Sept 12 2014 1 2 Configuring the pins for use Configuring the interrupts and callback functions Run time control of outputs interrupts and flags Checking the module status Rev 2 11 ENESAS 2 Driver Page 32 of 418 RX63T Group 2 Driver 2 17 General PWM Timer Driver The driver functions support the use of the eight 16 bit PWM timers providing the following operations 1 Selection of the G
421. oonnncinnnnnncccnnnconnoncnnnccnnancccnnrn nana nn cnn rana rana rca 13 1 33 Header TilS INClUSION miii polla NATAS 14 1 3 4 Header file Order cooocccnononnccconoccncnnonocnnnnonoancnnononnnnnonrnnnnnonornnnnnnocnnnnnnnrnnnnnnrrnnnnnarrnnnnnnennnnnnns 14 1 3 5 Recommended initialisation code o oocconnncccnnnocccccnnancccnononcccnnnoncc cnn non cn cnn nn cc cnn n nc cnn rca nc 14 tA DOCUMENT STUCIUTS ii a A A A la A ee 15 tS Acronyms and abbreviatiOns it a nad nde teat Md ee eee 16 DN o E AT 17 elie COVE WE A IAE ES AS AS cal atte otek NAS LOTA ati 17 22 Gontrol Functions summaty tic eth eae hata a tie de eatin ee ete 17 2 3 Clock Generation Circuit Driver eeccceecceeeeeeeeneeeeeee cece ee ceaeeeeaaeeeeeeesaeeesaaeeeeaaeseeeeeseaeeesaeeseaeeeeenees 19 2 4 Interrupt Control Driver a aaa aaa a a a ar a a aa a aaa 20 2S MO POR DAVE A A A EASA EEA AE EA TEARS 21 2 6 Multifunction Pin Controller Driver ecccececceeseeeceeeeeeeeeeeeeaeeeeaaeeeeneeceaeeeeaaeseeaaesgeeeseaeeeeaaeeeeaeeeneeess 22 2 f MCU OperationiDrive tes smc ia ido 23 2 8 Voltage Detection Circuit Driver ecceecececctceeeeeeeeeeeeeeeee esas nana 24 2 9 Clock Frequency Accuracy Measurement Circuit Driver cecceeececeeeeeeeeeeeeeeceeeeesaeeeeeaeseeeeeseaeess 25 2 10 Low Power Consumption Driver ccccceccceeeeeeeeeeeeeeeeeeeeeeceaeeeeaaeeeeeeeseaeeesaaeeeeaaeseeeeeeeaeeseaeeseeeeeeetess 26 2 11 R
422. option if 10 bit address mode is to be PDL_IIC_10_ BIT_SLAVE ADDRESS used instead of 7 bit mode when the slave address is lt FFh e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE received data3 The address of the slave device data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data data5 The number of bytes that must be received before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Polling PDL_NO_FUNC This function will continue until the required number of bytes has been received or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is received or PDL_NO_FUNC DMAC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest
423. opyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human lif
424. or PDL_SCI_PIN_SCIO_CTSO_PO1 or PDL_SCI_PIN_SCIO_CTSO_P24 PDL_SCI_PIN_SCIO_RTSO_PD7 or PDL_SCI_PIN_SCIO_RTSO_P22 or PDL_SCI_PIN_SCIO_RTSO_POO0 or PDL_SCI_PIN_SCIO_RTSO_ P01 or PDL_SCI_PIN_SCIO_RTSO_P24 PDL_SCI_PIN_SCIO_SSO_PD7 or PDL_SCI_PIN_SCIO_SSO P22 or PDL_SCI_PIN_SCIO_SSO_P0O0 or SSso PDL_SCI_PIN_SCIO_SSO P01 or PDL_SCI_PIN_SCIO_SSO_ P24 RXDO SMISOO SSCLO TXDO SMOSIO SCIO SSDAO SCKO CTSO RTSO EN ESAS Page 234 of 418 RX63T Group Description 2 4 Valid when n 1 4 Library Reference R20UT2201EE0211 Sept 12 2014 PDL_SCI_PIN_SCI1 RXD1_PD5 or PDL_SCI_PIN_SCI1 RXD1_P93 or PDL_SCI_PIN_SCI1 RXD1_P96 or PDL_SCI_PIN_SCI1 RXD1_PF2 or PDL_SCI_PIN_SCI1 RXD1_PF4 or PDL_SCI_PIN_SCI1_SMISO1_PD5 or PDL_SCI_PIN_SCI1_SMISO1_P93 or PDL_SCI_PIN_SCI1_SMISO1_P96 or PDL_SCI_PIN SCI1_SMISO1_PF2 PDL_SCI_PIN_SCI1 SSCL1_PD5 or PDL_SCI_PIN_SCI1 SSCL1_P93 or PDL_SCI_PIN_SCI1_SMISO1_P96 or PDL_SCI_PIN_SCI1 SMISO1_PF2 PDL_SCI_PIN_SCI1 TXD1_PD3 or PDL_SCI_PIN_SCI1 TXD1_P94 or PDL_SCI_PIN_SCI1 TXD1_PF3 or PDL_SCI_PIN_SCI1 TXD1_P95 or PDL_SCI_PIN_SCI1 TXD1_P26 PDL
425. or Conversion completed on the 12 bit ADC unit n PDL_DMAC_TRIGGER_S12ADI1 or n 0 to 1 PDL_DMAC_TRIGGER_S12GBADI or Conversion completed on group B of the 12 bit PDL_DMAC_TRIGGER_S12GBADI1 or ADC unit n n 0 to 1 PDL_DMAC_TRIGGER_MTUAO or PDL_DMAC_TRIGGER_MTUA1 or PDL_DMAC_TRIGGER_MTUA2 or PDL_DMAC_ TRIGGER MTUA3 or il sl maten or e A on MTU PDL DMAC_TRIGGER_MTUA4 or Channel n 0 t04 On Galery PDL_DMAC_TRIGGER_MTUAG6 or PDL_DMAC_TRIGGER_MTUA7 or PDL_DMAC_TRIGGER_MTUBO or PDL_DMAC_TRIGGER_MTUB1 or PDL_DMAC_TRIGGER_MTUB2 or PDL_DMAC_TRIGGER_MTUB3 or PDL_DMAC_TRIGGER_MTUB4 or PDL_DMAC_TRIGGER_MTUB6 or PDL_DMAC_TRIGGER_MTUB7 or PDL_DMAC_TRIGGER_MTUCO or PDL_DMAC_TRIGGER_MTUC3 or PDL_DMAC_TRIGGER_MTUC4 or PDL_DMAC_TRIGGER_MTUC6 or PDL_DMAC_TRIGGER_MTUC7 or Compare match or input capture B on MTU channel n n 0 to 4 or 6 to 7 Compare match or input capture C on MTU channel n n 0 3 4 6 or 7 R20UT2201EE0211 Rev 2 11 RENESAS Page 134 of 418 Sept 12 2014 RX63T Group 4 Library Reference Description 3 4 PDL_DMAC_TRIGGER MTUDO or R20UT2201EE0211 Sept 12 2014 PDL_DMAC_TRIGGER_MTUD3 or PDL_DMAC_TRIGGER_MTUDA or PDL_DMAC_TRIGGER_MTUD6 or PDL_DMAC_TRIGGER_MTUD7 or PDL_DMAC_TRIGGER_MTUU5 or Compare match or input capture D on MTU channel n n
426. or selecting lower power consumption 9 Bus Controller These driver functions are used for configuring the external address bus data bus and chip select pins and handling any bus errors 10 Register Write Proctection These driver functions are used for controlling the register right protection 11 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 12 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 13 Multi Function Timer Pulse Unit These driver functions are used for configuring and controlling the multi function timers 14 Port Output Enable These driver functions are used for additional configuring and controlling of the timer outputs 15 General PWM Timer These driver functions are used for configuring and controlling the timers 16 Compare Match Timer These driver functions are used for configuring and controlling the timers 17 Watchdog Timer These driver functions are used for configuring and controlling the timer R20UT2201EE0211 Rev 2 11 RENESAS Page 17 of 418 Sept 12 2014 RX63T Group 2 Driver 18 Independent Watchdog Timer These driver functions are used for configuring and controlling the timer 19 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission
427. or the given product 1 Table of Contents INTO UCI id intitle A ua a aid Evie eke pee ka 1 1 1 Tool chain requirements diii eiA E EAEE E EEE ARAE a NAE E AEAT ACETA KAATET 2 1 2 Compiler options when you use this product ceeeeeeteeceeeee cee eeeeaeeeeeeeeeaeeeeaaeeseaeeseeeeesaaeeseaaeeeeeeeteas 2 1 3 Using the library within your PrOojeCt cera arene kae eene Aa EE EREA RERET AREER E e EREN KUGE REENE EINE RARS ESEE 3 13s ViathePDGgraphica util prada tddi radican 3 1 32 Using RADE standalone coito dota dra darla einen 3 10 Unzip the RPDL TS os sce tn 3 2 Copy the files into your project area oocoonincinncnninnccnccnnnonnnnncnncanc cnn 3 3 Include the new directory oooccconnoncconononoconnnancnnnc cnc 5 4 Add the RPDE liBrary Tile ss coi ici da iia AAT AEE AEE PANA Oan VETA AEE 6 5 Include the new source files ooononnnidnnnndin nvinnnnnnnnccnncccnnnnann aran nano cc narra rana cnn nc 7 6 Peripherals that are Not required oooocccncccnnnncinnccnnncccnonccnnonnnn nn n nano c cnn nana nnn nc 7 7 Peripherals that are not supported by RPDL ooonnnncccnnccnnnncnonocnnoncccnonnnnnonana noc nnacc narnia nnnnn cnn 7 8 Avoid conflicts with standard project files oonniocinidddnnnnnnnnnninnnnnncnnnnncncrannnccnnancnrnnrn narran cnn 8 9 Setthe Duild OPIONS miii titan rd ata aa PAS aE EREA sess AEAT 10 10 Build the projeti resres riencia rededor 12 11 Using library with debug information ooo
428. or the limit register values data3 If selected in parameter data2 specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA data4 If selected in parameter data2 specify either a the maximum negative deviation for the measured clock as a percentage or b the lower count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false Clock frequency accuracy measurement circuit R_CAC_Create Remarks Program example R20UT2201EE0211 Sept 12 2014 e If signal selection or limit value changes are required the measurement operation must be disabled The Disable operation is executed at the start of this function The Enable operation is executed at the end Therefore both options can be selected together with operation changes in one function call e Ifthe Disable and or Enable operation is selected this function will wait for the operation to complete before continuing To prevent lockup ensure that an enable disable operation is not also performed from a callback function at the same time If the CACREF input is selected the pin selection and digital filter setting used in R_CAC_ Create will be retained RPDL definitions include
429. orage location uint16_t data8 General register E storage location uint16_t data9 General register F storage location uint16_t data10 Cycle setting register storage location uint16_t data11 Cycle setting buffer register storage location uint16_t data12 Cycle setting double buffer register storage location uint16_t data13 ADC start request A register storage location uint16_t data14 ADC start request A buffer register storage location uint16_t data15 ADC start request A double buffer register storage location uint16_t data16 ADC start request B register storage location uint16_t data17 ADC start request B buffer register storage location uint16_t data18 ADC start request B double buffer register storage location uint16_t data19 Dead time up counting register storage location uint16_t data20 Dead time up counting buffer register storage location uint16_t data21 Dead time down counting register storage location uint16_t data22 Dead time down counting buffer register storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 3 for 64 and 48 pin packages n 0 to 7 for 144 120 112 100 pin packages data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if the flags are not to be read b15 b14 b13 b12 b11 b10 b8 Timer counter status Output protected sta
430. orted on 100 pin 112 pin 120 pin 144 pin packages only PDL_LPC_OUTPUT_PORT_RETAINED or PDL_LPC_OUTPUT_PORT_NOT_RETAINED Select whether the address bus and bus control signals retain the output state in software standby mode or deep software standby mode data2 Select the interrupt to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Deep software standby cancel control IRQ6 DS pin and IRQ7 DS pin are supported on 100 pin 112 pin 120 pin 144 pin packages only PDL_LPC_CANCEL_IRQO_DISABLE or PDL_LPC_CANCEL_IRQO_ FALLING or PDL_LPC_CANCEL_IRQO_RISING Prevent or allow an edge on the IRQO DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ1_DISABLE or PDL_LPC_CANCEL_IRQ1_FALLING or PDL_LPC_CANCEL_IRQ1_RISING Prevent or allow an edge on the IRQ1 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ2_DISABLE or PDL_LPC_CANCEL_IRQ2_FALLING or PDL_LPC_CANCEL_IRQ2_RISING Prevent or allow an edge on the IRQ2 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ3_DISABLE or PDL_LPC_CANCEL_IRQ3_FALLING or PDL_LPC_CANCEL_IRQ3_RISING Prevent or allow an edge on the IRQ3 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ4_DISABLE or PDL_LPC_CANCEL_IRQ4 FALLING or PDL_LPC_CANCEL_IRQ4 RISING PDL_LPC_CANCEL_IRQ5_DISABLE or PDL_LPC_CANCEL_IRQ5_ FALLING or PDL_LPC_CANCEL_IRQ5 R
431. oscillator e Main clock Oscillation Stop Detection flag control PDL_CGC_OSC_STOP_CLEAR_FLAG Clear the main clock oscillation stop detection flag data3 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection PLL control PDL_CGC_PLL_ENABLE or PDL_CGC_PLL_DISABLE Enable or disable the PLL circuit e IWDT dedicated low speed on chip oscillat or control PDL_CGC_IWDTLOCO_ENABLE or PDL_CGC_IWDTLOCO_DISABLE Enable or disable the IWDTLOCO Rev 2 11 ENESAS Page 53 of 418 RX63T Group 4 Library Reference Return value True if all parameters are valid and exclusive and a selected clock source has been configured otherwise false Category Clock generation circuit References R_CGC_Set R_LPC_GetStatus R_LPC_Create Remarks e Use R_CGC_Set to configure a clock source before selecting it Ifthe main clock oscillation stop detection flag is cleared the interrupt output is also disabled Use this function to re enable the interrupt output after the main clock oscillation has been restored Do not stop a clock that is in use Do not change the clock source if an Operating Power Control Mode transition is taking place see R_LPC_GetStatus If low speed operating mode 1 is selected do not enable the PLL
432. otection data1 The Protect Register PRCR If the value is not required specify PDL_NO_PTR b7 b4 b3 b2 b1 bO LVD Mode and Reset CGC 0 0 Write Disabled 0 0 Write Disabled 0 Write Disabled 1 Write Enabled 1 Write Enabled 1 Write Enabled data2 The MPC Write Protect Register PWPR If the value is not required specify PDL_NO_PTR b7 b6 b5 bO BOWI PFSWE 0 Writing to the PFSWE bit is enabled 0 Writing to the PFS register is disabled 0 1 Writing to the PFSWE bit is disabled 1 Writing to the PFS register is enabled Return value True Category RWP Reference None Remarks Program example RPDL definitions include r_pdl_rwp h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t PRCR_value uint8_t PWPR_value Read the protection registers R_RWP_Get Status amp PRCR_value amp PWPR_value i R20UT2201EE0211 Rev 2 11 RENESAS Page 122 of 418 Sept 12 2014 RX63T Group 4 2 10 1 R_BSC_Set Synopsis Prototype 4 Library Reference Bus Controller Configure the Bus operation bool R_BSC_Set uint1i6_tdata Bus priority selection Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Configure the priority of the internal and externa
433. oup 4 Library Reference 3 R_SPI_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shutdown an SPI channel bool R_SPI_Destroy uint8 tdata Channel selection Shutdown the selected SPI channel data Select channel SPIn where n 0 1 only For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 True if all parameters are valid otherwise false SPI None The SPI channel is put into the power down state RPDL definitions include r_pdl_spi h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown SPI channel 0 R_SPI_Destroy 0 3 R20UT2201EE0211 Rev 2 11 EN ESAS Page 284 of 418 Sept 12 2014 RX63T Group 4 Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 R_SPI_Command Configure an SPI command bool R_SPI_Command Channel selection Command selection Command options Extended timing control uint8_t data1 uint8_t data2 uint32_t data3 uint8_t data4 Select the options for a command data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Select command n where n 0 to 7 data3 Select the command options If multiple
434. ous receive mode valid only in asychronuous mode PDL_SCI_RX_CONTINUOUS_DISABLE or Disable or enable the continuous receive PDL_SCI_RX_CONTINUOUS_ ENABLE when interrupt is used as the receive method ID reception control valid only in Multi processor mode PDL_SCI_MP_ID_ CYCLE Use the upper byte as the station ID The valid ID range is 0 to 255 data3 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data or for ID cycle in Multi processor mode data4 The number of bytes that must be received before the function completes or the callback function is called Specify 0 for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Pollin PDL_NO_FUNC This function will continue until the required number of bytes has 9 been received The function to be called when the number of received bytes reaches the threshold Interrupts number DMAC Either the function to be called when each byte is received or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_D
435. overed by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses
436. ow PDL_INTC_VECTOR_TGIA4 PDL_INTC_VECTOR_TGIB4 PDL_INTC_VECTOR_TGIC4 PDL_INTC_VECTOR_TGID4 PDL_INTC_VECTOR_TCIV4 Multi function Timer Pulse Unit channel 4 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow or underflow PDL_INTC_VECTOR_TGIU5 PDL_INTC_VECTOR_TGIV5 PDL_INTC_VECTOR_TGIW5 Multi function Timer Pulse Unit channel 5 Compare match or Input capture U Compare match or Input capture V Compare match or Input capture W PDL_INTC_VECTOR_TGIA6 PDL_INTC_VECTOR_TGIB6 PDL_INTC_VECTOR_TGIC6 PDL_INTC_VECTOR_TGID6 PDL_INTC_VECTOR_TCIV6 Multi function Timer Pulse Unit channel 6 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow PDL_INTC_VECTOR_TGIA7 PDL_INTC_VECTOR_TGIB7 PDL_INTC_VECTOR_TGIC7 Multi function Timer Pulse Unit Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C PDL_INTC_VECTOR_OEI4 PDL_INTC_VECTOR_OEI5 PDL_INTC_VECTOR_TGID7 channel 7 Compare match or Input capture D PDL_INTC_VECTOR_TCIV7 Overflow PDL_INTC_VECTOR_OEI1 BBE NTS VECIOR OE Port Output Input level sampling or output level BBE Iie
437. package Function R_CGC_Set must be called to set the frequency The frequency division ratio between PCLK and ADCLK should be one of the following 1 1 1 2 1 4 1 8 2 1 4 1 e Make sure sampling time calculated or specified for channel O and self diagnosis are the same e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only Rev 2 11 EN ESAS Page 316 of 418 RX63T Group 4 Library Reference Program example R20UT2201EE0211 Sept 12 2014 RPDL definitions r pdl_adc_10 h include RPDL device specific definitions include r_pdl_definitions h ADC callback function void ADC_callback void void func void Rev 2 11 Set up the ADC in single mode R_ADC_10_CreateUnit 0 PDL_ADC_10_SCAN_SINGLE PDL_ADC_10_TRIGGER_SOFTWARE PDL_NO_DATA ADC_callback 2 ENESAS using software trigger Page 317 of 418 RX63T Group 4 Library Reference 3 R_ADC_10 CreateChannel Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Configure 10 bit ADC analog channels bool R_ADC_10_CreateChannel uint8_t data1 ADC unit selection uint8_t data2 Analog channel selection uint16_tdata3 Channel configuration double data4 Sampling time Channel specific control Used to
438. pin packages Refer to Hardware manual section 15 Interrupt controller Table 15 3 Interrupt Vector Table for details Name Trigger cause PDL_DTC_TRIGGER_CHAIN or Chain transfer PDL_DTC TRIGGER SW or By software PDL_DTC TRIGGER CMTO or PDL_DTC TRIGGER CMT1 or PDL_DTC TRIGGER CMT2 or Compare match on channel CMTn n 0 to 3 PDL_DTC_ TRIGGER CMTS or PDL_DTC _TRIGGER_USB_DO or PDL_DTC TRIGGER USB_D1 or FIFO interrupt from USBO PDL_DTC_TRIGGER_SPIO_RX or Receive buffer full on SPI channel 0 PDL_DTC_TRIGGER_SPI0_TX or Transmit buffer empty on SPI channel 0 ENESAS Page 145 of 418 RX63T Group 4 Library Reference Description 2 2 PDL_DTC_TRIGGER_SPI1_RX or Receive buffer full on SPI channel 1 R20UT2201EE0211 Sept 12 2014 PDL_DTC_TRIGGER_SPI_TX or Transmit buffer empty on SPI channel 1 PDL_DTC TRIGGER CMP4 or Interrupt request from Comparator 4 PDL_DTC TRIGGER CMP5 or Interrupt request from Comparator 5 PDL DTC TRIGGER CMP6 or PDL_DTC_TRIGGER_IRQO or PDL_DTC_TRIGGER_IRQ1 or PDL_DTC_TRIGGER_IRQ2 or PDL_DTC_TRIGGER_IRQ3 or PDL_DTC_TRIGGER_IRQ4 or PDL_DTC_TRIGGER_IRQ5 or PDL_DTC_TRIGGER_IRQ6 or PDL_DTC_TRIGGER_IRQ7 or Interrupt request from Comparator 6 Valid edge detected on pin IRQn n 0 to 7 PDL_DTC_ TRIGGER ADIO or Conversion completed on the
439. pport The format may be either The transfer bit rate in bits per second bps The clock division values will be calculated using this value This format is valid only when the on chip baud rate generator is selected as the data clock source in parameter data2 Or the following using to separate each selection b31 b30 b24 b23 b0 A value between 256 0x100 and 16 776 960 OxFFFFOO that is 1 0 nearest to the expected transfer bit rate ABCS selection required for asynchronous mode PDL_SCI_CYCLE_BIT_16 or PDL SCI CYCLE BIT 8 Select 16 or 8 base clock cycles for one bit period e CKS selection required if the on chip baud rate generator is selected as the data clock source PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or Select the internal clock signal PCLKB 1 4 16 or 64 as PDL_SCI_PCLK_DIV_16 or the baud rate generator clock source PDL_SCI_PCLK_DIV_64 BRR setting required if the on chip baud rate generator is selected as the data clock source The BRR register value between 0 and 255 data4 The interrupt priority level for data transmission Select between 1 lowest priority and 15 highest priority This parameter may be zero if the following functions will not be used with a callback function R_SCI_Send R_SCI_Receive R_SCI_SPI_Transfer R_SCI_IIC_Write and R_SCI_IIC_Read data5 The interrupt priority level for receive error
440. ption for all APIs 151 MTU Add MTU5 macro for bigger pin package 254 271 IIC add more comment for data1 of all APIs 260 262 IIC Add PDL_IIC_10_BIT_SLAVE_ADDRESS for channel configuration parameter data2 74 76 INTC Add comment for package support 306 309 ADC_10 Add sampling time parameter for Self Dianostic 403 Revise sample code of ADC_10 308 310 Add remark Make sure sampling time calculated or specified for channel O and self diagnosis are the same R20UT2201EE0211 Rev 2 11 AZOUT2201EE0211 Rev211 RENESAS Revisionhistoy lt ESAS Revision history 3 Sept 12 2014 RX63T Group Revision History Description Summary self diagnosis are the same R_ADC_12_Read Add remark for Self diagnosis result format R_ADC_10_Read Add remark for Self diagnosis result format R_DTC_Create Update DTC vector name 254 270 IIC Rephrase comment for available channels in different pin packages 271 283 SPI Rephrase comment for available channels in different pin packages Add the 1 2 Compiler options when you use this product Change 1 3 2 content into Using RPDL stand alone Revise picture litle to little Add content To use library with debug information enter 2 03 Sept 12 2013 RPDL RX630_library_debug as the File path Add content In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you
441. r void BusErrorFunc void void func void Select CS2 on pin PD2 all address signals enable interrupts and register the callback function R_BSC_Create PDL_BSC_CS2_PD2 PDL_NO_DATA PDL_NO_DATA PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE PDL_BSC_ERROR_TIME_OUT_ENABLE BusErrorFunc 5 R20UT2201EE0211 Rev 2 11 RENESAS Page 126 of 418 Sept 12 2014 RX63T Group 3 R_BSC_CreateArea Synopsis Configure an external bus area Prototype bool R_BSC_CreateArea uint8_t data1 Area selection uint16_t data2 uint8_t data3 RRCV cycles uint8_tdata4 WRCV cycles uint8_t data5 CSPRWAIT cycles uint8_tdata6 CSPWWAIT cycles uint8_tdata7 CSRWAIT cycles uint8_tdata8 CSWWAIT cycles uint8_t data9 CSROFF cycles uint8_tdata10 CSWOFF cycles uint8_t data11 WDOFF cycles uint8_t data12 AWAIT cycles uint8_t data13 uint8_t data14 uint8_t data15 uint8_t data16 RDON cycles WRON cycles WDON cycles 1 CSON cycles Description 1 2 Set up an external bus area R20UT2201EE0211 Sept 12 2014 data1 The address area n where n 0 to 3 data2 Configure the operation of area CSn 4 Library Reference Configuration selection If multiple selections are required use to separate each selection The default settings are shown in bold External bus
442. r a initial high level active low level or b initial low level active high level If dead time is not generated the options for negative phases will be ignored as their outputs are always the inversion of the positive phases All six phase outputs can be controlled together by selecting one of each PDL_MTU3_OUT_P PHASE ALL HIGH_LOW or PDL_MTU3_OUT_P PHASE ALL LOW_HIGH PDL_MTU3_OUT_N_PHASE_ALL_HIGH_LOW or PDL_MTU3_OUT_N PHASE ALL LOW_HIGH Positive phase outputs Negative phase outputs Or independently by selecting one option for each required output PDL_MTU3_OUT_P_PHASE_1_HIGH_LOW or PDL_MTU3_OUT_P_PHASE 1_LOW_HIGH PDL_MTU3_OUT_N_PHASE_1_HIGH_LOW or PDL_MTU3_OUT_N PHASE 1 _LOW_HIGH PDL_MTU3_OUT_P_PHASE_2 HIGH_LOW or PDL_MTU3_OUT PDL_MTU3_OUT PDL_MTU3_OUT y 3 4 2 PHASE_2 LOW_HIGH The same outputs as listed for Output PHASE_2 HIGH_LOW or enable control PHASE _2 LOW_HIGH 3 3 3 3 Z Z U U Z Z U UZ Z UU PDL_MTU3_OUT_P_PHASE_3_HIGH_LOW or PDL_MTU3_OUT_P PHASE 3 LOW_HIGH PDL_MTU3_OUT_N_PHASE_3_HIGH_LOW or PDL_MTU3_OUT_N PHASE 3 LOW_HIGH Write access control applies only to reset synchronised or complementary PWM modes PDL_MTU3_OUT_LOCK ENABLE Prevent further changes to the phase output control PWM synchronous output control applies only to reset synchronised or c
443. r 4 in each transfer Before calling this function call R_DTC_Set e Call this function before configuring the peripherals that will be involved in the data transfer e Call this function once for each peripheral that will trigger a transfer and for each chained transfer For chain transfers each transfer data area in the chain must be contiguous When all calls to this function are complete call R_DTC_Control to start the DTC RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h Reserve 16 bytes full address mode for the CMTO triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32_t dtc_cmt0_transfer_datal 4 void func void Configure the DTC for CMTO R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CMTO dtc_cmt0_transfer_data void 0x0000AA00 void 0x0000BBOO 100 0 Rev 2 11 EN ESAS Page 148 of 418 RX63T Group 4 Library Reference 3 R_DTC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Disable the Data Transfer Controller bool R_DTC_Destroy void No parameter is required
444. r ODRO Port Driving Ability control for option PDL_IO_PORT_DRIVE_BUS b15 b8 b7 b0 Do not care Register DSCR1 Port Driving Ability control for option PDL_IO_PORT_DRIVE_SPI b15 b8 b7 b0 Do not care Register DSCR2 True if all parameters are valid and exclusive otherwise false Category I O port References None R20UT2201EE0211 Rev 2 11 2tENESAS Sept 12 2014 Page 84 of 418 RX63T Group 4 Library Reference Remarks Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver Create functions Take care to not overwrite existing settings e Pin PE2 is fixed as an input and can only be modified by option PDL_IO_PORT_MODE e If port is input for the data1 PDL_IO_PORT_DRIVE_BUS or PDL_IO_PORT_DRIVE_SPI is selected for data2 data3 will modify whole register value for Driving Ability Control Register Refer to register DSCR1 and DSCR2 description in hardware manual Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the lower 4 bits on port PB to output R_IO_PORT_ModifyControl PDL_IO_PORT_B PDL_IO PORT DIRECTION PDL_IO_PORT_OR Ox0F R20UT2201EE0211 Rev 2 11 EN ESAS Page 85 of 418 Sept 12 2014 RX63T Group 4 Library Reference
445. r SCLK Options which are available in SPI mode e SPI SS Pin PDL_SCI_SPI_SS_DISABLE or The SS pin is not used Single master environment The SS pin is used PDL_SCI_SPI_SS_ENABLE Note This option is not available if using SPI Master mode if selected the function will return false e Data inversion PDL_SCI_INVERSION_OFF or Ba PDL_SCI INVERSION ON Control data inversion transmission and reception R20UT2201EE0211 Rev 2 11 LEN ESAS Page 239 of 418 RX63T Group Description 3 4 R20UT2201EE0211 Sept 12 2014 Rev 2 11 Options which are available in IIC mode e Noise Filter Clock Select 4 Library Reference PDL_SCI_IIC_FILTER_ DISABLED or The noise filter is disabled PDL_SCI_IIC_FILTER_CLOCK_DIV1 or PDL_SCI_IIC_FILTER_CLOCK_DIV2 or PDL_SCI_IIC_FILTER_CLOCK_DIV4 or PDL_SCI_IIC_FILTER_CLOCK_DIV8 noise filter The clock signal 1 2 4 or 8 is used with the SCL pin SSDA Delay Output Select Delay of output on the SDA Pin relative to the falling edge on the PDL _SCI_IIC_DELAY SDA _0_1 or 0 to 1 cycle delay PDL_SCI_IIC_DELAY_SDA_1_2 or 1 to 2 cycle delay PDL_SCI_IIC_DELAY_SDA_2_3or 2 to 3 cycle delay sequence continues PDL_SCI_IIC_DELAY_SDA_29 30 or 29 to 30 cycle delay PDL_SCI_IIC_DELAY_SDA_30_31 30 to 31 cycle delay Options which are available in Smart Card Interface mo
446. r value shall be stored Specify PDL_NO_PTR if it is not required ENESAS Page 177 of 418 RX63T Group Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference data4 For n A 5 A pointer to where the TGRA register value shall be stored For n 5 A pointer to where the TCNTV register value shall be stored Specify PDL_NO_PTR if it is not required data5 For n A 5 A pointer to where the TGRB register value shall be stored For n 5 A pointer to where the TCNTW register value shall be stored Specify PDL_NO_PTR if it is not required data6 For n 0 3 4 6 and 7 A pointer to where the TGRC register value shall be stored For n 5 A pointer to where the TGRU register value shall be stored Specify PDL_NO_PTR if it is not required data7 For n 0 3 4 6 and 7 A pointer to where the TGRD register value shall be stored For n 5 A pointer to where the TGRV register value shall be stored Specify PDL_NO_PTR if it is not required data8 For n 0 3 4 6 and 7 A pointer to where the TGRE register value shall be stored For n 5 A pointer to where the TGRW register value shall be stored Specify PDL_NO_PTR if it is not required data9 For n 0 4 and 7 A pointer to where the TGRF register value shall be stored Specify PDL_NO_PTR if it is not required Tru
447. r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h void func void Clear the measurement complete flag without stopping R_CAC Control PDL_CAC_CLEAR_MEASUREMENT PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Rev 2 11 EN ESAS Page 111 of 418 RX63T Group 4 R_CAC_GetStatus Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Rev 2 11 Read the clock accuracy circuit status bool R_CAC_GetStatus uint8_t data1 uint16_t data2 Data storage location uint16_t data3 Data storage location uint16_t data4 Data storage location Read the status limit and counter registers 4 Library Reference Pointer to the variable where the status value shall be stored data1 The status flags shall be stored in the format below b7 b4 b3 b2 b1 bO Overflow Measurement Frequency error Operation 0 0 Not detected 0 No event 0 Not detected 0 Disabled 1 Detected 1 Completed 1 Detected 1 Enabled data2 Where the upper limit value register CAULVR value shall be stored Specify PDL_NO_PTR if it is not required data3 Where the lower limit value register CALLVR value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the counter bu
448. ram example R20UT2201EE0211 Sept 12 2014 If an external clock input pin MTCLKx or I O pin MTIOCnx is made active this function will configure that pin for input or output and disable other functions on that pin Call R_MTU3_Set before calling this function to select the pins to be used Either R_MTU3_ControlChannel or R_MTU3_ControlUnit must be used to start the timers If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 86 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed If the channel is configured for phase counting mode the counter clock source setting is ignored If reset synchronised or complementary PWM mode is required then follow these steps in the order they are presented 1 Call this function for channel 3 or 6 and specify the required PWM mode At this time the associated channel 4 or 7 will be set to normal mode 2 To configure the associated channel 4 or 7 call this function again and specify Normal operation not a PWM mode Call R_MTU3_ControlUnit with PDL_MTU3_PWM_RS_COMP_ENABLE If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not vali
449. re disabled the module is put into the power down state e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down DAC channel 1 R_DAC_10_Destroy PDL_DAC_10_CHANNEL_1 Y Rev 2 11 EN ESAS Page 325 of 418 RX63T Group 4 Library Reference 3 R_DAC_10 Write Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Write data to a DAC channel bool R_DAC_10 Write uint8_t data1 Channel selection uint16 tdata2 Output value uint16 tdata3 Output value Write data to the selected DAC channel s data1 Select the DAC channel output to be modified PDL_DAC 10 CHANNEL O Select channel 0 PDL_DAC 10 CHANNEL_1 Select channel 1 data2 The value to be written to the channel 0 output register Ignored if the channel is not selected data3 The value to be written to the channel 1 output register Ignored if the channel is not selected True if all parameters are valid otherwise false DAC R_DAC_10 Create e Refer to the data alignment that was selected when R_DAC_10_Create was called This function is supported on 100 pin 112 pin 120 pin 144 pin pack
450. re match or input capture U on MTU channel 5 PDL_DTC_TRIGGER_MTUV4 or PDL_DTC_TRIGGER_MTUV5 or PDL_DTC_TRIGGER_MTUV7 or Compare match or input capture V on MTU channel 5 Counter over or underflow V on MTU channel 4 and 7 PDL_DTC_TRIGGER_MTUW5 or Compare match or input capture W on MTU channel 5 PDL_DTC TRIGGER CMPO or Interrupt request from Comparator 0 PDL_DTC TRIGGER CMP1 or Interrupt request from Comparator 1 PDL_DTC_TRIGGER_CMP2 or Interrupt request from Comparator 2 PDL_DTC_ TRIGGER _IIC1_RX or Receive buffer full on 12C channel 1 PDL_DTC TRIGGER _IIC1_TX or Transmit buffer empty on 12C channel 1 PDL_DTC TRIGGER _IICO_RX or Receive buffer full on 12C channel O PDL_DTC_TRIGGER_IICO_TX or Transmit buffer empty on I2C channel 0 PDL_DTC_TRIGGER_DMACOI PDL DTC TRIGGER DMAC1I PDL_DTC_TRIGGER DMAC2I PDL_DTC TRIGGER DMACSI Transfer complete on DMAC channel n n 0 to 3 Rev 2 11 ENESAS Page 146 of 418 RX63T Group 4 Library Reference Description 3 4 PDL_DTC_TRIGGER_GPTAO or R20UT2201EE0211 Sept 12 2014 PDL_DTC_TRIGGER_GPTA1 or PDL_DTC_TRIGGER_GPTA2 or PDL_DTC_TRIGGER_GPTA3 or PDL DTC TRIGGER _GPTA5 or PDL_DTC_TRIGGER_GPTA4 or PDL_DTC TRIGGER GPTA6 or PDL_DTC_TRIGGER_GPTA7 or Compare match or input capture A on GPT channel n n 0 to 7
451. re the SCI pin selection for SCI channels where there is a choice of SCI pins bool R_SCI_Set uint8_t data1 uint32_t data2 Channel selection VO configuration for channels Configure I O pins for all SCI channels There is no default option data1 The channel number n where n 0 1 or 12 for 64 and 48 pin packages n 0 1 2 3 or 12 for 144 120 112 and 100 pin packages data2 Configure the I O pins required only if the pins are used for the SCI function Use to separate each selection Valid when n 0 PDL_SCI_PIN_SCIO_RXDO_PB1 or PDL_SCI_PIN_SCIO_RXDO_P24 or PDL_SCI_PIN_SCIO_RXDO_P22 or PDL_SCI_PIN_SCIO_RXDO_PA5 PDL_SCI_PIN_SCIO_SMISOO_PB1 or PDL_SCI_PIN_SCIO_SMISOO_P24 or PDL_SCI_PIN_SCIO_SMISOO_P22 or PDL_SCI PIN _SCIO_SMISOO PA5 PDL_SCI_PIN_SCIO_SSCLO _PB1 or PDL_SCI_PIN_SCIO_SSCLO_P24 or PDL_SCI_PIN_SCIO_SSCLO_P22 or PDL_SCI_PIN_SCIO_SSCLO_PA5 PDL_SCI_PIN_SCIO_TXDO_PB2 or PDL_SCI_PIN_SCIO_TXDO_P30 or PDL_SCI_PIN_SCIO_TXDO_P23 or PDL_SCI PIN _ SCIO_TXDO PA4 PDL_SCI_PIN_SCIO_SMOSIO_PB2 or PDL_SCI_PIN_SCIO_SMOSIO_P30 or PDL_SCI_PIN_SCIO_SMOSIO_P23 or PDL_SCI_PIN_SCIO_SMOSIO_PA4 PDL_SCI_PIN_SCIO_SSDAO_PB2 or PDL_SCI_PIN_SCIO_SSDAO_P30 or PDL_SCI_PIN_SCIO_SSDAO_P23 or PDL_SCI_PIN_SCIO_SSDAO_PA4 PDL_SCI_PIN_SCIO_SCKO_PB3 or PDL_SCI_PIN_SCIO_SCKO_P23 or PDL_SCI_PIN_SCIO_SCKO_P30 or PDL_SCI_PIN_SCIO_SCKO_PA3 PDL_SCI_PIN_SCIO_CTSO_PD7 or PDL_SCI_PIN_SCIO_CTSO_P22 or PDL_SCI_PIN_SCIO_CTSO_POO0
452. reateUnit If analog channels are used as the input sources call this function after calling R_ADC_10_CreateUnit e Function R_CGC_Set must be called to set the frequency e The frequency division ratio between PCLK and ADCLK should be one of the following 1 1 1 2 1 4 1 8 2 1 4 1 e Channel 8 to channel 19 shares the same sampling state register so please use same sampling time for channel 8 onwards e Make sure sampling time calculated or specified for channel 0 and self diagnosis are the same e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only Rev 2 11 EN ESAS Page 318 of 418 RX63T Group 4 Library Reference Program example R20UT2201EE0211 Sept 12 2014 RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Configure ANO R_ADC_10_CreateChannel 0 0 PDL_ADC_10_CH_VALUE_ADDITION_DISABLE 6E 6 Rev 2 11 ENESAS Page 319 of 418 RX63T Group 4 Library Reference 4 R_ADC 10 Destroy Synopsis Shut down the ADC unit Prototype bool R_ADC_10_Destroy uint8 tdata ADC unit selection Description Put the ADC into the Power down state with minimal power consumption data Select the ADC unit to be shut down This must be 0 for all device packages Return value True if a
453. ripheral module clock PCLKB IWDT low speed on chip oscillator or input to pin CACREF as the reference signal PDL_CAC_REFERENCE_RISING or PDL_CAC_REFERENCE_FALLING or PDL_CAC_REFERENCE BOTH Select rising edges falling edges or both rising and falling edges to be valid PDL_CAC_REFERENCE_DIV_32 or PDL_CAC_REFERENCE_DIV_128 or PDL_CAC_REFERENCE_DIV_1024 or PDL_CAC_REFERENCE_DIV_8192 Divide the reference signal by 32 128 1024 or 8192 Not applicable when the CACREF input is selected as the reference signal Measured clock selection and division PDL_CAC_MEASURE_MAIN PDL_CAC_MEASURE_PCLK or PDL_CAC_MEASURE_IWDTLOCO Select the Main clock oscillator Peripheral module clock PCLKB or IWDT low speed on chip oscillator for measurement PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or PDL_CAC_MEASURE_DIV_8 or PDL_CAC_MEASURE_DIV_ 32 Divide the clock to be measured by 1 4 8 or 32 Limit value calculation PDL CAC LIMIT TOLERANCE or PDL_CAC_LIMIT_REGISTER Parameters data4 and data5 will contain either the tolerance or the limit register values data2 Choose the CACREF input settings Use to separate each selection If the CACREF input is not required specify PDL_NO_DATA External input configuration PDL_CAC_CACREF_PORT_0_0 or PDL_CAC_CACREF_PORT_0_1 or PDL_CAC_CACREF_PORT_2 3 or PDL_CAC_CACREF_PORT_B 3 Select the pin to be used for signal CACREF
454. rity bit PDL_SCI_PARITY_EVEN or Note Do not set parity bit for Multi Processor PDL_SCI_PARITY_ODD Asynchronous mode e Stop bit length PDL_SCI_STOP_1 or O bi PDL_SCI_STOP 2 ne or two stop bits The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in all Clock Synchronous modes including IIC and SPI e SPI mode selection SPI Mode selected Use the R_SCI_SPI_Transfer function RBE ABILSEL MODE not R_SCI_Send or R_SCI_Receive IIC mode selection IIC Mode selected Use the functions R_SCI_IIC_Read and PDL SCILIG_ MODE R_SCI_IIC_Write not R_SCI_Send or R_SCI_Receive Options which are available in Clock Synchronous and SPI mode e Data clock source selection Select the On chip baud rate generator PDL_SCI_CLK_INT_OUT or The SCKn pin outputs the bit clock In SPI Mode this is Master mode Input the clock to the SCKn pin la ei age EXI In SPI Mode this is Slave mode e SPI Clock Polarity Inversion PDL_SCI_CLOCK_POLARITY_INVERTED The SCK clock is inverted e SPI Clock Phase Delay PDL_SCI_CLOCK_PHASE_DELAYED The SCK clock is delayed Options which are available in Clock Synchronous mode Not SPI or IIC e Hardware Flow Control Select the Hardware Flow Control Option Notes PDL oc HW FLOW NONE or da CTS can only be selected if using an internal clock PDL_SCI_HW_FLOW_CTS or for SCLK PDL_SCI_HW_FLOW_RTS ae e RTS can only be selected if using external clock source fo
455. rnal interrupt use Pin IRQ1 DS is used to detect a falling edge and generates an interrupt Peripheral driver function prototypes include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototypes void SWl_handler void void SW2_handler void void SW3_handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL 0 Select the pins for SW1 SW2 and SW3 if defined DEVICE_PACKAGE_64_PIN defined DEVICE_PACKAGE_48_PIN R_INTC_SetExtInterrupt PDL_INTC_IRQO_P10 PDL_INTC_IRO1_P11 PDL_INTC_IRQ2_ P00 3 else R_INTC_SetExtInterrupt PDL_INTC_IRQO_P10 PDL_INTC_IRO1_P11 PDL_INTC_IRO2 P1 a endif Configure the SW1 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IROO PDL_INTC_FALLING SWl_handler 7 Configure the SW2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ1 PDL_INTC_FILTER_DIV_32 PDL_INTC_FALLING SW2_handler 7 Configure the SW3 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING SW3_handler gt void SW1_handler void volatile uint8_t irq_ status 0u R_INTC_GetExtInterruptStatus PDL_ INTC TROO R20UT2201EE0211 Rev 2 11 EN ESAS Page 338 of 418 Sept 12 2014 RX63T Group 5 Usage Examples
456. rsions of the tool chain The latest version of the tool chain can be downloaded from the Renesas Web site Home Products Software and Tools Coding Tools C C Compilers and Assemblers C C Compiler Package for RX Family 1 2 Compiler options when you use this product 1 The options which must be specified in your project are listed below The options other than cpu dbl_size are the default setting of the compiler cpu rx600 round nearest denormalize off dbl_size 8 unsigned_char unsigned_bitfield bit_order right unpack noexception rtti off fint_register 0 branch 24 2 The options which must NOT be specified in your project are listed below As the default setting of the compiler the following options are not specified int_to_short auto_enum base patch pic pid nouse_pid_register Save_acc R20UT2201EE0211 Rev 2 11 RENESAS Page 2 of 418 Sept 12 2014 RX63T Group 1 Introduction 1 3 Using the library within your project The driver library can be used in two ways 1 3 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pdg The directions for use of the PDG utility are given in the PDG manual 1 3 2 Using RPDL stand alone To add the driver library to your project s build environment you need to Unzip the RPDL distribution Copy the required source header and library files into your project folder Include th
457. s R_SPI_Set 0 Rev 2 11 PDL_SPI_RSPCKA_P24 PDL_SPI_MOSIA_P23 PDL_SPI_MISOA_P22 PDL_SPI_SSLAO_P30 PDL_SPI_SSLA1_P31 PDL_SPI_SSLA2_ P32 PDL_SPI_SSLA3_P33 PDL_NO_DATA ztENESAS Page 280 of 418 RX63T Group 2 R_SPI_Create Synopsis Prototype Description 1 3 R20UT2201EE0211 Sept 12 2014 4 Library Reference Configure an SPI channel bool R_SPI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Data format uint32_t data4 Extended timing control uint32_t data5 Bit rate or register value Set up the selected SPI channel data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold e Connection mode PDL_SPI_MODE_SPI_MASTER or PDL_SPI_MODE_SPI_MULTI_MASTER or The required SPI four wire or Clock PDL_SPI_MODE_SPI_SLAVE or synchronous three wire operation PDL_SPI_MODE_SYNC_MASTER or connection type PDL_SPI_MODE_SYNC_SLAVE Reception control PDL_SPI_FULL_DUPLEX or PDL_SPI_TRANSMIT_ONLY Enable or disable reception operations e Pin control If output signal SSLx where x 0 1 2 or 3 is used call function R_SPI_Set to se
458. s include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint16_t Counter void func void Read the channel 2 values R_CMT_Read 2 amp Flags amp Counter Rev 2 11 EN ESAS Page 225 of 418 RX63T Group 4 2 17 1 R_WDT_Set Synopsis Prototype Description Return value Category Reference R20UT2201EE0211 Sept 12 2014 Watchdog Timer Configure the Watchdog timer bool R_WDT_Set uint32_t data Set up and start the Watchdog timer data Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold Time out selection 4 Library Reference Configuration selection PDL_WDT_TIMEOUT_1024 or PDL_WDT_TIMEOUT_4096 or PDL_WDT_TIMEOUT_8192 or PDL_WDT_TIMEOUT_16384 Time out period specified in cycles of the divided clock as specified in the Clock Selection below Clock selection PDL_WDT_PCLK_DIV_4 or PDL_WDT_PCLK_DIV_64 or PDL_WDT_PCLK_DIV_128 or PDL_WDT_PCLK_DIV_512 or PDL_WDT_PCLK_DIV_2048 or PDL_WDT_PCLK_DIV_8192 The division ratio for the internal clock signal PCLKB MCU reset control PDL_WDT_TIMEOUT_RESET or PDL_WDT_TIMEOUT_NMI When the WDT times out select if either a Reset or an NMI interrupt will be generated Wi
459. s const char source_string_1 Renesas RX63T volatile uint8_t destination_string_1 Callback function prototype void IRQ2_ handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG IPL 0 Enable control of L R_IO_PORT_Set PDL_IO PORT_ PDL_IO PORT_ Set the DTC options R_DTC_Set PDL_NO_DATA dtc_vector_table y Configure the DTC for IRQ2 R_DTC_Create PDL_DTC_BLOCK PDL_DTC_DESTINATION PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_ PLUS PDL_DTC_SIZE_8 PDL_DTC_IRO COMPLETE PDL_DTC_TRIGGER_IRQ2 dtc_irq_transfer_data source_string_l R20UT2201EE0211 Rev 2 11 RENESAS Page 355 of 418 Sept 12 2014 RX63T Group 5 Usage Examples destination_string_l 1 uint8_t strlen char source_string_1 Set TRO2 pin R_INTC_SetExtInterrupt PDL_INTC_IRQ2_PIN Enable the IRQ2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_FALLING PDL_INTC_DTC_TRIGG IRQ2_handler 7 Start the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA i Wait for IRQ2 falling signal while 1 void IRQ2_ handler void uint16_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint16_t Trans
460. s PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT2201EE0211 Rev 2 11 EN ESAS Page 98 of 418 Sept 12 2014 RX63T Group 3 R_MCU_OFS Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Configure the device start up operation R_MCU_OFS uint32_t data1 uint32_t data2 uint32_t data3 4 Library Reference WDT configuration options WDT configuration options LVD configuration options Select the auto start settings to be stored in registers OFSO and OFS1 data1 Select the post reset IWDT configuration settings If multiple selections are required use to separate each selection Auto start control PDL_MCU_OFS_IWDT_HALTED or PDL_MCU_OFS_IWDT_AUTOSTART Disable or enable the IWDT auto start mode If auto start mode is enabled select one setting from each of the following Rev 2 11 Timeout period PDL_MCU_OFS_IWDT TIMEOUT_1024 or PDL_MCU_OFS_IWDT TIMEOUT_4096 or PDL_MCU_OFS_IWDT TIMEOUT_8192 or PDL_MCU_OFS IWDT TIMEOUT_16384 Timeout period specified in cycles of the divided clock as specified in the Clock division selection below Clock division PDL_MCU_OFS_IWDT CLOCK_LOCO_1 or PDL_MCU_OFS_IWDT CLOCK_LOCO_16 or PDL_MCU_OFS_IWDT CLOCK_LOCO_32 or PDL_MCU_OFS_IWDT CLOCK_LOCO_64 or PDL_MCU_OFS_IWDT CLOCK_LOCO_128 or PDL_MCU_OFS I
461. selections are required specify PDL_NO_DATA Software Standby waiting time Prevent or allow an edge on the NMI pin to cancel deep software standby mode PDL_LPC_MAIN_2 or PDL_LPC_MAIN_4 or PDL_LPC_MAIN_8 or PDL_LPC_MAIN_16 or PDL_LPC_MAIN_32 or PDL_LPC_MAIN_64 or PDL_LPC_MAIN_512 or PDL_LPC_MAIN_1024 or PDL_LPC_MAIN_2048 or PDL_LPC_MAIN_4096 or PDL_LPC_MAIN_16384 or PDL_LPC_MAIN_32768 or PDL_LPC_MAIN_65536 or PDL_LPC_MAIN_131072 or PDL_LPC_MAIN_262144 or PDL_LPC_MAIN_524288 data5 Select the PLL waiting times If no selections are required specify PDL_NO_DATA Select the oscillation settling time of the main clock oscillator before the CPU resumes after exiting from software standby mode When updating this value the main clock oscillator must be stopped Deep Software Standby waiting time PDL_LPC_PLL_16 or PDL_LPC_PLL_32 or PDL_LPC_PLL_64 or PDL_LPC_PLL_512 or PDL_LPC_PLL_1024 or PDL_LPC_PLL_2048 or PDL_LPC_PLL_4096 or PDL_LPC_PLL_16384 or PDL_LPC_PLL_32768 or PDL_LPC_PLL_65536 or PDL_LPC_PLL_131072 or PDL_LPC_PLL_262144 or PDL_LPC_PLL_524288 or PDL_LPC_PLL_1048576 or PDL_LPC_PLL_2097152 or PDL_LPC_PLL_4194304 Select the oscillation settling time of the PLL before the CPU resumes after exiting from software standby mode When updating this value the PLL circuit must be stopped True if all parameters are valid and exclusive otherwise false LPG R_LPC_Control R_CGC
462. selections are required use to separate each selection The default settings are shown in bold Clock phase and polarity 4 Library Reference Idle clock Data sampling edge PDL_SPI_CLOCK_MODE_0 or Low Rising PDL SPI _CLOCK_MODE_1 or Falling PDL_SPI_CLOCK_MODE 2 or High Rising PDL_SPI_CLOCK_MODE_3 9 Falling Clock division PDL_SPI_DIV_1 or PDL_SPI_DIV_2 or PDL_SPI_DIV_4 or PDL_SPI_DIV_8 Use the bit rate specified for R_SPI_Create 1 2 4 or 8 Ignored in Slave mode SSL assertion PDL_SPI_ASSERT_SSLO or PDL_SPI_ASSERT_SSL1 or PDL_SPI_ASSERT_SSL2 or PDL_SPI_ASSERT_SSL3 The SSL pin to be asserted during the frame transfer Ignored in Slave mode SSL negation PDL_SPI_SSL_NEGATE or PDL_SPI_SSL_KEEP Negate or retain the SSL signal after the frame transfer Ignored in Slave mode Frame data length PDL_SPI_LENGTH_8 or PDL_SPI_LENGTH_9 or PDL_SPI_LENGTH_10 or PDL_SPI_LENGTH_11 or PDL_SPI_LENGTH_12 or PDL_SPI_LENGTH_13 or PDL_SPI_LENGTH_14 or PDL_SPI_LENGTH_15 or PDL_SPI_LENGTH_16 or PDL_SPI_LENGTH_20 or PDL_SPI_LENGTH_24 or PDL_SPI_LENGTH_32 The number of bits in the frame transfer If a buffer size of 64 bits was selected when R_SPI_Create was called the number of bits must not exceed 16 Data transfer format Rev 2 11 PDL_SPI_MSB_FIRST or PDL_SPI_LSB FIRST Select least or most significant bit first
463. shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_SPI_TX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_TX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_TX_DTC_TRIGGER_ENABLE data byte is transmitted DMAC DTC trigger control PDL_SCI_SPI_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_RX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_RX_DTC_TRIGGER_ENABLE data byte is received data3 The number of bytes that must be transferred either transmitted received or both before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data func1 Transmit callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent Interrupts The function to be called when the last byte has been sent Either the function to be called when each byte is sent or PDL_NO_FUNC DMAG if the callback
464. stop an ADC unit Prototype bool R_ADC_12 Control uint32_t data Conversion unit control Description 1 2 Controls start stop operation of the specified ADC R20UT2201EE0211 Sept 12 2014 data To select multiple options at the same time use to separate each value On off control for Comparator on ANOOO Unit 0 PDL_ADC 12 CMP_000_ON or Start the comparator on ANOOO PDL_ADC 12 CMP_000_OFF Stop the comparator on ANOOO e On off control for Comparator on ANOO1 Unit 0 PDL_ADC_12_CMP_001_ON or Start the comparator on ANOO1 PDL_ADC 12 CMP_001_OFF Stop the comparator on ANOO1 e On off control for Comparator on ANOO2 Unit 0 PDL_ADC 12 CMP_002 ON or Start the comparator on AN002 PDL_ADC 12 CMP_002 OFF Stop the comparator on AN002 e On off control for Comparator on AN100 Unit 1 PDL_ADC 12 CMP_100_ON or Start the comparator on AN100 PDL_ADC 12 CMP_100_OFF Stop the comparator on AN100 e On off control for Comparator on AN101 Unit 1 PDL_ADC 12 CMP_101_ON or Start the comparator on AN101 PDL_ADC_12 CMP_101_OFF Stop the comparator on AN101 e On off control for Comparator on AN102 Unit 1 PDL_ADC 12 CMP_102 ON or Start the comparator on AN102 PDL_ADC 12 CMP_102 OFF Stop the comparator on AN102 e On off control for ADC unit 0 PDL_ADC_12 0 ONor Start a software triggered conversion or
465. stop and clear control are disabled PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR ANOOO or ANOO1 or ANOO2 or AN100 or AN101 or AN102 or Comparator detection on 12 bit ADC input ANxxx PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR GTIOC3A_IN or GTIOC3B_IN or A valid edge on the GPT pin PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR GTIOC3A_OUT or GTIOC3B_OUT or A valid edge on the GPT output compare Not valid for channel 3 PDL_GPT_HW_STOP_CLEAR PDL_GPT_HW_STOP_CLEAR GTETRGO or GTETRG1 A valid edge on the GTETRGn pin Rev 2 11 ENESAS Page 195 of 418 RX63T Group Description 4 7 R20UT2201EE0211 Sept 12 2014 Rev 2 11 data6 4 Library Reference I O pin control options If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Compare match Input capture selection for pin GTIOCnA PDL_GPT_A_DISABLED or Not used or PDL_GPT_A_CM_RETAIN or PDL_GPT_A_CM_LOW or PDL_GPT_A_CM_HIGH or PDL_GPT_A_CM_INVERT or At a compare match the output is retained set low set high or toggled or PDL_GPT_A_IC_RISING_EDGE or PDL_GPT_A_IC_FALLING_EDGE or Input capture at rising edge falling edge or PDL_GPT_
466. supported by RPDL The file Interrupt_not_RPDL c also contains handlers for the peripherals that are not supported by RPDL This allows the user to add handler code for these peripherals while supporting the Fast Interrupt feature see R_INTC_CreateFastinterrupt R20UT2201EE0211 Rev 2 11 AS Page 7 of 418 Sept 12 2014 RENES RX63T Group 1 Introduction 8 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them a Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files OK Interrupt_DMAC c C workSpace a C workSpace CAW orkSpace CAwWorkSpace CXAWorkSpace CAWorkSpace Cancel C workSpace Remove All Remove C workSpace C WorkSpace C WworkSpace CAW orkSpace _ C workS pace C workSpace CAwWorkSpace C workSpace R20UT2201EE0211 Rev 2 11 AS Page 8 of 418 Sept 12 2014 RENES RX63T Group 1 Introduction b Exclusion Select the two files and use the key sequence Alt B to exclude them benoak melo ARR on pengisi EER jome we 2 2 EEE be Figure 1 3 intprg c and vecttbl c have been excluded R20UT2201EE0211 Rev 2 11 AS Page 9 of 418 Sept 12 2014 RENES RX63T Group 1 Introduction 9 Set the build options Use the key sequence Alt B R to open
467. system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set pin options R_SCI_Set 0 if defined DEVICE_PACKAGE_64_PIN amp amp defined EVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCIO_RXDO_PB1 PDL_SCI_PIN_SCIO_TXDO_PB2 else PDL_SCI_PIN_SCIO_RXDO_P24 PDL_SCI_PIN_SCIO_TXDO_P30 endif i Configure the RS232 port specify Async MP mode R_SCI_Create 0 PDL_SCI_8N1 PDL_SCI_ASYNC_MP 57600 di Async MP mode data Transmission by CPU ISR NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x0A by internal polling R_SCI_Send 0 Ox0A00 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC di tx_end false Send data to Target Station ID 0x0A using interrupts R_SCI_Send 0 PDL_NO_DATA send_data0 0 SCItx R20UT2201EE0211 Rev 2 11 AS Page 379 of 418 Sept 12 2014 RENES RX63T Group 5 Usage Examples NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x01 by internal polling R_SCI_Send 0 0x0100 PDL_SCI_MP_ID_CYCLE PDL_NO_PTR 0 PDL_NO_FUNC Send data to Target Station ID 0x01 by polling R_SCI_Send 0 PDL_NO_DATA send_data 0 PDL_NO_FUNC di while 1 SCI
468. t R20UT2201EE0211 Rev 2 11 LEN ESAS Page 220 of 418 Sept 12 2014 RX63T Group Remarks Program example R20UT2201EE0211 Sept 12 2014 4 Library Reference e Function R_CGC_Set must be called with the current clock source selected before using this function Function R_CMT_Create is not required Ensure that the timer channel is stopped before calling this function Note that the timer is stopped automatically when the one shot period is reached e If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the peripheral module clock PCLKB frcike MHz Equation 50 48 12 5 12 32 8 8 Tmn EE 160ns 166 67ns 640ns 666 67ns 250ns tus Frcrx T 92 SS 671ms 699ms 2 68s 2 79s 1 05s 4 19s x Trex f the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period RPDI include RPDI include L definitions r pdl_cmt h r pdl_definitions h void func void L device specific definitions Use CMT channel 0 for a lms pause R_CMT_CreateOneShot Rev 2 11 0 PDL_
469. t a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_ Control function to manually generate a stop lf a callback function is specified and the interrupt priority level is zero this function will return false The SCI IIC module is always configured to use Reception and Transmission interrupts IICINTM bit 1 rather than ACK NACK interrupts This means that if using the DMAC or DTC to transmit then all data will be transmitted even if the slave device fails to ACK RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h define CHANNEL_SCI_IIC 1 define SLAVE_ADDRESS 0xA0 Buffer for IIC data volatile uint8_t IIC_Buffer 10 void func void Wait while send 10 bytes R_SCI_IIC_Write CHANNEL_SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 TIC_Buffer PDL_NO_FUNC R20UT2201EE0211 Rev 2 11 EN ESAS Page 254 of 418 Sept 12 2014 RX63T Group 4 Library Reference 8 R_SCI_IIC_Read Synopsis Prototype Description 1 2 R20UT2201EE0211 Sept 12 2014 Perform an IIC master read on an SCI channel bool R_SCI_IIC_Read uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave Address uint16_t data4 Number of
470. t16_t iwdtclk_counter_results 16 void func void Read the status flags and IWDTCLK count registers R_GPT_ReadUnit 0 amp Flags amp iwdtclk_counter amp iwdtclk_counter_result_average amp iwdtclk_counter_upper_limit amp iwdtclk_counter_lower_limit iwdtclk_counter_results R20UT2201EE0211 Rev 2 11 RENESAS Page 212 of 418 Sept 12 2014 RX63T Group 4 Library Reference 9 R_GPT_EdgeDelay_ Create Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Enable the PWM Edge Delay circuit bool R_GPT_EdgeDelay_Create uint8 data1 Channel 0 configuration uint8 data2 Channel 1 configuration uint8 data3 Channel 2 configuration uint8 data4 Channel 3 configuration Enable the PWM Edge Delay circuit data1 Channel 0 configuration Specify PDL_NO_DATA to use the default e Configuration PDL_GPT_PWM_DELAY LEAVE Leave the current configuration PDL_GPT_PWM_DELAY_ENABLE Enable and activate the delay circuit PDL_GPT_PWM_DELAY_DISABLE Disable the delay circuit data2 Channel 1 configuration See data1 for format data3 Channel 2 configuration See data1 for format data4 Channel 3 configuration See data1 for format True if all parameters are valid and exclusive otherwise false General PWM Timer unit None
471. tart PDL_IIC_START_DISABLE condition at the beginning of the transfer e Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end PDL_IIC_STOP_DISABLE of the transfer e Slave address size override Specify this option if 10 bit address mode is to be PDL_IIC_10_ BIT SLAVE_ADDRESS used instead of 7 bit mode when the slave address is lt FFh e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE transmitted data3 The address of the slave device Ignored if the Start condition is disabled data4 The start address of the data to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data5 The number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is sent or PDL_NO_FUNC DMAG if the callback function specified
472. tary PWM mode PDL_MTU3_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU3_OUT_BUFFER_TRANSFER_CREST or PDL_MTU3_OUT_BUFFER_TRANSFER_TROUGH or PDL_MTU3 OUT BUFFER TRANSFER BOTH In Reset synchronised PWM mode Disable or enable on detection of crest trough or both PDL_MTU3_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU3 OUT BUFFER _TRANSFER_CLEAR Disable or enable on counter clear Buffer transfer to temporary transfer control Applicable for complementary PWM modes PDL_MTU3_BUFFER_TRANSFER_DISABLE or Disable transfers PDL_MTU3_BUFFER_TRANSFER_ENABLE or enable without linking to interrupt skipping or PDL_MTU3_BUFFER_TRANSFER_LINK enable and link to interrupt skipping Rev 2 11 ENESAS Page 174 of 418 RX63T Group Description 6 6 Return value Category Reference R20UT2201EE0211 Sept 12 2014 4 Library Reference int_skip_control Interrupt skipping control settings All settings are optional but only one skipping function type may be selected If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Interrupt skipping control type 1 PDL_MTU3_INT_SKIP_TROUGH_DISABLE or PDL_MTU3_INT_SKIP_TROUGH_1 or PDL_MTU3_INT_SKIP_TROUGH_2 or PDL_MTU3_INT_SKIP_TROUGH_3 or PDL_MTU3_INT_SKIP_TROUGH_4 or PDL_MTU3_INT_SKIP_TROUGH_5 or PDL_MTU3_INT_SKIP_TROUGH_6 or PDL_MTU3_INT_SKIP_TROUGH_7 PDL
473. tatus The maximum number of characters to be received or transmitted is 65535 Wait until a transmission on the same channel is complete before calling this function f no error callback function func3 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed In SPI master mode the slave s SS pin must be asserted before calling this function A general I O pin can be used for this see the I O Port API e If using the DMAC or DTC this module does not know when the transfer has ended Therefore when the transfer has completed the user must call the R_SCI_Control function with options PDL_SCI_STOP_TX PDL_SCI_STOP_RX to manually disable the transmission reception as appropriate If a callback function is specified and the interrupt priority level is zero this function will return e f using this function to perform a full duplex transfer then the transfer mode for transmit and receive can be set independently If using the polling transfer mode for only one direction this function must not be called from an interrupt handler so that interrupts can still be serviced for the non polling transfer direction Category SCI Reference Remarks false R20UT2201EE0211 Sept 12 2014 Rev 2 11 EN ESAS Page 251 of 41
474. tch E or F Counter limit match Transfer error or event generation Data received Start of next data transfer End of data transfer PDL_INTC_VECTOR_ICEEIO PDL_INTC_VECTOR_ICRXIO PDL_INTC_VECTOR_ICTXIO PDL_INTC_VECTOR_ICTEIO 12C bus interface channel 0 Transfer error or event generation Data received Start of next data transfer End of data transfer PDL_INTC_VECTOR DMACOI PDL_INTC_VECTOR DMAC1I PDL_INTC_VECTOR DMAC2I Direct memory access Transfer complete or Transfer escape end PDL_INTC_ VECTOR DMAGSI controler PDL_INTC_VECTOR_RXIO Data received PDL_INTC_VECTOR_TXIO SCI channel 0 Start of next data transfer PDL_INTC_VECTOR_TEIO End of data transfer PDL_INTC_VECTOR_RXI1 Data received PDL_INTC_VECTOR_TXI1 SCI channel 1 Start of next data transfer PDL_INTC_VECTOR_TEI1 End of data transfer PDL_INTC_VECTOR_RXI2 Data received PDL_INTC_VECTOR_TXI2 SCI channel 2 Start of next data transfer PDL_INTC_VECTOR_TEI2 End of data transfer PDL_INTC_VECTOR_RXI3 Data received PDL_INTC_VECTOR_TXI3 SCI channel 3 Start of next data transfer PDL_INTC_VECTOR_TEI3 End of data transfer PDL_INTC_VECTOR RXI12 PDL_INTC_VECTOR TXI12 PDL_INTC_VECTOR TEI12 SCI channel 12 Data received Start of next data transfer End of data transfer PDL_INTC_VECTOR_GTCIAO PDL_INTC_VECTOR_GTCIBO PDL_IN
475. te Dead time 00b Normal error detection Other Protected due to the Interrupt 0 Down O Stopped GTCCRA value at buffer transfer skipping 1 Up 1 Counting 01b GTCCRA 0 Po counter 10b GTCCRA 2 GTPR at trough i 11b GTCCRA 2 GTPR at crest b7 b6 b5 b4 b3 b2 bi bO Event detection Compare match Input capture or compare match Underflow Overflow F E D C B A 0 Not detected 1 Detected If any register value is not required specify PDL_NO_PTR data3 A pointer to where the Timer counter register value shall be stored data4 A pointer to where the General register A value shall be stored data5 A pointer to where the General register B value shall be stored R20UT2201EE0211 Rev 2 11 EN ESAS Page 208 of 418 Sept 12 2014 RX63T Group Description 2 2 Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 4 Library Reference data6 A pointer to where the General register C value shall be stored data7 A pointer to where the General register D value shall be stored data8 A pointer to where the General register E value shall be stored data9 A pointer to where the General register F value shall be stored data10 A pointer to where the Cycle setting register value shall be stored data11 A pointer to where the Cycle setting buffer register value shall be stored d
476. terrupt vectors for high pin package 79 82 INTC Update group interrupt 340 INTC Update usage example 191 214 GPT Added extra channels unit support for bigger pin package 294 308 ADC_12 add new option and unit support for bigger pin package 97 R_MCU_GetStatus update date1 92 MPC MPC register definitions 156 R_MTU3_Set Add new macro definition 270 284 IIC Add a new channel option for bigger pin package 233 SCI Delete a wrong pin 236 SCI Add MTU3 clock source selection for bigger pin package 365 388 SCI Update usage example 92 MPC add note for Multifunction Pin Controller 64 INTC Update external interrupt 232 R_IWDT_Set Add a remark 145 146 DTC Add lack trigger for bigger pin package 184 R_MTU3_ReadChannel Add a remark 239 240 R_SCI_Receive Add continuous receive mode 178 179 R_POE_Set Correct macro and remove redundant information 79 R_IO_PORT_ReadControl add description in data3 and remark 81 R_IO_PORT_ModifyControl add description in data3 and remark 313 R_ADC_10_ Control remove redundant comment 338 LPC revise wrong comments of sample code 48 R_CGC_Set Change BCLK pin limit 66 69 INTC Update parameter name 271 283 SPI Update description in data1 of all APIs and update description in data3 of R_SPI_Set 310 ADC_10 Add type description for data4 78 R_IO_PORT_Set Add a remark Apr 05 2013 30 GPT Modify number of channel from four to eight 186 209 GPT Update packages descri
477. terrupts and main at same time R_POE_Set Updated the description for date3 R_DMAC_Create Updated the program example R_DTC_Set Edit remark of data2 R_DTC_Create Updated the program example Sep 28 2012 R_DTC_Control Updated the second program example R_MTU3_Set Amended the program example R_MTU3_Destroy Amended the program example R_BSC_Create Updated the description for data1 data2 and data3 R_POE Create Updated the description for func2 and func5 R_GPT_Set Amended the program example R_GPT_CreateUnit Added support for DMAC activation R_GPT_CreateUnit Amended the program example R_GPT_CreateChannel Added support for DMAC activation R_GPT_CreateChannel Updated the description for data11 data12 data13 and data14 R_GPT_ControlChannel Amended the program example R_GPT_ControlUnit Amended the program example R_SCI_Set Amended the program example R_SCI_Create Modified the description of data3 R_ADC_12 CreateChannel Corrected the program example R_ADC_12 Read Updated the description for data3 Modified the IO Port usage example Updated the DTC usage example 1 No RTOS Support sentence added 2 00 Oct 31 2012 3 Updated screen shots of batch copy utility 49 51 R_CGC_Set Added support for packages with 100 pins or more R20UT2201EE0211 Rev 2 11 QEN ESAS Revision history 1 Sept 12 2014 RX63T Group 52 76 77 78 80 98 179 222 222 248 280 294 42 47 312 315 397 337 339 41 47
478. the RX CPU R20UT2201EE0211 Rev 2 11 RENESAS Page 15 of 418 Sept 12 2014 RX63T Group 1 Introduction 1 5 Acronyms and abbreviations Full Form Analog to Digital Converter Application Programming Interface Binary Coded Decimal Binary digit Bits per second Bus State Controller Controller Area Network Clock Generation Circuit CMOS Complementary Metal Oxide Semiconductor CMT Compare Match Timer CPU Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Direct Current Direct Memory Access DMA Controller Digital Signal Processing Data Transfer Controller Electrically Erasable and Programmable ROM First In First Out General PWM Timer Global System for Mobile communications High performance Embedded Workbench Inter Integrated Circuit Interrupt Controller Input Output IWDT____ Independent WDT Kilo Byte 1024 bytes Low speed On Chip Oscillator Low Power Consumption Least Significant Bit Mega Byte 1024 kB Microcontroller Unit Multifunction Pin Controller Most Significant Bit Multi function Timer pulse Unit Non Maskable Interrupt Option Function Select Peripheral Driver Generator Phase Locked Loop Port Output Enable Programmable Pulse Generator Pulse Width Modulation Random Access Memory Read Only Memory Renesas Peripheral Driver Library Renesas SPI Serial Communications Interface Synchronous Dynamic RAM System Management Bus Serial Peripheral Interface Universa
479. the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call R20UT2201EE0211 Rev 2 11 EN ESAS Page 140 of 418 Sept 12 2014 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h include lt string h gt const char source_string_1 Renesas RX63T Volatile char destination string Ll is eke ks ete edhe Seek de ees me void func void Re enable transfers on channel 2 R_DMAC_Control DMAC_ENABLE L_NO_PTR L_NO_PTR L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA L_NO_DATA Y o UU DDN OOo k K R KA kl S Reload and trigger channel 1 R_DMAC_Control 1 PDL_DMAC_ENABLE PDL_DMAC_START PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE DESTINATION PDL_DMAC_UPDATE_COUNT PDL_DMAC_UPDATE_SIZE source_string_l destination_string_l 1 uint16_t strlen source_string_1 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA R20UT2201EE0211 Sept 12 2014 Rev 2 11 EN ESAS Page 141 of 418 RX63T Group 4 Library Reference 4 R_DMAC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept
480. the register is not selected TGRC_TGRU_value For n 0 3 4 6 and 7 The register TGRC value For n 5 The register TGRU value This will be ignored if the register is not selected TGRD_TGRV_value For n 0 3 4 6 and 7 The register TGRD value For n 5 The register TGRV value This will be ignored if the register is not selected TGRE_TGRW_value For n 0 3 4 6 and 7 The register TGRE value For n 5 The register TGRW value This will be ignored if the register is not selected TGRF_value For n 0 4 and 7 The general register TGRF value This will be ignored if the register is not selected TADCOBRA_value For n 4 and 7 ADC start request cycle set buffer A This will be ignored if the register is not selected TADCOBRB_value For n 4 and 7 ADC start request cycle set buffer B This will be ignored if the register is not selected True if the channel number is valid otherwise false Multi function Timer Pulse Unit R_MTU3_Create R_MTU3_ControlUnit e Before calling this function use R_MTU3_Create to configure the channel operation e Either this function or R_MTU3_ControlUnit must be used to start the timers e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call Rev 2 11 EN ESAS Page 168 of 418 RX63T Group 4 Library Reference
481. tion Description Transition to one of the low power modes data Control selection All selections are optional If multiple selections are required use to separate each selection e Mode selection PDL_LPC_MODE SLEEP or PDL_LPC_ MODE ALL MODULE _CLOCK_STOP or PDL_LPC_MODE_SOFTWARE_STANDBY or PDL LPC_ MODE DEEP SOFTWARE STANDBY Select the mode to be entered Check the Remarks section for any restrictions 1 O port retention cancellation PDL_LPC_IO_ RELEASE Cancel the retention of I O port pin states Return value True if all parameters are valid and exclusive otherwise false Category LPC References R_LPC_Create Remarks Sleep mode is utilised by some peripheral drivers to turn off the CPU when required R20UT2201EE0211 Sept 12 2014 When entering software standby or deep software standby mode the oscillation stop detection function is disabled The detection is re enabled if software standby mode is interrupted On exit from deep software standby mode the MCU is reset Do not set up the DMACA and DTC to rewrite any registers related to WDT while the chip is in sleep mode e If IWDT is stopped do not set up the DMACA and DTC to rewrite any registers related to IWDT while the chip is in sleep mode e If a condition for the independent watchdog timer to stop counting applied at the time of a transition to
482. tion flags shall be stored in the format below Specify PDL_NO_PTR if the flags are not to be read b7 b5 b4 b3 b2 b1 bO External trigger IWDTCLK counter edge 0 Falling Rising Overflow Deviation limit IWDTCLK divided rising edge 0 Not detected 1 Detected If any register value is not required specify PDL_NO_PTR data3 A pointer to where the IWDTCLK counter LCNT register value shall be stored data4 A pointer to where the IWDTCLK count result average LCNTA register value shall be stored data5 A pointer to where the IWDTCLK count upper permissible deviation LCNTDU register value shall be stored data6 A pointer to where the IWDTCLK count lower permissible deviation LCNTDL register value shall be stored data7 A pointer to where the IWDTCLK count result LCNTxx registers value shall be stored Provide space for 16 sixteen bit values True General PWM Timer unit None Ifthe flags are read any flag that has been set to 1 shall be automatically cleared to O by this function Rev 2 11 EN ESAS Page 211 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_gpt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint16_t iwdtclk_counter uint16_t iwdtclk_counter_result_average uint16_t iwdtclk_counter_upper_limit uint16_t iwdtclk_counter_lower_limit uin
483. tions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions void func void uint8_t data_to_restore R_PDL_LPC_BACKUP_AR Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_ARI True if all parameters are valid otherwise false wh EA SIZE EA SIZ Rev 2 11 ENESAS The definition R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are Page 119 of 418 RX63T Group 4 Library Reference 5 R_LPC_GetStatus Synopsis Read the status flags Prototype bool R_LPC_GetStatus uint32_t data Data pointer Description Read the Low power status flags data The status flags shall be stored in the format below Interrupt flags of IRQ6 DS pin and IRQ7 DS pin are supported on 100 pin 112 pin 120 pin 144 pin packages only b31 b24 0 b23 b22 b20 b19 b18 b17 b16 Event detection flags 0 not detected 1 detected An interrupt has caused an exit Poweron from deep software standby mode 0 LVD2 LVD1 LVDO reset followed by an internal reset b15 b13 b12 b11 b10 b9 b8 Deep Software Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by one of the following signals 0 NMI 0 LVD2 LVD1 b7 b6 b5 b4 b3 b2 b1 bO Deep Software Standby cancel request det
484. ts callbacks Category References R_CGC_ Set Remarks reference R20UT2201EE0211 Sept 12 2014 Rev 2 11 EN ESAS Page 107 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_cac h RPDL device specific definitions include r_pdl_definitions h Callback functions void CAC_frequency_error void void CAC_measurement_complete void void CAC_overflow void void func void Use the main clock to check the IWDTLOCO accuracy R_CAC_Create PDL_CAC_REFERENCE MAIN PDL_CAC_ REFERENCE RISING PDL_CAC_REFERENCE_DIV_8192 PDL_CAC_MEASURE_IWDTLOCO PDL_CAC_MEASURE_DIV_1 PDL_CAC_LIMIT_TOLERANCE PDL_NO_DATA PDL_NO_DATA 10 10 CAC_frequency_error CAC_measurement_complete CAC_overflow 10 R20UT2201EE0211 Rev 2 11 EN ESAS Page 108 of 418 Sept 12 2014 RX63T Group 2 R_CAC Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 Stop the clock accuracy circuit bool R_CAC_Destroy void No parameter is required Disable and shutdown the Clock frequency accuracy measurement circuit True Clock frequency accuracy measurement circuit None e The CAC module is halted
485. tx void tx_end true Figure 5 26 Example of SCI Transmission code in Asynchronous Multi Processor mode R20UT2201EE0211 Rev 2 11 RENESAS Page 380 of 418 Sept 12 2014 RX63T Group 5 Usage Examples 5 17 8 SCI in SPI Mode This shows the setting of SCI channel 0 in to SPI master mode and the transmission of data using interrupts PDL functions include r_pdl_sci h include r_pdl_cgc h PDL device specific definitions include r_pdl_definitions h static void SCItx v id volatile bool data_sent false void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Please refer to 5 1 Clock Generation Circuit Set Channel 0 pin options R_SCI_Set 0 if defined DEVICE PACKAGE 64_ PIN amp amp defined DEVICE_PACKAGE_48_PIN PDL_SCI_PIN_SCIO_SMISOO_PB1 PDL_SCI_PIN_SCIO_SMOSIO_PB2 PDL_SCI_PIN_SCIO_SCKO_PB3 PDL_SCI_PIN_SCIO_SSO_PD7 else PDL_SCI_PIN_SCIO_SMISOO_P24 PDL_SCI_PIN_SCIO_SMOSIO_P30 PDL_SCI_PIN_SCIO_SCKO_P23 PDL_SCI_PIN_SCIO_SSO_P22 fendif i Create SPI master R_SCI_Create 0 PDL_SCI_SYNC PDL_SCI_SPI_MODE PDL_SCI_RX_DISCONNECTED PDL_SCI_CLK_INT_OUT 19200 1 0 Start sending data R_SCI_SPI_Transfer 0 PDL_NO_DATA 5 12345 SCItx PDL_NO_DATA PDL_NO_FU
486. ue if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU3_Create e Before calling R_MTU3_Create call this function to configure the relevant pins Make sure no more than one peripheral function is assigned to a single pin Make sure the configuration of MTCLK pins is consistent for all the channels There are some pin restrictions when not using the 64 pin device package or not using the package that is greater than 64 pin RPDL definitions include r_pdl_mtu3 h RPDL device specific definitions include r_pdl_definitions h void func void Configure the MTU pins R_MTU3_Set 0 PDL_MTU3_PIN_0A_P31 Rev 2 11 EN ESAS Page 155 of 418 RX63T Group 2 R_MTU3_Create Synopsis Configure an MTU channel Prototype bool R_MTU3_Create uint8_t data1 R_MTU3_Create_structure ptr R_MTU3_Create_structure members Description 1 9 R20UT2201EE0211 Sept 12 2014 uint16_t channel_mode uint32_t event_trigger_operation uint32_t counter_operation uint32_t ADC_trigger_operation uint32_t buffer_operation uint32_t TGR_A_B_ operation uint32_t TGR_C_D operation uint32_t T 4R_U_V_W_ operation uint16_t TCNT_TCNTU_value uint16_t TGRA_TCNTV_value uint16_t TGRB_TCNTW_value uint16_t TGRC_TGRU_value uint16_t TGRD_TGRV_value uint16_t TGRE_TGRW_value uint16_t TGRF_value uint16_t TADCORA_value uint16_t TADCORB_
487. uint32_t data2 Channel 0 pin selection uint32_t data3 Channel 1 pin selection Description 1 2 Set up the global SPI options R20UT2201EE0211 Sept 12 2014 data1 Select channel SPI For device packages with 48 or 64 pin this must be 0 for other packages 0 or 1 data2 Pin configuration for the channel 0 Use to separate each selection Specify PDL_NO_DATA if not required e Pin selection for channel 0 PDL_SPI_RSPCKA_P24 or PDL_SPI_RSPCKA_PA4 or Select the RSPCKA pin PDL_SPI_RSPCKA_PDO PDL_SPI_MOSIA_P23 or PDL_SPI_MOSIA_PBO or Select the MOSIA pin PDL_SPI_MOSIA_PD2 PDL_SPI_MISOA_P22 or PDL_SPI_MISOA_PA5 or Select the MISOA pin PDL_SPI_MISOA_PD1 PDL_SPI_SSLAO_P30 or PDL_SPI_SSLAO_PA3 or Select the SSLAO pin optional PDL_SPI_SSLAO_PD6 PDL_SPI_SSLA1_P31 or PDL_SPI_SSLA1_PA2 or Select the SSLA1 pin optional PDL_SPI_SSLA1_PD7 PDL_SPI_SSLA2 P32 or PDL_SPI_SSLA2_ PEO or Select the SSLA2 pin optional PDL_SPI_SSLA2 PA1 PDL_SPI_SSLA3_P33 or PDL_SPI_SSLA3_PE1 or Select the SSLA3 pin optional PDL_SPI_SSLA3 PAO Rev 2 11 EN ESAS Page 279 of 418 RX63T Group Description 2 2 Return value Category Reference Remarks Program example R20UT2201EE0211 Sept 12 2014 data3 4 Library Reference Pin configuration for the channel 1 Use to separate each selection Specify PDL_NO_DAT
488. uired data3 Specify a pointer to a variable where the self diagnostic result shall be stored Specify PDL_NO_PTR if this information is not required Refer to hardware manual Section 36 2 2 for the format of self diagnosis result True if a valid unit is selected otherwise false 10 bit ADC R_ADC_10 CreateUnit R_ ADC_10 CreateChannel Depends on the parameters supplied to R_ADC_10_CreateUnit and R_ADC_10_CreateChannel for configuration lf analog channels are selected as the input source valid array pointer should be supplied to data2 If self diagnostic is enabled the respective result will be stored to data3 Ensure that the storage area is big enough for the requested number of results The format of values stored to the array is specified using R_ADC_10_CreateUnit If no callback function is used this function waits for the IR flag to indicate that conversion is complete before reading the results e This function is supported on 100 pin 112 pin 120 pin 144 pin packages only RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t adc_results 20 uint16_t diag_result Read the ADC R_ADC_10_Read 0 adc_results amp diag_result Y Rev 2 11 EN ESAS Page 322 of 418 RX63T Group 4 Library Reference 4 2 25 10 bit Digital to Analog Converter 1 R_DAC 10 Create Synopsis Protot
489. unction specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create Rev 2 11 True if all parameters are valid and the operation completed without errors False if a parameter was out of range or if the channel was already transmitting or if an error occurred during transmission SCI R_SCI_Control R_SCl_GetStatus ztENESAS Page 244 of 418 RX63T Group 4 Library Reference Remarks R20UT2201EE0211 Sept 12 2014 The compiler adds a null character to the end of string constants If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared In Multi processor mode R_SCI_Send is to be called in pair the first one is to send ID ID cycle the second one is to send data Data cycle For ID transmission it will be sent by internal polling operation For Data transmissi
490. up each required area and then call R_BSC_ Create This function is not required when using 64 pin and 48 pin package The endian mode of the CPU is selected by the MDE bits in the MDES or MDEB registers Multifunction Pin Control registers are modified by this function The cycle count parameters are not checked for validity Use the hardware manual to check these values Setting single write strobe mode is prohibited in the 8 bit bus space Rev 2 11 EN ESAS Page 128 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Configure CS2 8 bit width maximum cycle counts R_BSC_CreateArea 2 PDL_BSC_WIDTH_8 15 T5 7 7 R20UT2201EE0211 Rev 2 11 RENESAS Page 129 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 R_BSC_Destroy Synopsis Stop the External Bus Controller Prototype bool R_BSC_Destroy uint8_tdata Area selection Description Disable an external bus area data Select the external bus area CSn where n 0 to 3 to be disabled Return value True Category Bus Controller Reference R_BSC_Control Remarks e error interrupt request will not be disabled by this function Use R_BSC_Control to isable it e Multifunction Pin Control registers are modified by this
491. urn value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Write data to an I O port bool R_IO_PORT_Write uint16_tdata1 Port or port pin selection uint8_t data2 The data to be written to the I O port or port pin Write data to an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value must be between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port None e f an invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the output of port pin P22 R_IO_PORT_Write PDL_IO_PORT_2 2 0 i Set the output of port B R_IO_PORT_Write PDL_IO_PORT_B 0x55 i Rev 2 11 ENESAS Page 87 of 418 RX63T Group 4 Library Reference 6 R_IO_PORT_Compare Synopsis Prototype Description Return value Category References Remarks Program example R20UT2201EE0211 Sept 12 2014 Check the pin states on an I O port bool R_IO_PORT_Compare uint16_tdata1 Input port or port pin selection uint8_t data2
492. wo cycles of the PDL_SPI_NEXT_DELAY_4 or peripheral clock between the end of one frame and the PDL_SPI_NEXT_DELAY_5 or start of the next frame PDL_SPI_NEXT_DELAY_6 or Ignored in Slave mode PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 Rev 2 11 Page 282 of 418 ENESAS RX63T Group 4 Library Reference Description 3 3 data5 The format must be either e The maximum required bit rate Or e b31 b30 to b8 b7 b0 1 0 The SPBR register value If only Slave mode will be used specify PDL_NO_DATA Return value True if all parameters are valid otherwise false Category SPI Reference R_CGC_Set R_SPI_Set R_SPI_Command Remarks Function R_CGC_Set must be called with the current clock source selected before using this function R_IO_PORT_Set can be used to select between CMOS and Open drain output Function R_SPI_Set must be called before any use of this function The actual bit rate will be reduced if division gt 1 is specified in R_SPI_Command Program example RPDL definitions tinclude r_pdl_spi h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure SPI channel 0 R_SPI_Create 0 PDL_SPI_MODE_SPI_MASTER PDL_SPI_PIN_SSLO_LOW PDL_SPI_FRAME_1_1 PDL_NO_DATA 2E6 R20UT2201EE0211 Rev 2 11 2tENESAS Page 283 of 418 Sept 12 2014 RX63T Gr
493. y output control make sure the operation of the corresponding channel is stopped Select one option for each output PDL_MTU3_OUT_P_ PHASE 1 ENABLE or For channels 3 and 4 control MTIOC3B PDL_MTU3_OUT_P PHASE 1 DISABLE For channels 6 and 7 control MTIOC6B PDL_MTU3_OUT_N PHASE 1_ ENABLE or For channels 3 and 4 control MTIOC3D PDL_MTU3_OUT_N PHASE 1 DISABLE For channels 6 and 7 control MTIOC6D PDL_MTU3_OUT_P_ PHASE 2 ENABLE or For channels 3 and 4 control MTIOC4A PDL_MTU3 OUT P PHASE 2 DISABLE For channels 6 and 7 control MTIOC7A PDL_MTU3_OUT_N PHASE 2 ENABLE or For channels 3 and 4 control MTIOC4C PDL_MTU3_OUT_N PHASE 2 DISABLE For channels 6 and 7 control MTIOC7C PDL_MTU3_OUT_P_ PHASE 3 ENABLE or For channels 3 and 4 control MTIOC4B PDL_MTU3_OUT_P PHASE 3 DISABLE For channels 6 and 7 control MTIOC7B PDL_MTU3_OUT_N PHASE 3 ENABLE or For channels 3 and 4 control MTIOC4D PDL_MTU3_OUT_N PHASE 3 DISABLE For channels 6 and 7 control MTIOC7D Or all six phase outputs can be controlled together by selecting one of each PDL_MTU3_OUT_P PHASE ALL ENABLE or All P phase outputs PDL_MTU3 _OUT_P_PHASE_ALL_DISABLE p puts PDL_MTU3_OUT_N_PHASE ALL ENABLE or All N phase outputs PDL_MTU3_OUT_N_PHASE ALL_DISABLE p puis Output inversion control applies only to reset synchronised or complementary PWM modes Each phase output can be configured fo
494. y this function Page 142 of 418 RX63T Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t StatusValue uint32_t SourceAddr Read the status and current source address for channel 2 R_DMAC_GetStatus 2 amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT2201EE0211 Rev 2 11 RENESAS Page 143 of 418 Sept 12 2014 RX63T Group 4 Library Reference 4 2 12 Data Transfer Controller 1 R_DTC Set Synopsis Prototype Description Return value Category Reference Remarks R20UT2201EE0211 Sept 12 2014 Program example Set the Data Transfer Controller options bool R_DTC_ Set uint8_t data1 Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Read skip control PDL_DTC_READ SKIP_DISABLE or Disable or enable skipping of transfer data read PDL_DTC_READ_SKIP_ENABLE when the vector numbers match e Address size control PDL_DTC_ADDRESS FULL or PDL_DT
495. ype Description Return value Category References Remarks R20UT2201EE0211 Sept 12 2014 Configure the 10 bit DAC module bool R_DAC_10_Create uint8_t data1 Configuration uint16_tdata2 Output value uint16_tdata3 Output value Enable the DAC module and set the operating conditions data1 Configuration options To set multiple options at the same time use to separate each value The default settings are shown in bold e Channel enable PDL DAC_10 CHANNEL 0 Enable channel 0 PDL DAC_10 CHANNEL 1 Enable channel 1 Data alignment selection The alignment of the 10 bit output data within the 16 bit PDL_DAC_10_ALIGN_LEFT or parameters data2 and data3 PDL_DAC_10_ALIGN_RIGHT Left padded at the MSB end Right padded at the LSB end D A A D Synchronous Start Control PDL_DAC_10_ADC_SYNC_CONV_DISABLE or Disable or enable the D A A D PDL_DAC_10_ADC_SYNC_CONV_ENABLE synchronous conversion data2 The value to be written to the channel 0 output register Ignored if the channel is not enabled data3 The value to be written to the channel 1 output register Ignored if the channel is not enabled True if all parameters are valid and exclusive otherwise false DAC None e This function configures the relevant pin of selected channel for DAC operation This function brings the converter module out of th

RX63T Group Renesas Peripheral Driver Library User`s Manual

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