cameleon - Optomotive
Contents
1. C Xilinx L1 EDK EDK sw ue en eee eon le 4 Program Flash Memory F Se ee Tie C C Projects x SEa P g y eh jm Software repository associated with hardware design SEFT ENAT pE Z D Projekti Wincor EDK WNT_v1 1 SDK SDK_Export Eliz D Projekti Wincor EDK WNT v1 1 SDK SD iKON eee eee gt ae Lang User Defined Software R itori f microblaze 0 microblaze haan a na Ata Sa saemniats eS cameleon microblaze 0 sw platform sein ta ef 2 KAL IS ee microblaze 0 sw_pisttonm id Software Platform Settings H Q Archives Ye Generate Linker Script Ei microblaze_0 i oe libgen log E Bash Shell 4 test r n ATA le libgen mk Frest r n xil printf peripherals r toggle extern The order of precedence is X 1 user defined repositories in the order they appear enables Pixel 2 repository associated with hardware design enables Profi 3 repository provided by SDK toggle loopba toggle read o St arta rinne xil printf 2 xil printf xil printf xil printf xil printf 16 xil nrinrfi pa p jet SOPIAH Figure 9 Setting SDK repository search path We have noticed also one bug which occurs during download Program FPGA in SDK Choose again proper system bit system bd bmm and ELF in Program FPGA dialog window Program FPGA Program FPGA Program the FPGA connected to the JTAG cable interface a Bit and Emm2. OptoMotive OUI IOIO FPGA smart camera Developer Guide v1 2 Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 1 21 OptoMotive 1 Introduction Cameleon is an innovative USB camera based on FPGA system on chip SOC technology The camera with a powerful HSDK hardware software development kit opens ways for rapid customization and integration of various digital systems into camera itself The camera is a readymade solution but still open for a user to add his own features if he wishes so The true power of FPGA Field Programmable Gate Array over the sequential microprocessor is a pipelined parallel data processing Parallelism reduces system clock and power consumption considerably while boosting processing power With the latest set of tools from Xilinx System Generator and Accel DSP you can rapidly develop DSP algorithms even in MathWorks Matlab The current integrated image processing is focused on laser line detection laser triangulation The image processing is used to reduce required bus bandwidth which enables usage of multiple cameras on the same bus Key camera features e Industrial vision proven CMOS sensor e Up to 4 sensors per one camera perfectly synchronized e Can capture video or processed information profiles e Since the image processing is integrated inside the camera the host comp
3. info optomotive si www optomotive si page 11 21 OptoMotive sensor c source for common sensor functions utils h header for utils mainly timer functions utils c source for utils mainly timer functions mtXXXXX h header for sensor type specific sensor functions XXXX is a sensor type mtXXXXX c source for sensor type specific sensor functions XXXX is a sensor type The system operation is as following e Initialize the system in the following order Detect and initialize the imaging sensors Initialize the OMCAM structure Initialize the image storage buffers o Initialize the interrupts e Wait for command to be input to Control_FIFO either from UART terminal or i2c_slave_int_handler The XPS_I2C_SLAVE triggers interrupt when 12 bytes are received from FX2 USB microcontroller When the command is executed the Microblaze sends trigger to FX2 USB microcontroller by writing to MB2FX2_REG1 e Execute received instruction usually begin image transmission O O Upon image transmission instruction RunPixels and StartTransfer function are called The RunPixels initializes transmission by clearing memory buffers and setting proper transmission mode Immediately by calling StartTransfer the data from imaging sensor is transmitted to internal memory using DMA The image transmission to internal memory is fully automatic circular buffer The captureN int handler interrupt routines are triggered after each frame They are used
4. Files Save and Program Cancel Figure 10 Program FPGA dialog window Press Save and program If nothing happens for 1 minute than kill the process javaw exe in Windows Task Manager Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 10 21 OptoMotive Try to rerun Export HW design to FPGA in XPS and Program FPGA again If it still does not work either reset the computer and try again or download bistream using XPS The other option which usually works is to download bistream using XPS Click on Download Bitstram to FPGA botton in XPS An pie Edit View Poyect Heydar Software Deere Confeqguntem Debug Simuliion Wondew Help OF Bd S O BS XDOxe saja BOGHRS SAS BH SD f Appiano Dex P L L a Bin inim eorn Ara hel Softee Progects L Marni H Default mengelolah Project demo a Processor meceoblana 0 koscuteka Do Propet encore Were SIT ew idern et ane Wether Add heat Applen Propect_ Wi Dabu et eae 0 Bn i i j mirobiam dlmak il mb pit i 44 kab ore 3 DUR AAN m Cree UI i F ah berak bre rm 2 Header Fi Ja J gpu da an f IE Project bocblaadar 1 debyg module 2 Processor meceoblare 0 ie 2 aga Bose ubah DO Projek ino IDC PET wle bana 1 i fi 1 ape fe 3 Coempdier Optics 1 3 LED a a api ede ak O 3 ep ai i i a A om
5. Table 4 PCB modifications for using P3 connector int T i 1 t vas uw 3 an Lie s TA p Wis biis bite bi reve tere orie t Figure 17 PCB modification top board revision 1 Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 20 2 OptoMotive Figure 19 PCB modification only on bottom board revision 1 2 8 Revision history Rev Date Author Description 1 2 3 8 20101 AG Updated to Xilinx tools v1 2 and added system description Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 2 1 21
6. Window Help JAK JEER se AE ee E EAE E MNS E E E O E Project Information Area x P E Tana a B faces Ports Addresses Project Applications IP Catalog A E N Bus Connection IP Type IP Version x Platform microblaze 710d Project Files Imb_v10 1 00 a MHS File system mhs Imb_v1Q 1 00 4 MSS File system mss pib_v46 Lia UCF File data system ucf Imb bram if enti 210 iMPACT Command File etc download cmd Imb_bram_if_ent 2 10 Implementation Options File etc fast runtime opt mpmc 403 4 Bitgen Options File etc bitgen ut bram block 1 00 4 amp Project Options apture_dma_mux 1 00 Device xc3s1 600efg320 4 dm 100d Netlist TopLevel output_dma_fifos 1 00 4 Tp 1 00 2 Implementation XPS Xplorer HDL VHDL apio Sim Model BEHAVIORAL xp Da Reference Files ps 0 a Log Files xp Na E Synthesis Report Files Nps Da Rpa a xps Fr a xpa a Xps 10 b xp3 steppet Ia 2 b ps limet J p 435232 xps uartlite 100a chipscope_icon_0 chipscope_icon 1 02 4 chipscope_ila_ chipscope_ila 1 02 4 clock_generafor_0 clock generator 2 01 4 gt pircik dem dcm module 1 00 d Ww Figure 6 Opening the SDK project In XPS from version 11 x and later make sure you select Include bitstream and BMM file and then press Export and Launch SDK button If you have moditied hardware and SDK is already opened press Export Only button Cameleon Developer Guide v1 2 Optomotive mehat
7. image line de multiplexing The image processing core XPS_PEAK processes the image line coming from DMA_FIFOS and outputs 32 bit 3D point per one image line The processed data is buffered inside DDR SDRAM and send to USB through XPS FX2 If the rotation and 3D processing is not needed BASE clean project the then XPS_NPI_DMA is connected directly to XPS_FX2 But this way only 32 bit DMA implementation is possible When transferring raw image to USB port the data is transferred directly from DMA engine to XPS_FX2 The XPS_I2C_SLAVE is used to send commands from the PC to the MicroBlaze low speed communication through I2C Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 6 2 OptoMotive The XPS MCH IIC peripheral is used to communicate with imaging sensors It has the ability to send commands to multiple sensors at the same time different cable lengths are also supported by using independent sync clock The XPS_STEPPER core is used in conjunction with stepper motor driver and takes care for image synchronous motor rotation The integrated motor driver core simplifies the system integration The XPS_STEPPER core unfortunately does not support acceleration and deceleration Standard EDK cores are used to communicate with RS232 XPS UARTLITE SPI FLASH XPS_SPI 2 ra x N IPLB DPLB XPS_U
8. o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 3 21 OptoMotive 3 Pre requisites Before starting with the camera software modification you need Cameleon camera USB cable Installation software downloaded from www optomotive si For camera firmware development o Xilinx JTAG Download Debug cable Platform Cable USB II recommended o Xilinx ISE 10 1 03 or higher o Xilinx EDK 10 1 03 or higher o Xilinx SDK 10 1 03 or higher Recommended also Xilinx Chipscope Pro 10 1 or higher Microsoft MS Visual C 2008 Express Edition or higher for API DLL development free download from www microsoft com express Qt SDK by Nokia v2009 02 or higher for QtCamera development free download from www qtsoftware com The camera is based on a Trenz Electronic TEO300 Industrial Micromodule Before proceeding we recommend to read the module User Manual htto www trenz electronic de products fpga boards trenz electronic industrial micromodules html It contains important information about connection the module to debug cable manual SPI FLASH programming and DIP switches information The DIP switches can help you to restore the system if FLASH or EEPROM contain no valid booting data 4 EDK project Embedded System on Chip The EDK project is located in distibution N EDK project_name_version To open the project and invoke Xilinx Platform Studio XPS you have to double click on th
9. 21 OptoMotive 2 Building blocks The camera is composed of a 3 basic parts e FPGA System on a module e Base sensor board e Head sensor board All of the vital system components are assembled on a module This includes power supply FPGA DDR SDRAM USB controller and SPI Flash Figure 1 The module is USB powered with triple DC DC converters for maximal power efficiency SMPS Switching Mode Power Supply in Figure 1 The core is a Spartan FPGA with DDR SDRAM The DDR has 16 bit optional 32 bit wide data bus running at 100 MHz offering 400 optional 800 MB s peak bandwidth The gateway to the PC is a well proven Cypress CY7C68013A also known as FX2 USB microcontroller which offers up to 36 MB s of bandwidth from FPGA to PC in bulk mode The link between FPGA and FX2 is 8 bit wide and runs at 48 MHz The FX2 is also connected to FPGA through lC which is used as a command interface The board also includes non volatile SPI FLASH memory The SPI bus is shared by FPGA and FX2 which is necessary to enable USB tirmware upgrade and FPGA booting The system board is connected to the base board through two board to board connectors 1 2V SMPS DDR SDRAM 4Mbyte SPI FLASH 2 5V SMPS 3 3V SMPS i 0 USB 2 0 HIGH SPEED XILINX Cypress FX2 in SPARTAN USB i i troller FPGA microcon optional IO extension simple IO I2C stepper Figure 1 Camera structure block scheme Cameleon Developer Guide v1 2 Optomotive mehatronika d o
10. ABLES TO THIS CONNECTOR REVERSING POWER POLARITY OR OVER VOLTAGE WILL CAUSE A PREMATURE DEATH OF THE CAMERA Table 3 Connector P3 pinout Standard USB cable colours 5V 46V Red USB Data USB Data CHASIS GND SHIELD Header connector P3 is a 5 pin 2 54 mm 100 mil pitch connector compatible with the following industrial USB connectors e Bulgin Mini USB Buccaneer PX0443 IP68 B type Mini USB front panel mounted 5 way crimp connector at rear Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 8 21 OptoMotive se Figure 15 Bulgin PXO443 front panel connector e Bulgin Mini USB Buccaneer PXO446 recommended IP68 B type Mini USB rear panel mounted 5 way header connector at rear Figure 16 Bulgin PXO446 rear panel connector Before connecting the USB to P3 the PCB modifications should be made according to following table and the two figures as a reference ONLY SKILLED WORKERS SHOULD DO THE SOLDERING TOO LONG SOLDERING OR TOO HOT TIP MAY DAMAGE THE PCB TO REMOVE THE SHORT CIRCUIT WE RECOMMEND USING DESOLDERING WICK BRAID Be careful to look at the pictures for correct board revision Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 19 21 OptoMotive
11. ARTLITE FPGA FABRIC CUSTOM CORE _ Figure 4 Fully featured FPGA system on chip architecture For documentation on specific core including Optomotive custom cores right click on the core in XPS in the System Assembly or in the IP Catalog window Then select View PDF Datasheet if available Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 7 2 1 OptoMotive es Name Bus Name microblaze 0 dimb iimb mb_pib dimb cntir ilmb ontir DDR SDRAM Imb bram capture dma mux 0 debug module regist 0 Bh Configure IP LED xps ic slave O xps image capture O xps image capture 1 xps image capture 2 J xps intcO 5 ar mna Driver xps_fx2_v1_00_a gt View MPD View PDF Datasheet Browse HDL Sources J3 xps npidma 0 j SPI FLASH xp3 timer O Delete Instance Make This IP Local m a D 8 Bl B1 8888 88 8 8 Figure 5 Opening core datasheet 5 SDK project Embedded System Software To open the Cameleon SDK project click on the Launch Platform Studio SDK icon in Xilinx Platform Studio w Xilinx Platform Studio E Projekti Cameleon EDK BASE_v0 8 0 0 system xmp System Assembly View1 fo eX File Edit View Project Hardware Software Device Configuration Debug Simulation
12. aa aapi I ul a api ore cet 7 NES a a yi eh ar 4 lie ue iie a api api dmna D we a SP FLASH e a es birer 0 a In I 1 Project Aogktatone IP Catalog gt Start Up Page x Deng Surry Figure 11 Downloading merged bitstream using XPS Just make sure that Project cameleon is marked to initalize BRAM right click on Software project This way XPS takes SDK generated executable Microblaze software ELF merges it with hardware bitstream and downloads to FPGA 5 1 Embedded software description The SDK project Cameleon project SDK SDK_Workspace cameleon is divided in the tollowing files cameleon Id cameleon bram Id main c control fifo h control fifo c datatype h dma func h dma_func c func h func c interrupts h interrupts c sensors h Cameleon Developer Guide v1 2 linker script for mapping software to DDR SDRAM linker script for mapping software to internal Block RAM source file of main routine header for control FIFO which is used to buffer global commands source for control FIFO which is used to butter global commands header for global structure definition OMCAM all global variables header for DMA functions source for DMA functions header for commonly used functions source for commonly used functions header for interrupt routines source for interrupt routines header for common sensor functions Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914
13. cameleon E system make 12KB MAKE File 8 1 2009 7 53 PM settings ISI system_incl make 13KB MAKE File 8 1 2009 7 53 PM 5 Debug i system mhs 21KB MHS File 7 19 2009 10 41 AM implementation l3 system mss 3KB MSS File 7 11 2009 11 59 PM microblaze_0_sw_platform Jplatgen opt 1KB OPT File 7 19 2009 7 37 PM a O sw leo xInx auto O restore 40KB RESTORE File 11 9 2008 5 37 PM synthesis aj _impactbatch log SKB Text Document 8 1 2009 7 58 PM test_hw 8 bitinit log 7KB Text Document 8 1 2009 7 58 PM H 5 TestApp_Memory clock_generator_0 log 3KB Text Document 7 19 2009 7 35 PM E E TestApp_Peripheral coregen log 1KB Text Document 7 19 2009 10 44 AM 63 xInx auto 0 xdb Jlibaen log 49KB Text Document 7 19 2009 11 30 AM E OtCamera Ka plataen log 51KB Text Document 7 19 2009 7 37 PM Ready2use system log 507 KB Text Document 7 19 2009 7 58 PM USB driver tim 69KB Xilinx ISE Project 7 19 2009 10 44 AM E USBFWUTool 3KB Xilinx Platform Studi 7 19 2009 9 02 AM Figure 2 Opening the EDK project The system xmp file is an entry point to any EDK project It contains information about target FPGA custom peripheral depository location and other files location etc THIS FILE SHOULD NOT BE MODIFIED BY HAND UNLESS YOU KNOW WHAT YOU ARE DOING To manage hardware project use the Xilinx Platform Studio XMP instead The hardware project is defined by system mhs hardware composition and system ucf system signals to exter
14. e system xmp in project folder in Windows Explorer Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 4 2 OptoMotive 5 Cameleon_ 1 1 C pcores File Folder 7 28 2009 9 40 PM E CAM API S PREPARE_Fw File Folder 7 28 2009 9 33 PM Doc SDK _projects File Folder 7 28 2009 9 31 PM a EK sw File Folder 7 28 2009 9 31 PM S Base_v0 8 0 1 synthesis File Folder 7 28 2009 9 31 PM amp xps test_hw File Folder 7 28 2009 9 30 PM E _xmsgs OTestApp Memory File Folder 7 28 2009 9 30 PM bikdiagram LO TestApp_Peripheral File Folder 7 28 2009 9 30 PM E Chipscope xInx_auto_0_xdb File Folder 7 28 2009 9 30 PM data E system mhs bak 21KB BAK File 3 31 2009 2 46 PM E drivers E xmd ini bak 1KB BAK File 2 13 2009 2 24 PM Get El download bit 729KB BIT File 6 2 2009 1 36 PM hdl E system bit 729KB BIT File 6 2 2009 1 36 PM E IMPACT _ E system bsb 3KB BSB File 3 10 2008 9 22 PM implementation xmd ini 1KB Configuration Settings 2 13 2009 6 40 PM E E microblaze 0 chipscope ila O cdc SKB DesignCenter Previ 7 19 2009 10 45 AM pcores E logs 2KB File 7 19 2009 10 44 AM DB PREPARE _FW E wizlog OKB File 3 10 2008 9 21 PM amp SOK projects ed tx_addr_fifo_fifo_g 1KB LSO File 7 19 2009 10 44 AM HI SDK_metadata i tx_fifo_fifo_genera 1KB LSO File 7 19 2009 10 42 AM S
15. eleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 14 21 OptoMotive 7 Connectors The camera base board has 3 connectors besides mini USB and JTAG connector on TEO300 FPGA board e P 2x20 pin1 27 mm header for additional sensor head connection e P22x 17 pin 2 54 mm header for connection of add on boards e P3 5 pin 2 54 mm free pads for industrial USB cable connection BEFORE ATTACHING EXTERNAL USB CABLE READ CAREFULLY SECTION 0 ALL I O PINS ARE 3 3V LVTLL AND ARE NOT TOLERANT Output I O pins on P1 and ALL I O pins on P2 are 100Q serially terminated to reduce noise Se kanna pin in P pin Figure 13 Camera baseboard connectors Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 15 21 OptoMotive 7 1 PI pinout The connector P1 is used to connect 40 pin ribbon cable for an additional sensor head It contains dual power 5V and 3 3V 20 I Os and multiple ground signals for improved noise immunity The pin HEAD_RESET_N is currently held static 3 3V Table 1 Connector P1 pinout 14 11 E 9 9 _ 10 10 8 6 7 7 E D A A A E F E E D F E D F AIA AN EN Lae E9 MEAD SYCLK Elo D10 F8 E D7 7 6 8 Cameleon Developer Guide v1 2 Op
16. lose SDK e Delete SDK SDK_Export hw do not delete SDK SDK_Export sw since it contains custom drivers Delete SDK SDK_Workspace metadata Delete SDK SDK_Workspace microblaze_O_sw_platform Click Export HW design to FPGA in XPS In SDK Menu gt File gt New gt Software Platform Project name microblaze O sw plattormx and press finish Import project cameleon to workspace Menu gt File gt Import Click Existing SDK project into Workspace Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 9 2 OptoMotive The other solution is to use external custom cores directory pcores and drivers When using external repository make sure that Software Repositories search path is set properly prior re compiling project Select menu Tools gt Software Repositories At Software Repositories window select proper User Defined Software Repositories by clicking Edit Select one directory up directory EDK from MyProcessorIPLib which is the actual repository for drivers Configure Software Repositories File Edit Refactor Navigate Search Project Hardware Design Run Window Help rs ian EH By 4 2 Rt Configure ITAGS ttings G e 4 Add change or remove software repositories E Fie C C a Program FPGA Ctri Shift D Software repository provided by SDK
17. nal FPGA pinout mapping The system mhs can be edited using the XPS GUI or manually experienced users The system ucf can only be edited by hand To edit files by hand simply double click on the filename in the Project options tab Project Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si Cameleon Developer Guide v1 2 page 5 21 OptoMotive w Xilinx Platform Studio E Projekti Cameleon EDK BASE v0 8 0 01system xmp System Assembly View1 File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help JA X n EE an e a aA E a rE aa a a I EO LH Project Information Area x P L L Ts Bas lntartases Ports Addresses Project Appkestions IP Catalog Ie s e e ies ECT tee TP Version l Platform TE l i Ips cra ae 740d amp Project Files MHS File system mhs MSS File system mss UCF File data system ucf iMPACT Command File etc download cmd Implementation Options File etc fast_runtime opt Bitaen Options File etc bitgen ut Project Options Device xc3s1600efg320 4 i E wb eta Bam tt E DOAR SDRAM mpmc 4 03 a E S mi_bram bram_block 1 00 4 B gt capfure_dma_ona_0 capture_dma_mux 1 00 a Netlist TopLevel Implementation XPS Xplorer HDL YHDL 7 ske E output dma Kos O output_dma_fifos 1 00 4 Sim Model BEHAVIORAL amp Reference Files L
18. o BRAM for code execution Unfortunatelly this is limited to 32kB No caching is necessary for this option 1 Compile you SW project using a linker script that maps all code to BRAM usually included in SDK project 2 Mark the project to initialize BRAM to be loaded on power up 3 Download the bitstream to FPGA Program FPGA to generate merged bistream to verity the result Use PREPARE_FWU build_bram_SDK bat script to generate FIRMWARE FWU Disconnect JTAG before upgrade 6 Upload the FIRMWARE FWU via USB using the USBFirmwareUpgradeTool oS 6 2 For systems executing code from DDR SDRAM using bootloader The Microblaze system can also use DDR SDRAM for code execution The only limitation in this case is FLASH size 4MB Caching is almost necessary for this option for performance issues But you need a bootloader to transfer code from FLASH to DDR SDRAM and boot from there This procedure has been fully automated using the provided tools 1 Compile you SW project using a linker script that maps all code to DDR SDK right click Generate linker script Remember that Stack and Heap size should be more than 0x800 otherwise the system migh not work properly 2 Mark the bootloader project to initialize BRAM to be loaded on power up 3 Download the bitstream to FPGA to generate merged bistream 4 Use PREPARE_FWU copyandbuild_boot bat script to download everything to FLASH using JTAG cable or use the generated FIRMWARE FWU
19. og Files Synthesis Report Files 6000000000008 HM EOE ELK ES ciate Project opti B System assembl P senso L SD OE tem SE aaae ie eN deari aa 4 B2 System Assembly View Block Diagram Analyzing file sw test_hw elf a Running Data2Mem with the following command data2mem bm implementation system bd bt implementation system bit bad su test_hu elf tag microblaze 0 ob imp lementation download bit Memory Initialization completed successfully Done oa lt S 5 Output Warming Error Figure 3 Project in XPS environment 4 1 Hardware system description The hardware system is basically an embedded system with a Xilinx MicroBlaze 32 bit soft microprocessor Figure 4 The MicroBlaze is used to initialize and setup the system The horsepower for high bandwidth data streaming is a Multiport Memory Controller MPMC Using a custom built DMA engine XPS_NPI_DMA it can stream data from multiple imaging sensors to external RAM through a MPMC Native Port Interface NPI XPS_NPILDMA can do also simultaneous data reading to transfer data to USB port at the same time This custom built DMA can also rotate transpose the images before processing for example 3D processing on 90 degrees rotated image This way we get 752 instead of 480 3D points at WVGA sensor 57 more 3D points Since we get 6 10 bit pixels 64 bit bus at one transaction the DMA_FIFOS takes care for proper
20. or 6 can versicn Helease O cew versicn Build 1 Xincl eheracrer fito_ctrig tite_waak Xics char8 cimeour Xulnut33 i cx_adde Xu1ut33 countec lt 0 Xusat kz xil print ri n Entering main Carelson tdLIaLId 5d rin rin caw version Major cam Koplo wSerpataReg APAR LED BASEANDR Ls 232 cas prop LED OXxFF SleepTinec Bassidicess XPAR XPS TIMER O BASSADDR my El 2 IGR RMD corae amp my O irina Bicroprocessor Debug CID imiLinx EDR 10 1 93 Build 30K amp 5 Copyright cl 1995 Z007 Xilinr J irkerrupts Cveweriding IP level propezti Address Kap Processor alercd 10009000090 04000071 t dixb Uri cNOODG Oxletretet DDR 20 10 ls000090 0x1ef ffEfj DOD s5 10x 1400090 0x314011ff LED 10x81800090 043L8011f1 xps in 10x83400000 01834011 1 SPI 3L OxP3enOnAN Oxa3cOftet xps ti UsBSOUO0U0 OxU400Ftet gt RSF 10x884000 0 0x84901fEf debuc_ 10xc1600090 0x3L601f71 xps im Oncl 20000 Oucl leret xp3 in 1Orc18000090 0xs1L60tftft zp3 ps OrelahobadeOxelalittet gt xps rp iOxclx20000 0OxclaZifEf xpx_ac OseSe00000 OxceeOL LCL xpe_i2 10xc7200000 0x272011 1 xps tx 10xrc2600090 0x506011 t nps eo Figure 8 Downloading the hardware and software application to the camera When using Xilinx SDK v 11 x it is necessary to rebuild software project after major hardware modifications or moving copying project to another folder Follow this procedure to accomplish this e C
21. ronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 8 21 OptoMotive This dialog allows you to export hardware platform information to be used in Xilinx Software Development Kit MJ Indude bitstream and BMM file XPS will regenerate bitstream if necessary and it may take some time to finish Directory location for hardware description files SDKISDK Export Export Only Figure 7 Opening the using Export to SDK To program the camera with hardware and software bitstream click on the Program FPGA button in SDK Cit Fis ER Radir Nevigala Say ry a eS n m o Gee Te CA Projects 3 OC kh Ef 5 cameken mood eze_0_oy_pisiform E Brerics bon E K corta oh Im detaypeh t im cma fun h jh tah E ntenugts h E fm mSy0344 t hn sereors h fm utk e control Afo Ef omea_func c i Lo fun nterupta c t Lc man c T fe mun Ie res E utk ja candeon d D camedoon Hd bak Le camelson_beem id D cameleon bram kd bak cbk P main c Xilinx Plat orm Stuc o SDK Projekti Cameleon Distribution Cameleon_V1 1 EDK BASE_v0 8 0 1 system xmp Mic Toob Cevis Configuration Ruy Wida Hep wla al Reelin im a l e t amp QO Q O 4 Siw ee Meluas Le nterupts c Le ps_npi_dma h Le ps gi da Le mens Beane X Ini Ao ite TO Angke Cao vecsion Major O can vecsicn Min
22. to notify software to increment FIFO head pointer to currently transmitted frame and FIFO count number of bytes left in the buffer OMCAM structure i2c_slave_int_handler captureO_int_handler capture 1_int_handler captureN_int_handler i2c slave interrupt image captureO0 interrupt image capturel interrupt image captureN interrupt Figure 12 Camera software operation block scheme Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 12 21 OptoMotive The main routine loop constantly checks the image FIFO and FX2 buffer status and sends data via DMA pixels from ram routine to the FX2 if the TX_BUFFER is empty enough to accept another packet If the flag DropFrames 1 then the main loop also throttles the transmission by decimating the number of frames before they reach the DMA by setting XPS_IMAGE_CAPTURE_SetFrameDec This prevents memory overflow if the USB cannot transmit all the received frames With timer and increment value the user can control the amount of image buffering and therefore a delay between image capture and sending to USB if 2500000 lt SysTimer_GetValue amp amp cam prop Mode lt 2 50ms loop ul6 increment 10 6 Firmware creation 6 1 For systems executing code from FPGA s block RAM BRAM The Microblaze system has the fastest access t
23. to upload the via USB using the USBFirmwareUpgradeTool Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 13 21 OptoMotive The copyandbuild_boot bat script copies bit and elf file and calls the build_boot bat The bit file includes bitstream and bootloader executable while the elf is a SDRAM executable The build_boot bat accepts both files and SDRAM booting address usually base address of SDRAM controller The script calls several programs in bin directory and Xilinx installation directory and does the following steps change the bitstream to MCS remove the vectors table from the executable and save as binary save vectors table to binary files insert header to executable binary using custom program prepare_bootdata exe convert all flash files to MCS and combine in single file build flash binary and pack FWU burns flash through JTAG at the end if JTAG connection to FPGA is available At booting the FPGA is loaded with bitstream which contains bootloader application The processor bootloader reads first the header from the FLASH at specified address In header there are processor interrupt vectors number of bytes to read checksum and booting address Then it copies all executable data from FLASH to SDRAM and verifies checksum After success new vectors are written to BRAM and application boots from SDRAM Cam
24. tomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 16 21 OptoMotive 7 2 P2 pinout The connector P2 is used to connect additional external peripherals triggers UART stepper driver video DAC PS2 It contains dual power 5V and 3 3V 28 1 Os and multiple ground signals In the table the pin names in brackets are default pin designations Table 2 Connector P2 pinout ee a en a ra cz GND 4 EXPI UARTTX 15 6 EXP3 TRIG_OUT R6 8 EXP4 ISTEPR DIR U4 EXPSISTEPRACK V7 10 _ Ce e 15 EXP10 STEPR_RST_N R8 EXPI STEPR STEP T8 16 ea eee Pe Pn NA ee a GND im p23 exei6 OT Pio 2x7 R 22 For UART debug the best option is to use FTDI TTL 232R 3V3 USB to RS232 cable Connect it to P2 following this pinout FTDI cable pind EXP1 UART TX pind EXPO UART RX The UART cable GND is better to leave unconnected to prevent ground loops if using the cable and camera on the same computer Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 17 21 OptoMotive Figure 14 FTDI TTL 232R 3V3 UART cable 7 3 P3 pinout and connection The P3 connector is used to connect USB data lines to the USB microcontroller on the TEO300 micromodule BE CAREFUL WHEN CONNECTING C
25. uter processor is free for other tasks Low cost Xilinx Spartan FPGA 64MB optional 128MB in camera buffer Up to 127 cameras can be connected to a single USB port but sharing the bandwidth Multiple cameras can be synchronized to an external trigger or to a master camera strobe e Firmware soft hw and sw can be upgraded in a minute e Full source code of the complete system simplifies integration and enables user to customize the camera to his needs or to train FPGA SOC designing research and development The camera is sold in two basic configurations MONO single sensor or STEREO dual sensors You can upgrade your camera any time by purchasing additional sensor head The stereo version is NOT a TRADITIONAL STEREO VISION CAMERA since it does not output disparity maps User can add image processing core to add this functionality The Cameleon Stereo can only output 2 video streams or processed profiles Note Source code licence is only valid for usage in Optomotive products Unauthorised usage of custom cores and supplied software in other commercial products is a violation of licence agreement and intellectual property IP rights For usage in other products a commercial IP licences should be obtained Contact Optomotive for more information info optomotive si Cameleon Developer Guide v1 2 Optomotive mehatronika d o o V Murglah 229 SI 1000 Ljubljana Slovenia 386 1 4292914 info optomotive si www optomotive si page 2
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