V850/SF1 Usage Restrictions
Contents
1. lt 1 gt The NP flag of the PSW register is 1 NMI servicing in progress set by software lt 2 gt The ID flag of the PSW register is 1 Interrupt servicing in progress DI instruction set by software lt 3 gt The El interrupt enable state had been set during interrupt servicing to enable multiple interrupt servicing but was released by an interrupt with the same or lower priority than the interrupt being serviced The operation of the bug is shown below using the power save mode setting example from the user s manual rD PSC setting value rX Value written to PSW rY Value written back to PSW assuming PSW has been set ZBG BF 05 0001 Attachment 1 7 8 Idsr rX 5 Sets PSW to the value of rX st b r0 PRCMD r0 Writes to PRCMD st b rD PSC r0 Sets the PSC register PSC setting Idsr rY 5 Returns the value of PSW After 4 bytes nop 2 to 5 NOP instructions After 6 bytes nop After 8 bytes Bug occurs here nop After 10 bytes lt 1 gt Discrepancy with PC nop After 12 bytes lt 2 gt Instructions ignored nop After 14 bytes Next instruction After 16 bytes Workaround 1 Do not use a power save mode IDLE or STOP while an instruction is being executed on the external ROM 2 If it is necessary to use a power save mode IDLE or STOP while an instruction is being executed on the external ROM take the software workaround shown below lt 1 gt Insert 6 NOP instructions 4 bytes afte2. IF flag 1 El NOP 1 system clock NOP 1 system clock NOP 1 system clock NOP 1 system clock JR LP OO 3 system clocks branch to LP routine LP1 DI lt Interrupt servicing is executed at 8th clock cycle after the El instruction No 4 External bus interface address incrementation Description When the external bus interface is used and the address bus A16 to A21 is incremented an address value 10000H larger than the expected value is inadvertently output for the address immediately before it was incremented For example if the address value is incremented from 14FFFEH to 150000H the erroneous address 15FFFEH is output at the timing at which 14FFFEH should be output Cause of bug The clock signal that latches the address bus data A16 to A21 is delayed beyond the internal address bus data change point by the circuit added to enable support of the EVA chip function which causes the address value of the next bus cycle to be latched A detailed timing chart is provided on the attachment Note that because the EVA chip function circuit is only incorporated in flash memory products this bug does not occur in mask ROM products Workaround i Temporary workaround Using software make the address area in which the address bus A21 to A16 is incremented use prohibited when using the external bus interface e Use prohibited area xxnmFFF8H to xxnmFFFFEH n 0 to 3 m 0 to E XxnFFFF8H to xxnFFFFFEH n 0 to 2 ZB
3. 5 0001 2 2 Description Newly created Addition of bugs No 1 to No 5 SBG DT 02 0028 December 12 2002 Addition of bugs No 6 and No 7 ZBG BF 05 0001 January 21 2005 6 List of restrictions Addition of bug No 8 A list of restrictions in the V850 SF1 including the revision history and detailed information is described on the following pages ZBG BF 05 0001 Attachment 1 1 8 List of Restrictions in V850 SF1 1 Product Version e V850 SF1 B version UPD70F3079BYGC GF uwPD70F3079BYGC A Rank K e V850 SF1 A version UPD703075AYGC GF PD703075AYGC A Rank K LPD703076AYGC GF uPD703076AYGC A Rank K UPD703078AYGC GF PD703078AYGC A Rank K UPD703079AYGC GF PD703079AYGC A Rank K LPD70F3079AYGC GF uwPD70F3079AYGC A Rank K e V850 SF 1 UPD703078YGC GF Rank K E UPD703079YGC GF Rank K E UPD70F3079YGC GF Rank K E The rank is indicated by the letter appearing as the 5th digit from the left in the lot number marked on each product 2 Product History V850 SF1 B versions flash memory versions PD70F3079BY PD70F3079BY A Bugs and Restrictions FCAN global timer clock selection Restriction on 16 bit timer one shot pulse output function Restriction on interrupt servicing acknowledgement after El instruction External bus interface address incrementation Restriction on power save function on external ROM Restriction on reading t
4. 9BYGC A 8EU Cautions 1 Implement the following procedure when the debugger is activated when emulating the FCAN function using the emulation board IE 703079 MC EMI a Supply power to the VDDO pin GC package pin 8 GF package pin 11 from the target board before the debugger is activated b Set the memory mapping in the debugger as shown below Attribute Target memory Mapping address nFF800H to nFFFFFH n 3 7 or B c Do not mask WAIT and HLDRQ when accessing the FCAN memory ZBG BF 05 0001 Attachment 2 1 2 Modified specifications and cautions in line with upgrade to A version V850 SF 1 HPD70F3079Y uPD703079Y uwPD703078Y V850 SF1 Aversion u uPD70F3079AY uPD703079AY uPD703078AY uwPD703076AY uPD703075AY Remarks 1 The A version is completely upwardly compatible with the non A version except for the items shown below 2 The B version is completely upwardly compatible with the A version except for the bug items Specifications modified in line with upgrade to the A version are as follows 1 Change of the oscillation stabilization time after reset release by changing the initial value of the oscillation stabilization time setting register 2 Change of the CLKOUT pin output function 3 Modification the FCAN time stamp function specification 4 Expansion of operating voltage range at 16 MHz operation 5 Addition of mask ROM 128 KB version to product lineup 1 Change of the oscillation stabilizat
5. G BF 05 0001 Attachment 1 6 8 e Example of workaround Using a link directive file ensure that program code is not allocated to the use prohibited area described above TEXT1 LOAD RX V0x100000 text1 PROGBITS AX objectt o object2 o0 object3 o i Make the total size of TEXT2 ILOAD RX VOx110000 objects in one segment text2 PROGBITS AX object4 o less than 64 KB TEXT3 LOAD RX V0x120000 text3 PROGBITS AX object5 o object6 0 No 5 Power save function on external ROM Description If the affected products are used under the following conditions a discrepancy may occur between the address indicated by the program counter PC and the address at which the instruction is actually read following the release of a power save mode This may result in the CPU ignoring a 4 or 8 byte instruction from between 4 bytes and 16 bytes after an instruction is executed to write to the PSC register which could in turn result in the execution of an erroneous instruction Note that this bug only occurs if all of conditions 1 to 3 below are met Conditions 1 A power save mode IDLE or STOP is set while an instruction is being executed on the external ROM 2 The power save mode is released by an interrupt 3 The next instruction is executed while interrupts are in a pending state following the release of the power save mode Note that interrupts are held pending under any of the following conditions
6. Microcomputer Technical Information V850 SF 1 Usage Restrictions Document No CP K O ZBG BF 05 0001 Date issued January 21 2005 Issued by Related V850 SF1 Hardware User s documents Manual U14665EJ4VOUD V850 Family Architecture User s Manual U10243EJ7VOUD 1 Affected products Car Audio Solution Development Group Automotive Systems Division 4th Systems Operations Unit NEC Electronics Corporation Notification classification V850 SF1 Series on chip flash memory microcontrollers uPD70F3079YGC UPD70F3079AYGC uPD70F703079AY GF UPD70F3079AYGC A 2 Details of bug y Usage restriction Upgrade Document modification Other notification This notification concerns the following bug No 8 See attachment 1 for details e No 8 Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request 3 Workaround e No 8 There is no workaround 4 Action The circuit will be modified to correct this bug Part Number After Modification Sample Shipment Schedule B Version HPD70F3079BYGC 8EU Late January 2005 HPD70F3079BYGF 3BA UPD70F3079BYGC A 8EU ES CS Early April 2005 For the detailed release schedule of modified products contact an NEC Electronics sales representative 5 Document revision history Document Number Issued on SBG DT 0008 October 4 2001 ZBG BF 0
7. cation of the FCAN time stamp function specification The value of the time stamp counter is not captured even if EOF is detected in the CAN bus Modification of settings of the TMR bit of the CANn control register CnCTRL Time Stamp Control Bit for Reception V850 SF1 The value of the time stamp counter is captured when an EOF is detected confirms the valid message in the CAN bus V850 SF1 A version The time stamp counter is not captured The value of the time stamp counter is captured when an EOF is detected confirms the valid message in the CAN bus 4 Expansion of operating voltage range at 16 MHz operation i Flash Memory Version 16 MHz Mask ROM Version 16 MHz V850 SF 1 4 5 to 5 5 V 4 0 to 5 5 V V850 SF1 A version 4 0 to 5 5 V 3 5 to 5 5 V Other electrical specifications have been modified In particular the AC characteristics have been modified but this is modification in line with the above voltage range expansion Therefore there is no problem in upgrading from a previous version of the V850 SF1 to an A version of the V850 SF 1 Refer to the electrical specifications chapter in the user s manual 5 Addition of mask ROM 128 KB version to product lineup LPD703076AY ROM 128 KB RAM 12 KB FCAN 2 channels HPD703075AY ROM 128 KB RAM 12 KB FCAN 1 channel
8. errupt service routine as soon as the instruction execution in 1 is complete However the instruction execution in 1 is delayed due to DMA transfer in 3 The CPU acknowledges the interrupt request in 2 during this period and returns the ACK signal to INTC and the ISPR flag is set before the read timing of 1 Workaround Read the ISPR register while interrupts are disabled DI state No 7 Restriction on rewriting compare values during 16 bit timer TM2 to TM6 count operation Description The higher 8 bits of the CRn register are undefined when the value of the compare register CRn n 2 to 6 is changed during a timer count operation Workaround Be sure to stop the timer count operation before setting values to the compare register CRn n 2 to 6 No 8 Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request Description If a write operation R W signal L to the external memory area and acknowledgement of a bus hold request HLDRQ conflict at a specific timing the R W signal becomes the high level read though it is in the write cycle Consequently the write operation to the external memory area cannot be performed normally in the bus cycle in which the conflict has occurred Workaround There is no workaround Action The circuit will be modified to correct this bug Part number after modification B version UPD70F3079BYGC 8EU LPD70F3079BYGF 3BA LPD70F307
9. g acknowledgement after El instruction External bus interface address incrementation Restriction on power save function on external ROM Restriction on reading the ISPR register Restriction on rewriting compare values during 16 bit timer TM2 to TM6 count operation Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request y Bug does not occur A Bug will also apply in future x Bug occurs Not relevant ZBG BF 05 0001 Attachment 1 3 8 V850 SF1 mask ROM versions PD703078Y u PD703079Y Bugs and Restrictions FCAN global timer clock selection Restriction on 16 bit timer one shot pulse output function Restriction on interrupt servicing acknowledgement after El instruction External bus interface address incrementation Restriction on power save function on external ROM Restriction on reading the ISPR register Restriction on rewriting compare values during 16 bit timer TM2 to TM6 count operation Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request y Bug does not occur A Bug will also apply in future x Bug occurs Not relevant V850 SF1 flash memory version PD70F3079Y Bugs and Restrictions m FCAN global timer clock selection Restriction on 16 bit timer one shot pulse output function Restriction on i
10. he ISPR register Restriction on rewriting compare values during 16 bit timer TM2 to TM6 count operation Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request yV Bug does not occur A Bug will also apply in future x Bug occurs Not relevant ZBG BF 05 0001 Attachment 1 2 8 V850 SF1 A versions mask ROM versions UPD703075AY uPD703076AY uPD703078AY uPD703079AY UPD703075AY A PD703076AY A PD703078AY A PD703079AY A No Bugs and Restrictions Re 1 FCAN global timer clock selection 2 Restriction on 16 bit timer one shot pulse output function A 3 Restriction on interrupt servicing acknowledgement after El instruction A 4 External bus interface address incrementation 5 Restriction on power save function on external ROM A 6 Restriction on reading the ISPR register A 7 Restriction on rewriting compare values during 16 bit timer TM2 to A TM6 count operation 8 Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request yV Bug does not occur A Bug will also apply in future x Bug occurs Not relevant V850 SF1 A versions flash memory versions PD70F3079AY PD70F3079AY A Bugs and Restrictions FCAN global timer clock selection Restriction on 16 bit timer one shot pulse output function Restriction on interrupt servicin
11. ion time after reset release by changing the initial value of the oscillation stabilization time setting register The initial value of the oscillation stabilization time setting register OSTS has been changed as follows V850 SF1 2 fxx 131 ms 16 MHz V850 SF1 A version 2 fxx 16 ms 16 MHz Internal system clock p AANI X1 RESET Internal system reset signal l j Reset acknowledged Reset released 2 Change of the CLKOUT pin output function lt 1 gt Addition of Hi Z output settings 7 6 5 3 2 1 0 psc pocki oco o o o we sP o R W 4 R W R W R W R W R W R W R W ZBG BF 05 0001 Attachment 2 2 2 DCLK1 DCLKO Specification of CLKOUT Pin Operation Output enabled V850 SF 1 Setting prohibited V850 SF1 A version Hi Z output Setting prohibited Output disabled low level output Note Hi Z output is not possible in the in circuit emulator lt 2 gt Modification of CLKOUT pin status during reset period V850 SF 1 Hi Z V850 SF1 A version Low level insertion of pull down resistor Note 1 2 3 Notes 1 A pull down resistor can be inserted during the reset period only The setting is changed to low level output default setting of the PSC register when a reset is released 2 Do not input a high level to the CLKOUT pin when reset is released otherwise the operation after the input cannot be guaranteed 3 Pull down resistor value 40 kQ TYP 3 Modifi
12. least 7 clocks are required as determination time between the generation of an interrupt and its acknowledgement Because instructions continue to be executed in this period if the DI instruction interrupt disable is executed interrupts become disabled This causes all interrupts to be held pending until the re execution of the El instruction interrupt enable Since this determination time is also required when the El instruction is executed at least 7 clocks must be allowed before interrupts can be acknowledged after execution of the El instruction Consequently if the DI instruction is executed before these 7 clocks have elapsed interrupts will be held pending and not acknowledged To ensure proper acknowledgement of interrupts therefore insert an instruction other than those below of at least 7 execution clocks between the El and DI instructions e IDLE STOP mode setting e El DI instruction e RETI instruction e LDSR instruction for PSW register e Access to interrupt control register xxICn Example When EIl instruction processing is invalid Program example DI MK flag 0 interrupts enabled Interrupt request generated IF flag 1 El JR LP1 POI 7 clocks have not elapsed between El and DI instructions 3 clocks LP1 DI 4 Interrupt request is not acknowledged ZBG BF 05 0001 Attachment 1 5 8 Workaround example DI MK flag 0 interrupts enabled Interrupt request generated
13. nterrupt servicing acknowledgement after El instruction External bus interface address incrementation Restriction on power save function on external ROM Restriction on reading the ISPR register gt gt gt 2 gt gt Je Restriction on rewriting compare values during 16 bit timer TM2 to TM6 count operation Bug related to the conflict between writing to external memory area and acknowledgement of bus hold request y Bug does not occur A Bug will also apply in future x Bug occurs Not relevant ZBG BF 05 0001 Attachment 1 4 8 3 Details of Usage Restrictions No 1 FCAN global timer clock selection Description Because the global timer clock selection which is set using the GTCS1 and GTCSO bits of the CGCS register cannot be set it is fixed to the initial value fets fyew 2 fuew 4 fuew 8 and fmem 16 cannot be set No 2 16 bit timer one shot pulse output function Description When using the one shot pulse function of timers 0 1 and 7 as a software trigger the level of the T1 pin or its alternate function port cannot be changed Because the external trigger is also enabled in this case the trigger will inadvertently clear amp start even if the level of the T1 pin or its alternate function port is changed causing a pulse to be output at an unintended timing No 3 Interrupt servicing acknowledgement after El instruction Description In this product at
14. r an instruction that writes to the PSC register lt 2 gt Insert the br 2 instruction after the NOP instructions to eliminate the PC discrepancy Program example rD PSC setting value rX Value written to PSW rY Value written back to PSW assuming PSW has been set Idsr rX 5 Sets PSW to the value of rX st b r0 PRCMD r0 Writes to PRCMD st b rD PSC r0 Sets the PSC register Idsr rY 5 Returns the value of PSW nop lt 1 gt 6 or more NOP instructions nop nop nop nop nop br 2 lt 2 gt Eliminates PC discrepancy No 6 Restriction on reading the ISPR register Description When an interrupt request to the CPU is generated from INTC the CPU returns the interrupt ACK signal to INTC if the request is acknowledgeable and enters the interrupt service routine after the instruction currently being executed is complete When the interrupt ACK signal is received INTC sets the ISPR register This processing in INTC is performed asynchronously to the CPU If the following three conditions conflict therefore the value after ISPR is set may be read even though the CPU still has not entered the interrupt service routine 1 CPU executes a load instruction to the ISPR flag 2 An interrupt request to the CPU occurs while the instruction in 1 is being executed 3 DMA transfer occurs while the instruction in 1 is being executed ZBG BF 05 0001 Attachment 1 8 8 At this time the CPU jumps to the int
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