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LC87BK00 SERIES USER`S MANUAL

1. 3 34 3 6 4 Related Registers Fuuasassusuuupmsensunuusssesununsansusucssussuaseussusunusy5nessuansussseununsunsus 3 39 3 7 Timers 6 and 7 T6 T7 3 44 3 7 1 Overview 3 44 3 7 2 Functions wurususessunuuusussusunsussusumsussausunensuusyuSEMssEhHARAESHEEEARERERRSRRERRRERSRSARE RR 3 44 3 7 3 Circuit Configuration 3 44 3 7 4 Related Registers Furuasassusuuuamsansusuusunsununsusausussuhsassussusasauusussunsussseusensunsus 3 47 38 Base Timer BT ssanasassansausansuunuaussanssaessanssCsaunsAHAuUSHauahnHausanaunuuauauansuuanen 3 49 3 8 1 Overview 3 49 3 8 2 Functions wurussssssunuanassssunuamssusussmseHsusensuuaessunsussususssusuususseussunsusususensnsunause 3 49 Contents 3 8 8 Circuit Configuration mmm ee 3 50 3 8 4 Related Registers meme 3 51 3 9 Serial Interface 1 SIO1 m HMHHeHH 3 53 939
2. 2 8 2 11 5 Direct Addressing dst mmm 2 8 211 6 ROM Table Look up Addressing 2 9 2 11 7 External Data Memory 2 9 2 12 Wait Operation mnm enne enne nre nere 2 10 2 1 2 1 Occurrence of a Wait Operation TP PPP LLL 2 1 0 2 1 2 2 What is a Wait Operation ee ee eee eee ee eee ee eee eee eee rere re 2 1 0 Chapter 3 Peripheral System Configuration 3 1 Port 0 eer errr eer rere ee ree rere rere eee eee TTT 3 1 3 1 1 Overview eee rere er ere rere eer eee eee re 3 1 Contents 3 1 2 Functions ELI 3 1 3 1 3 Related Registers wusasassssunuuunsassunsnsssausunsususauansnsuassusunsunisHGe5ssussusassusunsusaneus 3 2 3 1 4 Options muruasassssuuausassunsussssusussusasausssuuuuasuseusunsnusssussuzsaAssussnsunsiussssusunsunuues 3 4 3 1 E HALT and HOLD Mode Operation 3 4 3 2 Port 1 TTT 3 5 3 2 1 Overview wuuusasassunuassusumnsuuuuCansnsuuisssssunsuusascusensaususunsuue amp eazessensuusseununsuansuse 3 5 3 2 2 Functions wuruusssesssuuunsussuuuuuaussecansuuaususssssusasussussaAnussussmsussussusnensuususensssuuuas 3 5 3 2 3 Related Registers
3. mn IP23 0001BH ER 0 00013H IP13 4 4 LC87BKO0 Chapter A 4 2 System Clock Generator Function 4 2 4 Overview This series of microcontrollers incorporates five systems of oscillator circuits i e a main clock oscillator a subclock oscillator low and medium speed RC oscillators and a multifrequency RC oscillator as system clock generator circuits The low and medium speed RC oscillator circuits and multifrequency RC oscillator circuit have internal resistors and capacitors so that no external circuit is required The system clock can be selected from these five types of clock sources under program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from five types of clocks generated by the main clock oscillator subclock oscillator low and medium speed RC oscillators and multifrequency RC oscillator 2 System clock frequency division Divides the frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock The frequency divider circuit has two stages 1 222 1 The first stage allows selection of division ratios of 1 1 1 1 1 P 11 The second stage allows the selection of division ratios of gt gt 4 1 2 4 8 16 32 64 and 3 Oscillator circuit control Allows the start stop c
4. When it is active TIHRUN 1 the match buffer register is loaded with the contents of when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEID 0000 0000 R W TIHR TIHR7 TIHR6 5 TIHR4 TIHR3 2 TIHRO 3 41 gt D E D 9 lt gt a g be gt Modes 0 2 T1L T1H Match signal Interrupt flag set T1PWMH T1PWML Figure 3 6 5 Modes 0 2 Operating Waveform Example FFH o gt _ c 2 TiL T1H Match signal FFH Counter value Interrupt flag set T1PWML T1PWMH Figure 3 6 6 Mode 1 Operating Waveform Example 3 42 LC87BKO00 Chapter gt E D o 2 a g be gt Match signal Interrupt flag set T1PWMH FFH Counter value Match signal FFH Counter value Interrupt flag set T1PWML Figure 3 6 7 Mode 3 Operating Waveform Example 3 43 T6 T7 3 7 Timers 6 and 7 T6 T7 3 7 1 Overview Timer 6 T6 and timer 7 T7 incorporated in this series of microcontrollers are 8 bit timers with two independently controlled 6 bit prescalers 3 7 2 Functions 1 Timer 6 T6 Timer 6 is an 8 bit timer that runs on a 4 Tcyc 16 Tcyc or 64 Tcyc clock It can generate toggle waveforms at pin 06 whose frequency is equal to the period of timer 6
5. ADTM2 DATALS bit 7 DATAL2 bit 6 DATAL1 bit 5 DATALO bit 4 Low order 4 bits of AD conversion results ADRL3 bit 3 Fixed bit This bit must always be set to 0 ADRL2 bit 2 Fixed bit This bit must always be set to 0 bit 1 Fixed bit This bit must always be set to 0 ADTM bit 0 AD conversion time control This bit and ADTMI bit 1 and ADTMO bit 0 of the AD mode register ADMRC are used to control the conversion time See the subsection on the AD mode register for the procedure to set up the conversion time Note The conversion result data contains errors quantization error combination error Be sure to use only the valid conversion results based on the specifications provided in the latest Semiconductor Data Sheet 3 10 4 4 AD conversion result register high byte ADRHC 1 This register is used to hold the high order 8 bits of the results of an AD conversion that is carried out in the 12 bit AD conversion mode The register holds the entire 8 bits of the results of an AD conversion that is carried out in 8 bit AD conversion mode 2 Sincethe data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial Value R W Name BIT7 BIT6 BIT5 4 BIT2 BIT1 BITO FESB 0000 0000 ADRHC DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATAO 3 69 ADC
6. 1211 1221 LA N 4 Reset When timer 1 stops operation or a T1H reset signal is generated 3 6 3 5 Timer 1 low byte T1L 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock TIL prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset When the counter stops operation or a match signal occurs in mode 0 or 2 3 6 3 6 Timer 1 high byte T1H 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset When the counter stops operation or a match signal occurs in mode 0 2 or 3 3 35 3 6 3 7 Timer 1 match data register low byte T1LR 8 bit register with a match buffer register 1 This register is used to store the match data for It has 8 bit match buffer register match signal is generated when the value of this match buffer register matches the value of timer 1 low byte TIL 2 The match buffer register is updated as follows When it is inactive TILRUN O the match buffer register matches TILR e When it is active TILRUN 1 the match buffer register is loaded with the contents of TILR when the valu
7. e L level Int request to vector 00003 I01CR FE5D Int request to vector 0000B INTO Port 1 and Port 7 Interrupt Block Diagram AII 6 LC87BK00 APPENDIX II March 9 2011 Ver 1 10 Microcontroller Development Department SANYO Semiconductor Co Ltd LC872000 LC87B000 Series On chip Debugger Pin Treatment Guide 1 Overview The LC872000 LC87B000 Series On chip Debugger Pin Treatment Guide describes the treatment of pins for low pin count 30 pins or less microcontrollers that are equipped with multiple on chip debugger pin channels 2 Operation of On chip Debugger Pins On chip debugger pins DBGPx0 to DBGPx2 are placed in the state shown below when a system reset is performed even when no debugger is connected Debugger Pin Name Pin Status Affected Products DBGP00 DBGP10 Low level output during LC87F2416A DBGPX0 DBGP20 reset sequence Low level output for LC87F2608A LC87F2708A LC87F2G08A LC87F2H08A several us after the reset LC87F2R04A LC87FBK08A LC87FBLO8A state is released LC87FBGOSA LC87FBH08A DBGPOI DBGPI1 LC87F2416A DBGP21 Held high by a pull up LC87F2708A resistor for several us after the reset state is released DBGP02 DBGP12 DBGP22 Held high by a pull up LC87F2608A LC87F2708A LC87F2G08A LC87F2H08A resistor for several us after LC87F2RO4A LC87FBK08A LC87FBL08A the reset state is released LC87FBG08A LC87FBH08A 3 Pin Treatment Procedures For pins that also have
8. CLKOEN ckODV2 ckODv 1 3 1 3 Related Registers 3 1 31 Port 0 data latch PO 1 Thislatch is an 8 bit register that controls port 0 output data and port 0 interrupts 2 When this register is read with an instruction data at pins POO to 7 is read in If PO 4 is manipulated using a NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE40 0000 0000 R W P07 P06 P05 P04 P03 P02 01 00 3 1 3 2 Port 0 data direction register PODDR 1 Thisregister is an 8 bit register that controls the I O direction of port 0 data in 4 bit units the pull up resistors in 4 units and port 0 interrupts FE41 0000 0000 R W PODDR POHPUS POLPUS POFLG POIE POHPU POLPU POHDDR POLDDR POHPUS bit 7 7 to P04 high low impedance pull up resistor select A 1 in this bit selects high impedance pull up resistors for PO7 to P04 and a 0 selects low impedance pull up resistors POLPUS bit 6 to POO high low impedance pull up resistor select A 1 in this bit selects high impedance pull up resistors for to POO and a 0 selects low impedance pull up resistors POFLG bit 5 PO interrupt source flag This flag is set when a low level is applied to port 0 set
9. Frequency divider 1 Frequency divider 2 Medium speed RC oscillator System clock RCSTOP SCLK RC clock Low speed RC oscillator SLRCSTAT fSCLK System clock frequency fCYC Cycle clock frequency minimum instruction cycle fCYC fSCLK 3 To watchdog timer amp Oscillation control from 2 base timer circuit watchdog timer Figure 4 2 1 System Clock Generator Circuit Block Diagram 4 2 4 Related Registers 4 2 41 Power control register PCON 3 bit register 1 This register is a 3 bit register used to specify the operating mode normal HALT HOLD X tal HOLD See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE Bits 7 to 3 These bits do not exist They are always read as 1 XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating Mode Normal or HALT mode TET moa 1 3 HOLD mode lt l gt These bits must be set with an instruction When the CPU enters HOLD mode all oscillators main clock subclock low medium speed RC multifrequency RC are suspended and the related registers are placed in the states described below If bit 1 of the SLWRC register is set to 1 bit 0 of the SLWRC register is set and bits 4 a
10. L8 9 rus mino wr Ex Pa s mu 00000000 R TNTA7INTE contro FIG FIG maea rus ox 0000 ww M rne Ducit j 3 r j s j i a j ERES ee j FE j rg T RL j T P T TL L TL TT ji r EL j i j mm Jj j J j J j j J mg Jj j J j J j ij Tu i E a NR mm ure 57 FE58 0000 0000 ADCRC 12 DM AD control ADCHSEL3 ADCHSEL2 ADCHSEL1 ADCHSELO ADCR3 ADSTART ADENDF ADIE Feso 0000 0000 Rm 12 bit AD mde Ab aDwos oe me Es 00000000 RA I2 bit AD conversion result L DA Danz DWTALI DATO ALS ADRL2 ALT _ res 0000 0000 Rm 12 bit AD conversion result H DATA omae Datas mu omas DW DADO _ mm mmn RAT LE Fee 000 0000 Rm ioi contre nr INTIE no TWTOL IWTGIF AI 3 Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO FESE 00
11. The port output data is controlled by the port 2 data latch P2 FE48 and the I O direction is controlled by the port 2 data direction register P2DDR 49 Each port bit is provided with a programmable pull up resistor 2 Interrupt input pin function The port INT4 selected from P20 and P21 is provided with a pin interrupt function respectively This function detects a low edge a high edge or both edges and sets the interrupt flag These two selected ports can also be used as timer 1 count clock input or timer 0 capture signal input 3 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INT4 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode medium or low speed RC oscillator selected as system clock When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When a signal change that sets the INT4 interrupt flag is input in HOLD mode an interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INT4 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when INT4 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 it is recommended that INT4 be used in both edge interrupt mode
12. External reset input internal reset output CF1 XT1 Ceramic resonator 32 768 kHz crystal resonator input Pin functions General purpose input port CF2 XT2 Ceramic resonator 32 768 kHz crystal resonator output Pin functions General purpose I O port 1 9 1 6 On chip Debugger Pin Connection Requirements For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and Appendix III LC872000 LC87B000 Series On chip Debugger Pin Processing 1 7 Recommended Unused Pin Connections Recommended Unused Pin Connections Pin Name Board Software POO to P07 Open Output low P10 to P17 Open Output low P20 to P21 Open Output low P70 Open Output low CF1 XT1 Pulled down with a resistor of 100 or less General purpose input port CF2 XT2 Pulled down with a resistor of 100kQ or less General purpose input port 1 8 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in the output mode Option Selected in Output Type Pull up Resistor Units of P00 to P07 Programmable Note 1 channel open drain N P10 to P17 CMOS Programmable P20 P21 N channel open drain Programmable N channel open drain Programmable CF2 XT2 Ceramic resonator 32 768 kHz N crystal resonator o
13. PCON register FEO7H bit 2 set to 1 and bit 1 to 1 eX tal HOLD mode Note 3 The main clock low medium speed RC and multifrequency RC oscillators stopped The subclock retains the state established when X tal HOLD mode is entered The contents of OCR SLWRC and MRCR registers remain unchanged CPU enters this mode after selecting subclock or low medium speed RC oscillator as the system clock CPU and all peripheral modules except the base timer stop operation and the base timer retains the state established when X tal HOLD mode is entered When X tal HOLD mode is exited the oscillators return to the state established when the mode is entered X tal HOLD mode release conditions Base timer interrupt request generated INTO or INT1 level interrupt request generated Request for INT2 4 or port 0 interrupt generated Reset entry conditions established Note 1 Note 2 The CPU cannot return from HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into HALT HOLD or X tal HOLD mode Note 3 The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer See Section 4 5 Watchdog Timer for details HALT HOLD or X tal HOLD mode No interrupt request present Interrupt level at which the CPU entered HALT
14. 8 lt 8 RAMH8 lt REGH8 RAML8 REGL8 8 lt 8 lt RAML8 PI REG8 lt RAM8 OV PUSH PUSH PUSHW PUSH_P PUSH_BA P1 lt REG8 P1 lt REGH8 P1 lt RAM8 P1 bitl when PSW is popped REGH8 lt RAMH8 REGL8 lt RAML8 PIX RAMH8 P1 lt bit1 when high order address of PSW is opped POP P P1 RAMI bit 1 POP BA PRAM X REG8oPI Same as left XCHW 8 lt REGL8 PI P1 lt REGH8 Same as left INC 9 bits P1 REGS after computation INC 17 bits REGL8 lt low byte of CY P1 lt REGH8 after computation C DEC 9 bits P1 REGS after computation DECW DEC 17 bits P1 lt REGH8 after 8 lt low byte of CY inverted computation DBNZ DEC 9 bits PI REGS8 DBZ DEC 9 bits P1 lt REG8 SETI C Bit 8 ignored INC 9 bits INC 17 bits CH INC INCW DE B DEC 9 bits DEC 17 bits DEC 9 bits check low order 8 bits DEC 9 bits check low order 8 bits CLRI BP GNE M MUL24 8 lt 1 8 of RAM address DIV24 for storing results is set to 1 iem Ne c oum 7 s Note A I is read if the processing target is an 8 bit register no bit 8 Legends REGS Bit 8 of a RAM or SFR location 8 Bit 8 of the high order byte the low order byte of a RAM location or SFR RAMS Bit 6 of a RAM location 8 8 Bit 8 of the high order byte the low order byte of a RAM location
15. Note 1 The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer See Section 4 5 Watchdog Timer for details Note 2 The CPU switches to the reset state if it exits the current mode on the establishment of reset entry conditions 4 17 Standby Table 4 3 2 Pin States and Operating Modes This series Pin Reset Time Normal Mode HALT Mode HOLD Mode On Exit from Name HOLD Mode RES Input pin CFI XTI Pull down output CF oscillation inverter oscillation inverter State established Oscillation not input general purpose input general purpose on entry into started input selected by bit 3 of input is in the state HOLD mode register XT2PC FE43H established on entry After reset release Oscillation enable into HOLD mode Input pin disable controlled by register OCR FEOEH started Feedback resistors Feedback resistor Feedback resistor for and XT are between CF1 and CF2 between CF1 and CF2 turned off controlled by a program is in the state established on entry into HOLD mode e High impedance CF oscillation inverter CF oscillation inverter State established Oscillation not input general purpose output general purpose on entry into started input selected by bit 3 of input output is in the HOLD mode CF2 XT2 register XT2PC FE43
16. TOLO 3 5 4 4 Timer counter 0 high byte TOH 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or overflow occurring in TOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHI TOHO 3 5 4 5 Timer counter 0 match data register low byte TOLR 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the low order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode 2 The match buffer register is updated as follows When it is inactive TOLRUN 0 the match buffer register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated 14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLRI TOLRO 3 30 LC87BKO00 Chapter 3 3 5 4 6 Timer counter 0 match data register high byte TOHR 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode 2 The match buffer register is updated as follows When it is inact
17. erowr suecser sacro 4 2 3 Circuit Configuration 4 2 31 Main clock oscillator circuit 1 main clock oscillator circuit is prepared for oscillation by connecting a ceramic resonator and a capacitor to the CF1 XT1 and CF2 XT2 pins and controlling OCR and XT2PC registers 2 The data the CFI XTI and CF2 XT2 pins can be read as bits 2 and 3 of the OCR register 3 CF2 XT2 pin can be used as a general purpose output N channel open drain port 4 Refer to Section 1 7 Recommended Unused Pin Connections when 1 2 or 3 above is not to be used 4 2 3 2 Subclock oscillator circuit 1 subclock oscillator is prepared for oscillation by connecting a crystal resonator 32 768 kHz typ a capacitor and a damping resistor to the and CF2 XT2 pins and controlling OCR and XT2PC registers 2 The data at the CF2 XT2 pin be read as bit 3 of OCR register The data at the CF1 XT1 pin is not read as bit 2 of the OCR register 4 6 LC87BKO0 Chapter A 4 2 3 3 Internal low speed RC oscillator circuit 1 Thiscircuit oscillates due to the internal resistor and capacitor 100 kHz typ 2 internal low speed RC oscillator serves as the system clock to be used for low power low speed operation 4 2 8 4 Internal medium speed RC oscillator circuit conventional RC oscillator circuit 1 This circuit oscillates due to the internal resistor and capacitor 1 MHz typ 2 Theclock fr
18. period 6 1 x 4 nz1 2 3 Period of cycle clock 2 Timer 7 T7 Timer 7 is an 8 bit timer that runs on a 4 Tcyc 16 Tcyc or 64 Tcyc clock It can generate toggle waveforms at pin PO7 whose frequency is equal to the period of timer 7 T7 period T7R 1 x 4 nz1 2 3 Period of cycle clock 3 Interrupt generation An interrupt request to vector address 0043H is generated when the overflow flag is set at the interval of timer 6 or timer 7 period and the corresponding interrupt request enable bit is set 4 Itis necessary to manipulate the following special function registers to control timer 6 and timer 7 T7 T67CNT T6R T7R POFCR Initial Value BIT2 BIT1 0000 0000 T7IE T6OV 2 7 2 TRI r2 0000 porcr 3 7 3 Circuit Configuration 3 7 3 1 Timer 6 7 control register T67CNT 8 bit register 1 Thisregister controls the operation and interrupts of T6 and T7 3 7 8 2 Timer 6 counter TGCTR 8 bit counter 1 This counter counts the number of clocks from the timer 6 prescaler The value of the timer 6 counter reaches 0 on the clock following the clock that reaches the value specified in the timer 6 period setting register T6R when the interrupt flag T6OV is set 2 When T6CO and T67CNT FE78 bits 4 and 5 ar
19. x A A dO C SANYO VCT24 3mm x 3mm lead free halogen free product make to order 1 6 1 4 System Block Diagram C lt Xtal Interrupt control LC87BK00 Chapter 1 Standby control IR PLA 5 SRC c RC MRC Lk Watchdog 1 Q timer j y 8 Reset circuit E LVD POR e Bus interface SIO1 lt P amp Port 0 Timer 0 lt Port 1 Timer 1 gt lt p Port 2 Timer 6 gt P Timer 7 gt 4 pi ADC Base timer INTO to INT2 w noise filter Port2 4 1 7 Flash ROM M PC ACC B register C register gt Stack pointer On chip debugger 1 5 Pin Functions Name UO Description VSS1 552 Power supply pin VDDI Power supply pin Port 0 8 bit I O port P00 to P07 O can be specified in 4 bit units d Pull up resistors can be turned on and off in 4 bit units HOLD release input Port 0 interrupt input Pin functions P05 System clock output P06 Timer 6 toggle output P07 Timer 7 toggle output P00 ANO to P06 AN6 AD converter input port P05 DBGP00 to P07 DBGP02 On chip debugger 0 pins Por
20. 2 12 LC87BKO0 Chapter 3 Peripheral System Configuration This chapter describes the internal functional blocks peripheral systems of this series of microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix II for reference 3 1 Port 0 3 1 1 Overview Port 0 is an 8 bit I O port equipped with programmable pull up resistors It consists of a data latch a data direction register and a control circuit The I O direction and pull up registers are determined by the data direction register in 4 bit units This port can also be used as a pin for external interrupts and can release HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output can be selected as the output type in 1 bit units Notes on the flash ROM version Port 05 is temporarily set low when the microcontroller is reset During the reset sequence do not apply a clock or any medium voltage level signal including Hi Z to port P07 For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and Appendix III LC872000 LC87B000 Series On chip Debugger Pin Processing 3 1 2 Functions 1 Input output port 8 bits POO to P07 The port output data is controlled by port 0 data latch PO FE40 in 1 bit units T O control of to P03 is accomplished by POLDDR PODDR FE41 bit 0 T O co
21. Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE48 HH00 R W P2 P21 P20 ro RW DDR Pei Port 2 3 3 3 Related Registers 3 3 3 1 Port 2 data latch P2 1 Thislatch is a 2 bit register that controls port 2 output data and pull up resistors 2 When this register is read with an instruction data at pins P20 and P21 is read in If P2 FE48 is manipulated using a NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port 2 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 6 5 4 2 BITO FE48 HHHH 00 R W P2 P21 P20 3 3 3 2 Port 2 data direction register P2DDR 1 This register is a 2 bit register that controls the I O direction of port 2 data in 1 61 units Port P2n is placed in output mode when P2nDDR is set to 1 and in input mode when bit P2nDDR is set to 0 2 When bit P2nDDR is set to 0 and bit P2n of the port 2 data latch is set to 1 port P2n becomes input with a pull up resistor Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE49 00 P2DDR P21DDR P20DDR Register Data Port P2n State Internal Pull up Input Resistor Enabled OFF 0 0 1
22. O0 Enabled Internal pull up resistor O 1 Enabled Enabled High open CMOS N channel open drain 3 3 8 8 External interrupt 4 5 control register I45CR 1 Thisregister is an 8 bit register that controls external interrupts 4 and 5 Address Initial Value Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4A 0000 0000 R W I45CR FIXO FIXO FIXO FIXO INT4HEG INT4LEG INT4IF INT4IE FIXO bits 7 to 4 Fixed bits These bits must always be set to 0 INT4HEG bit 3 INT4 rising edge detection control INT4LEG bit 2 INT4 falling edge detection control INT4HEG INT4LEG INT4 Interrupt Conditions Pin Data 0 No edge detected Falling edge detected 0 s 1 0 JRisngedgedetcted INTAIF bit 1 INT4 interrupt source flag This bit is set when the conditions specified by INT4HEG and INT4LEG are satisfied When this bit and the INT4 interrupt request enable bit INTAIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 14 LC87BKO00 Chapter The interrupt flag however cannot be set by a rising edge occurring when the INT4 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when the INT4 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with INT4 it is recommended that INT4 be used in both edge interrupt mode This
23. and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs 2 e Go to 3 in step 7 if SITRUN is set to 1 If SILRUN is set to 0 implying an interrupt from 4 in step 7 clear SIIEND and SILOVR and return to 1 in step 4 3 e Read SBUFI and check transmission data as required Note Bit 8 of SBUFI is not yet updated because the rising edge of the 9th clock has not yet occurred Load SBUFI with the next output data Clear SIIEND and exit interrupt processing Release the clock port after the lapse of SBR1 value 1 3 x Return to 1 in step 7 if an acknowledge from the master is present L If there is no acknowledge from the master SIO1 recognizing the end of data transmission automatically clears SI1RUN and releases the data port However if the restart condition occurs just after the event SITREC must be set to 1 before exiting the interrupt SII REC is for detecting a start condition and is not set automatically It may disturb the transmission of address from the master if there is an unexpected restart just after the slave transmission when SII REC is not set to 1 by software 4 e When a stop condition is detected an interrupt is generated and processing returns to 2 in step 7 8 Terminating communication Set SITREC Return to in step 6 to automatically terminate communication To force communication to terminate clear SILRUN and
24. for details When the subclock is selected as the WDT clock WDTCKSL 1 When the watchdog timer is used with WDTCKSL set to 1 set EXTOSC OCR bit 6 to 1 and start the watchdog timer operation with a program control allowing the subclock oscillator to be stabilized If the CPU detects that the subclock oscillation has stopped when EXTOSC OCR bit 6 is set to 0 or when HOLD mode is entered while the watchdog timer 15 running the watchdog timer considers that a program runaway has occurred and triggers a WDT reset In this case WDTRSTF is set This mode is primarily used for applications using the real time clock to realize low power operation 4 28 4 6 4 6 1 LC87BKO00 Chapter 4 Internal Reset Function Overview This series of microcontrollers incorporates internal reset functions called the power on reset POR and low voltage detection reset LVD The use of these functions contribute to a reduction in the number of externally required reset circuit components reset IC etc 4 6 2 2 4 6 3 Functions Power on reset POR function POR is a hardware feature that generates a reset to the microcontroller when the power is turned on This function allows the user to select the POR release level by option only when the low voltage detection reset function is set to disable It is necessary to use the below mentioned low voltage detection reset function together with this function or configure an externa
25. oscillator started Note Low speed RC oscillator stopped Note Note Oscillation start stop control for low speed RC oscillator circuit is performed when WDTCKSL is set to 0 Figure 4 5 2 Sample Watchdog Timer Operation Waveforms 4 5 4 Related Register 4 5 41 WDT control register WDTCNT 1 This register is used to manipulate the WDT reset detection flag to select the standby mode operation to select the overflow time and to control the operation of the WDT Address Initial Value RW Name BIT7 BIT6 5 BIT4 BIT3 BIT2 BIT1 BITO 79 0000 0000 R W WDTCNT WDTRSTF WDTCKSL WDTRUN IDLOPI IDLOPO WDTSL2 WDTSL1 WDTSLO bit 7 WDT reset detection flag This bit 15 cleared when a reset 1s triggered by applying a low level signal to the external RES pin or by using the internal reset POR LVD function This bit 15 set when a WDT triggered reset occurs This flag can be rewritten with an instruction WDTCKSL bit 6 WDTCT input clock select WDTCKSL WDTCT Input Clock 0 Internal low speed RC oscillator Subclock 4 25 WDT WDTRUN bit 5 WDT operation control Setting this bit to 0 stops operation Setting this bit to 1 starts the WDT operation IDLOP1 bit 4 IDLOPO bit 3 IDLOP1 Standby mode operation select IDLOPO Standby Mode Operation 0 0 usaq Dh 1 o Stop count operation while retaining the count val
26. s s ss 5 s s _ 0000 0000 s S sz so s s ro www RW um o ew FEO EE its aksa ci 990 0 0 0 0 0 p eu E FETO TOT Timer contro TOM TG TOR TOTE i ew rors Tora TORNO 0 0 0 0 0 0 X X FETS ro 06 To Toc 3o FETA own TOR5 o oR 0 FETS 0000 006 WR RA RW RAW FE12 000000 R mo 102 E m FETE E a R TOCAN FE18 0000 0000 R W TICNT Timer 1 control TIHRUN TILRUN TILONG T1PWM 1 TILCMP TILIE FE19 0000 0000 RAN TIHPRC2 TIHPRC1 TIHPRCO TILCMP TILIE mu oo z TL rig oo R TM ric 0000 0000 THR FED 0 FEO FE08 FE09 FEN FEB FEOG FED _ FEOE DD D FED FE ECCE FEIS FEIS FE FEIA FEB FEIC FED R W
27. 0000 0000 R W PSW CY AC PSWBS5 PSWB4 LDCBNK OV CY bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are following four types of carries 1 Carry resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the high order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table look up instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table look up instruction 0 ROM ADR 0 to 1FFFF 1 ROM ADR 20000 to OV bit 2 Overflow flag OV 15 set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive number 2
28. 0000H Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO SFR space Note Some registers 9 bit 1 Bit instruction direct long Bit instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect A A A Non bit instruction direct short Figure 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the low order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the high order 9 bits in SP 2 after which SP is set to SP 2 Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address in the internal data memory space initialized to on reset FE00 0000 0000 R W AREG AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREGO 2 6 B Register B The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the
29. 1 e GE 3 53 3 9 2 Functions eee eee rere rere ee eee ree eee eee eee eee ee eee eee eee eee eee ee 3 53 3 9 3 Circuit Configuration mmm eee 3 54 3 9 4 SIO1 Communication Examples 3 58 3 9 5 Related Registers meme 3 62 3 10 AD Converter ADC12 mH HH 3 65 3 65 9310 2 Ereegnes 3 65 3 10 3 Circuit mme 3 66 3 10 4 Related Registers meme 3 66 3 10 5 AD Conversion Example mmm 3 70 3 10 6 Hints on the Use of the ADC E 3 71 Chapter 4 Control Functions 4 1 Interrupt Function ees 4 1 4 1 1 Overview eee ere reece eee ere eee eee eee eee eee eee eee ee eee eee ee eee eee eee eee ee eee eee eee 4 1 4 1 2 Functions 4 1 41 3 Circuit Configuration Frkurrussrssyusesyuyuesuyuesanesusuesensensseenssenssesssssssisesssesseessseses 4 2 4 1 4 Related Registers eee eee eee ee ee eee eee eee ee eee eee eee eee ee eee ee ee ee eee 4 3 4 2 System Clock Generator Function n M M 4 5 4 2 1 Overview eee eee errr ere eee eee eee eee eee eee rere eee ee eee eee eee eee eee ee ee eee ee eee 4 5 4 2 2 Functions eee eee eee eee ere ee eee eee eee eee ee eee ee ee eee ee eee ee eee eee ree 4 5 4 2 3 Circuit Configuration Pee eee eee eee eee
30. BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0000 0000 R TIL TIL7 T1L6 TILS TIL3 112 TILO 3 6 4 4 Timer 1 high byte T1H 1 This is a read only 8 bit timer It counts up on the prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITO FEIB 0000 0000 R TIH 6 5 4 T1H3 2 T1HO 3 6 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte 2 The match buffer register is updated as follows When it is inactive TILRUN O the match buffer register matches TILR When it is active TILRUN 1 the match buffer register is loaded with the contents of when the value of reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITO FEIC 00000000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO 3 6 4 6 Timer 1 match data register high byte TTHR 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte 2 The match buffer register is updated as follows When it is inactive TIHRUN O the match buffer register matches
31. OL capture input function A timer OL capture signal is sent each time a signal change that sets the interrupt flag is supplied to a port selected from P70 and P16 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle intervals for the duration of the input signal 5 Timer capture input function A timer capture signal is sent each time a signal change that sets the interrupt flag is supplied to a port selected from P17 and 15 When a selected level of signal is input to P17 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle intervals for the duration of the input signal 3 5 Port 1 6 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTI or INT2 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode main oscillation by medium speed RC or low speed RC oscillator When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When the signal level that sets an interrupt flag is input to P17 that is specified for level triggered interrupts in HOLD mode the interrupt flag is set In this case if the corresponding interrupt enable flag is set HOLD mode is released When a signal change that sets an interrupt flag is input to P16 in HOLD mode the interrupt flag is set In thi
32. SIIEND release the clock port e An interrupt occurs when a stop condition is detected Then clear SILEND and SIIOVR and return to 2 in step 4 3 9 5 Related Registers 3 9 5 1 5101 control register 5 1 1 Thisregister is an 8 bit register that controls the operation and interrupts of SIOI Address initial Value RW Name e BITS Bits R W 0000 0000 R W SIIMO SIIRUN SIIREC SIIDIR SILOVR SIIEND SI1M1 bit 7 SIO1 mode control SI1MO bit 6 SIO1 mode control Table 3 9 2 5101 Operating Modes Operating Mode Synchronous 8 bit SIO UART 1 stop bit no parity 3 62 LC87BKO0 Chapter SI1RUN bit 5 5101 operation lt 1 gt Alin this bit indicates that SIOI is running 2 See Table 3 9 1 for the conditions for setting and clearing this bit SI REC bit 4 SIO1 receive transmit control lt 1 gt Setting this bit to 1 places SIO1 into reception mode 2 Setting this bit to 0 places SIO1 into transmission mode SI DIR bit 3 MSB LSB first select lt l gt A 1 in this bit selects MSB first lt 2 gt this bit selects LSB first SI1OVR bit 2 SIO1 overrun flag lt l gt This bit is set when the falling edge of the input clock is detected with SITRUN 0 in modes 0 1 and 3 lt 2 gt This bit is set if the conditions for setting SITEND are established when SI1END 1 lt 3 gt In mode 3 this bit is set when the start con
33. Secure a data setup time then manipulate the data output port PI4FCR 0 P14DDR 1 P14 1 and set the data output to 1 In this case the SIO1 overrun flag SIILOVR SCONI FE34 bit 2 is set but this will exert no influence on the operation of SIOI Restore the data output port to the original state set PI4FCR to 1 then PIADDR to 1 and P14 to 0 Clear SILEND and 5 then exit interrupt processing Return to step 4 to repeat operation 3 60 LC87BKO0 Chapter 3 9 4 4 Bus slave mode mode 3 2 3 4 5 7 Setting clock Setup SBRI to set the acknowledge data setup time Setting the mode Set as follows SIIMO 1 SIIMI1 1 SIIDIR SHIE 1 SILREC 0 Setting up ports Configure the clock port P15 and data port P14 as N channel open drain output ports by setting the option Set P14 P1 bit 4 and P15 P1 bit 5 to 0 Set PIAFCR PIFCR bit 4 and PISFCR 1 bit 5 to 1 Set PIADDR PIDDR bit 4 and PISDDR PIDDR bit 5 to 1 Starting communication waiting for an address e Set SIITREC 2 e SIIRUN is automatically set on detection of a start bit Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs Checking address data after an interrupt e When a start condition is detected SILOVR is set Check SIITRUN 1 and SIIOVR 1 to determine if the address has been rece
34. When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC87BK00 Chapter 2 3 When the high order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the high order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 4 1 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there is an odd number of 175 in A register It is cleared to 0 when there is an even number of 175 in the A register 2 9 Stack Pointer SP LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the microcontroller type The SP is 16 bits long and made up of two registers SPL at address and SPH at address It is initialized to 0000H on reset The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory Address Initial Value R W Name BIT7 6 5 BIT4 BITS BIT2 BIT1 BITO FEOA 0000 0000 R W SPL SP7
35. a debugging function it is generally necessary to mount the components that are recommended for connection listed in the table on page 11 of the RD87 On chip Debugger Installation Guide on the circuit board of mass production sets Pins that are not used for onboard reprogramming on the mass production set however can be treated by installing a minimum number of external components and observing the following restriction conditions for the reasons that are described in the previous section Debugger Pin Name Pin Set Specification Restrictions and Components to Install Remarks DBGPO00 DBGP10 Input I O analog input Insert a current limiting resistor of 1000 or more Reference DBGPX0 DBGP20 Ges 1 Output Output restrictions No restrictions and no components need to be installed no No restrictions and no components need to be installed need to be installed DBGPOI DBGP11 Input I O output No restrictions and no components need to be installed DBGP21 analog input DBGP02 DBGP12 Input Make sure that no pulses of 100 kHz or higher are input DBGP22 during the system reset sequence When a pulse of 100 kHz or more is to be input assign the pulse signal to a different pin Pull up or down the pin that is placed in the floating Reference Hi Z state during the system reset sequence using a example 2 100 resistor Note 2 For LC87F2416A up or down the pin using a 100 Reference
36. and selects its detection level See Subsection 4 6 4 External capacitor Core Pull up resistor Regs After the reset signal from the internal reset circuit 15 released the reset period 15 further stretched according to the external CR time constant This enables the microcontroller to avoid repetitive entries and releases of the reset state from occurring when power on chatter occurs The circuit configuration shown in Figure 4 6 1 in which the capacitor and pull up resistor Bar are externally connected is recommended when both POR and LVD functions are to be used The recommended constant values are Cres 0 022 uF and Rers 510 The external pull up resistor must always be installed even when the set s specifications inhibit the installation of the external capacitor Cres to the reset pin 4 29 Internal Reset Interior of microcontroller Rres 510 Reset Cres 0 022u F Power on reset POR Low voltage detection reset LVD Pulse stretcher Figure 4 6 1 Internal Reset Circuit Configuration 4 6 4 Options The POR and LVD options are available for the reset circuit 1 LVD Reset Function Options Enable Use Disable Non use 2 LVD Reset Level Option 3 POR Release Level Option Typical Value of Min Operating Typical Value of Min Operating Selected Option VDD Value Selected Option VDD Value 2 57V 2 7V to 2 81V 2 87V 3 0V to 3
37. bit must be cleared with an instruction as it is not cleared automatically INTAIE bit 0 INT4 interrupt request enable When this bit and INTAIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 3 8 4 External interrupt 4 5 pin select register 14551 1 Thisregister is an 8 bit register used to select pins for the external interrupts 4 and 5 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE4B 0000 0000 R W 14551 FIXO FIXO I4SL3 14512 14511 14510 FIXO bits 7 to 4 Fixed bits These bits must always be set to 0 I4SL3 bit 3 INT4 pin select 14512 bit 2 INT4 pin select 14513 14512 Pin Assigned to INTA 0 0 20 D 1 L1 O 14511 bit 1 INT4 pin function select 14510 bit 0 INT4 pin function select When the data change specified in the external interrupt 4 5 control register 145 is given to the pin that is assigned to timer 1 count clock input and timer 0 capture signal are generated 14511 14510 Function other than INT4 Interrupt 0 None Timer 1 count clock input 0 s 0 Timer OL capture signal input Timer 0H capture signal input Notes 1 When timer OL capture signal input or timer OH capture signal input is specified for INT4 together with P70 or P17 to P15 the signal from P70 or P17 to P15 is ignored 2 When INT4 is specified as time
38. carried out in the 12 bit AD conversion mode for the first time after a system reset The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula given in the paragraph entitled Conversion time calculation formulas is required in the second and subsequent conversions or in AD conversions that are carried out in the 8 bit AD conversion mode The conversion result data contains some errors quantization error combination error Be sure to use only valid conversion results based on the specifications provided in the latest Semiconductor Data Sheet Make sure that only input voltages that fall within the specified range are supplied to PO0 ANO to P06 AN6 and P70 AN8 Application of a voltage higher than VDD or lower than VSS to an input pin may exert an adverse influence on the conversion value of the channel in question or of other channels Take the following measures to prevent a reduction in conversion accuracy due to noise interferences etc e Add external bypass capacitors several uF thousands of pF near the VDD1 and VSS1 pins as close as possible desirably 5 mm or less Add external low pass filters RC or capacitors most suitable for noise reduction very close to the analog input pins To avoid any adverse coupling influence use a ground that is free of noise interference as the ground for the c
39. conversion resolution can be selected according to the operating conditions of the application The AD mode register ADMRC is used to select the AD conversion mode 3 S channel analog input The signal to be converted is selected using the AD control register ADCRC from 8 types of analog signals that are supplied from to 06 and 70 4 Conversion time selection The AD conversion time can be set from 1 1 to 1 128 frequency division ratio The AD mode register ADMRC and AD conversion result register low byte ADRLC are used to select the conversion time for appropriate AD conversion 5 Itis necessary to manipulate the following special function registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Address Initial Value BIT4 BIT2 BIT1 AD AD AD FESS 00000000 CHSEL3 CHSEL2 CHSELI CHSELO START ENDF ADMR2 ADTMI ADRL2 ADRLI ADTM2 DATA DATAO 3 65 ADC12 3 10 3 Circuit Configuration 3 10 3 1 AD conversion control circuit 1 Thiscircuit runs in two modes 12 and 8 bit AD conversion modes 3 10 3 2 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion results The conversion end flag ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the A
40. ee eee ee eee ee eee eee ee eee eee eee eee ee eee ee eee 4 6 4 2 4 Related Registers Fekuesyusrauysuessyesanesuneeussenuneepssessseesssesssesssesssesssessseessseses 4 8 4 2 5 Example of Switching the CF Oscillation Amplifier Size 8 4 13 4 3 Standby Function eHHMHHHRHRHHMMHHHHHMMMMHHHMMMHMMMMHHMMHHMHHHMHHHHHeH 4 14 4 3 1 Overview eee eee re eee ere ree eee ree reer OTTO 4 14 4 3 2 Functions 4 14 4 3 3 Related Register eee eee eee eee eer eee ee eee eee eee eee eee eee eee eee ee eee eee 4 15 4 4 Reset Function eee eee eee reer reer errr errr errr errr crete rere rer rrr 4 20 4 4 1 Overview DUTOT OTTO OTTO 4 20 4 4 2 Functions FasuruuhesyyseeseesuuesusuensssesssenssranssassuAsspeseseesspesuessessseesssesssesssessse 4 20 4 4 3 Reset State eee reer erect err ee ere rere rere ree ee rere eee rere eee eee eee ere rer 4 21 4 5 Watchdog Timer WDT 0000000000000 0 L9Q 4 22 4 5 1 Overview eee eee eee eee eee eee eee eee ee eee eee eee ee eee eee eee ee eee eee eee eee ee eee eee ee 4 22 4 5 2 Functions eee eee eee eee ee eee rere eee eee ee eee ee eee ee ee ee eee eee eee eee ree eee ee ee eee ee 4 22 4 5 3 Circuit Configuration eee eee eee eee eee eee ee eee eee eee eee eee eee eee eee eee 4 23 Contents 4 5 4 Related Register Frksrrsyusrasyursasyuessuysesaunensuuenuseenssessseesnssessp
41. function control This bit controls the output data at pin P10 When P10 is placed in output mode PIODDR 1 and P10FCR is set to 1 the value of the port data latch is placed at pin P10 3 8 LC87BKO0 Chapter 3 2 8 4 External interrupt 0 1 control register 01 1 Thisregister is an 8 bit register that controls external interrupts 0 and 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIF INTHE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P17 Pin Data 0 0 Falling edge detected 0 1 Low level detected 1 0 JRisingedge detected High level detected INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit INTIIE set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INT
42. is set to 0 P03 to POO are placed in the input mode POFLG is set when a low level is detected at a port whose corresponding port 0 data latch PO bit is set to 1 P07 to P04 pull up resistor selection settings POHPUS POHPU Port for Which POHDDR 0 and CMOS Option is Specified X 0 Pull up resistor OFF X 0 Pulupresistor OFF o 1 Low impedance pull up resistor ON High impedance pull up resistor ON P03 to P00 pull up resistor selection settings POLPUS POLPU Port for Which POLDDR 0 and CMOS Option is Specified x 0 Pull up resistor OFF Pull up resistor OFF o 0 1 Low impedance pull up resistor ON High impedance pull up resistor ON 3 1 3 3 Port 0 function control register POFCR 1 Thisregister is a 6 bit register that controls the multiplexed pin outputs of port 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 00HH 0000 R W POFCR 7 T6OE CLKOEN CKODV2 CKODVI CKODVO 7 bit 7 This bit controls the output data at pin 7 This bit is disabled when P07 is in input mode When P07 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 7 and the value of the port data latch T6OE bit 6 This bit controls the output data at pin P06 This bit is disabled when P06 is in input mode When P06 is in output mode 0 Carries the v
43. level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 ee 1 O J Subclock Timer counter 0 prescaler output BUZON bit 3 Buzzer output timer 1 PWMH output select When P17FCR bit 7 is set to 1 this bit selects the data buzzer output or timer 1 PWMH output to be sent to P17 When this bit is set to 1 the timer 1 PWMH output is fixed high and a signal derived by dividing the base timer clock by 16 fBST 16 is sent to P17 as buzzer output When this bit is set to 0 the buzzer output is fixed high and the timer 1 PWMH output data is sent to 17 fBST The frequency of the input clock to the base timer that is selected through input signal select register ISL bits 5 and 4 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select NFSEL NFON Noise Filter Time Constant Tcyc STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When this bit is set to 1 a timer 0 count clock is generated when an input that satisfies
44. measures be taken to stop the base timer before placing the CPU in HOLD mode See Section 4 2 System Clock Generator Function for the state of the oscillator circuits in standby mode Counting errors may occur in the base timer if the base timer clock source is changed change ISL bits 5 and 4 while the base timer is running Be sure to stop the base timer in advance when changing the base timer clock source 3 8 4 2 Input signal select register ISL 1 This register is an 8 bit register that is used to control the timer 0 input noise filter time constant to select buzzer output timer 1 PWMH output and to select base timer clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN STOHCP bit 7 Timer OH capture signal input port select STOLCP bit 6 Timer OL capture signal input port select These 2 bits have nothing to do with the control function of the base timer bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 gt H 4 Pp 1 O _ Sublok Timer counter 0 prescaler output BUZON bit 3 Buzzer output timer 1 PWMH output select This bit selects data buzzer output or timer 1 PWMH to be transferred to P17 when P17FCR PIFCR bit 7 is set to 1 When this bit is set to 1 the timer 1 PWMH output is
45. one of INTO INT1 INT2 and INT4 pins INTO and X tal HOLD mode release is available only when level detection is set 5 Establishing an interrupt source at port 0 67 Establishing an interrupt source in the base timer circuit Note Available only when X tal oscillation is selected 1 4 LC87BKO00 Chapter 1 On chip debugger function flash ROM version only Supports software debugging with the microcontroller mounted on the target board Software break setting Stepwise execution of instructions Real time RAM data monitoring function the memory contents can be monitored and rewritten when the program 15 running Part of the special function register SFR data cannot be rewritten Two channels of on chip debugger pins are available for compatibility with small pin count devices DBGPO P0 DBGP1 P1 Data security function flash ROM version only Protects the program data stored in flash memory from unauthorized read or copy Note This data security function does not necessarily provide absolute data security Package form 245 300mil Lead free and halogen free product e SSOP24 225mil Lead free and halogen free product e SSOP24 275mil Lead free and halogen free product make to order e VCT24 3mm x 3mm Lead free and halogen free product make to order Development tools On chip debugger lt 1 gt 87 Type LC87FBK08A lt 2 gt 87 Type 3 wi
46. oscillator low speed medium speed multifrequency RC oscillators and crystal oscillator automatically stop operation Note The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer 2 There are five ways of releasing HOLD mode lt 1 gt Low level input to the reset pin lt 2 gt Generating a reset by low voltage detection lt 3 gt Generating a reset by the watchdog timer lt 4 gt Establishing an interrupt source at least at one of INTO INT1 INT2 and INT4 pins INTO and INTI HOLD mode release is available only when level detection is set lt 5 gt Establishing an interrupt source at port 0 e X tal HOLD mode Suspends instruction execution and the operation of the peripheral circuits except the base timer when X tal oscillator is selected 1 The CF low speed medium speed multifrequency RC oscillators automatically stop operation Note The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer 2 The state of crystal oscillation established when X tal HOLD mode is entered is retained 3 There are six ways of releasing X tal HOLD mode lt 1 gt Low level input to the reset pin lt 2 gt Generating a reset by low voltage detection lt 3 gt Generating a reset by the watchdog timer lt 4 gt Establishing an interrupt source at least at
47. output mode PI6DDR 1 and P16FCR is set to 1 the EOR of timer 1 PWML output data and the port data latch is placed at pin P16 P15FCR bit 5 P15 function control SIO1 clock output control This bit controls the output data at pin P15 When P15 is placed in output mode PI5DDR 1 and PISFCR is set to 1 the OR of the SIO1 clock output data and the port data latch is placed at pin P15 P14FCR bit 4 P14 function control SIO1 data output control This bit controls the output data at pin P14 When P14 is placed in output mode PI4DDR 1 and 14 is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P14 When the SIO1 is active SIO1 input data is read in from P14 regardless of the I O state of P14 P13FCR bit 3 P13 function control SIO1 data output control This bit controls the output data at pin P13 When P13 is placed in output mode PI3DDR 1 and P13FCR is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P13 P12FCR bit 2 P12 function control This bit controls the output data at pin P12 When 12 is placed in output mode PI2DDR 1 and P12FCR is set to 1 the value of the port data latch is placed at pin P12 P11FCR bit 1 P11 function control This bit controls the output data at pin P11 When P11 is placed in output mode PI 1DDR 1 and P11FCR is set to 1 the value of the port data latch is placed at pin P11 P10FCR bit 0 P10
48. resistor example 3 For models other than LC87F2416A pull up the pin Note 2 with a 100 resistor Analog input When the analog input impedance is high 5 or Reference more or when noise is easily superimposed onto the example 4 analog input signal assign the analog channel to a Note 3 different pin Unused N C Select an N channel open drain output port with a port option and short circuit the pin to VSS1 GND in input mode Note 1 The set may not operate properly after the reset 15 released unless it is subjected to pin treatment that complies with the set specifications Note 2 Depending on the microcontroller output status current may flow to the external pull up or pull down resistors when standby mode 15 entered so be sure to set these pins to the same potential or Hi Z before entering standby mode AIIT 1 On chip Debugger Pin Treatment Note 3 Assign the DBGPx2 pins to applications with few data changes due to digital I O whenever possible Reference example 1 Limits the through current during system reset When Pch Tr is ON during system reset Insert 100 Q or more Reference example 2 DBGPx0 Pch Tr OFF during system reset Microcontroller interior Nch Tr ON during the system reset period or for several us after reset is released Digital input Prevents floating status Hi Z during system reset Pull up resistor several to 100kQ
49. selected by the input signal select register ISL It generates a 2 kHz buzzer output and base timer interrupt 1 flag set signals The overflow from this counter serves as the clock for the 6 bit binary counter 3 8 3 2 6 bit binary up counter 1 This counter is a 6 bit up counter that receives as its input the signal selected by the input signal select register ISL or the overflow signal from the 8 bit counter It generates base timer interrupt 0 1 set signals The switching of the input clock is accomplished by the base timer control register BTCR 3 8 3 3 Base timer input clock source 1 clock input to the base timer be selected from among the cycle clock timer counter 0 prescaler output and subclock by the input signal select register ISL Set in ISL FE5Fh register 16tBST Buzzer output Tcyc Timer 0 prescaler e MESI 8 bit counter DB Subclock 256tBST 16384 64tBST 6 bit counter gt BTIFO flag set Selector gt BTIF1 flag set Selector Figure 3 8 1 Base Timer Block Diagram 3 50 LC87BKO0 Chapter 3 8 4 Related Registers 3 8 41 Base timer control register BTCR 1 Theregister is an 8 bit register that controls the operation of the base timer Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE7F 0000 0000 R W BTCR BTFST BTON BTC10 BTIFI BTIFO BTIEO BTFST b
50. shifter at beginning of operation Rising edge of 8th clock Input data read in on rising edge of 9th clock 1 P13 13 output control lt SIO1 output control gt P14 port latch P14 P14 output control Clock Clock generator circuit Baudrate generator Serial transfer end flag MSB LSB first select SBR1 FE36h Overrun flag Y Vv SIO1 output control ae P15 port latch 15 P15 output control bit7 bite bit5 bit4 bit3 bit2 bit SCON1 FE34h Figure 3 9 1 3 56 S Interrupt request SIO1 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1 0 SI1M0z0 LC87BKO0 Chapter Start bit additional circuit Shift input Shift input Start stop bit additional circuit At time operation starts LSB MSB first select 8 bit shift register SIOSF1 Shift clock transfer ends Stop bit data input SIO1 output control gt gt P13 P13 port latch P13 output control SBUF1 FE35h Stop bit input clock Clock generator circuit Baudrate Set SEND when generator stop bit data ends SBR1 FE36h SIO1 output control P14 port latch 2 L m SH P14 output control Overrun flag Em SCON1 FE34h Interrupt request Figure 3 9 2 5101 Mode 1 Asynchronous
51. the settings of CKODV2 to CKODVO bits 2 to 0 Do not change the system clock selection when CLKOEN bit 3 is set to 1 Do not change the settings of CLKCB5 and CLKCBA bits 5 and 4 of the OCR register SLRCSEL bit 1 of SLWRC register and MRCSEL bit 7 of MRCR register CLKOEN will not go to 0 immediately even when the user executes an instruction that loads the POFCR register with data that sets the state of CLKOEN 3 from 1 to 0 CLKOEN is set to 0 at the end of the clock that is being output on detection of a falling edge of the clock Accordingly when changing the frequency division setting of the clock or changing the system clock selection after setting CLKOEN to 0 with an instruction be sure to read the CLKOEN value in advance and make sure that it is 0 3 1 4 Options Two user options are available 1 2 CMOS output with a programmable pull up resistor N channel open drain output 3 1 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port 0 retains the state that is established when HALT HOLD mode is entered 3 4 LC87BKO0 Chapter 3 2 Port 1 3 2 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It consists of a data latch a data direction register a function control register and a control circuit The I O direction is determined by the data direction register in 1 bit units Port 1 can also be used as a serial interface I O port or PWM outpu
52. timer OH capture signal input is specified for INT4 together with P70 or P17 to PI5 the signal from P70 or P17 to P15 is ignored 3 4 4 Options There is no user option for this port 3 4 5 HALT and HOLD Mode Operation The pull up resistor of P70 is turned off 3 22 LC87BKO00 Chapter 3 3 5 Timer Counter 0 TO 3 5 1 Overview The timer counter 0 TO incorporated in this series of microcontrollers 15 a 16 bit timer counter that has the following four functions 1 2 3 4 Mode 0 8 bit programmable timer with a programmable prescaler with 8 bit capture register x 2 channels Mode 1 8 bit programmable timer with a programmable prescaler with an 8 bit capture register 8 bit programmable counter with an 8 bit capture register Mode 2 16 bit programmable timer with a programmable prescaler with a 16 bit capture register Mode 3 16 bit programmable counter with a 16 bit capture register 3 5 2 Functions 1 2 Mode 0 8 bit programmable timer with a programmable prescaler with an 8 bit capture register x 2 channels Two independent 8 bit programmable timers TOL and TOH run on the clock with a period of 1 to 256 from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P16 INT2 TOIN P20 and P21 timer OL capture input pins The contents of TOH are captured into the ca
53. timer interrupt 1 request enable control Setting this bit and 1 to 1 generates an X tal HOLD mode release signal and an interrupt request to vector address 001BH BTIFO bit 1 Base timer interrupt 0 flag This flag is set at the interval of the base timer interrupt 0 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIEO bit 0 Base timer interrupt 0 request enable control Setting this bit and BTIFO to 1 generates an X tal HOLD mode release signal and an interrupt request to vector address 001BH 3 51 Notes Set the conditions under which the flags BTIF1 BTIFO are set at intervals of the base timer interrupt period so that the period of the cycle clock Tcyc and the base timer interrupt period satisfy the following relationship Period of cycle clock Tcyc lt Base timer interrupt period 2 Since program processing e g interrupt processing routine is involved in practice the time that is required to execute such processing should be taken into consideration when setting up the optimum interrupt period Note that there are cases 1 is set to 1 if BTCII or BTCIO is rewritten when the base timer is active If the crystal oscillator subclock is selected as the base timer clock source erroneous counting may occur in the base timer because oscillation stabilization time cannot be secured when HOLD mode is exited It is therefore recommended that
54. 00 0000 R W 1230 INT2 INT3 control INT3HEG INTSLEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE FEF ooo WK ii O Lang sm Tam Bw WoW T T T L TL T L TL T T m T T T I TT _ T FE63 FE64 ees cc noxae clu j j j e C E Cf C E h C h h r E r gt FEI FE78 0000 0000 T67CNT Timer 1 control EE 1761 1760 T6C1 1660 T70V T7IE T60V 0000 0000 RA WTOHT Watchdog timer contro WOTOG ID OPT 0 wrsta worsto 0000000 m T mee Tes Tes Tort 0000 0000 TR rm Ts ve rm rm vm rm rec mm ww s L T Ll 1 Lesen AI 4 LC87BK00 APPENDIX I Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO FE7D FE7E 0000 0000 R W FSRO FLASH control bit4 is R O UH FSROB7 FSROB6 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ Fix to 0 Fix to 0 0000 0000 R w Base timer control BIFST Bron BICI BTIFI BTIEI BTIFO BIIEO Ec uec fh E E EEN 2 22 49 z EE j P pugni ecco We sr 5 5 s xr 2 EE E E
55. 00H to FDFFH Consequently it is not possible to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when R5 contains and the C register contains 1 since the basic area is 3 RAM stack area OOOOH to the intended address OFDFFH 1 lies outside the basic area and OFFH is consequently placed in the ACC as the result of LD If the instruction LD R5 C is executed when R5 contains OFEFFH and the C register contains 2 since the basic area is 2 SFR area to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of the computation OFFO1H amp OFFH 0FEO0H 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off In this addressing mode the results of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains 2 and off has a value of 7EH 2 for example the A register FEO2H 2 FE00H is designated Examples When RO contains 123 RAM address 0 23H RAM address 1 01H LD 10H Trans
56. 12 3 10 5 3 10 5 1 1 2 3 4 5 6 AD Conversion Example 12 bit AD conversion mode Setting up the 12 bit AD conversion mode Set ADMD3 bit 6 of the AD mode register ADMRC to 0 Setting up the conversion time set the conversion time to 1 32 frequency division ratio set ADTM2 bit 0 of the AD conversion result register low byte ADRLC to 1 ADTMI bit 1 of the AD mode register ADMRC to 0 and ADTMO bit 0 of the AD mode register ADMRC to 1 Setting up the input channel When using AD channel input ANS set the AD control register ADCRC ADCHSEL3 bit 7 to 0 ADCHSEL2 bit 6 to 1 ADCHSEL1 bit 5 to 0 and ADCHSELO bit 4 to 1 Starting AD conversion Set ADSTART bit 2 of the AD control register ADCRC to 1 The conversion time is doubled when the AD conversion is carried out for the first time after a system reset or after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula is required in the second and subsequent conversions Checking the AD conversion end flag Monitor ADENDF bit 1 of the AD control register ADCRC until it is set to 1 e Clear the conversion end flag ADENDF to 0 after confirming that ADENDF bit 1 is set to 1 Reading the AD conversion results Read the AD conversion result register high byte ADRHC and AD conversion result register low byte ADRLC Since the conversion resul
57. 3 Related Registers 3 2 3 1 Port 1 data latch P1 1 Thislatch is an 8 bit register that controls port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If P1 FE44 is manipulated using a NOTI CLRI SETI DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W Pl P17 P16 P15 P14 P13 P12 P11 P10 3 6 LC87BKO0 Chapter 3 2 3 2 Port 1 data direction register PIDDR 1 This register is 8 bit register that controls the I O direction of port 1 data in 1 bit units Port is placed in output mode when bit PInDDR is set to 1 and in input mode when bit PInDDR is set to 0 2 When bit PInDDR is set to 0 and bit PIn of the port 1 data latch is set to 1 port PIn becomes an input with a pull up resistor Address Initial Value R W Name BIT7 6 5 4 2 BITO 45 0000 0000 R W PIDDR P17DDR PI6DDR PISDDR PI4DDR PI3DDR P12DDR P11DDR PIODDR Register Data Port Pin State Internal Pull up Input Resistor 0 0 Enabled OFF 1 O Enabled Internal pull upresistor ON 0 1 Enabled OFF 3 2 3 3 Port 1 function control register P1FCR 1 Thi
58. 3 Related Registers FurasassusuuuanensunsusssesunsunsuseunssssaAnassusunsusensunsussseunensunsus 3 18 3 4 4 Options 3 22 3 4 5 HALT and HOLD Mode Operation Fuuuusssssyuansassusuuunmuuussununsausenensuaumsusensunsanus 3 22 3 5 Timer Counter 0 TO 3 23 3 5 1 Overview FuuusassssunuamssusumsusuassczsensususcssunsaHsausunsnsausunensuuasusSssashEREsSAsERRRRSAS 3 23 3 5 2 Functions wuruusassssuuuassansuumuuumsusussunsuasusunsnunuaususssssaSasassusuuuimssussununusausussnsunsuse 3 23 3 5 3 Circuit Configuration wuruusassusuuuumsusssassnuuuassansuunuuimisesssensusuausunsnsuunaseussusuuuanen 3 24 3 5 4 Related Registers Furuasassssunuuazsemuunuansansunumssuusususssssusssessanuasenseunsusassunsuuunsus 3 29 3 6 Timer Counter 1 T1 TTT 3 32 3 6 1 Overview 3 32 3 6 2 Functions wurusssesssuuuasansusunuymnaSssunsusausunsnsuaunmu5unsuusuuuassuuuunaecesumnsuuasusunsnsuuause 3 32 3 6 3 Circuit Configuration
59. 5 6 7 Immediate Immediate data refers to data whose value has been established at program preparation assembly time Indirect register Rn indirect 0 lt n lt 63 Indirect register Rn C register indirect 0 lt n lt 63 Indirect register RO Offset value indirect Direct ROM table look up External data memory access The rest of this section describes these addressing modes 2 11 1 Immediate Addressing The immediate addressing mode allows 8 bit 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD 12H Ll LDW 1234H PUSH 349 ADD 56H BE 78H L1 Loads the accumulator with byte data 12H Loads the BA register pair with word data 1234H Loads the stack with byte data 34H Adds byte data 56H to the accumulator Compares byte data 78H with the accumulator for a branch 2 6 LC87BK00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected register contains for example 2 it designates the C register Examples When R3 contains 123 RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator 11 STW R3 Transfers the contents of BA register pair to RAM addres
60. 79V 3 86V 4 0V to 4 28V 4 35V 4 5V to The minimum operating VDD value specifies the approximate lower limit of the VDD value beyond which the selected POR release level or LVD reset level cannot be effected without generating a reset 1 LVD reset function option When Enable is selected a reset is generated at the voltage that is selected by the LVD reset level option Note 1 In this configuration an operating current of several uA always flows in all modes No LVD reset is generated when Disable is selected Note 2 In this configuration no operating current flows in all modes See the sample operating waveforms of the reset circuit shown in Subsection 4 6 5 for details 2 LVD reset level option The LVD reset level can be selected from 3 level values only when Enable is selected in the LVD reset function options Select the appropriate detection level according to the user s operating conditions 3 POR release level option The POR release level can be selected from 4 level values only when Disable is selected in the LVD reset function options When not using the internal reset circuit set the POR release level to the lowest level 2 57V that will not affect the minimum guaranteed operating voltage Note 3 No operating current flows when the POR reset state is released Note 4 See the notes on the use of the internal reset circuit in paragraph 2 of Subsection 4 6 6 when selecting a PO
61. 8 8 Shift data 15 Shift data 15 Shift data 1 Shift data 1 8 Data input 8 8 lt lt 8 lt Input pin Input pin Input pin Input pin S it None Output Input Input Output Input High H L H L SBUF1 bit8 H L L top b Clock 9 lt lt Low output Internal on falling edge of 8th 8 Operation start SIIRUN T 1 1 on left side 1 on right No start bit on falling released on falling edge of SILEND With start bit 1 on rising edge of SH RUN SILRUN 0 when and SIIEND 0 5 0 Period 2 to 512 lt 8102048 lt 2 to 512Tcyc 2 to 512Tcyc lt Tcyc Tcyc SIIRUN Set Instruction lt 1 Start bit Instruction Already set Already set Start bit bit 5 Instruction detected 2 Start bit detected Clear End of lt End of stop lt 1 1 processing bit Stop Stop condition condition detected detected 2 2 When Ack 1 arbitration detected lost Note 1 Set End of lt End of stop lt D e 1 processing bit Rising edge Falling edge of 9th clock of 8th clock 2 2 Stop Stop condition condition detected detected SIIEND bit 1 Note 1 If internal data output value and data port value L are detected on the rising edges of the Ist to Sth clocks the CPU recognizes bus contention loss and clears SIIRUN and also stops sending the clock at the same time Continued on next page 3 55 SIO1 Tab
62. B register designates the high order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to 00H on reset Address Initial Value R W Name BIT7 6 5 BIT4 BITS BIT2 BIT1 BITO FEO1 0000 0000 R W BREG BREG7 BREG6 2 3 5 4 BREG2 BREGI BREGO 2 7 Register The register is used with ACC and register to store results of computation during execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address 2 of the internal data memory space and initialized to on reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 CREGS CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation results a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to on reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE06
63. BRI value 1 x 2 Tcyc Value range 2 to 512 Tcyc Mode 1 TSBRI SBRI value 1 x 8 Tcyc Value range 8 to 2048 Tcyc 3 63 SIO1 4 When in mode 3 the register sets the acknowledge data setup time See 3 9 4 4 6 7 When setting to mode 3 time that clock port is released after SIIEND is cleared is SBRI value 1 3 5 0 is inhibited Set this value to meet the opponent device s data setup time Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRGI7 SBRGI6 SBRGI5 SBRG14 SBRGI3 SBRGI2 SBRG11 SBRG10 3 64 LC87BKO0 Chapter 3 10 AD Converter ADC12 3 10 1 Overview This series of microcontrollers incorporates a 12 bit resolution AD converter that has the features listed below It allows the microcontroller to capture analog signals easily 1 12 bit resolution 2 Successive approximation 3 AD conversion mode selection resolution switching 4 8 channel analog input 5 Conversion time selection 3 10 2 Functions 1 Successive approximation The AD converter has a resolution of 12 bits Some conversion time is required after starting conversion processing The conversion results are transferred to the AD conversion result registers ADRLC ADRHC 2 AD conversion mode selection resolution switching The AD converter supports two AD conversion modes 12 and 8 bit conversion modes so that the appropriate
64. CALA TOCAL3 TOCAL2 TOCALI TOCALO rez ToCAHT TOCAH6 TOCAHS TOCAH4 TOCAH3 TOCAH2 TOCAHI 3 5 3 Circuit Configuration 3 5 3 1 Timer counter 0 control register TOCNT 8 bit register 1 Thisregister controls the operation and interrupts of TOL and 3 24 LC87BKO00 Chapter 3 3 5 3 2 Programmable prescaler match register TOPRR 8 bit register 1 3 5 3 3 1 2 3 4 3 5 3 4 1 2 3 4 3 5 3 5 1 2 3 4 3 5 3 6 1 2 3 5 3 7 1 2 This register stores the match data for the programmable prescaler Programmable prescaler 8 bit counter Start stop This register runs in modes other than HOLD mode Count clock Cycle clock period 1 Tcyc Match signal A match signal is generated when the count value matches the value of the register TOPRR period 1 to 256 Tcyc Reset The counter starts counting from 0 when a match signal is generated or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop Stop start is controlled by the 0 1 value of TOLRUN timer 0 control register bit 6 Count clock Either a prescaler match signal or an external signal must be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data need
65. CMOS 8 BIT MICROCONTROLLER LC87BK00 SERIES 21727 USER S MANUAL Si REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or othe
66. D conversion terminates in the conversion time designated by the conversion time control register The conversion results are stored in the AD conversion result registers ADRHC ADRLC 3 10 3 3 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 8 channels 3 10 4 Related Registers 3 1041 AD control register ADCRC 1 Thisregister is an 8 bit register that controls the operation of the AD converter AD AD AD AD AD AD KESS 00000009 ADCRC CHSEL3 CHSEL2 CHSELI CHSELO ADERS START ENDF ADIE ADCHSEL3 bit 7 ADCHSELS BIEG AD conversion input signal select ADCHSEL1 bit 5 OREN ID pd SIM ADCHSELDO bit 4 These 4 bits are used to select the signal to be subject to AD conversion ADCHSEL3 ADCHSEL2 ADCHSEL1 ADCHSELO Signal Input Pin POI AN1 2 2 P03 AN3 P06 AN6 P70 AN8 0 0 0 0 GE m 0 9 scc ER wawa 1 0 P04 AN4 ef cbe HI ADCRS bit 3 Fixed bit This bit must always be set to 0 3 66 LC87BKO0 Chapter ADSTART bit 2 AD converter operation control This bit starts 1 or stops 0 AD conversion processing Setting this bit to 1 starts AD conversion The bit is automatically reset when the AD conversion ends The amount of time specified by the conversion time control register is required to complete the conversion
67. E bit 0 HALT mode setting flag Setting this bit places the CPU into HALT mode 2 This bit is automatically set when bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 15 Standby Note 1 The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer See Section 4 5 Watchdog Timer for details 4 16 LC87BK00 Chapter 4 Table 4 3 1 Standby Mode Operations Item Mode Reset State HALT Mode HOLD Mode X tal HOLD Mode Entry conditions RES applied PCON register PCON register PCON register Reset from LVD Bit 1 0 Bit 2 0 Bit 2 1 Reset from watchdog Bit 9 1 Bit 1 1 Bit 121 timer Initialized as shown in Data changed on entry separate table When watchdog timer reset WDTCNT register bit 7 is set Main clock oscillation Internal Subclock oscillation Multifrequency RC oscillation CPU I O pin state RES Undefined LVD Undefined or data retained depends on supply voltage reset Data retained Base timer lt Exit conditions Entry conditions cancelled Normal mode Note 2 Data changed on PCON register bit 0 0 exit Internal low speed RC oscillation Running medium speed RC x oscillation Stopped Stopped Stopped See Table 4 3 2 When watchdog timer Stopped Peripheral
68. FuruansassusuuuasansunuuusuusunuansunsAsussussausassusunuansussunsusussununsunsuss 3 6 3 2 4 Options 3 1 2 3 2 5 HALT and HOLD Mode Operation Fuuuusessauuunyuassusunuunsauceununsuaseunensuususensunsanus 3 1 2 3 3 Port 2 mrhmRRRuuuasrrseuuuuuuausssenuusssuassesssenusssmussecenunssasssussensussseseeensumssssecesess 3 1 3 3 3 1 Overview wuruusassusuuuamusbesumuunmsusuuusunsuusssessunsusassussmuuususunsuuesussussunsusassunsnsunsus 3 13 3 3 2 Functions 3 1 3 3 3 3 Related Registers Fuuasassusuuuamsassunumsansusunsunsasensussaseucsunsunsausessansussseunansunsus 3 14 3 3 4 Options 3 16 3 3 5 HALT and HOLD Mode Operation wuhuusssssuansassusuuunssessscussmsausussnsnuausensunususus 3 1 6 3 4 Port 7 DTD 3 1 7 3 4 1 Overview FuuusassssuuuansusunsussassaMsenumuausunsunsusasssunsuuususunensuumuessunsussssunsusuusus 3 17 3 4 2 Functions wurusssessusuyuszsusassumuyymR ArMnsaensuuaucunsnssuausunssesausuyusssuusussesunsnsausunsnsuuause 3 1 7 3 4
69. H state established on After reset release Oscillation enable entry into HOLD disable controlled by Input pin lt Oscillation not register OCR FEOEH started Feedback resistors Feedback resistor Feedback resistor for CF and XT are between CF1 and CF2 between CF1 and CF2 turned off controlled by a is in the state program established on entry into HOLD mode 00 07 Input mode Input output pull up Pull up resistor off resistor controlled by a program P10 P17 Input mode Input output pull up Pull up resistor off resistor controlled by a program P20 P21 Input mode Input output pull up Pull up resistor off resistor controlled by a program P70 nput mode Input output pull up Same as in Pull up resistor off resistor controlled by a Pull up resistor normal mode program off 4 18 LC87BKO0 Chapter 4 e Reset state entry conditions Low level applied to RES pin Reset signal generated by internal reset function POR LVD Reset signal generated by watchdog timer HOLD mode entry condition PCON register FEO7H bit 2 set to 0 and bit 1 to 1 HOLD mode Note 3 All oscillators stopped If SLWRC register bit 1 is set to 1 Since the SLWRC register bit 0 is set and the OCR register bits 4 5 are cleared the low speed RC oscillator is activated and designated as the system clock when HOLD mode is released If the SLWRC reg
70. Jee i cr pet Reset period Tai Reset period aa gt gt e ae m Reset undefined state LVUKS There also exists an undefined state LVUKS before the transistor starts functioning normally when both POR and LVD functions are used Resets are generated both when power is turned on and when the power level lowers The reset release voltage and entry voltage in this case may have some range Refer to the latest Semiconductor Data Sheet for details A hysteresis width LVHYS is provided to prevent repetitions of reset release and entry cycles near the detection level 4 32 LC87BKO00 Chapter 4 4 6 6 Notes on the Use of the Internal Reset Circuit 1 When generating resets only with the internal POR function When generating resets using only the internal POR function do not short the reset pin directly to VDD as when using it with the LVD function Be sure to use an external capacitor Cres of an appropriate capacitance and a pull up resistor Rggs or a pull up resistor Rggs alone Test the circuit extensively under the anticipated power supply conditions to verify that resets are reliably generated Microcontroller RRES Reset From POR CRES TU Figure 4 6 2 Reset Circuit Configuration Using Only the Internal POR Function 2 When selecting a release voltage level of 2 57V only with the internal POR function When selecting an internal POR rel
71. L 12 40 40 ET EE EE EE ERT E E 2 E E Fes j j j j T j j j j j j E CH MEM C C j 2 1 2 1 1 4 2 s 2 22 1 4022 12 22 2 FE98 NOM NEU PEE UEM EMEN FE9A e o oe e c onu 1 AI 5 Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO FE9C 1 42 742 ur m 12 Fee 411144112 cap ec s cut FEAT FEA2 oes e j j j j e ll EE a A a pM LC87BK00 APPENDIX I Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO FEBC 1 1 2 ur q 2 2 411144111 oer 41111412 B P EE DEE WEN j eer FEC1 FEC2 ees iR pe 7 mu pM AI 8 LC87BK00 APPENDIX II T7OUT PO7 T6OUT P06 FE40 bits 7 5 P07 POS lt lt AD input L 6 40 bit4 FE40 bits 3 0 P03 lt lt AD input L AN3 ANO PODDR FE41 Po7 None Timer7 toggle output Timer 6 toggle output o Clock Pull up resistor is Not attached if N ch
72. L output Set Invert T1PWMH output Match buffer register Reload Reload T1LCMP T1HCMP T1LR flag set T1HR Match buffer register flag set 16 bit programmable timer gt Figure 3 6 4 Mode Block Diagram T1LONG 1 T1PWM 1 3 38 LC87BKO00 Chapter 3 3 6 4 Related Registers 3 6 4 1 Timer 1 control register T1CNT 1 Thisregister is an 8 bit register that controls the operation and interrupts of TIL and T1H T1HRUN bit 7 count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of has the same value as TIHR When this bit is set to 1 timer 1 high byte T1H performs the required counting operation T1LRUN bit 6 T1L count control When this bit is set to 0 timer 1 low byte stops on a count value of 0 The match buffer register of TIL has the same value as TILR When this bit is set to 1 timer 1 low byte T1L performs the required counting operation T1LONG bit 5 Timer 1 bit length select When this bit is set to 0 timer 1 high and low order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit timer since the timer 1 high byte T1H counts up at the interval of the timer 1 low byte T1L Independent match signals are generated from T1H and TIL when their count value matches the contents of the corresponding match buffer register regardless of the
73. MRCR register bits 6 7 are cleared the multifrequency RC oscillator is stopped when HOLD mode is released Start stop of each of the selecting the subclock or low oscillators programmable medium speed RC oscillator as the system clock When HOLD mode is exited HALT mode Note 1 the oscillators return to the state oscillators retain the state established when the mode is established when HALT mode entered is entered Note 1 The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer See Section 4 5 Watchdog Timer for details Note 2 After HOLD mode is released the medium or low speed RC oscillator is automatically enabled and designated as the system clock according to the value of bit 1 of the low speed RC oscillator control register SLWRC that is established when HOLD mode is entered 6 Itis necessary to manipulate the following special function registers to control the system clock PCON OCR CLKDIV MRCR XT2PC SLWRC Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH H000 R W PCON XTIDLE PDN IDLE rem ww mcs EE es rw wem ER RCM rere wv
74. OLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detected Low level detected 0 i ora s 1 0 JRisngedgedetected INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated Note INTO HOLD mode release function is available only when level detection is set 3 2 8 5 External interrupt 2 3 control register I23CR 1 Thisregister is an 8 bit register that controls external interrupts 2 and 3 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W D3CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE Port 1 bit 7 INT3 rising edge detection control bit 6 INT3 falling edge detection control INT3HEG INT3LEG Interrupt Conditions P15 Pin Data No edge detected bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are
75. PWML and TIPWMH run on the cycle clock TIPWML period 256 x TILPRC count x Tcyc TIPWML low period TILR 1 x TILPRC count x Tcyc TIPWMH period 256 x TIHPRC count x Tcyc low period TIHR 1 x TIHPRC count x Tcyc 3 Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output The low order 8 bits may be used as a timer counter with toggle output Functions as a 16 bit programmable timer counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events Since interrupts can occur from the low order 8 bit timer at the interval of TIL period low order 8 bits of this 16 bit programmable timer counter can be used as the reference timer TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and periods respectively Note 1 3 32 LC87BKO00 Chapter 3 TIL period z TILR 1 x TILPRC count x 2 Tcyc or TILR TILPRC count events detected TIPWML period period x 2 period TIHR 1 x TIHPRC count x T1L period TIPWMH period period x 2 4 Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits may be used as a PWM 16 bit programmable timer runs on the cycle clock low order 8 bits run as PWM TIPWML having a period of 256 TIPWMH generates a signal that toggles at the interval of T1 period No
76. Protective resistor device DBGPx2 Reference example 3 Prevents the floating status Hi Z during system reset 100 pull up resistor DBGPx2 Lowers impedance to prevent the superimposition of noise during system reset Reference example 4 Analog voltage DBGPx2 Microcontroller interior Nch Tr OFF during System reset amp Example of selecting the Nch OD option Digital input on chip debugger input Microcontroller interior Pch Nch Tr OFF during system reset Digital input on chip debugger input Microcontroller interior Nch Tr OFF during system reset Ix Example of selecting the Nch OD option Digital input on chip debugger input Analog input 2 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear no responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC87BK00 SERIES USER S MANUAL Rev 1 00 October 21 2011 ON Semiconductor Digital Solution Division Microcontroller amp Flas
77. R 45 bits 5 0 D Q W P1DDR C R P1DDR Port 1 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 3 Port Block Diagrams Low PU P2 FE48 bits 1 0 W P2 P21 P20 Special input R P2 INT4 P21 P20 P2DDR FE49 bits 1 0 W P2DDR R P2DDR Special Function Input Function Output NT4 timer OL capture timer capture input NT4 timer OL capture timer OH capture input Table of Port 2 Multiplexed Functions Port 2 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units Int request to vector 00013 I45SL 4 Timer 1 count clock Timer OL capture signal Tmo Timer OH capture signal Port 2 Interrupt Block Diagram AII 4 LC87BK00 APPENDIX II a Low PU 2 m HALT HOLD ke P7 FE5C bit 0 D Q lt 70 C W P7 S 1 E AD input 8 L R P7 INTO P7 FE5C bit 4 D Q C Special Function Input Function Output INTO timer OL capture AD analog 8 input Table of Port 7 Multiplexed Functions Port 7 Block Diagram Option None AII 5 Port Block Diagrams ISL FE5F RJ E Noise fitter filter is Timer capture signal L Int request to Timer 0 clock input vector 00013 I23CR FEBE Int request to vector 0001B _ L INT2 Dy N lQO O yn1 i i _ v Timer 0L capture signal INT1
78. R W R W R W RAN RAN R W R W FED 0000 0000 RA TU Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO FEIE ee EE EE DEE ccc cut FE23 FE24 es iR EE e E m pM FE33 sU Lies sq sss so FE37 FE38 Kl ECC j rem 12 141 AI 2 LC87BK00 APPENDIX I Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO FESE ES AE LE Y LES IE 0000 000 RW f EE P e ms WM mv wi Po _ Fea 0000 0000 WW Pook O POPUS Por wat 0000 WK M TE FE43 og 0000 R W x XT2PCB7 XT2PCB6 NEN NEN XTCF IN XT2PCB2 XT2PCB1 XT2PCBO O FE Tuo ru oram ww rr Era Pra Fur FUR ra 0000 ww rno oswor FINO re mno wr m EE
79. R release level that is lower than the minimum guaranteed operating voltage 2 57V 4 30 LC87BKO00 Chapter 4 e Selection example 1 Selecting the optimum reset level to keep the microcontroller running without resetting it until VDD falls below 3 0V according to the set s requirements Set the LVD reset function option to Enable and select 2 81V as the LVD reset level Set operating range VDD 3 0V LVD release voltage LVDET LVHYS LVD reset voltage LVDET Typ 2 81 e Selection example 2 Selecting the optimum reset level that meets the guaranteed operating conditions of VDD 2 7V 250 ns Set the LVD reset function option to Enable and select 2 81V as the LVD reset level Microcontroller operation guaranteed range VDD 2 7V to 5 5V Tcyc 250ns LVD release voltage LVDET LVHYS Pie ete LVD reset voltage lt 2 81V Operation guaranteed voltage lower limit VDD 2 7V Tcyc 250ns e Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3 0V see also paragraph 1 of Subsection 4 6 7 Set the LVD reset function option to Disable and select 2 57V as the POR release level Set operating range l a o sas External 3 0V detection circuit POR release voltage PORRL Typ 2 57V Note 5 The operation guaranteed values voltage
80. ROM that is actually incorporated varies with the type of microcontroller The ROM table look up instruction LDCW can be used to refer all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 01F00H to OIFFFH for this series are reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM This series of microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated varies with the type of the microcontroller Nine bits are used to access addresses 0000H to FDFFH of the 128 ROM space and 8 or 9 bits are used to access addresses to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table look up instruction LDCW however their bit length is set to 17 bits 9 high order bits 8 low order bits As shown in Figure 2 4 1 the available instructions vary depending on the RAM address The high efficiency of the ROM used and a higher execution speed can be attempted using these instructions properly 87 00 Chapter 2 FFFFH Space reserved for system FF00H m FEFFH FEOOH FDFFH 2000H Stack space 1FFFH 9 bit 0200H 01FFH 0100H
81. SIIM1 1 SIIDIR SHIE 1 SILREC 0 3 Setting up the ports Configure the clock port P15 and data port P14 as N channel open drain output ports by setting the option Set P14 P1 bit 4 and P15 P1 bit 5 to 0 Set PIAFCR PIFCR bit 4 and PISFCR PIFCR bit 5 to 1 Set PIADDR PIDDR bit 4 and PISDDR PIDDR bit 5 to 1 4 Starting communication sending an address Load SBUFI with address data Set SIIRUN transfer a start bit SBUFI 8 bits stop bit H 3 59 SIO1 5 Checking address data after an interrupt Read SBUFI SBUFI has been loaded with serial data from data I O port even in transmission mode When SBUFI is read in the data on the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 9 1 no interrupt will be generated as SIITRUN is cleared in that case If there is a possibility of a condition for losing the bus contention for example when another device in master mode is in the system perform timeout processing using the timer module etc to detect the condition 6 Transmitting data Load SBUFI with output data Clear 8 and exit interrupt processing transfer SBUFI 8 bits stop bit H 7 Checking transmission data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in tran
82. SP6 SP5 SP4 SP3 SP2 SPI 5 0 The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP SP SP 1 ROM BANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off which use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes These addressing modes use 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM on a 1 9 bits basis if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 RAM Reserved for system Address TEED Lesen el 7EH R63 lower R63 7EH __R1 Uppen 02H R1 lower R1 2 R upper 00H RO lower RO 0 Figure 2 10 1 Allocation of Indirect Registers 2 11 Addressing Modes LC870000 series microcontrollers support the following seven addressing modes 1 2 3 4
83. Serial UART Block Diagram SI1M1 0 511 0 1 3 57 SIO1 3 9 4 SIO1 Communication Examples 3 9 4 4 Synchronous serial communication mode 0 1 Setting the clock Setup SBRI when using an internal clock 2 Setting the mode Set as follows 51 00 SI1M1 0 SIIDIR SIIIE 1 3 Setting up the ports and 5 bit 4 Clock Port P15 Internal clock Output Extemal clock Data Output Port Data UO Port P13 P14 Data transmission only Output Data reception only a 1 Data transmission reception 3 wire Output N channel open Data transmission reception 2 wire 1 1 drain dus i NR 4 Setting up output data Write output data into SBUFI in the data transmission mode SIIREC 0 5 Starting operation Set SITRUN 6 Reading data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode e Clear SIIEND and exit interrupt processing Return to step 4 to repeat operation 3 9 4 2 Asynchronous serial communication mode 1 1 Setting the baudrate Setup SBRI 2 Setting the mode Set as follows SIIMO 1 8 0 SIIDIR SIIIE 1 3 Setting up the ports Data Output Port Data Port P13 P14 Data transmission reception 2 wire Data transmission reception N channel open drain output 1 wire Output Input 3 58 LC87BKO0 Chapter 4 Starting transmit operatio
84. Since the WDTCT can be cleared by a program it is necessary to code the program so that the WDTCT can be cleared at regular intervals f the WDT operation is started with the internal low speed RC oscillator clock selected as the WDT clock source the internal low speed RC oscillator circuit is controlled by both the low speed RC oscillation control register SLWRC and the Since they control the oscillation independently of each other even if the system clock happens to be suspended by a program runaway condition the WDT continues operation making it possible to detect the runaway condition the operation is started when the subclock is selected as the clock a WDT reset 15 generated on detection of a subclock oscillation suspended by the and XT2 function control bit EXTOSC of the oscillation control register OCR or on entry into HOLD mode In this case WDTRSTF is set 2 Standby mode time operations The action that the WDT takes in standby mode can be selected from three operating modes continue count operation stop operation and stop count operation while retaining the count value If the internal low speed RC oscillator clock is selected as the WDT clock source when continue count operation is selected an operating current of several dozen pA is always flowing in the IC even when it is in standby mode because the internal low speed RC oscillator circuit is continuing oscillation For
85. Synchronous 8 bit serial I O 2 or 3 wire system 2 to 512 Tcyc transfer clock Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048Tcyc baudrate Mode 2 Bus mode 1 start bit 8 data bits 2 to 512 Tcyc transfer clock Mode 3 Bus mode 2 start detection 8 data bits stop detection AD converter 12 bits x 8 channels 12 8 bit AD converter resolution selectable Remote control receiver circuit multiplexed with P15 SCK1 INT3 TOIN pin e Noise rejection function noise filter time constant selectable from Tcyc 32Tcyc 128Tcyc Clock output function 10101010101 1 1 Capable of generating a clock with a frequency of 2 4 3 16 32 the source oscillator clock selected as the system clock 2 Capable of generating a source oscillator clock for the subclock Watchdog timer Capable of generating an internal reset on an overflow of a timer that runs on either the low speed RC oscillator clock or subclock Operation when the CPU enters standby mode can be selected from three modes continue count operation stop operation and stop count operation while retaining the count value 1 2 LC87BKO00 Chapter 1 Interrupts 15 sources 9 vector addresses 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt request of the level equal to or lower than the current interrupt 15 not accepted 2 When interrupt request
86. The conversion time is defined using three bits i e the ADTM2 0 of the AD conversion result register low byte ADRLC and the ADTMI bit 1 and bit 0 of the AD mode register ADMRC Setting this bit to 0 stops the AD conversion No correct conversion results can be obtained if this bit is cleared when AD conversion is in progress Never clear this bit while AD conversion is in progress bit 1 AD conversion end flag This bit identifies the end of AD conversion It is set 1 when AD conversion is completed Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF is set to 0 it indicates that no AD conversion is in progress This flag must be cleared with an instruction ADIE bit 0 AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes Setting ADCHSEL3 to ADCHSELO to 0111 and between 1001 and 1111 is prohibited Do not place the microcontroller in HOLD mode with ADSTART set to 1 Make sure that ADSTART is set to 0 before putting the microcontroller in HOLD mode Since the digital input buffer for the analog input channel AN8 of P70 is always open a through current will flow through the analog channel when the analog voltage is fed If through current is a problem for operations other than AD conversion keep the pins at either VDD or VSS level via an ex
87. These bits and ADTM2 bit 0 of the AD conversion result register low byte ADRLC define the conversion time AD conversion time control ADRLC ADMA Magister AD Frequency Division Ratio 1 28 3 68 LC87BKO00 Chapter 3 Conversion time calculation formulas 2 bit AD conversion mode Conversion time 52 AD division ratio 2 x 1 3 x Tcyc 8 bit AD conversion mode Conversion time 32 AD division ratio 2 x 1 3 x Tcyc Notes The conversion time is doubled in the following cases lt gt AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset 2 The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the above formula is required in the second and subsequent conversions or in AD conversions that are carried out in the 8 bit AD conversion mode 3 10 4 3 conversion result register low byte ADRLC 1 This register is used to hold the low order 4 bits of the results of an AD conversion carried out in the 12 bit AD conversion mode and to control the conversion time 2 Sincethe data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed 0000 0000 R W ADRLC DATAL3 DATAL2 DATALI DATALO ADRL3 ADRL2
88. To realize ultra low power operation using HOLD mode it is necessary to disable the watchdog timer from running in HOLD mode by setting IDLOP1 and IDLOPO to or 2 When setting IDLOP1 and IDLOPO to 0 or 3 several dozen of operating current flows at all times because the low speed RC oscillator circuit continues oscillating even in HOLD mode If standby mode is entered when the watchdog timer is running with IDLOP1 IDLOPO set to 2 the internal low speed RC oscillator circuit stops oscillation and the watchdog timer stops count operation and retains the count value When the CPU subsequently exits standby mode the low speed RC oscillator circuit resumes oscillation and the watchdog timer restarts count operation If the period from the release of standby mode to the next entry into standby mode is less than low speed RC oscillator clock x 4 however the low speed RC oscillator circuit may not stop oscillation when the CPU enters standby mode In such a case standby mode 15 on several dozen pA of operating current flows because the low speed RC oscillator circuit is active though the watchdog timer is inactive To minimize the standby power requirement of the set code the program so that an interval of low speed RC oscillator clock x 4 or longer is provided from the release of standby mode to the next entry into standby mode The low speed RC oscillation frequency varies from IC to IC Refer to the latest Semiconductor Data Sheet
89. When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated Note INTO HOLD mode release is enabled only when level detection is set 3 4 3 3 External interrupt 2 3 control register I23CR 1 Thisregister is an 8 bit register that controls external interrupts 2 and 3 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W D3CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE Port 7 bit 7 INT3 rising edge detection control bit 6 INT3 falling edge detection control INT3HEG INT3LEG Interrupt Conditions P15 Pin Data No edge detected bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit must be cleared with an instruction as it is not cleared automatically bit 4 INT3 interrupt request enable When this bi
90. al Er 2 1 0 1 1 3 26 LC87BKO00 Chapter Clock Clear g Match Capture trigger Registers 101CR FE5Dh I23CR FESEh ISL FE5Fh 145CR FE4Ah and 145SL FE4Bh need setting TOCAL 4 e O 2 Re Capture Capture Clear Match Match Match buffer register TOLCMP Match buffer register En Reload flag set TOLR 8 bit programmable timer gt 8 bit programmable timer gt with programmable prescaler with programmable prescaler Figure 3 5 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 Clock Clear Registers I01 CR FE5Dh 23 ISL FESFh Compara FS l45CR FE4Ah and I45SL FEABh need setting TOPRR TOCAL TOCAH External Clock Capture Capture ojear input gt TOL TOH Set in register ISL FESFh Matc Match Match buffer register TOLCMP Match buffer register TOHCMP flag set flag set Can programmable counter PON programmable umer gt with programmable prescaler Figure 3 5 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 3 27 Clock Clear roe D Match Capture trigger TOCAH TOCAL Registers 01 I23CR FEBEh ISL FE5Fh l45CR FE4Ah and I45SL FE4Bh need setting Capture Match TOLCMP Match buffer register TOHCMP flag set TOHR TOLR 16 bit programmable timer with programmable Figure 3 5 3 Mode 2 Bloc
91. alue of the port data latch 1 Carries the OR of the waveform that toggles at the interval determined by timer 6 and the value of the port data latch Port 0 CLKOEN bit 3 This bit controls the output data at pin PO5 This bit is disabled when 05 is in input mode When 05 is in output mode 0 1 Carries the value of the port data latch Carries the OR of the system clock output and the value of the port data latch CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 These bits define the frequency of the system clock to be placed at P05 000 001 010 011 100 101 110 111 Frequency of source oscillator selected as system clock 1 2 of frequency of source oscillator selected as system clock 1 4 of frequency of source oscillator selected as system clock 1 8 of frequency of source oscillator selected as system clock 1 16 of frequency of source oscillator selected as system clock 1 32 of frequency of source oscillator selected as system clock 1 64 of frequency of source oscillator selected as system clock Frequency of source oscillator selected as subclock Notes on the use of the clock output function Follow notes 1 to 3 given below when using the clock output function Anomalies may be observed in the waveform of the port clock output if these notes are violated 1 2 3 Do not change the frequency division setting of the clock output when CLKOEN bit 3 is set to 1 gt Do not change
92. annel OD option is m 03 Poo AD analog input None Table of Port 0 Multiplexed Functions selected Programmable if CMOS option is selected Port 0 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 1 Port Block Diagrams PODDR FE41 Int request to vector 0004B 40 bit 7 P07 pin input data interrupt detect PO FE40 bit 6 06 pin input data PO FE40 bit 5 P05 pin Y data PO FE40 bit 4 PO interrupt detect PODDR L2 bit 1 P04 pin input data PO FE40 bit pin input data PO FEAO bit 2 P02 pin input data 40 bit 1 P01 pin input data ED PO FE40 bit 0 POO pin input data PODDR FE41 bit 0 Port 0 Interrupt Block Diagram AII 2 LC87BK00 APPENDIX II Function outputs 7 6 P1FCR FE46 bits 7 6 o C Low PU a P1 FE44 9 bits 7 6 D CMOS Pin W P1 Q Es or Nch OD XOR P17 P16 lt INT2 INT1 P1DDR FE45 bits 7 6 D Q C R P1 Special Function Input Function Output OH capture input Timer 1HPWM output INT2 timer 0 pulse input Timer 1LPWM output FUNCTION outputs 5 3 Table of Port 1 Multiplexed Functions P1FCR 46 bits 5 0 W P1FCR C Low PU al lt a R P1FCR d P1 44 bits 5 0 CMOS LD TE W P1 Q Nch OD E OR P15 P10 4 Special input L R P1 INTS P15 P1DD
93. ap pas mss p IP23 IPIB 4 1 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 This register enables and disables H and L level interrupts 2 The state of the interrupt level flag can be read 3 The register selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 This register selects the level H or L of interrupts to vector addresses 00013H to 0004BH 4 2 LC87BKO0 Chapter 4 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 1 This register is a 6 bit register for controlling the interrupts Bits 6 to 4 are read only Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0000 00 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO IE7 bit 7 H L level interrupt enable disable control A in this bit enables H and L level interrupt requests to be accepted this bit disables H and L level interrupt requests to be accepted X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H leve
94. apacitors rough standard values R less than 5k Q C 1000 pF to 0 luF Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur Shield both ends of analog signal lines with noise free ground Make sure that no digital pulses are applied to or generated from the pins adjacent to the analog input pin that is being subject to conversion 3 71 ADC12 10 Correct conversion results may not be obtained because of noise interference if the state of port outputs is changing To minimize the adverse influences of noise interference it is necessary to keep line resistance across the power supply and the VDD pins of the microcontroller at a minimum This should be kept in mind when designing an application circuit Adjust the amplitudes of the voltage at the oscillator pin and the I O voltages at the other pins so that they fall within the voltage range between VDD and VSS To obtain valid conversion data perform conversion operations several times discard the maximum and minimum values of the conversion results and use an average of the remaining data 3 72 LC87BKO0 Chapter 4 4 Control Functions 4 1 Interrupt Function 4 1 1 Overview This series of microcontrollers has the capabilities to control three levels of multiple interrupts i e low level L high level H and highest level X Th
95. as input and the corresponding PO FE40 bit is set A HOLD mode release signal and an interrupt request to vector address 004BH are generated when this bit and the interrupt request enable bit POIE are set to 1 This bit must be cleared with an instruction as it is not cleared automatically POIE bit 4 PO interrupt request enable Setting this bit and POFLG to 1 generates HOLD mode release signal and an interrupt request to vector address 004 POHPU bit 3 P07 to P04 pull up resistor control When this bit is set to 1 and POHDDR to 0 pull up resistors are connected to port bits 7 to P04 that are selected as CMOS output by option 3 2 LC87BKO0 Chapter POLPU bit 2 PO3 to POO pull up resistor control When this bit is set to 1 and POLDDR to 0 pull up resistors are connected to port bits to POO that are selected as CMOS output by option POHDDR bit 1 P07 to P04 I O control When this bit is set to 1 PO7 to P04 are placed in output mode and the contents of the corresponding port 0 data latch PO are output from the port When this bit is set to 0 PO7 to P04 are placed in input mode POFLG is set when a low level is detected at port whose corresponding port 0 data latch PO bit is set to 1 POLDDR bit 0 to POO control When this bit is set to 1 PO3 to POO are placed in output mode and the contents of the corresponding port 0 data latch PO are output from the port When this bit
96. ase the WDTCT is cleared and count instruction MOV operation is restarted at a count value of 0 the WDTCT is not cleared when it is loaded with 55H by any other instruction Note The internal low speed RC oscillator circuit is started by setting WDTCKSL to 0 and WDTRUN to 1 Once the oscillator starts oscillation operating current of several dozen uA flows For details refer to the latest Semiconductor Data Sheet Note that the oscillation is also started by setting SLRCSTAT SLWRC bit 0 to 1 4 26 LC87BKO0 Chapter 4 4 5 5 Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed 1 Starting the watchdog timer 1 Set the time for a WDT reset to occur to WDTCKSL WDTCNT bit 6 and WDTSL2 to WDTSLO WDTCNT bits 2 to 0 2 Set the standby mode operation HALT HOLD X tal HOLD to IDLOP1 to IDLOPO WDTCNT bits 4 to 3 3 After 1 and 2 set WDTRUN WDTCNT bit 5 to 1 The watchdog timer starts functioning when WDTRUN is set to 1 Once the watchdog timer starts operation WDTCNT is disabled for writes it is only possible to clear WDTCT and read WDTCNT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped only when a low level signal is applied to the external RES pin a reset by the internal reset POR LVD function occurs or standby mode is entered when IDLOPI to IDLOPO a
97. atch buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 0 high and low order bytes serve as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer registers of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL becomes the match signal for the prescaler When this bit is set to 1 the count clock for TOL becomes an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH and a match signal is generated while is running TOHRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated 3 29 la TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL and a match signal is gener
98. ated while TOL is running TOLRUN I Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated Notes TOHCMP and TOLCMP must be cleared to 0 with an instruction When the 16 bit mode is to be used TOLRUN and must set to the same value at the same time to control operation TOLCMP and TOHCMP are set at the same time in the 16 bit mode 3 5 4 2 Timer 0 programmable prescaler match register TOPRR 1 Thisregister is an 8 bit register used to define the clock period Tpr of timer counter 0 2 Thecount value of the prescaler starts at 0 when TOPRR is loaded with data 3 1 Tcyc Tcyc Period of cycle clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE11 0000 0000 R W TOPRR TOPRR7 TOPRR6 TOPRRS TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO 3 5 4 3 Timer counter 0 low byte TOL 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler or external signals Address Initial Value R W Name BIT7 6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 1015 TOL4 TOL3 TOL2
99. bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the respective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC Value BNK Value Reset Note 00000 0 um o _ mm j mm m gt Kas sesi Kap DESS EE EE Conditional branch BE BNE DBNZ DBZ BZ BNZ instructions BZW BNZW BP BN BPC nb Number of instruction bytes RCALLA PC PC 1 Areg 0 to 255 Unchanged Return instructions RET RETI PC16 to 08 SP BNK is set to 7 to 00 SP 1 bit 8 of SP denotes the contents of RAM SP 1 address designated by the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes Note The reset time program start address can be selected through a user option in the flash version product In the mask version the program start address is fixed at address 00000H 2 3 Program Memory ROM This series of microcontrollers has a program memory space of 256K bytes but the size of the
100. ck source when the CPU exits HOLD mode CFSTOP bit 0 Main clock oscillator circuit control Setting this bit to 1 stops the oscillation of the main clock oscillator circuit 2 Setting this bit to O starts the oscillation of the main clock oscillator circuit 3 When a reset occurs this bit and bit 3 of the XT2PC register are cleared and the CFI XT1 and CF2 XT2 pins are configured as input pins OCR Register XT2PC Register CF1 XT1 OCR Register FEOEH EXTOSC CFSTOP XTCFSEL CF2 XT2 State XT2IN Main clock CF2 XT2 1 1 oscillator started pin data pin data M Undefined Undefined oscillator stopped 1 1 X Subclock oscillator 0 is read started pin data General purpose CF2 XT2 CF1 XT1 input pin data pin data General purpose CF2 XT2 CF1 XT1 input output pin data pin data 4 2 43 Low speed RC oscillation control register SLWRC 3 bit register 1 This register is a 3 bit register that controls the operation of the low medium speed RC oscillator circuits and selects the amplifier size of the CF oscillator circuit Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO HHHH H000 R W SLWRC CFLAMP SLRCSEL SLRCSTAT 4 10 LC87BKO0 Chapter A Bits 7 to 3 These bits do not exist They are always read as 1 CFLAMP bit 2 CF oscillation amplifier size select control lt 1 gt A 1 in this bit selects the low amplifier size fo
101. d TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from the P17 INTI TOHCP P15 INT3 TOIN P20 and P21 timer OH capture input pins TO period TOHR TOLR 1 x 1 x Tcyc 16 bits 4 Mode 3 16 bit programmable counter with a 16 bit capture register Timer counter 0 serves as a 16 bit programmable counter that counts the number of external input detection signals from the P16 INT2 TOIN and P15 INT3 TOIN pins The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from the P17 INTI TOHCP P15 INT3 TOIN P20 and P21 timer capture input pins period TOHR 1 16 bits 5 Interrupt generation TOL or TOH interrupt request is generated at the counter period of TOL or TOH if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control timer counter 0 TO TOCNT TOPRR TOL TOH TOLR TOHR TOCAL TOCAH P7 ISL 0 D3CR P2 P2DDR 145 I45SL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE 00000000 TOL ro TOL2 rori XXXXXXXX TOCAL TOCAL7 TOCAL6 TOCALS TO
102. details refer to the latest Semiconductor Data Sheet 3 It is necessary to manipulate the following special function register to control the watchdog timer WDT WDTCNT Address Initial Value RAV BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE79 00000000 R W WDTCNT WDTRSTF WDTCKSL WDTRUN IDLOPI IDLOPO WDTSL2 WDTSLI WDTSLO 4 22 LC87BKO0 Chapter 4 4 5 3 Circuit Configuration 4 5 3 1 WDT control register WDTCNT 8 bit register 1 This register is used to manipulate the WDT reset detection flag to select operation in standby mode to select the overflow time and to control the operation of the WDT Note Note Note The WDTCNT is initialized to 00H when a low level signal is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bit 6 and bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs The WDTCNT is disabled for writes once WDT operation is started WDTRUN set to 1 If the instruction MOV Z55H WDTCNT is executed in this case the WDTCT is cleared and count operation is restarted at a count value of 0 the WDTCT is not cleared when it is loaded with 55H by any other instruction The internal low speed RC oscillator circuit is started by setting WDTCKSL WDTCNT bit 6 to 0 WDTRUN WDTCNT bit 5 to 1 Once the oscillator starts oscillation operating current of several dozen flows For
103. details refer to the latest Semiconductor Data Sheet Note that the oscillation is also started by setting SLRCSTAT SLWRC bit 0 to 1 4 5 3 2 WDT counter WDTCT 17 bit counter 1 Operation start stop Start stop is controlled by the 1 0 value of WDTRUN The CPU enters standby mode when is set to 1 and IDLOPI and IDLOPO WDTCNT bits 4 and 3 are set to 2 2 Count clock The WDT clock selected from the internal low speed RC oscillator clock or subclock 3 Overflow Generated when the WDTCT count value matches the count value selected by WDTSL2 to WDTSLO WDTCNT bits 2 to 0 Generates the WDT reset signal the WDTRUN clear signal and the WDTRSTF WDTCNT bit 7 set signal 4 Reset Setting WDTRUN to 0 or setting WDTRUN to 1 and executing the 55 WDTCNT instruction See Figure 4 5 2 for details on WDT operation 4 23 WDT SLRCSTAT SLWRC bitO PDN PCON bit1 XTIDLE PCON bit2 Low speed RC oscillation control circuit Enable WDTRUN oscillation WDTCKSL WDT Oscillation stopped low speed RC oscillation control circuit Low speed RC oscillator clock XTCLK Clock stopped WDTCKSL Figure 4 5 1 To system clock Oscillation control Internal low speed RC PUS as WDTCNT MOV 55H WDTCNT oscillator circuit write instruction detector circuit WDT counter Reset WDTCT O WDTRUN WDT reset 4 WDTRUN clear signal generato
104. dition is detected lt 4 gt This bit must be cleared with an instruction SI1END bit 1 Serial transfer end flag This bit is set when serial transfer terminates see Table 3 9 1 lt 2 gt This bit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control lt l gt When this bit and SITEND are set to 1 an interrupt request to vector address 003BH is generated 3 9 5 2 Serial buffer 1 SBUF1 1 Serial buffer 1 is a 9 bit register used to store data to be handled during SIO1 serial transfer 2 The low order 8 bits of SBUFI are transferred to the data shift register for data transmission reception at the beginning of transfer processing and the contents of the shift register are placed in the low order 8 bits of SBUFI when 8 bit data is transferred 3 In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data data on the position of the stop bit that is received Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE35 00000 0000 SBUFI SBUFIS8 SBUFI7 SBUFI6 SBUF15 SBUF14 SBUFI3 SBUFI2 SBUF11 SBUFIO 3 9 5 3 Baudrate generator register SBR1 1 Thisregister is an 8 bit register that defines the baudrate of SIOI serial transfer modes 0 1 and 2 2 Loading this register with data causes the baudrate generating counter to be initialized immediately 3 The baudrate varies from mode to mode Modes 0 2 TSBRI S
105. e 1 2 3 4 5 Note Note System clock state Set the system clock to a state other than the CF oscillation main Switch the CF oscillator amplifier size to low amp Set CFLAMP bit 2 of the low speed RC oscillation control register to 1 Wait for the CF oscillator stabilization time Wait for the CF oscillator stabilization time specified in the latest Semiconductor Data Sheet Check the CF oscillator this step is highly recommended especially when using a low voltage configuration Using the CF oscillation monitoring function make sure that the system clock is oscillating Switch the system clock source Set CLKCBA bit 4 of the oscillation control register to 1 CLKCBS bit 5 to 0 to switch the system clock source to CF oscillator main Do not switch the amplifier size of the CF oscillator when the system clock is set to the CF oscillator main Switching the amplifier size in this case may cause unstable oscillation resulting in a system malfunction The operating voltage range differs for the CF oscillator low and normal amplifiers Refer to the latest Semiconductor Data Sheet before using the CF oscillator low amplifier 4 13 Standby 4 3 Standby Function 4 3 1 Overview This series of microcontrollers supports three standby modes 1 HALT HOLD and X tal HOLD modes which are used to reduce current consumption at power failure time or in program standby mode I
106. e When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 3 6 Input signal select register ISL 1 This register is an 8 bit register that controls the timer 0 input noise filter time constant buzzer output timer PWMH output select and base timer clock select Address Initial Value R W Name BIT7 6 5 4 2 BIT1 FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON LC87BKO0 Chapter STOHCP bit 7 Timer OH capture signal input port select This bit selects the timer OH capture signal input port When this bit is set to 1 a timer capture signal is generated when an input that satisfies the INTI interrupt detection conditions is supplied to P17 If the INTI interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at 17 When this bit is set to 0 a timer capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When this bit is set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to
107. e PCON register 15 cleared and the CPU switches to HALT mode Note 1 The low speed RC oscillation is also controlled directly by the watchdog timer Its oscillation in the standby mode is also controlled by the watchdog timer See Section 4 5 Watchdog Timer for details Note 2 Do not allow the CPU to enter HOLD or X tal HOLD mode while AD conversion is in progress Make sure that ADSTART ADCRC register bit 2 is set to O before placing the CPU into one of the standby modes 4 14 LC87BKO0 Chapter 4 4 3 3 Related Register 4 3 3 1 Power control register PCON 3 bit register 1 Thisregister is a 3 bit register that specifies the operating mode normal HALT HOLD X tal HOLD Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE07 HHHH H000 R W XTIDLE PDN IDLE Bits 7 to 3 These bits do not exist They are always read as 1 XTIDLE bit 2 X tal HOLD mode setting flag PDN bit 1 HOLD mode setting flag XTIDLE PDN Operating mode Normal or HALT mode X tal HOLD mode 0 1 HOLD mode These bits must be set with an instruction When the CPU enters HOLD mode all oscillators main clock subclock low medium speed RC multifrequency RC are suspended and the related registers are placed in the states described below If bit 1 of the SLWRC register is set to 1 bit 0 of the SLWRC register is set and bits 4 and 5 of the OCR regis
108. e established Stopped Stopped Stopped Stopped at entry time Immediately after State established State established State established State established State established State established at exit from X tal at entry time at entry time at entry time at entry time at entry time entry time HOLD mode See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes 4 5 System Clock e HOLD mode Note 1 All oscillators stopped the SLWRC register bit 1 is set to 1 Since the SLWRC register bit 0 is set and the OCR register bits 4 5 are cleared the low speed RC oscillator is activated and designated as the system clock when HOLD mode is released the SLWRC register bit 1 is set to 0 Since the OCR register bits 1 4 5 are cleared the medium speed RC e Reset clock stopped Subclock stopped Low speed RC oscillator stopped Medium speed RC oscillator started Multifrequency RC oscillator stopped e Normal operating mode Note 1 e X tal HOLD mode Note 1 The main clock low medium speed RC oscillators and multifrequency RC oscillator are stopped The subclock retains the state established when X tal HOLD mode is entered The contents of OCR SLWRC and MRCR registers remain unchanged CPU enters this mode after oscillator is activated and designated as the system clock when HOLD mode is released Since the
109. e master interrupt enable register IE and interrupt priority control register IP are used to enable or disable interrupts and determine the priority of interrupts 4 1 2 Functions 1 2 3 4 5 Interrupt processing Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 When the CPU receives an interrupt request from a peripheral module it determines the level priority and interrupt enable status If the interrupt request is legitimate for processing the CPU saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the old state of PC and the interrupt level Multilevel interrupt control interrupt function supports three levels of interrupts 1 the low level L high level H and highest level X The interrupt function will not accept any interrupt requests of the same level or lower level than the one that is currently being processed Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests When interrupt requests of the same level occur at the same time the one whose vector address is the lowest has priority Interrupt reque
110. e of reaches 0 3 6 3 8 Timer 1 match data register high byte T1HR 8 bit register with a match buffer register 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte T1H 2 The match buffer register is updated as follows When it is inactive TIHRUN O the match buffer register matches When it is active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 3 6 3 9 Timer 1 low byte output TTPWML 1 TIPWML output is fixed high when TIL is inactive If TIL is active the TIPWML output is fixed low when TILR FFH 2 When TIPWM timer 1 control register bit 4 is set to O timer 1 low byte output is a toggle output whose state changes on match signal 3 When TIPWM timer 1 control register bit 4 is set to 1 timer 1 low byte output is a PWM output that is cleared on a TIL overflow and set on a T1L match signal 3 6 3 10 Timer 1 high byte output TTPWMH 1 The TIPWMH output is fixed high when is inactive If T1H is active the TIPWMH output is fixed low when 2 When TIPWM 0 or TILONG 1 the timer 1 high byte output is a toggle output whose state changes match signal 3 When TIPWM 1 and TILONG 0 timer 1 high byte output is a PWM o
111. e set to 0 the timer 6 counter stops at a count value of 0 In other cases the timer 6 counter continues operation 3 When data is written into T6R while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 44 LC87BKO00 Chapter 3 3 7 3 3 Timer 6 prescaler 6 bit counter 1 This prescaler is used to define the clock period for timer 6 with the value of T6CO and T67CNT FE78 bits 4 and 5 Table 3 7 1 Timer 6 Count Clocks T6C1 T6CO T6 Count Clock 0 Timer 6 prescaler and timer counter are in the reset state 1 4 31 o 64 Toye 3 7 3 4 Timer 6 period setting register 8 bit register 1 Thisregister defines the period of timer 6 2 When data is written into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 7 3 5 Timer 7 counter T7CTR 8 bit counter 1 This counter counts the number of clocks from the timer 7 prescaler T7PR The value of the timer 7 counter T7CTR reaches 0 on the clock following the clock that reaches the value specified in the timer 7 period setting register T7R when the interrupt flag T7OV is set 2 When 7 0 and 7 T67CNT 78 bits 6 and 7 are set to 0 the timer 7 counter stops at a count value of 0 In other cases the timer 7 counter continues operation 3 When data is written into T7R while timer 7 is run
112. e stopped while the system reset sequence is in progress Since they remain suspended after the reset is released they must be started under program control System clock frequency division function Low power consumption operation is possible The minimum instruction cycle can be selected from among 300ns 600ns 1 2us 2 Aus 4 8 5 9 6us 19 2us 28 Aus and 76 8 5 at a main clock rate of 10MHz 1 3 Internal reset circuit e Power on reset POR function 1 POR reset is generated only when power is turned on 2 The POR release level can be selected from 4 levels 2 57V 2 87V 3 86V and 4 35V by setting options e Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate reset when power is turned on and when power voltage falls below a certain level 2 The use non use of the LVD function and the low voltage detection level 3 levels 2 81V 3 79V 4 28V can be selected by setting options Standby function HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillators do not stopped automatically 2 There are four ways of releasing HALT mode lt 1 gt Low level input to the reset pin lt 2 gt Generating a reset by low voltage detection lt 3 gt Generating a reset by the watchdog timer lt 4 gt Generating an interrupt e HOLD mode Suspends instruction execution and operation of the peripheral circuits 1 The CF
113. e timer When the base timer is used as a 6 bit timer it can clock at intervals of approximately 2 ms if the 32 768 kHz subclock is used as the count clock The bit length change can be specified using the base timer control register BTCR Buzzer output function The base timer can generate a 2 kHz buzzer output when the 32 768 kHz subclock is used as the count clock The buzzer output can be controlled using the input signal select register ISL The buzzer output can be transmitted via pin P17 Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set The base timer can generate two types of interrupt requests base timer interrupt 0 and base timer interrupt 1 X tal HOLD mode operation and X tal HOLD mode release function The base timer is enabled for operation X tal HOLD mode when bit 2 of the power control register PCON is set X tal HOLD mode can be released by an interrupt from the base timer This function allows the microcontroller to perform low current intermittent operations 3 49 7 Itis necessary to manipulate the following special function registers to control the base timer BTCR ISL P1 PIDDR Address Initial Value BTIFO 3 8 3 Circuit Configuration 3 8 3 1 8 bit binary up counter 1 This counter is up counter that receives as its input the signal
114. e undefined at power on time When using the internal reset function it is necessary to implement and connect an external circuit to the reset pin according to the user s operating environment Be sure to review and observe the operating specifications circuit configuration precautions and considerations discussed in Section 4 6 Internal Reset Function 4 2 WDT 4 5 Watchdog Timer WDT 4 5 1 Overview This series of microcontrollers incorporates a watchdog timer WDT that has the following features 1 Capable of generating an internal reset signal on an overflow occurring in a timer that runs on either an internal low speed RC oscillator clock or subclock 2 Operation when the CPU enters standby mode can be selected from three modes continue count operation stop operation and stop count operation while retaining the count value The primary function of the watchdog timer is to detect program runaway conditions The use of the watchdog timer is highly recommended to enhance system reliability 4 5 2 Functions 1 Watchdog timer function A 17 bit up counter WDTCT runs on the WDT clock selected from either the internal low speed RC oscillator clock or subclock A WDT reset internal reset signal is generated when the overflow time selected out of 8 time values that is selected by the watchdog timer control register WDTCNT expires At this time reset detection flag WDTRSTF is set
115. ease level of 2 57V connect the external capacitor Core and pull up resistor of the values that match the power supply rise time to the reset pin and make necessary adjustments so that the reset state is released after the release voltage exceeds the minimum guaranteed operating voltage Alternatively set and hold the voltage level of the reset pin at the low level until the release voltage exceeds the minimum guaranteed operating voltage When POR release level is 2 57V Min guaranteed operating voltage Reset VIH level Reset undefined state LVUKS Figure 4 6 3 Sample Release Level Waveform in Internal POR Only Configuration 4 33 Internal Reset 3 When temporary power interruptions or voltage fluctuations shorter than several hundred us are anticipated The response time measured from the time the LVD detects a power voltage drop at the option selected level until it generates a reset signal is defined as the minimum low voltage detection width TLvbw shown in Figure 4 6 4 see Semiconductor Data Sheet If temporary power interruptions or voltage fluctuations shorter than this minimum low voltage detection width are anticipated be sure to take the preventive measures shown in Figure 4 6 5 or other necessary measures LVD release voltage LVD reset voltage B i LVDET Microcontroller Figure 4 6 5 Example of Power Interruption Voltage Fluctuation Countermeasures 4 34 LC87BKO00 C
116. ed by CFSTOP bit 0 If the OCR register is read when XT2PC bit 3 is set to 0 bit 3 reads the data at the CF2 XT2 pin and bit 2 reads the data at the CF1 XT1 pin 4 9 System Clock 5 bit 5 System clock select CLKCBA bit 4 System clock select lt l gt CLKCB5 and CLKCBA are used to select the system clock 2 CLKCBS CLKCBA are cleared on reset or when HOLD mode is entered CLKCB5 CLKCBA System Clock 0 Internal low medium speed RC oscillator 1 Main clock 0 XT2IN bit 3 CF2 XT2 pin data read only XT1IN bit 2 CF1 XT1 pin data read only Data that can be read via XTIIN varies as shown in the table below according to the value of EXTOSC bit 6 RCSTOP bit 1 Internal medium speed RC oscillator circuit control lt gt Setting this to 1 stops the oscillation of the internal medium speed RC oscillator circuit 2 Setting this bit to O starts the oscillation of the internal medium speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the internal RC oscillator circuit is enabled for oscillation 4 When the CPU enters HOLD mode this bit is set as described below according to the state of bit 1 of the SLWRC register If bit 1 of the SLWRC register is set to 1 the state of this bit remains unchanged If bit 1 of the SLWRC register is set to 0 this bit is cleared and the oscillator starts oscillation and is designated as the system clo
117. er SBRGI7 SBRGI6 SBRGIS SBRGI4 SBRGI3 SBRGI2 SBRGI I SBRGIO 3 53 SIO1 3 9 3 Circuit Configuration 3 9 3 1 5101 control register SCON1 8 bit register 1 Thisregister controls the operation and interrupts of SIO1 3 9 3 2 SIO1 shift register SIOSF1 8 bit shift register 1 This register is a shift register used to transfer and receive SIO1 data 2 Thisregister cannot be directly accessed with an instruction It is accessed via SBUFI 3 9 3 3 5101 data register SBUF1 9 bit register 1 Thelow order 8 bits of SBUFI are transferred to SIOSFI at the beginning of data transfer 2 At the end of data transfer the contents of SIOSF1 are placed in the low order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUF1 it is possible to check for a stop bit etc 3 9 3 4 SIO1 baudrate generator SBR1 8 bit reload counter 1 Thisisa reload counter for generating internal clocks 2 The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 54 LC87BKO0 Chapter Table 3 9 1 SIO1 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transfer Receive Transfer Receive Transfer Receive Transfer Receive SI1REC 0 SHREC 1 SI1REC 0 SHREC 1 SI1REC 0 SHREC 1 SHMREC 0 SHREC 1 None None Output Input See 1 and 2 Not required Not required See 2 below Low Low below Data output 8 8 8 8 8
118. er Pin Treatment Recommendations VDD1 VSS1 n 1 11 Chapter 2 Internal Configuration 2 1 Memory Space ee eee eee eee eee ee eee ee ee ee ee eee ee eee ree 2 1 2 2 Program Counter PC eee ee eee eee ee eee eee ee ee eee ee eee ee 2 1 2 3 Program Memory ROM 0n 0G 2 2 24 Internal Data Memory RAM B Le 2 2 2 5 Accumulator A Register ACC A 00 0L0 eee 2 3 2 6 B Register B 2 3 27 Register C eee eee eee eee eee eee eee eee eee eee eee ee eee eee eee eee eee eee eee eee 2 4 2 8 Program Status Word PSW C 2 4 2 9 Stack Pointer SP 0n0L0EL009C I 2 5 2 10 Indirect Addressing Registers ee eee eee eee eee eee ee eee eee eee ee 2 5 2 1 1 Addressing Modes 2 6 2 11 1 Immediate Addressing 2 6 2 11 2 Indirect Register Indirect Addressing Rn n8 2 7 2 11 3 Indirect Register C Register Indirect Addressing Rn CH 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off eee ere eee
119. errupts of T6 and T7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE78 0000 0000 R W 7 7 0 T6CO T7OV T7IE T6OV T6IE T7C1 bit 7 T7 count clock control T7CO bit 6 T7 count clock control T7C1 T7CO T7 Count Clock 0 Timer 7 prescaler and timer counter are stopped in the reset state 0 02 77 oo o 1 0 eme oo T6C1 bit 5 T6 count clock control T6CO bit 4 T6 count clock control T6C1 T6CO T6 Count Clock Timer 6 prescaler and timer counter are stopped in the reset state 4 T7OV bit 3 T7 overflow flag This flag is set at the interval of the timer 7 period when timer 7 is running This flag must be cleared with an instruction T7IE bit 2 T7 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T7OV are set to 1 T6OV bit 1 T6 overflow flag This flag is set at the interval of the timer 6 period when timer 6 is running This flag must be cleared with an instruction T6IE bit 0 T6 interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and T6OV are set to 1 3 7 4 2 Timer 6 period setting register T6R 1 Thisregister is an 8 bit register for defining the period of timer 6 Timer 6 period 6 1 x Timer 6 prescaler value 4 16 or 64 2 When data is wri
120. esssssssesssesmseessseses 4 25 455 Using the Watchdog Timer Fekuuashrsuyseuuuesuuesuseesuseenssenssessysesssesspessseeesseses 4 27 4 5 6 Notes on the Use of the Watchdog Timer PPP LLL 4 28 4 6 Internal Reset Function 4 29 4 6 1 Overview eee eee ere reer ee rere errr rere er err OTTO OTTO 4 29 4 6 2 Functions erect errr reer errr ere reer rere re Cece errr errr crete rrr rer rere eter rere ree ere rere 4 29 4 6 3 Circuit Configuration Fekursyusrasyssesuysesanesanesessenuseenssesssespssesssuaespsysesspeseseesssee 4 29 4 6 4 Options 4 30 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 4 32 4 6 6 Notes on the Use of the Internal Reset Circuit 4 33 4 6 7 Notes to be Taken When Not Using the Internal Reset Circuit 555555 4 35 Appendixes Appendix Special Function Register SFR Map n Al 1 7 Appendix ll Port Block Diagrams m MH All 1 6 Appendix Ill LC872000 LC87B000 Series On chip Debugger Pin Treatment Guide GE 1 2 LC87BKO00 Chapter 1 1 Overview 1 1 Overview The 87 00 series is an 8 bit microcontroller that centered around CPU running at a minimum bus cycle time of 83 3 ns integrates on a single chip a number of hardware features such as 8K byte flash ROM onboard programmable or 8K 6K 4K byte mask ROM 256 byte RAM an on chip debugger f
121. et circuit is not used as in case 1 in Subsection 4 6 7 When configuring an external POR circuit with a Cres value of 0 1uF or larger to obtain a longer reset period than with the internal POR however be sure to connect an external diode Dres as shown in Figure 4 6 8 Microcontroller Reset From POR Connect an external diode Figure 4 6 8 Sample External POR Circuit Configuration 4 36 Appendixes Table of Contents Special Function Register SFR Appendix ll Port 0 Block Diagram Port 1 Block Diagram Port 2 Block Diagram Port 7 Block Diagram Port 1 and Port 7 Interrupt Block Diagram Appendix lll e LC872000 LC87B000 Series On chip Debugger Pin Treatment Guide LC87BK00 APPENDIX I Address Initial Value R W LC87BK00 Remarks BIT8 BIT7 BIT6 5 4 BIT3 BIT2 BITI BITO 0 00FF XXXX XXXX RAN RAM256B 9 bits long FEO i NES ME Gs AM NEG ARE FEO WE ras een _ FEO S nes oea cnt contar ee DEE j FE05 WC m o o y o X ws UK Pr 0 0 F 3 EL te Gi wo me Wis ime xw rm 0000 0000 S ime 98 IPs _ rm 0000 0000 WW S s s
122. exist They are always read as 1 XTCFSEL bit 3 CF1 XT1 and CF2 XT2 input control lt 1 gt This bit and EXTOSC OCR FEOEH bit 6 and CFSTOP OCR FEOEH bit 0 are used to select the function of the CFI XTI and CF2 XT2 pins from among the main clock subclock and general purpose input port pins See 4 2 4 2 Oscillation control register for details XT2DR bit 1 CF2 XT2 input output control XT2DT bit 0 CF2 XT2 output data Register Data CF2 XT2 State XT2DT XT2DR Input Output Enabled Open Enabled Open 0 0 xe we o C 3 j saj m Note To use the CF2 XT2 as a general purpose output port set XTCFSEL XT2PC FE43H bit 3 to 0 CFSTOP OCR FEOEH bit 0 to 1 and EXTOSC OCR FEOEH bit 6 to 0 System Clock 4 2 45 Multifrequency RC oscillation control register 2 bit register 1 This register is a 2 bit register that controls the operation of the multifrequency RC oscillator circuit and selects the main clock Address Initial Value R W Name BIT7 6 5 BIT4 BIT3 BIT2 BIT1 BITO FEOD OOHH HHHH R W MRCR MRCSEL MRCST MRCSEL bit 7 Multifrequency RC oscillator clock select lt l gt When this bit is set to 1 the clock output from the multifrequency RC oscillator is selected as the main clock The multifrequency RC oscillator clock will be the system clock if the main clock is selected as the system clock in the OCR register setting 2 When this bit i
123. fers the contents of RAM address 133H to the accumulator 11 STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area to FFFFH 2 SFR area to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when contains since the basic area is 3 RAM stack area 0000H to the intended address OFDFFH 1 OFEO0H lies outside the basic area and is placed in the ACC as the result of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic area is 2 SFR area to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the re
124. fixed high and the signal that is obtained by frequency dividing the base timer clock by 16 fBST 16 is sent to P17 as the buzzer output When this bit is set to 0 the buzzer output is fixed high and the timer 1 PWMH output data is sent to P17 fBST The frequency of the input clock to the base timer selected by the input signal select register ISL bits 5 and 4 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select STOIN bit 0 Timer 0 count clock input port select These 3 bits have nothing to do with the control function of the base timer 3 52 LC87BKO0 Chapter 3 9 Serial Interface 1 SIO1 3 9 1 Overview The serial interface 1 5101 incorporated in this series of microcontrollers has the following four functions 1 Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system 2 to 512 Tcyc transfer clock 2 Mode 1 Asynchronous serial half duplex 8 data bits 1 stop bit 8 to 2048 Tcyc baudrate 3 Mode 2 Bus master start bit 8 data bits 2 to 512 Tcyc transfer clock 4 Mode 3 Bus slave start detection 8 data bits stop detection 3 9 2 Functions 1 Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The period of the internal clock is programmable within the range of 2 to 512 Tcyc 2 Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop b
125. h Business Unit
126. hapter 4 4 6 7 Notes to be Taken When Not Using the Internal Reset Circuit 1 When configuring an external reset IC without using the internal reset circuit The internal POR function is activated and the capacitor Cres discharging N channel transistor connected to the reset pin turns on when power is turned on even if the internal reset circuit is not used For this reason when connecting an external reset IC adopt a reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level 2 57V that does not affect the minimum guaranteed operating voltage The figures provided below show sample reset circuit configurations that use reset ICs of N channel open drain and CMOS types respectively Reset IC Microcontroller Several hundred N channel open drain type Reset From POR Figure 4 6 6 Sample Reset Circuit Configuration Using an N channel Open Drain Type Reset IC Insert a protective resistor of several to dozens of kO to prevent through current Reset IC Microcontroller CMOS type Reset From POR Figure 4 6 7 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4 35 Internal Reset 2 When configuring the external POR circuit without using the internal reset circuit The internal POR function is activated when power is turned on even if the internal res
127. hisregister is a 2 bit register that controls the I O direction of port 7 data and pull up resistors 2 When this register is read with an instruction data at pin P70 is read into bit Bit 4 is loaded with bit 4 of register P7 If P7 FESC is manipulated using a NOTI CLR1 SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced as bit 0 instead of the data at the port pin 3 Port 7 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BITO FESC HHHOHHHO R W P7 P70DDR P70DT Register Internal Pull up Resistor P70DDR Input Enabled Open OFF 0 0 1 O Enabled Intemalpul upresisr ON 0 1 Enabled LNchamd open drain low o Bits 7 to 5 These bits do not exist They are always read as 1 P70DDR bit 4 P70 UO control A lorO in this bit controls the output N channel open drain or input of pin P70 Bits 3 to 1 These bits do not exist They are always read as 1 P70DT bit 0 P70 data The value of this bit is output from pin P70 when P70DDR is set to 1 Since this bit is N channel open drain output type it is placed in the high impedance state when P70DT is set to 1 A lorO in this bit turns on or off the internal pull up resistor for pin P70 LC87BKO0 Chapter 3 4 3 2 External interrupt 0 1 control register 01 1 T
128. hisregister is an 8 bit register that controls external interrupts 0 and 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIF INTHE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P17 Pin Data 0 0 Falling edge detected 0 1 Low level detected 1 0 JRisingedge detected High level detected INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit INTIIE set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P70 Pin Data 0 Falling edge detected Low level detected 0 i ora s 1 0 JRisngedgedetected INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied
129. ister bit 1 is set to 0 Since the OCR register bits 1 4 5 are cleared the medium speed RC oscillator is activated and designated as the system clock when HOLD mode is released Since the MRCR register bits 6 7 are cleared the multifrequency RC oscillator is stopped when HOLD mode is released CPU and peripheral modules are stopped HOLD mode release conditions INTO or INT1 level interrupt request generated Request for INT2 4 or port 0 interrupt generated Reset entry conditions established Note 1 HALT mode entry condition PCON register FE07H bit 1 set to 0 and bit 0 to 1 Note 1 The CPU enters the reset state when the reset entry conditions are established Reset Main clock stopped Subclock stopped Low speed RC oscillator stopped Medium speed RC oscillator started Multifrequency RC oscillator stopped All registers initialized Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally HALT mode All oscillators retain the state established when HALT mode is entered CPU stopped Peripheral modules keep running HALT mode release conditions Interrupt request accepted Note 2 Reset entry conditions established Note 1 modes e Reset state release conditions Lapse of predetermined time after the reset entry conditions are removed X tal HOLD mode entry conditions
130. it 7 Base timer interrupt 0 period control This bit is used to select the interval at which base timer interrupt 0 is to occur When this bit is set to 1 the base timer interrupt O flag is set when an overflow occurs in the 6 bit counter The interval at which overflows occur is 64tBST When this bit is set to 0 the base timer interrupt 0 flag is set when an overflow occurs in the 14 bit counter The interval at which overflows occur is 16384tBST This bit must be set to 1 when high speed mode is to be used CS The period of the input clock to the base timer selected by the input signal select register ISL bits 5 and 4 BTON bit 6 Base timer operation control When this bit is set to 0 the base timer stops when the count value reaches 0 When this bit is set to 1 the base timer continues operation BTC11 bit 5 Base timer interrupt 1 period control 10 bit 4 Base timer interrupt 1 period control Base Timer Interrupt 0 Base Timer Interrupt 1 Period Period 16384tBST 321 5 1 0 0 BT 2 o 1 j i1 4BsST 1857 _ 1 0 BST 128487 0 1638488 51487 I 1 I 34BST 2044857 0 BTIF1 bit 3 Base timer interrupt 1 flag This flag is set at the interval of the base timer interrupt 1 period that is defined by BTFST BTC11 and 10 This flag must be cleared with an instruction BTIE1 bit 2 Base
131. it asynchronous serial communication The baudrate is programmable within the range of 8 to 2048 Tcyc 3 Mode 2 Bus master SIO1 is used as a bus master controller The start conditions are automatically generated but the stop conditions must be generated by manipulating ports Clock synchronization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combined with mode 3 to provide support for multi master configurations The period of the output clock is programmable within the range of 2 to 512 Tcyc 4 Mode 3 Bus slave SIO1 is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the output of acknowledge require program intervention SIOI can generate an interrupt by forcing the clock line to a low level on the falling edge of the 8th clock for recognition by a program 5 Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control the serial interface 1 5101 SCONI SBUFI SBRI P1 PIDDR PIFCR Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 0000 0000 SCONI SIIMI SIIMO SIIRUN SII REC SIIDIR SIIOVR SIIEND SIE SBUFIO 00000000 rw s
132. ive TOHRUN 0 the match buffer register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded with the contents of TOHR when a match signal is generated Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7 TOHR6 TOHRS TOHR4 TOHR3 TOHR2 TOHRI TOHRO 3 5 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE16 XXXX XXXX R TOCAL TOCAL7 TOCAL6 TOCALS TOCAL4 TOCAL3 TOCAL2 TOCALO 3 5 4 8 Timer counter 0 capture register high byte TOCAH 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE17 XXXX XXXX R TOCAH TOCAH7 TOCAH6 5 TOCAH3 2 TOCAHI TOCAHO 3 31 3 6 Timer Counter 1 T1 3 6 1 Overview The timer counter 1 T1 incorporated in this series of microcontrollers is a 16 bit timer counter that has the following four functions 1 Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle o
133. ived 5 is not automatically cleared Clear it by software e Read SBUFI and check the address f no address match occurs clear SILRUN and SILEND and exit interrupt processing then wait for a stop condition detection at in step 8 Receiving data e Clear SIIEND and exit interrupt processing If a receive sequence has been performed send an acknowledge and release the clock port after the lapse of SBR1 value 1 3 x Tcyc e When a stop condition is detected is automatically cleared and an interrupt is generated Then clear SI END to exit interrupt processing and return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs However the clock counter is cleared if a start condition is detected in the middle of receive processing in which case another 8 clocks are required to generate an interrupt Read SBUFI and store the read data Note Bit 8 of SBUFI is not yet updated because the rising edge of the 9th clock has not yet occurred Return to in step 6 to continue receive processing Transamitting data Clear SIIREC Load SBUFI with output data Clear SIIEND and exit interrupt processing Send an acknowledge for the preceding receive operation and release the clock port after the lapse of 5 1 value 1 3 x 3 61 SIO1 1 e Perform a transmit operation 8 bits
134. k Diagram TOLONG 1 TOLEXT 0 Capture trigger TDCAH TRE AE Registers 101CR FE5Dh I23CR FESEh ISL FESFh Clear I45CR FEAAh and I45SL FEABh need setting Capture External Clock input E in register Comparator TOLCMP TOHCMP Match buffer register Reload flag set TOHR TOLR a 6 bit programmable counter Figure 3 5 4 Mode 3 Block Diagram TOLONG 1 TOLEXT 1 LC87BKO0 Chapter 3 5 4 Related Registers 3 5 41 Timer counter 0 control register TOCNT 1 Thisregister is an 8 bit register that controls the operation and interrupts of TOL and TOH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The m
135. k select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Subclock Cycle clock 0 ee 1 O J Subclock Timer counter 0 prescaler output BUZON bit 3 Buzzer output timer 1 PWMH output select When P17FCR bit 7 is set to 1 this bit selects the data buzzer output or timer 1 PWMH output to be sent to P17 When this bit is set to 1 the timer 1 PWMH output is fixed high and a signal that is obtained by dividing the base timer clock by 16 fBST 16 is sent to P17 as buzzer output When this bit is set to 0 the buzzer output is fixed high and the timer 1 PWMH output data is sent to P17 JBST The frequency of the input clock to the base timer that is selected through the input signal select register ISL bits 5 and 4 NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select NFSEL NFON Noise Filter Time Constant l 32 3 2 Port 7 STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When this bit is set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 Note When timer OL capture signal input or
136. l interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH interrupt level control flag A lin this bit sets all interrupts to vector address 0000BH to the L level this bit sets all interrupts to vector address 0000BH to the X level XCNTO bit 0 00003H interrupt level control flag A in this bit sets all interrupts to vector address 00003H to L level A O in this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 This register is an 8 bit register that selects the level H or L of interrupts to vector addresses 00013H to 0004BH Address Initial Value R W Name BIT7 BIT6 BIT5 4 BIT2 BIT1 BITO FE09 00000000 R W IP IP43 IP3B IP33 IP2B IIP23 Interrupt Vector Address MEURE LENEI L 0004BH n 00043H IP43 0003BH IP3B 00033H IP33 la
137. l reset circuit 1f chatter occurs when power 15 turned on or if there is a possibility that a momentary power loss may occur Low voltage detection reset LVD function This function when used together with the POR function can generate a reset when power is turned on and when the power level lowers As a user option the use enable or non use disable and the detection level of this function can be specified Circuit Configuration The internal reset circuit consists of the POR LVD pulse stretcher circuit capacitor discharging transistor external capacitor Core pull up resistor or pull up resistor alone The circuit diagram of the internal reset circuit 15 provided in Figure 4 6 1 Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals It is used to stretch the internal reset period and discharge the external capacitor Cpgs connected to the reset pin The stretching time lasts from 30 us to 100 ps e Capacitor Cres discharging transistor This is an N channel transistor used to discharge the external capacitor connected to the reset pin If the capacitor Cres is not to be connected to the reset pin it is possible to monitor the internal reset signal by connecting only the external pull up resistor Regs Option selector circuit The option selector circuit is used to configure the LVD options This circuit selects whether to enable or disable the LVD
138. le 3 9 1 Transfer Transfer Receive SI1REC 0 SHREC 1 SIO1 Operations and Operating Modes cont Synchronous Mode 0 UART Mode 1 Receive SHREC 0 SHREC 1 Bus Master Mode 2 Transfer Receive 0 SHREC 1 Bus Slave Mode 3 Transfer SI1REC 0 Receive SI REC 1 SIIOVR 1 bit 2 Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions met when SIIEND 1 sss Lc ERU Shifter data update SBUFI shifter at beginning of operation Shifter gt SBUFI bits O to 7 Automatic data update of SBUFI bit 8 Data input lt 1 ES Falling edge of clock detected when SI RUN 0 2 SIIEND set conditions met when SIIEND 1 SBUF1 shifter at beginning of operation When 8 bit data transferred data Input data read in on stop bit When 8 bit 1 lt SILEND set conditions met when SIIEND 1 SBUFI shifter at beginning of operation Rising edge of 8th clock received Input data read in on rising edge of 9th clock 4 Data 8 bit shift register SIOSF1 output Clock At time At time operation transfer ends starts bit7 bit6 bit5 bit4 bit3 bit2 bit0 SBUF1 FE35h SIO1 output control gt P13 port latch 1 lt Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions met when SIIEND 1 3 Start bit detected SBUFI
139. ls with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SET1 or instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 gt gt 16 amp 1 Loads in PSW with bit 16 of the TBL address STW R0 Loads indirect register RO with the TBL address bits 16 to 0 LDCW 1 Reads the ROM table B 78H ACC 12H MOV 1 C Loads the C register with 01H LDCW RO C Reads the ROM table B278H ACC 12H INC Increments the register by 1 LDCW _ RO C Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW needs to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highest order byte of the address and the contents 16 bits of Rn Rn C or RO off either one as the low order bytes of the addres
140. mers Timer 0 16 bit timer counter with a capture register Mode 0 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit counter with an 8 bit capture register Mode 2 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register Mode 3 16 bit counter with 16 bit capture register Timer 1 16 bit timer counter that supports PWM toggle output Mode 0 8 bit timer with an 8 bit prescaler with toggle output 8 bit timer counter with an 8 bit prescaler with toggle output Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Mode 2 16 bit timer counter with an 8 bit prescaler with toggle output Toggle output also possible from the low order 8 bits Mode 3 16 bit timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a PWM module Timer 6 8 bit timer with a 6 bit prescaler with toggle output Timer 7 8 bit timer with a 6 bit prescaler with toggle output Base timer 1 The clock can be selected from the subclock 32 768kHz crystal oscillation system clock and timer 0 prescaler output 2 Interrupts can be generated at five specified time intervals 3 The base timer cannot be used when the CF oscillator circuit is selected Serial interface 5101 8 bit asynchronous synchronous serial interface Mode 0
141. mode X H and L levels Interrupt request level that can release L level X and H levels H level X level X level None unable to release with interrupt Figure 4 3 1 Standby Mode State Transition Diagram 4 19 Reset 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or while it is running 4 4 2 Functions This series of microcontrollers provides the following three types of reset functions 1 2 3 Exterior of microcontroller External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200 us or longer Note however that a low level of a small duration less than 200 us is likely to trigger a reset The RES pin can serve as a power on reset pin when it is provided with an appropriate external time constant Internal reset The internal reset function is available in two types the power on reset POR that triggers a reset when power is turned on and the low voltage detection reset LVD that triggers a reset when the power voltage falls below a certain level Options are available to set the power on reset resetting level to enable use and disable non use the low voltage detection reset function and to set the threshold level Reset function using a watchdog timer The watchdog timer of this series of microcontroller can be used to generate a reset b
142. mode When P06 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval of the timer 6 period and the value of the port data latch Bits 5 4 These bits do not exist They are always read as 1 CLKOEN bit 3 CKODV2 bit 2 CKODV bit 1 CKODVO bit 0 These 4 bits have nothing to do with the control functions of timers 6 and 7 See the description of port 0 for details on these bits 3 48 LC87BKO0 Chapter 3 8 Base Timer BT 3 8 1 Overview The base timer BT incorporated in this series of microcontrollers is a 14 bit binary up counter that has the following five functions 1 2 3 4 5 3 8 2 1 2 3 4 5 Clock timer 14 bit binary up counter High speed mode when used as a 6 bit base timer Buzzer output X tal HOLD mode release Functions Clock timer The base timer can count clocks at 0 5 second intervals when a 32 768 kHz subclock is used as the count clock for the base timer In this case one of the three clocks i e cycle clock timer counter 0 prescaler output and subclock must be selected by the input signal select register ISL as the base timer count clock 14 bit binary up counter A 14 bit binary up counter can be constructed using an 8 bit binary up counter and a 6 bit binary up counter These counters can be cleared under program control High speed mode when used as a 6 bit bas
143. modules Stopped except base timer WDTCNT bit 5 is cleared if WDTCNT register bit 4 0 and bit 3 21 WDTCNT register bit 5 is cleared if WDTCNT register bit 4 0 and bit 3 e PCON bit 0 turns to 1 If SLWRC register FE7C bit 1 is reset OCR register FEOE bits 5 4 and 1 are cleared If SLWRC register FE7C bit 1 is set SLWRC register FE7C bit 0 is set and OCR register FEOE bits 5 and 4 are cleared State established at entry time State established at entry time Note 1 State established at entry time State established at entry time State established at entry time Data retained State established at entry time State established at entry time Note 2 nterrupt request accepted Reset entry conditions established nterrupt request from INTO to INT2 INT4 or port 0 Reset entry conditions established WDTCNT register bit 5 is cleared if WDTCNT register bit 4 0 and bit 371 PCON bit 0 turns to 1 Stopped Stopped Stopped Note 1 Stopped Note 1 Stopped Stopped Stopped State established at entry time Stopped Stopped Stopped Stopped lt lt Data retained Data retained Stopped State established at entry time Stopped Stopped Interrupt request from INTO to INT2 INTA port 0 or base timer Reset entry conditions established HALT mode Note 2 HALT mode Note 2 PCON register bit 1 0 PCON register bit 1 0
144. n Set SIIREC to 0 and load SBUF1 with output data Set SILRUN Note Use the SIOI data I O port P14 when using SIO1 transmission only in mode 1 In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode I is on the falling edge of data is always detected at the data I O port P14 Consequently if the transmission port is assigned to the data output port P13 it is likely that data transmission is started unexpectedly according to the changes in the state of P14 5 Starting receive operation Set SIIREC to 1 Once SII REC is set to 1 do not attempt to write data to the SCONI register until the SIIEND flag is set Detect the falling edge of receive data 6 Reading data after an interrupt e Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data on the position of the stop bit is read into bit 1 of the PSW e Clear SIIEND and exit interrupt processing Return to step 4 to repeat operation Note Make sure that the following conditions are met when performing continuous receive operation in mode 1 UART The number of stop bits is set to 2 or greater Clearing of SITEND during interrupt processing terminates before the next start bit arrives 3 9 4 3 Bus master mode mode 2 Setting the clock Setup SBRI N Setting the mode Set as follows 51 00
145. n standby mode the execution of all instructions 1s suspended 4 3 2 Functions 1 HALT mode The CPU suspends the execution of instructions but its peripheral circuits continue processing Note 1 HALT mode 15 entered by setting bit 0 of the PCON register Bit 0 of the PCON register is cleared and the CPU returns to normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode All oscillations are suspended The CPU suspends the execution of instructions and the peripheral circuits stop processing Notes 1 2 HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 0 In this case bit 0 of the PCON register HALT mode setting flag is automatically set When a reset occurs or a HOLD mode release signal INTO INT2 INT4 or port 0 interrupt occurs bit 1 of the PCON register is cleared and the CPU switches to HALT mode 3 X tal HOLD mode All oscillations except the subclock oscillation are suspended The CPU suspends the execution of instructions and all the peripheral circuits except the base timer stop processing Notes 1 2 X tal HOLD mode is entered by setting bit 1 of the PCON register to 1 when bit 2 is set to 1 In this case bit 0 of the PCON register HALT mode setting flag 1s automatically set When a reset occurs or a X tal HOLD mode release signal base timer interrupt INTO INTI INT2 INTA or port 0 interrupt occurs bit 1 of th
146. n 8 bit register that controls the operation of the oscillator circuits selects the system clock and reads data from the CF1 XT1 and CF2 XT2 pins Except for read only bits 3 and 2 all bits of this register can be read or written Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOE 0000 XX00 R W OCR CLKSGL EXTOSC CLKCB5 CLKCB4 XT2IN XTIIN RCSTOP CFSTOP CLKSGL bit 7 Clock division ratio select lt 1 gt When this bit is set to 1 the clock selected by bits 4 and 5 is used as the system clock as is 2 When this bit is set to 0 the clock having a frequency of i of the clock selected by bits 4 and 5 is used as the system clock EXTOSC bit 6 CF1 XT1 and CF2 XT2 function control lt l gt When this bit is set to 1 and CFSTOP bit 0 is set to 1 the CFI XTI and CF2 XT2 pins serve as the pins for subclock oscillation and are prepared for oscillation when a crystal resonator 32 768 kHz typ capacitors and damping resistors are connected When the OCR register is read in this case bit 3 reads the data at the CF2 XT2 pin and bit 2 does not read the data at the CF1 XT1 pin but reads 0 2 When this bit is set to 0 and XT2PC bit 3 is set to 1 the CFI XTI and CF2 XT2 pins serve as the pins for main clock oscillation and are prepared for oscillation when a ceramic resonator capacitors feedback resistors and damping resistors are connected Start stop of the main clock oscillation is controll
147. nd 5 of the OCR register are cleared If bit 1 of the SLWRC register is set to 0 bits 1 4 and 5 of the OCR register are cleared 4 8 LC87BKO0 Chapter A When the CPU returns from HOLD mode the low or medium speed RC oscillator starts operation depending on the state of the SLWRC and registers and is designated as the system clock source The main clock and subclock return to the state that is established before the CPU enters HOLD mode When the CPU enters X tal HOLD mode all oscillators except subclock main clock low medium speed RC multifrequency RC are suspended but the state of the OCR register remains unchanged Since X tal HOLD mode is used usually for low current clock counting less current will be consumed if the system clock is switched to the subclock and low medium speed RC multifrequency RC oscillators are suspended before X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 PDN is cleared when a HOLD mode release signal INTO 2 INT4 or POINT or a reset signal occurs 4 Bit 0 is automatically set when is set IDLE bit 0 HALT mode setting flag lt 1 gt Setting this bit places the CPU into HALT mode 2 This bit is automatically set when bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 2 4 2 Oscillation control register OCH 8 bit register 1 This register is a
148. ning both the timer 7 prescaler and counter are cleared and start counting again 3 7 3 6 Timer 7 prescaler T7PR 6 bit counter 1 This prescaler is used to define the clock period for timer 7 with the value of T7CO and T7CI T67CNT 78 bits 6 and 7 Table 3 7 2 Timer 7 Count Clocks T7C1 T7CO T7 Count Clock 0 Timer 7 prescaler and timer counter are in reset state 0 EE Le ry 3 7 3 7 Timer 7 period setting register T7R 8 bit register 1 Thisregister defines the period of timer 7 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again 3 45 Timer 6 period setting register T6R FE7Ah Timer 6 7 control register T67CNT FE78h Set prescaler count value Timer 6 prescaler T6PR T6 overflow T6R 1 x count clock Clock 1Tcyc Timer 6 7 control register T67CNT FE78h T6 interrupt T7 interrupt Timer 7 counter T7CTR Timer 7 prescaler T7PR D 1Tcyc Set prescaler count value T7 overflow Timer 6 7 control register T7R 1 x count clock T67CNT FE78h Timer 7 period setting register T7R FE7Bh Figure 3 7 1 Timer 6 7 Operation Block Diagram 3 46 LC87BKO0 Chapter 3 7 4 Related Registers 3 7 4 4 Timer 6 7 control register T67CNT 1 Thisregister is an 8 bit register that controls the operation and int
149. ntrol An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 Note TIHCMP and TILCMP must be cleared to 0 with an instruction 3 6 4 2 Timer 1 prescaler control register T1PRR 1 This register sets the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer T1L T1H is updated Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE19 0000 0000 R W TIHPRC2 TIHPRCI TIHPRCO TILPRE TILPRC2 TILPRCI TILPRCO bit 7 Timer 1 prescaler high byte control T1HPRC2 bit 6 Timer 1 prescaler high byte control bit 5 Timer 1 prescaler high byte control T1HPRCO bit 4 Timer 1 prescaler high byte control T1HPRE T1HPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count T1LPRE bit 3 Timer 1 prescaler low byte control T1LPRC2 bit 2 Timer 1 prescaler low byte control T1LPRC1 bit 1 Timer 1 prescaler low byte control T1LPRCO bit 0 Timer 1 prescaler low byte control 3 40 LC87BKO0 Chapter TILPRE T1LPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count 0 1 l pop 3 6 4 3 Timer 1 low byte T1L 1 This is a read only 8 bit timer It counts up on prescaler output clock Address Initial Value R W Name BIT7 BIT6
150. ntrol of P04 07 is accomplished by POHDDR PODDR FE41 bit 1 Ports selected as CMOS output as a user option are provided with programmable pull up resistors The programmable pull up resistors may be of either low impedance or high impedance type user selectable The programmable pull up resistors for POO to are controlled by POLPU PODDR FE41 bit 2 Their type either low impedance or high impedance is selected by POLPUS PODDR FE41 bit 6 The programmable pull up resistors for P04 to 7 are controlled by POHPU PODDR FE41 bit 3 Their type either low impedance or high impedance is selected by POHPUS PODDR FE41 bit 7 2 Interrupt pin function POFLG PODDR FE41 bit 5 is set when an input port is specified and 0 level data is input to one of port bits whose corresponding bit in the port 0 data latch PO FE40 is set to 1 In this case if POIE PODDR FE41 bit 4 is 1 HOLD mode is released and an interrupt request to vector address 004BH is generated 3 1 Port 0 3 Multiplexed pin function 05 also serves as the system clock output PO6 as the timer 6 toggle output 7 as the timer 7 toggle output and POO to P06 as the analog input channel ANO to AN6 Address Initial Value R W Name BIT7 BITe BITS BIT3 BIT2 BITI BITO FE40 00000000 Rw ro rv ro pos pos por ro rm 0000 porcR
151. om the medium speed RC oscillator is designated as the system clock after the reset is released After HOLD mode is exited the clock from the medium or low speed RC oscillator that is selected when HOLD mode is entered is designated as the system clock 4 2 3 5 Multifrequency RC oscillator circuit with no variable modulation frequency function 1 This circuit oscillates due to the internal resistor and capacitor 2 Unlike conventional types the LC872G00 LC872RO00 series this circuit provides no variable modulation frequency function its clock output frequency is fixed at 1 2 of the 16 MHz source oscillation frequency 8 MHz 3 It is suited to generate a main clock which does not require the precision in frequency that the external CF oscillator would provide 4 2 3 6 Power control register PCON 3 bit register 1 This register specifies the operating mode normal HALT HOLD X tal HOLD 4 2 3 7 Oscillation control register OCR 8 bit register 1 Thisregister controls the start stop operations of the oscillator circuits 2 Theregister selects the system clock 3 Thisregister sets the division ratio of the oscillator clock to be used as the system clock to a or E 4 data at CFI XTI and CF2 XT2 pins can be read as bits 2 and 3 of this register 4 2 38 Low speed RC oscillation control register SLWRC 3 bit register 1 Thisregister controls the start stop operation of the low medium speed RC oscillat
152. ontrol of the five systems of oscillators to be executed independently through instructions The main clock and subclock oscillator circuits share pins 1 1 and CF2 XT2 and cannot be used at the same time The CF oscillator circuit may be either a low power dissipation type CF oscillation low amplifier or a CF oscillation normal amplifier 4 Multiplexed input pin function The CF oscillator crystal oscillator pins CFI XT1 and CF2 XT2 can also be used as general purpose input ports 5 Oscillator circuit states and operating modes Low speed RC Medium Mode Clock Main Clock Subclock Oscillator speed RC Note1 Oscillator Reset Stopped Stopped Stopped Running Stopped Medium speed RC oscillator Reset released Stopped Stopped Stopped Running Stopped Medium speed RC oscillator Programmable Programmable Programmable Programmable Programmable Programmable HALT State established State established State established State established State established State established at at entry time at entry time at entry time at entry time at entry time entry time OLD Stopped Stopped Stopped Stopped Stopped Stopped Multifrequency RC Oscillator System Clock Immediately after State established State established Running Stopped Low or medium exit from HOLD Jat entry time at entry time speed RC oscillator mode according to the state that has been defined on entry by bit 1 of SLWRC register X tal HOLD Stopped Stat
153. operating frequency shown in the examples vary with the microcontroller type Be sure to see the latest Semiconductor Data Sheet and select the appropriate setting level 4 31 Internal Reset 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 1 Waveform observed when only POR is used LVD not used Reset pin Pull up resistor only release voltage PORRL Reset period 4 gt Reset undefined state POUKS RES i There exists an undefined state POUKS before the POR transistor starts functioning normally The POR function generates a reset only when the power is turned on starting at the VSS level The reset release voltage in this case may have some range Refer to the latest Semiconductor Data Sheet for details No stable reset will be generated if power 15 turned on again if the power level does not go down to the VSS level as shown a If such a case is anticipated use the LVD function together as explained in 2 or implement an external reset circuit A reset 15 generated only when the power level goes down to the VSS level and power is turned again after this condition continues for 1005 or longer as shown in b 2 Waveform observed when both POR and LVD functions are used Reset pin Pull up resistor Rggs only LVD hysteresis width LVD release voltage LVHYS LVDET LVHYS LVD reset voltage LVDET EU genee eiser eege
154. or circuits 2 This register switches between the low speed RC oscillator clock and the medium speed RC oscillator clock 3 This register selects the amplifier size of the CF oscillator circuit CF oscillation low amplifier is effective for reducing power dissipation under such conditions as low voltage when 4 MHz or when the system frequency division ratio 1 4 to 1 16 4 2 39 CF1 XT1 and CF2 XT2 general purpose port input control register XT2PC 3 bit register 1 This register controls the functions of the main clock oscillator circuit 2 Theregister controls the general purpose output N channel open drain of the CF2 XT2 pin 4 2 3 10 Multifrequency RC oscillation control register 2 bit register 1 This register controls the start stop operation of the multifrequency RC oscillator circuit 2 Theregister selects the main clock from the external CF oscillator and multifrequency RC oscillator 4 2 3 11 System clock division control register CLKDIV 3 bit register 1 This register controls the operation of the system clock divider circuit The division ratios of i 1 1 1 1 1 1 ET and are available 4 8 16 32 64 128 H 4 7 System Clock CF1 XT1 CF2 XT2 EXTOSC Subclock Subclock X tal oscillator MRCSEL CFSTOP Main clock CF clock XTCFSEL CF oscillator Main clock MRCST Multifrequency RC oscillator CLKCB5 4 cI ksGL CLKDV2 0 SLRCSEL
155. pture register TOCAH on external input detection signals from the P17 INT1 TOHCP P15 INT3 TOIN P20 and P21 timer capture input pins TOL period TOLR 1 x 1 x Tcyc period 1 x TOPRR 1 x Tcyc Period of cycle clock Mode 1 8 bit programmable timer with a programmable prescaler with an 8 bit capture register 8 bit programmable counter with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signals from the P16 INT2 TOIN and P15 INT3 TOIN pins serves as 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from the P70 INTO TOLCP P16 INT2 TOIN P20 and P21 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from the P17 INTI TOHCP P15 INT3 TOIN P20 and P21 timer capture input pins TOL period TOLR 1 period TOHR 1 x TOPRR 1 x Tcyc 3 23 3 Mode 2 16 bit programmable timer with a programmable prescaler with a 16 bit capture register Timer counter 0 serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 from an 8 bit programmable prescaler The contents of TOL an
156. r 1 PWMH output select and base timer clock select Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 FESF 0000 0000 R W ISL STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON LC87BKO0 Chapter STOHCP bit 7 Timer OH capture signal input port select This bit selects the timer OH capture signal input port When this bit is set to 1 a timer capture signal is generated when an input that satisfies the INTI interrupt detection conditions is supplied to P17 If the INTI interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P17 When this bit is set to 0 a timer capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P15 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When this bit is set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P70 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P70 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 bit 5 Base timer cloc
157. r 1 count clock input timer IL functions as an event counter If INT4 is not specified for timer 1 count clock input the timer 1L counter counts on every 2 Port 2 3 3 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 3 5 HALT and Hold Mode Operation When in HALT or HOLD mode port 2 retains the state that is established when HALT or HOLD mode is entered LC87BKO0 Chapter 3 4 Port7 3 4 4 Overview Port 7 is a 1 bit I O port equipped with programmable pull up resistors It consists of a data control latch and a control circuit The I O direction is determined in 1 bit units Port 7 can be used as an input port for external interrupts It can also be used as a port for the capture signal input or HOLD mode release signal input There is no user option for this port 3 4 2 Functions 1 Input output port 1 bit P70 The port output data is controlled by bit 0 of the port 7 control register P7 FE5C and the I O direction is controlled by bit 4 P70 is N channel open drain output type The port bit is provided with a programmable pull up resistor 2 Interrupt input pin function P70 is assigned to INTO and is used to detect a low or high level or a low or high edge and to set the interrupt flag 3 Timer OL capture input function A timer OL capture signal is generated each
158. r WDIRSIT T WDT reset circuit WDTRSTF set signal WDTSL2 O IDLOP1 0 2 Standby mode WDTRST O IDLOP1 0 1 Enter standby mode WDTRUN clear signal WDTRUN WDTCKSL WDTRUN clear signal WDT reset WDTRSTF set signal EXTOSC OCR bit6 Enter HOLD mode Watchdog Timer Block Diagram 4 24 LC87BKO00 Chapter 4 Operation performed when IDLOP1 0 are set to 0 or 3 continue count operation Overflow WDTSL2 0 set count value WDTCT Count value 0 Time set in WDTSL2 0 WDT operation started MOV 55H WDTCNT WDT reset signal generated WDTRUN 1 instruction executed WDTRUN cleared to 0 Low speed RC oscillator WDTCT cleared to 0 WDTRSTEF set to 1 started Note Low speed RC oscillator stopped Operation performed when IDLOP1 0 are set to 1 stop operation Standby mode entered WDTSL2 0 set count value WDTCT Count value 0 WDT operation started WDTRUN cleared to 0 WDTRUN 1 Low speed RC Low speed RC oscillator stopped oscillator started Note Note Operation performed when IDLOP1 0 are set to 2 stop count operation while retaining the count value Standby mode entered Standby mode exited Overflow Low speed RC oscillator Low speed RC oscillator stopped Note started Note V WDTSL2 0 set count value xen WDTCT Count value 0 i Time set in WDTSL2 0 Standby mode time operation started WDT reset signal generated WDTRUN 1 WDTRUN cleared to 0 Low speed RC WDTRSTF set to 1
159. r applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter 1 Overview 1 1 Overview mH Hee 1 1 1 2 Features eee eee ere reer eee reer reer eee ee eee eee eee ree eee ee eee ree eT ee eee eee eee eee eee 1 1 1 3 Pin Assginment eee ee eee eee eee eee ee eee ee ee eee eee eee ee eee eee eee eee eee 1 6 1 4 System Block Diagram ee eee eee eee ee eee eee eee eee eee ee ee eee ee 1 7 1 5 Pin FUNCTIONS ess 1 8 1 6 On chip Debugger Pin Connection Requirements 1 10 1 7 Recommended Unused Pin Connections MB B 1 10 1 8 Port Output Types DUTOT 1 1 0 1 9 User Option Table MM M Mee 1 11 1 10 Pow
160. r the CF oscillator circuit 2 this bit selects the normal amplifier size for the CF oscillator circuit Predefined procedure is required to switch the selection See Subsection 4 2 5 SLRCSEL bit 1 Internal low medium speed RC oscillator clock select control lt 1 gt Alin this bit selects the clock for the internal low speed RC oscillator 2 this bit selects the clock for the internal medium speed RC oscillator SLRCSTAT bit 0 Internal low speed RC oscillator circuit control lt 1 gt Alin this bit starts the internal low speed RC oscillator circuit 2 0 this bit stops the internal low speed RC oscillator circuit 3 When a reset occurs this bit is cleared 4 This bit is set as described below according to the state of SLRCSEL bit 1 when the CPU enters HOLD mode If SLRCSEL bit 1 is set to 1 this bit is set and the oscillator starts oscillation and is designated as the system clock source when the CPU exits HOLD mode If SLRCSEL bit 1 is set to O the state of this bit remains unchanged 4 2 44 CF1 XT1 CF2 XT2 general purpose port input control register XT2PC 3 bit register 1 This register is a 3 bit register that controls the general purpose input at the and CF2 XT2 pins Address Initial Value R W Name BIT7 6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE43 0000 0000 R W XT2PC XTCFSEL XT2DR XT2DT Bits 7 to 4 and 2 These bits do not
161. re cable LC87FBK08A Programming board Package Programming Board MFP24S 300mil W87F2GM SSOP24 225mil W87F2GS SSOP24 275mil Make to order VCT24 3mm x 3mm W87FBGV 1 5 1 3 Pin Assignment P70 INTO TOLCP ANS 1 24 P07 T70 DBGP02 RES 2 23 P06 AN6 T6O DBGPO01 vss1 22 P05 AN5 CKO DBGP00 CFI XTI 4 21 1 P04 AN4 CF2 XT2 5 20 P03 AN3 VDD1 6 TOP VIEW 19 2 2 P10 7 18 71 PO1 AN1 Pll 8 17 P00 ANO 12 9 16 P2I INTA TIIN P13 SO1 DBGP12 10 15 P20 INT4 T1IN P14 SI1 SB1 DBGP11 11 14 P17 TIPWMH BUZ INTI TOHCP P15 SCK1 INT3 TOIN DBGP10 12 13 P16 TIPWML INT2 TOIN SANYO 245 300mil SSOP24 225mil lead free halogen free product SSOP24 275mll lead free halogen free product make to order z ied D ES t sy O XN eR EI CES BEA ie tei Juve Cel lt Hd H in e E EL E LEE S Oy uM H ez S4 GO SO cO QV OB a a a a a a a E EE E EJ P04 ANA 19 12 P17 T1PWMH BUZ INT1 TOHCP P05 AN5 CKO DBGP00 20 11 P16 T1PWML INT2 TOIN P06 AN6 T60 DBGP01 21 10 P15 SCK1 INT3 TOIN DBGP10 TOP VIEW zu P07 T70 DBGP02 22 9 P14 SI1 SB1 DBGP11 P70 INTO TOLCP AN8 23 8 P13 S01 DBGP12 RES 24 7 P12 a IN sn juni N e E ci
162. re set to 1 In this case WDTRUN is cleared 2 Clearing the WDTCT When the watchdog timer starts operation WDTCT counts up When this WDTCT overflows a WDT reset occurs To run the program in normal mode it is necessary to periodically clear WDTCT before it overflows Execute the following instruction to clear WDTCT while it is running MOV 55 WDTCNT 3 Detecting a runaway condition Unless the above mentioned instruction is executed at regular intervals WDTCT overflows because the watchdog timer is not cleared If an overflow occurs the watchdog timer considers that a program runaway has occurred and triggers reset In this case WDTRSTF WDTCNT bit 7 is set After a WDT reset occurs the program execution restarts at address 0000H In the flash ROM version the program execution restarts at the address selected as an option 4 27 WDT 4 5 6 Notes on the Use of the Watchdog Timer 1 2 When the internal low speed RC oscillator clock is selected as the clock WDTCKSL 0 If the internal low speed RC oscillator clock is not to be used as the system clock set SLRCSTAT SLWRC bit 0 to 0 the start stop of the internal low speed RC oscillator circuit is also controlled from the watchdog timer side If SLRCSTAT SLWRC bit 0 is set to 1 the internal low speed RC oscillator circuit continues oscillation in HALT mode even though the watchdog timer is running with IDLOPI and IDLOPO set to 1 or 2
163. register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOHRUN O the match buffer register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded with the contents of TOHR when a match signal is generated 3 25 10 3 5 3 8 Timer counter 0 capture register low byte TOCAL 8 bit register 1 Capture clock External input detection signals from the P70 INTO TOLCP P16 INT2 TOIN P20 and P21 timer OL capture input pins when TOLONG timer 0 control register bit 5 is set to 0 External input detection signals from the P17 INTI TOHCP P15 INT3 TOIN P20 and P21 timer capture input pins when TOLONG timer 0 control register bit 5 is set to 1 2 Capture data Contents of timer counter 0 low byte TOL 3 5 3 9 Timer counter 0 capture register high byte TOCAH 8 bit register 1 Captureclock External input detection signals from the P17 INTI TOHCP P15 INT3 TOIN P20 and P21 timer 0H capture input pins 2 Capture data Contents of timer counter 0 high byte TOH Table 3 5 1 Timer 0 TOH TOL Count Clocks Mode TOLEXT TOH Count Clock TOL Count Clock TOH TOL Count Clock 0 TOPRR match signal TOPRR match signal x w match signal External sign
164. s Examples LDW 934569 Sets up the low order 16 bits STW R5 Loads the indirect register R5 with the low order 16 bits of the address MOV 12H B Sets up the high order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123456H to the accumulator 2 9 2 12 Wait Operation 2 12 1 Occurrence of a Wait Operation This series of microcontrollers does not perform a wait operation that automatically suspends execution of instructions 2 12 2 What is a Wait Operation 1 2 3 4 5 When a wait request occurs according to the event explained in Subsection 2 12 1 the CPU suspends the execution of the instruction for one cycle during which the required data is transferred This is called a wait operation Peripheral circuits such as timers and PWM continue processing during the wait operation A wait operation is not performed 2 cycles or more consecutively The microcontroller does not perform a wait operation when it is in HALT or HOLD mode Note that one cycle of discrepancy is introduced between the progress of the program counter and progress of time once a wait operation occurs 2 10 LC87BKO00 Chapter 2 Table 2 4 1 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction Bit 8 RAM SFR P1 PSW Bit 1 Remarks LD LDW Kei 5 S P1 lt REG8 D P1 lt REGH8 REG8 lt P1 REGL8 REGH8 lt P1 REG8 amp lt P1 8 lt
165. s 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In the indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FE02H and the C register contains 1 the address B register FE02H 1 FEO1H is designated Examples When R3 contains 123 and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator 11 STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of RAM address 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 C L1 Decrements the contents of RAM address 125 by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area to FFFFH 2 SFR area to and 3 RAM stack area 00
166. s are as equal L1 L1 L2 L2 as possible Connect a large capacitance capacitor C1 and a small capacitance capacitor C2 in parallel The capacitance of C2 should be approximately 0 1uF L2 L1 e vss1 C1 C2 VDD1 L2 L1 2 Internal Configuration 2 1 Memory Space 87 00 Chapter 2 This series of microcontrollers has the following three types of memory space 1 Program memory space 256K bytes 128K bytes x 2 banks 2 Internal data memory space 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared with the stack area 3 External data memory space Address Program memory space 3FFFFH ROM bank 1 1FFFFH ROM bank 0 128KB 00000H Address FFFFH FFOOH FEFFH FEOOH FDFFH 0000H 16M bytes Internal data memory space Reserved for system SFR 8 bit some 9 bit RAM Stack 64 KB 9 bit config External data memory space Address FFFFFFH RAM 16MB 000000H Note SFR is the area in which special function registers such as the accumulator are allocated see APPENDIX A I Figure 2 1 1 Types of Memory Space 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The low order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current
167. s case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when the P16 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P16 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in both edge interrupt mode 7 Multiplexed pin functions P17 also serves as the timer 1 PWMH or base timer BUZ output P16 as the timer 1 PWML output and P15 to P13 SIO1 I O Interrupt Input Timer 0 Capture HOLD Mode Signal Detection Count Input Input Release CMOS N channel L level H level Timer 0H Enabled open drain L edge H edge Note L edge edge Enabled Both edges Yes TimerOH Note P17 HOLD mode release is enabled only when level detection is set Output Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE44 0000 0000 R W Pll P10 ses ww ipa rires ieope Tessar rises ruines Pion Fess 00000000 pircr Pi7FCR Pi6FCR Pi4FCR 2 000 Fixo Fixo ro mxo mxo Bits 7 to 4 and 0 of PITST FE47 are reserved for testing They must always be set to 0 3 2
168. s set to 0 the multifrequency RC oscillator is not selected as the main clock CF is designated as the main clock 3 This bit is cleared when the CPU enters HOLD mode MRCST bit 6 Multifrequency RC oscillation start control lt 1 gt A 1 in this bit starts the multifrequency RC oscillator circuit 2 A 0 in this bit stops the multifrequency RC oscillator circuit 3 This bit is cleared when the CPU enters HOLD mode Bits 5 to 0 These bits do not exist They are always read as 1 Note When the system clock is switched secure an oscillation stabilization time of 100 us or longer afier the multifrequency RC oscillator circuit switches from the oscillation stopped to oscillation enabled State 4 2 46 System clock division control register CLKDIV 3 bit register This register controls the frequency division processing of the system clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOC HHHH H000 R W CLKDIV CLKDV2 CLKDV1 CLKDVO Bits 7 to 3 These bits do not exist They are always read as 1 CLKDV2 bit 2 CLKDV1 bit 1 These bits define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 0 0 0 i 1 0 0 1 5 0 1 0 1 0 1 1 5 1 0 0 15 1 0 1 E 1 1 0 er 1 1 1 is 4 12 LC87BKO0 Chapter A 4 2 5 Example of Switching the CF Oscillation Amplifier Siz
169. s to match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 high byte 8 bit counter Start stop Stop start is controlled by the 0 1 value of TOHRUN timer 0 control register bit 7 Count clock Either a prescaler match signal or a TOL match signal must be selected through the 0 1 value of TOLONG timer 0 control register bit 5 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data needs to match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the low order byte of timer counter 0 16 bits of data needs to match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOLRUN 0 the match buffer register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Timer counter 0 match data register high byte 8 bit register with a match buffer register This register is used to store the match data for TOH It has an 8 bit match buffer
170. s to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt with the lowest vector address has priority No Vector Level Interrupt Source 1 00003H XorL INTO 6 000BH mp OB 00043 HorL ADC T6 T7 0004BH Priority level X gt H gt L When interrupts of the same level occur at the same time an interrupt with the lowest vector address is processed first Subroutine stack level Up to 128 levels The stack is allocated in RAM High speed multiplication division instructions 16 bits x 8 bits 5 Tcyc execution time 24 bits x 16 bits 12 Tcyc execution time 16 bits 8 bits 8 Tcyc execution time 24 bits 16 bits 12 Tcyc execution time Oscillator circuits Internal oscillator circuits 1 Low speed RC oscillator circuit For system clock 100kHz 2 Medium speed RC oscillator circuit For system clock IMHz 3 Multifrequency RC oscillator circuit For system clock 8MHz External oscillator circuits 1 High speed CF oscillator circuit For system clock with internal Rf 2 Low speed crystal oscillator circuit For low speed system clock with internal Rf lt 1 gt The CF oscillator circuit and the crystal oscillator circuit use the same pin the selection of which is programmable lt 2 gt Both the CF and crystal oscillator circuits ar
171. satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit must be cleared with an instruction as it is not cleared automatically bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P16 Pin Data 0 No edge detected Falling edge detected 0 1 0 Risingedgedetected INT2IF bit 1 2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when P16 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P16 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enabl
172. smission mode When SBUFI is read in the data on the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 9 1 no interrupt will be generated as is cleared in that case If there is a possibility of a condition for losing the bus contention for example when another device in master mode is in the system perform timeout processing using the timer module etc to detect the condition Return to step 6 to continue data transmission Go to step 10 to terminate communication 8 Receiving data Set 5 to 1 Clear SIIEND and exit interrupt processing receive 8 bits output SBUFI bit 8 acknowledge 9 Reading received data after an interrupt Read SBUFI Return to step 8 to continue data reception Go to in step 10 to terminate communication At this moment SBUFI bit 8 has already been output as acknowledge data and the clock for the master side has been released 10 Terminating communication Manipulate the clock output port 5 0 PI5DDR 1 P1520 and set the clock output to 0 Manipulate the data output port P14FCR 0 PI4DDR 1 P1420 and set the data output to 0 Restore the clock output port to the original state 1 PISDDR 1 P1520 and release the clock output Wait for all slaves to release the clock and the clock to be set to 1
173. sregister is an 8 bit register that controls the multiplexed pin outputs of port 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 0000 0000 R W PIFCR PI6FCR PISFCR P13FCR PI2FCR PIOFCR P1nFCR Pin Pin Data in Output Mode P1nDDR 1 Value of port data latch P17 1 The high data output at a pin that is selected as an N channel open drain output by user option is represented by an open circuit 1 1 1 1 1 1 1 0 anasu napr EE DE ny gu Wap amas Ta Pe sg rai px nu ls SENSE t EN RUNS ANS NE CEN NEUE pu 45 22 10572 INI SC E k i 8 3 7 Port 1 P17FCR bit 7 P17 function control timer 1 PWMH or base timer BUZ output control This bit controls the output data at pin P17 When P17 is placed in output mode P17DDR 1 and P17FCR is set to 1 timer 1 PWMH output or BUZ output from the base timer is EORed with the port data latch and the result is placed at pin P17 Selection between timer PWMH and the base timer BUZ output is accomplished by BUZON ISL FESF bit 3 P16FCR bit 6 P16 function control timer 1 PWML output control This bit controls the output data at pin P16 When P16 is placed in
174. st enable control The master interrupt enable register IE can be used to control the enabling disabling of H and L level interrupt requests nterrupt requests of the X level cannot be disabled Interrupt disable period Interrupts are held disabled for a period of 2 Tcyc after a write operation is performed to the IE 08 or IP FE09 register or HOLD mode is released No interrupt can occur during the interval between the execution of an instruction that loads the PCON 07 register and the execution of the next instruction No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts No Vector Address Selectable Level Interrupt Sources 00003H XorL INTO 0000BH INTI 00013H INT2 TOL INT4 0001BH INT3 base timer e OBH Hor ruri s OBH Hor E Priority level gt gt When interrupts of the same level occur at the same time an interrupt with the lowest vector address is processed first 7 Itis necessary to manipulate the following special function registers to enable interrupts and to specify their priority JE IP Initial Value Name BIT6 BIT5 BIT4 BIT2 BIT1 BITO 0000 00 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO IP Feo 0000 0000 rw w
175. sult of computation OFFO1 H amp OFFH 0FEO0H OFE01H 2 11 5 Direct Addressing dst Direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates the optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction 11 STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H 11 Decrements the contents of RAM address 123H by 1 and causes a branch if zero 2 8 LC87BKO00 Chapter 2 2 11 6 ROM Table Look up Addressing LC870000 series microcontrollers can read 2 byte data on the ROM into the BA register pair at once using the LDCW instruction Three addressing modes Rn Rn C and off are available for this purpose In this case only Rn is configured as 17 bit registers 128K byte space For mode
176. t port by manipulating the function control register As user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units Notes on the flash ROM version Port 15 is temporarily set low when the microcontroller is reset During the reset sequence do not apply a clock or any medium voltage level signal including Hi Z to port P13 For the treatment of the on chip debugger pins refer to the separately available documents entitled RD87 On chip Debugger Installation Manual and Appendix III LC872000 LC87B000 Series On chip Debugger Pin Processing 3 2 2 Functions 1 Input output port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch P1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor 2 Interrupt input pin function P17 is assigned to and is used to detect a low or high level or a low or high edge and to set the interrupt flag P16 and 15 are assigned to INT2 and INT3 respectively and used to detect a low or high edge or both edges and to set the interrupt flag 3 Timer 0 count input function count signal is sent to timer 0 each time a signal change that sets the interrupt flag is supplied to a port selected from P16 and 15 4 Timer
177. t 1 8 bit I O port P10 to P17 T O can be specified in 1 bit units T Pull up resistors can be turned on and off in 1 bit units Pin functions P13 SIOI data output 14 SIOI data input bus P15 SIO1 clock I O INT3 input input with noise filter timer 0 event input timer capture input P16 Timer 1 PWML output INT2 input HOLD release input timer 0 event input timer OL capture input P17 Timer 1 PWMH output buzzer output INT1 input HOLD release input timer 0H capture input P15 DBGP10 to DBGP12 On chip debugger 1 pins Interrupt acknowledge type Rising amp Falling H level L level Rising Falling Port 2 2 bit I O port P20 P21 O can be specified in 1 bit units Pull up resistors can be turned on and off in 1 bit units Pin functions P20 P21 INT4 input HOLD release input timer event input timer OL capture input timer 0H capture input Interrupt acknowledge type Rising amp Falling H level L level bit I O port O can be specified Pull up resistors can be turned on and off Pin functions P70 INTO input HOLD release input timer OL capture input P70 AN8 AD converter input port Interrupt acknowledge type Rising amp Falling Rising Falling H level L level Continued on next page 1 8 Continued from preceding page Name Description LC87BKO00 Chapter 1 RES
178. t and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P16 Pin Data 0 No edge detected Falling edge detected 0 1 0 Risingedgedetected INT2IF bit 1 2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when P16 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P16 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P16 it is recommended that P16 be used in both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 4 8 4 Input signal select register ISL 1 This register is an 8 bit register that controls the timer 0 input noise filter time constant buzzer output time
179. t data contains errors quantization error combination error use only the valid conversion results based on the specifications provided in the latest Semiconductor Data Sheet Send the above read data to application software processing Return to step 4 to repeat conversion processing 3 70 3 10 6 1 2 3 4 5 6 7 8 9 LC87BKO0 Chapter Hints on the Use of the ADC The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest edition of Semiconductor Data Sheet to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion function Do not place the microcontroller in HOLD mode while AD conversion processing is in progress Make sure that ADSTART is set to 0 before putting microcontroller in HOLD mode ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished the AD conversion end flag ADENDF is set and at the same time the AD conversion operation control bit ADSTART is reset The end of conversion processing can be identified by monitoring ADENDF Setting ADIE causes an interrupt request to vector address 0043H to be generated at the end of conversion The conversion time is doubled in the following cases The AD conversion is
180. te 1 TIPWML period 256 x TILPRC count x TIPWML low period TILR 1 x TILPRC count x Tcyc period TIHR 1 x TIHPRC count x TIPWML period TIPWMH period period x 2 5 Interrupt generation A TIL or interrupt request is generated at the counter period of TIL or T1H if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control timer 1 TICNT TIPRR TIL TIH TILR TIHR P1 PIDDR PIFCR P2 P2DDR 145 I45SL 0000 0000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHIE TILCMP TILIE Ere www x mur rus mua rus Crem x rm Tur nme Tina Note 1 The output of TIPWML is fixed high if TIL is stopped If TIL is running the output of TIPWML is fixed low when TILR The output of TIPWMH is fixed high if T1H is stopped If T1H is running the output of TIPWMH is fixed low when FFH 3 33 Ti 3 6 3 Circuit Configuration 3 6 3 1 Timer 1 control register TI CNT 8 bit register 1 This register controls the operation and interrupts of TIL and 3 6 3 2 Timer 1 prescaler control register TIPRR 8 bit register 1 This register sets the clocks for TIL and 3 6 3 3 Timer 1 prescaler low byte 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 con
181. ter are cleared If bit 1 of the SLWRC register is set to 0 bits 1 4 and 5 of the OCR register are cleared When the CPU returns from HOLD mode low or medium speed RC oscillator starts oscillation according to the values of the SLWRC and OCR registers and is designated as the system clock source The main clock and subclock return to the state that is established before the CPU enters HOLD mode and the multifrequency RC oscillator stops oscillation When the CPU enters X tal HOLD mode all oscillators except subclock main clock low medium speed RC multifrequency RC are suspended but the contents of the OCR SLWRC and MRCR registers remain unchanged Since no adequate oscillation stabilization time can be secured for the main clock and multifrequency RC oscillator when the CPU returns from X tal HOLD mode it is necessary to select the subclock or low medium speed RC oscillator as the system clock to be used when X tal HOLD mode is entered Since X tal HOLD mode is usually used for low current clock counting less current will be consumed if the system clock is switched to the subclock and low medium speed RC multifrequency RC oscillators are suspended before X tal HOLD mode is entered 2 XTIDLE must be cleared with an instruction 3 PDN is cleared when a HOLD mode release signal INTO INT2 INT4 or port 0 interrupt or a reset signal occurs 4 0 is automatically set when PDN is set IDL
182. ternal circuit or use the analog input channels ANO to AN of which the digital input buffer is closed 3 67 ADC12 3 10 4 2 AD mode register ADMRC 1 Thisregister is an 8 bit register that controls the operating mode of the AD converter Address Initial Value R W Name BIT7 BIT6 BIT5 4 BIT3 BIT2 BIT1 BITO FES9 0000 0000 R W ADMRC ADMD4 ADMD3 ADMD2 ADMDI ADMDO ADMR2 ADTMI ADTMO ADMD4 bit 7 Fixed bit This bit must always be set to 0 bit 6 AD conversion mode control resolution switching This bit selects the AD converter resolution between 12 bit AD conversion mode 0 and 8 bit AD conversion mode 1 When this bit is set to 1 the AD converter operates as an 8 bit AD converter The conversion results are placed only in the AD conversion result register high byte ADRHC and the contents of the AD conversion result register low byte ADRLC remain unchanged When this bit is set to 0 the AD converter operates as a 12 bit AD converter The conversion results are placed in the AD conversion result register high byte ADRHC and the high order 4 bits of the AD conversion result register low byte ADRLC 2 bit 5 Fixed bit This bit must always be set to 0 ADMD1 bit 4 Fixed bit This bit must always be set to 0 ADMDO bit 3 Fixed bit This bit must always be set to 0 ADMR2 bit 2 Fixed bit This bit must always be set to 0 ADTM1 bit 1 ADTMO bit 0
183. the INT3 interrupt detection conditions is supplied to P15 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P16 Note When timer OL capture signal input or timer OH capture signal input is specified for INT4 together with P70 or P17 to P15 the signal from P70 or P17 to P15 is ignored 3 11 Port 1 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port 1 retains the state that is established when HALT or HOLD mode is entered 3 12 LC87BKO0 Chapter 3 3 Port2 3 3 1 Overview Port 2 is a 2 bit I O port equipped with programmable pull up resistors It consists of a data latch a data direction register and a control circuit The I O direction is determined by the data direction register in 1 bit units Port 2 can also serve as an input port for external interrupts It can also be used as a port for the timer 1 count clock input timer 0 capture signal input and HOLD mode release signal input As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 3 2 Functions 1 Input output port 2 bits P20 and P21
184. time a signal change that sets the interrupt flag is supplied to the port selected from P70 and 16 When a selected level of signal is input to P70 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle intervals for the duration of the input signal 4 HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode medium or low speed RC oscillator selected as system clock When the interrupt is accepted the CPU switches from HALT mode to normal operating mode When a signal change that sets the interrupt flag is input to P70 that is specified for level triggered interrupts in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set 5 Multiplexed pin function P70 also serves as the ANS analog input channel function 3 17 Port 7 Interrupt Input Capture HOLD Mode Signal Detection Count Input Release N channel L level H level Timer OL Enabled Note open drain L edge H edge Note P70 HOLD mode release is enabled only when the level detection is set Address Initial Value R W Name BIT7 BIT6 5 BIT4 BITS BIT2 BIT1 BITO FESC HHHO HHHO R W P70DDR P70DT P7 INTOLH 3 4 3 Related Registers 3 4 3 1 Port 7 control register P7 1 T
185. trol register bit 6 2 Count clock Depends on the operating mode Mode T1LONG T1L Prescaler Count Clock 0 0 2 Tcyc events Note 1 0 deene Note 1 TIL serves as an event counter when INT4 is specified as the timer 1 count clock input in the external interrupt 4 5 pin select register I45SL It serves as a timer that runs on 2Tcyc as its count clock if INT4 is not specified as the timer 1 count clock input Note 2 TIL will not run normally if INT4 is specified as the timer I count clock input when TIPWM 1 When TIPWM 1 do not specify INT4 as the timer I count clock input 3 Prescaler count Determined by TIPRR value The count clock for T1L is output at intervals determined by the prescaler count T1LPRE TILPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count 0 ETE NN 4 Reset When timer 1 stops operation or a T1L reset signal is generated 3 34 LC87BKO0 Chapter 3 6 3 4 Timer 1 prescaler high byte 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Countclock Depends on the operating mode Mode T1LONG T1PWM T1H Prescaler Count Clock 0 0 2 Tcyc 3 Prescaler count Determined by the value The count clock for T1H is output at intervals determined by the prescaler count T1HPRE T1HPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count 0 1 128 256
186. tten into while timer 6 is running both the timer 6 prescaler and counter are cleared and start counting again 3 47 T6 T7 3 7 4 3 Timer 7 period setting register T7R 1 Thisregister is an 8 bit register for defining the period of timer 7 Timer 7 period 1 x Timer 7 prescaler value 4 16 or 64 Tcyc 2 When data is written into T7R while timer 7 is running both the timer 7 prescaler and counter are cleared and start counting again Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE7B 0000 0000 R W T7R T7R7 T7R6 T7R5 7 4 T7R3 T7R2 T7R1 T7RO 3 7 4 4 Port 0 function control register POFCR 1 POFCR is a 6 bit register used to control the multiplexed output of port 0 pins It controls the toggle outputs of timers 6 and 7 Address Initial Value R W Name BIT7 6 5 4 2 BIT1 BITO FE42 00HH 0000 R W POFCR T7OB T6OE CLKOEN CKODV2 CRODVI1 CKODVO T7OE bit 7 This bit is used to control the timer 7 toggle output at pin P07 This bit is disabled when 7 is in input mode When P07 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the waveform that toggles at the interval of the timer 7 period and the value of the port data latch T6OE bit 6 This bit is used to control the timer 6 toggle output at pin 06 This bit is disabled when P06 is in input
187. ue See Figure 4 5 2 for details of the WDT operating modes WDTSL2 bit 2 WDTSL1 bit 1 WDTSLO bit 0 WDTSL2 Overflow time select WDTSL1 WDTSLO Continue count operation Stop operation Continue count operation WDTCT Set Count Value and Overflow Generation Time Example Count Value Low speed RC Clock Subclock 0 0 0 1 EE Ur np de 1 1 1 1024 2048 4096 8192 16384 32768 65536 10 24ms 20 48ms 40 96ms 81 92ms 163 8ms 327 6ms 655 3ms 31 25ms 62 50ms 125 0ms 250 0ms 500 0ms 1 000s 2 000s 1 131072 1 3105 4 0005 Time values in low speed RC clock column of table refer to time for a WDTCT overflow to occur when the low speed RC oscillation frequency is 100 kHz typ The low speed RC oscillation frequency varies from IC to IC For details refer to the latest Semiconductor Data Sheet Time values in the subclock column of the table refer to the time for a WDTCT overflow to occur when the 32 768 kHz X tal oscillator is used Note The WDTCNT is initialized to 00H when a low level signal is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bit 6 and bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs Note The WDTCNT is disabled for writes once the WDT operation is started WDTRUN set to 1 If the 55H WDTCNT is executed in this c
188. unction flash ROM version only a sophisticated 16 bit timer counter may be divided into 8 bit timers a 16 bit timer counter may be divided into 8 bit timers or 8 bit PWMs two 8 bit timers with a prescaler a base timer serving as a time of day clock an asynchronous synchronous SIO interface a 12 bit 8 channel AD converter with 12 8 bit resolution selector a system clock frequency divider an internal reset circuit and 15 source 9 vector interrupt function 1 2 Features ROM Flash ROM version LC87FBKO8A 8192 x 8 bits Capable of onboard programming with a wide supply voltage range of 2 7 to 5 5V 128 byte block erase possible Can be written in units of two bytes Mask ROM version LC87BK08A 8192 x 8 bits LC87BK06A 6144 x 8 bits LC87BK04A 4096 x 8 bits RAM Flash ROM version LC87FBKO08A 256 x 9 bits Mask ROM version LC87BKO8A 256 x 9 bits LC87BKO06A 256 x 9 bits LC87BK04A 256 x 9 bits Minimum bus cycle time 83 3 ns I2MHz VDD 2 7 to 5 5V Note The bus cycle time here refers to the ROM read speed Minimum instruction cycle time Tcyc 250 ns 12MHz VDD 2 7 to 5 5V Ports Normal withstand voltage I O ports Ports whose I O direction can be designated in 1 bit units 12 P20 P21 P70 CF2 XT2 Ports whose I O direction can be designated in 4 bit units 8 POn Normal withstand voltage input port 1 CFI XTI Reset pin 1 RES Power pins 2 VSS1 VDD1 1 1 Ti
189. utput 8 bit programmable timer counter with an 8 bit prescaler with toggle output 2 Mode 1 8 bit with an 8 bit prescaler x 2 channels 3 Mode 2 16 bit programmable timer counter with an 8 bit prescaler with toggle output The low order 8 bits may be used as a timer counter with toggle output 4 Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits may be used as a PWM 3 6 2 Functions 1 Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output 8 bit programmable timer counter with an 8 bit prescaler with toggle output Two independent 8 bit programmable timers T1L and T1H run on a clock that is obtained by dividing the cycle clock by 2 TIL functions as an 8 bit programmable timer counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events while functions as an 8 bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2 TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and periods respectively Note 1 TIL period TILR 1 x TILPRC count x 2 Tcyc or TILR 1 x TILPRC count events detected TIPWML period period x 2 period 1 x TIHPRC count x 2 period period x 2 2 Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Two independent 8 bit PWMs TI
190. utput N channel open drain N channel open drain when selected as general purpose I O port Note 1 The control of the presence or absence of the programmable pull up resistors for port 0 and switching between low and high impedance pull up connections is exercised in nibble 4 bit units POO to or P04 to P07 1 10 1 9 User Option Table LC87BKO0 Chapter 1 Option to be Mask Flash ROM Option Selected Option Applied on Version 1 Version in Units of Option selection CMOS 1 bp N channel open drain CMOS P10 to P17 O 1 bit type N channel open drain CMOS P20 to P21 1 bit N channel open drain Program start x 00000H address 2 01E00H Detecti Enable Use Low voltage function Disable Non use detection reset function Detection 3 levels level Power on Power on reset function reset level O 4 levels Mask option selection No change is possible after mask is completed 2 Program start address of the mask version is 00000H 1 10 Power Pin Treatment Recommendations VDD1 VSS1 Connect bypass capacitors between the VDD1 and VSSI pins so that the following conditions are satisfied e Connect the VDD1 and 551 pins and bypass capacitors and C2 using the shortest possible heavy lead wires making sure that the impedances between both pins and bypass capacitor
191. utput that is cleared on a overflow and set on match signal 3 36 LC87BKO0 Chapter 2 Clock or gt TiL prescaler external events Set in 145CR FE4Ah 145SL FE4Bh registers Clock 2Tcyc gt T1H prescaler T1PWML output TIL Invert T1PWMH output Match buffer register Match buffer register Reload Reload T1LCMP T1HR T1HCMP flag set flag set 8 bit programmable 882055 gt 8 bit programmable timer gt Figure 3 6 1 Mode 0 Block Diagram T1LONG 0 TIPWM 0 Clock 1 gt T1L prescaler Clock 1 gt prescaler Overflow Reset Overflow T1PWML output Set Reset T1PWMH output Set Match buffer Match buffer register lt Reload 2 Reload T1LCMP flag set flag set lt 8 bit PWM lt 8 bit PWM Figure 3 6 2 Mode 1 Block Diagram T1LONG 0 T1PWM 1 register 2Tcyc external events Set in l45CR FE4Ah l45SL FE4Bh registers Clock T1H prescaler Clear mc de Invert Invert T1PWML T1PWMH output output Match buffer register 2 Reload TEM T1HR T1HCMP ag set flag set 16 bit programmable timer counter Figure 3 6 3 Mode 2 Block Diagram T1LONG 1 T1PWM 0 Match buffer register Reload T1LR Clock T1L prescaler T1H prescaler Clear m P Match T1PWM
192. value of this bit T1PWM bit 4 T1 output mode select This bit and 5 determine the output mode of TIPWMH and TIPWML as summarized in Table 3 6 1 Table 3 6 1 Timer 1 Output TTPWMH T1PWML Mode T1LONG TIPWM Toggle Period T1HR 1 x TIHPRC count x 2Tcyc x2 Toggle Period TILR 1 x TILPRC count output output x 2Tcyc x 2 or Period A x D HS count x events PWM Period 256 x TIHPRC count x Tcyc PWM Period 256 x count x Tcyc output output Toggle Period T1HR 1 x TIHPRC count x TILR 1 Toggle Period TILR 1 x TILPRC count x TILPRC count x 2 Tcyc x2 output x 2Tcyc x 2 or Period T1HR 1 x TIHPRC count x TILR 1 or Period ee x count x TILPRC count x events x 2 x events Toggle Period T1HR 1 x TIHPRC count x 256 x PWM Period 256 x ERC count x Tcyc output TILPRC count x x 2 output T1HCMP bit 3 match flag This flag is set if reaches 0 when is active TIHRUN 1 This flag must be cleared with an instruction 3 39 T1HIE bit 2 interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TIHCMP are set to 1 T1LCMP bit 1 T1L match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction 1 bit 0 T1L interrupt request enable co
193. y the internal low speed RC oscillator or the subclock at a predetermined time interval An example of a reset circuit 15 shown in Figure 4 4 1 The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power on reset circuit 15 configured Interior of microcontroller Watchdog timer WDT Internal Sync circuit reset signal Internal reset circuit POR LVD Figure 4 4 1 Sample Reset Circuit Block Diagram 4 20 LC87BK00 Chapter A 4 4 3 Reset State When a reset is generated by the RES pin internal reset circuit or watchdog timer the hardware functional blocks of the microcontroller are initialized by the reset signal that is in synchronization with the system clock Since the system clock 15 switched to the internal medium speed RC oscillator when a reset occurs hardware initialization is also carried out immediately even at power on time The system clock must be switched to the main clock when oscillation of the main clock 15 stabilized On reset the program counter is initialized to the program start address selected by the user option The special function registers SFRs are also initialized to the values that are listed the Special Function Register SFR Map shown in Appendix A I Notes and precautions The stack pointer is initialized to 0000H Data RAM is never initialized by a reset Consequently the contents of RAM ar

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