R32C/102 Group User`s Manual: DSP
Contents
1. RO1UHO208EJ0100 Rev 1 00 TENESAS Page 29 of 35 May 12 2011 R32C 102 Group JTAG Interface 9 JTAG Interface An on chip emulator is embedded in the CoolFlux DSP and debugging is controlled externally via a JTAG interface Refer to CoolFlux DSP Multi core Debugger User Guide for details RO1UHO208EJ0100 Rev 1 00 TENESAS Page 30 of 35 May 12 2011 R32C 102 Group Bootloader 10 Bootloader The DSP operates according to the DSP programs stored in the DSP program RAM When the power is turned on the DSP programs need to be transferred from the MCU ROM to the DSP program RAM since no programs are stored in the program RAM The bootloader which is stored in the DSP boot ROM as a default is a program for storing DSP programs and data transferred from the MCU to the DSP RAMs This chapter explains the procedure from the DSP program transfer to the start up 10 1 Overview The DSP supports program transfer mode and program execution mode They can be selected with the DSPC register belonging to the DAP control register using the MCU programs The DSP starts in program transfer mode by setting the DMOD bit in the DSPC register to 0 and then the DRR bit from 0 reset to 1 reset released and the bootloader runs After the program transfer the DSP starts in program execution mode by setting the DMOD bit to 1 and then the DRR bit from 0 to 1 and the DSP programs stored in the program RAM are executed RO1UHO208EJ02. The following illustration describes registers used throughout this manual e e e Register b7 b6 b5 b4 b3 b2 b1 bO Address Reset Value h sesseb b eef Dg not use this combination No register bit If necessary set to 0 When read the read value is y b2 undefined p EES Reserved Should be written with 0 Eko l b4 undefined value 5 e i Functions vary with operating modes Blank box Set this bit to 0 or 1 according to the function 0 Set this bit to 0 1 Set this bit to 1 X Nothing is assigned to this bit 2 RW Read and write RO Read only WO Write only the read value is undefined Not applicable 3 e Reserved bit This bit field is reserved Set this bit to a specified value For RW bits the written value is read unless otherwise noted 4 e No register bit s No register bit s is are assigned to this field If necessary set to 0 for possible future implementation e Do not use this combination Proper operation is not guaranteed when this value is set e Functions vary with operating modes Functions vary with peripheral operating modes Refer to register illustrations of the respective mode 4 Abbreviations and Acronyms The following acronyms and terms are used throughout this manual Abbreviation Acronym Meaning Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller
3. 2011 R32C 102 Group Synchronous Serial Interface Serial Interface Control Register b23 b16b15 b8 b7 bO Symbol Address Reset Value SCR 0022h 00 0000h b7 46 b5 b4 b3 b2 b1 bO ojoj Jojo fo Bit Name Function Reserved Should be written with 0 Reserved Should be written with 1 Reserved Should be written with 0 0 Reception disabled 1 Recel Enable Bit 1 Reception enabled 2 A A 0 Transmission disabled i it Taree Enable Bit 1 Transmission enabled 2 Reserved Should be written with 0 No register bits should be written with O and read as O 1 Changes should be made after setting bits RE and TE to 0 2 Enable the SSI with the SIS bit in the SIR register before setting this bit to 1 Figure 6 3 SCR Register Transmit Buffer Register b23 b16b15 b8 b7 bO Symbol Address Reset Value TBR 0023h 00 00XXh b7 b0 Data to be transmitted b23 b8 No register bits should be written with O and read as 0 Figure 6 4 TBR Register RO1UHO208EJ0100 Rev 1 00 TENESAS Page 15 of 35 May 12 2011 R32C 102 Group Serial Status Register b23 b16b15 b8 b7 bO SSR b7 46 b5 b4 b3 b2 b1 bO Bit Symbol b1 bo TSRE ORE RBRF b23 b8 No register bits should be written with O and read as 0 Symbol 0024h Bit Name Function Reserved Should be written with 0 Transmit Shift Register Empty Flag Reserved Should be written with 0 Overrun Error Flag Recei
4. LENESAS E 0 D 0 lt Q gt C D R32C 102 Group OO NO User s Manual DSP RENESAS MCU M16C Family R32C 100 Series All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest informaton published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 1 00 May 2011 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby un
5. and RBRF Bits in the SSR register SIS Bit in the SIR register Note 1 This is an internal signal and no pins exist Figure 6 1 SSI Block Diagram RO1UHOZ208EJ0100 Rev 1 00 TENESAS Page 13 of 35 May 12 2011 R32C 102 Group Synchronous Serial Interface 6 2 Registers Table 6 2 lists functions of SSI associated registers and Figure 6 2 to Figure 6 6 show the registers Table 6 2 Functions of Serial Communication Associated Registers Address Register Function 0020h Serial Interface Setting Register Enabling serial interface 0022h Serial Control Register Enabling disabling communication 0023h Transmit Buffer Register Setting data to be transmitted to the MCU 0024h Serial Status Register Communication status 0025h Receive Buffer Register Data received from the MCU The following DAP control registers also need to be set by the MCU e Set the TXDD bit in the DPC4 register to 1 set the DTXD pin to output e Set the TXDS bit in the DPC10 register to 1 output the DTXD signal e Set UART8 communication associated registers Serial Interface Setting Register b23 b16b15 b8 b7 bo Symbol Address Reset Value SIR 0020h 00 0000h r 7 b7 b6 b5 b4 b3 b2 b1 b0 1jojojojojojojo Slee cle ae ata Should be written with 1 No register bits should be written with O and read as O b23 b8 Figure 6 2 SIR Register RO1UHO208EJ0100 Rev 1 00 TENESAS Page 14 of 35 May 12
6. or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal cir
7. 10 3 1 1 Packet Header A packet header is 24 bit data to specify the memory type and start address of the destination Table 10 1 lists its details Table 10 1 Packet Header Details Bit Name Bit Setting b23 Packet type Set this bitto 0 b22 Read write bit Set this bit to O write 00b Do not use this combination 01b Program RAM 10b Data RAM 11b Coefficient RAM b21 to b20 Memory b19 to b16 Reserved Set these bits to 0 b15tobO Start address 1 Specify the start address of a transfer in 16 bits Note 1 Address 0000h is reserved and should not be specified as the start address when writing to the data RAM 10 3 1 2 Data Length Data length specifies the number of words of transferring data in 24 bits Data needs to be divided into multiple packets when the total number of words exceeds the range listed in Table 10 2 Table 10 2 Setting Range of Data Words Program RAM 1 to 2047 Data RAM and Coefficient RAM 1 to 4095 10 3 1 3 Transfer Data Transfer data is the data itself to be transferred The number of bits per word is 32 bits for the program RAM and 24 bits for the data RAM and coefficient RAM The MCU repeatedly transmits the data for the number of times specified in the data length 10 3 2 Checksum The DSP calculates a checksum after receiving a packet data and returns the value to the MCU upon the request The checksum value is a lower byte of the total value which is calculated b
8. 3 3 Overrun Error An overrun error occurs when the next data is received before reading the RBR register The ORE bit in the SSR register thereby becomes 1 overrun error occurs Figure 6 9 shows the timing of an overrun error DCLK PRO O 10010500 3 RBRF bit in the SSR register Data is transferred from the receive shift register to the RBR register Read the RBR register an undefined value is read ORE bit in the SSR register An overrun error occurs Set to 0 by a program Figure 6 9 Overrun Error Timing When an overrun error occurs set the ORE bit to 0 by a program and then read the RBR register to enable the next data reception The read value is undefined R01UH0208EJ0100 Rev 1 00 TENESAS Page 19 of 35 May 12 2011 R32C 102 Group Interrupt Controller 7 Interrupt Controller 7 1 Overview The DAP has an internal interrupt controller aside from the one in the MCU Interrupt requests to the DSP are transmitted from this internal interrupt controller There are two types of interrupts the SAl interrupt which is generated by the audio interface at each frame and the SSI interrupt which is generated by the SSI at transmission reception Either the reception complete interrupt or transmission buffer empty interrupt can be selected for the SSI interrupt Note that the SAI interrupt request has a higher priority and is accepted first when the SAI interrupt request and SSI interrupt request are generated
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10. Global System for Mobile Communications High Impedance Inter Equipment Bus Input Output Infrared Data Association Least Significant Bit Most Significant Bit Non Connection Phase Locked Loop Pulse Width Modulation Subscriber Identity Module Universal Asynchronous Receiver Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners TABLE OF CONTENTS 1 Overview 1 1 1 Performance OVeEIVIEW ossei oera a a a e a a a aeaa ae 1 2 DAP Control Registers 3 3 DSP 4 4 Memory and DSP Peripheral Function Registers 5 4 1 MEMO sic lt ataca ein 5 4 2 DSP Peripheral Function Registers ecra aiea oe EAA EE AE AEE RAE 6 4 3 Access CVCles ia La enira a 2 e antec tl baba eed aad 6 5 Serial Audio Interface 7 5 1 OVERVIOW E E A E E abdde tate tenohceed E bhleh TTII TTT ESEE 7 5 2 Regier S ia Ria 9 5 2 1 Audio Data Transmit Receive Buffer Registers ooonnnniccinnnnnnccccnnnnnocccccnnnnorcc cano nnrnccnnnnnnnnnnnn 9 5 3 Audio Data TransmissiOn ReceptiON oooocccccnncccnnnnccccccnconnonnnnnnncnnnnnncnnnnnnnnnn nn nn nnnnnnnnnnrnnnnnnnnnnnnnnnnnnnnns 11 5 3 1 Recepci n dd a 11 5 3 2 IANSMISSION ii da tees tale ne atte dali o rial am To TERO 12 6 Synchronous Serial Interface 13 6 1 OVENVIEW saton Sav mi edited babe ed ro ea ae aed endl dees 13 6 2 Kestel A 14 6 3 Data Transmission and ReceptiON oocconococccnccnnc
11. Reception 2 ceceeeeeeeeeeeeetteesennaees 35 ENESAS R32C 102 Group RENESAS MCU RO1UHO208EJ0100 Rev 1 00 May 12 2011 1 Overview The R32C 102 Group is a system in package SiP incorporating the R32C 100 Series CPU core embedded MCU and the CoolFlux DSP digital signal processor embedded digital audio processor DAP in one package The MCU and the DAP operate independently enabling the CPU to control devices and the DSP to control sound fields in parallel The MCU is connected to the DAP by two channels of serial interface to control the DAP and provide communication between the CPU and DSP DSP programs are also transferred from the MCU ROM to the DAP RAM using the serial interface This manual describes specifications of the DAP peripheral functions controlled by the DSP and program transfer from the MCU to DAP 11 Performance Overview Table 1 1 lists the specifications and Figure 1 1 shows a block diagram Table 1 1 Specifications Specification R5J64026LPFE CoolFlux DSP core R5J64026PFE R5J64029PFE Performance 1024 step fs 1536 step fs Operating Frequency DSP clock 1024 fs 45 158 MHz fs 44 1 kHz 49 152 MHz fs 48 0 kHz 1536 fs 67 737 MHz fs 44 1 kHz 73 728 MHz fs 48 0 kHz Arithmetic Precision 24 bits Multiply accumulate unit 24 bit x 24 bit 56 bit gt 56 bits 2 circuits Boot ROM e Program RAM 1 536 w
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13. does not automatically revert back to 0 since the DSP does not accept the interrupt In this case set it to 0 by a program Figure 7 3 ICR1 Register RO1UHO208EJ0100 Rev 1 00 TENESAS Page 22 of 35 May 12 2011 R32C 102 Group Interrupt Controller Interrupt Control Register 2 b23 b16b15 b8 b7 bO Note 1 Figure 7 4 Symbol Address Reset Value ICR2 0002h 00 0000h SSI Interrupt Request Flag 0 No interrupt requested SIR 1 RW 1 1 Interrupt requested No register bits should be written with O and read as undefined b23 b3 value This bit automatically becomes 0 once the DSP accepts an interrupt when the SSIE bit in the ICRO register is 1 interrupt enabled Do not set this bit to O by a program Although this bit becomes 1 when an interrupt is generated even when the SSIE bit is O interrupt disabled it does not automatically revert back to 0 since the DSP does not accept the interrupt In this case set it to 0 by a program ICR2 Register RO1UHO208EJ0100 Rev 1 00 TENESAS Page 23 of 35 May 12 2011 R32C 102 Group Interrupt Controller 7 3 Operation Sequence 7 3 1 Interrupt Setting Procedure e Steps to set the SAI interrupt 1 Set the SAIE bit in the ICRO register to O interrupt disabled 2 Set the AIR bit in the ICR1 register to 0 no interrupt requested 3 Wait for the AIR bit to become 1 interrupt requested 4 Set the AIR bit to 0 5 Set the SAIE bit to 1 interru
14. simultaneously Table 7 1 lists interrupts and Figure 7 1 shows a block diagram of the interrupt controller Table 7 1 Interrupts Interrupt Interrupt Request Generation Timing SAI interrupt At every frame 1 5 cycles of the BTCLK clock 1 to 2 cycles of the DSP clock after the rising edge 1 of the LRCLK signal SSI interrupt 2 Notes 1 It is the falling edge when using the 12S format SSI reception complete interrupt When the RBRF bit in the SSR register changes from 0 to 1 interrupt SSI transmit buffer empty When the TBRE bit in the SSR register changes from 0 to 1 2 Either the SSI reception complete interrupt or SSI transmit buffer empty interrupt can be selected for the SSI interrupt SAl interrupt source signal SSI reception complete SSI transmit buffer empty Interrupt controller SAL IREQ sQ Uaj SSI IREQ sQ R SAIE SSIE and SSIS Bits in the ICRO register AIR Bit in the ICR1 register SIR Bit in the ICR2 register Figure 7 1 RO1UHO208EJ0100 Rev 1 00 May 12 2011 Interrupt Controller Block Diagram SAl INT saLack Interrupt timing generation circuit SSI_INT SSI_ACK TENESAS CoolFlux DSP INT1 Page 20 of 35 R32C 102 Group Interrupt Controller Signals SAl INT and SSI_INT are connected to DSP interrupt port O INTO and interrupt port 1 INT1 respectively When an interrupt is accepted the instructio
15. 100 Rev 1 00 TENESAS Page 31 of 35 May 12 2011 R32C 102 Group Bootloader 10 2 Procedure on Starting DSP The MCU needs to transfer the DSP programs to DSP memories in order to start the DSP Figure 10 1 shows the procedure for the MCU programs to be executed from transferring the DSP programs to starting the DSP Set the DMOD bit in the DSPC register to 0 and then the DRR bit to 1 Pa ave at least 0 6 us elapsed after reset is released Yes Enable transmission and reception Receive a communication authorization code Is the communication authorization code 55h Disable reception Transmit a data packet Wait at least 1 6 us Enable reception Receive a checksum Completed all packet transmissions Set the DRR bit to 0 Set the DMOD bit to 1 and then the DRR bit to 1 Figure 10 1 DSP Start up Procedure MCU Programs la Starting the DSP in program transfer mode Establishing a connection for communication gt Transferring DSP programs gt Starting the DSP in program execution mode RO1UH0208EJ0100 Rev 1 00 RENESAS May 12 2011 Page 32 of 35 R32C 102 Group Bootloader Establishing a connection for the communication is required in order to enable the communication between the MCU programs and the bootloader After setting the DRR bit in the DSPC register from 0 reset to 1 reset released wait at least 0 6 us to receive a communication authorization code and make su
16. 84h 0025h Receive Buffer Register X Undefined 4 3 Access Cycles 0000XXh Table 4 3 lists the memory types and numbers of cycles to access the DSP peripheral function registers Table 4 3 Access Cycles Memory Type Access Cycles Program RAM 1 Data RAM 1 Coefficient RAM 1 DSP Peripheral Function Registers 1 2 Note 1 These registers cannot be accessed continuously using indirect addressing R01UH0208EJ0100 Rev 1 00 May 12 2011 TENESAS Page 6 of 35 R32C 102 Group Serial Audio Interface 5 Serial Audio Interface 5 1 Overview The serial audio interface SAI connects the DSP to the A D and D A converters There are two channels of SAI for input and three channels for output and they are all synchronized with the LRCLK and BITCLK Each channel has a data buffer for the L channel and R channel Serial audio data is input output via audio buffer registers Table 5 1 lists the specifications and Figure 5 1 shows the serial audio interface and its peripherals Table 5 1 Specifications Item Specification Selectable from the following Left justified format Right justified format or 12S format Bit Order Fixed to MSB first Data Format Selectable from the following paa Lengi 24 bits 20 bits or 16 bits Digital audio processor DAP Serial audio interface SAI MCLK converter 1 Lo AOUTIR uu AOLTB Stereo D A FO AOUTOL BUGER AORTB conver
17. AINL Stereo A D interface Stereo D A AOUT2L AINR converter pi SAI converter 2 AOUT2R SDINO SDOUTO SDIN1 O SDOUT1 SDOUT2 Interrupt controller Audio data Request zx Acknowledge CoolFlux DSP HO Coefficient RAM General purpose I O ports Synchronous serial interface SSI DAP control registers P10_0 DP_0 P10_7 DP_7 MCU P10_0 to P10_7 UART8 P11_0toP11_2 UART6 P15_4toP15_7 Note 1 CoolFlux DSP is an NXP Semiconductor DSP core Figure 1 1 DAP Block Diagram R01UH0208EJ0100 Rev 1 00 TENESAS Page 2 of 35 May 12 2011 R32C 102 Group DAP Control Registers 2 DAP Control Registers DAP control registers are accessed by the CPU and used to set the DSP operating conditions Table 2 1 lists only the DAP control registers required for controlling the DSP Refer to the R32C 102 Group User s Manual Hardware for details on the DAP control registers Table 2 1 DAP Control Registers Required for Controlling the DSP Register Function Audio Interface Configuration Register Selecting serial audio data format DSP Control Register Selecting DSP operating mode CODEC Data Selector Control Register Switching audio input signal DAP I O Pin Control Register 2 Controlling general purpose l O ports DAP I O Pin Control Register 3 Controlling general purpose l O ports DAP I O Pin Control Register 4 Setting environment for serial communication DAP I O Pin Control Register 7 Controlling
18. AS Page 17 of 35 May 12 2011 R32C 102 Group Synchronous Serial Interface 6 3 2 Data Reception When one character 8 bits of data is received the data is transferred from the receive shift register to the RBR register and the next data reception becomes enabled The double buffered structure of the RBR register and receive shift register enables continuous data reception Make sure that the RBRF bit in the SSR register is 1 data held in the RBR register before reading the RBR register An SSI receive complete interrupt request is generated toward interrupt controller in the DAP at the same time as the RBRF bit becomes 1 Perform the following reception procedure e Before receiving 1 Set bits TE and RE in the SCR register to 0 transmission reception disabled 2 Set the SIS bit in the SIR register to 1 3 Set the RE bit in the SCR register to 1 reception enabled e Receiving data 4 Wait for the RBRF bit in the SSR register to become 1 data held in the RBR register 5 Read data from the TBR register Figure 6 8 shows an operation example of data reception DCLK o 0 00000 01200002004 RBRF bit in the SSR register 7 Read the RBR register a Transferring data from the receive shift register to the RBR register receive interrupt source Figure 6 8 Operation Example of Data Reception RO1UHO208EJ0100 Rev 1 00 TENESAS Page 18 of 35 May 12 2011 R32C 102 Group Synchronous Serial Interface 6
19. BRE bit in the SSR register is 1 no data in the TBR register to set data in the TBR register An SSI transmit buffer empty interrupt request is generated toward the interrupt controller in the DAP at the same time the TBRE bit becomes 1 When a synchronous clock signal is input while the TE bit in the SCR register is O transmission disabled the following values are transmitted FFh when the MSB of the previously transmitted data is 1 and 00h when the MSB is 0 Perform the following transmission procedure Before transmitting 1 Set bits TE and RE in the SCR register to 0 transmission reception disabled 2 Set the SIS bit in the SIR register to 1 3 Set the TE bit in the SCR register to 1 transmission enabled e Transmitting data 4 Wait for the TBRE bit in the SSR register to become 1 no data in the TBR register 5 Write transmit data to the TBR register Figure 6 7 shows an operation example of data transmission Set the next transmit data a b during transmission TBRE bit in the y SSR register Transmission Transmission Transmission Transmission starts completes starts completes TSRE bit in the SSR register DCLK Transmitting 8 bit data Continuous transmission of two 8 bit data a Setting data to the TBR register b Transferring data from the TBR register to the transmit shift register Figure 6 7 Operation Example of Data Transmission RO1UHO208EJ0100 Rev 1 00 TENES
20. DPIE Bit in the DICO register belonging to the DAP control register Figure 8 1 General Purpose I O Port Block Diagram RO1UHO208EJ0100 Rev 1 00 TENESAS Page 26 of 35 May 12 2011 R32C 102 Group General Purpose I O Ports 8 2 Register DSP I O Register b23 b16b15 b8 b7 Address Reset Value 0007h 00 0000h Bit Symbol Bit Name Function When set as input A value is written to the corresponding bit It is not output to General Purpose I O Port 1 DAP general purpose I O ports due to input mode selected The read value is the state of the corresponding DAP general purpose l O ports as follows General Purpose l O Port 3 0 Low 1 High General Purpose l O Port 0 General Purpose l O Port 2 General Purpose l O Port 4 When set as output The written value is reflected to the level of the corresponding general purpose I O port General Purpose I O Port 6 0 Output low 1 Output high The read value is the value set in the corresponding bit b23 b8 No register bits should be written with 0 and read as 0 Figure 8 2 DIOR Register General Purpose I O Port 5 General Purpose I O Port 7 RO1UHO208EJ0100 Rev 1 00 TENESAS Page 27 of 35 May 12 2011 R32C 102 Group General Purpose I O Ports 8 3 Input Output Setting Set pin I O using the CPU programs 8 3 1 Input Setting Perform the following to set the general purpose I O ports to input and MCU port P10 to input output 1 Setting input o
21. Figure 5 7 Registers AORTB to A2RTB RO1UHO208EJ0100 Rev 1 00 TENESAS Page 10 of 35 May 12 2011 R32C 102 Group Serial Audio Interface 5 3 Audio Data Transmission Reception 5 3 1 Reception Figure 5 8 shows an operation example when receiving serial audio data ere JL UUL VUUUL UVUUL UUUUUUUVI LRCLK L channel R channel L channel R channel L channel R channel SDINn L data 1 R data 1 L data 2 R data 2 j L data 3 R data 3 AnLRB register E eer data 1 j L data 2 AnRRB register ta TMX data 1 j R data 2 SAI interrupt source i signal gt 1 cycle of the DSP clock gt 1 5 cycles of the BITCLK clock 1 to 2 cycles of the DSP clock The figure above applies under the following condition When the BCKS bit in the AIFC register belonging to the DAP control register is O BITCLK is 64 fs Figure 5 8 Operation Example When Receiving Audio Data in Left justified Format n 0 1 After the L channel and R channel have successively completed receiving serial audio data the data is transferred to registers AnLRB and AnRRB respectively Then an SAI interrupt source signal is generated The SAI interrupt source signal is input to the DAP s internal interrupt controller Refer to 7 Interrupt Controller for details on interrupts RO1UHO208EJ0100 Rev 1 00 TENESAS Page 11 of 35 May 12 2011 R32C 102 Group Serial Audio Interface 5 3 2 Transmission Figure 5 9 shows an operation example when transmit
22. SAI interrupt is Interrupt signal SSI_INT accepted Interrupt acknowledge signal SSI_ACK SSI interrupt is 2 to 5 cycles of the 2 to 5 cycles of the accepted DSP clock DSP clock Figure 7 6 Operation Example of Multiple Interrupts R01UH0208EJ0100 Rev 1 00 TENESAS Page 25 of 35 May 12 2011 R32C 102 Group General Purpose I O Ports 8 General Purpose I O Ports 8 1 Overview General purpose I O ports are connected to MCU port P10 in a wired OR configuration They enable communication between the DSP and MCU and communication with external devices using ports DP_0 to DP_7 Use the CPU programs to set the general purpose I O ports The ports can be set to either input or output in 1 bit units Refer to 8 3 Input Output Setting for details Figure 8 1 shows a block diagram associated with the general purpose ports CoolFlux DSP General purpose I O ports DSP PO DPOS DPOD Port latch H ort latc 3 P nt I Port read signal i lt CH l il P10_6 DP_6 O P10_5 DP_5 O P104 DP4O P10_3 DP_3 0 P102 DP2O P10_1 DP_1 O P10_0 DP_0 O O NR oa a NR o a DPOS to DP2S Bits in the DPC7 register belonging to the DAP control register DP35S and DP67S Bits in the DPC8 register belonging to the DAP control register DPOD to DP5D Bits in the DPC2 register belonging to the DAP control register DP6D and DP7D Bits in the DPC3 register belonging to the DAP control register
23. ccccnccnccnnonnonnnncnnnnnnnnnncnnnnnnnnn nn nn nnnnnnnnnr nn nn nnnannnn nen 17 6 3 1 Data Transmission a e e nd km ar rato ra lao Tla 17 6 3 2 Data Reception ice sa a A erta a dial ria 18 6 3 3 Overrun EMO samc a nm Tato peo udu an 2 danan nape cues eee a NOS 19 7 Interrupt Controller 20 71 OVEIVIEW tt armoj suai ether nalts pide Ln KO eect dead A era ate ied dares 20 7 2 ROSS ivi a l AL LA LLL LAA A 22 7 3 Operation SSQuenCe ois vade stall lal ented hatbeaute And llenado mruua o buda logi tia lail kas etica 24 7 3 1 Interrupt Setting Procedure c ecess a EAA R ET aA ee RE 24 7 3 2 SINGIS ONP aAa sku ka AA E A ees T eee eee eee 24 7 3 3 Multiple Interr pts caia e ert karabo Loa aspera 25 8 General Purpose I O Ports 26 8 1 NN 26 8 2 Register dt 27 8 3 Input Output Setting 3 sss a stu ler coa 28 8 3 1 Input Setii sm sn gaan eke na o in kann lto onk as kodo 28 8 3 2 tput Set msm ean oo ve eka ea e Ine en Trello 29 9 JTAG Interface 30 10 Bootloader 31 10 1 O 31 10 2 Procedure on Starting DSP esr sitio AN sL isn LV ise katia 32 10 3 DSP PrograM Transfer ss ssistretas licencia coil beboolb lan desea kado accetantes condo ta o akg oka dabe aksa bidodo 33 10 3 1 Data Packets sas ot mu pu A aan etree E nu ee ro en et 33 10 3 2 CHECKSUM wise 2 itt sen rne SA abo ekoo frak lu nolan Lae kdo 34 10 4 Transmit Data Formats isets sra eet cig di 35 10 5 Communication Authorization Code and Checksum
24. cuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stabl
25. der any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Elec
26. e 5 Differences between Products Before changing from one product to another e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products 1 About This Manual Purpose and Target User This manual is designed to be read primarily by application developers who have an understanding of this microcomputer MCU including its hardware functions and electrical characteristics The user should have a basic understanding of electric circuits logic circuits and MCUs Carefully read all notes in this document prior to use Notes are found throughout each chapter The Revision History at the end of this manual summarizes primary modifications and additions to the previous versions For details please refer to the relative chapters or sections of this manual The R32C 102 Group includes the documents listed below Verify this manual is the latest version by visiting the Renesas Electronics website Type of Document Datasheet Contents Overview of Hardware and Electrical Characteristics Document Name R32C 102 Group Datasheet Document Number REJO3B0300 0101 User s Manual Hardware Specificat
27. general purpose l O ports DAP I O Pin Control Register 8 Controlling general purpose I O ports DAP I O Pin Control Register 10 Setting environment for serial communication DAP Input Signal Control Register 0 Controlling general purpose I O ports RO1UHO208EJ0100 Rev 1 00 TENESAS Page 3 of 35 May 12 2011 R32C 102 Group DSP 3 DSP Figure 3 1 shows a block diagram of the DSP Interrupt request CoolFlux DSP a Serial audio interface SAI General purpose I O ports Synchronous serial interface SSI Program control Figure 3 1 DSP Block Diagram RO1UHO208EJ0100 Rev 1 00 TENESAS Page 4 of 35 May 12 2011 R32C 102 Group Memory and DSP Peripheral Function Registers 4 Memory and DSP Peripheral Function Registers 4 1 Memory The DSP uses program memory data RAM and coefficient RAM The program memory contains a boot ROM and program RAM The target memory switches to the boot ROM in program transfer mode and program RAM in program execution mode Table 4 1 lists memory specifications Table 4 1 Memory Size Program RAM Data RAM Memory Size Bits Per Word 32 bits R5J64026LPFE 1 536 words R5J64026PFE R5J64029PFE 3 072 words 24 bits 4 096 words 12 288 words Coefficient RAM 24 bits 512 words 1 792 words RO1UHO208EJ0100 Rev 1 00 May 12 2011 TENESAS Page 5 of 35 R32C 102 Group Memory a
28. h Figure 5 3 shows the bit configuration of each buffer register and Figure 5 4 to Figure 5 7 show the buffer registers b23 bO Data length 24 bits Audio data 24 bits Data length 20 bits Audio data 20 bits Data length 16 bits Audio data 16 bits Figure 5 3 Bit Configurations of the Buffer Registers The 4 lower bits in the 20 bit data and the 8 lower bits in the 16 bit data are all read as 0 from the receive buffer registers They are all transmitted as 0 regardless of the values written to the transmit buffer registers Audio Receive Buffer Register Ln n 0 1 b23 bo Symbol Address Reset Value AOLRB A1LRB 0010h 0018h Undefined b23 b0 L channel receive audio data RO Figure 5 4 Registers AOLRB and A1LRB Audio Receive Buffer Register Rn n 0 1 b23 bo Symbol Address Reset Value AORRB A1RRB 0011h 0019h Undefined b23 b0 R channel receive audio data RO Figure 5 5 Registers AORRB and A1RRB RO1UHO208EJ0100 Rev 1 00 TENESAS Page 9 of 35 May 12 2011 R32C 102 Group Serial Audio Interface Audio Transmit Buffer Register Ln n 0 to 2 b23 bO Symbol Address Reset Value AOLTB A1LTB A2LTB 0012h 0014h 0016h 00 0000h b23 b0 L channel transmit audio data Figure 5 6 Registers AOLTB to A2LTB Audio Transmit Buffer Register Rn n 0 to 2 b23 bO Symbol Address Reset Value AORTB A1RTB A2RTB 0013h 0015h 0017h 00 0000h b23 b0 R channel transmit audio data
29. ions and detailed descriptions of pin layout memory map peripherals electrical characteristics timing characteristics Refer to the Application Manual for peripheral usage R32C 102 Group User s Manual Hardware REJ09B0578 0101 User s Manual DSP Specifications and detailed descriptions memory map and peripherals of the DSP embedded in the DAP of this MCU R32C 102 Group User s Manual DSP This publication User s Manual Software Software Manual Descriptions of instruction set R32C 100 Series Software Manual REJO9B0267 0100 Application Note Usages Applications Sample programs Programing technics using Assembly language or C programming language Renesas Technical Update Bulletins on product specifications documents etc Available on the Renesas Electronics website 2 Numbers and Symbols The following explains the denotations used in this manual for registers bits pins and various numbers 1 Registers bits and pins Registers bits and pins are indicated by symbols Each symbol has a register bit pin identifier after the symbol Example PMO3 bit in the PMO register P3_5 pin VCC pin 2 Numbers A binary number has the suffix b except for a 1 bit value A hexadecimal number has the suffix h A decimal number has no suffix Example Binary notation 11b Hexadecimal notation EFAOh Decimal notation 1234 3 Registers
30. n jumps to the address set in the interrupt vector table Refer to CoolFlux DSP Assembly Programmer s Manual or CoolFlux DSP C Programmer s Manual for details on the interrupt vectors Figure 7 2 to Figure 7 4 show the interrupt control registers RO1UHO208EJ0100 Rev 1 00 TENESAS Page 21 of 35 May 12 2011 R32C 102 Group Interrupt Controller 7 2 Registers Interrupt Control Register O LZ PIS bid DB DE bo Symbol Address Reset Value ICRO 0000h 00 0000h Bit Symbol Bit Name Function 0 Interrupt disabled SAIE SAI Interrupt Enable Bit 1 Interrupt enabled 0 Interrupt disabled SSIE SSI Interrupt Enable Bit 1 Interrupt enabled 0 SSI reception complete interrupt SSI Interrupt Select Bit 1 SSI transmit buffer empty interrupt No register bits should be written with O and read as undefined b23 b3 value Figure 7 2 ICRO Register Interrupt Control Register 1 pes bibis _ babr pi Symbol Address Reset Value ICR1 0001h 00 0000h SAI Interrupt Request Flag 0 No interrupt requested AIR 1 RW 1 1 Interrupt requested No register bits should be written with O and read as undefined b23 b3 value Note 1 This bit automatically becomes 0 once the DSP accepts an interrupt when the SAIE bit in the ICRO register is 1 interrupt enabled Do not set this bit to O by a program Although this bit becomes 1 when an interrupt is generated even when the SAIE bit is 0 interrupt disabled it
31. nd DSP Peripheral Function Registers 4 2 DSP Peripheral Function Registers Use the DSP peripheral function registers mapped in I O space to configure peripheral functions such as the audio interface and serial interface Table 4 2 lists the DSP peripheral function registers Refer to CoolFlux DSP Assembly Programmer s Manual or CoolFlux DSP C Programmer s Manual for details on accessing the I O space Table 4 2 DSP Peripheral Function Registers Address Register 0000h Interrupt Control Register 0 Symbol Reset Value 000000h 0001h Interrupt Control Register 1 000000h 0002h Interrupt Control Register 2 000000h 0007h DSP I O Register 000000h 0010h Audio Receive Buffer Register 0 L XXXXXXh 0011h Audio Receive Buffer Register 0 R XXXXXXh 0012h Audio Transmit Buffer Register 0 L 000000h 0013h Audio Transmit Buffer Register O R 000000h 0014h Audio Transmit Buffer Register 1 L 000000h 0015h Audio Transmit Buffer Register 1 R 000000h 0016h Audio Transmit Buffer Register 2 L 000000h 0017h Audio Transmit Buffer Register 2 R 000000h 0018h Audio Receive Buffer Register 1 L XXXXXXh 0019h Audio Receive Buffer Register 1 R XXXXXXh 0020h Serial Interface Setting Register 000000h 0022h Serial Control Register 000000h 0023h Transmit Buffer Register 0000XXh 0024h Serial Status Register 0000
32. nditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products
33. ng to the DAP control register PD10 i Bits in the PD10 register SFR Figure 8 3 Input Signal Flows RO1UHO208EJ0100 Rev 1 00 TENESAS Page 28 of 35 May 12 2011 R32C 102 Group General Purpose I O Ports 8 3 2 Output Setting Perform the following to set the general purpose I O ports to output and MCU port P10 to input 1 Set the corresponding bit in the PD10 register SFR to O input 2 Set the corresponding bits in registers DPC2 and DPC3 belonging to the DAP control register to 1 output 3 Set the corresponding bits in registers DPC7 and DPC8 belonging to the DAP control register to 1 output the general purpose I O port signal 4 Set the DPIE bit in the DICO register belonging to the DAP control register to 1 DP_0 to DP_7 signal input enabled only when reading the output data Make sure the corresponding bits of the both ports are not set to output at the same time Figure 8 4 shows an output signal flow according to the I O setting Digital audio processor DAP General purpose I O ports DPiD 1 DPjS 1 DSP_Pi output Port P10_i input PD10_ 0 DPIE 1 Pins P10_i DP_i i Oto 7 j 0 1 2 35 67 DPiD Bits in registers DPC2 and DPC3 belonging to the DAP control register DPjsS Bits in registers DPC7 and DPC8 belonging to DAP control register DPIE Bit in the DICO register belonging to the DAP control register PD10_i Bits in the PD10 register SFR Figure 8 4 Output Signal Flow
34. ommunications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use co
35. ords of 32 bits Data RAM 4 096 words of 24 bits e Coefficient RAM 512 words of 24 bits Boot ROM e Program RAM 3 072 words of 32 bits Data RAM 12 288 words of 24 bits e Coefficient RAM 1 792 words of 24 bits Audio Interface Input 2 channels Output 3 channels Synchronous Serial Interface 1 channel exclusively used for the communication with the CPU Interrupt Controller Interrupt sources 2 e SAI interrupt e SSI interrupt Select either the SSI transmit buffer empty interrupt or SSI reception complete interrupt General Purpose l O Port RO1UHO208EJ0100 Rev 1 00 May 12 2011 8 ports connected to MCU port P10 in a wired OR configuration TENESAS Page 1 of 35 R32C 102 Group Overview The DSP can access the program RAM data RAM coefficient RAM and DSP peripheral function registers The bootloader is stored in the boot ROM and transfers the DSP programs and data sent from the CPU to the RAMs In the serial audio interface SAI serial audio data input to the DAP is converted to DSP readable data The DSP processed data is converted to serial audio data Interrupt sources generated in the SAI and SSI are processed in the DAP s internal interrupt controller and the interrupt request signals are input to the DSP Digital audio processor DAP AOUTOL MCLK Stereo D A converter 0 AOUTOR AOUT1L BITCLK Stereo D A converter 1 AOUT1R Serial audio
36. pt enabled e Steps to set the SSI reception complete interrupt 1 Set the SSIE bit in the ICRO register to O interrupt disabled 2 Set the SIR bit in the ICR2 register to 0 no interrupt requested 3 Set the SSIS bit in the ICRO register to 0 SSI reception complete interrupt 4 Set the SSIE bit to 1 interrupt enabled e Steps to set the SSI transmit buffer empty interrupt 1 Set the SSIE bit in the ICRO register to O interrupt disabled 2 Set the SIR bit in the ICR2 register to 0 no interrupt requested 3 Set the SSIS bit in the ICRO register to 1 SSI transmit buffer empty interrupt 4 Set the SSIE bit to 1 interrupt enabled 7 3 2 Single Interrupt Figure 7 5 shows an operation example of when a single interrupt is generated DSP clock SAl interrupt source signal Interrupt request signal SAl IREQ Interrupt signal SAl INT Interrupt acknowledge signal SAl ACK H 2to 5 cycles of the DSP clock Figure 7 5 Operation Example of a Single Interrupt RO1UHO208EJ0100 Rev 1 00 TENESAS Page 24 of 35 May 12 2011 R32C 102 Group Interrupt Controller 7 3 3 Multiple Interrupts Figure 7 6 shows an operation example when multiple interrupts are generated SAI interrupt source signal SSI interrupt source signal Interrupt request signal SAI_IREQ Interrupt request signal SSI_IREQ SAI interrupt has a higher priority Interrupt signal SAI_INT Interrupt acknowledge signal SAI_ACK
37. r output direction of the general purpose I O ports Set the corresponding bits in registers DPC2 and DPC3 belonging to the DAP control register to 0 input 2 Setting input or output direction of MCU port P10 Inputting a signal from pins DP_0 to DP_7 to the general purpose l O ports Set the corresponding bit in the PD10 register SFR to O input e Inputting output data of the MCU port P10 to the general purpose I O ports Set the corresponding bit in the PD10 register SFR to 1 output 3 Enabling a signal input of pins DP_0 to DP_7 to the general purpose l O ports Set the DPE bit in the DICO register belonging to the DAP control register to 1 DP_0 to DP_7 signal input enabled Make sure that ports P10_0 to P10 7 and the corresponding ports DP 0 to DP_7 are not set to output at the same time Figure 8 3 shows input signal flows according to the I O setting e When inputting a signal from the P10_i pin to the general purpose I O ports Digital audio processor DAP General purpose I O ports DPiD 0 ae DPIE 1 DSP Pi input Port P10 i input PD10_i 0 Pins P10_i DP_i e When inputting the output data of the MCU port P10 ito the general purpose I O ports Digital audio processor DAP General purpose I O ports DPiD 0 on DPIE 1 DSP_Pi input Port P10_i output PD10 i 1 Pins P10 i DP i i 0to7 DPiD Bits in registers DPC2 and DPC3 belonging to the DAP control register DPIE Bit in the DICO register belongi
38. re that the code is 55h When the communication authorization code is not 55h reset the DSP again since the connection for the communication is not yet established Refer to 10 5 Communication Authorization Code and Checksum Reception for details on receiving the communication authorization code Refer to 10 3 DSP Program Transfer for details on transferring the DSP programs 10 3 DSP Program Transfer The MCU transfers the DSP programs in packet units After transmitting a data packet the MCU waits at least 1 6 us to receive a checksum This is repeated when transmitting multiple data packets 10 3 1 Data Packet A data packet consists of a packet header data length and transfer data Data is transferred in word units whose data length is either 32 bits or 24 bits The number of words which can be transferred per packet is limited Thus when that limit is exceeded the data needs to be divided into multiple packets to be transferred Refer to 10 3 1 2 Data Length for the number of transferable words per packet Figure 10 2 shows the data packet structure 1 packet A L A Packet header Data length n Transfer data 1 A Transfer data n 24 bits 24 bits 24 bits 32 bits 24 bits 32 bits Uu E Y 1 word k v n words n the number of the words of transfer data Figure 1022 Data Packet Structure RO1UHO208EJ0100 Rev 1 00 TENESAS Page 33 of 35 May 12 2011 R32C 102 Group Bootloader
39. t detect the timing of the LRCLK rising edge RO1UHO208EJ0100 Rev 1 00 TENESAS Page 12 of 35 May 12 2011 R32C 102 Group Synchronous Serial Interface 6 Synchronous Serial Interface 6 1 Overview The synchronous serial interface SSI is a DSP peripheral function to enable the communication between the CPU and the DSP It only supports synchronous serial communication and uses the DCLK transmit receive clock DTXD transmit data and DRXD receive data signal lines Table 6 1 lists the specifications and Figure 6 1 shows a block diagram of the synchronous serial interface Table 6 1 Specifications Item Specification Master slave MCU DSP Synchronous 3 wire serial DTXD Transmit data DRXD Receive data DCLK Transmit receive clock Character length 8 bits e Receive interrupt When data transferred from the receive shift register to lntemuiptgeneratngtimning the RBR register is completed e Transmit buffer empty interrupt When data transferred from the TBR register to the transmit shift register is completed Synchronous serial interface SSI SSI transmit buffer empty to interrupt controller RXD8 P11_2 Note 1 DTXD Transmit shift register TBR register CoolFlux DSP TXD8 P11_0 Note 1 DRXD Receive shift register RBR register CLK8 P11_1 Note 1 DCLK SSI receive completion to interrupt controller TE and RE Bits in the SCR register TSRE ORE TBRE
40. ter 0 O AOUTOR AINL DSPIS pots i RI AICTE Stereo D A O AOUTIL gt A1RTB j AOLRB AINR AORRB SDINO A1LRB A2LTB SDIN1 baw cba Stereo D A FO AOUT2L l A1RRB i p A2RTB converter 2 _ O AQUT2R O SDOUTO 24 O SDOUT1 O SDOUT2 CoolFlux DSP DSPIS Bit in the CDSC register belonging to the DAP control register AOLRB A1LRB AORRB and A1RRB Audio receive buffer registers AOLTB to A2LTB and AORTB to A2RTB Audio transmit buffer registers Figure 5 1 Block Diagram of the Serial Audio Interface and Peripherals Set bits FMT3 to FMTO in the AIFC register belonging to the DAP control register to select the data format and data length Figure 5 2 shows each format RO1UHO208EJ0100 Rev 1 00 TENESAS Page 7 of 35 May 12 2011 R32C 102 Group Serial Audio Interface e Left justified format a LRCLK SDIN SDOUT 20 bits SDIN SDOUT 24 bits e 12S format The figure above applies under the following condition When the BCKS bit in the AIFC register belonging to the DAP control register is O BITCLK is 64 fs Figure 5 2 Data Formats RO1UHO208EJ0100 Rev 1 00 TENESAS Page 8 of 35 May 12 2011 R32C 102 Group Serial Audio Interface 5 2 Registers 5 2 1 Audio Data Transmit Receive Buffer Registers The DSP inputs and outputs audio data via buffer registers Set bits FMT3 to FMTO in the AIFC register belonging to the DAP control register to select the data lengt
41. ting audio data 32 1 32 1 32 1 BITCLK j T j Ni J r a a J a d LRCLK R channel L channel R channel L channel R channel L channel SAI interrupt source signal s M yj JL B C A B LA B c A 1 Write enabled period apog CER Write enabled period to the AnRTB register RETAJ R data 2 R data 3 SDOUTn l L data 1 R data 1 L data 2 R data 2 X L data 3 The figure above applies under the following condition When the BCKS bit in the AIFC register belonging to the DAP control register is O BITCLK is 64 fs Note 1 Ais the period from the rising edge of the LRCLK signal until an SAl interrupt is generated 1 5 cycles of the BITCLK clock 1 to 2 cycles of the DSP clock B is the actual write enabled period for the transmit buffer 1 cycle of the LRCLK 2 cycles of the BITCLK 1 to 2 cycles of the DSP clock C is the write disabled period for the transmit buffer 0 5 cycles of the BITCLK clock Figure 5 9 Operation Example When Transmitting Audio Data in Left justified Format n 0 to 2 The audio data written to registers AnLTB and AnRTB is output as serial audio data at the next frame As shown in Figure 5 9 data should not be written to registers AnLTB and AnRTB during period C since itis a preparation period for the serial audio data to be output Although writing to registers AILTB and AiRTB is enabled during periods A and B write data during period B using the SAI interrupt since the DSP canno
42. tronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment c
43. ve Complete Flag anami Buffer Empty Flag 1 This bit can only be set to 0 It should not be set to 1 Figure 6 5 SSR Register Receive Buffer Register b23 b16b15 b8 b7 bO Symbo RBR I Address 0025h Address Synchronous Serial Interface Reset Value 00 0084h 0 Data held in the transmit shift register during transmission 1 No data in the transmit shift register transmission completed 0 No overrun error 1 Overrun error 0 No data in the RBR register 1 Data held in the RBR register 0 Data held in the TBR register 1 No data in the TBR register Reset Value 00 00XXh b7 b0 Received data RO b23 b8 No register bits should be written with O and read as O Figure 6 6 RBR Register RO1UHO208EJ0100 Rev 1 00 May 12 2011 TENESAS Page 16 of 35 R32C 102 Group Synchronous Serial Interface 6 3 Data Transmission and Reception 6 3 1 Data Transmission When data is set in the TBR register while the transmit shift register is empty the data is transferred to the transmit shift register and a transmission starts The double buffered structure of the transmit buffer register and transmit shift register enables continuous data transmission If the next transmit data has already been written to the TBR register when one character 8 bits of data has been transmitted the data is transferred to the transmit shift register and transmitted continuously Make sure that the T
44. y adding one packet of data packet headers data length and all transfer data together in 1 byte units The MCU should wait until a checksum calculation is completed 1 6 us before receiving a checksum Refer to 10 5 Communication Authorization Code and Checksum Reception for details on receiving a checksum RO1UHO208EJ0100 Rev 1 00 TENESAS Page 34 of 35 May 12 2011 R32C 102 Group Bootloader 104 Transmit Data Formats Data in a packet is transmitted from upper to lower bytes from the LSB There is no need to insert waits between bytes Figure 10 3 shows the transmit data format Middle byte Figure 10 3 Transmit Data Format Using 24 bit Data 10 5 Communication Authorization Code and Checksum Reception The MCU must generate clocks for one byte since synchronous serial communication whose master is the MCU is used to receive a communication authorization code and checksum The clock is generated when writing a dummy data to the transmit buffer The dummy data value must be 00h RO1UH0208EJ0100 Rev 1 00 TENESAS Page 35 of 35 May 12 2011 Revision History R32C 102 Group User s Manual DSP Description Page Summary May 12 2011 Initial release Rev Date R32C 102 Group User s Manual DSP Publication Date Rev 1 00 May 12 2011 Published by Renesas Electronics Corporation LENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com
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