the user manual for the SIO4BX2-SYNC
Contents
1. 15 2 16 FW TYPE ID REGISTER LOCAL OFFSET 0 15 2 17 FEATURES REGISTER LOCAL OFFSET OXOOFC c cccccccsessssecececeesesseseeecececseseeaeseeeeeesesseaesesececeeseaeeeeeeeesenea 15 CHAPTER 3 aee nn n RR XE SENE sse SES NETTES REVERSE NN nE REPE ee oe na USE nS SSES 17 3 1 SERIAL INTERFACE EET RS 17 3 1 1 SERIAL INTERFACE DEFINITION 17 3 1 2 TWO SIGNAL INTERFACE 2 22 41 00200 00000000000000000000000000000000 17 3 1 3 TX BIT COUNTS DX GAP i tese e eso eee cosa Par aes opt eee Vere 17 3 1 4 BIECOUNT 5p OR ve tients 18 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com iii Rev 0 General Standards Corporation High Performance Bus Interface Solutions 3 2 ize c CT 18 FIPO FLAGS RN RR E E 18 8 22 5 m 19 3 23 FIFO SYE2. 19 3 3 BOARD VS CHANNEL R OO TEA S a a 19 3 4 PROGRAMMABLE OSCILLATOR PROGRAMMABLE 8 19 3 5 MULTIPROTOCOL TRANSCEIVER 19 3 6 entree Ir O E E 20 3 7 LOOPBACK 8 E E E EA EE E EEEE E S 20 3 8 GENERAL PURPOSE IO reete tee teer E E EE EEEE OE OEE 21 3 9 P T A EA EAA E HQ 21 310 PCIDMA EDI 21 CHAPTER 4 PCIINTERFACE o 22 4 0 PCLINTEREACE REGISTERS EAEE AEAEE AE AE EAA 22 4 1 PCLREGISTBRS eI E EE EE EAE E A E EE E AE 22 4 1 1 PCI CONFIGURATION 5 5 22 4 1 2 LOCAL CONFIGURATION 5 5 23 4 1 3 RUNTIME REGISTERS 22 41 4 DNMEA REGISTEBS 55 eee rore reete eios ertet ite rib 23 4 1 4 1 DMA CHANNEL MODE REGISTER PCI 0x80 0X94 23 CHAPTER 5 HARDWARE CONFIGURATION eee ee eerta none e asses e sese s 24 5 0
3. er DPI IM 24 5 1 BOARD ID 7255555554 ERES 24 5 2 TERMINATION RESISTORS eene n en nen n n nenne 25 5 3 IMP 25 5 4 INTERFACE CONNECTOR 525 5 26 CHAPTER 6 ORDERING OPTIQNS 5iroiree eese eo toot nonae ea bp Poe en eae eis Een aen a e oup neas 27 6 0 ORDERING INFORMATION csc lt caecsscavevesseatevesssanevcave esee 27 6 1 INTEREACE Pe EE EE CY DE E 27 6 2 DEVICE RPEREN 27 6 3 5 8 22 004 27 APPENDIX PROGRAMMABLE OSCILLATOR 1 ete 28 APPENDIX FIRMWARE REVISIONS FEATURES REGISTER 31 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35
4. or OxOOAC CLOCK RAM2 The user simply sets the RAM Address register to the appropriate offset then reads or writes the the RAM data The Programmable Osc Control Status register allows the user to program the CY22393 or setup the clock post dividers The GSC Local Programmable Clock Registers are defined as follows 0x00A0 RAM Address Register Defines the internal CLOCK RAM address to read write 0x00A4 RAM Datal Register Provides access to the CLOCK pointed to by the RAM Addr Register 0x00A C RAM Data2 Register Provides access to the CLOCK RAM2 pointed to by the RAM Addr Register 0x00A8 Programmable Osc Control Status Register Provides control to write the contents of the CLOCK RAM to the CY22393 and setup additional post dividers for the input clocks Control Word Write Only DO Program Oscillator 1 Program contents of CLOCK RAM to 22393 Automatically resets to 0 D1 Measure Channel 1 Clock D2 Measure Channel 2 Clock D3 Measure Channel 3 Clock General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 28 Rev 0 General Standards Corporation High Performance Bus Interface Solutions D4 Measure Channel 4 Clock D5 Reserved Unused D6 Status Word Readback Control 0 gt Status Word D31 D8 Measured Channel Value 1 gt Status Word 031 08 Control Word D23 DO D
5. cccesssceccceceeseanceeececsesseaececcceceesenaesesececeessaeseseeseceseaeaeseeeesesssseaeseeseeenes 3 1 3 M L TIPROTOCOL TRANSCEIVERS iiss itio eetiecet ette epe 3 1 4 PMC PCT INTERFACE 4 1 5 GENERAL PURPOSE TO n 4 1 6 CONNECTOR INTERFACE 4 CHAPTER 2 LOCAL SPACE REGISTER cssscccssssscesssseccsssscccessscccsssscccesssscccesscescessacescssnecseessccessssscceessnes 5 2 0 GSC FIRMWARE LOCAL SPACE REGISTERS 4 44 000 040000 00000000 ener niente nes 5 2 1 FIRMWARE REVISION LOCAL OFFSET 0X0000 cccescccccecsesessscecececeesessesesecececeeseeseseeseeeseseaeseeeeseeesssaeseeees 6 2 2 BOARD CONTROL LOCAL OFFSET OX0004 ccccssssccccecsessssscecececsessaesecececeesesaseeeeeeceeseaaeceeeceeeeseaaseeseeeeeenes 6 2 3 BOARD STATUS LOCAL OFFSET OXOO08 ccccecsesseceeececeesssaececececeesenaesesececeessaaesececseceseaeseseesesessnsaeeeeseeenes 7 2 4 CHANNEL TX ALMOST FLAGS LOCAL OFFSET 0x0010 0x0020 0x0030 0 0040 8 2 5 CHANNEL ALMOST FLAGS LOCAL OFFSET 0 0014 0x0024 0x0034 0 0044 8 2 6 CHANNEL FIFO LOCAL OFFSET 0X0018 0x0028 0x0038 0 004
6. Data and Envelope change on the falling edge of the Clock The Data and Envelope signals are both Active Lo The Clock is still continuous Clock continues even when Data is Invalid TxC Idl Data is transmitted in 16 bit words TxCount with a one Clock gap TxGap in between each word Data Valid for 16 bits Invalid for 1 T agnNRRERSRSRERERSRERSRURERERURSRSERURERERERERER uu n Data Valid aes Data Valid L Data NRZ C Mile 0 Wa a T 0 4 0 b i n Ed a 0 0 0 OP ee ee Laer faa Data Valid 1 Data Valid NESS 2 P T Oo 1 o qv o Oo o T o 1 o o 1 Oo 1 T 1 1 fo TxCount 16 TxGap 1 Idl 0 Figure 1 2 Three Signal Serial Interface General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 2 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 1 11 2 Two Signal Serial Interface Figure 1 3 shows how the Clock can be used to qualify the Data to give a two signal serial interface In this case Data is considered valid at every Clock In this example Data is Active Hi and changes on the rising edge of the Clock The Clock is not present when Data is invalid TxC Idl Data is transmitted in 8 bit word
7. If an interrupt source is enabled in the Interrupt Control Register a 1 in Interrupt Status Register indicates the respective interrupt has occurred The interrupt source will remain latched until the interrupt is cleared either by writing to the Interrupt Status Clear Register with a 1 in the respective interrupt bit position or the interrupt is disabled in the Interrupt Control Register Clearing an interrupt which is not enabled or not asserted will have no effect 2 8 3 Interrupt Edge Level Local Offset 0x0068 The Interrupt Edge Register is an information only read only register This register can be used by a generic driver to determine if the interrupt source is edge or level triggered interrupt sources on SIO4BX2 SYNC are edge triggered 2 8 4 Interrupt Hi Lo Local Offset 0x006C The Interrupt Edge Register is an information only register which denotes all interrupt sources as edge triggered The Interrupt Hi Lo Register defines each interrupt source as rising edge or falling edge For example a rising edge of the TX Empty source will generate an interrupt when the TX FIFO becomes empty Defining the source as falling edge will trigger an interrupt when the TX FIFO becomes NOT Empty General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 11 Rev 0 General Standards Corporation High P
8. LOCAL SPACE REGISTERS 2 0 GSC Firmware Local Space Registers The PCIe SIOA4B X2 SYNC is accessed through two sets of registers PCI Registers and GSC Firmware Registers The GSC Firmware Registers referred to as Local Space Registers which provide the control status for the SIO4BX2 SYNC board are described below The PCI registers internal to the PLX 9056 PCI controller are discussed in Chapter 3 0 000 Reserved 00000000 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0 002 0 0030 0 0034 0 0038 0 003 0 0040 0 0044 0 0048 0 004 0 0050 0 005 RESERVED 0 0060 00000000 0 0064 00000000 0x0068 0 006 0x0070 0x007C RESERVED 0 0080 00000020 0 0084 00000020 0 0088 00000020 0 008 00000020 0 0090 000000XX General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 5 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 0 00 Ox00F0 0x00F4 RESERVED 24 Firmware Revision Local Offset 0 0000 The Firmware ID register provides version information about the firmware on the board This is useful for technical support to identify the firmware version D31 16 HW Board Rev OxE225 PCIe SIO4BX2 Rev E D15 8 Firmware Type ID 0x04 Sync Firmware D7 0 Firmw
9. This will allow the user feedback as to whether the programmable oscillator was programmed correctly To measure a clock select the clock to measure in the Control word and also clear Bit D6 to allow for readback of the result Read back the Status Word until D2 is set Status Word D31 D8 should contain a value representing 1 10 the measured clock frequency Value 10 2 Measured Frequency in MHz Keep in mind that this value will not be exactly the programmed frequency due to the 100ppm 0 0196 accuracy of the on board reference General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 29 Rev 0 General Standards Corporation High Performance Bus Interface Solutions The Internal RAM is defined as follows RAM Address 0x08 0x57 correspond directly to the CY22393 registers 0x00 0x05 Reserved Unused 0x00 0x06 Reserved OxD2 0x07 Reserved 0x08 0x08 Divisor Setup0 0x01 0x09 Divisor Setupl 0x01 Divisor Setup0 0 01 OxOB Divisor Setup1 0 01 ClkC Divisor 0 01 0 0 ClkD Divisor 0 01 OxOE Source Select 0x00 OxOF Bank Select 0x50 0x10 Drive Setting 0 55 Ox11 PLL2 Q 0x00 0x12 PLL2 P Lo 0x00 0x13 PLL2 Enable PLL2 P Hi
10. Ch3 Tx 011 Ch4 Rx 111 2 Ch4 Tx 23 Board Status Local Offset 0x0008 The Board Status Register gives general overall status for a board The Board Jumpers 01 00 are physical jumpers which can be used to distinguish between boards if multiple 5104 boards are present in a system D31 D9 D8 D7 D6 D5 D4 D3 D0 D3 D2 D1 DO RESERVED 0 Standard 1 Sync RESERVED FIFO Size 10 256K Board Jumper J2 Board ID4 02J2 7 J2 8 jumper installed Board ID3 02J2 5 J2 6 jumper installed Board ID2 02J2 3 J2 4 jumper installed Board 1 02J2 1 J2 2 jumper installed General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 7 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 2 4 Channel TX Almost Flags Local Offset 0x0010 0x0020 0x0030 0x0040 The Tx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered interrupt sources to the Interrupt Register D31 16 TX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more D15 0 TX Almost Empty Flag Value Number of words fro
11. Gather as well as Demand Mode Since many features of the PCI9056 are not utilized in this design it is beyond the scope of this document to duplicate the PCI9056 User s Manual Only those features which will clarify areas specific to the PCle SIO4BX2 are detailed here Please refer to the PCI9056 User s Manual See Related Publications for more detailed information Note that the BIOS configuration and software driver will handle most of the PCI9056 interface Unless the user is writing a device driver the details of this PCI Interface Chapter may be skipped 4 1 PCI Registers The PLX 9056 contains many registers many of which have no effect on the SIO4BX2 performance The following section attempts to filter the information from the PCI9056 manual to provide the necessary information for a SIO4BX2 specific driver The SIO4BX2 uses an on board serial EEPROM to initialize many of the PCI9056 registers after a PCI Reset This allows board specific information to be preconfigured correctly 4 1 4 PCI Configuration Registers The PCI Configuration Registers allow the PCI controller to identify and control the cards in a system PCI device identification is provided by the Vendor ID Device ID Addr 0x0000 and Sub Vendor ID Sub Device ID Registers 0x002C The following definitions are unique to the General Standards SIO4BX2 boards drivers should verify the ID Sub ID information before attaching to this card These val
12. for simple IO control of all the cable interface signals For outputs the output value is set using the appropriate field in the Pin Source Register inputs can be read via the Pin Status register Since TxAuxC and RxAuxC share a single pin the TxAuxC Src field in the Pin Source Register controls whether AuxC will function as an input or output If the field is set to Tri State the pin is set as RxAuxC Input Otherwise The TxAuxC output will be driven and the RxAuxC input will be equal to the TxAuxC output Likewise the TxSp Src field in the Pin Source Register controls the Spare pin direction If the field is set to Tri State RxSp will be an Input Otherwise RxSp will follow the TxSp output 3 9 Interrupts The PCIe SIO4B X2 SYNC has a number of interrupt sources which are passed to the host CPU via the PCI IRQA Since there is only one physical interrupt source for the board the interrupts pass through a number of levels to get multiplexed onto this single interrupt The interrupt originates in the PCI9056 PCI Bridge which combines the internal PLX interrupt sources DMA with the Local on board interrupt The single Local Interrupt is made up of the interrupt sources described in Section 2 8 The user should be aware that interrupts must be enabled at each level for an interrupt to occur For example if a FIFO interrupt is used it must be setup and enabled in the GSC Firmware Interrupt Control Register as well as ena
13. the key to providing four high speed serial channels without losing data Several features have been implemented to help in managing the on board FIFOs These include FIFO flags Empty Full Almost Empty and Almost Full presented as both real time status bits and interrupt sources and individual FIFO counters to determine the exact FIFO fill level DMA of data to from the FIFOs provides for fast and efficient data transfers A single memory address is used to access both transmit and receive FIFOs for each channel Data written to this memory location will be written to the transmit FIFO and data read from this location retrieves data from the receive FIFO Individual resets for the FIFOs are also provided in the Channel Control Status Register 3 2 1 FIFO Flags Four FIFO flags are present from each on board FIFO FIFO Empty FIFO Full FIFO Almost Empty and FIFO Almost Full These flags may be checked at any time from the Channel Control Status Register Note these flags are presented as active low signals 0 signifies condition is true The Empty and Full flags are asserted when the FIFO is empty or full respectively The Almost Empty and Almost Full flags are software programmable such that they may be asserted at any desired fill level This may be useful in determining when a data transfer is complete or to provide an indicator that the FIFO is in danger of overflowing and needs immediate service The Almost Flag value represents the numbe
14. to access these registers See Section 4 6 for more information 212 Tx Count Register Local Offset 0 00 0 0x00B4 0x00B8 D31 16 Gap Bit Count When transmitting these bits indicate the number of idle clocks between transmitted words To output a continuous stream of bits this value should be set to zero D15 0 Transmit Bit Count These bits indicate the number of consecutive bits to transmit for each transmit word 213 Rx Count Register Local Offset 0 00 0 0x00C4 0x00C8 0xCC D31 16 RESERVED D15 0 Receive Bit Count When receiving these bits indicate the number of consecutive bits received for the last received word 2 44 FIFO Count Register Local Offset 0x00D0 0x00D4 0x00D8 0x00DC The FIFO Count Registers display the current number of words in each FIFO This value along with the FIFO Size Registers may be used to determine the amount of data which can be safely transferred without over running or under running the FIFOs General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 14 Rev 0 General Standards Corporation High Performance Bus Interface Solutions D31 D16 Number of words in Rx FIFO D15 D0 Number of words in Tx FIFO 2 15 FIFO Size Register Local Offset 0 00 0 0x00E4 0 00 8 0x00EC The FIFO Size Registers display the sizes of the installed data FIFOs This v
15. to efficiently move data to and from the board 1 5 General Purpose IO Since some signals may not be used in all applications the SIO4BX2 provides the flexibility to remap unused signals to be used as general purpose IO For example this would allow support for an application requiring DTR DSR signals to be implemented on an unused DCD or TxAuxC signals This also allows signals from unused channels to be available as general purpose IO 1 6 Connector Interface The SIO4BX2 provides a user IO interface through a front side card edge connector four serial channels interface through this high density 68 pin SCSI 3 type connector and are grouped to simplify separating the cable into four distinct serial connectors Standard cables are available from General Standards in various lengths to adapt the single 68 pin SCSI 3 connector into four DB25 connectors one per channel A standard cable is also available with a single 68 pin SCSI 3 connector on one end and open on the other This allows the user to add a custom connector or connect to a terminal block General Standards will also work with customers to fabricate custom cables Consult factory for details on custom cables General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 4 Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 2
16. 0 653 9970 FAX 256 880 8788 Email salest generalstandards com 24 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 5 2 Termination Resistors The PCIe SIO4B X2 SYNC transceivers have built in termination resistors for the RS422 RS485 mode The built in RS422 RS485 termination is a 120 Ohm parallel termination If desired the internal termination resistors may be disabled by setting bit D30 in the Pin Source Register The board is designed with socketed external parallel termination if a different value than the internal termination is required The external termination resistors are 8 pin SIPs There are 8 termination SIPs RP1 RP4 RP7 RP10 The external parallel resistors are for RS422 RS485 termination only Refer to Figure 5 1 for resistor pack locations Please contact quotes generalstandards com if a different termination value is required 5 3 LEDs Five bicolor LEDs 01 05 are accessible via software Refer to Figure 5 1 for these LED locations LED D1 is controlled from the Board Control Register LED D1 Red is controlled by 025 and LED Green is controlled D24 The remaining 4 LEDs are controlled from D23 D20 of the four Channel Control Registers Each Channel Control Register controls 1 LED If D23 D22 10 the Red LED will turn off Likewise if D23 D22 11 the Red LED will turn on D21 D20 controls the Green LED in the pair LED D2 is controlled by Ch 4 LED D3 is control
17. 029 Receive Count Reset 1 Reset Receive Bit Counter General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 8 Rev 0 General Standards Corporation D28 D27 D26 D25 D24 D23 20 D19 High Performance Bus Interface Solutions Transmit MSB LSB 0 2 Transmit MSB first default 1 Transmit LSB first Receive MSB LSB 0 Receive MSB first default 1 Receive LSB first Stop Transmit On FIFO Empty 0 Transmitter remains enabled under software control D17 1 Transmitter will be disabled 025 0 if Tx FIFO becomes empty Transmit Enable 1 Transmitter enabled Note that cable transceiver direction should be set and transceivers enabled before the Transmit Enable is set Receive Enable 1 Receiver enabled Note that cable transceiver direction should be set and transceivers enabled before the Receive Enable is set LED Control Each Channel controls 2 LEDs on the back of the PCB See Section 5 3 for more detailed information about the LEDs Rx Stop on Full D18 8 Channel Status Bits D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 0 D7 D6 05 04 03 02 D1 DO Rx FIFO Underflow Tx FIFO Overflow Latched Rx FIFO Overflow Latched 1 Rx Data was lost due to Rx Overflow Note This bit is latched Write D16 1 to clear Rx FIFO Full Flag Lo 0 Rx FIFO Full Rx FIFO Almo
18. 0x00 0 14 PLL3Q 0x00 0 15 PLL3 P Lo 0x00 0x16 PLL3 Enable PLL3 P Hi 0x00 0 17 OSC Setting 0x00 Ox18 Reserved 0x00 0 19 Reserved 0x00 OxlA Reserved OxE9 Ox1B Reserved 0x08 Ox1C Ox3F Reserved Unused 0x00 0x40 Setup0 0x00 0x41 PLL1 P Lo 0 Setup0 0x00 0x41 PLL1 Enable PLL1 P Hi Setup0 0x00 0x43 PLL1 Setupl 0x00 0x44 P Lo 0 Setupl 0x00 0x45 PLL1 Enable PLL1 P Hi Setup1 0x00 0x46 PLL1 Setup2 0x00 0x47 P Lo 0 Setup2 0x00 0x48 PLL1 Enable PLL1 P Hi Setup2 0x00 0x49 Setup3 0x00 Ox4A P Lo 0 Setup3 0x00 Ox4B PLL1 Enable PLL1 P Hi Setup3 0x00 0 4 Setup4 0x00 Ox4D P Lo 0 Setup4 0x00 Ox4E PLL1 Enable PLL1 P Hi Setup4 0x00 Ox4F PLL1 Setup5 0x00 0x50 PLLI P Lo 0 Setup5 0x00 0x51 PLL1 Enable PLL1 P Hi Setup5 0x00 0x52 PLL1 Setup6 0x00 0x53 PLL1 P Lo 0 Setup6 0x00 0x54 PLL1 Enable PLL1 P Hi Setup6 0x00 0x55 PLL1 Setup 0x00 0x56 PLLI P Lo 0 Setup7 0x00 0x57 PLL1 Enable PLL1 P Hi Setup 0x00 0 58 Reserved Unused 0x00 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 30 Rev 0 General Standards Corporation High Performance Bus Interface Solutions APPENDIX B FIRMWARE REVISIONS FEATURES REGISTER Since 5104 boards can exist across multiple form factors and with various hardware features t
19. 4 TXD4 RXD4 TXC2 RXC2 Unused Hi TXC4 4 Unused Hi TXC2 RXC2 TXC2 TXC2 TXC4 RXC4 TXC4 SPARE2 Unused Hi 4 Unused Hi SPARE2 SPARE2 SPAREA SPAREA AUXC2 Unused Hi AUXC4 Unused Hi AUXC2 AUXC2 AUXC4 AUXC4 Table 1 Front Panel P2 IO Connections General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 26 Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 6 ORDERING OPTIONS 6 0 Ordering Information PCIe SIO4BX2 SYNC Temperature Option ValidSelections C to 70 C Commercial Standard 40 C to 85 C Industrial 6 1 Interface Cable General Standards Corporation can provide an interface cable for the PCIe SIO4BX2 SYNC board This standard cable is a twisted pair cable for increased noise immunity Several standard cable lengths are offered or the cable length can be custom ordered to the user s needs Versions of the cable are available with connectors on both ends or the cable may be ordered with a single connector to allow the user to adapt the other end for a specific application A standard cable is available which will breakout the serial channels into eight DB25 connectors Shielded cable
20. 7 Post divider set 0 Ignore D23 D8 during Command Word Write 1 Set Channel Post Dividers from D23 D8 during Command Word Write D11 D8 Channel Post Divider D15 D12 Channel 2 Post Divider D19 D16 Channel 3 Post Divider D23 D20 Channel 4 Post Divider D31 D24 Reserved Unused Status Word Read Only DO Program Oscillator Done 0 Oscillator Programming in progress Program Oscillator Error 1 Oscillator Programming Error has occurred D2 Clock Measurement complete 0 Clock Measurement in progress D7 D3 Reserved Unused D31 D8 If Command Word D6 0 Measured Channel Clock Value If Command Word D6 1 Control Word D23 D0 Channel Clock Post Dividers The Control Word defines 4 fields for Channel Clock Post dividers These post dividers will further divide down the input clock from the programmable oscillator to provide for slow baud rates Each 4 bit field will allow a post divider of 2 n For example if the post divider 0 the input clock is not post divided A value of 2 will provide a post divide of 4 2 2 This will allow for a post divide value of up to 32768 2415 for each input clock Bit D7 of the Control word qualifies writes to the post divide registers This allows other bits in the command register to be set while the post divide values are maintained Channel Clock Measurement The Control Word defines 4 bits which will select one of the 4 channel clocks input clock post divide for a measurement
21. 8 8 2 7 CHANNEL CONTROL STATUS LOCAL OFFSET 0x001C 0x002C 0x003C 0 004 8 2 8 INTERRUPT REGISTERS cccccecessessecesececeesesececececeesesseseseeccscsesaaecececeesesaaesesececeeeaaececececseseaeseeeeseeesenseaeeeeees 10 2 8 1 INTERRUPT CONTROL LOCAL OFFSET 0 0060 11 2 8 2 INTERRUPT STATUS CLEAR LOCAL OFFSET 0 0064 11 2 8 3 INTERRUPT EDGE LEVEL LOCAL OFFSET 0 0068 ccceccccceceesesssseeecececeesesaeceesceesesaaeeeeececeeseaaeseeeeeeeenes 11 2 8 4 INTERRUPT HI LO LOCAL OFFSET OXOO6C cc cccccccecsesscececececsesseseeecececsenseaeceeccecsesseaeseeececeenesaeseeeeeceene 11 2 9 CHANNEL PIN SOURCE LOCAL OFFSET 0x0080 0x0084 0x0088 0x008C 12 2 10 CHANNEL PIN STATUS LOCAL OFFSET 0 0090 0x0094 0x0098 0 009 14 2 11 PROGRAMMABLE CLOCK REGISTERS LOCAL OFFSET 4 14 2 12 TX COUNT REGISTER LOCAL OFFSET OXOOB4 OXOOB8 OXBC eene 14 2 13 RX COUNT REGISTER LOCAL OFFSET 0x00CA 0 00 8 OxCC essere 14 2 14 FIFO COUNT REGISTER LOCAL OFFSET 0 00 0 0 00 04 0 0008 0x00DC 14 2 15 FIFO SIZE REGISTER LOCAL OFFSET OXOOEA OxOOES
22. 802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com iv Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 1 INTRODUCTION 1 0 General Description The PCIe SIO4BX2 SYNC is four channel synchronous serial interface card which provides high speed full duplex multi protocol serial channels for PCIe applications The PCle SIO4BX2 SYNC combines a flexible serial interface deep external FIFOs and software selectable multi protocol transceivers to provide four fully independent synchronous serial channels These features along with a high performance one lane PCIe interface engine give PCIe SIO4BX2 SYNC unsurpassed performance in a synchronous serial interface card Chan 1 4 Sync Protocol Multi protocol 2 Controller Transceiver Cable Receiver lt Interface FIFO gt 4 68 SCSI LN 32kb o Transmitter a s P2 66MHz PCle PCI 32 bit PCIe Bus Bridge PCI Interface Osc Figure 1 1 Block Diagram of PCIe SIO4BX2 SYNC L4 Control Logic Features OneLane PCI Express PCIe Interface Four Independent Multi Protocol Synchronous Serial Channels Independent Transmit and Receive FIFOs for each Serial Channel 32K byte each Multi protocol Transceivers support RS422 RS485 RS232 Fast RS422 RS485 Differential Cable Trans
23. Bus Interface Solutions 36 DCE DTE Mode As all signals are bidirectional the DCE or DTE mode will set the direction for each signal For the transceivers to be configured as either DTE or set the DCE DTE Enable bit in the Pin Source register D31 The following table gives the input output configuration for each signal The DCD direction is set in the Pin Source register fields independent of DCE DTE mode TxC TxC Out RxC In RxC RxC In TxC Out TxD TxD Out RxD In RxD RxD In TxD Out TxE TxE RxE In RxE RxE In TxE AuxC Direction controlled by Pin Source Reg D10 9 Spare Direction controlled by Pin Source Reg D12 11 3 7 Loopback Modes For normal operation the Cable Transceiver Enable bit of the Pin Source Register will turn on the cable transceivers and the DTE DCE Mode bit will set the transceiver direction These bits must be set before any data is transmitted over the user interface Additionally there are several ways to loopback data to aid in debug operations Data may be physically looped back externally by connecting one channel to another For DB25 cable applications this simple loopback method will require a gender changer to connect one channel to another One channel will be set to DTE mode the other to DCE mode Data sent from one channel will be received on the other An External Loopback mode External Loopback bit set in the Pin Source Register is also provided to loop b
24. IFO The size of each FIFO is auto detected following a board reset Real time FIFO counters report the exact number of data words currently in each FIFO By utilizing this information the user can determine the exact amount of data which can safely be transferred to the transmit FIFOs or transferred from the receive FIFO This information should help streamline data transfers by eliminating the need to continuously check empty and full flags yet still allow larger data blocks to be transferred 32 3 FIFO Size Unlike previous 5104 boards which had ordering options for different FIFO sizes the PCle SIO4BX2 always uses 32k byte deep FIFOs 3 3 Board vs Channel Registers Since four serial channels are implemented on a single board some registers apply to the entire board while others are unique to each channel It is intended that each channel can act independently but the user must keep in mind that certain accesses will affect the entire board Typically the driver will adequately handle keeping board and channel interfaces separate However the user must also be mindful that direct access to certain registers will affect the entire board not just a specific channel The Board Control and Board Status registers provide board level controls Fundamentally a board reset will do just that reset all the GSC registers and FIFOs to their default state Interrupt control is also shared among all registers although local bits are segregated by c
25. PCle S5IOA4BX2 5 Y NC Hardware User s Manual Four Channel High Performance Serial I O PCIe Card Featuring RS422 RS485 RS232 Software Configurable Transceivers and 32K Byte FIFO Buffers 256K Byte total RS485 RS422 V 11 RS232 V 28 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail techsupport generalstandards com Rev 0 General Standards Corporation High Performance Bus Interface Solutions PREFACE Revision History 1 Rev 0 2013 Original rev from PMC66 SIO4BXR SYNC manual Additional copies of this manual or other General Standards Corporation literature may be obtained from General Standards Corporation 8302A Whitesburg Drive Huntsville Alabama 35802 Telephone 256 880 8787 Fax 256 880 8788 URL www generalstandards com The information in this document is subject to change without notice General Standards Corporation makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corporation assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporatio
26. XEI 1 TXEI RXE3 TXE3 RXE3 TXE3 RXD1 TXD1 Unused Hi TXD3 Unused Hi RXDI TXDI RXDI TXDI RXD3 TXD3 RXD3 TXD3 Unused Hi RXC3 TXC3 Unused Hi RXCI TXCI RXCI TXCI RXC3 TXC3 RXC3 TXC3 Unused Hi TXE3 RXE3 Unused Hi TXEI RXEI TXEI RXEI TXE3 RXE3 TXE3 RXE3 w 1 RXDI Unused Hi TXD3 RXD3 Unused Hi A TXDI RXDI TXDI RXDI TXD3 RXD3 TXD3 RXD3 Em Unused Hi TXC3 RXC3 Unused Hi m TXCI RXCI TXCI RXCI TXC3 RXC3 TXC3 RXC3 17 SGNDI SGND2 SGNDI SGND2 SGND3 SGND4 SGND3 SGND4 RXE2 TXE2 Unused Hi RXE4 TXE4 Unused Hi RXE2 TXE2 RXE2 TXE2 RXE4 TXE4 RXE4 TXE4 RXD2 TXD2 Unused Hi RXD4 TXD4 Unused Hi RXD2 TXD2 RXD2 TXD2 RXD4 TXD4 RXD4 TXD4 RXC2 TXC2 Unused Hi RXC4 TXC4 Unused Hi RXC2 TXC2 RXC2 TXC2 RXC4 TXC4 TXC4 2 RXE2 Unused Hi TXE4 RXE4 Unused Hi TXE2 RXE2 TXE2 RXE2 TXE4 RXE4 TXE4 RXE4 TXD2 RXD2 Unused Hi TXD4 RXD4 Unused Hi TXD2 RXD2 TXD2 RXD2 4 RXD
27. ace to be further customized with the following user configurable options Clocking Data on either rising or falling edge of the clock Active Hi or Active Lo polarity for the Envelope Signal NRZ Level or NRZB Inverted Level Data Encoding Continuous Transmit Clock or Transmit Clock disabled when Data is invalid Clock present only for valid Data Transmit Word Size may be configured from 1 to 64k bits consecutive bit count Transmit Gap Size number of clocks between transmit words may be configured from 0 to 64k bits Data may be transmitted MSB first or LSB first 8 bit or less word size Transmit Clock may be configured from 10MHz down to 400Hz on a per channel basis Auxiliary Clock Input from cable may be used as Transmit Clock The following sections show some typical examples of how the SIO4BX2 SYNC can be configured to support different two and three signal interfaces 1 1 1 Three Signal Serial Interface Figure 1 2 shows two examples of typical 3 signal interfaces The two diagrams show how the card can be configured to handle different interface requirements For the top diagram Data and Envelope change on the rising edge of the Clock The Data and Envelope are both Active Hi The Clock is continuous e g the Clock continues even when Data is Invalid TxC Idl Data is transmitted in 8 bit words TxCount with a two Clock gap TxGap in between each word Data Valid for 8 bits Invalid for 2 In the lower example
28. ack data on the same channel without requiring any external cabling In this mode the DTE DCE mode will control the location for the transmit signals TxC TXD and the receive signals will use these same signals as the receive inputs Since signals are transmitted and received through the transceivers this mode allows the setup to be verified including signal polarity without any external connections Since external signals could interfere with loopback operation all cables should be disconnected when running in external loopback mode An Internal Loopback Mode is also provided which loops back on the same channel internal to the board This provides a loopback method which does not depend on DTE DCE mode or signal polarity This can remove cable transceiver and signal setup issues to aid in debugging If the Cable Transceivers are enabled the transmit data will still appear on the appropriate transmit pins based on DTE DCE Mode setting The Pin Status register will not reflect internally looped back signals only signals to from the transceivers General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 20 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 3 8 General Purpose IO Unused signals at the cable may be used for general purpose IO The Pin Source and Pin Status Registers provide
29. alue is calculated at power up This value along with the FIFO Count Registers may be used to determine the amount of data which can be safely transferred without over running or under running the FIFOs D31 D16 Size of installed Rx FIFO D15 D0 Size of installed Tx FIFO 2 6 FW Type ID Register Local Offset 0x00F8 This register allows boards to be designed with different functionality on each channel For example a board could contain two Standard SIO channels with Z16C30 and two Raw Synchronous channels Each byte corresponds to a channel This register is read only it reflects the implemented logic D31 D24 Channel 4 FW Type 04 Sync D23 D16 Channel 3 FW Type 04 Sync D15 D8 Channel 2 FW Type 04 Sync D7 D0 Channel 1 FW Type 04 Sync 2 17 Features Register Local Offset 0 00 The Features Register allows software to account for added features in the firmware versions Bits will be assigned as new features are added See Appendix B for more details D31 23 RESERVED D22 1 Rx Stop on Full in Ch Ctrl D21 1 SRAM Debug D20 1 No Rx Status byte std only D19 D18 10 Internal Timestamp std only D17 D16 01 FPGA Reprogram field D15 D14 01 Configurable FIFO space D13 1 FIFO Test Bit D12 1 FW Type Reg D11 8 Features Rev Level BX level D7 1 Demand Mode DMA Single Cycle Disable feature implemented D6 1 Board Reset D5 1 FIFO Counters Size D4 1 D3 0 Programmable Clock Configura
30. are Revision XX Firmware Version 2 2 Board Control Local Offset 0x0004 The Board Control Register defines the general control functions for the board The main function in this register defines the Demand mode DMA channel requests D31 Board Reset 1 Reset all Local Registers and FIFOs to their default values Notes This bit will automatically clear to 0 following the board reset Board Reset will NOT reset programmable oscillator Following a Board Reset ResetInProgress bit D31 of the Board Status Register will remain set until the Board reset is complete D30 RESERVED Debug Test 029 RESERVED FIFO Test D28 27 RESERVED FIFO Configuration D26 RESERVED D25 LED D1 Red D24 LED D1 Green D23 9 RESERVED General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 6 Rev 0 General Standards Corporation High Performance Bus Interface Solutions D8 D7 D6 4 D3 D2 0 Rx FIFO Stop on Full 1 If Rx FIFO becomes full stop receiving data disable receiver Demand Mode DMA Channel 1 Single Cycle Disable Demand Mode DMA Channel 1 Request 000 Rx 100 Chl Tx 010 Ch2 Rx 110 Ch2 Tx 001 Ch3 Rx 101 2 Ch3 Tx 011 Ch4 Rx 111 2 Ch4 Tx Demand Mode DMA Channel 0 Single Cycle Disable Demand Mode DMA Channel 0 Request 000 Chl Rx 100 Chl Tx 010 Ch2 Rx 110 2 Ch2 Tx 001 Ch3 Rx 101 2
31. bled in the PCI9056 In addition the interrupt must be acknowledged and or cleared at each level following the interrupt The driver will typically take care of setting up and handling the PCI9056 interrupts as well as most local interrupts The specific driver manual should have more information on how to handle these interrupts 310 PCI The PCI DMA functionality allows data to be transferred between host memory and the SIO4BX2 onboard FIFOs with the least amount of CPU overhead The PCI9056 bridge chip handles all PCI DMA functions and the device driver should handle the details of the DMA transfer Note DMA refers to the transfer of Data from the on board FIFOs over the PCI bus This should not be confused with the DMA mode of the USC transfer of data between the USC and the on board FIFOs This On Board DMA is setup by the driver and should always be enabled There are two PCI DMA modes Demand Mode DMA and Non Demand Mode DMA Demand Mode DMA refers to data being transferred on demand For receive this means data will be transferred as soon as it is received into the FIFO Likewise for transmit data will be transferred to the FIFOs as long as the FIFO is not full The disadvantage to Demand Mode DMA is that the DMA transfers are dependent on the user data interface If the user data transfer is incomplete the Demand mode DMA transfer will also stop If a timeout occurs there is no way to determine the exact amount of data transfer
32. ceivers Provide Data Rates up to 10Mbps RS232 Cable Transceivers Provide Data Rates up to 250kbps Two Signal Clock Data or Three Signal modes Clock Data Data Valid e Programmable Oscillators provide increased flexibility for Baud Rate Clock generation e Programmable Transmit Bit Counts allow for various transmit word lengths e Programmable Transmit Gap Bit Counts allow for variable gap between words Fully Programmable Polarity on all signals Fight signals per channel configurable as either DTE or DCE 3 Serial Clocks TxC RxC AuxC 2 Serial Data TxD RxD 2 Data Valid TXE RxE plus Spare e Unused signals may be reconfigured as General Purpose IO e SCSI type 68 pin front edge I O Connector e Standard Cable to four DB25 connectors and Custom Cables available e Interchangeable 1200 Termination Resistors RS422 RS485 Mode e Available drivers include VxWorks WinNT Win2k WinXP Linux and Labview e Industrial Temperature Option Available General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 1 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 1 1 Serial Interface The simple synchronous interface may be configured as a three signal interface Clock Data and Envelope Data Valid or an even simpler two signal interface Clock and Data The SIO4BX2 SYNC allows the serial interf
33. d for each mode D27 24 Transceiver Protocol Mode 0 0 0 0 RS422 RS485 0 0 1 0 RS232 0 0 X 1 RESERVED 0 1 X X RESERVED 1 X X X RESERVED D23 Int LB 0 Normal Mode 1 Internal Loopback TxC TxD TxE looped back internally D22 21 RESERVED D20 TxC Idl 0 TxC driven low 0 while Idle Envelope Negated 1 TxC driven high 1 while Idle Envelope Negated D19 TxD Idi 0 TxD driven low 0 while Idle Envelope Negated General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 12 Rev 0 General Standards Corporation High Performance Bus Interface Solutions D18 17 D16 D15 14 D13 D12 11 D10 9 D8 6 D3 D2 0 RESERVED RxD Src RxE Src Sre TxSp Src TxAuxC Src TxD Src TxE Src TxC Idl TxC Src 1 00 0X0 0X1 1X0 1X1 000 001 010 011 1X0 1X1 TxD driven high 1 while Idle Envelope Negated RxD Active Hi NRZ RxD Active Lo NRZB RxE Active Hi RxE Active Lo RxE Disabled Sample Data on Falling Edge of Clock Data Change on Rising Sample Data on Rising Edge of Clock Data Change on Falling Disabled Input 0 1 y Tri State ProgClk 2 0 1 TxD Active Hi NRZ TxD Active Lo NRZB 0 1 1 Active Hi TxE Active Lo 0 1 y TxC driven while Idle Envelope Negated No TxC while Idle Enve
34. erformance Bus Interface Solutions 2 9 Channel Pin Source Local Offset 0x0080 0x0084 0x0088 0x008C The Channel Pin Source Register configures the function of the cable interface signals as well as controls the transceiver protocols 31 30 29 28 27 26 25 24 Cable x Ext Loopback DCE DTE Transceiver Protocol Mode Enable Enable Mode 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 Int XXX TxD RxD RxE RxC TxSp TxAuxC TxD TxE TxC TxC LB Idl Src Src Sre Sre Src Src Src Idi Src Pin Source Register D31 Cable Transceiver Enable Setting this bit turns on the cable transceivers If this bit is cleared the transceivers are tristated D30 Termination Disable 029 External Loopback Mode When Cable Transceiver is enabled Bit D31 this bit will automatically loopback the TxC RxC TxD RxD and TxE RxE signals at the cable transceivers enabled Notes The DCE DTE mode will select the set of signals DCE or DTE to be looped back e Since the transceivers will be enabled in this mode all external cables should be disconnected to prevent interference from external sources D28 DCE DTE Mode This bit sets up the transceiver direction Setting the mode to 1 will enable DCE mode while 0 will set DTE mode default See Section 5 3 for a detail of the signal direction as define
35. ess to complete FIFO status to optimize data transfers In addition to Empty and Full indicators each FIFO has a programmable Almost Empty Flag and a programmable Almost Full Flag These FIFO flags may be used as interrupt sources to monitor FIFO fill levels In addition real time FIFO counters showing the exact number of words in the FIFO are also provided for each FIFO By utilizing these FIFO counters data transfers can be optimized to efficiently send and receive data 1 3 Multiprotocol Transceivers The SIO4BX2 data is transferred over the user interface using high speed multiprotocol transceivers These multiprotocol transceivers are software selectable as RS422 RS485 or RS232 on a per channel basis Each channel direction may also be configured as DTE or DCE configuration This allows for either full duplex or half duplex configurations General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 3 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 1 4 PCIe Interface The control interface to SIO4BX2 SYNC is through a one channel PCIe interface An industry standard bridge chip from PLX Technology is used to implement PCIe Specification 1 1 The PEX8311 provides a one lane 250MBit sec interface between the PCIe bus and the Local 32 bit bus It also provides for high speed DMA transfers
36. h2 RxE Rising Edge Falling Edge 5 Ch2 Tx FIFO Almost Empty Rising Edge Falling Edge IRQ6 Ch2 Rx FIFO Almost Full Rising Edge Falling Edge IRQ7 Ch2 RxSp Rising Edge Falling Edge IRQ8 Ch3 RxE Rising Edge Falling Edge IRQ9 Ch3 Tx FIFO Almost Empty Rising Edge Falling Edge IRQIO Ch3 Rx FIFO Almost Full Rising Edge Falling Edge Ch3 RxSp Rising Edge Falling Edge IRQI2 Ch4 RxE Rising Edge Falling Edge IRQI3 Ch4 Tx FIFO Almost Empty Rising Edge Falling Edge IRQ14 Ch4 Rx FIFO Almost Full Rising Edge Falling Edge 15 Ch4 Rising Edge Falling Edge 16 Chl Tx FIFO Empty Rising Edge Falling Edge IRQI7 Chl Tx FIFO Full Rising Edge Falling Edge 18 Chl Rx FIFO Empty Rising Edge Falling Edge 19 Chl Rx FIFO Full Rising Edge Falling Edge IRQ20 Ch2 Tx FIFO Empty Rising Edge Falling Edge IRQ21 Ch2 Tx FIFO Full Rising Edge Falling Edge IRQ22 Ch2 Rx FIFO Empty Rising Edge Falling Edge IRQ23 Ch2 Rx FIFO Full Rising Edge Falling Edge IRQ24 Ch3 Tx FIFO Empty Rising Edge Falling Edge IRQ25 Ch3 Tx FIFO Full Rising Edge Falling Edge IRQ26 Ch3 Rx FIFO Empty Rising Edge Falling Edge IRQ27 Ch3 Rx FIFO Full Rising Edge Falling Edge IRQ28 Ch4 Tx FIFO Empty Rising Edge Falling Edge IRQ29 Ch4 Tx FIFO Full Rising Edge Falling Edge IRQ30 Ch4 Rx FIFO Empty Rising Edge Falling Edge IRQ31 Ch4 Rx FIFO Full Rising Edge Falling Edge For all interrupt registers the IRQ source IRQ31 IRQO will correspond to the respective data bi
37. hannel The device driver should take care of appropriately handling the inter mixed channel interrupts and pass them on to the application appropriately 34 Programmable Oscillator Programmable Clocks The On Board Programmable Oscillator provides each channel with a unique programmable clock source using a Cypress Semiconductor CY22393 Programmable Clock generator In order to program the oscillator it is necessary to calculate and program values for different clock frequencies General Standards has developed routines to calculate the necessary values for a given setup and program the clock generator These clock setup routines have been incorporated into most of the drivers The default clock configuration at power up for the programmable clock on all channels is 20MHz See Appendix A for more detailed information concerning programming the on board clock frequencies as well as common frequency setups The specific driver manual should have information on clock setup If not please contact GSC tech support for assistance 3 5 Multiprotocol Transceiver Control The SIO4BX2 SYNC has multiprotocol transceivers which allow RS422 RS485 or RS232 The mode is set by the Protocol Mode field in the Pin Source Register General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 19 Rev 0 General Standards Corporation High Performance
38. he firmware features registers attempt to help identify the exact version of a SIO4 board This appendix provides a more detailed breakdown of what the firmware and features registers and detail differences between the firmware revisions Firmware Register Local Offset 0x00 0xE5100400 D31 16 HW Board Rev 0 510 PCIe SIO4BX2 Rev NR D31 D30 D29 028 D27 D24 D23 D20 D19 D16 1 Features Register Present 1 Complies with this standard 1 66MHz PCI bus interface 0 33MHz PCI bus interface 1 64 bit PCI bus interface 0 32 bit bus interface Form Factor 0 Reserved 1 PCI 2 3 4 104 5 PCIe 6 XMC HW Board sub field of form factor 0 PCIe4 SIO8BX2 1 PCIe SIO4BX2 HW Board Rev lowest rev for firmware version 0 NR D15 8 Firmware Type ID 0 01 Std Firmware default 0x04 Sync Firmware default D7 0 Firmware Revision XX Firmware Version 0x00 Initial release from PMC66 SIO4BXR v417 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 31 Rev 0 General Standards Corporation High Performance Bus Interface Solutions Feature Register Local Offset 0x00197AF4 D31 23 RESERVED D22 1 Rx Stop on Full in Ch Ctrl D21 1 SRAM Debug D20 1 No Rx Status byte std only D19 D18 Timestamp 01 single external clock 10 single internal cl
39. led by Ch 3 LED D4 is controlled by Ch 2 LED D5 is controlled by Ch 1 Additionally if all the LED controls are set to 0 in all four of the Channel Control Registers power up default the LEDs will display the lower 4 bits of the firmware revision in Green LED D2 to LED D5 LED D6 displays the PCIe link status It will be green for No Link and off when the PCIe link is established The remaining LED D7 displays the firmware status This LED should flash at power up or after a PCIe reset then it will turn off The LED should be off during normal operation General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 25 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 5 4 Interface Connector User I O Connector Part Number Mating Connector 68 pin SCSI connector female P2 AMP TYCO 787170 7 AMP TYCO 749111 6 or equivalent Pin 34 Pin 1 o Pin 68 Note 5422 5485 mode or RS232 mode is set on a per channel basis Pin 35 CREE ee CNN a DTE DCE DTE MUT Hi AUXO S AUXCI AUXCI AUXC3 AUXC3 SPAREI Unused Hi SPARE3 Unused Hi SPAREI SPAREI SPARE3 SPARE3 Unused Hi RXE3 Unused Hi R
40. lope Negated Clock Data on Rising Edge of Internal Programmable Clock 2 Data Envelope change on rising edge Clock Data on Falling Edge of Internal Programmable Clock 2 Data Envelope change on falling edge Clock Data on Rising Edge of External Clock Data Envelope change on rising edge Clock Data on Falling Edge of External Clock Data Envelope change on falling edge 0 1 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 13 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 2 10 Channel Pin Status Local Offset 0x0090 0x0094 0x0098 0x009C In addition to standard inputs unused inputs may be utilized as general purpose input signals The Channel Pin Status Register allows the input state of all the IO pins to be monitored Output signals as well as inputs are included to aid in debug operation D31 D10 RESERVED D9 TxSp Output D8 RxSp Input D7 TxAuxC Output D6 TxE Output D5 TxD Output D4 TxC Output D3 RxAuxC Input D2 RxE Input D1 RxD Input DO RxC Input 211 Programmable Clock Registers Local Offset 0x00A0 0x00A4 0x00A8 The Programmable Clock Registers allow the user to program the on board programmable oscillator and configure the channel clock post dividers As GSC should provide software routines to program the clock the user should have no need
41. m FIFO Empty when the Almost Empty Flag will be asserted 2 5 Channel Rx Almost Flags Local Offset 0x0014 0x0024 0x0034 0x0044 The Rx Almost Flag Registers are used to set the Almost Full and Almost Empty Flags for the transmit FIFOs The Almost Full Empty Flags may be read as status bits in the Channel Control Status Register and are also edge triggered interrupt sources to the Interrupt Register D31 16 RX Almost Full Flag Value Number of words from FIFO Full when the Almost Full Flag will be asserted i e FIFO contains FIFO Size Almost Full Value words or more D15 0 RX Almost Empty Flag Value Number of words from FIFO Empty when the Almost Empty Flag will be asserted 2 6 Channel FIFO Local Offset 0x0018 0 0028 0x0038 0x0048 The Channel FIFO Register passes serial data to from the serial controller The same register is used to access both the Transmit FIFO writes and Receive FIFO reads D31 8 RESERVED D7 0 Channel FIFO Data 2 7 Channel Control Status Local Offset 0x001C 0x002C 0x003C 0x004C The Channel Control Status Register provides the reset functions and data transceiver enable controls and the FIFO Flag status for each channel D31 RESERVED D30 24 Channel Control Bits D30 Receive Gap Enable 0 D24 Receiver Enable controls when data reception starts 1 Data reception will begin when D24 1 and RxE is negated This waits for a gap in the data stream before data reception begins
42. mplete a gap will be inserted Therefore if the TxCount is greater than 8 bits some data should be preloaded into the TxFIFO before the transmit is enabled This will ensure a continuous data stream of the correct length For a continuous data stream the TxCount should be set to 8 and TxGap to 0 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 17 Rev 0 General Standards Corporation High Performance Bus Interface Solutions Certain TxCount TxGap combinations may not work correctly in a very few instances In general a data word cannot be transmitted or received faster than 500ns per byte If the TxCount TxGap and serial data rate result in a throughput rate of greater than 1 byte in 500ns correct operation cannot be guaranteed If an application requires such an interface please contact GSC tech support to determine if the board will work for your application 3 1 4 Rx Bit Count The Rx Bit Count is primarily a debug feature to check that the expected number of bits in a frame were received The Rx Bit Count will simply count received bits in the current frame It will reset at the beginning of each frame based on RxE or may be reset via the Rx Bit Count Reset bit of the Channel Control Register For a two signal interface this register will count all bits received 32 FIFOs Deep transmit and receive FIFOs are
43. n does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent right of any rights of others General Standards Corporation assumes no responsibility resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corporation reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No parts of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corporation Copyright 2013 General Standards Corporation General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 800 653 9970 FAX 256 880 8788 Email salest generalstandards com i Rev 0 General Standards Corporation High Performance Bus Interface Solutions RELATED PUBLICATIONS PLX PEX8311AA Data Book PLX Technology Inc 390 Potrero Avenue Sunnyvale CA 4085 408 774 3735 http www plxtech com EIA 422 A Electrical Characteristics of Balanced Voltage Digital Interface Circuits EIA order number EIA 422A EIA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number EIA 485 EIA Standards and Publications can be purcha
44. ock D17 D16 FPGA Reprogram field 01 Present 00 Not Present D15 D14 Configurable FIFO space 01 Rx Tx select Up to 32k deep FIFOs D13 1 FIFO Test Bit D12 1 FW Type Reg D11 D8 FW Feature Level Set at common code level 0x01 RS232 support Pin Source Change 0x02 Multi Protocol support 0x03 Common Internal External FIFO Support 0x04 FIFO Latched Underrun Overrun Level 0x05 Demand mode DMA Single Cycle for Tx 0x06 DMA Single Cycle Dis updated Pin Src 0x07 Rx Underrun Only Reset Status 0x08 Clock to 50Hz with 10Hz resolution 0x09 No Legacy Support No Clock Control Register 0x0A Falling Int fix D7 1 DMA Single Cycle Disable D6 1 Board Reset FIFO present bits D5 1 FIFO Size Counters present D4 1 FW ID complies with this standard 03 00 Clock Oscillator 0x0 Fixed 0x1 ICD2053B 1 Osc 0x2 ICD2053B 4 Osc 0x3 CY22393 4 Osc 0 4 2 x CY22393 6 Osc General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 32 Rev 0
45. on the SIO4BX2 other Runtime Registers initialize to the default values described in the PCI9056 Manual 4 1 4 DMA Registers The Local DMA registers are used to setup the DMA transfers to and from the on board FIFOs DMA is supported only to the four FIFO locations The SIO4BX2 supports both Demand DREQ controlled and Non Demand mode DMA Both Channel 0 and Channel 1 DMA are supported 4 1 4 1 DMA Channel Mode Register PCI 0x80 0x94 The DMA Channel Mode register must be setup to match the hardware implementation Bit Description Value Notes D1 0 Local Bus Width 11 32 bit Although the serial FIFOs only contain 8 bits of 00 8 bit data the register access is still a 32bit access It is possible to pack the data by setting the Local Bus Width to 8 but this is only guaranteed to work with Non Demand Mode DMA 05 2 Internal Wait States 0000 Unused D6 Ready Input Enable 1 Enabled D7 Bterm Input Enabled 0 Unused D8 Local Burst Enable 1 Supported Bursting allows fast back to back accesses to the FIFOs to speed throughput D9 Chaining Enable Scatter X DMA source addr destination addr and byte Gather DMA count are loaded from memory in PCI Space D10 Done Interrupt Enable X DMA Done Interrupt D11 Local Addressing Mode 1 No Increment DMA to from FIFOs only D12 Demand Mode Enable X Demand Mode DMA is supported for FIFO accesses on the SIO4BXR See Section 3 3 D13 Wri
46. options are also available Please consult our sales department for more information on cabling options and pricing 6 2 Device Drivers General Standards has developed many device drivers for The SIO4BX2 boards including VxWorks Windows Linux and LabView As new drivers are always being added please consult our website www generalstandards com or consult our sales department for a complete list of available drivers and pricing 6 3 Custom Applications Although the PCIe SIO4BX2 SYNC board provides extensive flexibility to accommodate most user applications user application may require modifications to conform to a specialized user interface General Standards Corporation has worked with many customers to provide customized versions based on the SIO4B X2 boards Please consult our sales department with your specifications to inquire about a custom application General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 27 Rev 0 General Standards Corporation High Performance Bus Interface Solutions APPENDIX A PROGRAMMABLE OSCILLATOR PROGRAMMING The 4 on baord clock frequencies are supplies via two Cypress Semiconductor CY22393 Programmable Clock Generatosr In order to change the clock frequencies this chip must be reprogrammed This document supplies the information necessary to reprogram the on board clock frequencie
47. put General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 16 Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 3 PROGRAMMING 3 1 Serial Interface 3 1 1 Serial Interface Definition The Pin Source Register contains information which defines the physical serial interface This register contains fields to setup the polarity of the TxC RxC TxD RxD TxE and RxE signals As these signals are all individually configurable it is possible to setup the Receive channel differently than Transmit channel In addition the TxD Idle field defines the state of the TxD signal while idling not sending data The MSB LSB for both transmit and receive is setup in the Channel Control Status register Note that this acts only upon the current byte MSB will send receive bit D7 first LSB will send receive DO first For word lengths of other than 8 bits the word should be right left justified accordingly Since the MSB LSB only acts upon 8 bits if the bit length is greater than 8 bits the bits will only be reversed on a byte by byte basis The user may need to rearrange bytes for bit lengths greater than 8 bits 3 1 2 Two Signal Interface A two signal interface is a special setup case of the three signal serial interface In a three signal interface an envelope signal defines when data i
48. r of bytes from each respective end of the FIFO The Almost Empty value represents the number of bytes from empty and the Almost Full value represents the number of bytes from full NOT the number of bytes from empty For example the default value of 0x0007 0007 in the FIFO Almost Register means that the Almost Empty Flag will indicate when the FIFO holds 7 bytes or fewer It will transition as the 8 byte is read or written In this example the Almost Full Flag will indicate that the FIFO contains FIFO Size 7 bytes or more For the standard 32Kbyte FIFO an Almost Full value of 7 will cause the Almost Full flag to be asserted when the FIFO contains 32761 32k 7 or more bytes of data The values placed in the FIFO Almost Registers take effect immediately but should be set while the FIFO is empty or the FIFO should be reset following the change Note that this is different than the method for FIFO Flag programming which has previously been implemented on 51 4 boards No FIFO programming delay is necessary General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 18 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 3 2 2 FIFO Counters The FIFO Size and FIFO count registers can be used to determine the exact amount of data in a FIFO as well as the amount of free space remaining in a F
49. red before it was aborted Non Demand Mode DMA does not check the FIFO empty full flags before or during the data transfer it simply assumes there is enough available FIFO space to complete the transfer If the transfer size is larger than the available data the transfer will complete with invalid results This is the preferred mode for DMA operation The FIFO Counters may be used to determine how much space is available for DMA so that the FIFO will never over under run Demand Mode DMA requires less software control but runs the risk of losing data due to an incomplete transfer The GSC library uses this method Non Demand DMA and checking the FIFO counters as the standard transfer method General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 21 Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 4 PCIINTERFACE 4 0 Interface Registers The PMC PCI interface is handled by a PCI9056 I O Accelerator from PLX Technology The PCI interface is compliant with the 5V 66MHz 32 bit PCI Specification 2 2 The PCI9056 provides dual DMA controllers for fast data transfers to and from the on board FIFOs Fast DMA burst accesses provide for a maximum burst throughput of 264 to the PCI interface To reduce CPU overhead during transfers the controller also implements Chained Scatter
50. s GSC has developed routines to calculate and program the on board oscillator for a given set of frequencies so it should not be necessary for the user need the following information it is provided for documentation purposes Please contact GSC for help in setting up the on board oscillator The CY22393 contains several internal address which contain the programming information GSC has mirrored this data internal to the FPGA CLOCK RAM to allow the user to simply setup the data in the FPGA RAM and then command the on board logic to program the clock chip This isolates the user from the hardware serial interface to the chip For detailed CY22393 programming details please refer to the Cypress Semiconductor CY22393 dat sheet For the SIO4B X2 a second programmable oscillator has been added to assure that each channel has a dedicated PLL The older SIO4BX uses 3 PLLs in a single CY22393 to generate all four clocks To implement this a second CLOCK RAM block was added CLOCK programs the first CY22393 using CLKA Ch1_Clk CLKB Ch2 CLKC Ch3 and CLOCK RAM2 programs the second CY22393 using CLKD Ch4 Since the original SIO4BX with a single CY22393 used CLKD for the same code can be made to support both schemes by simply programming CLKD of the first CY22393 Each CLOCK RAM block is accessed through 2 registers Address Offset at local offset 0 00 0 and Data at local ffset at 0x00A4 CLOCK
51. s TxCount with a two clock gap TxGap in between each word Data Valid for 8 bits Invalid for 2 In the lower example Data and Envelope change on the falling edge of the Clock The Data and Envelope signals are both Active Lo The clock is still continuous Clock continues even when Data is Invalid TxC Idl Data is transmitted in 16 bit words TxCount with a one Clock gap TxGap in between each word Data Valid for 16 bits Invalid for 1 Rising Edge Ld bg LI Data NRZ 0 0 EE Y 1 0 T E 4 19 E 19 1 t 0 1 0 0 0 TxCount 16 TxGap 1 TxC 19 1 Figure 1 3 Two Signal Serial Interface 12 Deep Transmit Receive FIFOs Data is transferred to from the serial interface through Transmit and Receive FIFOs Each of the four serial channels has an independent Transmit FIFO and a Receive FIFO for a total of eight separate on board FIFOs These FIFOs are always 32k bytes deep FIFOs allow data transfer to continue to from the IO interface independent of PCI interface transfers and software overhead The required FIFO size may depend on several factors including data transfer size required throughput rate and the software overhead which will also vary based on OS Generally faster baud rates greater than 500kbps will require deeper FIFOs Deeper FIFOs help ensure no data is lost for critical systems The SIO4BX2 provides acc
52. s valid For a two wire case every clock indicates valid data When data is invalid the clock simply stops For transmit the TxC Idle field defines the two signal interface By setting the TxC Idle enable the clock will stop during idle periods The TxCount and TxGap still apply The TxE signal may be left enabled and simply unconnected or may be reconfigured as a general purpose output For receive a two wire interface is defined when RxE is set as a general purpose input When RxE is set as an input the internal logic simply assumes the internal RxE is always valid Thus all data is considered valid based on the RxC clock 3 1 3 Tx Bit Count Tx Gap The TxCount TxGap register defines the number of consecutive bits to transmit in a word as well as the number of idle clock cycles between words This configurability allows this board to interface with a custom user interface data sent to from the board is in 8 bit increments Therefore if TxCount is not a multiple of 8 all extra bits will be padded with zeros For example a TxCount of 14 would use 14 bits out of two consecutive bytes and the two extra bits would be ignored Note that there is no hardware interlock to ensure that TxCount bits are present in the Tx FIFO before a transmit can begin If TxCount is greater than 8 bits and transmit is enabled the first 8 bits will be transmitted as soon as it is loaded into TxFIFO If the TxFIFO is empty when the first 8 bits co
53. sed from GLOBAL ENGINEERING DOCUMENTS 15 Inverness Way East Englewood CO 80112 Phone 800 854 7179 http global ihs com PCI Local Bus Specification Revision 2 2 December 18 1998 Copies of PCI specifications available from PCI Special Interest Group NE 2575 Kathryn Street 17 Hillsboro OR 97124 http www pcisig com General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com ii Rev 0 General Standards Corporation High Performance Bus Interface Solutions TABLE OF CONTENTS HM 9 I RELATED II TABLE OF CONTENTS III CHAPTER 555 655 E E eoe 1 1 0 GENERAL DESCRIPTION 5 1 1 1 SERTAL gud el 2 1 11 1 THREE SIGNAL SERIAL INTERFACE cccccccccccsessssscecececeesesseaesecececessaueseesceesessuaesecececeeseaaeceeseeesesseasseseseceeseaees 2 1 1 2 TWO SIGNAL SERIAL INTERFACE ccccsccccccecsessssscecececeesenseaecececseneuececececeenesaaececececseaaeeeeeeeeseaaaeeeeeeeceeneages 3 1 2 DEEP TRANSMIT RECEIVE FIFOS
54. st Full Flag Lo 0 Rx FIFO Almost Full Rx FIFO Almost Empty Flag Lo 0 Rx FIFO Almost Empty Rx FIFO Empty Flag Lo 0 Rx FIFO Empty Tx FIFO Full Flag Lo 0 Tx FIFO Full Tx FIFO Almost Full Flag Lo 0 Tx FIFO Almost Full Tx FIFO Almost Empty Flag Lo 0 Tx FIFO Almost Empty Tx FIFO Empty Flag Lo 0 Tx FIFO Empty Channel Control Bits RESERVED RESERVED Channel Reset RESERVED FIFO Rx Tx Allocation RESERVED Reset Channel Rx FIFO Pulsed Note This value will automatically clear to 0 Reset Channel Tx FIFO Pulsed Note This value will automatically clear to 0 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email sales generalstandards com 9 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 2 8 Interrupt Registers There are 32 on board interrupt sources in addition to PLX interrupts each of which may be individually enabled Four interrupt registers control the on board interrupts Interrupt Control Interrupt Status Interrupt Edge Level and Interrupt Hi Lo The Interrupt sources are IRQO Chl Rising Edge Falling Edge IRQI Chl Tx FIFO Almost Empty Rising Edge Falling Edge IRQ2 Chl Rx FIFO Almost Full Rising Edge Falling Edge IRQ3 Chl RxSp Rising Edge Falling Edge IRQ4 C
55. t 031 00 of each register DO IRQO D1 IRQI etc All FIFO interrupts are edge triggered active high This means that an interrupt will be asserted assuming it is enabled when a FIFO Flag transitions from FALSE to TRUE rising edge triggered or TRUE to FALSE falling edge For example If Tx FIFO Empty Interrupt is set for Rising Edge Triggered the interrupt will occur when the FIFO transitions from NOT EMPTY to EMPTY Likewise if Tx FIFO Empty Interrupt is set as Falling Edge Triggered the interrupt will occur when the FIFO transitions from EMPTY to NOT EMPTY General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 10 Rev 0 General Standards Corporation High Performance Bus Interface Solutions Interrupt Sources share a single interrupt request back to Local Interrupt Input of the PCI9056 PLX chip This Local Interrupt input must be enabled in the PLX Interrupt Control Status Register to be recognized as a PCI interrupt source 2 8 1 Interrupt Control Local Offset 0x0060 The Interrupt Control register individually enables each interrupt source A 1 enables each interrupt source a 0 disables An interrupt source must be enabled for an interrupt to be generated 2 8 20 Interrupt Status Clear Local Offset 0x0064 The Interrupt Status Register shows the status of each respective interrupt source
56. te amp Invalidate Mode X D14 DMA EOT Enable 0 Unused D15 DMA Stop Data Transfer 0 BLAST Enable terminates DMA D16 DMA Clear Count Mode 0 Unused D17 DMA Channel Interrupt X Select D31 18 Reserved 0 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salest generalstandards com 23 Rev 0 General Standards Corporation High Performance Bus Interface Solutions CHAPTER 5 HARDWARE CONFIGURATION 5 0 Board Layout The following figure is a drawing of the physical components of the PCIe SIO4BX2 SYNC Figure 5 1 Board Layout Top 5 1 Board ID Jumper J2 Jumper J2 allows the user to set the Board ID in the Board Status Register See Section 2 1 3 This is useful to uniquely identify a board if more than one SIO4BX2 SYNC card is in a system When the Board ID jumper is installed it will read 1 in the Board Status Register The Board Status Register bit will report 0 when the jumper is removed Refer to Figure 5 1 for Jumper J2 location J2 Jumper 1 2 Board ID 1 Board ID 1 in Board Status Register DO 3 4 Board ID 2 Board ID 2 in Board Status Register D1 5 6 Board ID 3 Board ID 3 in Board Status Register D2 7 8 Board ID 4 Board ID 4 in Board Status Register D3 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 80
57. tion 0x4 Two CY22393 6 Oscillators D5 3 USC RxC Source General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 15 Rev 0 General Standards Corporation High Performance Bus Interface Solutions The clock source must agree with the USC Clock setup USC I O Control Reg D5 3 to ensure the signal is not being driven by both the USC and the FPGA D4 USC RxC Source USC IOCR D2 D0 Setup 0 0 0 Prog Clock 000 Input 0 0 1 Inverted Prog Clock 000 Input 0 1 0 0 000 Input 0 1 1 T 000 Input 1 0 0 Cable RxC Input 000 Input 1 0 1 Cable RxAuxC Input 000 Input 1 1 0 RESERVED 1 1 1 Driven from USC IOCR D2 DO 000 Output D2 0 USC TxC Source Since this signal is bidirectional it may be used as either an input or output to the USC the clock source must agree with the USC Clock setup USC IO Control Reg D2 0 to ensure the signal is not being driven by both the USC and the FPGA D2 DO USC TxC Source USC IOCR D5 D3 Setup 0 0 0 Prog Clock 000 Input 0 0 1 Inverted Prog Clock 000 Input 0 1 0 0 000 Input 0 1 1 T 000 Input 1 0 0 Cable RxC Input 000 Input 1 0 1 Cable RxAuxC Input 000 Input 1 1 0 RESERVED 1 1 1 Driven from USC IOCR 05 03 000 Out
58. ues are fixed via the Serial EEPROM load following a PCI Reset and cannot be changed by software Vendor ID Ox10B5 PLX Technology Device ID 0x9056 PCI9056 Sub Vendor ID Ox10B5 PLX Technology Sub Device ID 0x3198 GSC SIO4BXR The configuration registers also setup the PCI IO and Memory mapping for the SIO4BX2 The PCI9056 is setup to use PCIBARO and PCIBARI to map the internal PLX registers into PCI Memory and IO space respectively PCIBAR2 will map the Local Space Registers into PCI memory space and PCIBAR3 is unused Typically the OS will configure the PCI configuration space For further information of the PCI configuration registers please consult the PLX Technology PCI9056 Manual General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 or 800 653 9970 FAX 256 880 8788 Email salesQgeneralstandards com 22 Rev 0 General Standards Corporation High Performance Bus Interface Solutions 41 2 Local Configuration Registers The Local Configuration registers give information on the Local side implementation These include the required memory size The SIO4BX2 memory size is initialized to 4k Bytes All other Local Registers initialize to the default values described in the PCI9056 Manual 41 3 Runtime Registers The Runtime registers consist of mailbox registers doorbell registers and a general purpose control register The mailbox and doorbell registers are not used and serve no purpose
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