Home

EUDET-Memo-2007-45

1. gt We VO VO vo VO Bem d Ou 5 9u 6 gu 7D time s 4 Pad Ring The pad ring of the chip is build with e Pads full custom designed for some of the analogue signals and power supplies e Pads from the AMS library for the digital signals and power supplies The pad ring is split in 6 functional independent parts Each part has its own supply pads October 2006 MimoTEL User Manual 11 MimoTEL 1 MimoTEL Pad Ring and Floor Plan View ja e rj DH sl e e OLD CH et EE dt EEHEHE OK 233 1 PA a P A3 75 Foundry submission information MimoTEL has been designed in AMS C35B401 CMOS 0 35 um The Process Design Kit V3 70 has been provided by CMP CAD tools are CADENCE DHII 5 0 with DIVA and ASSURA rules October 2006 MimoTEL User Manual MimoTEL 4 2 Pad List Glgnd Core logic and periphery cells supply AGNDALLP Ground periphery amp core 8 gnd Core logic and periphery cells supply AGNDALLP Ground periphery amp core 9fgnd_ Corelogicand periphery cells supply AGNDALLP Ground periphery amp core October 2006 MimoTEL User Manual 13 MimoTEL Core logic and periphery cells supply AGNDALLP Ground periphery amp core Core logic and periphery cells supply AGNDALLP Ground periphery amp core Pad ring segment 3 PL Pad General Function PadType Function for the chip LVDS Pad Ground AGNDALLP Ground for LVDS Pad CKRN LVDS In Full Custom Readout Clock Signal
2. 6 A F Zarnecki Analytical Track Fitting Method with Multiple Scattering of EUDET Collaboration Report 2007 1 7 A Bulgheroni et al First Test Beam Results from the EUDET Pixel Detector IEEE NSS MIC 2007 Conference Record to be published 8 W Dulinski et al Beam Telescope for Medium Energy Particles based on Thin Submicron Precision MAPS IEEE NSS MIC 2007 Conference Record to be published EUDET Memo 2007 45 Appendix A Delivery status of MimoTEL sensors Sensor Epi Status Holding Inst Comments thickness _ OK PHC OK PHC missing OK PAC OK Ferrara O JL DESY ___________ LO JL DESY __________ O DESY Le O JL DESY ____________ __Pixel yield DESY TI _ DESY O DESY JL _ DESY _ DESY JL PHC Le Nottested PHC TO Nottested IPHC Nottested IPHC EUDET Memo 2007 45 Appendix B Delivery status of Mimosa18 sensors Sensor Epi Status Holding Inst Comments thickness LL ul OK PC 2 204 OK PHC 1 1 1 1 1 1 1 1 1 IPHC IPHC DESY Dm IPHC Do IPHC O IPHC A IPHC 1 IPHC IPHC Do nl OK Frankfurt J o 6 10 n cm2 107 wem Ju OK Oregon __ _____________ Wu OK Oregon _____________ IPHC AAA IPHC Run 2007 IPHC Run 2007 thinned to 50um IPHC Run 2007 thinned to 50um 10 EUDET Memo 2007 45 Appendix C Mimosal 10 um pixel pitch on PCB 11 EUDET Memo 2007 45 Appendix D MimoTEL User
3. CKRP LVDS In LVDS Pad Supply AVDDALLP 3 3V for LVDS Pad Pod ring segment 2 P D2 60 gnd Pad supplying the output buffers GND3OP__ Ground CMOS Clock Input Buffer 2 mA JTAG Clock Core logic and periphery cells supply GND3RP 66 gnd Core logic and periphery cells supply GND3RP __68 vdda Analogue Pad Supply TAVDDALLP 33V 0 _ __69 vdda Analogue Pad Supply JAVDDALLP 33V 0 _ _ October 2006 MimoTEL User Manual 14
4. matter to do with the DIS_COL register 255 Msb 0 Lsb DisCol lt 255 gt DisCol lt 0 gt 2 2 BIAS DAC Register The BIAS DAC register is 88 bits large it sets simultaneously the 11 DAC registers As show bellow these 8 bit DACs set voltage and current biases After reset the register is set to O a value which fixes the minimum power consumption of the circuit The current values of the DACs are read while the new values are downloaded during the access to the register The image of the value of some critical biases can be measured on corresponding test pads Bi DAC DAC Internal DAC purpose Corresponding range Test Pad t 87 80 DACIO IKIMO External circuit monitoring KIMO 79 72 DAC9 I4PIX Pixel source follower bias DAC with positive IPIX 8 Z S kel EN slope 0 to 255 uA 1 uA step V4TESTI Test Level emulates a pixel output DAC with No pad positive slope 0 to 2 55V 10 mV step VATESTO DAC6 V4REG3 Regulator voltage bias for the column amplifier VREGAMP a Gain 3 amp 5 DAC with negative slope 3 3 to 4REG2 71 64 Z O o en 63 56 55 48 0 75 V by step of 10 mV 47 40 ea OJO ZIZ Z jo jo 3 bo re S S ajaja CN REGI 4REGO Idem 23 16 Regulator current bias for column amplifier G 3 amp 5 This DAC value is not very sensitive for No pad test DAC with positive slope 0 to 255 uA 1 uA step slope
5. Format of the analogue ouput Asglc0 eeeeeeerrreerereeeanaoa 9 E fe Ge EE EE eege 9 do Mimo Rs We ee e E 9 3 6 1 IN Oia R AO eee ee So saida a nine aaa 9 3 6 1 1 Alternate Mxfirst signal for normal readout oooooooonncnnnncnononiocnnnnnnnnnnnnnnos 11 3 6 2 Testmode te AO den da ee ac 11 do A RE 11 4 1 MimoTEL Pad Ring and Floor Plan View 12 BD AG E PR e PEU O E 13 October 2006 MimoTEL User Manual 2 MimoTEL 1 Introduction MimoTEL the third version of the MimoStar family has been designed in C35B401 the AMS 0 35 um opto process Like MimoStar 1 and 2 it is a Monolithic Active Pixel Sensor prototype dedicated to vertex particle tracking in the EUDET telescope The matrix is composed by 256 x 256 pixels of 30 um pitch and based on self biased diode architectures It is organised in 4 matrices or subframes of 256 lines x 64 columns accessed in parallel during the readout The individual pixel architecture should meet the radiation tolerance and the low leakage current requirements The addressing of each subframe is sequential and starts from the upper left pixel up to the lower right pixel The beginning of each subframe row is stamped by 2 dummy pixels acting as makers and having programmable levels Each subframe has its own analogue serial output a single ended voltage output buffer running up to 20 MHz which gives a readout time of 850us frame Digital Analog Supplies Supplies gnd vdd Vdd_diode vdda gnd
6. O to 255 uA 1 uA step with positive slope 0 to 255 uA 1 uA step DAC2 I4REGAMP 15 October 2006 MimoTEL User Manual MimoTEL 3 Running MimoTEL The following steps describe how to operate the ASIC 3 1 After reset On RSTB active low signal e All BIAS registers are set to the default value 1 e O e DIS COL is set to O te all columns are selected e RO_Mode is set to 0 e JTAG state machine is in the Test Logic Reset state e JTAG ID_CODE instruction is selected Then the bias register has to be loaded The same has to be done for the RO MODEO and DIS COL registers if the running conditions differ from defaults Finally the readout can be performed either in normal mode or in test mode 3 2 Biasing MimoTEL The BIAS_DAC register has to be loaded before operating the chip The 11 DACs constituting this register are built with the same 8 bits DAC current generator which has a 1 HA resolution Specific interfaces like current mirror for current sourcing or sinking and resistors for voltages customise each bias output The following table shows the downloaded codes which set the nominal bias Internal Simulation Resol Range DAC Codes DacInterna Output ution Code Codejo Name Code 1 current value uA IKIMO 100 100 a ra mV From 0 up to 2 FromOupto2 55V 30 From 0 up to 255 uA 195 From 0 up to 2 55 V V4TESTO B9 185 185 1 85 V 10mV From 0 up to 2 55 V E
7. TTP 2S 65 P EL 622 Press 0 gt AS E O OS MIS Pe SL A ES 0 gt MKI MKO Br 0 6 ro do cs vc Es RES 3 5 2 Test mode data format During the test mode the pixel matrix is not anymore connected to the multiplexing electronic In place of it two test levels V4TESTI V1 V4TESTO VO are available They emulate two pixel level outputs Actually these levels correspond to those of Marker 1 and Marker 0 They are adjustable via 2 DACs Even and odd columns are alternatively connected to one of them This pattern allows seeing the output signal changing and emulates the readout shift from one column of pixel to the other column of pixel Thus the 4 parallel outputs generate respectively the following stream formats Subframe 3 analogue ouput Asgl lt 3 gt V1 VO VO V1 V1 VO VO V1 Subframe 2 analogue ouput Asgl lt 2 gt VO V1 V1 VO VO V1 V1 VO Subframe 1 analogue ouput Asgl lt l gt V1 VO VO V1 V1 VO VO V1 Subframe O analogue ouput Asgl lt 0 gt VO V1 V1 VO VO V1 V1 VO 3 6 MimoTEL Chronogram The following chronograms describe typical access to the chip Reset JTAG download sequence and then the readout This one starts with the initialisation phase followed by the successive row readouts as showed in the zoom 3 6 1 Normal Readout Figure show the beginning of a typical normal data readout mode After Reset and JTAG settings one can see the initialisation phase of the readout of the first pixel row The Last
8. cm ladders for any microvertex application this may be of serious concern i eet Kn KL Y gue we a Ll 1 Figure 4 Mimosal8 thinned down to 50 um mounted and wire bonded on supporting PCB The laboratory test phase was also very useful for the estimation of sensor production yield In fact out of 18 MimoTELs and out of 20 Mimosal8 assembled and tested sensors including two M18 devices thinned down to 50 um all were found to be fully functional Among MimoTELSs two sensors were showing important amount of dead pixels In case of all assembled Mimosal8 the number of dead pixels was always smaller than 0 1 Appendix_A and Appendix_B show present status of all assembled chips Appendix_C presents a picture of Mimosal8 mounted on PCB including a scheme of its readout direction The first version of MimoTEL User Manual is included as Appendix_D 4 Status of delivery of PCBs In order to be able to assemble the telescope set up a set of PCB Printed Circuit Board has been developed It consists of several elements shown in Figure 5 The proximity board separate for MimoTEL and Mimosal8 is used for mechanical mounting and wire bonding of sensors It contains passive components for power and control lines stabilization and buffers for outgoing analog signals The Auxiliary PCB common for both sensors is used for EUDET Memo 2007 45 generation of power supply it provides buffers for digital controls and second level buffers
9. each subframe the addressing is done row by row each pixel is accessed sequentially from the left side to right side Each row contains 2 makers acting as dummy pixels and 64 active pixels One can use the adjustable level of the 2 makers as a pattern recogniser If the pixel coordinate format is specified as Px lt Line Column gt then for each subframe the upper left pixel is Px lt 255 63 gt while the lower right is Px lt 0 0 gt and the makers of each beginning row are named Mk1 and MKO Thus the 4 parallel outputs generate respectively the following stream formats 3 5 1 1 Format of the analogue ouput Asgl lt 3 gt MEL MKO Pe lt 255 255 gt Pe lt 255 254 gt p PR lt 255 192 gt MEL MRO Pe lt 254 2559 gt ERCL54 2504 gt ep Px lt 254 1927 MEL MRO Px lt 1 255 gt PX lt 1 25453 s 7 Px 1 192 gt MEL Mk Pas 0 2555 Pe lt 40 254 2 mp PR lt D 192 gt October 2006 MimoTEL User Manual 8 MimoTEL 3 5 1 2 Format of the analogue ouput Asgl lt 2 gt Me E le P io O AO Mk O P E A O A el Pt Oe ee o Me El AO Ps O ler e 3 5 1 3 Format of the analogue ouput Asgl lt 1 gt MEL MRO PK lt 255 127 Pxe255 126 gt lt gt oy Fx lt 255 64 gt MEL MRO Px lt 254 1276 8 lt 254 126 gt gt sp Px lt 254 64 gt MEL MkO Px lt 1 12 gt Px lt 1 126 gt 0 p Px lt 1 64 gt MET MkO Pee 0 127 gt Px lt 0 126 26 PX O 64 gt 3 5 1 4 Format of the analogue ouput Asgl lt 0 gt MEDA MRO
10. optimized and fabricated in a cost effective way using standard CMOS processes available through many commercial microelectronics companies The idea of using MAPS as a sensor plane for the construction of a new generation of high precision portable and equipped with flexible DAQ beam telescopes has been brought by EUDET Collaboration The telescope consisting of up to six reference planes should be optimized for medium energy particle beams as an electron beam line at DESY 6 GeV maximum A dedicated study was performed to understand the position resolution in the telescope in order to optimize its performance by choice of the best plane setup The approach is based on novel analytical track fitting method taking into account multiple Coulomb scattering effects 6 In the first implementation of the EUDET telescope called the demonstrator phase the reference planes are based on two types of specially developed and optimized sensors MimoTEL called also Mimosal7 and Mimosal8 known as a high resolution tracker In both of them very standard analog serial readout architecture of pixel has been chosen From the beginning a great importance has been given to provide sensors as thin as possible in order to minimize particle scattering and improve tracking quality The choice of MAPS shall allow reaching the thickness of a single reference plane of much less than 100 um of silicon 2 Engineering run AMS 0 35 um OPTO The pixel sensors for t
11. run was started at AMS in February 2007 with six wafers delivered in April This run is referenced as 2007 submission After testing in laboratory the telescope sensors has been intensely studied during 2007 at high energy beams at DESY and at CERN The results not discussed in this report have been already presented and published 7 8 EUDET Memo 2007 45 20um 200012 A0_p1 20um 200012 A0_p4 18036 A3_p4 Figure 3 Distribution of collected charge generated by 5 9 keV photons as a function of cluster size for two types of epitaxial wafers for MimoTEL sensor a and for Mimosa18 sensor b The thickness of the sensors as delivered by the foundry is of 700 um not very optimum from the point of view of application for medium energy particle tracking Therefore several reticles from one of the delivered wafers were thinned down to less than 100 um using a EUDET Memo 2007 45 commercially available post processing step Figure 4 shows a micro photography of a Mimosal8 sensor thinned down to about 50 um glued on top of supporting PCB and wire bonded to the interface electronics As seen on bottom picture an internal mechanical stress of the device generates a visible bowing effect with estimated amplitude of more than 100 um This effect is expected to be largely removed by more adequate choice of tooling for the gluing operation However for the construction of large area ultra light objects like several tens of sq
12. 6 230 V4REG 3 23 35 35 2 95 V 10mV From 3 3 down to 0 75 V 80 128 V4REG 2 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 VAREG 1 23 35 35 2 95 V 10mV From 3 3 down to 0 75 V 80 128 VAREG 0 23 35 35 2 95 V 10 mV From 3 3 down to 0 75 V 80 128 I4REG1 21 33 33 33 uA IuA From 0 up to 255 uA 1 1 I4AMP 64 100 100 100 HA 1uA From 0 up to 255 uA 3 3 ISLOWBUFSE 64 100 100 100 HA IuA From 0 up to 255 uA A 10 Note 1 The HRES ploysilicon used in the bias block is missing for this submission Experimental values correspond to the recalculated parameters that allow nevertheless the chip be operated A new submission of the chip is in progress Bias synthetic block diagram E I4PIX ISLOWBUFSE VAREG I4AMP n 0 1 2 3 for 4 sub matrices V4TEST1 V4TESTO October 2006 MimoTEL User Manual 7 MimoTEL Notel Vrefn V4REGn 1V 3 3 Setting the Readout_Mode Register If the desired operating mode does not correspond to the default one set the Readout_Mode0 register following the 2 2 5 information 3 4 Readout 3 4 1 Signal protocol Ones JTAG registers have been loaded the readout of MimoTEL may initiate with the following signal protocol e The readout clock CKRD is started This allows the output pad CK20M to generate a 20 MHz clock This clock follows the input e The SYNC signal is set e The readout starts at the first rising edge of CKRD after SYNC signal disappears e Signal markers allow th
13. Bias Tests VREGAMP IPIX IKIMO ITEST Power Supplies i On se a AZO XOF CMOS Signals 9056 E OZ 2 gt 0028 LVDS Signals o a k FF CE H gt L604 p E S POLES Y j n Y Analogue Signals amp q lt 0 aa l MimoTEL functional view Does not correspond to the floorplan neither for the core neither for the pad ring October 2006 MimoTEL User Manual 3 MimoTEL MimoTEL is very simple to operate e Power On Reset or Reset on the RSTB pad e Setup of the chip It is performed with programmable registers accessed via an embedded slow control interface It consists to e Load the DACs which bias the analogue blocks e If necessary load the ReadOut Register with a specific configuration The default setup on power on reset allows a normal readout once the biases have been set e Readout of the chip e The readout starts when the input SYNC token has its falling signal sampled by the LVDS readout input clock CKRD It happens at the first rising edge of the 20MHz clock which follows the SYNC falling edge e After a latency of 4 input clock cycles the analogue signals appear on the output buffers e Digital maker outputs are available for the control of the readout process e Pixels are sequentially read out in a specific order explained later in the document e Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the SYNC token again 2
14. Col signal is active meanwhile the last pixel of a row is read The last row of the frame makes the LastRow signal to be active One of the 4 parallel analogue outputs is showed One can distinguish the 2 makers placed at the beginning of each row Figure 2 1s the zoom of the readout of the first row Figure 3 1s an enlargement of the transition from one row to the successive one Figure 4 show the alternate option of the MxFirst signal It is active only during the time the first maker appears 1 e just before the first pixel of the frame This option is set via the RoMode register October 2006 MimoTEL User Manual 9 MimoTEL E SONS age 7 ERE SS a Se ee a ee eesemensessssms Ck2 Mout d dn j MxFirst HE LastCol RE RstB LastRow EE I 1 i ra ra rara ra RENE 1 36 l E Asgl 1 15 140 854m G AG 1 98u 3 8 5 78u 7 9 58u 11 4u 13 3u 15 2u 17 1u time s Reset Jtag access Idle row readout In Successive row readouts Last row readout Figure 1 Bel o are aa RAD eo ee de AA I i I TCK e Syne 7 ae ie we eek eee CkLyds do l d Ekel KR E ek le leks Reel Es ee ee Ie EC al A Rsthk LastCol LastRow E L l 1 1 38 Asgl lt 3 gt Marker lt 0 gt LE Px lt 255 254 gt Px lt 255 248 gt i Px lt 255 255 gt Px lt 255 253 gt Px lt 255 249
15. Control Interface The control interface complies with the Boundary Scan JTAG IEEE 1149 1 Rev 1999 standard It allows the access to the internal registers of the chip like the bias register and the readout mode selection register On Power On Reset an internal reset for the control interface is generated The finite state machine of the Test Access Port TAP of the controller enters in the Test Logic Reset state and the ID register is selected 2 1 JTAG Instruction Set The Instruction Register of the JTAG controller is loaded with the code of the desired operation to perform or with the code of the desired data register to access Bit Codes Selected Register JTAG mandatory instruction JTAG optional instruction JTAG optional instruction YPASS W Lo d Lo Es JTAG optional instruction JTAG mandatory instruction D register JTAG optional instruction IAS register User instruction isable Columns Reserved Not Used ead Out Model ead Out Mode0 YPASS JTAG mandatory instruction W YPASS SAMPLE PRELOAD ID_CODE BIAS_GEN ve Lo p Q RO MODE RO MODEO BYPASS IC IE Wiz October 2006 MimoTEL User Manual 4 MimoTEL 2 2 JTAG Register Set JTAG registers are implemented with a Capture Shift register and an Update register JTAG standard imposes that the last significant bit of a register is downloaded shifted first Notes Instruction Register Fixed pattern revious value
16. E instruction or after the fixed value is shifted via TDO the JTAG serial output of the chip ID CODE register value is OXFFFF8001 2 2 5 RO Mode Register0 The RO Mode registers are 8 bits large they allow the user to select specific features of the chip MimoTEL use only the RO Mode Registero October 2006 MimoTEL User Manual 5 Default value Disable LVDS readout clock is not active O LVDS selected anymore On MxFirst output pad select the MuxFirst MuxFirst Signal active signal or the First_Pixel_of the Frame signal See 3 4 Readout Select gain 3 for the serial differential output Gain 5 buffer NotUsed O LL EnaTstCol Test Mode Select the 2 Test Levels IVTEST1 Normal mode and IVTESTO which emulate a pixel output 2 2 6 DIS COL Register The DIS_COL register 1s 256 bit wide The purpose of this register is to disable the column current sources if a short circuit is suspected on a specific column During the readout even if a current source is disabled the corresponding column is selected i e no columns are skipped Obviously the signal of the corresponding pixel has no signification The default value of the DIS COL register is O it means that all current sources can be activated by the readout logic Setting a bit to 1 disables the corresponding current source The column lt 256 gt is on the left hand side while column lt 0 gt is on the right hand side The organisation of the chip in 4 subframes of 64 columns has no
17. EUDET Memo 2007 45 Status of pixel sensors for the demonstrator phase of EUDET beam telescope Wojciech Dulinski December 05 2007 Abstract A general purpose beam telescope of new generation has been constructed and tested All reference planes of the telescope are based on CMOS Monolithic Pixel Sensors MAPS fabricated for this application using AMS 0 35 um OPTO process Some of the sensors have been thinned down to about 50 um using commercially available post processing Present delivery status of the sensors is given in this report It includes also the status of auxiliary electronics PCBs and the User Manual of MimoTEL the standard reference sensor for the Telescope Demonstrator Phase IPHC Strasbourg France EUDET Memo 2007 45 1 Introduction A Monolithic Active Pixel Sensor MAPS integrates on the same substrate the detector element with the processing electronics The key element is the use of N well P substrate diode to collect through thermal diffusion the charge generated by the impinging particle in thin undepleted epitaxial silicon layer underneath the readout electronics 1 The device ability to provide charged particle tracking has been demonstrated on series of MIMOSA standing for Minimum Ionizing MOS Active sensor chip prototypes 2 4 Excellent tracking performances were experimentally verified 5 with measured spatial resolution down to 1 5um for 20um pixel pitch Such devices may now be easily
18. Manual 12 Institut o er ol de UREN Hubert 5 TRASBOURG MimoTEL User Manual C Colledani W Dulinski H Himmi Ch Hu I Valin Institut de Recherches Subatomiques IN2P3 CNRS ULP Strasbourg France SCIENTIFIQUE De IN2P 3 y al E UNIVERSIT LOUIS PASTEUR Insrrrur NATIONAL DE PHYSIQUE NUCL AIRE ET DE PHYSIQUE DES PARTICULES STRASBOURG ih MimolEL Document history October 2006 Based on MimoStar2 Version October 2006 MimoTEL User Manual MRM WT estar ees E E a ag 3 SE ee i A a cscs ne teroore E E canta A E A E E 4 2 1 TEA TS Ken EE 4 22 PAG REBET E 5 Zu Leal e RESISTE ee 5 222 A age O sos ad ee ie sde De te ie 5 2 2 3 Boundary scan ge ne da ua 5 2 2 4 UB HE 5 22 IA AAPP E O 5 220 DIS COL IC SCF sucia 6 2 EIERE 6 2 RUT NEGO AAA ate saree nee ae ol 7 3 1 E 7 Ie Pee Mino PE ae ae a a E 7 3 3 Sctune the Readout Mode RESISIER Se Se eege 8 BAe RAO RR RR 8 3 4 1 DS Hal OVO A E 8 3 4 2 Successive frames and resynchronisation ssseseessssssssseeerssssssseeeessssssseeeeees 8 3 5 Anal pue Data OMA eerie E E 8 3 5 1 Normal mode data format ss 8 3 5 1 1 Format of the analogue ouput Asgl lt 3 gt ooooonccnccccccnnoooccnnnnnnonononannnnnnnnnnnnnnnnos 8 3 5 1 2 Format of the analogue ouput Asgl lt 2 gt oooonnccnnccccnnnnnnonnnnnononnnnnonnnnnnnnnnnnnnnnos 9 3 5 1 3 Format of the analogue ouput Asgl lt l gt ooncccnnccccnnnoonccccnnnnnnnnnnancnnnnnnnnnonnnnns 9 3 5 1 4
19. d inside charge sensing Nwell The size of the sensing Nwell diode is of 4 4 x 3 4 um close to the minimum size required by the DRC rules of this process em emm em em em emm em emm gt gt em gt wm wm mm gt wm otiput Figure 1 Pixel circuit of sensors for the EUDET demonstrator phase beam telescope The signal information from each pixel is serialized by a circuit one per sub array which can withstand up to a 25 MHz readout clock frequency This provides respectively for the MimoTEL and Mimosal8 a full frame readout time of 800 us and 3 ms with four parallel outputs present in both In this architecture the frame readout time is equal to the signal integration window Information from two consecutive frames was read out one frame before and one frame after each trigger A data analysis based on the correlated double sampling CDS method was used for hit reconstruction MimoTEL MimoStar3 Figure 2 Layout of the single reticle from June 2006 IPHC engineering submission containing several MAPS prototypes for different applications The MimoTEL and the high resolution tracker Mimosa18 called also Imagerl0u was part of an engineering run submitted by IPHC in June 2006 Figure 4 shows the layout of a single reticle 2 x 2 cm silicon area from this submission which contains several other sensors The biggest one MimoSTAR3 320 x 640 pixel array 30 um pitch is a prototype devoted for microvertex detecto
20. e monitoring of the readout and the analogue data sampling o RstMk maker confirms that the internal reset of the readout logic is done o SSync marker shows that the readout starts o 4 extra CKRD clock cycles after SYNC sampling are necessary before the analogue signal of the first pixel appears on the output pad o The MxFirst digital signal helps for a better sampling of the analogue output signals The way it acts is set by the RO_Mode 4 bit RO_Mode 4 O MxFirst is active during the duration of the first maker of the frame RO_Mode 4 1 MxFirst is active on each pixel change on the analogue output Le it is a 20 MHz periodic signal o LastCol is active when the last column of the current row is selected o LastRow is active when the last row of the frame is selected o Ck20M output shows the internal clock running as long as input clock is running 3 4 2 Successive frames and resynchronisation Successive pixel frames are read until the readout clock is stopped A frame resynchronisation can be performed at any time by setting up the SYNC token again 3 5 Analogue Data Format Two types of signal can be generated e Normal pixel signal e Test signal 3 5 1 Normal mode data format In order to improve the readout speed MimoTEL is organized 4 subframes Each subframe has its own analogue serial output a single ended voltage output buffer running up to 20 MHz During the readout the 4 subframes are accessed in parallel For
21. for analog signals Another two boards ClockTree and ClockRoot are used only for laboratory test set up and for the back up version of data acquisition system of the telescope Beam area Trigger PCB BE E e W sse Jo q q Mimo Tel or HR Tracker on Auxiliary PCB 4 L em zm zm mm zf zm zm mm mmm mmm mm zm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mm mmm mm mm mm mm mmm mmm Figure 5 Schematic view of PCBs required building the demonstrator phase telescope In total 30 sets of front end boards has been produced one set contains one proximity board for MimoTEL one proximity board for Mimosal8 and one Auxiliary board It has been all assembled and tested between IPHC and DESY electronics workshop and are now available for the Collaboration In addition to this five sets of ClockTree and ClockRoot PCB have been supplied by IPHC for the laboratory tests 5 Conclusion Production assembling and delivery of sensors for the demonstrator went quite smoothly and is by now almost finished The only on going activity is thinning of sensors to less than 100 um detailed study of effects of thinning on the sensor global performance and better full statistics estimation of the production yield In order to improve the later one it is below our expectation for the big sensor we plan to have intense investigation of the layout in collaboration with AMS technology serv
22. gt Px lt 255 247 gt Matker lt 1 gt Gr 4 24u 4 Au 4 Ch E Gu E Stu 5 Hu Initialisation phase 1 st row readout phase I Figure 2 CkLyds Ck2 Mout RstMk 7 E Lusa aaa aaa a La sa a a aa aaa aaa aa sal 4 safa a a a sa a asa 4 MxFirst gt LastCol eos LastRow SSync ala Px lt 255 191 gt Marker lt 0 gt Px lt 255 254 gt Px lt 255 192 gt A t Px lt 255 253 gt 7 Bu eu 7 Au 7 6u 7 8u 8 9u 8 2u End of 1 st row readout 2 4 row readout Figure 3 October 2006 MimoTEL User Manual 10 MimoTEL 3 6 1 1 Alternate Mxfirst signal for normal readout Sync gt CkLvds Ck2 Mout RstMk SSync gt MxFirst LastCol LastRow ET RSS ni ES Some gt TUTTI nann inna UU UL nan LULU 188 Bbm E Eech L IR mel E S IAS LL EE ey ce er tae DRE ee te 4 90u 7 9 u 18 au 13 9u 16 9u 19 time si Figure 4 3 6 2 Test mode readout The initialisation phase if the test mode is the same than in the normal mode But it has to be noticed than the LastCol and LastRow makers are unavailable because the test mode has nothing to deal with the matrix and its line and column addressing registers For the same reason the MxFirst maker is unavailable in the First Pixel of frame mode but only continuous mode CkLyds Ck24Mout d a Asgl lt 2 gt 2 1 1 Asgl lt 9 gt l4 VO VO Vo Asgl lt 1 gt 9 9 x Asgl lt 3 gt
23. he telescope have been fabricated using AMS 0 35 OPTO process The AMS 0 35um OPTO process has been chosen for several reasons It is an advanced mixed signal CMOS process providing four metal layers two polysilicon layers high resistivity polysilicon and two types of transistor gates 3 3 V and 5 V The N well p epi diodes are optimized for a low dark current at room temperature The feature of a special interest 1s epitaxial layer having more than 10 um thickness Such a thick epitaxial layer should provide a comfortable charge signal from passing minimum ionizing particles The process is available through multi project submission runs at Austria Micro Systems which allows easy and cheap prototyping The first sensor used by EUDET collaboration as a standard reference plane of their telescope is called MimoTEL It consists of 256 x 256 pixel array having a 30 um pitch in both direction and providing a continuous sensitivity area of 7 6 x 7 6 mm The other one Mimosal8 is optimized for high resolution tracking It consists of 512 x 512 pixels with a EUDET Memo 2007 45 pixel pitch of 10 um A continuous tracking sensitive area with this device is of 5 x 5 mm In both sensors a simple read out architecture is used Fig 3 It consists of a 2 transistor pixel cell half of a source follower plus a readout selection switch connected to the charge collecting Nwell diode continuously biased by another diode forward biased implemente
24. ice Acknowledgement This work is supported by the Commission of the European Communities under the 6 Framework Program Structuring the European Research Area contract number RII3 026126 EUDET Memo 2007 45 References 1 B Dierickx G Meynants D Scheffer Near 100 fill factor CMOS active pixel in Proc of the IEEE CDD amp AIS Workshop Brugge Belgium 5 7 June 1997 2 R Turchetta J D Berst B Casadei G Claus C Colledani W Dulinski et al A Monolithic Active Pixel Sensor for Charged Particle Tracking Nucl Instrum Methods vol A458 pp 677 689 3 G Deptuch J D Berst G Claus C Colledani W Dulinski U Goerlach Yu Gornushkin Y Hu D Husson G Orazi R Turchetta Design and Testing of Monolithic Active Pixel Sensors for Charged Particle Tracking IEEE Trans Nucl Sci Vol 49 No 2 2002 601 4 G Deptuch G Claus C Colledani M Deveaux A Gay W Dulinski Yu Gornushkin Ch Hu Guo and M Winter Development of monolithic active pixel sensors for charged particle tracking Nucl Instrum Methods vol A511 pp 240 249 5 W Dulinski J D Berst A Besson G Claus C Colledani G Deptuch M Deveaux A Gay D Grandjean Y Gornushkin A Himmi Ch Hu J L Riester I Valin and M Winter CMOS Monolithic Active Pixel Sensors for Minimum Ionizing Particle Tracking Using Non Epitaxial Silicon Substrate IEEE Trans Nucl Sci Vol 49 No 2 2004 601
25. ifference in design layout of the diode it 1s a standard Nwell diode in case of Mimosal8 and radiation tolerant diode in case of MimoTEL Charge collection efficiency from epitaxy has been studied as function of cluster size and was found very different for two types of wafers Figure 3 This is in particular the case of seed central pixel of a cluster where the observed peak position from X rays photons converted in epitaxy is substantially lower for 20 um epitaxy type This effect will severely limit expected increase of a signal charge from minimum ionizing particles traversing thicker epitaxy layer During calibration phase of the Mimosal8 prototype a new feature of X rays spectrum was observed It consists of characteristic double peak in addition to the third small peak at the right corresponding to full charge collection clearly visible in case of 2x2 and 3x3 clusters This double peak is much more pronounced in case of 20 um epitaxy The explanation for this effect is still to be found During this phase of testing it was found that the foundry by mistake didn t implement one of required layer high resistivity polysilicon This missing layer has no influence on Mimosal8 it has not been applied in that sensor For MimoTEL a small modification on PCB was required in order to provide one additional reference voltage impossible to generate internally without high resistivity polysilicon In order to correct the mistake another production
26. r upgrade of the STAR experiment at RHIC Brookhaven National Laboratory Two types of wafers were used for this engineering submission a standard wafers with 14 um epitaxy and an experimental wafers with 20 um epitaxy To our knowledge it is the thickest epitaxy layer available through commercial CMOS process 4 EUDET Memo 2007 45 3 Status of the delivery and tests of sensors Immediately after reception of six wafers from AMS at the and of October 2006 two wafers one with 14 um epitaxy and one with 20 um epitaxy has been diced and chips bonded to the readout PCBs proximity boards Each sensor was electrically tested in the laboratory prior to the high energy particles tracking tests The standard calibration procedure using 5 9 keV X rays from a Fe source has been applied in order to measure basic parameters of the sensor Equivalent noise charge ENC was found to be equal to 15 1 electrons 10 electrons at room temperature for the signal integration time of 1 ms 4 ms respectively for Mimo TEL and Mimosal8 A dark current measured directly Mimo TEL or estimated from the measured temperature dependence of the ENC Mimosal8 of the sensing diode in this condition is of few dozens fA Mimo TEL and less than 0 5 fA Mimosal8 Only in case of MimoTEL the corresponding shot noise contributes substantially to the thermal noise of the input transistor The difference in dark current between two devices comes from the d
27. shifted out during write revious value shifted out during write P P Previous value shifted out during write Previous value shifted out during write NUI NU12 Not implemented For future use 2 2 1 Instruction Register The Instruction register is a part of the Test Access Port Controller defined by the IEEE 1149 1 standard The Instruction register is 5 bits long On reset it is set with the ID_CODE instruction When it is read the 2 last significant bits are set with the markers specified by the standard the remaining bits contain the current instruction x x x 1 jo 2 2 2 Bypass Register The Bypass register consists of a single bit scan register It is selected when its code is loaded in the Instruction register during some actions on the BSR and when the Instruction register contains an undefined instruction 2 2 3 Boundary Scan Register The Boundary Scan Register according with the JTAG instructions tests and set the IO pads The BSR 1s 9 bits long and allows the test of the following input and output pads Bit Corresponding Pad 8 LVDS CkRdP CkRdN CkRd Resulting CMOS signal after LVDS Receiver 17 ASyne Input Syne 6 __ SSyne Output SSyme 5 CKSM 4 CK20M EN RSMK 2 LastRow 1 LastCol O MxFirst 2 2 4 ID CODE Register The Device Identification register is implemented is this third version It is 32 bits long and has fixed value hardwired into the chip When selected by the ID_COD

EUDET-Memo-2007-45

Contents

Download Pdf Manuals

Related Search

Related Contents