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P0159 Datasheet - Mouser Electronics

1. Soe 61 DO AO 64 5 4 SDRAM TEST BY NIOS aote Vo vor diea 66 EE 69 3 0 TY BOX DEMONSTRATION 71 57 PS2 MOUSE DEMONSTRATION 74 5 8 IR EMITTER LED AND RECEIVER DEMONSTRATION 76 82 CHAPTERG 5 5 Feu 85 WTA 85 87 I o Ce BEES ICA HN OA 93 96 CHAPTER7 EXAMPLES FOR USING BOTH HPS SOC AND FGPA 99 1 1 HPS CONTROL LED AND HEX
2. 10 4 Switch x 10 4 Button x 4 TXJRX VI VGA 4 Video In 4 Audio 4 SDRAM 32MB PS2 uh iss De GPIO 0 Header w None Prefix Name GPIO 1 Header None Prefix Name Figure 4 4 System Configuration Group B GPIO Expansion Users can connect GPIO daughter cards onto the GPIO connector located on the development board shown in Figure 4 5 Select the daughter card you wish to add to your design under the appropriate GPIO connector to which the daughter card 15 connected The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard 27 DE1 SoC User Manual www terasic com JA DTE RYAN DE1 SoC V1 0 0 UNIVERSITY PROGRAM System Configuration Project Name WwW Ceresic com DE SOc DE1 SoC Board CLOCK 4 Seqment x 6 10 W Switch x 10 Button x 4 VIR TXJRX MI NGA Video In 4 Audio 4 SDRAM 32MB v PS2 GPIO 0 Header D5M bM Pixel Camera Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 5 GPIO Expansion Group The Prefix Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty B Proje
3. 0E 4 Figure 2 2 Development Board bottom view DEI SoC board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board B FPGA e Altera Cyclone SE SCSEMASF31C6N device e Altera Serial Configuration device EPCQ256 USB Blaster II on board for programming JTAG Mode 64MB SDRAM 16 bit data bus e 4 Push buttons e 10 Slide switches 10 Red user LEDs e Six 7 segment displays e Four 50MHz clock sources from clock generator 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 8 bit high speed triple DACs with VGA out connector Decoder NTSC PAL SECAM and TV in connector 5 2 mouse keyboard connector receiver and IR emitter e Two 40 pin Expansion Header with diode protection e A D Converter 4 pin SPI interface with FPGA 6 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN HPS Hard Processor System e 800MHz Dual core ARM Cortex A9 MPCore processor DDR3 SDRAM 32 bit data bus Gigabit Ethernet PHY with RJ45 connector 2 port USB Host Normal Type A USB connector e Micro SD card socket e Accelerometer I2C interface interrupt UART to USB USB Mini B connector e Warm reset button and cold reset button e user button and one use
4. 50 USER MANUAL P d sO of p Rig 5 ui s E ATERA UNIVERSITY www terasic com PROGRAM Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved CONTENTS 1 DEI SOC DEVELOPMENT KIT sicssssssseseisecevsrcscsestecstessnsssssdednavedcvoecsasseckssssaseesssseedecoeaccuessissedesndeceouss 3 IB OI 3 Vire 4 HPE 4 2 INTRODUCTION OF THE DE1 SOC BOARD eee eeee eene neon eee eee eee eee etat ena ones esee eee eee ee esee eterna 5 2 IM AYOUTANDEC ONPONENTS hd bros doni On M 5 22 BLOCK DIAGRAM THE DE1 SOC BOARD aito 7 CHAPTERS USING IHE DEISSOC BOARD 10 Dh TOCA OE UU 10 221 FPGA CONFIGURATION MODE SETTING Ha aU Ete 10 3 12 HPS BOOTSBILZANDCTISSBE SETTING 11 3 2 CONFIGURING THE CYCLONE V SOC 13 2 BOARD STATUS ELEMENTS seem cies eerste 18 ABOARD RESEPT ELEMENT nr
5. LSB LSB LSB LSB 4 5 Address Address Logical Inverse Command Command Logical Inverse IQ e 08 00 27ms 27ms p 67 5ms Figure 5 14 Typical frame of NEC protocol Note IR Receiver receives the signal a inverted value e g IR TX Controller send a lead code 9 ms high then 4 5 ms low IR Receiver will receive a 9 ms low then 4 5 ms high lead code B IR Remote When a key on the remote controller See Figure 5 15 15 pressed the remote controller will emit a standard frame shown in Table 5 6 The beginning of the frame is the lead code represents the start bit and then is the key related information and the last bit end code represents the end of the 78 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RA frame This frame 15 descript the signal which IR Receiver Received 0 o O O MENU RETURN MSS 5 O 9 Lv PLAY ADJUST Figure 5 15 Remote controller Table 5 6 Key code information for each Key on remote controller Key Code Key Code Key Code Key Code 79 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYA End Inv Key Code Lead Code 1bit Custom Code 16bits Key Code 8bits 8bits Figure 5 16 The transmitting frame of the IR remote controller IR RX Controller In this demo the of IR receiver controller 15 im
6. 5 5 5 5 55 JNO S8 RAN D22 PPS SPIM MOSI HPS SPIM MISO Cyclone y E24 LTC SoC HPS I2C2 SDAT Connector HPS I2C2 SCLK H23 HPS HPS LTC GPIO H17 U41 HPS SPIM MOSI i aw HPS 12 2 SDAT MOSI_SDA HPS_SPIM_CLK 5 12 2 5 HPS LTC GPIO TS3A5018 Figure 3 36 Connections between the LTC Connector and HPS Table 3 35 LTC Connector Pin Assignments FPGA Pin Description VO Standard HPS LTC GPIO PIN H17 HPS LTC GPIO HPS 2 2 SCLK HPS 2 2 Clock share bus with 3 3V G Sensor HPS 2 2 SDAT HPS 2 2 Data share bus with 3 G Sensor 3V 5 23 SPI Clock HPS_SPIM_MISO PIN E24 SPI Master Input Slave Output HPS SPIM MOSI D22 Master Output Slave Input HPS SPIM SS 024 SPI Slave Select 52 Terasic DE1 SoC User Manual www terasic com Chapter 4 DE 1 SoC System Builder This chapter describes how users can create a custom design project on the board by using the DEI SoC Software Tool DEI SoC System Builder 4 1 Introduction The DEI SoC System Builder is a Windows based software utility designed to assist users to create a Quartus II project for the board within minutes The generated Quartus II project files include e Quartus II Project File qpf e Quartus II Setting File qsf Top Level Design File v Synopsis Design Constraints file sdc e Pin Assignme
7. 5 5 00000000 none gt m Auto Detect Delete Change File Lab Save File tt up pu Down Figure 8 6 Quartus programmer window with two detected devices 109 1 5 DE1 SoC User Manual www terasic com www terasic com File Edit View Processing Tools Window Help 5 Search altera Enable real time ISP to allow background programming for MAX and MAX V devices xh File Device Checksum Usercode Program Verify Blank Configure h Factory default enhanced SCSXFCED6ES 00 64585 00 64585 P D output file jic EPCQ256 5715BBFC 3 Auto Detect lt gt SOCVHPS 00000000 none gt Delete Change File C as Save File Figure 8 7 Quartus programmer window with one JIC file 8 4 Erase the Quad Serial Configuration Device To erase the existed file in the serial configuration device follow the steps listed below Choose Programmer Tools menu and the Chain cdf window appears Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 Double click the green rectangle region as shown in Figure 8 6 the Select New Programming File page will appear and then select the correct JIC file Erase the serial configuration device by clicking the corresponding Erase b
8. 255IDRVR HPS USB DIR USBUP DM 7 SUP DM HPS USB STP USBUP DP USBUP DP HPS USBDN1_DP cm USBPHY_CLK_24 USBDN1 DM E USB USBDN2 DM USB3300 USBHUB_CLK_24 USB Type A U30 XTALIN CLKIN PS RESET n ADM812 Figure 3 34 Connections between Cyclone V SoC FPGA and USB OTG PHY Table 3 33 USB OTG PHY Pin Assignments Signal Name FPGA Pin No Description Standard HPS USB CLKOUT PIN N16 60MHz Reference Clock Output 3 3V HPS USB DATA 0 PIN E16 HPS USB DATA 0 3 3V HPS USB DATA 1 PIN G16 HPS USB DATA 1 3 3V HPS USB DATA 2 PIN D16 HPS USB DATA 2 3 3V HPS USB DATA 3 PIN D14 HPS USB DATA 3 3 3V HPS USB DATA 4 PIN A15 HPS USB DATA 4 3 3V HPS USB DATA 5 PIN C14 HPS USB DATA 5 3 3V HPS USB DATA 6 PIN D15 HPS USB DATA 6 3 3V HPS USB DATA 7 PIN M17 HPS USB DATA T7 3 3V HPS USB DIR PIN E14 Direction of the Data Bus 3 3V HPS USB NXT PIN A14 Throttle the Data 3 3V HPS USB RESET PIN G17 HPS USB PHY Reset 3 3V HPS USB STP PIN C15 Stop Data Stream on theBus 3 3V 3 8 G Sensor The board is equipped with a digital accelerometer sensor module The ADXL345 16 a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit twos complement and can be accessed using I2C interface The address of the G Sensor device is OxA6 OxA7 For more detailed information of better using this chip please refer to
9. Click OK The Convert Programming Files page displays See Figure 8 5 Click Generate 106 Terasic DE1 SoC User Manual www terasic com www terasic com Arria GX Arria II GX Arria II GZ Arria V Arria V GZ Cyclone Cyclone 1 Cyclone 15 Cydone IVE Cydone Iv Cydone v HardCopy Hardcopy III HardCopy IV MAXI scexFc7D6 scGxFC7D6ES 5cGxFC7D7 SCGXFC7D7ES Export 5CGXFC9A6 SCGXFC9A7 Edit sccxrcece scGxFC9c7 s5ccxrcepe Uncheck All C scaxrcop7 scaxrcoEe6 1 scaxrcse7 5 5 6 1 SCSEBASES 1 2 sScsxFcecsEs Remove Figure 8 4 Select Devices Page 107 12 51 DE1 SoC User Manual www terasic com www terasic com You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Indirect Configuration File jic Options Configuration device Mode Active Serial x4 File name D de 1 soc trunk cd CD HW revA Demonstrations FPGA DE 1 SoC Default output file jic am Advanced Remote Local update difference file NONE Create Memory Map File Generate output_file map Create
10. files Generate output_file periph jic and output file core rbf Input files to convert File Data area Properties Start Address Add Hex Data 4 Flash Loader e SCSXFC6D6ES sor Page 4 SOF Data Page 0 DE1_SoC_Default sof SCSXFC6D6F31ES Figure 8 5 Convert Programming Files Page 8 3 Write JIC File into Quad Serial Configuration Device To program the serial configuration device with the JIC file that you just created add the file to the Quartus Programmer window and follow the steps When the SOF to JIC file conversion is complete add the JIC file to the Quartus Programmer window Choose Programmer Tools menu and the Chain cdf window appears Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 Double click the green rectangle region as shown in Figure 8 6 the Select New Programming File 108 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RYAN page will appear and then select the correct JIC file Program the serial configuration device by clicking the corresponding Program Configure box a factory default SFL image will be loaded See Figure 8 7 Click Start to program serial configuration device SACER Enable real time ISP to allow background programming for MAX II and MAX V devices Device Checksum Usercode Proaram Verify eth Start 5 5 6 6 5 00000000 none
11. www terasic com SD_CLK SD_CMD D Socket Cyclone V SoC iim 11 gg m i 4 Figure 3 33 Connections between Cyclone SoC FPGA and SD Card Socket Table 3 32 SD Card Socket Pin Assignments Signal Name FPGA Pin No Description Standard HPS SD CLK PIN A16 HPS SD Clock 3 3V HPS SD CMD PIN F18 HPS SD Command Line 3 3V HPS SD DATA O0 PIN G18 HPS SD Data 0 3 3V HPS SD DATA 1 PIN C17 HPS SD Data 1 3 3V HPS SD DATA 2 PIN D17 HPS SD Data 2 3 3V HPS SD DATA 3 PIN B16 HPS SD Data 3 3 3V 3 7 7 2 port USB Host The board provides 2 port USB 2 0 host interfaces using the SMSC USB3300 controller and 2 port hub controller A SMSC USB3300 device in a 32 pin package device 15 used to interface to a SMSC USB2512B This device supports UTMI Low Pin Interface ULPI to communicate to USB 2 0 controller in HPS By connecting the ID pin of USB3300 to ground the PHY operates in Host mode When operating in Host mode the interface will supply the power to the device through the 2 port USB type A interface Figure 3 34 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 3 33 49 Terasic DE1 SoC User Manual www terasic com www terasic com U9 HPS_USB_DATAJ7 0 USB CPEN USB VCC5 Sa CLKOUT EXTVBUS SS FAULT_N S RAN HPS USB NXT NXT VBUS USB VBUS
12. XGA 85Hz 1280x1024 60Hz VGA mode Configuration VGA 60Hz VGA 85Hz SVGA 60Hz SVGA 75Hz SVGA 85Hz XGA 60Hz XGA 70Hz XGA 85Hz 1280 1024 60 2 sync Figure 3 21 VGA horizontal timing specification Table 3 17 VGA Horizontal Timing Specification Horizontal Timing Spec Resolution HxV 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a us 3 8 1 6 3 2 1 6 1 1 2 1 1 8 1 0 1 0 b us 1 9 2 2 2 2 3 2 2 7 2 5 1 9 2 2 2 3 5 25 4 17 8 20 16 2 14 2 15 8 13 7 10 8 11 9 d us 0 6 1 6 1 0 3 0 6 0 4 0 3 0 5 0 4 Table 3 18 VGA Vertical Timing Specification Vertical Timing Spec Resolution HxV 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a lines b lines c lines d lines OW 33 Terasic DE1 SoC User Manual www terasic com 33 25 23 21 27 29 29 36 38 480 480 600 600 600 768 768 768 1024 10 Pixel clock MHz Pixel clock MHz 25 www terasic com Signal Name VGA_R 0 VGA RI 1 VGA RI 2 VGA VGA 4 VGA 5 VGA RI6 VGA RI7 VGA 0 VGA G 1 VGA 2 VGA G 3 VGA 4 VGA G 5 VGA 6 VGA GI 7 VGA VGA VGA BI VGA VGA 4 VGA BI5 VGA 6 VGA BI7 VGA CLK VGA BLANK N VGA HS VGA VS VGA SYNC N Table 3 19 Pin Assignments for VGA FPGA Pin No PIN A13 PIN C13 PIN E13 PIN
13. 1 EOSC1 pin range 10 50MHz 10 12 5MHz 12 5 25MHz 25 50MHz sdmmc cclk out device 1 clk 128 1 clk 32 1 clk 64 1 clk 128 ID mode clock 391 KHz 391 KHz 391 KHz max 391 KHz max Controller baud rate divisor 32 32 32 32 Dat sdmmc cclk out device 1 clk 4 391 Osc1 clk 1 1 clk 2 1 clk 4 n clock 12 5 2 max 12 5 2 12 5MHzmax 12 5MHz max Controller baud rate divisor mode 1 1 1 1 svemnuimbers only bypass bypass bypass bypass controller clock wed EM MSc 2 50MHz max 50MHz max 50MHz max impu Osc1 1 clk 32 1 clk 16 1 clk 8 50MHz 400 400MHz max 400MHz max PLL modes Bypassed Locked Locked Locked Table 3 5 SW16 HPS BOOTSEL and CLKSEL Setting Board Reference Signal Name Description Default SW16 1 BOOTSELO Off e ed Sets the Cyclone V BOOTSEL 2 0 and n ets the Cyclone 0 an SW16 BOOTSEL2 ff 5 CLOCKSEL 1 0 pins 2 SW16 4 CLOCKSELO On SW16 5 CLOCKSEL1 On SW16 6 N A N A N A 12 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN 3 2 Configuring the Cyclone SoC FPGA The DEI SoC board contains a serial configuration device that stores configuration data for the Cyclone V SoC FPGA This configuration data 1s automatically loaded from the configuration device into the FPGA every time while power is applied to th
14. In addition users can use the PS 2 keyboard and mouse the DE1 SoC board simultaneously by plugging an extension PS 2 Y Cable See Figure 3 27 Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational websites The pin assignments for the associated interface are shown in Table 3 24 Q Note If users connect only one PS 2 equipment the PS 2 interface between FPGA 1 0 should be 52 CLK and PS2 DAT 39 wwwW terasic com Terasic DE1 SoC User Manual www terasic ADT PS2 CLK IS Ps2 JNO YAN Soc 2_ 2 PS2_DAT Figure 3 26 Connection between FPGA and PS 2 A 5 Figure 3 27 Y Cable use for both Keyboard and Mouse Table 3 24 PS 2 Pin Assignments FPGA Pin No Description Standard PIN AD7 PS 2 Clock 3 3V AE7 PS 2 Data 3 9 PS 2 Clock reserved for second PS 2 device 3 AEQ 5 2 Data reserved for second PS 2 device 3 3V 40 Terasic DE1 SoC User Manual www terasic com www terasic com JA DTE RYAN 3 6 12 A D Converter and 2x5 Header The DEI SoC contains AD7928 lower power eight channel CMOS 12 bit analog to digital converter This A to D provides conversion throughput rates up to IMSPS It can be configured to accept eight input signals at inputs ADC_INO through ADC_IN7 This eight input signals are connected to the 2x5 head
15. Rid Legale 99 CHAPTER 8 STEPS OF PROGRAMMING THE QUAD SERIAL CONFIGURATION DEVICE 103 8 1 BEFORE YOU 42 55405 4 103 a 103 9 3 WRITE JIC FILE INTO QUAD SERIAL CONFIGURATION DEVICE 0 0 0 0 2 0 0000000 108 9 4 ERASE THE QUAD SERIAL CONFIGURATION DEVICE 0 00 000001 110 112 S MUNI Ea ES A SLOT HI TONT EE 112 9 2 COPYRIGHT STATEMENT cccscescscescscescsceccscescscnccecsccececcscscescscscscscscssescnsescssescsseecssescssescscescscesescesescesescusescesecs 112 2 Terasic DE1 SoC User Manual www terasic com Chapter 1 DE71 SoC Development Kit The DE1 SoC Development Kit presents a robust hardware design platform built around the Altera System on Chip SoC FPGA which combines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC int
16. 1 26 PIN AK22 GPIO Connection 1 26 3 3V GPIO 1 27 PIN AJ22 GPIO Connection 1 27 3 3V GPIO 1 28 PIN 22 GPIO Connection 1 28 3 3V GPIO 1 29 PIN AG22 GPIO Connection 1 29 3 3V GPIO 1 30 PIN AF24 GPIO Connection 1 30 3 3V GPIO 1 31 PIN AF23 GPIO Connection 1 31 3 3V GPIO 1 32 PIN AE22 GPIO Connection 1 32 3 3V GPIO 1 33 PIN AD21 GPIO Connection 1 33 3 3V GPIO 1 34 PIN AA20 GPIO Connection 1 34 3 3V GPIO 1 35 PIN AC22 GPIO Connection 1 35 3 3V 3 6 4 Using the 24 bit Audio CODEC The DEI SoC board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC Encoder Decoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WMS731 is controlled via by a serial I2C bus which 15 connected to HPS or Cyclone V SoC FPGA through a I2C multiplexer A schematic diagram of the audio circuitry is shown in Figure 3 18 and the FPGA pin assignments are listed in Table 3 15 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s website in the DEI SOC datasheetsNAudio CODEC folder on the DEI SoC System CD 29 www terasic com Terasic DE1 SoC User Manual www terasic com ANU S RYA Cyclone SoC WMS8731 LE XTI MCLK AUD_BCLK BCLK AUD_DACDAT DACDAT AUD_DACLRCK DACLRCK AUD_ADCDAT ADCDAT AUD_ADCLRCK ADCLRCK Figure 3 18 Connections between FPGA and Au
17. 1 lists the settings for selecting a suitable boot source The default boot source for the HPS is from SD card with fixing BOOTSEL 2 0 101 HPS flash controller clock frequency can be set using CLOCKSEL signal Table 3 3 lists the setting for SD MMC controller CLOCKSEL pins The default CLOCKSEL setting is CLOCKSEL 1 0 00 If users need to change BOOTSEL 2 0 and CLOCKSEL 1 0 setting since we make our schematic layout flexible users can change BOOTSEL 2 0 CLOCKSEL 1 0 Change the BOOTSEL and CLOCKSEL resistors on the board e By soldering or removing the resistors R97 R100 106 111 will change the value of BOOTSEL and CLOCKSEL e Adda dip switch SW16 on the board Solder SW16 R97 R98 R107 and remove R99 R100 R110 will let MSEL 4 0 value to be changed by switching SW16 Table 3 4 shows the switch controls and descriptions for MSEL Table 3 3 BOOTSEL 2 0 Setting Values and Flash Device Selection BOOTSEL 2 0 Setting Value Flash Device 000 Reserved 001 FPGA HPS to FPGA bridge 11 DE1 SoC User Manual www terasic com www terasic com 010 1 8 NAND Flash memory 1 011 3 0 NAND Flash memory 1 100 1 8 V SD MMC Flash memory 1 101 3 0 V SD MMC Flash memory 110 1 8 V SPI or quad SPI Flash memory 1 111 3 0 V SPI or quad SPI Flash memory 1 Not supported on DEI SoC board Table 3 4 SD MMC Controller CSEL Pin Settings CSEL Pin Setting 0 1 2 3
18. 3 SDRAM Address 3 13 3 SDRAM Address 4 SDRAM Address 5 13 3 SDRAM Address 6 13 3 SDRAM Address 7 13 3 SDRAM Address 8 13 3 SDRAM Address 9 23 3 SDRAM Address 10 3 39V SDRAM Address 11 13 3 SDRAM Address 12 3 3 SDRAM Data 0 33V SDRAM Data 1 SDRAM Data 2 33V SDRAM Datea 3 q3 39V SDRAM Data 4 13 3 SDRAM Data 5 43 3V SDRAM Data 6 3 3 38 www terasic com ANU RYA DRAM DQ 7 PIN AJ11 SDRAM Data 7 3 3V DRAM DQ 8 PIN AH10 SDRAM Data 8 3 3V DRAM DQ 9 PIN AJ10 SDRAM Data 9 3 3V DRAM DQ 10 PIN AJ9 SDRAM Data 10 3 3V DRAM DOQ 11 PIN AH9 SDRAM Data 11 3 3V DRAM DQ 12 PIN 8 SDRAM Data 12 3 3V DRAM DQ 13 PIN AH7 SDRAM Data 13 3 3V DRAM DOQ 14 PIN AJ6 SDRAM Data 14 3 3V DRAM DQ 15 PIN AJ5 SDRAM Data 15 3 3V DRAM BA 0 PIN AF13 SDRAM Bank Address 0 3 3V DRAM 1 AJ12 SDRAM Bank Address 1 3 3V DRAM LDQM PIN 13 SDRAM byte Data Mask 0 3 3V DRAM_UDQM PIN AK12 SDRAM byte Data Mask 1 3 3V DRAM RAS N PIN AE13 SDRAM Row Address Strobe 3 3V DRAM CAS AF11 SDRAM Column Address Strobe 3 3V DRAM CKE PIN AK13 SDRAM Clock Enable 3 3V DRAM CLK PIN AH12 SDRAM Clock 3 3V DRAM WE N PIN AA13 SDRAM Write Enable 3 3V DRAM CS N PIN 11 SDRAM Chip Select 3 3V 3 6 11 PS 2 Serial Port The DEI SoC board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 26 shows the schematic of the PS 2 circuit
19. DDR3 DQ 2 HPS DDR3 DQ 3 HPS DDR3 4 HPS DDR3 DQ 5 HPS DDR3 DQ 6 HPS DDR3 DQ 7 HPS DDR3 DQ HPS DDR3 DQ 9 HPS DDR3 DQ 10 HPS DDR3 11 HPS DDR3 DQ 12 HPS DDR3 DQ 13 HPS DDR3 14 HPS DDR3 DQ 15 HPS DDR3 16 HPS DDR3 DQ 17 HPS DDR3 18 HPS DDR3 DQ 19 HPS DDR3 DQ 20 HPS DDR3 DQ 21 HPS DDR3 DQ 22 HPS DDR3 23 HPS DDR3 DQ 24 HPS DDR3 DQ 25 HPS DDR3 DQ 26 HPS DDR3 27 PIN C30 PIN B30 PIN C29 PIN H25 PIN E29 PIN J24 PIN J23 PIN E27 PIN L29 PIN L23 PIN M23 PIN H24 PIN K28 PIN M28 PIN R28 PIN W30 PIN K23 PIN K22 PIN H30 PIN G28 PIN L25 PIN L24 PIN J30 PIN J29 PIN K26 PIN L26 PIN K29 PIN K27 PIN M26 PIN M27 PIN L28 PIN M30 PIN U26 PIN T26 PIN N29 PIN N28 PIN P26 PIN P27 PIN N27 PIN R29 PIN P24 PIN P25 PIN T29 PIN T28 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 HPS DDR3 Data Mask 3 HPS DDR3 Data 0 HPS DDR3 Data 1 HPS DDR3 Data 2 HPS DDR3 Data 3 HPS DDR3 Data 4 HPS DDR3 Data 5 HPS DDR3 Data 6 HPS DDR3 Data 7 HPS DDR3 Data 8 HPS DDR3 Data 9 HPS DDR3 Data 10 HPS DDR3 Data 11 HPS DDR3 Data 12 HPS DDR3 Data 13 HPS D
20. Here 15 the main program of this Hello World demo 85 Terasic DE1 SoC User Manual www terasic com www terasic com finclude lt stdio h gt int wainfint argc char argv 1 printf Hello World sr im returni 0 J B Makefile To compile a project a Makefile is required Here is the Makefile used for this demo TARGET my first CROSS COMPILE arm linux gnueabihf CFLAGS g Wall I SOCEDS DEST ROOT ip altera hps altera hpa hwlib include LDFLAGS g Wall CROSS COMPILE arm 0 build TARGET TARGET main o CC LDFLAGS o 8 c 0 8 CFLAGS c F lt PHONY clean clean rm TARGET f 0 B Compile To compile a project please launch Altera SoC EDS Command Shell by executing C altera 13 0 embedded Embedded_Command_ Shell bat Use the cd command to change the current directory to where the Hello World project is located Then type make to build the project The executable my first hps will be generated after the compiling process is finished The clean all command can be used to remove all temporary files 86 Terasic DE1 SoC User Manual www terasic com www terasic com Demonstration Source Code e Build Tool Altera SoC EDS v13 0 e Project directory Demonstration SoC my_first_hps Binary file my_first_hps e Build Command make make clean to remove all temporary f
21. LEES SEE MEE 41 3 7 INTERFACE ON HARD PROCESSOR SYSTEM HPS seeeseeeseeeeenn n ee enne nnne enne hne nnne sr e rne e enne 42 OUI USER PUSHBUTTON AND LEDON HPS MEE nS 42 SEPA GO T SUUS IN 43 WA Bw 44 Osce c 45 E 47 1 DE1 SoC User Manual www terasic com ANU RYAN ORO D NNMERO 48 I I M M M i M 49 NE EIE RU 50 SM MS MB eO gt E 51 CHAPTER 4 DEI SOC SYSTEM BUILDER ccccccccccccccssccccccccccccccccccccccccccccsccccccccccccccccccccccceccccccccccccceccccocsocces 53 ZR We WANTS OE TON 53 4 2 GENERAL DESIGN FLOW ccceccscesceccecceccsccceccecescescccsccsceecscescecesceecsecsceecescescsscscescscsscsctscecescssescescescesessescesceses 53 DEISOC SYSTEM E 54 CHAPTERS EXAMPLES FOR FPGA ssseseseseseseoececscscscsesesecseoeceseoeocoscscseseseseseseseceseceososesesesesesesesesesssssscseseseseseses 60 S I DBISOCPACTORY CONFIGURATION aE ANE REENA AN 60 5 2 AUDIO RECORDING AND
22. Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 33 Terasic DE1 SoC User Manual www terasic com JA DTE RYAN DE1 SoC V1 0 0 2 UNIVERSITY PROGRAM WW Cerasic com System Configuration DE1 SoC Board CLOCK 4 Seqment x 6 10 v Switch x 10 Button x 4 v IR TXJRX vI VGA v Video In 4 Audio ADC SDRAM 32MB PS2 GPIO 0 Header Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 3 Board Type and Project Name System Configuration Under the System Configuration users are given the flexibility of enabling their choice of included components on the board as shown in Figure 4 4 Each component of the board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled DEI SoC System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard 56 Terasic DE1 SoC User Manual www terasic com JA DTE RYAN DE1SoC V1 0 0 X ATERA Pasic UNIVERSITY PROGRAM www terasic com System Configuration Project Name DEI SOC DE1 SoC Board CLOCK 4 Seqment x 6
23. are the exact same devices connected to the FPGA in capacity IGB and data width 32 bit comprised of two x16 devices with a single address command bus This interface connects to dedicate Hard Memory Controller for HPS I O banks and the target speed is 400 MHz Table 3 30 lists DDR3 pin assignments I O standards and descriptions with Cyclone V SoC FPGA Table 3 30 Pin Assignments for DDR3 Memory Signal Name FPGA Pin No Description Standard HPS DDR3 A 0 PIN F26 HPS DDR3 Address 0 SSTL 15 Class HPS DDR3_A 1 PIN_G30 HPS DDR3 Address 1 SSTL 15 Class HPS DDR3_A 2 28 HPS DDR3 Address 2 SSTL 15 Class HPS DDR3_A 3 PIN_F30 HPS DDR3 Address 3 SSTL 15 Class HPS DDR3_A 4 PIN_J25 HPS DDR3 Address 4 SSTL 15 Class HPS DDR3_A 5 PIN_J27 HPS DDR3 Address 5 SSTL 15 Class HPS DDR3_A 6 PIN_F29 HPS DDR3 Address 6 SSTL 15 Class HPS DDR3 A T7 PIN E28 HPS DDR3 Address 7 SSTL 15 Class HPS DDR3_A 8 PIN_H27 HPS DDR3 Address 8 SSTL 15 Class HPS DDR3_A 9 PIN_G26 HPS DDR3 Address 9 SSTL 15 Class HPS DDR3 A 10 PIN D29 HPS DDR3 Address 10 SSTL 15 Class 45 Terasic DE1 SoC User Manual www terasic com www terasic HPS 11 5 DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 BA 0 HPS DDR3 BA 1 HPS DDR3 BA HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n HPS DDR3 5 DDR3 HPS DDR3 DM 2 HPS DDR3 DM 3 HPS DDR3 DQ O HPS DDR3 DQ 1 HPS
24. 0 output file jic Remote Local update difference file NONE Create Memory Map File Generate output file map Create files Generate output file periph jic and output file core rbf File Data area Flash Loader SOF Data Figure 8 2 Convert Programming Files Dialog Box Click Add File Select the SOF that you want to convert to a JIC file Click Open Highlight the Flash Loader and click Add Device See Figure 8 5 Click OK The Select Devices page displays 105 Terasic DE1 SoC User Manual www terasic com www terasic com You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Indirect Configuration File r Confowatondewces 8000088 File name Advanced Remote update difference file NONE Create Memory File Generate output file map Create files Generate output file periph jic and output file core rbf Input files to convert File Data area Start Address Flash Loader 4 SOF Data 0 lt auto gt DE 1_SoC_Default sof SCSXFC6D6F31ES Down Properties Figure 8 3 Highlight Flash Loader Select the targeted FPGA that you are using to program the serial configuration device See Figure 8 4
25. 17 GPIO 0 18 GPIO 0 19 GPIO 0 20 GPIO 0 21 GPIO 0 22 GPIO 0 23 GPIO 0 24 GPIO 0 25 GPIO 0 26 GPIO 0 27 GPIO 0 28 GPIO 0 29 GPIO 0 30 GPIO 0 31 GPIO 0 32 GPIO 0 33 GPIO 0 34 GPIO 0 35 GPIO 1 0 GPIO 1 1 GPIO 1 2 GPIO 1 3 GPIO 1 4 GPIO 1 5 GPIO 1 6 GPIO 1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 PIN AK16 PIN AK18 PIN AK19 PIN AJ19 PIN AJ17 PIN AJ16 PIN AH18 PIN AH17 PIN AG16 PIN AE16 PIN AF16 PIN AG17 PIN AA18 PIN AA19 PIN AE17 20 19 AJ20 20 21 AD19 AD20 18 19 20 21 19 21 18 20 18 AJ21 17 21 21 AC23 AD24 23 24 25 26 AG25 26 24 GPIO Connection 0 4 GPIO Connection 0 5 GPIO Connection O 6 GPIO Connection 0 7 GPIO Connection O 8 GPIO Connection O 9 GPIO Connection 0 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection 0 16 GPIO Connection 0 17 GPIO Connection 0 18 GPIO Connection 0 19 GPIO Connection 0 20 GPIO Connection 0 21 GPIO Connection 0 22 GPIO Connection 0 23 GPIO Connection 0 24 GPIO Connection 0 25 GPIO Connection 0 26 GPIO Connection 0
26. 27 GPIO Connection 0 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1 9 GPIO Connection 1 10 GPIO Connection 1 11 28 Terasic DE1 SoC User Manual www terasic com 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com GPIO 1 12 27 GPIO Connection 1 12 3 3V GPIO 1 13 PIN AJ27 GPIO Connection 1 13 3 3V GPIO 1 14 PIN AK29 GPIO Connection 1 14 3 3V GPIO 1 15 PIN AK28 GPIO Connection 1 15 3 3V GPIO 1 16 PIN AK27 GPIO Connection 1 16 3 3V GPIO 1 17 PIN AJ26 GPIO Connection 1 17 3 3V GPIO 1 18 PIN AK26 GPIO Connection 1 18 3 3V GPIO 1 19 PIN AH25 GPIO Connection 1 19 3 3V GPIO 1 20 PIN AJ25 GPIO Connection 1 20 3 3V GPIO 1 21 PIN AJ24 GPIO Connection 1 21 3 3V GPIO 1 22 PIN AK24 GPIO Connection 1 22 3 3V GPIO 1 23 AG23 GPIO Connection 1 23 3 3V GPIO 1 24 PIN AK23 GPIO Connection 1 24 3 3V GPIO 1 25 AH23 GPIO Connection 1 25 3 3V GPIO
27. B12 PIN C12 PIN D12 PIN E12 PIN F13 PIN J9 PIN J10 PIN H12 PIN G10 PIN G11 PIN G12 PIN F11 PIN E11 PIN B13 PIN G13 PIN H13 PIN F14 PIN H14 PIN F15 PIN G15 PIN J14 PIN A11 PIN F10 PIN B11 PIN D11 PIN C10 3 6 7 TV Decoder The DEI SoC board is equipped with an Analog Device ADV7180 TV decoder chip The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signals NTSC PAL and SECAM into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras Terasic DE1 SoC User Manual www terasic com Description VGA Red 0 VGA Red 1 VGA Red 2 VGA Red 3 VGA Red 4 VGA Red 5 VGA Red 6 VGA Red 7 VGA Green 0 VGA Green 1 VGA Green 2 VGA Green 3 VGA Green 4 VGA Green 5 VGA Green 6 VGA Green 7 VGA Blue 0 VGA Blue 1 VGA Blue 2 VGA Blue 3 VGA Blue 4 VGA Blue 5 VGA Blue 6 VGA Blue 7 VGA Clock VGA BLANK VGAH SYNC VGAV SYNC VGA SYNC 34 Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com ANU RYAN The registers in the TV decoder can be programmed by serial I2C bus which is connected t
28. Blaster II Normal type B USB connector Memory Device 64MB 32Mx16 SDRAM on FPGA GB 2x256Mx16 DDR3 SDRAM on HPS 128MB QSPI Flash on HPS e Micro SD Card Socket on HPS Communication e Two Port USB 2 0 Host ULPI interface with USB type A connector UART to USB USB connector 10 100 1000 Ethernet e 5 2 mouse keyboard Emitter Receiver 2 Multiplexer Connectors e Two 40 pin Expansion Headers e One 10 pin ADC Input Header One LTC connector One Serial Peripheral Interface SPI Master I2C and one GPIO interface Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN Display 24 bit VGA DAC Audio e 24 bit CODEC Line in line out and microphone in jacks Video Input Decoder NTSC PAL SECAM and TV in connector Switches Buttons and Indicators e 5 User Keys FPGA x4 HPS x1 e 10 User switches FPGA x10 11 User LEDs FPGA x10 HPS x 1 e 2 HPS Reset Buttons HPS RESET n HPS WARM RST n e Six 7 segment displays Sensors G Sensor on HPS Power 12V DC input Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 3 Using the DE1 SoC Board This chapter gives instructions for using the board and describes each of its peripherals 3 1 Board Setup This section will explain the settings of FPGA configuration modes HPS boot source select and HPS flash cont
29. CLK PIN 23 2 Clock of the first HPS 2 concontroller 2 1 SDAT C24 12C Data of the first HPS 12C concontroller 3 HPS I2C2 SCLK 2 Clock of the second HPS 2 concontroller HPS I2C2 SDAT 5 2 Data of the second HPS 2 concontroller 3 3V 3 6 6 VGA DEI SoC board includes 15 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone V SoC FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC only the higher 8 bits are used 16 used to produce the analog data signals red green and blue It could support the SXGA standard 1280 1024 with a bandwidth of 100MHz Figure 3 20 gives the associated schematic 31 DE1 SoC User Manual www terasic com www terasic com R 7 0 G 7 0 UT hs VGA_B 7 0 ATERA VGA_CLK ao ADV7123 We soc VGA_SYNC_N VGA BLANK VGA VS VGA HS Figure 3 20 VGA Connections between FPGA and VGA The timing specification for VGA synchronization and RGB red green blue data can be found on various educational website for example search for signal timing Figure 3 20 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronizatio
30. DR3 Data 14 HPS DDR3 Data 15 HPS DDR3 Data 16 HPS DDR3 Data 17 HPS DDR3 Data 18 HPS DDR3 Data 19 HPS DDR3 Data 20 HPS DDR3 Data 21 HPS DDR3 Data 22 HPS DDR3 Data 23 HPS DDR3 Data 24 HPS DDR3 Data 25 HPS DDR3 Data 26 HPS DDR3 Data 27 46 Terasic DE1 SoC User Manual www terasic com SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class www terasic com HPS DDR3_DQ 28 HPS DDR3 DQ 29 HPS DDR3 DQ 30 HPS DDR3 31 HPS DDR3 DOS n 0 HPS DDR3 DOS n 1 HPS DDR3 DOS n 2 HPS DDR3 DOS n 3 HPS DDR3 DOS p 0 HPS DDR3 DOS 1 HPS DDR3 DOS p 2 HPS DDR3 DOS p 3 HPS DDR3 ODT HPS DDR3 RAS n HPS DDR3 RESET n HPS DDR3 WE n HPS DDR3 RZQ PIN R27 PIN R26
31. Digit O 2 Seven Segment Digit 0 3 Seven Segment Digit 0 4 Seven Segment Digit 0 5 Seven Segment Digit O 6 Seven Segment Digit 1 0 Seven Segment Digit 1 1 Seven Segment Digit 1 2 Seven Segment Digit 1 3 Seven Segment Digit 1 4 Seven Segment Digit 1 5 Seven Segment Digit 1 6 Seven Segment Digit 2 0 Seven Segment Digit 2 1 Seven Segment Digit 2 2 Seven Segment Digit 2 3 Seven Segment Digit 2 4 Seven Segment Digit 2 5 Seven Segment Digit 2 6 Seven Segment Digit 3 0 Seven Segment Digit 3 1 Seven Segment Digit 3 2 Seven Segment Digit 3 3 Seven Segment Digit 3 4 Seven Segment Digit 3 5 Seven Segment Digit 3 6 Seven Segment Digit 4 0 Seven Segment Digit 4 1 Seven Segment Digit 4 2 Seven Segment Digit 4 3 Seven Segment Digit 4 4 Seven Segment Digit 4 5 Seven Segment Digit 4 6 Seven Segment Digit 5 0 Seven Segment Digit 5 1 Seven Segment Digit 5 2 Seven Segment Digit 5 3 Seven Segment Digit 5 4 Seven Segment Digit 5 5 Seven Segment Digit 5 6 26 Terasic DE1 SoC User Manual www terasic com 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com ANU S RYAN 3 6 3 Using the 2x20 GPIO Expansion Headers The Board provides two 40 pin expansion headers The header connects directly to 36
32. ET_TX_EN A20 GMII and MII transmit enable 3 3V HPS TX 0 PIN F20 MII transmit data 0 3 3V 43 Terasic DE1 SoC User Manual www terasic com www terasic com HPS TX DATA 1 PIN J19 MII transmit data 1 3 3V HPS ENET TX DATA 2 PIN F21 MII transmit data 2 3 3V HPS ENET TX DATA 3 PIN F19 MII transmit data 3 3 3V HPS ENET RX DV PIN K17 GMII and MII receive data valid 3 3V HPS DATA O PIN A21 GMII and MII receive data 0 3 3V HPS ENET RX DATA 1 PIN B20 GMII and MII receive data 1 3 3V HPS ENET RX DATA 2 PIN B18 GMII and MII receive data 2 3 3V HPS DATA 3 021 GMII and MII receive data 3 3 3V HPS ENET RX CLK PIN G20 GMII and MII receive clock 3 3V HPS ENET RESET N PIN E18 Hardware Reset Signal 3 3V HPS ENET MDIO PIN E21 Management Data 3 3V HPS ENET MDC PIN B21 Management Data Clock Reference 3 3V HPS 19 Interrupt Open Drain Output 3 3V HPS ENET GTX CLK 19 GMII Transmit Clock 3 3V Additionally the Ethernet PHY KSZ9021RNI LED status has been set to two LED mode The LED control signals are connected to LEDs yellow and green on the RJ45 connector States and definitions can be found in Table 3 28 which can display the current status of the Ethernet For example once the green LED lights on the board has been connected to Giga bit Ethernet Table 3 28 LED Mode Pin Definition LED State LED Definition Link Activity LED
33. FPGA should be set in Asx4 mode i e let MSEL 4 0 to be set as 10010 8 2 Convert SOF File to JIC file Choose Convert Programming Files on Quartus window File menu See Figure 8 1 103 Terasic DE1 SoC User Manual www terasic com www terasic Edit View Project Assignments Process Close New Project Wizard Open Project Save Project Close Project cave Ctrl s Save Save All Ctrl Shift 5 File Properties Create Update Convert Programming Files Figure 8 1 File menu of Quartus In the Convert Programming Files dialog box scroll to the JTAG Indirect Configuration File jic from the Programming file type field In the Configuration device field choose EPCQ256 In the Mode field choose Active Serial X4 In the File name field browse to the target directory and specify an output file name Highlight the SOF data in the Input files to convert section See Figure 8 2 104 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RA p s Convert Program ming ile Ele Tools Window You can also import input file information from other files and save the conversion setup information created here for future use Lo X el Search altera com a Output programming file Programming file type JTAG Indirect Configuration File jic Options Configuration device Mode File name C faltera 13
34. G LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity RX TX 3 7 3 UART The board has one UART interface connected for communication with the HPS This interface wouldn t support HW flow control signals The physical interface is done using UART USB onboard bridge from an FT232R chip and connects to the host using an USB Mini B connector For detailed information on how to use the transceiver please refer to the datasheet which is available on the manufacturer s website or in the Datasheets UART TO USB folder on the DEI SoC System CD Figure 3 31 shows the related schematics and Table 3 29 lists the pin assignments of HPS in Cyclone V SoC FPGA 44 Terasic DE1 SoC User Manual www terasic com www terasic com FT232_DP HPS FT232 DM USB Mini B Connector HPS RESET n o MB FT232R Figure 3 31 Connections between the Cyclone V SoC FPGA and FT232R Chip Table 3 29 UART Interface I O Signal Name FPGA Pin No Description Standard HPS UART RX PIN B25 HPS UART Receiver 3 3V HPS UART TX PIN C25 HPS UART Transmitter 3 3V HPS 05 15 Reserve 3 3V 3 4 DDR3 Memory on HPS The DDR3 devices that are connected to the HPS
35. HPS to control the LED and HEX on the FPGA part through Lightweight HPS to FPGA Bridge B Function Block Diagram Figure 7 1 shows the diagram of this demonstration The HPS use Lightweight HPS to FPGA AXI Bridge to communicate with FPGA The HPS translate data to the FPGA through the Iwaxi bridge The hardware in FPGA part is built in Qsys The data translate through Lightweight HPS to FPGA Bridge is converted into Avalon MM master interface So the IP PIO controller and HEX Controller works as the Avalon MM slave in the system They control the pins related to the LED and HEX to change the LED and HEX s state This is similar to the system using NIOS II processor to control LED and HEX 99 Terasic DE1 SoC User Manual www terasic com www terasic 5 FPGA Qsys LED 9 0 HEX 5 0 Figure 7 1 HPS Control FPGA LED and HEX B LED and HEX control The Lightweight HPS to FPGA Bridge is a peripheral of the HPS The software running on linux operation system can t access the physical address of the HPS peripheral You must map the physical address to the user space at first then you can access to the peripheral or you can write a device driver module and add it to the kernel We only show the first method to the users in this demonstration We actually map in the entire CSR span of the HPS since we want to access various registers within that span If the users want to access any other peripherals whose physical addr
36. OL 0 00080000 The following statement can be used to configure 5 122 CONTROL associated pins as output pin alt setbits word virtual base uint32_t ALT GPIOI SWPORTA DDR ADDR amp uint32_t HW REGS MASK I2C CONTROL The following statement can be used to set 5 12 CONTROL high alt setbits word virtual base Cuint32 t C ALT SWPORTA DR ADDR amp uint32 t HW REGS MASK I2C CONTROL The following statement can be used to set 5 2 CONTROL low alt clrbits word virtual base uint32_t ALT SWPORTA DR ADDR amp uint32_t HW REGS MASK I2C CONTROL B 2 Driver Here 15 the list of procedures in order to read register value from TV Decoder by using the existing I2C bus driver in the system Set 5 DC CONTROL high so that HPS can access I2C bus Open I2C bus driver dev 12c 0 file open dev 12c 0 O_RDWR Specify ADV7180 s address 0x20 1octl file 2C SLAVE 0x20 Read or write registers set HPS I2C CONTROL low to release I2C bus 977 Terasic DE1 SoC User Manual www terasic com www terasic com Demonstration Source Code e Build tool Altera SoC EDS v13 0 Project directory Demonstration SoC hps_i2c_switch Binary file 12c_switch Build command make make clean to remove all temporal files e Execute command 12 switch B Demonstrat
37. PIN V30 PIN W29 PIN M19 PIN N24 PIN R18 PIN R21 PIN N18 PIN N25 PIN R19 PIN R22 PIN H28 PIN D30 PIN P30 PIN C28 PIN D27 3 7 5 QSPI Flash HPS DDR3 Data 28 HPS DDR3 Data 29 HPS DDR3 Data 30 HPS DDR3 Data 31 HPS DDR3 Data Strobe n 0 HPS DDR3 Data Strobe n 1 HPS DDR3 Data Strobe n 2 HPS DDR3 Data Strobe n 3 HPS DDR3 Data Strobe p 0 HPS DDR3 Data Strobe p 1 HPS DDR3 Data Strobe p 2 HPS DDR3 Data Strobe p 3 HPS DDR3 On die Termination DDR3 Row Address Strobe HPS DDR3 Reset HPS DDR3 Write Enable External reference ball for output drive calibration SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class 1 5 The board supports a 1G bit serial NOR flash device for non volatile storage of HPS boot code user data and program The device is connected to HPS dedicated interface It may contain secondary boot code This device has a 4 bit data interface and uses 3 3V CMOS signaling standard Connections between Cyclone V SoC FPGA and Flash are shown in Figure 3 32 To program the QSPI flash the HPS Flash Programmer is provided both as part of the Altera Quart
38. PS_GPIO54 which are controlled by the GPIO1 controller which also controls HPS GPIO29 HPS 57 HPS_GPIO54 941 KEY A24 HPS LED HPS 53 Figure 6 4 LED and KEY Pin Assignment Figure 6 5 shows the gpio swporta ddr register of the GPIOI controller The bit O controls the pin direction of HPS_GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to the HPS_LED the bits 25 controls the pin direction of HPS_GPIO54 which connects to the HPS_KEY and so on In summary the pin direction of HPS_LED HPS_KEY are controlled by the bit 24 bit 25 in the gpio swporta ddr register of the GPIOI controller respectively Similarly the output status of HPS LED is controlled by the bit 24 in the gpio swporta dr register of the GPIOI controller The status of KEY can be queried by reading the value of the bit 24 in the ext porta register of GPIOI controller GPIO1 Controller gpio swporta ddr register Controls the Direction of HPS GPIO29 Controls the Direction of HPS GPIO30 Controls the Direction of HPS GPIO31 Controls the Direction of 5 GPIOS3 HPS LED Controls the Direction of HPS GPIOS54 HPS KEY Controls the Direction of HPS_GPIO55 Controls the Direction of HPS 56 Controls the Direction of HPS GPIO57 Figure 6 5 swporta ddr Register in the GPIO1 91 DE1 SoC User Manual www terasic com www terasic com ANU RYAN In this demo code the
39. The device consists of 16 bit data line control line and address line connected to the FPGA This chip use the 3 3V LVCMOS signaling standard Connections between FPGA and SDRAM are shown in Figure 3 25 while the pin assignments are listed in Table 3 23 37 Terasic DE1 SoC User Manual www terasic com www terasic com Cyclone Signal Name DRAM_ADDR 0 DRAM ADDR 1 DRAM ADDR DRAM ADDR 3 DRAM_ADDR 4 DRAM ADDR 5 DRAM ADDRIS DRAM ADDR 7 DRAM ADDR DRAM ADDR g9 DRAM ADDR 10 DRAM ADDR 11 DRAM ADDR 12 DRAM DQ O DRAM DQ 1 DRAM DQ DRAM DQ 3 DRAM DO 4 DRAM DQ 5 DRAM DQ 6 Terasic DE1 SoC User Manual www terasic com SoC 32Mx16 SDRAM DRAM DQ 5 0 PS DRAM ADDR 12 0 DRAM BA 1 0 NEN DRAM CLK DRAM_CKE CKE DRAM_LDQM LDOM DRAM_UDQM UDQM DRAM_WE_N AWE DRAM_CAS_N CAS DRAM RAS N ARAS DRAM_CS_N ncs Figure 3 25 Connections between FPGA and SDRAM Table 3 23 SDRAM Pin Assignments FPGA Pin No PIN_AK14 PIN_AH14 AG15 PIN_AE14 PIN_AB15 14 AD14 15 15 13 PIN AG12 PIN AH13 PIN AJ14 PIN AK6 PIN AJ7 PIN AK7 PIN 8 PIN AK9 PIN AG10 11 Standard Description SDRAM Address 0 33V SDRAM Address 1 13 3 SDRAM Address 2 3
40. ations use SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QS YS We describe how the Altera s SDRAM Controller IP is used to access a SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The SDRAM controller handles the complex aspects of using SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The SDRAM controller is configured as a 64MB controller The working frequency of the SDRAM controller is 100MHZ and the Nios II program is running in the on chip memory 66 Terasic DE1 SoC User Manual www terasic com www terasic com FPGA BE 50 MHz KE On Chip lt gt Memory LL E SDRAM System Intercoment Fabric Figure 5 6 Block diagram of the SDRAM Basic Demonstration The system flow is controlled by a Nios II program First the Nios program writes test patterns into the whole 64MB of SDRAM Then it calls Nios II system function alt_dcache_flush_all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writin
41. card into the DEI SoC board e Poweronthe DEI SoC board e Launch PuTTY to connect to the UART port of DEI SoC board and type root to login Altera Yocto Linux e Inthe UART terminal of PuTTY execute hps_gpio to start the program COMS PuTTY Figure 6 6 Putty window HPS LED will flashing 2 times first Press 5 KEY to light up HPS LED Press CTRL C to terminate the application 6 3 I2C Interfaced G sensor This demonstration shows how to control the G sensor by accessing its registers through the built in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux B Function Block Diagram Figure 6 7 shows the function block diagram of this demonstration The G sensor on the DEI SoC board is connected to the 2 0 controller in HPS The G Sensor I2C 7 bit device address is 0x53 The system I2C bus driver 15 used to access the register files in the G sensor The G sensor interrupt signal 15 connected to the PIO controller In this demonstration we use polling method to read the register data so the interrupt method 15 not introduced here 95 DE1 SoC User Manual www terasic com www terasic com FPGA SoC DDR3 ARM Program Linux User Mode HPS I2C CLK 2 SDA G Sensor Linux Kernel Mode I2C address 0x53 Interrupt Figure 6 7 Block Diagram of the G sensor Demonstration B 2 Driver Here is the list of procedures in order to read a register va
42. ch uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector is responsible for detecting this instability The ITU R 656 Decoder block extracts YcrCb 4 2 2 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder is interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection 71 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN multiplexer MUX which is controlled by the VGA controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selection signals to the SDRAM Frame Buffer and filed selection multiplexer MUX The YUV422 to YUV444 block converts the selected YcrCb 4 2 2 YUV 4 2 2 video data to the YcrCb 4 4 4 YUV 4 4 4 video data format Finally the YcrCb_to_RGB block converts the YcrCb data into RGB data output The VGA Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable the display on a VGA monitor YUV 422 i Even Data Valid FPGA S f CZ 2 2 PPO T 2 pc MI 2 SDAT Figure 5 9 Block diagram of t
43. chain the board 13 Terasic DE1 SoC User Manual www terasic com www terasic com Configuring the FPGA in JTAG Mode There are two devices FPGA and HPS on the JTAG Chain the configure flow 15 different from DEI The following shows the programming flow with JTAG mode step by step Open Programmer and click Auto Detect as Figure 3 2 Programmer Chain3 Edit View Processing Tools Window Help 5 besc igi Stop Delete Add File 2 Change File A Save File 22 Add Device qu Up Down Figure 3 2 FPGA JTAG Programming Steps 1 e Select detected device as Figure 3 3 Please select device as same as which shows on the board X Select Device Found devices with shared JTAG ID for device 1 Please select your device SCSEBAS Figure 3 3 FPGA JTAG Programming Steps 2 14 DE1 SoC User Manual www terasic com www terasic com ANU S e Both FPGA and HPS will be detected as Figure 3 4 3 Hardware Setup DE SoC USB 1 Mode Enable real time ISP to allow background programming for MAX II and MAX V devices plu start Stop Delete Al Save File Down Figure 3 4 FPGA JTAG Programming Steps 3 Click the FPGA device right click mouse to popup the manual and then select sof file for FPGA as Figure 3 5 15 1 5 DE1 SoC Use
44. configure the data format as Full resolution mode 16g range mode Left justified mode The X Y Z data value can be derived from the DATA X0 0x32 DATAX1 0x33 0 0 34 DATAY 1 0x35 DATAZO 0x36 DATAX1 0x37 registers The DATA XO represents the least significant byte and DATA XI represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between reads of sequential registers Developer can use the following statement to read 6 bytes of X Y or Z value read file szData8 sizeof szData8 where szData is an array of six bytes B Demonstration Source Code e Build tool Altera SoC EDS v13 0 e Project directory Demonstration SoC hps_gsensor e Binary file gsensor Build command make make clean to remove all temporal files e Execute command gsensor loop count Demonstration Setup e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file gsensor is copied into the SD card under the home root folder 1n Linux e Insert the booting micro sdcard into the DEI SoC board 95 Terasic DE1 SoC User Manual www terasic com www terasic ANU S nA Power on the DEI SoC board Launch PuTTY to connect to the UART port of DEI SoC borad and type root to login Yocto Linux In the UART terminal of PuTTY execute gsensor to start
45. ct Setting Management DEI SoC System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 4 6 Users can save the current board configuration information into a cfg file and load it to the DEI SoC System Builder 58 Terasic DE1 SoC User Manual www terasic com ANU RYA System Configuration AU S RA UNIVERSITY Project Name PROGRAM DEI SOC www terasic com DE1 SoC Board 4 CLOCK 4 Seqment x 6 10 Switch x 10 7 Button x 4 WIR TX RX Video In Audio 4 ADC SDRAM 32MB PS2 0 Header D5M 5M Pixel Camera M Prefix Name GPIO 1 Header Save Setting None Prefix Name Load Setting Figure 4 6 Project Settings Project Generation When users press the Generate button the DEI SoC System Builder will generate the corresponding Quartus files and documents as listed in the Table 4 1 Description Top level Verilog HDL file for Quartus Il lt Project name gt qpf Quartus II Project File lt Project name gt qsf Quartus II Setting File ii Project name gt sdc Synopsis Design Constraints file for Quartus lt Project name gt htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof 59 Terasic DE1 SoC U
46. data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which is implemented C code The I2C pins from audio chip are connected to Qsys System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface 15 configured as 125 and 16 bit mode 18 432MHz clock generated by the PLL is connected to the MCLK XTI pin of the audio chip through the AUDIO Controller 62 Terasic DE1 SoC User Manual www terasic com joeuuoo1eju 5 Clock to SDRAM 4 milium d LED KEY 1 ISWII2C Figure 5 3 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions Hardware Project directory DEI Audio Bit stream used DEI SoC Audio sof Software Project directory DEI SoC AudioNsoftware Connect an Audio Source to the LINE IN port of the DEI SoC board Connect a Microphone to MIC IN port on the DEI SoC board Connect a speaker or headset to LINE OUT port the DEI SoC board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure audio with the Slide switches SWO as shown in Table 5 1 Press KEY3 on the DEI SoC board to start stop audio recording note 2 Press KEY2 on DEI SoC board to start stop audio playing note 3 Table 5 1 Slide switches usage for audio
47. der Launch Quartus II and Open Project Create New SOC Kit System Builder Add User Design Logic Project Generate Compile to generate SOF Configure FPGA Quartus Project and Document Figure 4 1 The general design flow of building a design 4 3 Using DE1 SoC System Builder This section provides the detailed procedures on how the DE1 SoC System Builder is used B Install and launch the DE1 SoC System Builder The DEI SoC System Builder is located in the directory ToolsNSystemBuilder on the DEI SoC 54 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN System CD Users can copy the whole folder to a host computer without installing the utility Launch the DEI SoC System Builder by executing the DEI SoC SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 4 2 DE1 SoC V1 0 0 5 NBT8 SYN System Configuration NU Project Name PROGRAM DE Se DE1 SoC Board z CLOCK 4 T Seqment x 6 LED x 10 Switch x 10 Button x 4 IIR TXIRX VI VGA Video In Audio ADC SDRAM 32MB PS2 GPIO 0 Header Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Figure 4 2 The DE1 SoC System Builder window B Input Project Name Input project name as show in Figure 4 3 Project Name
48. device download the bit stream to the board by using JTAG programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red LEDs are flashing e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA 60 Terasic DE1 SoC User Manual www terasic com www terasic com display should show color picture Optionally connect a powered speaker to the stereo audio out jack Press KEY 1 to hear a 1 kHz humming sound from the audio out port e There is a demo_batch folder in the project It is able to load the bit stream into the FPGA programming or erasing jic file to EPCQ by executing test bat file as shown in the Figure 5 1 If user want to download the new design into the EPCQ the easy method 15 to copy the new sof file into the demo_batch folder and Execute the test bat Select the option 2 to covert the sof to jic firstly Then using the option 3 to program jic file into EPCQ Plesase choise your operation a programming sof to FPGA A For converting sof to jic For programming jic to EPCQ for erasing jic From EPCQ i Please enter your choise 1 2 3 4 Figure 5 1 Batch file for download FPGA and EPCQ 5 2 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the DEI SoC board with the built in Audio CODEC chip This demonstration is develop
49. dio CODEC Table 3 15 Audio CODEC Pin Assignments SignalName FPGA Pin No Description AUD ADCLRCK PIN K8 Audio CODEC ADC LR Clock AUD ADCDAT PIN K7 Audio CODEC ADC Data AUD DACLRCK H8 Audio CODEC DAC LR Clock AUD DACDAT PIN J7 Audio CODEC DAC Data AUD XCK 67 Audio CODEC Chip Clock AUD_BCLK H7 Audio CODEC Bit Stream Clock 12C_SCLK 412 or PIN E23 12 Clock 2 SDAT PIN K12 or PIN C24 I2C Data 3 6 5 2 Multiplexer The DEI SoC board implements an I2C multiplexer so that HPS can access the I2C bus originally owned by FPGA Figure 3 19 shows the connection of I2C multiplexer HPS will own I2C bus and then can access Audio CODEC and TV Decoder when the HPS I2C CONTROL signal 1s set to high By default FPGA owns the I2C bus The FPGA pin assignments of I2C bus are listed Table 3 16 30 DE1 SoC User Manual www terasic com Mic In Line In BJ Line Out J3 O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com 2 Bus 55 23157 Switch_Control 12 HPS ARM Figure 3 19 Connections of I2C Multiplexer Table 3 16 Bus Pin Assignments Signal Name FPGA Pin No Description FPGA 2 SCLK 12 FPGA I2C Clock F Standard FPGA_I2C_SDAT PIN Ki2 FPGA 2 Data HPS I2C1 S
50. e home root folder in Linux e Insert the booting micro SD card into the DEI SOC board e Power on the DEI SOC board e Launch PuTTY to connect to the UART port of SoCKit board and type root to login Altera Yocto Linux Execute the demo batch file test bat under the quickfile Sof dwonload 101 Terasic DE1 SoC User Manual www terasic com www terasic com In UART terminal of PuTTY execute HPS LED HEX to start the program The putty will show the message as shown in Figure 7 2 and the LED 9 0 will flash the number on HEX 5 0 will change at the same time Press CTRL C to terminate the program Figure 7 2 Running result in putty 102 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 8 Steps of Programming the Quad Serial Configuration Device This chapter describes how to program the quad serial configuration device with Serial Flash Loader SFL function via the JTAG interface User can program quad serial configuration devices with a JTAG indirect configuration jic file To generate JIC programming files with the Quartus II software users need to generate a user specified SRAM object file sof which is the input file first Next users need to convert the SOF to a JIC file To convert a SOF to a JIC file in Quartus software follow these steps 8 1 Before you Begin To use the Quad serial flash as a FPGA configuration device please make sure the
51. e board Using the Quartus II software it is possible to reconfigure the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the quad serial configuration device EPCQ256 It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DEI SoC board is turned off When the board s power is turned on the configuration data in the EPCQ256 device is automatically loaded into the Cyclone V SoC FPGA B JTAG Chain DE1 SoC Board To use JTAG interface for configuring FPGA device the JTAG chain on DEI SoC must form a close loop that allows Quartus programmer to detect FPGA device Figure 3 1 illustrates the chain on DEI SoC board Extemal JTAG Header Installed FPGA M TDI FPGA TDI RYA n ey wu vox Cyclone V Connector Figure 3 1 The JTAG
52. eco DAP 7 0 000000 2 Mm o cr Ld NAND controller data OxFFZ09000 joe a arre OxFFB80000 TanUvAIA FPGA CANO controller registers controller registers OxFFC01000 Figure 6 3 GPIO Address Map Software Developers can use the following software API to access the register of GPIO controller open use to open memory mapped device driver mmap map physical memory to user space alt read word read a value from a specified register alt write word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt setbits word set specified bit value to zero for a specified register 21 clrbits word set specified bit value to one for a specified register To use the above API to access register of GPIO controller the program must include the following header files Terasic DE1 SoC User Manual www terasic com include lt stdio h gt include lt unistd h gt include lt fcntl h gt include lt sys mman h gt include hwlib h include socal socal h include socal hps h 90 www terasic com include socal alt_gpio h LED and KEY Control Figure 6 4 shows the HPS users LED and KEY pin assignment for the DEI SoC board The LED is connected to HPS_GPIO53 KEY is connected to H
53. ed based on Qsys and Eclipse Figure 5 2 shows the man machine interface of this demonstration Two push buttons and four slide switches are used for users to configure this audio system SWO is used to specify recording source to be Line in or MIC In SWI SW2 and SW3 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K Table 5 1 and Table 5 2 summarize the usage of Slide switches for configuring the audio recorder and player 61 Terasic DE1 SoC User Manual www terasic com www terasic com 77 917 ase Ej 23 gg E CIE t 518 5 515 ge e 5507 pn 3 Ciis 1 LI a o el e i is ure Ki 47 i Men a 188 BH f 1 i y B 24 H as Li Tut aH ic Audio Source Play MIC or LINE IN Sample Rate Record Figure 5 2 Man Machine Interface of Audio Recorder and Player Figure 5 3 shows the block diagram of the Audio Recorder and Player design There are hardware and software parts in the block diagram The software part stores the Nios II program in the on chip memory The software part is built by Eclipse in C programming language The hardware part is built by Qsys under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined Qsys component It 1s designed to send audio
54. egrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone DEI SoC development board includes hardware such as high speed DDR3 memory video and audio capabilities Ethernet networking and much more DEI SoC Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the DE1 SoC package DE1 SoC Board DE1 SoC Quick Start Guide Type A to B USB Cable O Type A to Mini B USB Cable Power DC Adapter 12V Figure 1 1 The DE1 SoC package contents 3 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN The DEI SoC package includes The DEI SoC development board DEI SoC Quick Start Guide USB Cable Type A to B for FPGA programming and control e USB Cable Type A to Mini B for UART control DEI SoC System CD ROM 12V DC power adapter 1 2 DE1 SoC System CD DEI SoC System CD containing the DEI SoC documentation and supporting materials including the User Manual System Builder reference designs and device datasheets User can download this System CD form the link http del soc terasic com 1 3 Getting Help Here are the addresses where you can get help if you encounter any problem e Alt
55. en data from USB Host to FT232R JTAG RX Reserved 18 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN 3 4 Board Reset Elements The board equips two HPS reset circuits See Figure 3 9 Table 3 7 shows the buttons references and its descriptions Figure 3 10 shows the reset tree on the board gt TOME os n HPS WARM RST n ena TOC T T HPS RESET Figure 3 9 Board Reset Elements able 7 7 Reset Elements HPS_RESET_N Places the HPS default state sufficient for software to boot KEY7 HPS_ WARM 5 Warm reset to the HPS block Active low input affects the system reset domains which allows debugging to operate mE Active low input that will reset all HPS logics that can be 19 Terasic DE1 SoC User Manual www terasic com www terasic co m USB Blaster JTAG Connector PIN 6 VCC3P3 Cyclone V SoC KEY HPS FPGA B 5 RST n HPS_NRST WARM_RST HPS_RESET_n m 5 _ 5 HPS RESET n GPIO42 10 100 1000 Base T Ethernet PHY KSZ9021RN RESET_N USB 2 0 OTG PHY USB3300 HPS RESET PHY RESET Figure 3 10 Reset Tree on the Development Board 3 5 Clock Circuitry Figure 3 11 is a diagram showing the default frequencies
56. ending out by IR TX Controller e Observe the six HEXs See Table 5 7 for detail e Releasing KEY O to stop the IR TX e Point the IR receiver with the remote controller and press any button e Observe the six HEXs See Table 5 7 for detail e And User can using Multi DEI SoC boards to do more IR test between boards 81 Terasic DE1 SoC User Manual www terasic com www terasic com Table 5 7 Detailed information of the indicators Indicator Name HEX5 nversed high byte of DATA Key Code HEX4 Inversed low byte of DATA Key Code HEX High byte of DATA KeyCode 2 5 9 ADC Reading This demonstration illustrates steps which can be used to evaluate the performance of the 8 channel 12 bit A D Converter ADC7928 The DC 5 0V on the 2x5 header is used to drive the analog signals and by using a trimmer potentiometer the voltage can be adjusted within the range of 0 5 0V The 12 bit voltage measurements are indicated on the NIOS II console Figure 5 19 shows the block diagram of this demonstration Note that the input voltage range is 0 5 and if your input voltage is 2 5 2 5V you can make the pre scale circuit to adjust their range to 0 5 V FPGA 50 MHz ouqe 12euuooJeju uigjes g 4 ADC Controller qmi 2x5 Header 1 Figure 5 19 ADC Reading Block Diagram 82 Terasic DE1 SoC User Manual www terasic com www terasic co m ANU RYAN Figure 5 20 depicts the pin ar
57. entified by an index from to 6 with the positions given in Figure 3 16 Table 3 12 shows the assignments of FPGA pins to the 7 segment displays 2 HEXO 0 HEXO 1 HEXO 2 HEXO 3 A 4 HEXO 5 4 JA OTE pP AN Figure 3 16 Connections between the 7 segment display and Cyclone SoC FPGA Signal Name 0 DE1 SoC User Manual www terasic com Table 3 12 Pin Assignments for 7 segment Displays FPGA Pin No AE26 Description Seven Segment Digit 0 0 3 3V 25 O Standard www terasic com HEXO 1 HEXO 2 HEXO 3 HEXO 4 HEXO 5 HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 210 2 1 212 HEX2 3 HEX2 4 HEX2 5 2 6 HEX3 0 HEX3 1 HEX3 2 HEX3 3 HEX3 4 HEX3 5 HEX3 6 HEXA 0 HEX4 1 412 4 3 HEX4 4 HEX4 5 4 6 HEX5 0 HEX5 1 HEX5 2 HEX5 3 HEX5 4 HEX5 5 HEX5 6 PIN AE27 PIN AE28 PIN AG27 PIN AF28 PIN AG28 PIN AH28 PIN AJ29 PIN AH29 PIN AH30 PIN AG30 PIN AF29 PIN AF30 PIN AD27 PIN AB23 PIN AE29 PIN AD29 PIN AC28 PIN AD30 PIN AC29 PIN AC30 PIN AD26 PIN AC27 PIN AD25 PIN AC25 PIN AB28 PIN AB25 PIN AB22 PIN AA24 PIN Y23 PIN Y24 PIN W22 PIN W24 PIN V23 PIN W25 PIN V25 PIN AA28 PIN Y27 PIN AB27 PIN AB26 PIN AA26 PIN AA25 Seven Segment Digit O 1 Seven Segment
58. er as shown in Figure 3 28 For more detailed information on the A D converter chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD VCC5 ADC INO IN1 ADC IN2 IN3 4 5 ADC IN6 7 GND Figure 3 28 Pin distribution of the 2x5 Header Figure 3 29 shows the connections on the 2x5 header A D converter and Cyclone V SoC device 41 Terasic DE1 SoC User Manual www terasic com www terasic AD7928BRUZ ADC_INO ADC_SCLK ADC_IN2 8 7 DIN lt ADC DOUT 2 5 ADC_IN3 Header ADC_IN4 ADC_CS_N ADC IN5 E 7 Cyclone e V IN6 gt 7 Figure 3 29 Wiring for 2x5 header and A D converter Table 3 25 Pin Assignments for ADC i 3V PIN_AK4 Digital data output PIN_AK2 Digital clock input 3 7 Interface on Hard Processor System HPS This section introduces the interfaces connected to the HPS section of the FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push button and LED on HPS Like the FPGA the HPS also features its own set of switches buttons LEDs and other user interfaces Users can control these interfaces for observing HPS status and debugging Table 3 26 gives the all the pin assignments of all the user interfaces 42 DE1 SoC User Ma
59. era Corporation e 101 Innovation Drive San Jose California 95134 USA Email university altera com Terasic Technologies No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 575 0880 Web del soc terasic com Terasic DE1 SoC User Manual www terasic com www terasic Chapter 2 Introduction of the DE 1 SoC Board This chapter presents the features and design characteristics of the board 2 1 Layout and Components A photograph of the board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components n c 5 5 VGA Out Mic Line Line VGA HPS Gigabit HPS Ethernet In In Out Video In 24 bit DAC JTAG Header Audio Codec Video Decoder PS2 USB Blaster II Power DC Jack Power ON OFF f 64MB SDRAM TR ADC ADC Header 7 Segment Display LED x10 2121 m Button 4 Switch x10 USB Host UART to USB USB HUB UART to USB Controller Micro SD Card USB PHY Ethernet PHY 2x20 GPIO x2 1GB DDR3 SDRAM with ARM Cortex A9 Accelerometer 2x7 LTC Expansion Header HPS User LED IR out IR in WARM RST HPS User Button HPS RST Figure 2 1 Development Board top view Terasic DE1 SoC User Manual www terasic com www terasic com FPGA Configuration Mode Switch EPCQ 259 i5 I 3 2 PES diee
60. erin E nee D NIME M EI IMEEM 19 LENLE LT E a o T PEE E T A ie oat Hap crow Gs a E o 20 u 21 3 6 1 USER PUSH BUTTONS SWITCHES AND LEDS ON FPGA 02 2000001 00011 22 502 5555 E 25 3 6 3 USING THE 2X20 GPIO EXPANSION HEADERS 0 0000000000000000011 0 27 3 6 4 USING THE 24 BIT AUDIO 29 ass 30 21 gt 2 D 34 REORUM NNNM 36 SORA EA VE 36 2 0 TO SDRANI MEMORY ON EPCHA 24 SON PIPER ua d ee ae 39 AND 2X5 245 dba and ced ss e
61. ess is in this span they can reuse the mapping function and the macro we defined below define HW REGS BASE ALT STM OFST define HW REGS SPAN 0x04000000 fdefine HW REGS MASK HW REGS SPAN 1 The Iwaxi bridge start address after being mapped be get using the ALT LWFPGASLVS OFST which is defined in altera hps hardware library Then the slave IP connected to the Iwaxi bridge can be accessed through the base address and the register offset in these IPs For instance the base address of the PIO slave IP in this system is 0 0001 0040 and the direction control register offset 15 0x01 the data register offset is 0x00 The following statement be used to get the base address of PIO slave IP h2p_lw_led_addr virtual_base unsigned long ALT LED BASE amp unsigned long HW REGS MASK In this demonstration we just need to set the PIO s direction as output which 15 the default direction of the PIO IP so we can skip this step The following statement 15 used to set the output state of the PIO 100 Terasic DE1 SoC User Manual www terasic com www terasic com alt write word h2p Iw led addr Mask The Mask in this statement decides which bit in the data register of the PIO IP is high or low The bits in data register decide the output state of the pins connected to the LEDs The program for the HEX controlling is similar to the LED Since the linux
62. evice will pull low the data line again as an acknowledgement which means that the data is correctly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 11 shows the waveform while communication happening on two lines Sending command CLK Inhibit qst 2nd gth 10 11 CLK CLK CLK CLK CLK eooo DATA 7 Start bit BitO Bit7 Parity bit Stop Line bit control bit Receiving data 1 st 2nd 1 oth 1 4th CLK CLK CLK CLK CLK Start bit BitO Bit7 Parity bit Stop bit Figure 5 11 Waveforms on two lines while communication taking place Demonstration Source Code e Project directory DEI SoC PS2 DEMO e Bit stream used DEI SoC PS2 DEMO sof 75 Terasic DE1 SoC User Manual www terasic com ANU RYA Demonstration Batch File Demo Batch File Folder DEI SoC PS2 DEMO Memo batch The demo batch file includes the following files e Batch File DEI SoC PS2 DEMO bat e FPGA Configure File DEI SoC PS2 DEMO sof Demonstration Setup File Locations and Instructions the bit stream into FPGA by executing DEI SoC PS2 DEMO Memo batch DEI SoC 52 DEMO bat e Plugin the PS 2 mouse e Press KEY 0 for enabling data transfer Press KEY 1 to clear the display data cache e You should see digital changes on 7 segment display when the PS 2 mouse moves and the LEDR 2 0 will bl
63. following mask is defined to control LED and KEY direction and LED s output value define USER IO DIR OxO 1000000 define BIT_LED OxO 1000000 define BUTTON MASK 0x02000000 The following statement can be used to configure the LED associated pins as output pins alt setbits word virtual base Cuint32 t ALT SWPORTA DDR ADDR amp uint32 t HW REGS MASK USER IO DIR The following statement can be used to turn on the LED alt setbits word virtual base Cuint32 t ALT SWPORTA DR ADDR amp uint32 t HW REGS MASK LED The following statement can be used to read the content of gpio ext porta register The bit mask is used to check the status of the key alt read word virtual base Cuint32 ALT GPIO1 EXT PORTA ADDR 6 uint32 t HW REGS MASK B Demonstration Source Code e Build tool Altera SoC EDS V 13 0 e Project directory Demonstration SoC hps_gpio e Binary file hps_gpio Build command make make clean to remove all temporal files e Execute command hps_gpio 92 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN Demonstration Setup e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file hps_gpio is copied into the SD card under the home root folder in Linux e Insert the booting micro SD
64. g reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tools e Quartus 13 0 e Nios II Eclipse 13 0 Demonstration Source Code e Quartus Project directory DEI SoC SDRAM Nios Test Nios II Eclipse DEI SoC SDRAM Noios Test Software B Nios II Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse 67 Terasic DE1 SoC User Manual www terasic com www terasic ANU RYAN Demonstration Batch File Demo Batch File Folder DEI SoC_SDRAM_Nios_ Test Nemo batch The demo batch file includes following files Batch File for USB Blaster ID DEI SoC SDRAM Test bat DEI SoC SDRAM 5 Test bashrc e FPGA Configure File DEI SoC SDRAM Noios Test sof e Nios Program DEI SoC SDRAM Test elf B Demonstration Setup e sure Quartus and Nios II are installed on your PC e Power the DEI SoC board e Use USB cable to connect PC and the DEI SoC board 713 and install USB Blaster driver if necessary Execute the demo batch file DEZ SoC SDRAM Nlios Test bat for USB Blaster II under the batch file folder DE SoC SDRAM Nios TestNlemo batch e After Nios program is downloaded and executed successfully a prompt message will be displayed in
65. he TV box demonstration Demonstration Source Code e Project directory DEI SoC TV e Bit stream used DEI SoC TV sof Demonstration Batch File Demo Batch File Folder DE1 SoC TV Memo batch The demo batch file includes the following files e Batch File DEI 5 TV bat e FPGA Configure File DEI 5 TV sof 72 DE1 SoC User Manual www terasic com www terasic ANU RYAN Demonstration Setup File Locations and Instructions e Connect a DVD player s composite video output yellow plug to the Video In RCA jack J6 of the DE1 SoC board See Figure 5 10 The DVD player has to be configured to provide e NTSC output e 60Hz refresh rate e 4 3 aspect ratio Non progressive video Connect the VGA output of the DEI SoC board to a VGA monitor both LCD and CRT type of monitors should work Connect the audio output of the DVD player to the line in port of the DEI SoC board and connect a speaker to the line out port If the audio output jacks from the DVD player RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DEI SoC board this is the same type of plug supported on most computers Load the bit stream into FPGA by execute the batch file DE1_SoC_TV bat under DEI SoC TV demo_batch folder Press KEYO on the DEI SoC board to reset the circuit VGA LCD CRT Monitor dir xc Video In VGA Out CVBS Output D
66. iles e Execute Command my_first_hps B Demonstration Setup e Connect USB cable to the USB to UART connector 74 on the DEI SoC board and host PC e Make sure the demo file my first hps is copied into the SD card under the home root folder in Linux e Insert the booting micro SD card into the DEI SoC board e Power on DEI SoC board e Launch PuTTY to connect to the UART port of Putty and type root to login Altera Yocto Linux e Inthe UART terminal of PuTTY type my_first_hps to start the program and you will see Hello World message in the terminal 6 2 Users LED and KEY This demonstration presents how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer to access the system physical memory B Function Block Diagram Figure 6 1 shows the function block diagram of this demonstration The users LED and KEY are 87 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN connected the GPIOI controller in HPS The behavior of the GPIO controller is controlled by the register in the GPIO controller The registers can be accessed by application software through the memory mapped device driver which is built into Altera SoC Linux FPGA SoC DDR3 ARM Program HPS Linux User Mode Linux Kernel Mode Figure 6 1 Block Diagram of GPIO Demonstration B GPIO I
67. ink respectively when the left button right button or middle button is pressed Table 5 5 gives the detailed information Table 5 5 Detailed information of the indicators Indicator Name Description OZ LEDR Right button press indicator byte of X displacement 2 byte of HEX3 High byte of Y displacement 5 8 IR Emitter LED and Receiver Demonstration In this demonstration we show a simple example of using Emitter LED and IR receiver All the codes this demonstration are coding by verilog HDL 76 Terasic DE1 SoC User Manual www terasic com www terasic com FPGA vo ES DATA E IR TX IR Emitter test pattern Controller LED t IR RX IR Controller dua Receiver im 5 IR Rmote Figure 5 12 Block Diagram of the IR Emitter LED and Receiver Demonstration gt 2 E Figure 5 12 shows the block diagram of the design It mainly implement a IR TX Controller and a IR RX Controller When is pressed Data test pattern generator continuously generates data to the IR TX Controller When IR TX Controller works it will format the sending data into NEC IR transmission protocol and send it out through IR emitter LED IR receiver will decode the received data and display it on six HEXs Also user can use a remote controller to sending data to IR Receiver The main function of IR TX RX controller and IR remote in this dem
68. ion Setup e Connect the USB cable to the USB to UART connector J4 on the DEI SoC board and host PC e Make sure the executable file i2c switch is copied into the SD card under the home root folder 1n Linux e Insert the booting micro sdcard into the DEI SoC board e Power on DEI SoC board Launch PuTTY to connect to the UART port of DEI SoC borad and type root to login Yocto Linux Inthe UART terminal of PuTTY execute 12 switch to start the 2 MUX test e The demo program will show the result in the Putty as shown in Figure 6 12 j pcom 800000 XT 3OCIDGBa yee 2w Figure 6 12 Terminal output of the MUX Test Demonstration Press CTRL C to terminate the program 98 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 7 Examples for using both HPS SoC and FGPA Although the HPS and the FPGA can operate independently they are tightly coupled via a high bandwidth system interconnect built from high performance ARM AMBA AXITM bus bridges Both FPGA fabric and HPS can access to each other via these interconnect bridges This chapter provides demonstrations for how to using these bridges that can achieve superior performance and lower latency when compared to solutions containing a separate FPGA and discrete processor 7 1 HPS Control LED and HEX This demonstration presents using
69. ion device EPCQ256 that stores configuration data for the Cyclone SoC FPGA This configuration data 15 automatically loaded from the quad serial configuration device chip into the FPGA when the board is powered up e To program the configuration device users will need to use a Serial Flash Loader SFL function to program the quad serial configuration device via the JTAG interface The 17 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S FPGA based SFL is a soft intellectual property IP core within the FPGA that bridges the JTAG and flash interfaces The SFL mega function is available from Quartus II software Figure 3 8 shows the programming method when adopting a SFL solution e Please refer to Chapter 9 Steps of Programming the Quad Serial Configuration Device for the basic programming instruction on the serial configuration device Quartus Programmer Ee SFL Image to Bridge The JTAG and ASMI Circuit AS x4 Quad Serial Figure 3 8 Programming a Quad Serial Configuration Device with the SFL Solution 3 3 Board Status Elements The board includes status LEDs Please refer to Table 3 6 for the status of the LED indicator Table 3 6 LED Indicators Board Reference LED Name 12 V Power illuminates when 12 V power is active UART TXD Illuminates when data from FT232R to USB Host UART RXD Illuminates wh
70. its datasheet which is available on manufacturer s website or under the Datasheet folder of the DEI SoC System CD Figure 3 35 shows the connections between ADXL345 and HPS The associated pin assignments are listed in Table 3 34 50 www terasic com Terasic DE1 SoC User Manual www terasic com U28 7 Fe HPS I2C1 SCLK gt SCL_SCLK y genx SDIO SoC HPS GSENSOR INT ITA des ADXL345 Figure 3 35 Connections between Cyclone V SoC FPGA and G Sensor Table 3 34 G Sensor Pin Assignments Signal Name FPGA Pin No Description Standard HPS_GSENSOR_INT PIN_B22 HPS GSENSOR Interrupt Output 3 3V HPS 2 1 SCLK PIN E23 HPS 12 Clock share bus with LTC 3 3V HPS 1261 SDAT PIN C24 HPS 2 Data share bus 3 3V 3 7 9 LTC Connector The board allows connection to interface card from Linear Technology The interface 1s implemented using al4 pin header that can be connected to a variety of demo boards from Linear Technology It will be connected to SPI Master and I2C ports of the HPS to allow bidirectional communication with two types of protocols The 14 pin header will allow for GPIO SPI 2 extension for user purposes if the interfaces to Linear Technology board aren t in use Connections between the LTC connector and the are shown in Figure 3 36 and the functions of the 14 pins is listed in Table 3 25 21 DE1 SoC User Manual www terasic com www terasic com
71. lue from G sensor register files by using the existing I2C bus driver in the system 1 Open I2C bus driver dev 12c 0 file open dev i2c 0 O_RDWR 2 Specify G sensor s I2C address 0x53 ioctl file 2C_SLAVE 0x53 3 Specify desired register index in g sensor write file amp Addr8 sizeof unsigned char 4 Read one byte register value read file amp Data8 sizeof unsigned char Because the G sensor I2C bus is connected to the I2CO controller as shown in the Figure 6 8 the given driver name is dev 12c 0 2 0 SCL E23 HPS 2 1 SCLK 2 0 SDA C24 HPS I2C1 SDAT Figure 6 8 Schematic of I2C To write a value into a register developer can change step 4 to write file amp Data8 sizeof unsigned char To read multiple byte values developer can change step 4 to read file amp szData8 sizeof szData8 where szData is an array of bytes 94 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RYA To write multiple byte values developer can change step 4 to write file amp szData8 sizeof szData where szData is an array of bytes B G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interface 1s used by setting the CS pin to high on this DEI SoC board The ADI ADXL345 G sensor provides user selectable resolution up to 13 bit 16g The resolution can be configured through the DATA 0 31 register In the demonstration we
72. m E sic 2 E te Bae sae E 9 i HESS Em 2 ESEN POR 952 J i T NE NE ue bast beet Pot bal bol foe loot De Interlace Figure 5 10 Setup for the TV box demonstration ITU R 656 YUV 422 Decoder 73 DE1 SoC User Manual www terasic com www terasic com ANU S RYA 5 7 PS 2 Mouse Demonstration We offer this simple PS 2 controller coded in Verilog HDL to demonstrate bidirectional communication between PS 2 controller and the device the PS 2 mouse You can treat it as a how to basis and develop your own controller that could accomplish more sophisticated instructions like setting the sampling rate or resolution which need to transfer two data bytes For detailed information about the PS 2 protocol please perform an appropriate search on various educational web sites Here we give a brief introduction B Outline PS 2 protocol use two wires for bidirectional communication one clock line and one data line The PS 2 controller always has total control over the transmission line but the PS 2 device generates clock signal during data transmission B Data transmit from the device to controller After sending an enabling instruction to the PS 2 mouse at stream mode the device starts to send displacement data out which consists of 33 bits The frame data 15 cut into three similar slices each of them containing a start bit always
73. n hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the similar as shown in Figure 3 21 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 17 and Table 3 18 show different resolutions and durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s website or in the Datasheets VIDEO DAC folder on DE1 SoC System CD The pin assignments between the Cyclone V SoC FPGA and the ADV7123 are listed in Table 3 19 32 Terasic DE1 SoC User Manual www terasic com www terasic com Back porch Display interval c Front porch d S DATA RGB HSYNC VGA mode Configuration VGA 60Hz VGA 85Hz SVGA 60Hz SVGA 75Hz SVGA 85Hz XGA 60Hz XGA 70Hz
74. nios2 terminal Press KEY3 KEYO of the DEI SoC board to start SDRAM verify process Press KEYO for continued test The program will display progressing and result information as shown in Figure 5 7 68 Terasic DE1 SoC User Manual www terasic com www terasic com Altera Nios I EDS 13 0 Using cable DE So0C USB 11 device 1 instance HxHH Resetting and pausing target processor OK Initializing cache amp if present OK Downloaded 61KB in 1s Werified OK Starting processor at address Hx2ZBH2H1B4 nios2 terminal connected to hardware target using JTAG UART on cable nins2 terminal DE SoG 5 8 1 1 device 1 instance mnios2 terminal Use the IDE stop button or Ctrl C to terminate SDRAM Test Size 64NB Clock 1466000060 gt Press any KEV to start test for continued test gt SDRAM Testing Iteration 1 write 1H 26 304 405 58x 8H Hz 1982 read uerifu 1H 292 382 48 5H ec C Figure 5 7 Display Progress and Result Information for the SDRAM Demonstration 5 5 SDRAM RTL Test This demonstration presents a memory test function on the bank of SDRAM on the DEI SoC board The memory size of the SDRAM bank is 64MB and all the test codes on this demonstration are written in Verilog HDL B Function Block Diagram Figure 5 8 shows the function block diagram of this demonstration The controller uses 50 MHz as a reference ww
75. nt Document htm By providing the above files the DEI SoC System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damage due to wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration due to improper pin assignments 4 2 General Design Flow This section will introduce the general design flow to build a project for the development board via the DEI SoC System Builder The general design flow is illustrated in Figure 4 1 53 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN Users should launch the DEI SoC System Builder and create a new project according to their design requirements When users complete the settings the DEI SoC System Builder will generate two major files a top level design file v and a Quartus II setting file qsf The top level design file contains top level Verilog HDL wrapper for users to add their own design logic The Quartus setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer must be used to download SOF file to the development board using a JTAG interface Launch SOC Kit System Buil
76. nterface Block Diagram The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block diagram of the GPIO Interface GPIO 28 0 is controlled by GPIOO controller and GPIO 57 29 15 controlled by GPIOI controller GPIO 70 58 and input only GPI 13 0 are controlled by GPIO2 controller GPI 13 0 GPIO Interface Cortex A9 Subsystem Core Generic Interrupt Controller Reset gpio rst n n Interrupt amp gpioO Intr In Manager Control Register Clock I4 Block Manager GPIO 28 0 GPIO 57 29 GPIO 70 58 Slave Interface L4 Peripheral Bus Figure 6 2 Block Diagram of GPIO Interface 88 Terasic DE1 SoC User Manual www terasic com www terasic ANU S RYA GPIO Register Block The behavior of I O pin is controlled by the registers in the register block In this demonstration we only use three 32 bit registers in the GPIO controller The registers are pio swporta dr used to write output data to output I O pin pio swporta ddr used to configure the direction of I O pin pio ext porta used to read input data of I O input pin For LED control we use gpio swporta ddr to configure the LED pin as output pin and drive the pin high or low by writing data to the gpio swporta dr register For the gpio swporta ddr register the first bit least significant bit controls direction of the first IO pin in
77. nual www terasic com www terasic com ANU RYAN Table 3 26 Pin Assignments LEDs Switches and Buttons Signal Name HPS GPIO Register bit Function HPS_KEY 54 GPIO1 25 vo HPS LED GPIO53 GPIO1 24 VO 3 7 2 Gigabit Ethernet The board provides Ethernet support via an external Micrel KSZ9021RN PHY chip and HPS Ethernet MAC function The KSZ9021RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support RGMII MAC interfaces Figure 3 30 shows the connection setup between the Gigabit Ethernet PHY and Cyclone V SoC FPGA The associated pin assignments are listed in Table 3 27 For detailed information on how to use the KSZ9021RN refers to its datasheet and application notes which are available on the manufacturer s website HPS TX DATA 3 0 TXD 3 0 HPS ENET GTX ctx GLK HPS TX EN EN MDI_HPS_N HPS_ENET_RX_DATAI3 01 oj _HPS_ JNO S RYAN RX CLK MDI HPS P HPS ENET RX DV RX_DV HPS ENET MDC HPS LED2 DUAL 1 HPS ENET MDIO DUAL LED2 DUAL 2 HPS ENET INT N INT HPS ENET RESET N RESET_N 25 S KSZ9021RN RJ45 Figure 3 30 Connections between Cyclone V SoC FPGA and Ethernet Table 3 27 Pin Assignments for Ethernet PHY Signal Name FPGA Pin No Description Standard HPS_EN
78. o HPS or Cyclone SoC FPGA through multiplexer as indicated in Figure 3 22 Note that the I2C address W R of the TV decoder U4 is 0 40 0 41 The pin assignments are listed in Table 3 20 Detailed information of the ADV7180 is available on the manufacturer s website or in the DEI_SOC_datasheets Video Decoder folder on the DE2 115 System CD ADV7180 TD DATA T 0 TD VS TD HS J6 me TD RESET Soc RCA JACK I2C_SDAT Y1 Figure 3 22 Connections between FPGA and TV Decoder Table 3 20 TV Decoder Pin Assignments Signal Name FPGA Pin No Description Standard TD DATA 0 PIN D2 TV Decoder Data 0 3 3V TD_DATA 1 1 Decoder Dataf 1 3 3V TD_DATA 2 PIN 2 TV Decoder Data 2 3 3V TD DATA 3 PIN B2 TV Decoder Data 3 3 3V TD DATA 4 PIN D1 TV Decoder Data 4 3 3V TD DATA 5 PIN E1 TV Decoder Data 5 3 3V TD DATA 6 PIN C2 TV Decoder Data 6 3 3V TD DATA 7 PIN B3 TV Decoder Data 7 3 3V TD HS PIN A5 TV Decoder H SYNC 3 3V TD VS PIN A3 TV Decoder V SYNC 3 3V TD CLK27 PIN H15 TV Decoder Clock Input 3 3V TD RESET N PIN F6 TV Decoder Reset 3 3V 2 SCLK PIN J12 or PIN E23 I2C Clock 3 3V 2 SDAT PIN K12 or PIN C24 I2C Data 3 3V 35 Terasic DE1 SoC User Manual www terasic com www terasic JA DTE RYA 3 6 8 IR Receiver The board provides an infrared remote control receiver module model 538 whose datasheet is offe
79. of all of the external clocks going to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter to FPGA The four distributing 50MHz clock signals are connected to the FPGA that are used for clocking the user logic One distributing 25MHz clock signal is connected to HPS clock inputs the other distributing 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver Two distributing 24MHz clock signals are connected to clock inputs of USB Host OTG PHY and USB Hub controller respectively The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 3 8 20 Terasic DE1 SoC User Manual www terasic com www terasic com 515350 25MHz IN DTE RYAN CLOCK_50 50MHz 59 CLOCK2_50 50MHz CLOCK4_50 50MHz CLOCK3 50 50MHz S HPS CLK 25 25MHz 234 HPS_CLK2 Gigabit Ethernet ENET CLK 25 25 2 Transceiver USB Host PHY USBPHY_CLK_24 24MHz 2 port Hub USBHUB_CLK_24 24MHz Controller Figure 3 11 Block diagram of the clock distribution Table 3 8 Pin Assignments for Clock Inputs PIN 50 MHz clock input 3 PIN_AA16 50 MHz clock input 3 PIN 50 MHz clock input 3 PIN_Y26 PIN Kia 50 MHz clock input PIN 025 25 MHz clock input 3 3 3V 3 6 Interface on FPGA This section describes the interfaces to the FPGA Users can control or monitor the different interfaces with
80. olume levels provided by the device 64 Terasic DE1 SoC User Manual www terasic com www terasic Line In lt gt Push Button Figure 5 4 Block diagram of the Karaoke Machine demonstration B Demonstration Setup File Locations and Instructions e Project directory DEI SOC i2sound e Bit stream used DEI SOC 12sound sof e Connect a microphone to the microphone in port pink color on the DEI SOC board e Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DEI SOC board e Connect headset speaker to the line out port green color on the DEI SOC board the bit stream into the FPGA by execute the batch file DEI SOC i2sound under the DE SOC 1i2soundMemo batch folder e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels to 9 Figure 5 5 illustrates the setup for this demonstration 65 Terasic DE1 SoC User Manual www terasic com www terasic co m MP3 Any Audio Output TT p P mel a T e M n nnam AAA IOMA ne bowl beet bret bl bet bel lool feel li Clock Data Frequency Generator Figure 5 5 Setup for the Karaoke Machine 5 4 SDRAM Test by Nios Many applic
81. onstration will be described in below B IR TX Controller User can input 8 bit address and 8 bits command into IR TX Controller IR TX Controller will encode the the address and command first and send it out according to NEC IR transmission protocol through IR emitter LED Note that the input clock of the Controller should be SOMHz The NEC IR transmission protocol uses pulse distance encoding of the message bits Each pulse burst 15 562 5us in length at a carrier frequency of 38kHz 26 3us As shown in Figure 5 13 Logical bits are transmitted as follows e Logical 0 a 562 5us pulse burst followed by a 562 5us space with a total transmit time of 1 125ms e Logical 1 a 562 5us pulse burst followed by 1 6875ms space with a total transmit time TI Terasic DE1 SoC User Manual www terasic com www terasic com JN OTS n AN of 2 25ms Logical 1 Logical 0 P 562 25us 562 25us ld 562 25us 2 25ms 1 125ms Figure 5 13 Logical 1 and Logical 0 Figure 5 14 shows the frame of the protocol Protocol will send a lead code first a 9ms leading pulse burst followed by 4 5msThe second inversed data is sent to verify the accuracy of the information received At last a final 562 5us pulse burst to signify the end of message transmission Because every time it 1s sent inversed data the overall transmission time 15 constant 000000001 1 1 4 1 1 1 1 O1 4 0 1 01 O 1 00 1 0 1 0
82. operate system support mult thread software The software for this system creates two threads one for controlling the LED and the other for controlling the HEX We can use the system call pthread create to complete the job The function is called in the main function and a sub thread is created The program running in the sub thread 15 to control the led flashing in a loop And the main thread in the main function 15 to control the digital shown on the HEX changing in a loop The LED and HEX s state changing at the same time when the FPGA is configured and the software is running on HPS Demonstration Source Code Build tool Altera SoC EDS V13 0 e Project directory Demonstration SoC_FPGA HPS_LED_HEX e Quick file directory Demonstration SoC_FPGA HPS_LED_HEX quickfile Batch File Demonstration SoC_FPGA HPS_LED_HEX quickfile sof_dwonload test bat FPGA Configure File HPS LED HEX sof e Binary file HPS LED HEX e Build app command make make clean to remove all temporal files e Execute app command 5 LED HEX Demonstration Setup e sure Quartus and Nios II are installed on your PC e Connect the USB blaster cable to the USB blaster connector 713 on the DEI SOC board and host PC install USB Blaster driver II if necessary e Connect the USB cable to the USB to UART connector 74 on the DEI SOC board and host PC e Make sure the executable 5 LED HEX is copied into the SD card under th
83. ormation ae dod At MET NT d Cyclone 4 Soc dH 2 ES H E 24 8025 RU2Z6 CHE 29 eim n e Figure 5 21 ADC Reading hardware setup 84 Terasic DE1 SoC User Manual www terasic com www terasic com Chapter 6 Examples for HPS SoC This chapter provides a number of C code examples based on the Altera SoC Linux built by Yocto Project These examples provide demonstrations of the major features which connected to HPS interface on the board such as users LED KEY I2C interfaced G sensor and 2 MUX All of the associated files can be found in the Demonstrations SOC folder in the DEI SoC System CD B Installation of the Demonstrations To install the demonstrations on your computer Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v13 0 is required for users to compile the c code project 6 1 Hello Program This demonstration presents how to develop your first HPS program by using Altera SoC EDS tool For operation details please refer to First HPS pdf in the system CD Here are the major procedures to develop and build HPS project Make sure Altera SoC EDS is installed on your PC Create program c h files with a generic text editor Create a Makefile with a generic text editor Build your project under Altera SoC EDS B Program File
84. ox a Factory default 110 Terasic DE1 SoC User Manual www terasic com www terasic com ANU S RA SFL image will be load See Figure 8 8 Tools Window Help 5 Enable real time ISP to allow background programming for MAX and MAX devices File Device Checksum Usercode Proaram Verify Blank Examine Start Configure Check Factory default enhanced SCSXFC6D6ES 00 64585 00 64585 E E D autput 256 97158 C iy Auto Detect lt none gt SOCVHPS 00000000 lt none gt ai X Delete Change File lg Save File pu Down Figure 8 8 Erasing setting in Quartus programmer window Click Start to erase the serial configuration device 111 1 5 DE1 SoC User Manual www terasic com www terasic com Chapter 9 Appendix 9 1 Revision History Change Log Initial Version Preliminary Add CH5 and CH6 Modify CH3 Add CH6 HPS Copyright 2013 Terasic Technologies All rights reserved 112 DE1 SoC User Manual www terasic com www terasic com Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Terasic P0159
85. pins of the Cyclone V SoC FPGA and also provides DC 5V VCC5 DC 3 3V VCC3P3 and two GND pins The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 3 13 Table 3 13 Power Supply of the Expansion Header Supplied Voltage Max Current Limit 5V 1A 3 3V 1 5A Each pin on the expansion headers 15 connected to two diodes and a resistor that provides protection against high and low voltages Figure 3 17 shows the protection circuitry for only one of the pin on the header but this circuitry is included for all 72 data pins Table 3 14 shows all the pin assignments of the GPIO connector VCC3P3 ANU S RYAN Cyclone V Soc GPIO_0 35 0 E EE REE MX 59 999909090990909909999909909 m Figure 3 17 Connections between the GPIO connector and Cyclone V SoC FPGA Table 5 14 Pin Assignments for Expansion Headers Signal Name FPGA Pin No Description Standard GPIO O 0 PIN AC18 GPIO Connection 0101 3 3V GPIO O 1 PIN Y17 GPIO Connection 0 1 3 3V _ GPIO_0 2 PIN_AD17 GPIO Connection 0 2 3 8V GPIO_0 3 Y18 GPIO Connection 0 3 3 3V 27 Terasic DE1 SoC User Manual www terasic com www terasic com GPIO_0 4 0 5 GPIO 0 6 GPIO 0 7 0 8 GPIO 0 9 GPIO 0 10 GPIO 0 11 GPIO 0 12 GPIO 0 13 GPIO 0 14 GPIO 0 15 GPIO 0 16 GPIO 0
86. plemented in the FPGA As Figure 5 17 show it includes Code Detector State Machine and Shift Register First the IR receiver demodulates the signal inputs to Code Detector block The Code Detector block will check the Lead Code and feedback the examination result to State Machine block The State Machine block will change the state from IDLE to GUIDANCE once the Lead code 15 detected Once the Code Detector has detected the Custom Code status the current state will change from GUIDANCE to DATAREAD state At this state the Code Detector will save the receiving data and output to Shift Register then displays it on 7 segment displays Figure 5 18 shows the state shift diagram of State Machine block Note that the input clock should be 50MHz IR Signal Cod State Machine Figure 5 17 The IR Receiver controller 80 Terasic DE1 SoC User Manual www terasic com End Code Lead Code Custom Code Figure 5 18 State shift diagram of State Machine Demonstration Source Code e Project directory DEI SoC IR e Bitstream used DEI SOC IR sof Demonstration Batch File Demo Batch File Folder 5 IR demo batch The demo batch file includes the following files e Batch File DEI SoC IR bat FPGA Configure File DEI SOC IR sof Demonstration Setup File Locations and Instructions the bit stream into FPGA by executing DEI 5 IR demo_batch DEI 5 IR bat Press KEY 0 to enable the continuously pattern s
87. r LED LIC 2x7 expansion header 2 2 Block Diagram of the DE1 SoC Board Figure 2 3 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the Cyclone V SoC FPGA device Thus the user can configure the FPGA to implement any system design JTAG 40 pin GPIO 40 pin GPIO VGA 8 bit x12 5CSEMA5F31C6N x6 FPGA HPS 12C 2 2 From HPS Switch Control x1 Gis 09 FPGA x6 x1 x1 x1 x1 9 x10 x42 x10 HPS HPS WARM User FLED RST User RST Button LED x10 Push Button x4 BBRRRRRRAA Slide Switch x BGBBBHH 7 Segment Display x6 Figure 2 3 Board Block Diagram 7 Terasic DE1 SoC User Manual www terasic co m Micro x6 SD Card mu Ethernet m nm USB Host Normal Type A DOR3 SDRAM x16 64 MB x72 x3 di USB Mini B Accelerometer x3 2x7 LTC Header x7 www terasic com ANU RYAN Following is more detailed information about the blocks in Figure 2 3 FPGA Device Cyclone V SoC 5 Device e Dual core ARM Cortex A9 HPS e 85K Programmable Logic Elements e 4 450 Kbits embedded memory e 6 Fractional PLLs 2 Hard Memory Controllers Configuration and Debug Quad Serial Configuration device EPCQ256 on FPGA On Board USB
88. r Manual www terasic com www terasic com File Edit View Processing Tools Window Help Search altera com kr Enable real time ISP to allow background programming for MAX and MAX devices Add IPS File Change IPS File Delete IPS File Add PR Programming File Change Programming File Delete PR Programming File Attach Flash Device Change Flash Device Delete Flash Device Change Device Down Figure 3 5 FPGA JTAG Programming Steps 4 Select sof file for FPGA as Figure 3 6 que Select Mew Programming Fi DE1 SoC Default sof Files of type Programming Files sof pof jam jbc ekp jic Figure 3 6 FPGA JTAG Programming Steps 5 16 Terasic DE1 SoC User Manual www terasic com ANU S RA e Click Program Configure check box and then click Start button to download sof file into FPGA as Figure 3 7 xp Programmer Chain2 cdf File Edit View Processing Tools Window 5 Hardware Setup DE 5oC USB 1 Mode Enable real time ISP to allow background programming for MAX II and MAX V devices Usercode Program Verify Blank Configure Check 03888274 03888274 00000000 gt un 13 Figure 3 7 FPGA JTAG Programming Steps 6 Configuring the FPGA AS Mode from EPCQ256 e The board contains a quad serial configurat
89. rangement of the 2x5 header In this demonstration this header is the input source of ADC convertor Users can connect a trimmer to the specified ADC channel ADC_INO ADC_IN7 that provides voltage to the ADC convert Then FPGA will read the associated register in the convertor via serial interface and translates it to voltage value displayed on the NIOS II console ADC_INO ADC_IN2 ADC_IN4 ADC_IN6 VCC5 ADC_IN1 ADC_IN3 ADC_IN5 ADC_IN7 2x5 Box Header Figure 5 20 ADC Pin distribution of the 2x5 Header System Requirements The following items are required for the ADC Reading demonstration DEI SoC board x1 o Trimmer Potentiometer x1 o Wire Strip x3 B Demonstration File Locations e Hardware Project directory DEI SoC_ADC Bit stream used DEI SoC ADC sof Software Project directory DEI SoC software e Demo batch file DEI SoC ADCMemo batch DEI 5 ADC bat B Demonstration Setup and Instructions e Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure 5 21 to read from as well as the 5V and GND signals Note the setup shown above is connected ADC channel 0 83 Terasic DE1 SoC User Manual www terasic com www terasic com JA DTE RYAN Execute the demo batch file DEI SoC ADC bat to load bit stream and software execution file in FPGA The NIOS II console will display the voltage of the specified channel voltage result inf
90. red in the Datasheets IR Receiver and Emitter folder on DE1 SoC System CD The accompanied remote controller with an encoding chip of uPD6121G is very suitable of generating expected infrared signals Figure 3 23 shows the related schematic of the IR receiver Table 3 21 shows the IR receiver interface pin assignments VCC3P3 IRDA_RXD JNO S RA 7 GND CHASSIS Figure 3 23 Connection between FPGA and IR Receiver Table 3 21 Pin Assignments for IR Signal Name FPGA Pin No Description vO Standard IRDA_RXD AA30 IR Receiver 3 3V 3 6 9 IR Emitter LED The board provides an IR Emitter LED for IR communication which 15 widely used for operating the television device wirelessly from a short line of sight distance Match this IR Emitter LED with an IR receiver will allow the board to communicate with similarly equipped system Figure 3 24 shows the related schematic of the IR emitter LED Table 3 22 shows the IR emitter interface pin assignments 36 Terasic DE1 SoC User Manual www terasic com www terasic com VCC3P3 IR Emitter LED IRDA_TXD N ANU B4AN HE8050G amp O Figure 3 24 Connection between FPGA and IR Emitter LED Table 3 22 Pin Assignments for IR Signal Name FPGA Pin No Description IRDA_TXD AB30 3 6 10 SDRAM Memory on FPGA The board features 64MB of SDRAM implemented using a 64MB 32Mx16 SDRAM device
91. ription PIN_AB12 Slide Switch 0 PIN AC12 Slide Switch 1 PIN AF9 Slide Switch 2 PIN AF10 Slide Switch 3 PIN AD11 Slide Switch 4 PIN AD12 Slide Switch 5 PIN AE11 Slide Switch 6 PIN AC9 Slide Switch 7 PIN AD10 Slide Switch 8 PIN AE12 Slide Switch 9 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V Table 3 10 Pin Assignments for Push buttons Standard FPGA Pin No Description 14 Push button 0 PIN 15 Push button 1 PIN W15 Push button 2 PIN Y16 Push button 3 24 3 3V 3 3V 3 3V 3 3V www terasic com ANU RYAN Signal LEDR 0 LEDR 1 LEDR 2 LEDR 3 LEDR 4 LEDR 5 LEDR 6 LEDR 7 LEDR 8 LEDR 9 FPGA Pin No PIN V16 PIN W16 PIN V17 PIN V18 PIN W17 PIN W19 PIN Y19 PIN W20 PIN W21 PIN Y21 Description LED 0 LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8 LED 9 Table 3 11 Pin Assignments for LEDs O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 6 2 Using the 7 segment Displays The DEI SoC board has six 7 segment displays These displays are arranged into three pairs behaving the intent of displaying numbers of various sizes As indicated in the schematic in Figure 3 16 the seven segments common anode are connected to pins on Cyclone V SoC FPGA Applying a low logic level to a segment will light it up and applying a high logic level turns it off Each segment a display 15 id
92. roller clock frequency in detail 3 1 1 FPGA Configuration Mode Setting Table 3 1 gives the MSEL pins setting for each configuration scheme of Cyclone V SoC devices FPGA default works in ASx4 Fast mode with MSEL 4 0 10010 Table 3 1 MSEL pin Settings for each Scheme of Cyclone V Device Configuration Design Security Delay Compression Feature Valid MSEL 4 0 Scheme Feature Fast 77 10100 Disabled Disabled FPPx8 i Disabled Enabled Fast poor Standard moon Enabled Disabled fono Standard M010 Fast 00000 Disabl Enabl pisaba Fast 00001 Disabled Disabled pisaba Fast 00010 Enabled Enabled ooo 10 DE1 SoC User Manual www terasic com www terasic com Fast 10000 PS Enabled Disabled Disabled i Standard 10001 Fast 10010 AS X1 and X4 Enabled Disabled Enabled Standard 10011 Table 3 2 shows the switch controls and descriptions for MSEL Table 3 2 SW10 FPGA Configuration Mode Switch Board Reference Signal Name Description Default SW10 1 MSELO On SW10 2 MSEL1 Sets the Cyclone MSEL 4 0 pins SW10 3 MSEL2 Use these pins to set the configuration On SW10 4 MSEL3 scheme and POR delay On SW10 5 MSEL4 Off SW10 6 N A N A N A 3 1 2 HPS BOOTSEL and CLKSEL Setting The processor in the HPS can be boot from many sources such as the SD card QSPI Flash or FPGA Selecting the boot source for the HPS can be set using the BOOTSEL signal Figure 3
93. ser Manual www terasic com www terasic com Chapter 5 Examples For FPGA This chapter provides a number of examples of advanced circuits implemented by RTL or Qsys on the DEI SoC board These circuits provide demonstrations of the major features which connected to FPGA interface on the board such as audio SDRAM and IR receiver All of the associated files can be found in the Demonstrations FPGA folder on the DEI SoC System CD B Installing the Demonstrations To install the demonstrations on your computer Copy the directory Demonstrations into a local directory of your choice It 15 important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work Note Quartus II v13 or later is required for all DE1 SoC demonstrations to support Cyclone V SoC device 5 1 DE1 SoC Factory Configuration The DEI SoC board is shipped from the factory with a default configuration bit stream that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DEI SoC Default e Bit stream used DEI 5 Default sof or DEI SoC Default jic e Power on the DEI SoC board with the USB cable connected to the USB Blaster port If necessary that 1s 1f the default factory configuration of the DEI SoC board 15 not currently stored 1n EPCQ
94. source Slide Switches 0 DOWN Position 1 UP Position swo Audiois from MIC Audio is from LINE IN 63 Terasic DE1 SoC User Manual www terasic com www terasic co m ANU S RYA Table 5 2 Slide switch setting for sample rate switching for audio recorder and player SW5 SW4 SW3 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K Note 7 Execute SoC Audio demo_batch DE7 SoC Audio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely 5 3 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DEI SOC board to create a Karaoke Machine application The WM 8731 CODEC is configured in the master mode with which the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 4 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via 2 bus cycling within ten predefined gain values v
95. t to the edge of the board it provides a low logic level to the FPGA and when the switch is in the UP position it provides a high logic level PN OTE Cyclone V SoC fasal Aniol AC9 AD11 TIT AC12 AB 12 Logic 1 1111117 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 Logic 0 Figure 3 14 Connections between the slide switches and Cyclone V SoC FPGA There are also ten user controllable LEDs connected to FPGA on the board Each LED is driven directly by a pin on the Cyclone V SoC FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 15 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 9 Table 3 10 and Table 3 11 list the pin assignments of these user interfaces 23 Terasic DE1 SoC User Manual www terasic com www terasic com Signal Name SW 0 SW 1 SW 2 SW 3 SW 4 SW 5 SW 6 SW 7 SW 8 SW 9 Signal Name KEY 0 KEY 1 KEY 2 KEY 3 Terasic DE1 SoC User Manual w terasic com ww 16 W16 V17 PIN_V18 RYAN en wir W19 W20 W21 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED LED8 LED9 21 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED LED8 LEDO Figure 3 15 Connections between the LEDs and Cyclone V SoC FPGA Table 3 9 Pin Assignments for Slide Switches VO Standard FPGA Pin No Desc
96. tch file folder DEI SoC SDRAM RTL Test demo batch e Press KEYO on the DEI SoC board to start the verification process When KEYO is pressed the LEDs LEDR 2 0 should turn on At the instant of releasing KEYO LEDR1 LEDR2 should start blinking After approximately 8 seconds LEDRI should stop blinking and stay on to indicate that the SDRAM has passed the test respectively Table 5 3 lists the LED indicators e If LEDR2 is not blinking it means clock source is not working If LEDRI fail to remain on after 8 seconds the corresponding SDRAM test has failed e Press KEYO again to regenerate the test control signals for a repeat test Table 5 3 LED Indicators Table 5 ANAME Description LEDRO Reset LEDR1 If light SDRAM test pass LEDR2 Blinks 5 6 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and TV decoder on the DEI SoC board Figure 5 9 shows the block diagram of the design There two major blocks in the circuit called I2C_AV_Config and The TV_to_VGA block consists of the ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCbCr to RGB and VGA Controller The figure also shows the TV Decoder ADV7180 and the VGA DAC ADV7123 chips used As soon as the bit stream is downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the I2C_AV_Config block whi
97. the associated GPIO controller and the second bit controls the direction of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the I O direction is output and the value 0 in the register bit indicates the I O direction is input For the gpio swporta dr register the first bit controls the output value of first I O pin in the associated GPIO controller and the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value 15 high and the value 0 indicates the output value is low The status of KEY can be queried by reading the value of gpio ext porta register The first bit represents the input status of first IO pin in the associated GPIO controller and the second bit represents the input status of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the input state is high and the value 0 indicates the input state 15 low B GPIO Register Address Mapping The registers of HPS peripherals are mapped to HPS base address space 000000 with 64K B size Registers of GPIOI controller are mapped to the base address OXFF208000 with 4KB size and registers of GPIO2 controller are mapped to the base address OxXFF20A000 with 4KB size as shown in Figure 6 3 89 Terasic DE1 SoC User Manual www terasic com www terasic
98. the gsensor polling The demo program will show the X Y and Z values in the Putty as shown in Figure 6 9 Press CTRL C to terminate the program Figure 6 9 Terminal output of the G sensor Demonstration 6 412C MUX Test This demonstration shows how to switch the I2C multiplexer so that HPS can access the I2C bus originally owned by FPGA B Function Block Diagram Figure 6 11 shows the function block diagram of this demonstration The I2C bus from both FPGA and HPS are connected to an 2 multiplexer and I2C multiplexer is controlled by HPS I2C CONTROL which connected to GPIOI controller in HPS The HPS is connected to the I2C0 controller in HPS Gsensor is also connected to 2 controller See Figure 6 10 FPGA SoC DDR3 ARM Program FPGA 12 5 Linux User Mode 2 Mux HPS 2 Linux Kernel Mode Figure 6 11 Block Diagram of the I2C MUX Test Demonstration HPS I2C CONTROL TV Audi Decoder 96 Terasic DE1 SoC User Manual www terasic com www ter asic com ANU S RYA B HPS CONTROL Control HPS 2 CONTROL is connected to HPS_GPIO48 bit 19 of GPIOI controller HPS will own I2C bus and then can access Audio CODEC and TV Decoder when the HPS I2C CONTROL signal 15 set to high In this demo code the following mask is defined to control HPS 2 CONTROL direction and their output value HPS I2C CONTR
99. us II suite and as part of the free Altera Quartus II Programmer The HPS Flash Programmer sends file contents over an Altera download cable such as the USB Blaster II to the HPS and instructs the HPS to write the data to the flash memory 47 Terasic DE1 SoC User Manual www terasic com www terasic com JNO RYA Soc HPS HPS FLASH DATA 3 HPS FLASH DATA 2 HPS FLASH DATA 1 HPS FLASH DATA 0 HPS FLASH DCLK HPS FLASH NCSO U13 HOLD n DQ3 W n Vpp DQ2 DQ1 FLASH Figure 3 32 Connections Between Cyclone V SoC FPGA and QSPI Flash Table 3 31 below summarizes the pins on the flash device Signal names are from the device datasheet and directions are relative to the Cyclone V SoC FPGA Signal Name HPS FLASH DATA O HPS FLASH DATA 1 HPS FLASH DATA 2 HPS FLASH DATA 3 HPS FLASH DCLK HPS FLASH NCSO 3 7 6 Micro SD FPGA Pin No PIN C20 PIN H18 PIN A19 PIN E19 PIN D19 PIN A18 Table 3 31 Flash Interface Description Standard HPS FLASH Data 0 3 3V HPS FLASH Data 1 3 3V HPS FLASH Data 2 3 3V HPS FLASH Data 3 3 3V HPS FLASH Data Clock 3 3V HPS FLASH Chip Enable 3 3V The board supports Micro SD card interface using x4 data lines And it may contain secondary boot code for HPS Figure 3 33 shows the related signals Finally Table 3 32 lists all the associated pins for interfacing HPS respectively Terasic DE1 SoC User Manual www terasic 48
100. user logic on the FPGA DE1 SoC User Manual www terasic com 21 www terasic com ANU RYAN 3 6 1 User Push buttons Switches and LEDs FPGA The board provides four push button switches connected to FPGA as shown in Figure 3 12 Connections between the push button and Cyclone V SoC FPGA Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 3 13 The four outputs called KEYO KEY1 KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone V SoC FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clock or reset inputs in a circuit VCC3P3 KEYO w15 Y16 KEY2 74HC245 Figure 3 12 Connections between the push button and Cyclone V SoC FPGA hbutton depressed pum released Before o UUU Schmitt Trigger Debounced 6 gt Figure 3 13 Switch debouncing 22 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN There are ten slide switches connected to FPGA on the board See Figure 3 14 These switches not debounced and are assumed for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone V SoC FPGA When the switch is in the DOWN position closes
101. w terasic com clock generates one 100 MHz clock as memory clock 69 Terasic DE1 SoC User Manual www terasic com Memory gt Conrtoller Qo 2 RW_Test A Test 9 lt E Contro CEYO Process gt LED Figure 5 8 Block Diagram of the SDRAM Demonstration RW_test modules read and write the entire memory space of the SDRAM through the interface of the controller In this project the read write test module will first write the entire memory and then compare the read back data with the regenerated data the same sequence as the write data KEYO will trigger test control signals for the SDRAM and the LEDs will indicate the test results according to Table 5 3 l CLOCK_50 Design Tools e Quartus 13 0 B Demonstration Source Code Project directory DEI SoC SDRAM RTL Test e Bit stream used DEI SoC SDRAM RTL Test sof B Demonstration Batch File Demo Batch File Folder DE SoC SDRAM RTL TestNdemo batch The demo batch file includes following files Batch File DEI SoC SDRAM RTL Test bat FPGA Configure File DEI SoC SDRAM RTL Test sof B Demonstration Setup e sure Quartus is installed on your PC 70 Terasic DE1 SoC User Manual www terasic com ANU S RYA e Connect the USB cable to the USB Blaster connector on the DE1_SoC board and host e Power on the DEI SoC board e Execute the demo batch file DEI SoC SDRAM RTL Test bat under the ba
102. zero and eight data bits with LSB first one parity check bit odd check and one stop bit always one PS 2 controller samples the data line at the falling edge of the PS 2 clock signal This could easily be implemented using a shift register of 33 bits but be cautious with the clock domain crossing problem B Data transmit from the controller to device Whenever the controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmit process or to indicate the start of a new transmit process which usually be called as inhibit state After that it pulls low the data line then release the clock line and this 1s called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 10ms time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state 74 Terasic DE1 SoC User Manual www terasic com www terasic com ANU RYAN change the data line the next clock cycle If there s no change on the data line for one clock cycle the d

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